From 32a3dcad128fb90d8c6563e17476a75582f26bd8 Mon Sep 17 00:00:00 2001 From: jake Date: Sat, 8 Mar 2025 17:09:58 -0800 Subject: [PATCH] removed uneeded files. --- src/attic/CMakeLists.txt | 7 - src/attic/hardware_header_all_combined.h | 12914 ---------------- src/attic/temp_transition_helper.c | 226 - src/extralibs/.clang-format | 5 + src/extralibs/ch32v003_GPIO_branchless.h | 504 +- src/extralibs/ch32v003_SPI.h | 400 +- src/extralibs/ch32v003_touch.h | 276 +- src/extralibs/ch32v307gigabit.h | 796 +- src/extralibs/font_8x8.h | 5118 +++--- src/extralibs/hsusb_v30x.c | 1036 +- src/extralibs/hsusb_v30x.h | 75 +- src/extralibs/lib_rand.h | 172 +- src/extralibs/ssd1306.h | 763 +- src/extralibs/ssd1306_i2c.h | 458 +- src/extralibs/ssd1306_i2c_bitbang.h | 170 +- src/extralibs/ssd1306_spi.h | 107 +- src/extralibs/usb_defines.h | 3038 ++-- src/extralibs/ws2812b_dma_spi_led_driver.h | 365 +- src/extralibs/ws2812b_simple.h | 83 +- src/misc/attic/.clang-format | 5 + src/misc/attic/temp_transition_helper.c | 398 +- .../drivers_for_WCH-LinkE/R0-1v3/README.txt | 11 - .../R0-1v3/WCH-Link_(Interface_0).cat | Bin 5072 -> 0 bytes .../R0-1v3/WCH-Link_(Interface_0).inf | Bin 4858 -> 0 bytes src/misc/tests/Makefile | 23 - 25 files changed, 6911 insertions(+), 20039 deletions(-) delete mode 100644 src/attic/CMakeLists.txt delete mode 100644 src/attic/hardware_header_all_combined.h delete mode 100644 src/attic/temp_transition_helper.c create mode 100644 src/extralibs/.clang-format create mode 100644 src/misc/attic/.clang-format delete mode 100644 src/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt delete mode 100644 src/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).cat delete mode 100644 src/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).inf delete mode 100644 src/misc/tests/Makefile diff --git a/src/attic/CMakeLists.txt b/src/attic/CMakeLists.txt deleted file mode 100644 index c0be186..0000000 --- a/src/attic/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -add_library(attic STATIC - temp_transition_helper.c -) - -target_include_directories(attic PUBLIC - ${CMAKE_CURRENT_LIST_DIR} -) diff --git a/src/attic/hardware_header_all_combined.h b/src/attic/hardware_header_all_combined.h deleted file mode 100644 index 45c50e3..0000000 --- a/src/attic/hardware_header_all_combined.h +++ /dev/null @@ -1,12914 +0,0 @@ -#ifndef TODO_HARDWARE_H -#define TODO_HARDWARE_H - -#include "ch32fun.h" - -#ifndef __ASSEMBLER__ // Things before this can be used in assembly. - -#ifdef __cplusplus -extern "C" { -#endif - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 3 Exception Interrupt */ -#if defined(CH32V20x) || defined(CH32V30x) - Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ - Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ - Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ -#endif - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - -#if defined(CH32V003) || defined(CH32X03x) - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - FLASH_IRQn = 18, /* FLASH global Interrupt */ - RCC_IRQn = 19, /* RCC global Interrupt */ - EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ - AWU_IRQn = 21, /* AWU global Interrupt */ - DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 29, /* ADC global Interrupt */ - I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ - USART1_IRQn = 32, /* USART1 global Interrupt */ - SPI1_IRQn = 33, /* SPI1 global Interrupt */ - TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 38, /* TIM2 global Interrupt */ -#if defined(CH32X03x) - USART2_IRQn = 39, /* UART2 Interrupt */ - EXTI15_8_IRQn = 40, /* External Line[8:15] Interrupt */ - EXTI25_16_IRQn = 41, /* External Line[25:16] Interrupt */ - USART3_IRQn = 42, /* UART2 Interrupt */ - USART4_IRQn = 43, /* UART2 Interrupt */ - DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ - USBFS_IRQn = 45, /* USB Full-Speed Interrupt */ - USBFS_WakeUp_IRQn = 46, /* USB Full-Speed Wake-Up Interrupt */ - PIOC_IRQn = 47, /* Programmable IO Controller Interrupt */ - OPA_IRQn = 48, /* Op Amp Interrupt */ - USBPD_IRQn = 49, /* USB Power Delivery Interrupt */ - USBPD_WKUP_IRQn = 50, /* USB Power Delivery Wake-Up Interrupt */ - TIM2_CC_IRQn = 51, /* Timer 2 Compare Global Interrupt */ - TIM2_TRG_IRQn = 52, /* Timer 2 Trigger Global Interrupt */ - TIM2_BRK_IRQn = 53, /* Timer 2 Brk Global Interrupt */ - TIM3_IRQn = 54, /* Timer 3 Global Interrupt */ -#endif -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 18, /* Tamper Interrupt */ - RTC_IRQn = 19, /* RTC global Interrupt */ - FLASH_IRQn = 20, /* FLASH global Interrupt */ - RCC_IRQn = 21, /* RCC global Interrupt */ - EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ - EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ - EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ - EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ - EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ -#if !defined(CH32V10x) // CH32V20x/30x only - USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ -#endif - EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 44, /* TIM2 global Interrupt */ - TIM3_IRQn = 45, /* TIM3 global Interrupt */ - TIM4_IRQn = 46, /* TIM4 global Interrupt */ - I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ - I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ - I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ - SPI1_IRQn = 51, /* SPI1 global Interrupt */ - SPI2_IRQn = 52, /* SPI2 global Interrupt */ - USART1_IRQn = 53, /* USART1 global Interrupt */ - USART2_IRQn = 54, /* USART2 global Interrupt */ - USART3_IRQn = 55, /* USART3 global Interrupt */ - EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ -#endif -#if defined(CH32V10x) || defined(CH32V20x) - USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ - USBHD_IRQn = 59, /* USBHD global Interrupt */ -#endif -#if defined(CH32V20x) - USBHDWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */ - -#ifdef CH32V20x_D6 - UART4_IRQn = 61, /* UART4 global Interrupt */ - DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ - -#elif defined(CH32V20x_D8) - ETH_IRQn = 61, /* ETH global Interrupt */ - ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ - TIM5_IRQn = 65, /* TIM5 global Interrupt */ - UART4_IRQn = 66, /* UART4 global Interrupt */ - DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ - OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ - OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ - -#elif defined(CH32V20x_D8W) - ETH_IRQn = 61, /* ETH global Interrupt */ - ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ - BB_IRQn = 63, /* BLE BB global Interrupt */ - LLE_IRQn = 64, /* BLE LLE global Interrupt */ - TIM5_IRQn = 65, /* TIM5 global Interrupt */ - UART4_IRQn = 66, /* UART4 global Interrupt */ - DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ - OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ - OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ -#endif - -#elif defined(CH32V30x) - -#ifdef CH32V30x_D8 - TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ -#elif defined (CH32V30x_D8C) - USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ -#endif - TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ - RNG_IRQn = 63, /* RNG global Interrupt */ - FSMC_IRQn = 64, /* FSMC global Interrupt */ - SDIO_IRQn = 65, /* SDIO global Interrupt */ - TIM5_IRQn = 66, /* TIM5 global Interrupt */ - SPI3_IRQn = 67, /* SPI3 global Interrupt */ - UART4_IRQn = 68, /* UART4 global Interrupt */ - UART5_IRQn = 69, /* UART5 global Interrupt */ -#endif - -#if defined(CH32V30x) - TIM6_IRQn = 70, /* TIM6 global Interrupt */ - TIM7_IRQn = 71, /* TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 77, /* ETH global Interrupt */ - OTG_FS_IRQn = 83, /* OTGFS global Interrupt NOTE: THIS APPEAR TO BE INCORRECT */ - USBHSWakeup_IRQn = 84, /* USBHS Wakeup Interrupt */ - USBHS_IRQn = 85, /* USBHS global Interrupt */ - DVP_IRQn = 86, /* DVP global Interrupt */ - UART6_IRQn = 87, /* UART6 global Interrupt */ - UART7_IRQn = 88, /* UART7 global Interrupt */ - UART8_IRQn = 89, /* UART8 global Interrupt */ - TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ - TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ - TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ - TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ - TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ - TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ - TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ - TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ - DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ - DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ - DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ - DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ - DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ - DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ -#endif - -} IRQn_Type; - - -#if defined (CH32V003) - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SR; - __IO uint32_t CNT; - uint32_t RESERVED0; - __IO uint32_t CMP; - uint32_t RESERVED1; -} SysTick_Type; - -#elif defined(CH32V20x) || defined(CH32V30x) - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SR; - __IO uint64_t CNT; - __IO uint64_t CMP; -} SysTick_Type; - -#elif defined(CH32X03x) - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SR; - __IO uint32_t CNTL; - __IO uint32_t CNTH; - __IO uint32_t CMPL; - __IO uint32_t CMPH; -} SysTick_Type; - -#elif defined(CH32V10x) - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CNTL; - __IO uint32_t CNTH; - __IO uint32_t CMPL; - __IO uint32_t CMPH; -} SysTick_Type; - -#endif - -#endif /* __ASSEMBLER__*/ - -#define HardFault_IRQn EXC_IRQn - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) - #define ADC1_2_IRQn ADC_IRQn -#endif - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -#ifndef __ASSEMBLER__ -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; -#if defined(CH32V20x) - __IO uint32_t DLYR; -#elif defined(CH32X03x) - __IO uint32_t CTLR3; - __IO uint32_t WDTR1; - __IO uint32_t WDTR2; - __IO uint32_t WDTR3; -#endif -} ADC_TypeDef; - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -/* Backup Registers */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DATAR1; - uint16_t RESERVED1; - __IO uint16_t DATAR2; - uint16_t RESERVED2; - __IO uint16_t DATAR3; - uint16_t RESERVED3; - __IO uint16_t DATAR4; - uint16_t RESERVED4; - __IO uint16_t DATAR5; - uint16_t RESERVED5; - __IO uint16_t DATAR6; - uint16_t RESERVED6; - __IO uint16_t DATAR7; - uint16_t RESERVED7; - __IO uint16_t DATAR8; - uint16_t RESERVED8; - __IO uint16_t DATAR9; - uint16_t RESERVED9; - __IO uint16_t DATAR10; - uint16_t RESERVED10; - __IO uint16_t OCTLR; - uint16_t RESERVED11; - __IO uint16_t TPCTLR; - uint16_t RESERVED12; - __IO uint16_t TPCSR; - uint16_t RESERVED13[5]; - __IO uint16_t DATAR11; - uint16_t RESERVED14; - __IO uint16_t DATAR12; - uint16_t RESERVED15; - __IO uint16_t DATAR13; - uint16_t RESERVED16; - __IO uint16_t DATAR14; - uint16_t RESERVED17; - __IO uint16_t DATAR15; - uint16_t RESERVED18; - __IO uint16_t DATAR16; - uint16_t RESERVED19; - __IO uint16_t DATAR17; - uint16_t RESERVED20; - __IO uint16_t DATAR18; - uint16_t RESERVED21; - __IO uint16_t DATAR19; - uint16_t RESERVED22; - __IO uint16_t DATAR20; - uint16_t RESERVED23; - __IO uint16_t DATAR21; - uint16_t RESERVED24; - __IO uint16_t DATAR22; - uint16_t RESERVED25; - __IO uint16_t DATAR23; - uint16_t RESERVED26; - __IO uint16_t DATAR24; - uint16_t RESERVED27; - __IO uint16_t DATAR25; - uint16_t RESERVED28; - __IO uint16_t DATAR26; - uint16_t RESERVED29; - __IO uint16_t DATAR27; - uint16_t RESERVED30; - __IO uint16_t DATAR28; - uint16_t RESERVED31; - __IO uint16_t DATAR29; - uint16_t RESERVED32; - __IO uint16_t DATAR30; - uint16_t RESERVED33; - __IO uint16_t DATAR31; - uint16_t RESERVED34; - __IO uint16_t DATAR32; - uint16_t RESERVED35; - __IO uint16_t DATAR33; - uint16_t RESERVED36; - __IO uint16_t DATAR34; - uint16_t RESERVED37; - __IO uint16_t DATAR35; - uint16_t RESERVED38; - __IO uint16_t DATAR36; - uint16_t RESERVED39; - __IO uint16_t DATAR37; - uint16_t RESERVED40; - __IO uint16_t DATAR38; - uint16_t RESERVED41; - __IO uint16_t DATAR39; - uint16_t RESERVED42; - __IO uint16_t DATAR40; - uint16_t RESERVED43; - __IO uint16_t DATAR41; - uint16_t RESERVED44; - __IO uint16_t DATAR42; - uint16_t RESERVED45; -} BKP_TypeDef; -#endif - -#if defined(CH32V20x) || defined(CH32V30x) -/* Controller Area Network TxMailBox */ -typedef struct -{ - __IO uint32_t TXMIR; - __IO uint32_t TXMDTR; - __IO uint32_t TXMDLR; - __IO uint32_t TXMDHR; -} CAN_TxMailBox_TypeDef; - -/* Controller Area Network FIFOMailBox */ -typedef struct -{ - __IO uint32_t RXMIR; - __IO uint32_t RXMDTR; - __IO uint32_t RXMDLR; - __IO uint32_t RXMDHR; -} CAN_FIFOMailBox_TypeDef; - -/* Controller Area Network FilterRegister */ -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/* Controller Area Network */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t STATR; - __IO uint32_t TSTATR; - __IO uint32_t RFIFO0; - __IO uint32_t RFIFO1; - __IO uint32_t INTENR; - __IO uint32_t ERRSR; - __IO uint32_t BTIMR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FCTLR; - __IO uint32_t FMCFGR; - uint32_t RESERVED2; - __IO uint32_t FSCFGR; - uint32_t RESERVED3; - __IO uint32_t FAFIFOR; - uint32_t RESERVED4; - __IO uint32_t FWR; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[28]; -} CAN_TypeDef; -#endif - -/* CRC Calculation Unit */ -typedef struct -{ - __IO uint32_t DATAR; - __IO uint8_t IDATAR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CTLR; -} CRC_TypeDef; - -#if defined(CH32V10x) || defined(CH32V30x) -/* Digital to Analog Converter */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SWTR; - __IO uint32_t R12BDHR1; - __IO uint32_t L12BDHR1; - __IO uint32_t R8BDHR1; - __IO uint32_t R12BDHR2; - __IO uint32_t L12BDHR2; - __IO uint32_t R8BDHR2; - __IO uint32_t RD12BDHR; - __IO uint32_t LD12BDHR; - __IO uint32_t RD8BDHR; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -} DAC_TypeDef; -#endif - -/* Debug MCU */ -typedef struct -{ - __IO uint32_t CFGR0; - __IO uint32_t CFGR1; -} DBGMCU_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; -#ifdef CH32V003 - __IO uint32_t BOOT_MODEKEYR; -#endif -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -#endif -} OB_TypeDef; - -typedef struct -{ - __IO uint16_t CAP; - __IO uint16_t RES1; - __IO uint32_t RES2; - __IO uint32_t UID0; - __IO uint32_t UID1; - __IO uint32_t UID2; - __IO uint32_t RES3; -} ESG_TypeDef; - -typedef struct -{ - union - { - __I uint32_t CHIPID; - struct - { - __I uint16_t REVID; - __I uint16_t DEVID; - }; - }; -} INFO_TypeDef; - -#if defined(CH32V30x) -/* FSMC Bank1 Registers */ -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/* FSMC Bank1E Registers */ -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/* FSMC Bank2 Registers */ -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; -#endif - -/* General Purpose I/O */ -typedef enum -{ - GPIO_CFGLR_IN_ANALOG = 0, - GPIO_CFGLR_IN_FLOAT = 4, - GPIO_CFGLR_IN_PUPD = 8, - GPIO_CFGLR_OUT_10Mhz_PP = 1, - GPIO_CFGLR_OUT_2Mhz_PP = 2, - GPIO_CFGLR_OUT_50Mhz_PP = 3, - GPIO_CFGLR_OUT_10Mhz_OD = 5, - GPIO_CFGLR_OUT_2Mhz_OD = 6, - GPIO_CFGLR_OUT_50Mhz_OD = 7, - GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, - GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, - GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, - GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, - GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, - GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, -} GPIO_CFGLR_PIN_MODE_Typedef; - -typedef union { - uint32_t __FULL; - struct { - GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; - GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; - }; -} GPIO_CFGLR_t; -typedef union { - uint32_t __FULL; - const struct { - uint32_t IDR0 :1; - uint32_t IDR1 :1; - uint32_t IDR2 :1; - uint32_t IDR3 :1; - uint32_t IDR4 :1; - uint32_t IDR5 :1; - uint32_t IDR6 :1; - uint32_t IDR7 :1; - uint32_t :24; - }; -} GPIO_INDR_t; -typedef union { - uint32_t __FULL; - struct { - uint32_t ODR0 :1; - uint32_t ODR1 :1; - uint32_t ODR2 :1; - uint32_t ODR3 :1; - uint32_t ODR4 :1; - uint32_t ODR5 :1; - uint32_t ODR6 :1; - uint32_t ODR7 :1; - uint32_t :24; - }; -} GPIO_OUTDR_t; -typedef union { - uint32_t __FULL; - struct { - uint32_t BS0 :1; - uint32_t BS1 :1; - uint32_t BS2 :1; - uint32_t BS3 :1; - uint32_t BS4 :1; - uint32_t BS5 :1; - uint32_t BS6 :1; - uint32_t BS7 :1; - uint32_t :8; - uint32_t BR0 :1; - uint32_t BR1 :1; - uint32_t BR2 :1; - uint32_t BR3 :1; - uint32_t BR4 :1; - uint32_t BR5 :1; - uint32_t BR6 :1; - uint32_t BR7 :1; - uint32_t :8; - }; -} GPIO_BSHR_t; -typedef union { - uint32_t __FULL; - struct { - uint32_t BR0 :1; - uint32_t BR1 :1; - uint32_t BR2 :1; - uint32_t BR3 :1; - uint32_t BR4 :1; - uint32_t BR5 :1; - uint32_t BR6 :1; - uint32_t BR7 :1; - uint32_t :24; - }; -} GPIO_BCR_t; -typedef union { - uint32_t __FULL; - struct { - uint32_t LCK0 :1; - uint32_t LCK1 :1; - uint32_t LCK2 :1; - uint32_t LCK3 :1; - uint32_t LCK4 :1; - uint32_t LCK5 :1; - uint32_t LCK6 :1; - uint32_t LCK7 :1; - uint32_t LCKK :1; - uint32_t :23; - }; -} GPIO_LCKR_t; -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __I uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -#ifdef CH32X03x - __IO uint32_t CFGXR; - __IO uint32_t BSXR; -#endif -} GPIO_TypeDef; - -#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) -#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL -#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} - -/* Alternate Function I/O */ -typedef struct -{ -#ifdef CH32V003 - uint32_t RESERVED0; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR; -#elif defined(CH32X03x) - uint32_t RESERVED0; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR1; - __IO uint32_t EXTICR2; - uint32_t RESERVED1; - uint32_t RESERVED2; - __IO uint32_t CTLR; -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - __IO uint32_t ECR; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t PCFR2; -#endif -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - __IO uint16_t RTR; - uint16_t RESERVED8; -#endif -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; -#ifdef CH32V003 // AWU is CH32V003-only - __IO uint32_t AWUCSR; - __IO uint32_t AWUWR; - __IO uint32_t AWUPSC; -#endif -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; -#ifdef CH32V003 - __IO uint32_t RESERVED0; -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - __IO uint32_t BDCTLR; -#endif - __IO uint32_t RSTSCKR; -#if defined(CH32V20x) || defined(CH32V30x) - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif -} RCC_TypeDef; - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -/* Real-Time Clock */ -typedef struct -{ - __IO uint16_t CTLRH; - uint16_t RESERVED0; - __IO uint16_t CTLRL; - uint16_t RESERVED1; - __IO uint16_t PSCRH; - uint16_t RESERVED2; - __IO uint16_t PSCRL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRMH; - uint16_t RESERVED8; - __IO uint16_t ALRML; - uint16_t RESERVED9; -} RTC_TypeDef; -#endif - -#if defined(CH32V30x) -/* SDIO Registers */ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; -#endif - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; -#ifdef CH32V003 - uint32_t RESERVED7; - uint32_t RESERVED8; -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -#endif -#if !defined(CH32V10x) - __IO uint16_t HSCR; - uint16_t RESERVED9; -#endif -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; -#ifdef CH32V003 - __IO uint32_t CH1CVR; - __IO uint32_t CH2CVR; - __IO uint32_t CH3CVR; - __IO uint32_t CH4CVR; - __IO uint16_t BDTR; - uint16_t RESERVED13; - __IO uint16_t DMACFGR; - uint16_t RESERVED14; - __IO uint16_t DMAADR; - uint16_t RESERVED15; -#elif defined(CH32X03x) - __IO uint32_t CH1CVR; - __IO uint32_t CH2CVR; - __IO uint32_t CH3CVR; - __IO uint32_t CH4CVR; - __IO uint16_t BDTR; - uint16_t RESERVED13; - __IO uint16_t DMACFGR; - uint16_t RESERVED14; - __IO uint16_t DMAADR; - uint16_t RESERVED15; - __IO uint16_t SPEC; - uint16_t RESERVED16; -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) - __IO uint16_t CH1CVR; - uint16_t RESERVED13; - __IO uint16_t CH2CVR; - uint16_t RESERVED14; - __IO uint16_t CH3CVR; - uint16_t RESERVED15; - __IO uint16_t CH4CVR; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DMACFGR; - uint16_t RESERVED18; - __IO uint16_t DMAADR; - uint16_t RESERVED19; -#endif -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ -typedef struct -{ - __IO uint32_t CTR; -} EXTEND_TypeDef; - - -#if defined(CH32V20x) || defined(CH32V30x) -/* OPA Registers */ -typedef struct -{ - __IO uint32_t CR; -} OPA_TypeDef; - -#if defined(CH32V30x) -/* RNG Registers */ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SR; - __IO uint32_t DR; -} RNG_TypeDef; - -/* DVP Registers */ -typedef struct -{ - __IO uint8_t CR0; - __IO uint8_t CR1; - __IO uint8_t IER; - __IO uint8_t Reserved0; - __IO uint16_t ROW_NUM; - __IO uint16_t COL_NUM; - __IO uint32_t DMA_BUF0; - __IO uint32_t DMA_BUF1; - __IO uint8_t IFR; - __IO uint8_t STATUS; - __IO uint16_t Reserved1; - __IO uint16_t ROW_CNT; - __IO uint16_t Reserved2; - __IO uint16_t HOFFCNT; - __IO uint16_t VST; - __IO uint16_t CAPCNT; - __IO uint16_t VLINE; - __IO uint32_t DR; -} DVP_TypeDef; - -/* USBHS Registers */ -typedef struct -{ - __IO uint8_t CONTROL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_AD; - __IO uint16_t FRAME_NO; - __IO uint8_t SUSPEND; - __IO uint8_t RESERVED0; - __IO uint8_t SPEED_TYPE; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t RESERVED1; - __IO uint32_t ENDP_CONFIG; - __IO uint32_t ENDP_TYPE; - __IO uint32_t BUF_MODE; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_RX_DMA; - __IO uint32_t UEP2_RX_DMA; - __IO uint32_t UEP3_RX_DMA; - __IO uint32_t UEP4_RX_DMA; - __IO uint32_t UEP5_RX_DMA; - __IO uint32_t UEP6_RX_DMA; - __IO uint32_t UEP7_RX_DMA; - __IO uint32_t UEP8_RX_DMA; - __IO uint32_t UEP9_RX_DMA; - __IO uint32_t UEP10_RX_DMA; - __IO uint32_t UEP11_RX_DMA; - __IO uint32_t UEP12_RX_DMA; - __IO uint32_t UEP13_RX_DMA; - __IO uint32_t UEP14_RX_DMA; - __IO uint32_t UEP15_RX_DMA; - __IO uint32_t UEP1_TX_DMA; - __IO uint32_t UEP2_TX_DMA; - __IO uint32_t UEP3_TX_DMA; - __IO uint32_t UEP4_TX_DMA; - __IO uint32_t UEP5_TX_DMA; - __IO uint32_t UEP6_TX_DMA; - __IO uint32_t UEP7_TX_DMA; - __IO uint32_t UEP8_TX_DMA; - __IO uint32_t UEP9_TX_DMA; - __IO uint32_t UEP10_TX_DMA; - __IO uint32_t UEP11_TX_DMA; - __IO uint32_t UEP12_TX_DMA; - __IO uint32_t UEP13_TX_DMA; - __IO uint32_t UEP14_TX_DMA; - __IO uint32_t UEP15_TX_DMA; - __IO uint16_t UEP0_MAX_LEN; - __IO uint16_t RESERVED2; - __IO uint16_t UEP1_MAX_LEN; - __IO uint16_t RESERVED3; - __IO uint16_t UEP2_MAX_LEN; - __IO uint16_t RESERVED4; - __IO uint16_t UEP3_MAX_LEN; - __IO uint16_t RESERVED5; - __IO uint16_t UEP4_MAX_LEN; - __IO uint16_t RESERVED6; - __IO uint16_t UEP5_MAX_LEN; - __IO uint16_t RESERVED7; - __IO uint16_t UEP6_MAX_LEN; - __IO uint16_t RESERVED8; - __IO uint16_t UEP7_MAX_LEN; - __IO uint16_t RESERVED9; - __IO uint16_t UEP8_MAX_LEN; - __IO uint16_t RESERVED10; - __IO uint16_t UEP9_MAX_LEN; - __IO uint16_t RESERVED11; - __IO uint16_t UEP10_MAX_LEN; - __IO uint16_t RESERVED12; - __IO uint16_t UEP11_MAX_LEN; - __IO uint16_t RESERVED13; - __IO uint16_t UEP12_MAX_LEN; - __IO uint16_t RESERVED14; - __IO uint16_t UEP13_MAX_LEN; - __IO uint16_t RESERVED15; - __IO uint16_t UEP14_MAX_LEN; - __IO uint16_t RESERVED16; - __IO uint16_t UEP15_MAX_LEN; - __IO uint16_t RESERVED17; - __IO uint16_t UEP0_TX_LEN; - __IO uint8_t UEP0_TX_CTRL; - __IO uint8_t UEP0_RX_CTRL; - __IO uint16_t UEP1_TX_LEN; - __IO uint8_t UEP1_TX_CTRL; - __IO uint8_t UEP1_RX_CTRL; - __IO uint16_t UEP2_TX_LEN; - __IO uint8_t UEP2_TX_CTRL; - __IO uint8_t UEP2_RX_CTRL; - __IO uint16_t UEP3_TX_LEN; - __IO uint8_t UEP3_TX_CTRL; - __IO uint8_t UEP3_RX_CTRL; - __IO uint16_t UEP4_TX_LEN; - __IO uint8_t UEP4_TX_CTRL; - __IO uint8_t UEP4_RX_CTRL; - __IO uint16_t UEP5_TX_LEN; - __IO uint8_t UEP5_TX_CTRL; - __IO uint8_t UEP5_RX_CTRL; - __IO uint16_t UEP6_TX_LEN; - __IO uint8_t UEP6_TX_CTRL; - __IO uint8_t UEP6_RX_CTRL; - __IO uint16_t UEP7_TX_LEN; - __IO uint8_t UEP7_TX_CTRL; - __IO uint8_t UEP7_RX_CTRL; - __IO uint16_t UEP8_TX_LEN; - __IO uint8_t UEP8_TX_CTRL; - __IO uint8_t UEP8_RX_CTRL; - __IO uint16_t UEP9_TX_LEN; - __IO uint8_t UEP9_TX_CTRL; - __IO uint8_t UEP9_RX_CTRL; - __IO uint16_t UEP10_TX_LEN; - __IO uint8_t UEP10_TX_CTRL; - __IO uint8_t UEP10_RX_CTRL; - __IO uint16_t UEP11_TX_LEN; - __IO uint8_t UEP11_TX_CTRL; - __IO uint8_t UEP11_RX_CTRL; - __IO uint16_t UEP12_TX_LEN; - __IO uint8_t UEP12_TX_CTRL; - __IO uint8_t UEP12_RX_CTRL; - __IO uint16_t UEP13_TX_LEN; - __IO uint8_t UEP13_TX_CTRL; - __IO uint8_t UEP13_RX_CTRL; - __IO uint16_t UEP14_TX_LEN; - __IO uint8_t UEP14_TX_CTRL; - __IO uint8_t UEP14_RX_CTRL; - __IO uint16_t UEP15_TX_LEN; - __IO uint8_t UEP15_TX_CTRL; - __IO uint8_t UEP15_RX_CTRL; -} USBHSD_TypeDef; - -typedef struct __attribute__((packed)) -{ - __IO uint8_t CONTROL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_AD; - __IO uint16_t FRAME_NO; - __IO uint8_t SUSPEND; - __IO uint8_t RESERVED0; - __IO uint8_t SPEED_TYPE; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t RESERVED1; - __IO uint32_t HOST_EP_CONFIG; - __IO uint32_t HOST_EP_TYPE; - __IO uint32_t RESERVED2; - __IO uint32_t RESERVED3; - __IO uint32_t RESERVED4; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t RESERVED5; - __IO uint32_t RESERVED6; - __IO uint32_t RESERVED7; - __IO uint32_t RESERVED8; - __IO uint32_t RESERVED9; - __IO uint32_t RESERVED10; - __IO uint32_t RESERVED11; - __IO uint32_t RESERVED12; - __IO uint32_t RESERVED13; - __IO uint32_t RESERVED14; - __IO uint32_t RESERVED15; - __IO uint32_t RESERVED16; - __IO uint32_t RESERVED17; - __IO uint32_t RESERVED18; - __IO uint32_t RESERVED19; - __IO uint32_t HOST_TX_DMA; - __IO uint32_t RESERVED20; - __IO uint32_t RESERVED21; - __IO uint32_t RESERVED22; - __IO uint32_t RESERVED23; - __IO uint32_t RESERVED24; - __IO uint32_t RESERVED25; - __IO uint32_t RESERVED26; - __IO uint32_t RESERVED27; - __IO uint32_t RESERVED28; - __IO uint32_t RESERVED29; - __IO uint32_t RESERVED30; - __IO uint32_t RESERVED31; - __IO uint32_t RESERVED32; - __IO uint32_t RESERVED33; - __IO uint16_t HOST_RX_MAX_LEN; - __IO uint16_t RESERVED34; - __IO uint32_t RESERVED35; - __IO uint32_t RESERVED36; - __IO uint32_t RESERVED37; - __IO uint32_t RESERVED38; - __IO uint32_t RESERVED39; - __IO uint32_t RESERVED40; - __IO uint32_t RESERVED41; - __IO uint32_t RESERVED42; - __IO uint32_t RESERVED43; - __IO uint32_t RESERVED44; - __IO uint32_t RESERVED45; - __IO uint32_t RESERVED46; - __IO uint32_t RESERVED47; - __IO uint32_t RESERVED48; - __IO uint32_t RESERVED49; - __IO uint8_t HOST_EP_PID; - __IO uint8_t RESERVED50; - __IO uint8_t RESERVED51; - __IO uint8_t HOST_RX_CTRL; - __IO uint16_t HOST_TX_LEN; - __IO uint8_t HOST_TX_CTRL; - __IO uint8_t RESERVED52; - __IO uint16_t HOST_SPLIT_DATA; -} USBHSH_TypeDef; - -#endif // #if defined(CH32V30x) - -/* USBD Full-Speed Device, Chapter 21. - NOTE: USBD and CAN controller share a dedicated 512-byte SRAM area for data - transmission and reception in the design, so when using USBD and CAN functions - at the same time, this shared area needs to be allocated reasonably to prevent - data conflicts. */ - -typedef struct -{ - __IO uint32_t ADDn_TX; - __IO uint32_t COUNTn_TX; - __IO uint32_t ADDn_RX; - __IO uint32_t COUNTn_RX; -} USBD_BTABLE_TypeDef; - -typedef struct -{ - __IO uint32_t EPR[8]; - __IO uint32_t RESERVED[8]; - __IO uint32_t CNTR; - __IO uint32_t ISTR; - __IO uint32_t FNR; - __IO uint32_t DADDR; - __IO uint32_t BTABLE; -} USBD_TypeDef; - -#define CAN_USBD_SHARED_BASE ((PERIPH_BASE + 0x6000)) -#define USBD_BASE ((PERIPH_BASE + 0x5C00)) - -/* USBD_CNTR */ -#define USBD_CTRM (1<<15) -#define USBD_PMAOVRM (1<<14) -#define USBD_ERRM (1<<13) -#define USBD_WKUPM (1<<12) -#define USBD_SUSPM (1<<11) -#define USBD_RESETM (1<<10) -#define USBD_SOFM (1<<9) -#define USBD_ESOFM (1<<8) -#define USBD_RESUME (1<<4) -#define USBD_FSUP (1<<3) -#define USBD_LPMODE (1<<2) -#define USBD_PDWN (1<<1) -#define USBD_FRES (1<<0) - -/* USBD_ISTR */ -#define USBD_CTR (1<<15) -#define USBD_PMAOVR (1<<14) -#define USBD_ERR (1<<13) -#define USBD_WKUP (1<<12) -#define USBD_SUSP (1<<11) -#define USBD_RESET (1<<10) -#define USBD_SOF (1<<9) -#define USBD_ESOF (1<<8) -#define USBD_DIR (1<<4) -#define USBD_EP_ID (0xf) - -/* USBD_FNR */ -#define USBD_RXDP (1<<15) -#define USBD_RXDM (1<<14) -#define USBD_LCK (1<<13) -#define USBD_LSOF (3<<11) -#define USBD_FN (0x7ff) - -/* USBD_DADDR */ -#define USBD_EF (1<<7) -#define USBD_ADD (0x7f) - -/* USBD_EPRx */ -#define USBD_CTR_RX (1<<15) -#define USBD_DTOG_RX (1<<14) -#define USBD_STAT_RX (3<<12) -#define USBD_SETUP (1<<11) -#define USBD_EPTYPE (3<<9) -#define USBD_EPKIND (1<<8) -#define USBD_CTR_TX (1<<7) -#define USBD_DTOG_TX (1<<6) -#define USBD_STAT_TX (3<<4) -#define USBD_EA (0xf) - -/* USBD_COUNTx_RX */ -#define USBD_BLSIZE (1<<15) -#define USBD_NUM_BLOCK (0x1f<<10) -#define USBD_COUNTx_RX 0x2ff - - -#define USBD ((USBD_TypeDef *) USBD_BASE) - -/* USB-FS-OTG Registers, Chapter 23. */ -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t UDEV_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) - __IO uint8_t INT_ST; - __IO uint32_t RX_LEN; - __IO uint8_t UEP4_1_MOD; - __IO uint8_t UEP2_3_MOD; - __IO uint8_t UEP5_6_MOD; - __IO uint8_t UEP7_MOD; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_DMA; - __IO uint32_t UEP2_DMA; - __IO uint32_t UEP3_DMA; - __IO uint32_t UEP4_DMA; - __IO uint32_t UEP5_DMA; - __IO uint32_t UEP6_DMA; - __IO uint32_t UEP7_DMA; - __IO uint16_t UEP0_TX_LEN; - __IO uint8_t UEP0_TX_CTRL; - __IO uint8_t UEP0_RX_CTRL; - __IO uint16_t UEP1_TX_LEN; - __IO uint8_t UEP1_TX_CTRL; - __IO uint8_t UEP1_RX_CTRL; - __IO uint16_t UEP2_TX_LEN; - __IO uint8_t UEP2_TX_CTRL; - __IO uint8_t UEP2_RX_CTRL; - __IO uint16_t UEP3_TX_LEN; - __IO uint8_t UEP3_TX_CTRL; - __IO uint8_t UEP3_RX_CTRL; - __IO uint16_t UEP4_TX_LEN; - __IO uint8_t UEP4_TX_CTRL; - __IO uint8_t UEP4_RX_CTRL; - __IO uint16_t UEP5_TX_LEN; - __IO uint8_t UEP5_TX_CTRL; - __IO uint8_t UEP5_RX_CTRL; - __IO uint16_t UEP6_TX_LEN; - __IO uint8_t UEP6_TX_CTRL; - __IO uint8_t UEP6_RX_CTRL; - __IO uint16_t UEP7_TX_LEN; - __IO uint8_t UEP7_TX_CTRL; - __IO uint8_t UEP7_RX_CTRL; - __IO uint32_t Reserve1; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -} USBOTG_FS_TypeDef; - -/* R8_USB_CTRL */ -#define USBOTG_UC_HOST_MODE (1<<7) -#define USBOTG_UC_LOW_SPEED (1<<6) -#define USBOTG_UC_DEV_PU_EN (1<<5) -#define USBOTG_UC_SYS_CTRL (1<<4) -#define USBOTG_UC_INT_BUSY (1<<3) -#define USBOTG_UC_RESET_SIE (1<<2) -#define USBOTG_UC_CLR_ALL (1<<1) -#define USBOTG_UC_DMA_EN (1<<0) - -/* R8_USB_INT_EN */ -#define USBOTG_UIE_DEV_NAK (1<<6) -#define USBOTG_UIE_FIFO_OV (1<<4) -#define USBOTG_UIE_HST_SOF (1<<3) -#define USBOTG_UIE_SUSPEND (1<<2) -#define USBOTG_UIE_TRANSFER (1<<1) -#define USBOTG_UIE_DETECT (1<<0) -#define USBOTG_UIE_BUS_RST (1<<0) - -/* R8_USB_DEV_AD */ -#define USBOTG_UDA_GP_BIT (1<<7) -#define USBOTG_USB_ADDR (1<<6) - -/* R8_USB_MIS_ST */ -#define USBOTG_UMS_SOF_PRES (1<<7) -#define USBOTG_UMS_SOF_ACT (1<<6) -#define USBOTG_UMS_SIE_FREE (1<<5) -#define USBOTG_UMS_R_FIFO_RDY (1<<4) -#define USBOTG_UMS_BUS_RESET (1<<3) -#define USBOTG_UMS_SUSPEND (1<<2) -#define USBOTG_UMS_DM_LEVEL (1<<1) -#define USBOTG_UMS_DEV_ATTACH (1<<0) - -/* R8_USB_INT_FG */ -#define USBOTG_U_IS_NAK (1<<7) -#define USBOTG_U_TOG_OK (1<<6) -#define USBOTG_U_SIE_FREE (1<<5) -#define USBOTG_UIF_FIFO_OV (1<<4) -#define USBOTG_UIF_HST_SOF (1<<3) -#define USBOTG_UIF_SUSPEND (1<<2) -#define USBOTG_UIF_TRANSFER (1<<1) -#define USBOTG_UIF_DETECT (1<<0) -#define USBOTG_UIF_BUS_RST (1<<0) - -/* R8_USB_INT_ST */ -#define USBOTG_UIS_IS_NAK (1<<7) -#define USBOTG_UIS_TOG_OK (1<<6) -#define USBOTG_UIS_TOKEN (3<<4) -#define USBOTG_UIS_ENDP 0xf -#define USBOTG_UIS_H_RES 0xf - -/* R32_USB_OTG_CR */ -#define USBOTG_CR_SESS_VTH (1<<5) -#define USBOTG_CR_VBUS_VTH (1<<4) -#define USBOTG_CR_OTG_EN (1<<3) -#define USBOTG_CR_IDPU (1<<2) -#define USBOTG_CR_CHARGE_VBUS (1<<1) -#define USBOTG_CR_DISCHAR_VBUS (1<<0) - -/* R32_USB_OTG_SR */ -#define USBOTG_SR_ID_DIG (1<<3) -#define USBOTG_SR_SESS_END (1<<2) -#define USBOTG_SR_SESS_VLD (1<<1) -#define USBOTG_SR_VBUS_VLD (1<<0) - -/* R8_UEPn_TX_CTRL */ -#define USBOTG_UEP_T_AUTO_TOG (1<<3) -#define USBOTG_UEP_T_TOG (1<<2) -#define USBOTG_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) -#define USBOTG_UEP_T_RES_ACK (0<<1) -#define USBOTG_UEP_T_RES_NONE (1<<0) -#define USBOTG_UEP_T_RES_NAK (1<<1) -#define USBOTG_UEP_T_RES_STALL (3<<0) - -#define USBOTG_UEP_R_AUTO_TOG (1<<3) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define USBOTG_UEP_R_TOG (1<<2) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 -#define USBOTG_UEP_R_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X receiving (OUT) -#define USBOTG_UEP_R_RES_ACK (0<<1) -#define USBOTG_UEP_R_RES_NONE (1<<0) -#define USBOTG_UEP_R_RES_NAK (1<<1) -#define USBOTG_UEP_R_RES_STALL (3<<0) - - - -/* R8_UEPn_ RX_CTRL */ -#define USBOTG_UEP_R_AUTO_TOG (1<<3) -#define USBOTG_UEP_R_TOG (1<<2) -#define USBOTG_UEP_R_RES (3<<0) - -/* R8_UEP7_MOD */ -#define USBOTG_UEP7_RX_EN (1<<3) -#define USBOTG_UEP7_TX_EN (1<<2) -#define USBOTG_UEP7_BUF_MOD (1<<0) - -/* R8_UEP5_6_MOD */ -#define USBOTG_UEP6_RX_EN (1<<7) -#define USBOTG_UEP6_TX_EN (1<<6) -#define USBOTG_UEP6_BUF_MOD (1<<4) -#define USBOTG_UEP5_RX_EN (1<<3) -#define USBOTG_UEP5_TX_EN (1<<2) -#define USBOTG_UEP5_BUF_MOD (1<<0) - -/* R8_UEP2_3_MOD */ -#define USBOTG_UEP3_RX_EN (1<<7) -#define USBOTG_UEP3_TX_EN (1<<6) -#define USBOTG_UEP3_BUF_MOD (1<<4) -#define USBOTG_UEP2_RX_EN (1<<3) -#define USBOTG_UEP2_TX_EN (1<<2) -#define USBOTG_UEP2_BUF_MOD (1<<0) - -/* R8_UEP4_1_MOD */ -#define USBOTG_UEP1_RX_EN (1<<7) -#define USBOTG_UEP1_TX_EN (1<<6) -#define USBOTG_UEP1_BUF_MOD (1<<4) -#define USBOTG_UEP4_RX_EN (1<<3) -#define USBOTG_UEP4_TX_EN (1<<2) -#define USBOTG_UEP4_BUF_MOD (1<<0) - -/* R8_UDEV_CTRL */ -#define USBOTG_UD_PD_DIS (1<<7) -#define USBOTG_UD_DP_PIN (1<<5) -#define USBOTG_UD_DM_PIN (1<<4) -#define USBOTG_UD_LOW_SPEED (1<<2) -#define USBOTG_UD_GP_BIT (1<<1) -#define USBOTG_UD_PORT_EN (1<<0) - - -#define USBFS_UDA_GP_BIT 0x80 -#define USBFS_USB_ADDR_MASK 0x7F - -#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ -#define UEP_SIZE 64 - -#define DEF_UEP_IN 0x80 -#define DEF_UEP_OUT 0x00 -#define DEF_UEP_BUSY 0x01 -#define DEF_UEP_FREE 0x00 - -#define DEF_UEP0 0 -#define DEF_UEP1 1 -#define DEF_UEP2 2 -#define DEF_UEP3 3 -#define DEF_UEP4 4 -#define DEF_UEP5 5 -#define DEF_UEP6 6 -#define DEF_UEP7 7 -#define UNUM_EP 8 - -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t Reserve1; - __IO uint8_t Reserve2; - __IO uint8_t HOST_EP_MOD; - __IO uint16_t Reserve3; - __IO uint32_t Reserve4; - __IO uint32_t Reserve5; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t HOST_TX_DMA; - __IO uint32_t Reserve6; - __IO uint32_t Reserve7; - __IO uint32_t Reserve8; - __IO uint32_t Reserve9; - __IO uint32_t Reserve10; - __IO uint16_t Reserve11; - __IO uint16_t HOST_SETUP; - __IO uint8_t HOST_EP_PID; - __IO uint8_t Reserve12; - __IO uint8_t Reserve13; - __IO uint8_t HOST_RX_CTRL; - __IO uint16_t HOST_TX_LEN; - __IO uint8_t HOST_TX_CTRL; - __IO uint8_t Reserve14; - __IO uint32_t Reserve15; - __IO uint32_t Reserve16; - __IO uint32_t Reserve17; - __IO uint32_t Reserve18; - __IO uint32_t Reserve19; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -} USBOTG_FS_HOST_TypeDef; - -/* R8_UHOST_CTRL */ -#define USBOTG_UH_PD_DIS (1<<7) -#define USBOTG_UH_DP_PIN (1<<5) -#define USBOTG_UH_DM_PIN (1<<4) -#define USBOTG_UH_LOW_SPEED (1<<2) -#define USBOTG_UH_BUS_RESET (1<<1) -#define USBOTG_UH_PORT_EN (1<<0) - -/* R32_UH_EP_MOD */ -#define USBOTG_UH_EP_TX_EN (1<<6) -#define USBOTG_UH_EP_TBUF_MOD (1<<4) -#define USBOTG_UH_EP_RX_EN (1<<3) -#define USBOTG_UH_EP_RBUF_MOD (1<<0) - -/* R16_UH_SETUP */ -#define USBOTG_UH_PRE_PID_EN (1<<10) -#define USBOTG_UH_SOF_EN (1<<2) - -/* R8_UH_EP_PID */ -#define USBOTG_UH_TOKEN (0xf<<4) -#define USBOTG_UH_ENDP (0xf<<0) - -/* R8_UH_RX_CTRL */ -#define USBOTG_UH_R_AUTO_TOG (1<<3) -#define USBOTG_UH_R_TOG (1<<2) -#define USBOTG_UH_R_RES (1<<0) - -/* R8_UH_TX_CTRL */ -#define USBOTG_UH_T_AUTO_TOG (1<<3) -#define USBOTG_UH_T_TOG (1<<2) -#define USBOTG_UH_T_RES (1<<0) - - - -#if defined(CH32V30x) -/* Ethernet MAC */ -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; -#endif // #if defined(CH32V30x) - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -/* ETH10M Registers */ -typedef struct -{ - __IO uint8_t reserved1; - __IO uint8_t reserved2; - __IO uint8_t reserved3; - __IO uint8_t EIE; - - __IO uint8_t EIR; - __IO uint8_t ESTAT; - __IO uint8_t ECON2; - __IO uint8_t ECON1; - - __IO uint16_t ETXST; - __IO uint16_t ETXLN; - - __IO uint16_t ERXST; - __IO uint16_t ERXLN; - - __IO uint32_t HTL; - __IO uint32_t HTH; - - __IO uint8_t ERXFON; - __IO uint8_t MACON1; - __IO uint8_t MACON2; - __IO uint8_t MABBIPG; - - __IO uint16_t EPAUS; - __IO uint16_t MAMXFL; - - __IO uint16_t MIRD; - __IO uint16_t reserved4; - - __IO uint8_t MIERGADR; - __IO uint8_t MISTAT; - __IO uint16_t MIWR; - - __IO uint32_t MAADRL; - - __IO uint16_t MAADRH; - __IO uint16_t reserved5; -} ETH10M_TypeDef; -#endif - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -/* OSC Registers */ -typedef struct -{ - __IO uint32_t HSE_CAL_CTRL; - __IO uint32_t Reserve0; - __IO uint16_t Reserve1; - __IO uint16_t LSI32K_TUNE; - __IO uint32_t Reserve2; - __IO uint32_t Reserve3; - __IO uint32_t Reserve4; - __IO uint32_t Reserve5; - __IO uint8_t Reserve6; - __IO uint8_t LSI32K_CAL_CFG; - __IO uint16_t Reserve7; - __IO uint16_t LSI32K_CAL_STATR; - __IO uint8_t LSI32K_CAL_OV_CNT; - __IO uint8_t LSI32K_CAL_CTRL; -} OSC_TypeDef; - -#endif - -#endif // #if defined(CH32V20x) || defined(CH32V30x) - - -#if defined(CH32X03x) -/* Touch Sensor, Mirrors Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t RESERVED0[3]; - __IO uint32_t CHARGE1; - __IO uint32_t CHARGE2; - __IO uint32_t RESERVED1[10]; - __IO uint32_t CHGOFFSET; - __IO uint32_t RESERVED2[3]; - __IO uint32_t DR_ACT_DCG; -} TKEY_TypeDef; - -/* Op amp / comparator */ -typedef struct -{ - __IO uint16_t CFGR1; - __IO uint16_t CFGR2; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t OPA_KEY; - __IO uint32_t CMP_KEY; - __IO uint32_t POLL_KEY; -} OPACMP_TypeDef; - -/* USB Full Speed Device Mode */ -typedef struct -{ - __IO uint8_t BASE_CTRL; //XXX (spelling) - __IO uint8_t UDEV_CTRL; // or host ctlr - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t RESERVED0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t RESERVED1; - __IO uint8_t UEP4_1_MOD; - __IO uint8_t UEP2_3_MOD; // Also HOST_EP_MOD - __IO uint8_t UEP567_MOD; - __IO uint8_t RESERVED2; - - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_DMA; - __IO uint32_t UEP2_DMA; // Also HOST_RX_DMA - __IO uint32_t UEP3_DMA; // Also HOST_TX_DMA - - //__IO uint32_t UEP0_CTRL; - __IO uint16_t UEP0_TX_LEN; - __IO uint16_t UEP0_CTRL_H; - - //__IO uint32_t UEP1_CTRL; - __IO uint16_t UEP1_TX_LEN; - __IO uint16_t UEP1_CTRL_H; // Also HOST_SETUP - - //__IO uint32_t UEP2_CTRL; - __IO uint16_t UEP2_TX_LEN; // Also HOST_PID - __IO uint16_t UEP2_CTRL_H; // Also HOST_RX_CTL - - //__IO uint32_t UEP3_CTRL; - __IO uint16_t UEP3_TX_LEN; // Also HOST_TX_LEN - __IO uint16_t UEP3_CTRL_H; // Also HOST_TX_CTL - - //__IO uint32_t UEP4_CTRL; - __IO uint16_t UEP4_TX_LEN; - __IO uint16_t UEP4_CTRL_H; - - __IO uint32_t RESERVED3[8]; - - __IO uint32_t UEP5_DMA; - __IO uint32_t UEP6_DMA; - __IO uint32_t UEP7_DMA; - - __IO uint32_t RESERVED4; - - //__IO uint32_t UEP5_CTRL; - __IO uint16_t UEP5_TX_LEN; - __IO uint16_t UEP5_CTRL_H; - - //__IO uint32_t UEP6_CTRL; - __IO uint16_t UEP6_TX_LEN; - __IO uint16_t UEP6_CTRL_H; - - //__IO uint32_t UEP7_CTRL; - __IO uint16_t UEP7_TX_LEN; - __IO uint16_t UEP7_CTRL_H; - - __IO uint32_t UEPX_MOD; -} USBFS_TypeDef; - - - -#define USB_PHY_V33 (1<<6) -#define USB_IOEN (1<<7) - - -#define USBFSD_UEP_MOD_BASE 0x4002340C -#define USBFSD_UEP_DMA_BASE 0x40023410 -#define USBFSD_UEP_LEN_BASE 0x40023420 -#define USBFSD_UEP_CTL_BASE 0x40023422 -#define USBFSD_UEP_RX_EN 0x08 -#define USBFSD_UEP_TX_EN 0x04 -#define USBFSD_UEP_BUF_MOD 0x01 -#define USBFSD_UEP_MOD( N ) (*((volatile uint8_t *)( USBFSD_UEP_MOD_BASE + N ))) -#define USBFSD_UEP_TX_CTRL( N ) (*((volatile uint8_t *)( USBFSD_UEP_CTL_BASE + N * 0x04 ))) -#define USBFSD_UEP_RX_CTRL( N ) (*((volatile uint8_t *)( USBFSD_UEP_CTL_BASE + N * 0x04 ))) -#define USBFSD_UEP_DMA( N ) (*((volatile uint32_t *)( USBFSD_UEP_DMA_BASE + N * 0x04 ))) -#define USBFSD_UEP_BUF( N ) ((uint8_t *)(*((volatile uint32_t *)( USBFSD_UEP_DMA_BASE + N * 0x04 ))) + 0x20000000) -#define USBFSD_UEP_TLEN( N ) (*((volatile uint16_t *)( USBFSD_UEP_LEN_BASE + N * 0x04 ))) - -/* R8_UEPn_TX_CTRL */ -#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 -#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) -#define USBFS_UEP_T_RES_ACK (0<<1) -#define USBFS_UEP_T_RES_NONE (1<<0) -#define USBFS_UEP_T_RES_NAK (1<<1) -#define USBFS_UEP_T_RES_STALL (3<<0) -// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) -// 00: DATA0 or DATA1 then expecting ACK (ready) -// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions -// 10: NAK (busy) -// 11: STALL (error) -// host aux setup - -/* R8_UEPn_RX_CTRL, n=0-7 */ -#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 -#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT) -#define USBFS_UEP_R_RES_ACK (0<<3) -#define USBFS_UEP_R_RES_NONE (1<<2) -#define USBFS_UEP_R_RES_NAK (1<<3) -#define USBFS_UEP_R_RES_STALL (3<<2) - - -#define EP1_T_EN (1<<6) -#define EP2_T_EN (1<<2) -#define EP3_T_EN (1<<6) -#define EP4_T_EN (1<<2) -#define EP1_R_EN (1<<7) -#define EP2_R_EN (1<<3) -#define EP3_R_EN (1<<7) -#define EP4_R_EN (1<<3) - - -/* R8_USB_CTRL */ -#define USBFS_UC_HOST_MODE 0x80 -#define USBFS_UC_LOW_SPEED 0x40 -#define USBFS_UC_DEV_PU_EN 0x20 -#define USBFS_UC_SYS_CTRL_MASK 0x30 -#define USBFS_UC_SYS_CTRL0 0x00 -#define USBFS_UC_SYS_CTRL1 0x10 -#define USBFS_UC_SYS_CTRL2 0x20 -#define USBFS_UC_SYS_CTRL3 0x30 -#define USBFS_UC_INT_BUSY 0x08 -#define USBFS_UC_RESET_SIE 0x04 -#define USBFS_UC_CLR_ALL 0x02 -#define USBFS_UC_DMA_EN 0x01 - -/* R8_USB_INT_EN */ -#define USBFS_UIE_DEV_SOF 0x80 -#define USBFS_UIE_DEV_NAK 0x40 -#define USBFS_UIE_FIFO_OV 0x10 -#define USBFS_UIE_HST_SOF 0x08 -#define USBFS_UIE_SUSPEND 0x04 -#define USBFS_UIE_TRANSFER 0x02 -#define USBFS_UIE_DETECT 0x01 -#define USBFS_UIE_BUS_RST 0x01 - -/* R8_USB_DEV_AD */ -#define USBFS_UDA_GP_BIT 0x80 -#define USBFS_USB_ADDR_MASK 0x7F - -/* R8_USB_MIS_ST */ -#define USBFS_UMS_SOF_PRES 0x80 -#define USBFS_UMS_SOF_ACT 0x40 -#define USBFS_UMS_SIE_FREE 0x20 -#define USBFS_UMS_R_FIFO_RDY 0x10 -#define USBFS_UMS_BUS_RESET 0x08 -#define USBFS_UMS_SUSPEND 0x04 -#define USBFS_UMS_DM_LEVEL 0x02 -#define USBFS_UMS_DEV_ATTACH 0x01 - - - - -#define USBFS_UDA_GP_BIT 0x80 -#define USBFS_USB_ADDR_MASK 0x7F - -#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ -#define UEP_SIZE 64 - -#define DEF_UEP_IN 0x80 -#define DEF_UEP_OUT 0x00 -#define DEF_UEP_BUSY 0x01 -#define DEF_UEP_FREE 0x00 - -#define DEF_UEP0 0 -#define DEF_UEP1 1 -#define DEF_UEP2 2 -#define DEF_UEP3 3 -#define DEF_UEP4 4 -#define DEF_UEP5 5 -#define DEF_UEP6 6 -#define DEF_UEP7 7 -#define UNUM_EP 8 - - - -/* USB Host Mode */ - -typedef struct -{ - __IO uint8_t RESERVED0; - __IO uint8_t HOST_CTRL; - __IO uint8_t RESERVED1; - __IO uint8_t RESERVED2; - __IO uint8_t RESERVED3; - __IO uint8_t RESERVED4; - __IO uint8_t RESERVED5; - __IO uint8_t RESERVED6; - __IO uint16_t RESERVED7; - __IO uint16_t RESERVED8; - __IO uint8_t RESERVED9; - __IO uint8_t HOST_EP_MOD; - __IO uint8_t RESERVED10; - __IO uint8_t RESERVED11; - - __IO uint32_t RESERVED12; - __IO uint32_t RESERVED13; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t HOST_TX_DMA; - - __IO uint16_t RESERVED14; - __IO uint16_t RESERVED15; - __IO uint16_t RESERVED16; - - __IO uint16_t HOST_SETUP; - __IO uint16_t HOST_EP_PID; - __IO uint16_t HOST_RX_CTL; - __IO uint16_t HOST_TX_LEN; - __IO uint16_t HOST_TX_CTL; - - __IO uint16_t RESERVED20; - __IO uint16_t RESERVED21; - - __IO uint32_t RESERVED22[8]; - - __IO uint32_t RESERVED23; - __IO uint32_t RESERVED24; - __IO uint32_t RESERVED25; - - __IO uint32_t RESERVED26; - - __IO uint16_t RESERVED27; - __IO uint16_t RESERVED28; - - __IO uint16_t RESERVED29; - __IO uint16_t RESERVED30; - - __IO uint16_t RESERVED31; - __IO uint16_t RESERVED32; - - __IO uint32_t RESERVED33; -} USBDH_TypeDef; - - -/* USB Power Delivery */ -typedef struct -{ - __IO uint32_t CONFIG; - __IO uint32_t CONTROL; - __IO uint32_t STATUS; - __IO uint32_t PORT; - __IO uint32_t DMA; -} USBPD_TypeDef; - - -/* USB Power Delivery */ -typedef struct -{ - __IO uint16_t CONFIG; - __IO uint16_t BCM_CLK_CNT; - - __IO uint8_t CONTROL; - __IO uint8_t TX_SEL; - __IO uint16_t BMC_TX_SZ; - - __IO uint8_t DATA_BUF; - __IO uint8_t STATUS; - __IO uint16_t BMC_BYTE_CNT; - - __IO uint16_t PORT_CC1; - __IO uint16_t PORT_CC2; - - __IO uint32_t USBPD_DMA; -} USBPD_DETAILED_TypeDef; - -#endif // #if defined(CH32X03x) - - -#endif - -/* Peripheral memory map */ -#ifdef __ASSEMBLER__ -#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ -#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ -#else -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ -#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ -#endif - -#if defined(CH32V30x) -#ifdef __ASSEMBLER__ -#define FSMC_R_BASE (b 0xA0000000) /* FSMC registers base address */ -#else -#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ -#endif -#endif - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#endif // CH32V10x, CH32V20x, CH32V30x -#if defined(CH32V30x) // CH32V30x -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define UART6_BASE (APB1PERIPH_BASE + 0x1800) -#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) -#define UART8_BASE (APB1PERIPH_BASE + 0x2000) -#endif // CH32V30x -#if defined(CH32V10x) // CH32V10x -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#endif // CH32V10x -#if defined(CH32V003) || defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#endif -#endif -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#if defined(CH32V10x) || defined(CH32V30x) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#endif // defined(CH32V30x) || defined(CH32V10x) -#endif -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#if defined(CH32V10x) || defined(CH32V30x) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#endif // defined(CH32V30x) || defined(CH32V10x) -#endif // defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#endif -#if defined(CH32V20x) || defined(CH32V30x) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#endif -#if defined(CH32V30x) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#endif -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#endif -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#if defined(CH32V10x) || defined(CH32V30x) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#endif - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#endif -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#endif -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#endif -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#if defined(CH32V10x) || defined(CH32V30x) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#endif -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#if defined(CH32V10x) || defined(CH32V30x) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) -#endif -#if defined(CH32V30x) -#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) -#endif - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#if defined(CH32V20x) -#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) -#endif -#if defined(CH32V10x) || defined(CH32V30x) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#if defined(CH32V30x) -#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) -#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) -#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) -#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) -#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) -#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) -#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) -#endif // defined(CH32V30x) -#endif -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ - -#if defined(CH32V20x) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define OPA_BASE (AHBPERIPH_BASE + 0x3804) -#define ETH10M_BASE (AHBPERIPH_BASE + 0x8000) - -#define USBFS_BASE ((uint32_t)0x50000000) -#elif defined(CH32X03x) - -#define OPA_BASE (AHBPERIPH_BASE + 0x6000) -#define USBFS_BASE (AHBPERIPH_BASE + 0x3400) -#define USBPD_BASE (AHBPERIPH_BASE + 0x7000) - -#elif defined(CH32V30x) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) -#define OPA_BASE (AHBPERIPH_BASE + 0x3804) -#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define USBFS_BASE ((uint32_t)0x50000000) -#define DVP_BASE ((uint32_t)0x50050000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#elif defined(CH32V10x) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define DBGMCU_BASE ((uint32_t)0xE000D000) -#endif - -#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ -#define ESIG_BASE ((uint32_t)0x1FFFF7E0) -#define INFO_BASE ((uint32_t)0x1FFFF704) - -#if defined(CH32V003) || defined(CH32V10x) -#define EXTEN_BASE ((uint32_t)0x40023800) -#elif defined(CH32V20x) || defined(CH32V30x) -#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) -#endif - -#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) -#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) - -#if defined(CH32V20x) -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -#define OSC_BASE (AHBPERIPH_BASE + 0x202C) -#endif -#endif - - - -// AFIO CTLR Bits -#define PB6_FILT_EN (1<<27) -#define PB5_FILT_EN (1<<26) -#define PA4_FILT_EN (1<<25) -#define PA3_FILT_EN (1<<24) -#define UDM_BC_CMPO (1<<19) -#define UDP_BC_CMPO (1<<17) -#define UDM_BC_VSRC (1<<17) -#define UDP_BC_VSRC (1<<16) -#define USBPD_IN_HVT (1<<9) -#define USBPD_PHY_V33 (1<<8) -#define USB_IOEN (1<<7) -#define USB_PHY_V33 (1<<6) -#define UDP_PUE_00 (0b00<<2) -#define UDP_PUE_01 (0b01<<2) -#define UDP_PUE_10 (0b10<<2) -#define UDP_PUE_11 (0b11<<2) -#define UDM_PUE_00 (0b00<<0) -#define UDM_PUE_01 (0b01<<0) -#define UDM_PUE_10 (0b10<<0) -#define UDM_PUE_11 (0b11<<0) -#define UDP_PUE_MASK 0x0000000C -#define UDP_PUE_DISABLE 0x00000000 -#define UDP_PUE_35UA 0x00000004 -#define UDP_PUE_10K 0x00000008 -#define UDP_PUE_1K5 0x0000000C -#define UDM_PUE_MASK 0x00000003 -#define UDM_PUE_DISABLE 0x00000000 -#define UDM_PUE_35UA 0x00000001 -#define UDM_PUE_10K 0x00000002 -#define UDM_PUE_1K5 0x00000003 - - -// USB PD Bits -#define IE_TX_END (1<<15) -#define IE_RX_RESET (1<<14) -#define IE_RX_ACT (1<<13) -#define IE_RX_BYTE (1<<12) -#define IE_RX_BIT (1<<11) -#define IE_PD_IO (1<<10) -#define WAKE_POLAR (1<<5) -#define PD_RST_EN (1<<4) -#define PD_DMA_EN (1<<3) -#define CC_SEL (1<<2) -#define PD_ALL_CLR (1<<1) -#define PD_FILT_EN (1<<0) -#define BMC_CLK_CNT_MASK (0xff) - -//R8_CONTROL -#define BMC_BYTE_HI (1<<7) -#define TX_BIT_BACK (1<<6) -#define DATA_FLAG (1<<5) -#define RX_STATE_MASK (0x7<<2) -#define RX_STATE_0 (1<<2) -#define RX_STATE_1 (1<<3) -#define RX_STATE_2 (1<<4) -#define BMC_START (1<<1) -#define PD_TX_EN (1<<0) - -#define TX_SEL4_MASK (3<<6) -#define TX_SEL4_0 (1<<6) -#define TX_SEL4_1 (1<<7) - -#define TX_SEL3_MASK (3<<4) -#define TX_SEL3_0 (1<<4) -#define TX_SEL3_1 (1<<5) - -#define TX_SEL2_MASK (3<<2) -#define TX_SEL2_0 (1<<2) -#define TX_SEL2_1 (1<<3) - -#define TX_SEL1 (1<<0) - -#define BMC_TX_SZ_MASK (0x1ff) - -//R8_STATUS -#define IF_TX_END (1<<7) -#define IF_RX_RESET (1<<6) -#define IF_RX_ACT (1<<5) -#define IF_RX_BYTE (1<<4) -#define IF_RX_BIT (1<<3) -#define IFBUF_ERR (1<<2) -#define BMC_AUX_MASK (3<<0) -#define BMC_AUX_1 (1<<1) -#define BMC_AUX_0 (1<<0) - -// PORT CC1 -#define CC1_CE_MASK (7<<5) -#define CC1_CE_0 (1<<5) -#define CC1_CE_1 (2<<5) -#define CC1_CE_2 (4<<5) - -#define CC1_LVE (1<<4) -#define CC1_PU_MASK (3<<2) -#define CC1_PU_DISABLE (0<<2) -#define CC1_PU_330uA (1<<2) -#define CC1_PU_180uA (2<<2) -#define CC1_PU_80uA (3<<2) -#define PA_CC1_AI (1<<0) - -#define CC2_CE_MASK (7<<5) -#define CC2_CE_0 (1<<5) -#define CC2_CE_1 (2<<5) -#define CC2_CE_2 (4<<5) - -#define CC2_LVE (1<<4) -#define CC2_PU_MASK (3<<2) -#define CC2_PU_DISABLE (0<<2) -#define CC2_PU_330uA (1<<2) -#define CC2_PU_180uA (2<<2) -#define CC2_PU_80uA (3<<2) -#define PA_CC2_AI (1<<0) - - - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define TIM5 ((TIM_TypeDef *)TIM5_BASE) -#if defined(CH32V30x) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define UART6 ((USART_TypeDef *) UART6_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#endif // defined(CH32V30x) -#if defined(CH32V10x) -#define TIM6 ((TIM_TypeDef *)TIM6_BASE) -#define TIM7 ((TIM_TypeDef *)TIM7_BASE) -#define TIM12 ((TIM_TypeDef *)TIM12_BASE) -#define TIM13 ((TIM_TypeDef *)TIM13_BASE) -#define TIM14 ((TIM_TypeDef *)TIM14_BASE) -#endif // defined(CH32V10x) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#endif // defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#if defined(CH32V10x) || defined(CH32V30x) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#endif -#endif // defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define UART4 ((USART_TypeDef *)UART4_BASE) -#if defined(CH32V10x) || defined(CH32V30x) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#endif -#endif // defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#endif -#if defined(CH32V20x) || defined(CH32V30x) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#endif -#if defined(CH32V30x) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#endif -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#endif -#define PWR ((PWR_TypeDef *)PWR_BASE) -#if defined(CH32V10x) || defined(CH32V30x) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#endif - -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#endif -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) -#endif -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define ADC2 ((ADC_TypeDef *)ADC2_BASE) -#endif -#ifdef CH32X03x -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TKey ((TKEY_TypeDef *)ADC1_BASE) -#define OPA ((OPACMP_TypeDef *)OPA_BASE) -#define USBFS ((USBFS_TypeDef *)USBFS_BASE) -#define USBPDWORD ((USBPD_TypeDef *)USBPD_BASE) -#define USBPD ((USBPD_DETAILED_TypeDef *)USBPD_BASE) -#define USBDH ((USBDH_TypeDef *)USBFS_BASE) - -#endif -#if defined(CH32V20x) || defined(CH32V30x) -#define TKey1 ((ADC_TypeDef *)ADC1_BASE) -#define TKey2 ((ADC_TypeDef *)ADC2_BASE) -#endif -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#if defined(CH32V10x) || defined(CH32V30x) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#endif -#define USART1 ((USART_TypeDef *)USART1_BASE) -#if defined(CH32V10x) || defined(CH32V30x) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#endif // defined(CH32V10x) || defined(CH32V30x) -#if defined(CH32V30x) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#endif - -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#if defined(CH32V20x) || defined(CH32X03x) -#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) -#endif -#if defined(CH32V10x) || defined(CH32V30x) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#if defined(CH32V30x) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) -#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) -#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) -#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) -#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) -#endif // defined(CH32V30x) -#endif // defined(CH32V10x) || defined(CH32V30x) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#endif -#if defined(CH32V20x) || defined(CH32V30x) -#if defined(CH32V30x) -#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) -#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) -#endif // defined(CH32V30x) -#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) -#define USBOTG_H_FS ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE) -#define OPA ((OPA_TypeDef *)OPA_BASE) -#if defined(CH32V20x) -#define ETH10M ((ETH10M_TypeDef *)ETH10M_BASE) -#elif defined(CH32V30x) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#endif -#endif // defined(CH32V20x) || defined(CH32V30x) -#define OB ((OB_TypeDef *)OB_BASE) -#define ESIG ((ESG_TypeDef *)ESIG_BASE) -// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. -#define INFO ((INFO_TypeDef *)INFO_BASE) -#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) -#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN - -#if defined(CH32V20x) -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -#define OSC ((OSC_TypeDef *)OSC_BASE) -#endif -#endif - -#if defined(CH32V30x) -#define DVP ((DVP_TypeDef *) DVP_BASE) - -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#endif - -#if defined(CH32V10x) -#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) -#endif - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ - -#if defined(CH32V20x) || defined(CH32V30x) -/******************************************************************************/ -/* Backup registers */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DATAR1 register ********************/ -#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR2 register ********************/ -#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR3 register ********************/ -#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR4 register ********************/ -#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR5 register ********************/ -#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR6 register ********************/ -#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR7 register ********************/ -#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR8 register ********************/ -#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR9 register ********************/ -#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR10 register *******************/ -#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR11 register *******************/ -#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR12 register *******************/ -#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR13 register *******************/ -#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR14 register *******************/ -#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR15 register *******************/ -#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR16 register *******************/ -#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR17 register *******************/ -#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_DATAR18 register ********************/ -#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR19 register *******************/ -#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR20 register *******************/ -#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR21 register *******************/ -#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR22 register *******************/ -#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR23 register *******************/ -#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR24 register *******************/ -#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR25 register *******************/ -#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR26 register *******************/ -#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR27 register *******************/ -#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR28 register *******************/ -#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR29 register *******************/ -#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR30 register *******************/ -#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR31 register *******************/ -#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR32 register *******************/ -#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR33 register *******************/ -#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR34 register *******************/ -#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR35 register *******************/ -#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR36 register *******************/ -#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR37 register *******************/ -#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR38 register *******************/ -#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR39 register *******************/ -#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR40 register *******************/ -#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR41 register *******************/ -#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR42 register *******************/ -#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_OCTLR register *******************/ -#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ -#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ -#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ -#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_TPCTLR register ********************/ -#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ -#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ - -/******************* Bit definition for BKP_TPCSR register ********************/ -#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ -#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ -#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ -#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ -#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ - -/******************************************************************************/ -/* Controller Area Network */ -/******************************************************************************/ - -/******************* Bit definition for CAN_CTLR register ********************/ -#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ -#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ -#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ -#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ -#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ -#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ -#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ -#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ -#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ - -/******************* Bit definition for CAN_STATR register ********************/ -#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ -#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ -#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ -#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ -#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ -#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ -#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ -#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ -#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ - -/******************* Bit definition for CAN_TSTATR register ********************/ -#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ -#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ -#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ -#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ -#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ -#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ -#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ -#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ -#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ -#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ -#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ -#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ -#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ -#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ -#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ -#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ - -#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ -#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ -#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ -#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ - -#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ -#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RFIFO0 register *******************/ -#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ -#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ -#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ -#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RFIFO1 register *******************/ -#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ -#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ -#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ -#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_INTENR register *******************/ -#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ -#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ -#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ -#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ -#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ -#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ -#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ -#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ERRSR register *******************/ -#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ -#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ -#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ - -#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ -#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ - -#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ - -/******************* Bit definition for CAN_BTIMR register ********************/ -#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ -#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ -#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ -#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ -#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ -#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ - -/****************** Bit definition for CAN_TXMI0R register ********************/ -#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TXMDT0R register *******************/ -#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/****************** Bit definition for CAN_TXMDL0R register *******************/ -#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/****************** Bit definition for CAN_TXMDH0R register *******************/ -#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI1R register *******************/ -#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT1R register ******************/ -#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL1R register ******************/ -#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH1R register ******************/ -#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI2R register *******************/ -#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT2R register ******************/ -#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL2R register ******************/ -#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH2R register ******************/ -#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI0R register *******************/ -#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT0R register ******************/ -#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL0R register ******************/ -#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH0R register ******************/ -#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI1R register *******************/ -#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT1R register ******************/ -#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL1R register ******************/ -#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH1R register ******************/ -#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_FCTLR register ********************/ -#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ - -/******************* Bit definition for CAN_FMCFGR register *******************/ -#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ -#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ -#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ -#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ -#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ -#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ -#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ -#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ -#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ -#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ -#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ -#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ -#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ -#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ -#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FSCFGR register *******************/ -#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ -#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ -#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ -#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ -#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ -#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ -#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ -#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ -#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ -#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ -#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ -#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ -#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ -#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ -#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FAFIFOR register *******************/ -#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ -#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ -#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ -#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ -#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ -#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ -#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ -#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ -#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ -#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ -#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ -#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ -#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ -#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ -#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FWR register *******************/ -#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ -#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ -#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ -#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ -#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ -#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ -#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ -#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ -#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ -#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ -#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ -#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ -#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ -#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ -#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************************************************************************/ -/* CRC Calculation Unit */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DATAR register *********************/ -#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ - -/******************* Bit definition for CRC_IDATAR register ********************/ -#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CTLR register ********************/ -#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ -#endif - -#if defined(CH32V30x) -/******************************************************************************/ -/* Digital to Analog Converter */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CTLR register ********************/ -#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ -#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ -#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ - -#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ -#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ - -#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ -#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ -#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ -#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ - -#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ -#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ -#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ - -#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ -#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ - -#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTR register ******************/ -#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ -#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ - -/***************** Bit definition for DAC_R12BDHR1 register ******************/ -#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_L12BDHR1 register ******************/ -#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_R8BDHR1 register ******************/ -#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_R12BDHR2 register ******************/ -#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_L12BDHR2 register ******************/ -#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_R8BDHR2 register ******************/ -#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_RD12BDHR register ******************/ -#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ -#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_LD12BDHR register ******************/ -#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ -#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_RD8BDHR register ******************/ -#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ -#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ -#endif - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ - -#if defined(CH32V20x) || defined(CH32V30x) -#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ -#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ -#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ -#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ -#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ -#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ -#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ -#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ -#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ -#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ -#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ -#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ -#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ -#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ -#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ -#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ -#endif - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR4 register *******************/ -#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFGR5 register *******************/ -#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFGR6 register *******************/ -#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR7 register *******************/ -#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ -#if defined(CH32V20x) || defined(CH32V30x) -#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ -#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ -#endif - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ -#if defined(CH32V20x) || defined(CH32V30x) -#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ -#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ -#endif - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#if defined(CH32V20x) || defined(CH32V30x) -#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ -#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ -#endif - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#if defined(CH32V20x) || defined(CH32V30x) -#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ -#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ -#endif - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ -#if defined(CH32V20x) || defined(CH32V30x) -#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ -#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ -#endif - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ -#if defined(CH32V20x) || defined(CH32V30x) -#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ -#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ -#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ -#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ -#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ -#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ -#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ -#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ -#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ -#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ -#endif - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -#if defined(CH32V003) || defined(CH32V10x) || defined(CH32X03x) -/******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ -#endif - -#if defined(CH32V10x) -#define FLASH_ACTLR_HLFCYA ((uint8_t)0x08) /* Flash Half Cycle Access Enable */ -#define FLASH_ACTLR_PRFTBE ((uint8_t)0x10) /* Prefetch Buffer Enable */ -#define FLASH_ACTLR_PRFTBS ((uint8_t)0x20) /* Prefetch Buffer Status */ -#endif - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ -#endif -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG (0x0001) /* Programming */ -#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ -#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT (0x0040) /* Start */ -#define FLASH_CTLR_LOCK (0x0080) /* Lock */ -#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ -#if defined(CH32V20x) || defined(CH32V30x) -#define FLASH_CTLR_FAST_LOCK (0x00008000) /* Fast Lock */ -#endif -#define FLASH_CTLR_PAGE_PG (0x00010000) /* Page Programming 64Byte */ -#define FLASH_CTLR_PAGE_ER (0x00020000) /* Page Erase 64Byte */ -#ifdef CH32V003 -#define FLASH_CTLR_BUF_LOAD (0x00040000) /* Buffer Load */ -#define FLASH_CTLR_BUF_RST (0x00080000) /* Buffer Reset */ -#elif defined(CH32V20x) || defined(CH32V30x) -#define FLASH_CTLR_PAGE_BER32 (0x00040000) /* Block Erase 32K */ -#define FLASH_CTLR_PAGE_BER64 (0x00080000) /* Block Erase 64K */ -#define FLASH_CTLR_PG_STRT (0x00200000) /* Page Programming Start */ -#endif - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -/****************** Bit definition for FLASH_WRPR2 register ******************/ -#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR3 register ******************/ -#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ -#endif - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -/****************** Bit definition for AFIO_ECR register *******************/ -#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ -#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ -#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ -#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ -#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ - -#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ -#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ -#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ -#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ -#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ -#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ -#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ -#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ -#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ -#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ -#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ -#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ -#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ -#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ -#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ -#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ - -#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ -#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ -#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ -#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ - -#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ -#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ -#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ -#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ -#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ - -#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ -#endif - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00200000) /* USART1 remapping higher bit */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 /* legacy compatibility */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP2 ((uint32_t)0x00000080) /* Partial remap (ETR/PD4, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CN2N/PA2, CH3N/PD1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#ifdef CH32V003 -#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#elif defined(CH32V20x) || defined(CH32V30x) -#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#endif -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - - -#if defined(CH32V003) -/***************** Bit definition for AFIO_EXTICR register *****************/ -#define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ -#define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ -#define AFIO_EXTICR_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ -#define AFIO_EXTICR_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ -#define AFIO_EXTICR_EXTI4 ((uint16_t)0x0300) /* EXTI 4 configuration */ -#define AFIO_EXTICR_EXTI5 ((uint16_t)0x0C00) /* EXTI 5 configuration */ -#define AFIO_EXTICR_EXTI6 ((uint16_t)0x3000) /* EXTI 6 configuration */ -#define AFIO_EXTICR_EXTI7 ((uint16_t)0xC000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ -#define AFIO_EXTICR_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ -#define AFIO_EXTICR_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ -#define AFIO_EXTICR_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ -#define AFIO_EXTICR_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ -#define AFIO_EXTICR_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ -#define AFIO_EXTICR_EXTI4_PC ((uint16_t)0x0200) /* PC[4] pin */ -#define AFIO_EXTICR_EXTI4_PD ((uint16_t)0x0300) /* PD[4] pin */ -#define AFIO_EXTICR_EXTI5_PC ((uint16_t)0x0800) /* PC[5] pin */ -#define AFIO_EXTICR_EXTI5_PD ((uint16_t)0x0C00) /* PD[5] pin */ -#define AFIO_EXTICR_EXTI6_PC ((uint16_t)0x2000) /* PC[6] pin */ -#define AFIO_EXTICR_EXTI6_PD ((uint16_t)0x3000) /* PD[6] pin */ -#define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ -#define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ -#endif - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ -#endif - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -/****************** Bit definition for I2C_RTR register *******************/ -#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ -#endif - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ -#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ -#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ -#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ -#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ -#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ -#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ -#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - -#if defined(CH32V30x) -/* for CH32V307 */ -#define RCC_PLL3RDY ((uint32_t)(1<<29)) -#define RCC_PLL3ON ((uint32_t)(1<<28)) -#define RCC_PLL2RDY ((uint32_t)(1<<27)) -#define RCC_PLL2ON ((uint32_t)(1<<26)) -#endif - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#if defined(CH32V003) || defined(CH32X03x) -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ -#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ -#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ -#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ -#endif - -#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ -#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ -#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ -#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ - -#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ - -#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ -#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ -#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ -#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ - -#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#ifdef CH32V003 -#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ -#endif - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ -#if defined(CH32V20x) -#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ -#endif - -#if defined(CH32V30x) - -/* for CH32V307 */ -#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ -#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ -#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ -#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ -#endif - -#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -/******************* Bit definition for RCC_CFGR2 register *******************/ -#ifdef CH32V30x -#define RCC_PREDIV1_OFFSET (0) -#define RCC_PREDIV1_MASK ((uint32_t)(0xf<= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ - (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3))) - -#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ - (((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2)) - -// Compressed load byte, zero-extend result -#define XW_C_LBU(RD, RS, IMM) XW_ENCODE1(XW_OP_LBU, RD, RS, IMM) - -// Compressed store byte -#define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM) - -// Compressed load half, zero-extend result -#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1))) - -// Compressed store half -#define XW_C_SH(RS1, RS2, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1))) - -#endif // CH32V003 - - -// Applies to all processors - - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - - -/* some bit definitions for systick regs */ -#define SYSTICK_SR_CNTIF (1<<0) -#define SYSTICK_CTLR_STE (1<<0) -#define SYSTICK_CTLR_STIE (1<<1) -#define SYSTICK_CTLR_STCLK (1<<2) -#define SYSTICK_CTLR_STRE (1<<3) -#define SYSTICK_CTLR_SWIE (1<<31) - -#define PFIC ((PFIC_Type *) PFIC_BASE ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) - - -#define SysTick ((SysTick_Type *) SysTick_BASE) - - -#define PA1 1 -#define PA2 2 -#define PC0 32 -#define PC1 33 -#define PC2 34 -#define PC3 35 -#define PC4 36 -#define PC5 37 -#define PC6 38 -#define PC7 39 -#define PD0 48 -#define PD1 49 -#define PD2 50 -#define PD3 51 -#define PD4 52 -#define PD5 53 -#define PD6 54 -#define PD7 55 - -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#define PA0 0 -#define PA3 3 -#define PA4 4 -#define PA5 5 -#define PA6 6 -#define PA7 7 -#define PA8 8 -#define PA9 9 -#define PA10 10 -#define PA11 11 -#define PA12 12 -#define PA13 13 -#define PA14 14 -#define PA15 15 -#define PB0 16 -#define PB1 17 -#define PB2 18 -#define PB3 19 -#define PB4 20 -#define PB5 21 -#define PB6 22 -#define PB7 23 -#define PB8 24 -#define PB9 25 -#define PB10 26 -#define PB11 27 -#define PB12 28 -#define PB13 29 -#define PB14 30 -#define PB15 31 -#define PC8 40 -#define PC9 41 -#define PC10 42 -#define PC11 43 -#define PC12 44 -#define PC13 45 -#define PC14 46 -#define PC15 47 -#define PD8 56 -#define PD9 57 -#define PD10 58 -#define PD11 59 -#define PD12 60 -#define PD13 61 -#define PD14 62 -#define PD15 63 -#endif // defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) - -/* - * This file contains various parts of the official WCH EVT Headers which - * were originally under a restrictive license. - * - * The collection of this file was generated by - * cnlohr, 2023-02-18 and - * AlexanderMandera, 2023-06-23 - * It was significantly reworked into several files cnlohr, 2025-01-29 - * - * While originally under a restrictive copyright, WCH has approved use - * under MIT-licensed use, because of inclusion in Zephyr, as well as other - * open-source licensed projects. - * - * These copies of the headers from WCH are available now under: - * - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the “Softwareâ€), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#endif // Header guard diff --git a/src/attic/temp_transition_helper.c b/src/attic/temp_transition_helper.c deleted file mode 100644 index a05b193..0000000 --- a/src/attic/temp_transition_helper.c +++ /dev/null @@ -1,226 +0,0 @@ -#include -#include -#include -#include - -const char * yes[] = { "SENTINEL_WILL_BE_REPLACED_BY_CMDLINE" }; // "CH32X03x", etc. element 0 is filled in by command-line -const char * no[] = { "CH32V10x", "CH32V30x", "CH32V20x", "CH32X03x", "CH32V003" }; - -char * WhitePull( const char ** sti ) -{ - const char * st = *sti; - int len = 0; - while( ( *st == ' ' || *st == '\t' || *st == '(' ) && *st ) { st++; } - const char * sts = st; - while( *st != ' ' && *st != '\t' && *st != '\n' && *st != ')' && *st != '(' && *st != 0 ) { st++; len++; } - if( *st == ')' ) { st++; } - char * ret = malloc( len + 1 ); - memcpy( ret, sts, len ); - ret[len] = 0; - *sti = st; - return ret; -} - -int NYI( const char * s ) -{ - int ret = 2; - char * wp = WhitePull( &s ); - int i; - for( i = 0; i < sizeof(yes)/sizeof(yes[0]); i++ ) - if( strcmp( yes[i], wp ) == 0 ) ret = 1; - if( ret != 1 ) - for( i = 0; i < sizeof(no)/sizeof(no[0]); i++ ) - if( strcmp( no[i], wp ) == 0 ) ret = 0; - free( wp ); - return ret; -} - -int EvalSpec( const char * spl ) -{ - int rsofar = 0; - int i; - int lastv = 0; - int lasto = -1; - int ret = 0; -cont: - char * wp = WhitePull( &spl ); - int def = -1; - if( strcmp( wp, "defined" ) == 0 ) def = 1; - if( strcmp( wp, "!defined" ) == 0 ) def = 2; - if( def < 0 ) return 2; - char * wpn = WhitePull( &spl ); - i = NYI( wpn ); -//printf( "SPIN: %s/%s/%d/%d/%d\n", wp, wpn, i, def, lasto ); - if( i == 2 ) return 2; - - if( def == 2 ) i = !i; - - if( lasto == 1 ) - { - ret = lastv || i; - } - else if( lasto == 2 ) - ret = lastv && i; - else - ret = i; - - char * wpa = WhitePull( &spl ); -//printf( "WPA: \"%s\"\n", wpa ); - lastv = ret; - lasto = -1; -//printf( "RET: %d\n", ret ); - if( strcmp( wpa, "||" ) == 0 ) { lasto = 1; goto cont; } - else if( strcmp( wpa, "&&" ) == 0 ) { lasto = 2; goto cont; } - else return ret; -} - -// 0 for no -// 1 for yes -// 2 for indeterminate -int NoYesInd( const char * preprocc ) -{ - int ret; - int ofs = 0; - if( strncmp( preprocc, "#if ", 4 ) == 0 ) ofs = 4; - if( strncmp( preprocc, "#elif ", 6 ) == 0 ) ofs = 6; - if( ofs ) - { - ret = EvalSpec( preprocc + ofs ); - //printf( "SPEC: %d\n", ret ); - } - else if( strncmp( preprocc, "#ifdef ", 7 ) == 0 ) - { - const char * ep = preprocc + 6; - char * wp = WhitePull( &ep ); - ret = NYI( wp ); - free( wp ); - } - else if( strncmp( preprocc, "#ifndef ", 8 ) == 0 ) - { - const char * ep = preprocc + 6; - char * wp = WhitePull( &ep ); - ret = NYI( wp ); - if( ret < 2 ) ret = !ret; - free( wp ); - } - else - ret = 2; - //printf( "%d-> %s\n", ret, preprocc ); - return ret; -} - -const char * sslineis( const char * line, const char * match ) -{ - while( *line == ' ' || *line == '\t' ) line++; - const char * linestart = line; - while( *line && *match == *line ) { line++; match++; } - if( *match == 0 ) - return linestart; - else - return 0; -} - -int main( int argc, char ** argv ) -{ - if( argc != 3 ) - { - fprintf( stderr, "Syntax: transition [#define to trigger on] [file to convert]\nNo'd architectures:\n" ); - int i; - for( i = 0; i < sizeof(no)/sizeof(no[0]); i++ ) - { - fprintf( stderr, "\t%s\n", no[i] ); - } - return -1; - } - - yes[0] = argv[1]; - - FILE * f = fopen( argv[2], "r" ); - if( !f ) - { - fprintf( stderr, "Error: Could not open \"%s\"\n", argv[2] ); - return -2; - } - char line[1024]; - char * l; - - - int depth = 0; - - // 0 = no - // 1 = yes - // 2 = indeterminate - // 3 = super no. (I.e. after a true #if clause) - int yesnoind[1024]; - yesnoind[0] = 1; - - while( l = fgets( line, sizeof(line)-1, f ) ) - { - const char * ss = 0; - int nyi = yesnoind[depth]; - int waspre = 0; - - if( (ss = sslineis( line, "#if " ) ) || (ss = sslineis( line, "#ifdef " ) ) || (ss = sslineis( line, "#ifndef " ) ) ) - { - waspre = 1; - //printf( "CHECK: %d/%s\n", depth, l ); - nyi = NoYesInd( ss ); - depth++; - yesnoind[depth] = nyi; - } - else if( (ss = sslineis( line, "#elif " ) ) ) - { - if( nyi != 2 ) - { - waspre = 1; - if( nyi == 1 ) - { - nyi = 3; - } - else - { - nyi = NoYesInd( ss ); - } - //printf( "ELIF check: %s %d\n", ss, nyi ); - yesnoind[depth] = nyi; - } - } - else if( (ss = sslineis( line, "#else" ) ) ) - { - if( nyi != 2 ) - { - waspre = 1; - if( yesnoind[depth] == 1 ) - nyi = 3; - else - nyi = !yesnoind[depth]; - yesnoind[depth] = nyi; - } - } - else if( (ss = sslineis( line, "#endif" ) ) ) - { - waspre = 1; - depth--; - if( depth < 0 ) - { - fprintf( stderr, "UNTERMD IF\n" ); - } - } - - int thisv = nyi; - int i; - for( i = 0; i <= depth; i++ ) - { - //printf( "%d", yesnoind[i] ); - if( yesnoind[i] == 0 || yesnoind[i] == 3 ) thisv = 0; - } - //printf( ">>%s", l ); - - if( thisv != 0 && thisv != 3 && ( thisv != 1 || !waspre ) ) - { - printf( "%s", l ); - } - } -} - - diff --git a/src/extralibs/.clang-format b/src/extralibs/.clang-format new file mode 100644 index 0000000..659faab --- /dev/null +++ b/src/extralibs/.clang-format @@ -0,0 +1,5 @@ +{ + "DisableFormat": true, + "SortIncludes": "Never" +} + diff --git a/src/extralibs/ch32v003_GPIO_branchless.h b/src/extralibs/ch32v003_GPIO_branchless.h index c3043ed..5504f0d 100644 --- a/src/extralibs/ch32v003_GPIO_branchless.h +++ b/src/extralibs/ch32v003_GPIO_branchless.h @@ -1,26 +1,22 @@ // 2023-06-26 recallmenot -//######## necessities +// ######## necessities // include guards #ifndef CH32V003_GPIO_BR_H #define CH32V003_GPIO_BR_H // includes -#include //uintN_t support #include "../ch32fun/ch32fun.h" - - +#include //uintN_t support /*######## library description This is a speedy and light GPIO library due to - static inlining of most functions - compile-time abstraction - branchless where it counts + static inlining of most functions + compile-time abstraction + branchless where it counts */ - - /*######## library usage and configuration first, enable the desired port. @@ -98,78 +94,81 @@ Writing `TIMx->SWEVGR |= TIM_UG` will immediately update the shadow register and */ +// ######## ports, pins and states: use these for the functions below! +#define GPIOv_from_PORT_PIN(GPIO_port_n, pin) -//######## ports, pins and states: use these for the functions below! - -#define GPIOv_from_PORT_PIN( GPIO_port_n, pin ) - -enum GPIO_port_n { - GPIO_port_A = 0b00, - GPIO_port_C = 0b10, - GPIO_port_D = 0b11, +enum GPIO_port_n +{ + GPIO_port_A = 0b00, + GPIO_port_C = 0b10, + GPIO_port_D = 0b11, }; -enum GPIO_pinModes { - GPIO_pinMode_I_floating, - GPIO_pinMode_I_pullUp, - GPIO_pinMode_I_pullDown, - GPIO_pinMode_I_analog, - GPIO_pinMode_O_pushPull, - GPIO_pinMode_O_openDrain, - GPIO_pinMode_O_pushPullMux, - GPIO_pinMode_O_openDrainMux, +enum GPIO_pinModes +{ + GPIO_pinMode_I_floating, + GPIO_pinMode_I_pullUp, + GPIO_pinMode_I_pullDown, + GPIO_pinMode_I_analog, + GPIO_pinMode_O_pushPull, + GPIO_pinMode_O_openDrain, + GPIO_pinMode_O_pushPullMux, + GPIO_pinMode_O_openDrainMux, }; -enum lowhigh { - low, - high, +enum lowhigh +{ + low, + high, }; // analog inputs -enum GPIO_analog_inputs { - GPIO_Ain0_A2, - GPIO_Ain1_A1, - GPIO_Ain2_C4, - GPIO_Ain3_D2, - GPIO_Ain4_D3, - GPIO_Ain5_D5, - GPIO_Ain6_D6, - GPIO_Ain7_D4, - GPIO_AinVref, - GPIO_AinVcal, +enum GPIO_analog_inputs +{ + GPIO_Ain0_A2, + GPIO_Ain1_A1, + GPIO_Ain2_C4, + GPIO_Ain3_D2, + GPIO_Ain4_D3, + GPIO_Ain5_D5, + GPIO_Ain6_D6, + GPIO_Ain7_D4, + GPIO_AinVref, + GPIO_AinVcal, }; // how many cycles the ADC shall sample the input for (speed vs precision) -enum GPIO_ADC_sampletimes { - GPIO_ADC_sampletime_3cy, - GPIO_ADC_sampletime_9cy, - GPIO_ADC_sampletime_15cy, - GPIO_ADC_sampletime_30cy, - GPIO_ADC_sampletime_43cy, - GPIO_ADC_sampletime_57cy, - GPIO_ADC_sampletime_73cy, - GPIO_ADC_sampletime_241cy_default, +enum GPIO_ADC_sampletimes +{ + GPIO_ADC_sampletime_3cy, + GPIO_ADC_sampletime_9cy, + GPIO_ADC_sampletime_15cy, + GPIO_ADC_sampletime_30cy, + GPIO_ADC_sampletime_43cy, + GPIO_ADC_sampletime_57cy, + GPIO_ADC_sampletime_73cy, + GPIO_ADC_sampletime_241cy_default, }; -enum GPIO_tim1_output_sets { - GPIO_tim1_output_set_0__D2_A1_C3_C4__D0_A2_D1, - GPIO_tim1_output_set_1__C6_C7_C0_D3__C3_C4_D1, - GPIO_tim1_output_set_2__D2_A1_C3_C4__D0_A2_D1, - GPIO_tim1_output_set_3__C4_C7_C5_D4__C3_D2_C6, +enum GPIO_tim1_output_sets +{ + GPIO_tim1_output_set_0__D2_A1_C3_C4__D0_A2_D1, + GPIO_tim1_output_set_1__C6_C7_C0_D3__C3_C4_D1, + GPIO_tim1_output_set_2__D2_A1_C3_C4__D0_A2_D1, + GPIO_tim1_output_set_3__C4_C7_C5_D4__C3_D2_C6, }; -enum GPIO_tim2_output_sets { - GPIO_tim2_output_set_0__D4_D3_C0_D7, - GPIO_tim2_output_set_1__C5_C2_D2_C1, - GPIO_tim2_output_set_2__C1_D3_C0_D7, - GPIO_tim2_output_set_3__C1_C7_D6_D5, +enum GPIO_tim2_output_sets +{ + GPIO_tim2_output_set_0__D4_D3_C0_D7, + GPIO_tim2_output_set_1__C5_C2_D2_C1, + GPIO_tim2_output_set_2__C1_D3_C0_D7, + GPIO_tim2_output_set_3__C1_C7_D6_D5, }; - - -//######## interface function overview: use these! -// most functions have been reduced to function-like macros, actual definitions downstairs +// ######## interface function overview: use these! +// most functions have been reduced to function-like macros, actual definitions downstairs // setup #define GPIO_port_enable(GPIO_port_n) @@ -202,72 +201,66 @@ static inline void GPIO_tim2_init(); #define GPIO_tim1_analogWrite(channel, value) #define GPIO_tim2_analogWrite(channel, value) +// ######## internal function declarations +// ######## internal variables -//######## internal function declarations +// ######## preprocessor macros - - -//######## internal variables - - - -//######## preprocessor macros - -#define CONCAT(a, b) a ## b +#define CONCAT(a, b) a##b #define CONCAT_INDIRECT(a, b) CONCAT(a, b) #undef GPIOv_from_PORT_PIN -#define GPIOv_from_PORT_PIN( GPIO_port_n, pin ) ((GPIO_port_n << 4 ) | (pin)) -#define GPIOv_to_PORT( GPIOv ) (GPIOv >> 4 ) -#define GPIOv_to_PIN( GPIOv ) (GPIOv & 0b1111) -#define GPIOv_to_GPIObase( GPIOv ) ((GPIO_TypeDef*)(uintptr_t)((GPIOA_BASE + (0x400 * (GPIOv >> 4))))) +#define GPIOv_from_PORT_PIN(GPIO_port_n, pin) ((GPIO_port_n << 4) | (pin)) +#define GPIOv_to_PORT(GPIOv) (GPIOv >> 4) +#define GPIOv_to_PIN(GPIOv) (GPIOv & 0b1111) +#define GPIOv_to_GPIObase(GPIOv) ((GPIO_TypeDef *)(uintptr_t)((GPIOA_BASE + (0x400 * (GPIOv >> 4))))) -#define GPIOx_to_port_n2(GPIOx) GPIOx_to_port_n_##GPIOx -#define GPIOx_to_port_n(GPIOx) GPIOx_to_port_n2(GPIOx) -#define GPIOx_to_port_n_GPIO_port_A 0b00 -#define GPIOx_to_port_n_GPIO_port_C 0b10 -#define GPIOx_to_port_n_GPIO_port_D 0b11 +#define GPIOx_to_port_n2(GPIOx) GPIOx_to_port_n_##GPIOx +#define GPIOx_to_port_n(GPIOx) GPIOx_to_port_n2(GPIOx) +#define GPIOx_to_port_n_GPIO_port_A 0b00 +#define GPIOx_to_port_n_GPIO_port_C 0b10 +#define GPIOx_to_port_n_GPIO_port_D 0b11 -#define GPIO_port_n_to_GPIOx2(GPIO_port_n) GPIO_port_n_to_GPIOx_##GPIO_port_n -#define GPIO_port_n_to_GPIOx(GPIO_port_n) GPIO_port_n_to_GPIOx2(GPIO_port_n) -#define GPIO_port_n_to_GPIOx_GPIO_port_A GPIOA -#define GPIO_port_n_to_GPIOx_GPIO_port_C GPIOC -#define GPIO_port_n_to_GPIOx_GPIO_port_D GPIOD +#define GPIO_port_n_to_GPIOx2(GPIO_port_n) GPIO_port_n_to_GPIOx_##GPIO_port_n +#define GPIO_port_n_to_GPIOx(GPIO_port_n) GPIO_port_n_to_GPIOx2(GPIO_port_n) +#define GPIO_port_n_to_GPIOx_GPIO_port_A GPIOA +#define GPIO_port_n_to_GPIOx_GPIO_port_C GPIOC +#define GPIO_port_n_to_GPIOx_GPIO_port_D GPIOD -#define GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph_##GPIO_port_n -#define GPIO_port_n_to_RCC_APB2Periph(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) -#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_A RCC_APB2Periph_GPIOA -#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_C RCC_APB2Periph_GPIOC -#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_D RCC_APB2Periph_GPIOD +#define GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph_##GPIO_port_n +#define GPIO_port_n_to_RCC_APB2Periph(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) +#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_A RCC_APB2Periph_GPIOA +#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_C RCC_APB2Periph_GPIOC +#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_D RCC_APB2Periph_GPIOD -#define GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG_##GPIO_pinMode(GPIO_Speed) -#define GPIO_pinMode_to_CFG(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_floating(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_FLOATING) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullUp(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullDown(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_analog(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_ANALOG) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPull(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrain(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_OD) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPullMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP_AF) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrainMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_IN_ANALOG) +#define GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG_##GPIO_pinMode(GPIO_Speed) +#define GPIO_pinMode_to_CFG(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_floating(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_FLOATING) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullUp(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullDown(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_analog(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_ANALOG) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPull(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrain(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_OD) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPullMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP_AF) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrainMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_IN_ANALOG) -#define GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD_##GPIO_pinMode(GPIOv) -#define GPIO_pinMode_set_PUPD(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) +#define GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD_##GPIO_pinMode(GPIOv) +#define GPIO_pinMode_set_PUPD(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_floating(GPIOv) -#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) -#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (GPIOv_to_PIN(GPIOv) + 16)) +#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) +#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (GPIOv_to_PIN(GPIOv) + 16)) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_analog(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_pushPull(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_openDrain(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_pushPullMux(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_openDrainMux(GPIOv) -#define GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD_##GPIO_pinMode(GPIO_port_n) -#define GPIO_port_pinMode_set_PUPD(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) +#define GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD_##GPIO_pinMode(GPIO_port_n) +#define GPIO_port_pinMode_set_PUPD(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_floating(GPIO_port_n) -#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b11111111 -#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b00000000 +#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b11111111 +#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b00000000 #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_analog(GPIO_port_n) #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_O_pushPull(GPIO_port_n) #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_O_openDrain(GPIO_port_n) @@ -287,91 +280,74 @@ static inline void GPIO_tim2_init(); #endif #if !defined(GPIO_timer_prescaler) -#define GPIO_timer_prescaler TIM_CKD_DIV2 // APB_CLOCK / 1024 / 2 = 23.4kHz +#define GPIO_timer_prescaler TIM_CKD_DIV2 // APB_CLOCK / 1024 / 2 = 23.4kHz #endif -//######## define requirements / maintenance defines - - - -//######## small function definitions, static inline +// ######## define requirements / maintenance defines +// ######## small function definitions, static inline #undef GPIO_port_enable #define GPIO_port_enable(GPIO_port_n) RCC->APB2PCENR |= GPIO_port_n_to_RCC_APB2Periph(GPIO_port_n); -#define GPIO_port_pinMode(GPIO_port_n, pinMode, GPIO_Speed) ({ \ - GPIO_port_n_to_GPIOx(GPIO_port_n)->CFGLR = (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 0)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 1)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 2)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 3)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 4)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 5)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 6)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 7)); \ - GPIO_port_pinMode_set_PUPD(pinMode, GPIO_port_n); \ +#define GPIO_port_pinMode(GPIO_port_n, pinMode, GPIO_Speed) ({ \ + GPIO_port_n_to_GPIOx(GPIO_port_n)->CFGLR = (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 0)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 1)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 2)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 3)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 4)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 5)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 6)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 7)); \ + GPIO_port_pinMode_set_PUPD(pinMode, GPIO_port_n); \ }) #undef GPIO_port_digitalWrite -#define GPIO_port_digitalWrite(GPIO_port_n, byte) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = byte +#define GPIO_port_digitalWrite(GPIO_port_n, byte) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = byte #undef GPIO_port_digitalRead -#define GPIO_port_digitalRead(GPIO_port_n) (GPIO_port_n_to_GPIOx(GPIO_port_n)->INDR & 0b11111111) +#define GPIO_port_digitalRead(GPIO_port_n) (GPIO_port_n_to_GPIOx(GPIO_port_n)->INDR & 0b11111111) #undef GPIO_pinMode -#define GPIO_pinMode(GPIOv, pinMode, GPIO_Speed) ({ \ - GPIOv_to_GPIObase(GPIOv)->CFGLR &= ~(0b1111 << (4 * GPIOv_to_PIN(GPIOv))); \ - GPIOv_to_GPIObase(GPIOv)->CFGLR |= (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * GPIOv_to_PIN(GPIOv))); \ - GPIO_pinMode_set_PUPD(pinMode, GPIOv); \ +#define GPIO_pinMode(GPIOv, pinMode, GPIO_Speed) ({ \ + GPIOv_to_GPIObase(GPIOv)->CFGLR &= ~(0b1111 << (4 * GPIOv_to_PIN(GPIOv))); \ + GPIOv_to_GPIObase(GPIOv)->CFGLR |= (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * GPIOv_to_PIN(GPIOv))); \ + GPIO_pinMode_set_PUPD(pinMode, GPIOv); \ }) #undef GPIO_digitalWrite_hi -#define GPIO_digitalWrite_hi(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) +#define GPIO_digitalWrite_hi(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) #undef GPIO_digitalWrite_lo -#define GPIO_digitalWrite_lo(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (16 + GPIOv_to_PIN(GPIOv))) +#define GPIO_digitalWrite_lo(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (16 + GPIOv_to_PIN(GPIOv))) #undef GPIO_digitalWrite -#define GPIO_digitalWrite(GPIOv, lowhigh) GPIO_digitalWrite_##lowhigh(GPIOv) -#define GPIO_digitalWrite_low(GPIOv) GPIO_digitalWrite_lo(GPIOv) -#define GPIO_digitalWrite_0(GPIOv) GPIO_digitalWrite_lo(GPIOv) -#define GPIO_digitalWrite_high(GPIOv) GPIO_digitalWrite_hi(GPIOv) -#define GPIO_digitalWrite_1(GPIOv) GPIO_digitalWrite_hi(GPIOv) +#define GPIO_digitalWrite(GPIOv, lowhigh) GPIO_digitalWrite_##lowhigh(GPIOv) +#define GPIO_digitalWrite_low(GPIOv) GPIO_digitalWrite_lo(GPIOv) +#define GPIO_digitalWrite_0(GPIOv) GPIO_digitalWrite_lo(GPIOv) +#define GPIO_digitalWrite_high(GPIOv) GPIO_digitalWrite_hi(GPIOv) +#define GPIO_digitalWrite_1(GPIOv) GPIO_digitalWrite_hi(GPIOv) #undef GPIO_digitalWrite_branching -#define GPIO_digitalWrite_branching(GPIOv, lowhigh) (lowhigh ? GPIO_digitalWrite_hi(GPIOv) : GPIO_digitalWrite_lo(GPIOv)) +#define GPIO_digitalWrite_branching(GPIOv, lowhigh) (lowhigh ? GPIO_digitalWrite_hi(GPIOv) : GPIO_digitalWrite_lo(GPIOv)) #undef GPIO_digitalRead -#define GPIO_digitalRead(GPIOv) ((GPIOv_to_GPIObase(GPIOv)->INDR >> GPIOv_to_PIN(GPIOv)) & 0b1) +#define GPIO_digitalRead(GPIOv) ((GPIOv_to_GPIObase(GPIOv)->INDR >> GPIOv_to_PIN(GPIOv)) & 0b1) #undef GPIO_ADC_set_sampletime // 0:7 => 3/9/15/30/43/57/73/241 cycles -#define GPIO_ADC_set_sampletime(GPIO_analog_input, GPIO_ADC_sampletime) ({ \ - ADC1->SAMPTR2 &= ~(0b111) << (3 * GPIO_analog_input); \ - ADC1->SAMPTR2 |= GPIO_ADC_sampletime << (3 * GPIO_analog_input); \ +#define GPIO_ADC_set_sampletime(GPIO_analog_input, GPIO_ADC_sampletime) ({ \ + ADC1->SAMPTR2 &= ~(0b111) << (3 * GPIO_analog_input); \ + ADC1->SAMPTR2 |= GPIO_ADC_sampletime << (3 * GPIO_analog_input); \ }) #undef GPIO_ADC_set_sampletimes_all -#define GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime) ({ \ - ADC1->SAMPTR2 &= 0; \ - ADC1->SAMPTR2 |= \ - GPIO_ADC_sampletime << (0 * 3) \ - | GPIO_ADC_sampletime << (1 * 3) \ - | GPIO_ADC_sampletime << (2 * 3) \ - | GPIO_ADC_sampletime << (3 * 3) \ - | GPIO_ADC_sampletime << (4 * 3) \ - | GPIO_ADC_sampletime << (5 * 3) \ - | GPIO_ADC_sampletime << (6 * 3) \ - | GPIO_ADC_sampletime << (7 * 3) \ - | GPIO_ADC_sampletime << (8 * 3) \ - | GPIO_ADC_sampletime << (9 * 3); \ - ADC1->SAMPTR1 &= 0; \ - ADC1->SAMPTR1 |= \ - GPIO_ADC_sampletime << (0 * 3) \ - | GPIO_ADC_sampletime << (1 * 3) \ - | GPIO_ADC_sampletime << (2 * 3) \ - | GPIO_ADC_sampletime << (3 * 3) \ - | GPIO_ADC_sampletime << (4 * 3) \ - | GPIO_ADC_sampletime << (5 * 3); \ +#define GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime) ({ \ + ADC1->SAMPTR2 &= 0; \ + ADC1->SAMPTR2 |= \ + GPIO_ADC_sampletime << (0 * 3) | GPIO_ADC_sampletime << (1 * 3) | GPIO_ADC_sampletime << (2 * 3) | GPIO_ADC_sampletime << (3 * 3) | GPIO_ADC_sampletime << (4 * 3) | GPIO_ADC_sampletime << (5 * 3) | GPIO_ADC_sampletime << (6 * 3) | GPIO_ADC_sampletime << (7 * 3) | GPIO_ADC_sampletime << (8 * 3) | GPIO_ADC_sampletime << (9 * 3); \ + ADC1->SAMPTR1 &= 0; \ + ADC1->SAMPTR1 |= \ + GPIO_ADC_sampletime << (0 * 3) | GPIO_ADC_sampletime << (1 * 3) | GPIO_ADC_sampletime << (2 * 3) | GPIO_ADC_sampletime << (3 * 3) | GPIO_ADC_sampletime << (4 * 3) | GPIO_ADC_sampletime << (5 * 3); \ }) #undef GPIO_ADC_set_power @@ -381,133 +357,137 @@ static inline void GPIO_tim2_init(); #define GPIO_ADC_set_power_0 ADC1->CTLR2 &= ~(ADC_ADON) #undef GPIO_ADC_calibrate -#define GPIO_ADC_calibrate() ({ \ - ADC1->CTLR2 |= ADC_RSTCAL; \ - while(ADC1->CTLR2 & ADC_RSTCAL); \ - ADC1->CTLR2 |= ADC_CAL; \ - while(ADC1->CTLR2 & ADC_CAL); \ +#define GPIO_ADC_calibrate() ({ \ + ADC1->CTLR2 |= ADC_RSTCAL; \ + while (ADC1->CTLR2 & ADC_RSTCAL) \ + ; \ + ADC1->CTLR2 |= ADC_CAL; \ + while (ADC1->CTLR2 & ADC_CAL) \ + ; \ }) // large but will likely only ever be called once -static inline void GPIO_ADCinit() { - // select ADC clock source - // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide by 2 - RCC->CFGR0 &= ~(0x1F<<11); +static inline void GPIO_ADCinit() +{ + // select ADC clock source + // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide by 2 + RCC->CFGR0 &= ~(0x1F << 11); - // enable clock to the ADC - RCC->APB2PCENR |= RCC_APB2Periph_ADC1; + // enable clock to the ADC + RCC->APB2PCENR |= RCC_APB2Periph_ADC1; - // Reset the ADC to init all regs - RCC->APB2PRSTR |= RCC_APB2Periph_ADC1; - RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1; + // Reset the ADC to init all regs + RCC->APB2PRSTR |= RCC_APB2Periph_ADC1; + RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1; - // set sampling time for all inputs to 241 cycles - GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime); + // set sampling time for all inputs to 241 cycles + GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime); - // set trigger to software - ADC1->CTLR2 |= ADC_EXTSEL; + // set trigger to software + ADC1->CTLR2 |= ADC_EXTSEL; - // pre-clear conversion queue - ADC1->RSQR1 = 0; - ADC1->RSQR2 = 0; - ADC1->RSQR3 = 0; + // pre-clear conversion queue + ADC1->RSQR1 = 0; + ADC1->RSQR2 = 0; + ADC1->RSQR3 = 0; - // power the ADC - GPIO_ADC_set_power(1); - GPIO_ADC_calibrate(); + // power the ADC + GPIO_ADC_set_power(1); + GPIO_ADC_calibrate(); } -static inline uint16_t GPIO_analogRead(enum GPIO_analog_inputs input) { - // set mux to selected input - ADC1->RSQR3 = input; - // allow everything to precharge - Delay_Us(GPIO_ADC_MUX_DELAY); - // start sw conversion (auto clears) - ADC1->CTLR2 |= ADC_SWSTART; - // wait for conversion complete - while(!(ADC1->STATR & ADC_EOC)) {} - // get result - return ADC1->RDATAR; +static inline uint16_t GPIO_analogRead(enum GPIO_analog_inputs input) +{ + // set mux to selected input + ADC1->RSQR3 = input; + // allow everything to precharge + Delay_Us(GPIO_ADC_MUX_DELAY); + // start sw conversion (auto clears) + ADC1->CTLR2 |= ADC_SWSTART; + // wait for conversion complete + while (!(ADC1->STATR & ADC_EOC)) {} + // get result + return ADC1->RDATAR; } - - #undef GPIO_tim1_map -#define GPIO_tim1_map(GPIO_tim1_output_set) ({ \ - RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ - AFIO->PCFR1 |= ((GPIO_tim1_output_set & 0b11) << 6); \ +#define GPIO_tim1_map(GPIO_tim1_output_set) ({ \ + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ + AFIO->PCFR1 |= ((GPIO_tim1_output_set & 0b11) << 6); \ }) #undef GPIO_tim2_map -#define GPIO_tim2_map(GPIO_tim2_output_set) ({ \ - RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ - AFIO->PCFR1 |= ((GPIO_tim2_output_set & 0b11) << 8); \ +#define GPIO_tim2_map(GPIO_tim2_output_set) ({ \ + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ + AFIO->PCFR1 |= ((GPIO_tim2_output_set & 0b11) << 8); \ }) -static inline void GPIO_tim1_init() { - // enable TIM1 - RCC->APB2PCENR |= RCC_APB2Periph_TIM1; - // reset TIM1 to init all regs - RCC->APB2PRSTR |= RCC_APB2Periph_TIM1; - RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1; - // SMCFGR: default clk input is CK_INT - // set clock prescaler divider - TIM1->PSC = GPIO_timer_prescaler; - // set PWM total cycle width - TIM1->ATRLR = GPIO_timer_resolution; - // CTLR1: default is up, events generated, edge align - // enable auto-reload of preload - TIM1->CTLR1 |= TIM_ARPE; - // initialize counter - TIM1->SWEVGR |= TIM_UG; - // disengage brake - TIM1->BDTR |= TIM_MOE; - // Enable TIM1 - TIM1->CTLR1 |= TIM_CEN; +static inline void GPIO_tim1_init() +{ + // enable TIM1 + RCC->APB2PCENR |= RCC_APB2Periph_TIM1; + // reset TIM1 to init all regs + RCC->APB2PRSTR |= RCC_APB2Periph_TIM1; + RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1; + // SMCFGR: default clk input is CK_INT + // set clock prescaler divider + TIM1->PSC = GPIO_timer_prescaler; + // set PWM total cycle width + TIM1->ATRLR = GPIO_timer_resolution; + // CTLR1: default is up, events generated, edge align + // enable auto-reload of preload + TIM1->CTLR1 |= TIM_ARPE; + // initialize counter + TIM1->SWEVGR |= TIM_UG; + // disengage brake + TIM1->BDTR |= TIM_MOE; + // Enable TIM1 + TIM1->CTLR1 |= TIM_CEN; } -static inline void GPIO_tim2_init() { - // enable TIM2 - RCC->APB1PCENR |= RCC_APB1Periph_TIM2; - // reset TIM2 to init all regs - RCC->APB1PRSTR |= RCC_APB1Periph_TIM2; - RCC->APB1PRSTR &= ~RCC_APB1Periph_TIM2; - // SMCFGR: default clk input is CK_INT - // set clock prescaler divider - TIM2->PSC = GPIO_timer_prescaler; - // set PWM total cycle width - TIM2->ATRLR = GPIO_timer_resolution; - // CTLR1: default is up, events generated, edge align - // enable auto-reload of preload - TIM2->CTLR1 |= TIM_ARPE; - // initialize counter - TIM2->SWEVGR |= TIM_UG; - // Enable TIM2 - TIM2->CTLR1 |= TIM_CEN; +static inline void GPIO_tim2_init() +{ + // enable TIM2 + RCC->APB1PCENR |= RCC_APB1Periph_TIM2; + // reset TIM2 to init all regs + RCC->APB1PRSTR |= RCC_APB1Periph_TIM2; + RCC->APB1PRSTR &= ~RCC_APB1Periph_TIM2; + // SMCFGR: default clk input is CK_INT + // set clock prescaler divider + TIM2->PSC = GPIO_timer_prescaler; + // set PWM total cycle width + TIM2->ATRLR = GPIO_timer_resolution; + // CTLR1: default is up, events generated, edge align + // enable auto-reload of preload + TIM2->CTLR1 |= TIM_ARPE; + // initialize counter + TIM2->SWEVGR |= TIM_UG; + // Enable TIM2 + TIM2->CTLR1 |= TIM_CEN; } -#define GPIO_timer_channel_set2(timer, channel) GPIO_timer_channel_set_##channel(timer) -#define GPIO_timer_channel_set(timer, channel) GPIO_timer_channel_set2(timer, channel) -#define GPIO_timer_channel_set_1(timer) timer->CHCTLR1 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) -#define GPIO_timer_channel_set_2(timer) timer->CHCTLR1 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) -#define GPIO_timer_channel_set_3(timer) timer->CHCTLR2 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) -#define GPIO_timer_channel_set_4(timer) timer->CHCTLR2 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) +#define GPIO_timer_channel_set2(timer, channel) GPIO_timer_channel_set_##channel(timer) +#define GPIO_timer_channel_set(timer, channel) GPIO_timer_channel_set2(timer, channel) +#define GPIO_timer_channel_set_1(timer) timer->CHCTLR1 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) +#define GPIO_timer_channel_set_2(timer) timer->CHCTLR1 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) +#define GPIO_timer_channel_set_3(timer) timer->CHCTLR2 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) +#define GPIO_timer_channel_set_4(timer) timer->CHCTLR2 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) #undef GPIO_tim1_enableCH -#define GPIO_tim1_enableCH(channel) ({ \ - GPIO_timer_channel_set(TIM1, channel); \ - TIM1->CCER |= (TIM_OutputState_Enable) << (4 * (channel - 1)); \ +#define GPIO_tim1_enableCH(channel) ({ \ + GPIO_timer_channel_set(TIM1, channel); \ + TIM1->CCER |= (TIM_OutputState_Enable) << (4 * (channel - 1)); \ }) #undef GPIO_tim2_enableCH -#define GPIO_tim2_enableCH(channel) ({ \ - GPIO_timer_channel_set(TIM2, channel); \ - TIM2->CCER |= (TIM_OutputState_Enable ) << (4 * (channel - 1)); \ +#define GPIO_tim2_enableCH(channel) ({ \ + GPIO_timer_channel_set(TIM2, channel); \ + TIM2->CCER |= (TIM_OutputState_Enable) << (4 * (channel - 1)); \ }) -#define GPIO_timer_CVR(channel) CONCAT_INDIRECT(CH, CONCAT_INDIRECT(channel, CVR)) +#define GPIO_timer_CVR(channel) CONCAT_INDIRECT(CH, CONCAT_INDIRECT(channel, CVR)) #undef GPIO_tim1_analogWrite -#define GPIO_tim1_analogWrite(channel, value) TIM1->GPIO_timer_CVR(channel) = value; +#define GPIO_tim1_analogWrite(channel, value) TIM1->GPIO_timer_CVR(channel) = value; #undef GPIO_tim2_analogWrite -#define GPIO_tim2_analogWrite(channel, value) TIM2->GPIO_timer_CVR(channel) = value; +#define GPIO_tim2_analogWrite(channel, value) TIM2->GPIO_timer_CVR(channel) = value; #endif // CH32V003_GPIO_BR_H diff --git a/src/extralibs/ch32v003_SPI.h b/src/extralibs/ch32v003_SPI.h index 6fcb867..cbca66b 100644 --- a/src/extralibs/ch32v003_SPI.h +++ b/src/extralibs/ch32v003_SPI.h @@ -1,15 +1,15 @@ -//######## necessities +// ######## necessities // include guards #ifndef CH32V003_SPI_H #define CH32V003_SPI_H // includes -#include //uintN_t support #include "ch32fun.h" +#include //uintN_t support #ifndef APB_CLOCK - #define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK +#define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK #endif /*######## library usage and configuration @@ -20,7 +20,7 @@ SYSTEM_CORE_CLOCK and APB_CLOCK should be defined already as APB_CLOCK is used b #ifndef APB_CLOCK - #define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK + #define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK #endif to enable using the functions of this library: @@ -47,10 +47,8 @@ then pick the desired setting of each group: #define CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL // toggle manually! */ - - -//######## function overview (declarations): use these! -// initialize and configure the SPI peripheral +// ######## function overview (declarations): use these! +// initialize and configure the SPI peripheral static inline void SPI_init(); // establish / end a connection to the SPI device @@ -67,14 +65,14 @@ static inline void SPI_NSS_software_high(); // read / write the SPI device // these commands are raw, you'll have to consider all other steps in SPI_transfer! -static inline uint8_t SPI_read_8(); +static inline uint8_t SPI_read_8(); static inline uint16_t SPI_read_16(); -static inline void SPI_write_8(uint8_t data); -static inline void SPI_write_16(uint16_t data); +static inline void SPI_write_8(uint8_t data); +static inline void SPI_write_16(uint16_t data); // send a command and get a response from the SPI device // you'll use this for most devices -static inline uint8_t SPI_transfer_8(uint8_t data); +static inline uint8_t SPI_transfer_8(uint8_t data); static inline uint16_t SPI_transfer_16(uint16_t data); // SPI peripheral power enable / disable (default off, init() automatically enables) @@ -87,31 +85,25 @@ static inline void SPI_poweron(); static inline void kill_interrrupts(); static inline void restore_interrupts(); - - -//######## internal function declarations -static inline void SPI_wait_TX_complete(); +// ######## internal function declarations +static inline void SPI_wait_TX_complete(); static inline uint8_t SPI_is_RX_empty(); -static inline void SPI_wait_RX_available(); +static inline void SPI_wait_RX_available(); - - -//######## internal variables +// ######## internal variables static uint16_t EXT1_INTENR_backup; - - -//######## preprocessor macros -// min and max helper macros -#define MIN(a,b) (((a)<(b))?(a):(b)) -#define MAX(a,b) (((a)>(b))?(a):(b)) +// ######## preprocessor macros +// min and max helper macros +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) // stringify for displaying what #defines evaluated to at preprocessor stage #define VALUE_TO_STRING(x) #x #define VALUE(x) VALUE_TO_STRING(x) -#define VAR_NAME_VALUE(var) #var "=" VALUE(var) +#define VAR_NAME_VALUE(var) #var "=" VALUE(var) -//compile-time log2 +// compile-time log2 #define LOG2(x) ((x) == 0 ? -1 : __builtin_ctz(x)) // compile-time clock prescaler calculation: log2(APB_CLOCK/SPEED_BUS) @@ -120,233 +112,249 @@ static uint16_t EXT1_INTENR_backup; // ensure that CLOCK_PRESCALER_VALUE is within the range of 0..7 _Static_assert(SPI_CLK_PRESCALER >= 0 && SPI_CLK_PRESCALER <= 7, "SPI_CLK_PRESCALER is out of range (0..7). Please set a different SPI bus speed. prescaler = log2(f_CPU/f_SPI)"); -//#pragma message(VAR_NAME_VALUE(SPI_CLK_PRESCALER)) +// #pragma message(VAR_NAME_VALUE(SPI_CLK_PRESCALER)) - - -//######## preprocessor #define requirements +// ######## preprocessor #define requirements #if !defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) && !defined(CH32V003_SPI_DIRECTION_1LINE_TX) - #warning "none of the CH32V003_SPI_DIRECTION_ options were defined!" +#warning "none of the CH32V003_SPI_DIRECTION_ options were defined!" #endif #if defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) && defined(CH32V003_SPI_DIRECTION_1LINE_TX) - #warning "both CH32V003_SPI_DIRECTION_ options were defined!" +#warning "both CH32V003_SPI_DIRECTION_ options were defined!" #endif #if ((defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) > 1 - #warning "more than one of the CH32V003_SPI_CLK_MODE_ options were defined!" + (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) > 1 +#warning "more than one of the CH32V003_SPI_CLK_MODE_ options were defined!" #endif #if ((defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) == 0 - #warning "none of the CH32V003_SPI_CLK_MODE_ options were defined!" + (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) == 0 +#warning "none of the CH32V003_SPI_CLK_MODE_ options were defined!" #endif #if ((defined(CH32V003_SPI_NSS_HARDWARE_PC0) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) > 1 - #warning "more than one of the CH32V003_SPI_NSS_ options were defined!" + (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) > 1 +#warning "more than one of the CH32V003_SPI_NSS_ options were defined!" #endif #if ((defined(CH32V003_SPI_NSS_HARDWARE_PC0) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) == 0 - #warning "none of the CH32V003_SPI_NSS_ options were defined!" + (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) == 0 +#warning "none of the CH32V003_SPI_NSS_ options were defined!" #endif +// ######## small function definitions, static inline +static inline void SPI_init() +{ + SPI_poweron(); + // reset control register + SPI1->CTLR1 = 0; -//######## small function definitions, static inline -static inline void SPI_init() { - SPI_poweron(); - - // reset control register - SPI1->CTLR1 = 0; + // set prescaler + SPI1->CTLR1 |= SPI_CTLR1_BR & (SPI_CLK_PRESCALER << 3); - // set prescaler - SPI1->CTLR1 |= SPI_CTLR1_BR & (SPI_CLK_PRESCALER<<3); +// set clock polarity and phase +#if defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) + SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_1Edge); +#elif defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) + SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_2Edge); +#elif defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) + SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_1Edge); +#elif defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) + SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_2Edge); +#endif - // set clock polarity and phase - #if defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) - SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_1Edge); - #elif defined (CH32V003_SPI_CLK_MODE_POL0_PHA1) - SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_2Edge); - #elif defined (CH32V003_SPI_CLK_MODE_POL1_PHA0) - SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_1Edge); - #elif defined (CH32V003_SPI_CLK_MODE_POL1_PHA1) - SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_2Edge); - #endif - - // configure NSS pin, master mode - #if defined(CH32V003_SPI_NSS_HARDWARE_PC0) - // _NSS (negative slave select) on PC0, 10MHz Output, alt func, push-pull1 - SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode - GPIOC->CFGLR &= ~(0xf<<(4*0)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*0); - AFIO->PCFR1 |= GPIO_Remap_SPI1; // remap NSS (C1) to _NSS (C0) - SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high - #elif defined(CH32V003_SPI_NSS_HARDWARE_PC1) - // NSS (negative slave select) on PC1, 10MHz Output, alt func, push-pull1 - SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode - GPIOC->CFGLR &= ~(0xf<<(4*1)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*1); - SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high - #elif defined(CH32V003_SPI_NSS_SOFTWARE_PC3) - SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode - GPIOC->CFGLR &= ~(0xf<<(4*3)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*3); - #elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode - GPIOC->CFGLR &= ~(0xf<<(4*4)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*4); - #elif defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) - SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode - #endif +// configure NSS pin, master mode +#if defined(CH32V003_SPI_NSS_HARDWARE_PC0) + // _NSS (negative slave select) on PC0, 10MHz Output, alt func, push-pull1 + SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode + GPIOC->CFGLR &= ~(0xf << (4 * 0)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 0); + AFIO->PCFR1 |= GPIO_Remap_SPI1; // remap NSS (C1) to _NSS (C0) + SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high +#elif defined(CH32V003_SPI_NSS_HARDWARE_PC1) + // NSS (negative slave select) on PC1, 10MHz Output, alt func, push-pull1 + SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode + GPIOC->CFGLR &= ~(0xf << (4 * 1)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 1); + SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high +#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC3) + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode + GPIOC->CFGLR &= ~(0xf << (4 * 3)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 3); +#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode + GPIOC->CFGLR &= ~(0xf << (4 * 4)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 4); +#elif defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode +#endif - // SCK on PC5, 10MHz Output, alt func, push-pull - GPIOC->CFGLR &= ~(0xf<<(4*5)); - GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF)<<(4*5); + // SCK on PC5, 10MHz Output, alt func, push-pull + GPIOC->CFGLR &= ~(0xf << (4 * 5)); + GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5); - // CH32V003 is master - SPI1->CTLR1 |= SPI_Mode_Master; - - // set data direction and configure data pins - #if defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) - SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex; + // CH32V003 is master + SPI1->CTLR1 |= SPI_Mode_Master; - // MOSI on PC6, 10MHz Output, alt func, push-pull - GPIOC->CFGLR &= ~(0xf<<(4*6)); - GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF)<<(4*6); - - // MISO on PC7, 10MHz input, floating - GPIOC->CFGLR &= ~(0xf<<(4*7)); - GPIOC->CFGLR |= GPIO_CNF_IN_FLOATING<<(4*7); - #elif defined(CH32V003_SPI_DIRECTION_1LINE_TX) - SPI1->CTLR1 |= SPI_Direction_1Line_Tx; +// set data direction and configure data pins +#if defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) + SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex; - // MOSI on PC6, 10MHz Output, alt func, push-pull - GPIOC->CFGLR &= ~(0xf<<(4*6)); - GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF)<<(4*6); - #endif + // MOSI on PC6, 10MHz Output, alt func, push-pull + GPIOC->CFGLR &= ~(0xf << (4 * 6)); + GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 6); + + // MISO on PC7, 10MHz input, floating + GPIOC->CFGLR &= ~(0xf << (4 * 7)); + GPIOC->CFGLR |= GPIO_CNF_IN_FLOATING << (4 * 7); +#elif defined(CH32V003_SPI_DIRECTION_1LINE_TX) + SPI1->CTLR1 |= SPI_Direction_1Line_Tx; + + // MOSI on PC6, 10MHz Output, alt func, push-pull + GPIOC->CFGLR &= ~(0xf << (4 * 6)); + GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 6); +#endif } -static inline void SPI_begin_8() { - SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // DFF 16bit data-length enable, writable only when SPE is 0 - SPI1->CTLR1 |= SPI_CTLR1_SPE; +static inline void SPI_begin_8() +{ + SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // DFF 16bit data-length enable, writable only when SPE is 0 + SPI1->CTLR1 |= SPI_CTLR1_SPE; } -static inline void SPI_begin_16() { - SPI1->CTLR1 |= SPI_CTLR1_DFF; // DFF 16bit data-length enable, writable only when SPE is 0 - SPI1->CTLR1 |= SPI_CTLR1_SPE; +static inline void SPI_begin_16() +{ + SPI1->CTLR1 |= SPI_CTLR1_DFF; // DFF 16bit data-length enable, writable only when SPE is 0 + SPI1->CTLR1 |= SPI_CTLR1_SPE; } -static inline void SPI_end() { - SPI1->CTLR1 &= ~(SPI_CTLR1_SPE); +static inline void SPI_end() +{ + SPI1->CTLR1 &= ~(SPI_CTLR1_SPE); } #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) -static inline void SPI_NSS_software_high() { - GPIOC->BSHR = (1<<3); +static inline void SPI_NSS_software_high() +{ + GPIOC->BSHR = (1 << 3); } -static inline void SPI_NSS_software_low() { - GPIOC->BSHR = (1<<(16+3)); +static inline void SPI_NSS_software_low() +{ + GPIOC->BSHR = (1 << (16 + 3)); } -#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) -static inline void SPI_NSS_software_high() { - GPIOC->BSHR = (1<<4); +#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) +static inline void SPI_NSS_software_high() +{ + GPIOC->BSHR = (1 << 4); } -static inline void SPI_NSS_software_low() { - GPIOC->BSHR = (1<<(16+4)); +static inline void SPI_NSS_software_low() +{ + GPIOC->BSHR = (1 << (16 + 4)); } #endif -static inline uint8_t SPI_read_8() { - return SPI1->DATAR; +static inline uint8_t SPI_read_8() +{ + return SPI1->DATAR; } -static inline uint16_t SPI_read_16() { - return SPI1->DATAR; +static inline uint16_t SPI_read_16() +{ + return SPI1->DATAR; } -static inline void SPI_write_8(uint8_t data) { - SPI1->DATAR = data; +static inline void SPI_write_8(uint8_t data) +{ + SPI1->DATAR = data; } -static inline void SPI_write_16(uint16_t data) { - SPI1->DATAR = data; +static inline void SPI_write_16(uint16_t data) +{ + SPI1->DATAR = data; } -static inline uint8_t SPI_transfer_8(uint8_t data) { - #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_high(); - #endif - SPI_write_8(data); - SPI_wait_TX_complete(); - asm volatile("nop"); - SPI_wait_RX_available(); - #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_low(); - #endif - return SPI_read_8(); +static inline uint8_t SPI_transfer_8(uint8_t data) +{ +#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_high(); +#endif + SPI_write_8(data); + SPI_wait_TX_complete(); + asm volatile("nop"); + SPI_wait_RX_available(); +#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_low(); +#endif + return SPI_read_8(); } -static inline uint16_t SPI_transfer_16(uint16_t data) { - #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_high(); - #endif - SPI_write_16(data); - SPI_wait_TX_complete(); - asm volatile("nop"); - SPI_wait_RX_available(); - #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_low(); - #endif - return SPI_read_16(); +static inline uint16_t SPI_transfer_16(uint16_t data) +{ +#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_high(); +#endif + SPI_write_16(data); + SPI_wait_TX_complete(); + asm volatile("nop"); + SPI_wait_RX_available(); +#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_low(); +#endif + return SPI_read_16(); } -static inline void SPI_poweroff() { - SPI_end(); - RCC->APB2PCENR &= ~RCC_APB2Periph_SPI1; +static inline void SPI_poweroff() +{ + SPI_end(); + RCC->APB2PCENR &= ~RCC_APB2Periph_SPI1; } -static inline void SPI_poweron() { - RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; +static inline void SPI_poweron() +{ + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; } -static inline void kill_interrrupts() { - EXT1_INTENR_backup = EXTI->INTENR; - // zero the interrupt enable register to disable all interrupts - EXTI->INTENR = 0; +static inline void kill_interrrupts() +{ + EXT1_INTENR_backup = EXTI->INTENR; + // zero the interrupt enable register to disable all interrupts + EXTI->INTENR = 0; } -static inline void restore_interrupts() { - EXTI->INTENR = EXT1_INTENR_backup; +static inline void restore_interrupts() +{ + EXTI->INTENR = EXT1_INTENR_backup; } - - -//######## small internal function definitions, static inline -static inline void SPI_wait_TX_complete() { - while(!(SPI1->STATR & SPI_STATR_TXE)) {} +// ######## small internal function definitions, static inline +static inline void SPI_wait_TX_complete() +{ + while (!(SPI1->STATR & SPI_STATR_TXE)) {} } -static inline uint8_t SPI_is_RX_empty() { - return SPI1->STATR & SPI_STATR_RXNE; +static inline uint8_t SPI_is_RX_empty() +{ + return SPI1->STATR & SPI_STATR_RXNE; } -static inline void SPI_wait_RX_available() { - while(!(SPI1->STATR & SPI_STATR_RXNE)) {} +static inline void SPI_wait_RX_available() +{ + while (!(SPI1->STATR & SPI_STATR_RXNE)) {} } -static inline void SPI_wait_not_busy() { - while((SPI1->STATR & SPI_STATR_BSY) != 0) {} +static inline void SPI_wait_not_busy() +{ + while ((SPI1->STATR & SPI_STATR_BSY) != 0) {} } -static inline void SPI_wait_transmit_finished() { - SPI_wait_TX_complete(); - SPI_wait_not_busy(); +static inline void SPI_wait_transmit_finished() +{ + SPI_wait_TX_complete(); + SPI_wait_not_busy(); } - -//######## implementation block -//#define CH32V003_SPI_IMPLEMENTATION //enable so LSP can give you text colors while working on the implementation block, disable for normal use of the library +// ######## implementation block +// #define CH32V003_SPI_IMPLEMENTATION //enable so LSP can give you text colors while working on the implementation block, disable for normal use of the library #if defined(CH32V003_SPI_IMPLEMENTATION) -//no functions here because I think all of the functions are small enough to static inline +// no functions here because I think all of the functions are small enough to static inline #endif // CH32V003_SPI_IMPLEMENTATION #endif // CH32V003_SPI_H diff --git a/src/extralibs/ch32v003_touch.h b/src/extralibs/ch32v003_touch.h index 825f7e8..44f42e2 100644 --- a/src/extralibs/ch32v003_touch.h +++ b/src/extralibs/ch32v003_touch.h @@ -3,44 +3,42 @@ /** ADC-based Capactive Touch Control. - see cap_touch_adc.c for an example. + see cap_touch_adc.c for an example. - // Enable GPIOD, C and ADC - RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC | RCC_APB2Periph_ADC1; - InitTouchADC(); + // Enable GPIOD, C and ADC + RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC | RCC_APB2Periph_ADC1; + InitTouchADC(); - // Then do this any time you want to read some touches. - sum[0] += ReadTouchPin( GPIOA, 2, 0, iterations ); - sum[1] += ReadTouchPin( GPIOA, 1, 1, iterations ); - sum[2] += ReadTouchPin( GPIOC, 4, 2, iterations ); - sum[3] += ReadTouchPin( GPIOD, 2, 3, iterations ); - sum[4] += ReadTouchPin( GPIOD, 3, 4, iterations ); - sum[5] += ReadTouchPin( GPIOD, 5, 5, iterations ); - sum[6] += ReadTouchPin( GPIOD, 6, 6, iterations ); - sum[7] += ReadTouchPin( GPIOD, 4, 7, iterations ); + // Then do this any time you want to read some touches. + sum[0] += ReadTouchPin( GPIOA, 2, 0, iterations ); + sum[1] += ReadTouchPin( GPIOA, 1, 1, iterations ); + sum[2] += ReadTouchPin( GPIOC, 4, 2, iterations ); + sum[3] += ReadTouchPin( GPIOD, 2, 3, iterations ); + sum[4] += ReadTouchPin( GPIOD, 3, 4, iterations ); + sum[5] += ReadTouchPin( GPIOD, 5, 5, iterations ); + sum[6] += ReadTouchPin( GPIOD, 6, 6, iterations ); + sum[7] += ReadTouchPin( GPIOD, 4, 7, iterations ); */ - - -#define TOUCH_ADC_SAMPLE_TIME 2 // Tricky: Don't change this without a lot of experimentation. +#define TOUCH_ADC_SAMPLE_TIME 2 // Tricky: Don't change this without a lot of experimentation. // Can either be 0 or 1. // If 0: Measurement low and rises high. So more pressed is smaller number. // If 1: Higher number = harder press. Good to pair with TOUCH_FLAT. // If you are doing more prox, use mode 0, otherwise, use mode 1. -#define TOUCH_SLOPE 1 +#define TOUCH_SLOPE 1 // If you set this to 1, it will glitch the line, so it will only read // anything reasonable if the capacitance can overcome that initial spike. // Typically, it seems if you use this you probbly don't need to do // any pre-use calibration. -#define TOUCH_FLAT 0 +#define TOUCH_FLAT 0 // Macro used for force-alingining ADC timing #define FORCEALIGNADC \ - asm volatile( \ - "\n\ + asm volatile( \ + "\n\ .balign 4\n\ andi a2, %[cyccnt], 3\n\ c.slli a2, 1\n\ @@ -50,169 +48,172 @@ jalr a2, 1\n\ .long 0x00010001\n\ .long 0x00010001\n\ - "\ - :: [cyccnt]"r"(SysTick->CNT) : "a1", "a2"\ - ); + " ::[cyccnt] "r"(SysTick->CNT) : "a1", "a2"); - -static void InitTouchADC( ); -void InitTouchADC( ) +static void InitTouchADC(); +void InitTouchADC() { - // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide sys clock by 2 - RCC->CFGR0 &= ~(0x1F<<11); + // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide sys clock by 2 + RCC->CFGR0 &= ~(0x1F << 11); - // Set up single conversion on chl 2 - ADC1->RSQR1 = 0; - ADC1->RSQR2 = 0; + // Set up single conversion on chl 2 + ADC1->RSQR1 = 0; + ADC1->RSQR2 = 0; - // turn on ADC and set rule group to sw trig - ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL; - - // Reset calibration - ADC1->CTLR2 |= ADC_RSTCAL; - while(ADC1->CTLR2 & ADC_RSTCAL); - - // Calibrate - ADC1->CTLR2 |= ADC_CAL; - while(ADC1->CTLR2 & ADC_CAL); + // turn on ADC and set rule group to sw trig + ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL; + + // Reset calibration + ADC1->CTLR2 |= ADC_RSTCAL; + while (ADC1->CTLR2 & ADC_RSTCAL) + ; + + // Calibrate + ADC1->CTLR2 |= ADC_CAL; + while (ADC1->CTLR2 & ADC_CAL) + ; } // Run from RAM to get even more stable timing. // This function call takes about 8.1uS to execute. -static uint32_t ReadTouchPin( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) __attribute__((noinline, section(".srodata"))); -uint32_t ReadTouchPin( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) +static uint32_t ReadTouchPin(GPIO_TypeDef *io, int portpin, int adcno, int iterations) __attribute__((noinline, section(".srodata"))); +uint32_t ReadTouchPin(GPIO_TypeDef *io, int portpin, int adcno, int iterations) { - uint32_t ret = 0; + uint32_t ret = 0; - __disable_irq(); - FORCEALIGNADC - ADC1->RSQR3 = adcno; - ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME<<(3*adcno); - __enable_irq(); + __disable_irq(); + FORCEALIGNADC + ADC1->RSQR3 = adcno; + ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME << (3 * adcno); + __enable_irq(); - uint32_t CFGBASE = io->CFGLR & (~(0xf<<(4*portpin))); - uint32_t CFGFLOAT = ((GPIO_CFGLR_IN_PUPD)<<(4*portpin)) | CFGBASE; - uint32_t CFGDRIVE = (GPIO_CFGLR_OUT_2Mhz_PP)<<(4*portpin) | CFGBASE; - - // If we run multiple times with slightly different wait times, we can - // reduce the impact of the ADC's DNL. + uint32_t CFGBASE = io->CFGLR & (~(0xf << (4 * portpin))); + uint32_t CFGFLOAT = ((GPIO_CFGLR_IN_PUPD) << (4 * portpin)) | CFGBASE; + uint32_t CFGDRIVE = (GPIO_CFGLR_OUT_2Mhz_PP) << (4 * portpin) | CFGBASE; + // If we run multiple times with slightly different wait times, we can + // reduce the impact of the ADC's DNL. #if TOUCH_FLAT == 1 -#define RELEASEIO io->BSHR = 1<<(portpin+16*TOUCH_SLOPE); io->CFGLR = CFGFLOAT; +#define RELEASEIO \ + io->BSHR = 1 << (portpin + 16 * TOUCH_SLOPE); \ + io->CFGLR = CFGFLOAT; #else -#define RELEASEIO io->CFGLR = CFGFLOAT; io->BSHR = 1<<(portpin+16*TOUCH_SLOPE); +#define RELEASEIO \ + io->CFGLR = CFGFLOAT; \ + io->BSHR = 1 << (portpin + 16 * TOUCH_SLOPE); #endif -#define INNER_LOOP( n ) \ - { \ - /* Only lock IRQ for a very narrow window. */ \ - __disable_irq(); \ - FORCEALIGNADC \ - \ - /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ - this We are catching it onthe slope much more effectively. */ \ - ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ - \ - ADD_N_NOPS( n ) \ - \ - RELEASEIO \ - \ - /* Sampling actually starts here, somewhere, so we can let other \ - interrupts run */ \ - __enable_irq(); \ - while(!(ADC1->STATR & ADC_EOC)); \ - io->CFGLR = CFGDRIVE; \ - io->BSHR = 1<<(portpin+(16*(1-TOUCH_SLOPE))); \ - ret += ADC1->RDATAR; \ - } +#define INNER_LOOP(n) \ + { \ + /* Only lock IRQ for a very narrow window. */ \ + __disable_irq(); \ + FORCEALIGNADC \ + \ + /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ + this We are catching it onthe slope much more effectively. */ \ + ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ + \ + ADD_N_NOPS(n) \ + \ + RELEASEIO \ + \ + /* Sampling actually starts here, somewhere, so we can let other \ + interrupts run */ \ + __enable_irq(); \ + while (!(ADC1->STATR & ADC_EOC)) \ + ; \ + io->CFGLR = CFGDRIVE; \ + io->BSHR = 1 << (portpin + (16 * (1 - TOUCH_SLOPE))); \ + ret += ADC1->RDATAR; \ + } - int i; - for( i = 0; i < iterations; i++ ) - { - // Wait a variable amount of time based on loop iteration, in order - // to get a variety of RC points and minimize DNL. + int i; + for (i = 0; i < iterations; i++) + { + // Wait a variable amount of time based on loop iteration, in order + // to get a variety of RC points and minimize DNL. - INNER_LOOP( 0 ); - INNER_LOOP( 2 ); - INNER_LOOP( 4 ); - } + INNER_LOOP(0); + INNER_LOOP(2); + INNER_LOOP(4); + } - return ret; + return ret; } // Run from RAM to get even more stable timing. // This function call takes about 8.1uS to execute. -static uint32_t ReadTouchPinSafe( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) __attribute__((noinline, section(".srodata"))); -uint32_t ReadTouchPinSafe( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) +static uint32_t ReadTouchPinSafe(GPIO_TypeDef *io, int portpin, int adcno, int iterations) __attribute__((noinline, section(".srodata"))); +uint32_t ReadTouchPinSafe(GPIO_TypeDef *io, int portpin, int adcno, int iterations) { - uint32_t ret = 0; + uint32_t ret = 0; - ADC1->RSQR3 = adcno; - ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME<<(3*adcno); + ADC1->RSQR3 = adcno; + ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME << (3 * adcno); - // If we run multiple times with slightly different wait times, we can - // reduce the impact of the ADC's DNL. + // If we run multiple times with slightly different wait times, we can + // reduce the impact of the ADC's DNL. -#define INNER_LOOP_SAFE( n ) \ - { \ - /* Only lock IRQ for a very narrow window. */ \ - __disable_irq(); \ - \ - FORCEALIGNADC \ - \ - /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ - this We are catching it onthe slope much more effectively. */ \ - ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ - \ - ADD_N_NOPS( n ) \ - \ - io->CFGLR = ((GPIO_CFGLR_IN_PUPD)<<(4*portpin)) | (io->CFGLR & (~(0xf<<(4*portpin)))); \ - io->BSHR = 1<<(portpin+16*TOUCH_SLOPE); \ - \ - /* Sampling actually starts here, somewhere, so we can let other \ - interrupts run */ \ - __enable_irq(); \ - while(!(ADC1->STATR & ADC_EOC)); \ - __disable_irq(); \ - io->CFGLR = (GPIO_CFGLR_OUT_2Mhz_PP)<<(4*portpin) | (io->CFGLR & (~(0xf<<(4*portpin)))); \ - __enable_irq(); \ - io->BSHR = 1<<(portpin+(16*(1-TOUCH_SLOPE))); \ - ret += ADC1->RDATAR; \ - } +#define INNER_LOOP_SAFE(n) \ + { \ + /* Only lock IRQ for a very narrow window. */ \ + __disable_irq(); \ + \ + FORCEALIGNADC \ + \ + /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ + this We are catching it onthe slope much more effectively. */ \ + ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ + \ + ADD_N_NOPS(n) \ + \ + io->CFGLR = ((GPIO_CFGLR_IN_PUPD) << (4 * portpin)) | (io->CFGLR & (~(0xf << (4 * portpin)))); \ + io->BSHR = 1 << (portpin + 16 * TOUCH_SLOPE); \ + \ + /* Sampling actually starts here, somewhere, so we can let other \ + interrupts run */ \ + __enable_irq(); \ + while (!(ADC1->STATR & ADC_EOC)) \ + ; \ + __disable_irq(); \ + io->CFGLR = (GPIO_CFGLR_OUT_2Mhz_PP) << (4 * portpin) | (io->CFGLR & (~(0xf << (4 * portpin)))); \ + __enable_irq(); \ + io->BSHR = 1 << (portpin + (16 * (1 - TOUCH_SLOPE))); \ + ret += ADC1->RDATAR; \ + } - int i; - for( i = 0; i < iterations; i++ ) - { - // Wait a variable amount of time based on loop iteration, in order - // to get a variety of RC points and minimize DNL. + int i; + for (i = 0; i < iterations; i++) + { + // Wait a variable amount of time based on loop iteration, in order + // to get a variety of RC points and minimize DNL. - INNER_LOOP_SAFE( 0 ); - INNER_LOOP_SAFE( 2 ); - INNER_LOOP_SAFE( 4 ); - } + INNER_LOOP_SAFE(0); + INNER_LOOP_SAFE(2); + INNER_LOOP_SAFE(4); + } - return ret; + return ret; } - #endif /* * MIT License - * + * * Copyright (c) 2023 Valve Corporation - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -221,4 +222,3 @@ uint32_t ReadTouchPinSafe( GPIO_TypeDef * io, int portpin, int adcno, int iterat * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ - diff --git a/src/extralibs/ch32v307gigabit.h b/src/extralibs/ch32v307gigabit.h index 60ca030..4af9137 100644 --- a/src/extralibs/ch32v307gigabit.h +++ b/src/extralibs/ch32v307gigabit.h @@ -2,7 +2,7 @@ #define _CH32V307GIGABIT_H /* This file is written against the RTL8211E -*/ + */ // #define CH32V307GIGABIT_MCO25 1 // #define CH32V307GIGABIT_PHYADDRESS 0 @@ -34,515 +34,515 @@ // ETH DMA structure definition (From ch32v30x_eth.c typedef struct { - uint32_t volatile Status; /* Status */ - uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ - uint32_t Buffer1Addr; /* Buffer1 address pointer */ - uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ + uint32_t volatile Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ } ETH_DMADESCTypeDef; // You must provide: -void ch32v307ethHandleReconfig( int link, int speed, int duplex ); +void ch32v307ethHandleReconfig(int link, int speed, int duplex); // Return non-zero to suppress OWN return (for if you are still holding onto the buffer) -int ch32v307ethInitHandlePacket( uint8_t * data, int frame_length, ETH_DMADESCTypeDef * dmadesc ); +int ch32v307ethInitHandlePacket(uint8_t *data, int frame_length, ETH_DMADESCTypeDef *dmadesc); -void ch32v307ethInitHandleTXC( void ); +void ch32v307ethInitHandleTXC(void); // This library provides: -static void ch32v307ethGetMacInUC( uint8_t * mac ); -static int ch32v307ethInit( void ); -static int ch32v307ethTransmitStatic(uint8_t * buffer, uint32_t length, int enable_txc); // Does not copy. -static int ch32v307ethTickPhy( void ); +static void ch32v307ethGetMacInUC(uint8_t *mac); +static int ch32v307ethInit(void); +static int ch32v307ethTransmitStatic(uint8_t *buffer, uint32_t length, int enable_txc); // Does not copy. +static int ch32v307ethTickPhy(void); // Data pursuent to ethernet. -uint8_t ch32v307eth_mac[6] = { 0 }; -uint16_t ch32v307eth_phyid = 0; // 0xc916 = RTL8211FS / 0xc915 = RTL8211E-VB -ETH_DMADESCTypeDef ch32v307eth_DMARxDscrTab[CH32V307GIGABIT_RXBUFNB] __attribute__((aligned(4))); // MAC receive descriptor, 4-byte aligned -ETH_DMADESCTypeDef ch32v307eth_DMATxDscrTab[CH32V307GIGABIT_TXBUFNB] __attribute__((aligned(4))); // MAC send descriptor, 4-byte aligned -uint8_t ch32v307eth_MACRxBuf[CH32V307GIGABIT_RXBUFNB*CH32V307GIGABIT_BUFFSIZE] __attribute__((aligned(4))); // MAC receive buffer, 4-byte aligned -ETH_DMADESCTypeDef * pDMARxGet; -ETH_DMADESCTypeDef * pDMATxSet; - +uint8_t ch32v307eth_mac[6] = {0}; +uint16_t ch32v307eth_phyid = 0; // 0xc916 = RTL8211FS / 0xc915 = RTL8211E-VB +ETH_DMADESCTypeDef ch32v307eth_DMARxDscrTab[CH32V307GIGABIT_RXBUFNB] __attribute__((aligned(4))); // MAC receive descriptor, 4-byte aligned +ETH_DMADESCTypeDef ch32v307eth_DMATxDscrTab[CH32V307GIGABIT_TXBUFNB] __attribute__((aligned(4))); // MAC send descriptor, 4-byte aligned +uint8_t ch32v307eth_MACRxBuf[CH32V307GIGABIT_RXBUFNB * CH32V307GIGABIT_BUFFSIZE] __attribute__((aligned(4))); // MAC receive buffer, 4-byte aligned +ETH_DMADESCTypeDef *pDMARxGet; +ETH_DMADESCTypeDef *pDMATxSet; // Internal functions -static int ch32v307ethPHYRegWrite( uint32_t reg, uint32_t val ); -static int ch32v307ethPHYRegAsyncRead( int reg, int * value ); -static int ch32v307ethPHYRegRead( uint32_t reg ); +static int ch32v307ethPHYRegWrite(uint32_t reg, uint32_t val); +static int ch32v307ethPHYRegAsyncRead(int reg, int *value); +static int ch32v307ethPHYRegRead(uint32_t reg); -static int ch32v307ethPHYRegAsyncRead( int reg, int * value ) +static int ch32v307ethPHYRegAsyncRead(int reg, int *value) { - static uint8_t reg_request_count = 0; + static uint8_t reg_request_count = 0; - uint32_t miiar = ETH->MACMIIAR; - if( miiar & ETH_MACMIIAR_MB ) - { - return -1; - } - if( ( ( miiar & ETH_MACMIIAR_MR ) >> 6 ) != reg || reg_request_count < 2 ) - { - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | - ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA - (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | - (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; - reg_request_count++; - return -1; - } - reg_request_count = 0; - *value = ETH->MACMIIDR; - ETH->MACMIIAR |= ETH_MACMIIAR_MR; // Poison register. - return 0; + uint32_t miiar = ETH->MACMIIAR; + if (miiar & ETH_MACMIIAR_MB) + { + return -1; + } + if (((miiar & ETH_MACMIIAR_MR) >> 6) != reg || reg_request_count < 2) + { + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | + ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA + (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | + (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; + reg_request_count++; + return -1; + } + reg_request_count = 0; + *value = ETH->MACMIIDR; + ETH->MACMIIAR |= ETH_MACMIIAR_MR; // Poison register. + return 0; } static int ch32v307ethTickPhy(void) { - int speed, linked, duplex; - const int reg = (ch32v307eth_phyid == 0xc916) ? 0x1a : 0x11; // PHYSR (different on each part) - int miidr; - if( ch32v307ethPHYRegAsyncRead( reg, &miidr ) ) return -1; + int speed, linked, duplex; + const int reg = (ch32v307eth_phyid == 0xc916) ? 0x1a : 0x11; // PHYSR (different on each part) + int miidr; + if (ch32v307ethPHYRegAsyncRead(reg, &miidr)) return -1; - printf( "REG: %02x / %04x / %04x\n", reg, miidr, ch32v307eth_phyid ); + printf("REG: %02x / %04x / %04x\n", reg, miidr, ch32v307eth_phyid); - if( reg == 0x1a ) - { - speed = ((miidr>>4)&3); - linked = ((miidr>>2)&1); - duplex = ((miidr>>3)&1); - } - else - { - speed = ((miidr>>14)&3); - linked = ((miidr>>10)&1); - duplex = ((miidr>>13)&1); - } + if (reg == 0x1a) + { + speed = ((miidr >> 4) & 3); + linked = ((miidr >> 2) & 1); + duplex = ((miidr >> 3) & 1); + } + else + { + speed = ((miidr >> 14) & 3); + linked = ((miidr >> 10) & 1); + duplex = ((miidr >> 13) & 1); + } - printf( "LINK INFO: %d %d %d\n", speed, linked, duplex ); - if( linked ) - { - uint32_t oldmaccr = ETH->MACCR; - uint32_t newmaccr = (oldmaccr & ~( ( 1<<11 ) | (3<<14) ) ) | (speed<<14) | ( duplex<<11); - if( newmaccr != oldmaccr ) - { - ETH->MACCR = newmaccr; - ch32v307ethHandleReconfig( linked, speed, duplex ); - return 1; - } - } - return 0; + printf("LINK INFO: %d %d %d\n", speed, linked, duplex); + if (linked) + { + uint32_t oldmaccr = ETH->MACCR; + uint32_t newmaccr = (oldmaccr & ~((1 << 11) | (3 << 14))) | (speed << 14) | (duplex << 11); + if (newmaccr != oldmaccr) + { + ETH->MACCR = newmaccr; + ch32v307ethHandleReconfig(linked, speed, duplex); + return 1; + } + } + return 0; } - // Based on ETH_WritePHYRegister -static int ch32v307ethPHYRegWrite( uint32_t reg, uint32_t val ) +static int ch32v307ethPHYRegWrite(uint32_t reg, uint32_t val) { - ETH->MACMIIDR = val; - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | - (((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11)) | // ETH_MACMIIAR_PA - (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | - ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; + ETH->MACMIIDR = val; + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | + (((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11)) | // ETH_MACMIIAR_PA + (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | + ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; - uint32_t timeout = 0x100000; - while( ( ETH->MACMIIAR & ETH_MACMIIAR_MB ) && --timeout ); + uint32_t timeout = 0x100000; + while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) && --timeout) + ; - // If timeout = 0, is an error. - return timeout ? 0 : -1; + // If timeout = 0, is an error. + return timeout ? 0 : -1; } -static int ch32v307ethPHYRegRead( uint32_t reg ) +static int ch32v307ethPHYRegRead(uint32_t reg) { - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | - ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA - (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | - (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | + ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA + (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | + (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; - uint32_t timeout = 0x100000; - while( ( ETH->MACMIIAR & ETH_MACMIIAR_MB ) && --timeout ); + uint32_t timeout = 0x100000; + while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) && --timeout) + ; - // If timeout = 0, is an error. - return timeout ? ETH->MACMIIDR : -1; + // If timeout = 0, is an error. + return timeout ? ETH->MACMIIDR : -1; } - -static void ch32v307ethGetMacInUC( uint8_t * mac ) +static void ch32v307ethGetMacInUC(uint8_t *mac) { - // Mac is backwards. - const uint8_t *macaddr = (const uint8_t *)(ROM_CFG_USERADR_ID+5); - for( int i = 0; i < 6; i++ ) - { - mac[i] = *(macaddr--); - } + // Mac is backwards. + const uint8_t *macaddr = (const uint8_t *)(ROM_CFG_USERADR_ID + 5); + for (int i = 0; i < 6; i++) + { + mac[i] = *(macaddr--); + } } -static int ch32v307ethInit( void ) +static int ch32v307ethInit(void) { - int i; + int i; #ifdef CH32V307GIGABIT_PHY_RSTB - funPinMode( CH32V307GIGABIT_PHY_RSTB, GPIO_CFGLR_OUT_50Mhz_PP ); //PHY_RSTB (For reset) - funDigitalWrite( CH32V307GIGABIT_PHY_RSTB, FUN_LOW ); + funPinMode(CH32V307GIGABIT_PHY_RSTB, GPIO_CFGLR_OUT_50Mhz_PP); // PHY_RSTB (For reset) + funDigitalWrite(CH32V307GIGABIT_PHY_RSTB, FUN_LOW); #endif - // Configure strapping. - funPinMode( PA1, GPIO_CFGLR_IN_PUPD ); // GMII_RXD3 - funPinMode( PA0, GPIO_CFGLR_IN_PUPD ); // GMII_RXD2 - funPinMode( PC3, GPIO_CFGLR_IN_PUPD ); // GMII_RXD1 - funPinMode( PC2, GPIO_CFGLR_IN_PUPD ); // GMII_RXD0 - funDigitalWrite( PA1, FUN_HIGH ); - funDigitalWrite( PA0, FUN_HIGH ); - funDigitalWrite( PC3, FUN_HIGH ); // No TX Delay - funDigitalWrite( PC2, FUN_HIGH ); + // Configure strapping. + funPinMode(PA1, GPIO_CFGLR_IN_PUPD); // GMII_RXD3 + funPinMode(PA0, GPIO_CFGLR_IN_PUPD); // GMII_RXD2 + funPinMode(PC3, GPIO_CFGLR_IN_PUPD); // GMII_RXD1 + funPinMode(PC2, GPIO_CFGLR_IN_PUPD); // GMII_RXD0 + funDigitalWrite(PA1, FUN_HIGH); + funDigitalWrite(PA0, FUN_HIGH); + funDigitalWrite(PC3, FUN_HIGH); // No TX Delay + funDigitalWrite(PC2, FUN_HIGH); - // Pull-up MDIO - funPinMode( PD9, GPIO_CFGLR_OUT_50Mhz_PP ); //Pull-up control (DO NOT CHECK IN, ADD RESISTOR) - funDigitalWrite( PD9, FUN_HIGH ); + // Pull-up MDIO + funPinMode(PD9, GPIO_CFGLR_OUT_50Mhz_PP); // Pull-up control (DO NOT CHECK IN, ADD RESISTOR) + funDigitalWrite(PD9, FUN_HIGH); - // Will be required later. - RCC->APB2PCENR |= RCC_APB2Periph_AFIO; + // Will be required later. + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; - // https://cnlohr.github.io/microclockoptimizer/?chipSelect=ch32vx05_7%2Cd8c&HSI=1,8&HSE=0,8&PREDIV2=1,1&PLL2CLK=1,7&PLL2VCO=0,72&PLL3CLK=1,1&PLL3VCO=0,100&PREDIV1SRC=1,0&PREDIV1=1,2&PLLSRC=1,0&PLL=0,4&PLLVCO=1,144&SYSCLK=1,2& - // Clock Tree: - // 8MHz Input - // PREDIV2 = 2 (1 in register) = 4MHz - // PLL2 = 9 (7 in register) = 36MHz / PLL2VCO = 72MHz - // PLL3CLK = 12.5 (1 in register) = 50MHz = 100MHz VCO - // PREDIV1SRC = HSE (1 in register) = 8MHz - // PREDIV1 = 2 (1 in register). - // PLLSRC = PREDIV1 (0 in register) = 4MHz - // PLL = 18 (0 in register) = 72MHz - // PLLVCO = 144MHz - // SYSCLK = PLLVCO = 144MHz - // Use EXT_125M (ETH1G_SRC) + // https://cnlohr.github.io/microclockoptimizer/?chipSelect=ch32vx05_7%2Cd8c&HSI=1,8&HSE=0,8&PREDIV2=1,1&PLL2CLK=1,7&PLL2VCO=0,72&PLL3CLK=1,1&PLL3VCO=0,100&PREDIV1SRC=1,0&PREDIV1=1,2&PLLSRC=1,0&PLL=0,4&PLLVCO=1,144&SYSCLK=1,2& + // Clock Tree: + // 8MHz Input + // PREDIV2 = 2 (1 in register) = 4MHz + // PLL2 = 9 (7 in register) = 36MHz / PLL2VCO = 72MHz + // PLL3CLK = 12.5 (1 in register) = 50MHz = 100MHz VCO + // PREDIV1SRC = HSE (1 in register) = 8MHz + // PREDIV1 = 2 (1 in register). + // PLLSRC = PREDIV1 (0 in register) = 4MHz + // PLL = 18 (0 in register) = 72MHz + // PLLVCO = 144MHz + // SYSCLK = PLLVCO = 144MHz + // Use EXT_125M (ETH1G_SRC) - // Switch processor back to HSI so we don't eat dirt. - RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI; + // Switch processor back to HSI so we don't eat dirt. + RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI; - // Setup clock tree. - RCC->CFGR2 |= - (1<CFGR2 |= + (1 << RCC_PREDIV2_OFFSET) | // PREDIV = /2; Prediv Freq = 4MHz + (1 << RCC_PLL3MUL_OFFSET) | // PLL3 = x12.5 (PLL3 = 50MHz) + (2 << RCC_ETH1GSRC_OFFSET) | // External source for RGMII + (7 << RCC_PLL2MUL_OFFSET) | // PLL2 = x9 (PLL2 = 36MHz) + (1 << RCC_PREDIV1_OFFSET) | // PREDIV1 = /2; Prediv freq = 50MHz + 0; - // Power on PLLs - RCC->CTLR |= RCC_PLL3ON | RCC_PLL2ON; - int timeout; + // Power on PLLs + RCC->CTLR |= RCC_PLL3ON | RCC_PLL2ON; + int timeout; - for( timeout = 10000; timeout > 0; timeout--) if (RCC->CTLR & RCC_PLL3RDY) break; - if( timeout == 0 ) return -5; - for( timeout = 10000; timeout > 0; timeout--) if (RCC->CTLR & RCC_PLL2RDY) break; - if( timeout == 0 ) return -6; + for (timeout = 10000; timeout > 0; timeout--) + if (RCC->CTLR & RCC_PLL3RDY) break; + if (timeout == 0) return -5; + for (timeout = 10000; timeout > 0; timeout--) + if (RCC->CTLR & RCC_PLL2RDY) break; + if (timeout == 0) return -6; - // PLL = x18 (0 in register) - RCC->CFGR0 = ( RCC->CFGR0 & ~(0xf<<18)) | 0; - RCC->CTLR |= RCC_PLLON; + // PLL = x18 (0 in register) + RCC->CFGR0 = (RCC->CFGR0 & ~(0xf << 18)) | 0; + RCC->CTLR |= RCC_PLLON; - for( timeout = 10000; timeout > 0; timeout--) if (RCC->CTLR & RCC_PLLRDY) break; - if( timeout == 0 ) return -7; + for (timeout = 10000; timeout > 0; timeout--) + if (RCC->CTLR & RCC_PLLRDY) break; + if (timeout == 0) return -7; - // Switch to PLL. + // Switch to PLL. #ifdef CH32V307GIGABIT_MCO25 - RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL | (9<<24); // And output clock on PA8 + RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL | (9 << 24); // And output clock on PA8 #else - RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL; + RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL; #endif - // For clock in. - funPinMode( PB1, GPIO_CFGLR_IN_FLOAT ); //GMII_CLK125 + // For clock in. + funPinMode(PB1, GPIO_CFGLR_IN_FLOAT); // GMII_CLK125 - RCC->CFGR2 |= RCC_ETH1G_125M_EN; // Enable 125MHz clock. + RCC->CFGR2 |= RCC_ETH1G_125M_EN; // Enable 125MHz clock. - // Power on and reset. - RCC->AHBPCENR |= RCC_ETHMACEN | RCC_ETHMACTXEN | RCC_ETHMACRXEN; - RCC->AHBRSTR |= RCC_ETHMACRST; - RCC->AHBRSTR &=~RCC_ETHMACRST; + // Power on and reset. + RCC->AHBPCENR |= RCC_ETHMACEN | RCC_ETHMACTXEN | RCC_ETHMACRXEN; + RCC->AHBRSTR |= RCC_ETHMACRST; + RCC->AHBRSTR &= ~RCC_ETHMACRST; - ETH->DMABMR |= ETH_DMABMR_SR; + ETH->DMABMR |= ETH_DMABMR_SR; - // Wait for reset to complete. - for( timeout = 10000; timeout > 0 && (ETH->DMABMR & ETH_DMABMR_SR); timeout-- ) - { - Delay_Us(10); - } + // Wait for reset to complete. + for (timeout = 10000; timeout > 0 && (ETH->DMABMR & ETH_DMABMR_SR); timeout--) + { + Delay_Us(10); + } - // Use RGMII - EXTEN->EXTEN_CTR |= EXTEN_ETH_RGMII_SEL; //EXTEN_ETH_RGMII_SEL; + // Use RGMII + EXTEN->EXTEN_CTR |= EXTEN_ETH_RGMII_SEL; // EXTEN_ETH_RGMII_SEL; - funPinMode( PB13, GPIO_CFGLR_OUT_50Mhz_AF_PP ); //GMII_MDIO - funPinMode( PB12, GPIO_CFGLR_OUT_50Mhz_AF_PP ); //GMII_MDC + funPinMode(PB13, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_MDIO + funPinMode(PB12, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_MDC - // For clock output to Ethernet module. - funPinMode( PA8, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // PHY_CKTAL + // For clock output to Ethernet module. + funPinMode(PA8, GPIO_CFGLR_OUT_50Mhz_AF_PP); // PHY_CKTAL - // Release PHY from reset. + // Release PHY from reset. #ifdef CH32V307GIGABIT_PHY_RSTB - funDigitalWrite( CH32V307GIGABIT_PHY_RSTB, FUN_HIGH ); + funDigitalWrite(CH32V307GIGABIT_PHY_RSTB, FUN_HIGH); #endif - Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 23ms (But only on the RTL8211FS) None is needed on the RTL8211E + Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 23ms (But only on the RTL8211FS) None is needed on the RTL8211E - funPinMode( PB0, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD3 - funPinMode( PC5, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD2 - funPinMode( PC4, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD1 - funPinMode( PA7, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD0 - funPinMode( PA3, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXCTL - funPinMode( PA2, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXC - funPinMode( PA1, GPIO_CFGLR_IN_PUPD ); // GMII_RXD3 - funPinMode( PA0, GPIO_CFGLR_IN_PUPD ); // GMII_RXD2 - funPinMode( PC3, GPIO_CFGLR_IN_PUPD ); // GMII_RXD1 - funPinMode( PC2, GPIO_CFGLR_IN_PUPD ); // GMII_RXD0 - funPinMode( PC1, GPIO_CFGLR_IN_PUPD ); // GMII_RXCTL - funPinMode( PC0, GPIO_CFGLR_IN_FLOAT ); // GMII_RXC + funPinMode(PB0, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD3 + funPinMode(PC5, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD2 + funPinMode(PC4, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD1 + funPinMode(PA7, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD0 + funPinMode(PA3, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXCTL + funPinMode(PA2, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXC + funPinMode(PA1, GPIO_CFGLR_IN_PUPD); // GMII_RXD3 + funPinMode(PA0, GPIO_CFGLR_IN_PUPD); // GMII_RXD2 + funPinMode(PC3, GPIO_CFGLR_IN_PUPD); // GMII_RXD1 + funPinMode(PC2, GPIO_CFGLR_IN_PUPD); // GMII_RXD0 + funPinMode(PC1, GPIO_CFGLR_IN_PUPD); // GMII_RXCTL + funPinMode(PC0, GPIO_CFGLR_IN_FLOAT); // GMII_RXC - funDigitalWrite( PA1, FUN_HIGH ); // SELGRV = 3.3V - funDigitalWrite( PA0, FUN_HIGH ); // TXDelay = 1 - funDigitalWrite( PC3, FUN_HIGH ); // AN[0] = 1 - funDigitalWrite( PC2, FUN_HIGH ); // AN[1] = 1 - funDigitalWrite( PC1, FUN_LOW ); // PHYAD[0] + funDigitalWrite(PA1, FUN_HIGH); // SELGRV = 3.3V + funDigitalWrite(PA0, FUN_HIGH); // TXDelay = 1 + funDigitalWrite(PC3, FUN_HIGH); // AN[0] = 1 + funDigitalWrite(PC2, FUN_HIGH); // AN[1] = 1 + funDigitalWrite(PC1, FUN_LOW); // PHYAD[0] - // Configure MDC/MDIO - // Conflicting notes - some say /42, others don't. - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42; + // Configure MDC/MDIO + // Conflicting notes - some say /42, others don't. + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42; - // Update MACCR - ETH->MACCR = - ( CH32V307GIGABIT_CFG_CLOCK_DELAY << 29 ) | // No clock delay - ( 0 << 23 ) | // Max RX = 2kB (Revisit if looking into jumbo frames) - ( 0 << 22 ) | // Max TX = 2kB (Revisit if looking into jumbo frames) - ( 0 << 21 ) | // Rated Drive (instead of energy savings mode) (10M PHY only) - ( 1 << 20 ) | // Bizarre re-use of termination resistor terminology? (10M PHY Only) - ( 0 << 17 ) | // IFG = 0, 96-bit guard time. - ( 0 << 14 ) | // FES = 2 = GBE, 1=100MBit/s (UNSET TO START) - ( 0 << 12 ) | // Self Loop = 0 - ( 0 << 11 ) | // Full-Duplex Mode (UNSET TO START) - ( 1 << 10 ) | // IPCO = 1, Check TCP, UDP, ICMP header checksums. - ( 1 << 7 ) | // APCS (automatically strip frames) - ( 1 << 3 ) | // TE (Transmit enable!) - ( 1 << 2 ) | // RE (Receive Enable) - ( CH32V307GIGABIT_CFG_CLOCK_PHASE << 1 ) | // TCF = 0 (Potentailly change if clocking is wrong) - 0; + // Update MACCR + ETH->MACCR = + (CH32V307GIGABIT_CFG_CLOCK_DELAY << 29) | // No clock delay + (0 << 23) | // Max RX = 2kB (Revisit if looking into jumbo frames) + (0 << 22) | // Max TX = 2kB (Revisit if looking into jumbo frames) + (0 << 21) | // Rated Drive (instead of energy savings mode) (10M PHY only) + (1 << 20) | // Bizarre re-use of termination resistor terminology? (10M PHY Only) + (0 << 17) | // IFG = 0, 96-bit guard time. + (0 << 14) | // FES = 2 = GBE, 1=100MBit/s (UNSET TO START) + (0 << 12) | // Self Loop = 0 + (0 << 11) | // Full-Duplex Mode (UNSET TO START) + (1 << 10) | // IPCO = 1, Check TCP, UDP, ICMP header checksums. + (1 << 7) | // APCS (automatically strip frames) + (1 << 3) | // TE (Transmit enable!) + (1 << 2) | // RE (Receive Enable) + (CH32V307GIGABIT_CFG_CLOCK_PHASE << 1) | // TCF = 0 (Potentailly change if clocking is wrong) + 0; - Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 19ms. + Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 19ms. - // Reset the physical layer - ch32v307ethPHYRegWrite( PHY_BCR, - PHY_Reset | - 1<<12 | // Auto negotiate - 1<<8 | // Duplex - 1<<6 | // Speed Bit. - 0 ); + // Reset the physical layer + ch32v307ethPHYRegWrite(PHY_BCR, + PHY_Reset | + 1 << 12 | // Auto negotiate + 1 << 8 | // Duplex + 1 << 6 | // Speed Bit. + 0); - // De-assert reset. - ch32v307ethPHYRegWrite( PHY_BCR, - 1<<12 | // Auto negotiate - 1<<8 | // Duplex - 1<<6 | // Speed Bit. - 0 ); + // De-assert reset. + ch32v307ethPHYRegWrite(PHY_BCR, + 1 << 12 | // Auto negotiate + 1 << 8 | // Duplex + 1 << 6 | // Speed Bit. + 0); - ch32v307ethPHYRegRead( 0x03 ); - ch32v307eth_phyid = ch32v307ethPHYRegRead( 0x03 ); // Read twice to be safe. - if( ch32v307eth_phyid == 0xc916 ) - ch32v307ethPHYRegWrite( 0x1F, 0x0a43 ); // RTL8211FS needs page select. + ch32v307ethPHYRegRead(0x03); + ch32v307eth_phyid = ch32v307ethPHYRegRead(0x03); // Read twice to be safe. + if (ch32v307eth_phyid == 0xc916) + ch32v307ethPHYRegWrite(0x1F, 0x0a43); // RTL8211FS needs page select. - ch32v307ethGetMacInUC( ch32v307eth_mac ); + ch32v307ethGetMacInUC(ch32v307eth_mac); - ETH->MACA0HR = (uint32_t)((ch32v307eth_mac[5]<<8) | ch32v307eth_mac[4]); - ETH->MACA0LR = (uint32_t)(ch32v307eth_mac[0] | (ch32v307eth_mac[1]<<8) | (ch32v307eth_mac[2]<<16) | (ch32v307eth_mac[3]<<24)); + ETH->MACA0HR = (uint32_t)((ch32v307eth_mac[5] << 8) | ch32v307eth_mac[4]); + ETH->MACA0LR = (uint32_t)(ch32v307eth_mac[0] | (ch32v307eth_mac[1] << 8) | (ch32v307eth_mac[2] << 16) | (ch32v307eth_mac[3] << 24)); - ETH->MACFFR = (uint32_t)(ETH_ReceiveAll_Disable | - ETH_SourceAddrFilter_Disable | - ETH_PassControlFrames_BlockAll | - ETH_BroadcastFramesReception_Enable | - ETH_DestinationAddrFilter_Normal | - ETH_PromiscuousMode_Disable | - ETH_MulticastFramesFilter_Perfect | - ETH_UnicastFramesFilter_Perfect); + ETH->MACFFR = (uint32_t)(ETH_ReceiveAll_Disable | + ETH_SourceAddrFilter_Disable | + ETH_PassControlFrames_BlockAll | + ETH_BroadcastFramesReception_Enable | + ETH_DestinationAddrFilter_Normal | + ETH_PromiscuousMode_Disable | + ETH_MulticastFramesFilter_Perfect | + ETH_UnicastFramesFilter_Perfect); - ETH->MACHTHR = (uint32_t)0; - ETH->MACHTLR = (uint32_t)0; - ETH->MACVLANTR = (uint32_t)(ETH_VLANTagComparison_16Bit); + ETH->MACHTHR = (uint32_t)0; + ETH->MACHTLR = (uint32_t)0; + ETH->MACVLANTR = (uint32_t)(ETH_VLANTagComparison_16Bit); - ETH->MACFCR = 0; // No pause frames. + ETH->MACFCR = 0; // No pause frames. - // Configure RX/TX chains. - ETH_DMADESCTypeDef *tdesc; - for(i = 0; i < CH32V307GIGABIT_TXBUFNB; i++) - { - tdesc = ch32v307eth_DMATxDscrTab + i; - tdesc->ControlBufferSize = 0; - tdesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC | ETH_DMATxDesc_FS; - tdesc->Buffer1Addr = (uint32_t)0; // Populate with data. - tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_TXBUFNB - 1) ? ((uint32_t)(ch32v307eth_DMATxDscrTab + i + 1)) : (uint32_t)ch32v307eth_DMATxDscrTab; - } - ETH->DMATDLAR = (uint32_t)ch32v307eth_DMATxDscrTab; - for(i = 0; i < CH32V307GIGABIT_RXBUFNB; i++) - { - tdesc = ch32v307eth_DMARxDscrTab + i; - tdesc->Status = ETH_DMARxDesc_OWN; - tdesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)CH32V307GIGABIT_BUFFSIZE; - tdesc->Buffer1Addr = (uint32_t)(&ch32v307eth_MACRxBuf[i * CH32V307GIGABIT_BUFFSIZE]); - tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_RXBUFNB - 1) ? (uint32_t)(ch32v307eth_DMARxDscrTab + i + 1) : (uint32_t)(ch32v307eth_DMARxDscrTab); - } - ETH->DMARDLAR = (uint32_t)ch32v307eth_DMARxDscrTab; + // Configure RX/TX chains. + ETH_DMADESCTypeDef *tdesc; + for (i = 0; i < CH32V307GIGABIT_TXBUFNB; i++) + { + tdesc = ch32v307eth_DMATxDscrTab + i; + tdesc->ControlBufferSize = 0; + tdesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC | ETH_DMATxDesc_FS; + tdesc->Buffer1Addr = (uint32_t)0; // Populate with data. + tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_TXBUFNB - 1) ? ((uint32_t)(ch32v307eth_DMATxDscrTab + i + 1)) : (uint32_t)ch32v307eth_DMATxDscrTab; + } + ETH->DMATDLAR = (uint32_t)ch32v307eth_DMATxDscrTab; + for (i = 0; i < CH32V307GIGABIT_RXBUFNB; i++) + { + tdesc = ch32v307eth_DMARxDscrTab + i; + tdesc->Status = ETH_DMARxDesc_OWN; + tdesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)CH32V307GIGABIT_BUFFSIZE; + tdesc->Buffer1Addr = (uint32_t)(&ch32v307eth_MACRxBuf[i * CH32V307GIGABIT_BUFFSIZE]); + tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_RXBUFNB - 1) ? (uint32_t)(ch32v307eth_DMARxDscrTab + i + 1) : (uint32_t)(ch32v307eth_DMARxDscrTab); + } + ETH->DMARDLAR = (uint32_t)ch32v307eth_DMARxDscrTab; - pDMARxGet = ch32v307eth_DMARxDscrTab; - pDMATxSet = ch32v307eth_DMATxDscrTab; + pDMARxGet = ch32v307eth_DMARxDscrTab; + pDMATxSet = ch32v307eth_DMATxDscrTab; - // Receive a good frame half interrupt mask. - // Receive CRC error frame half interrupt mask. - // For the future: Why do we want this? - ETH->MMCTIMR = ETH_MMCTIMR_TGFM; - ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM; + // Receive a good frame half interrupt mask. + // Receive CRC error frame half interrupt mask. + // For the future: Why do we want this? + ETH->MMCTIMR = ETH_MMCTIMR_TGFM; + ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM; - ETH->DMAIER = ETH_DMA_IT_NIS | // Normal interrupt enable. - ETH_DMA_IT_R | // Receive - ETH_DMA_IT_T | // Transmit - ETH_DMA_IT_AIS | // Abnormal interrupt - ETH_DMA_IT_RBU; // Receive buffer unavailable interrupt enable + ETH->DMAIER = ETH_DMA_IT_NIS | // Normal interrupt enable. + ETH_DMA_IT_R | // Receive + ETH_DMA_IT_T | // Transmit + ETH_DMA_IT_AIS | // Abnormal interrupt + ETH_DMA_IT_RBU; // Receive buffer unavailable interrupt enable - NVIC_EnableIRQ( ETH_IRQn ); + NVIC_EnableIRQ(ETH_IRQn); - // Actually enable receiving process. - ETH->DMAOMR = ETH_DMAOMR_SR | ETH_DMAOMR_ST | ETH_DMAOMR_TSF | ETH_DMAOMR_FEF; + // Actually enable receiving process. + ETH->DMAOMR = ETH_DMAOMR_SR | ETH_DMAOMR_ST | ETH_DMAOMR_TSF | ETH_DMAOMR_FEF; - return 0; + return 0; } -void ETH_IRQHandler( void ) __attribute__((interrupt)); -void ETH_IRQHandler( void ) +void ETH_IRQHandler(void) __attribute__((interrupt)); +void ETH_IRQHandler(void) { uint32_t int_sta; - do - { - int_sta = ETH->DMASR; - if ( ( int_sta & ( ETH_DMA_IT_AIS | ETH_DMA_IT_NIS ) ) == 0 ) - { - break; - } + do + { + int_sta = ETH->DMASR; + if ((int_sta & (ETH_DMA_IT_AIS | ETH_DMA_IT_NIS)) == 0) + { + break; + } - // Off nominal situations. - if (int_sta & ETH_DMA_IT_AIS) - { - // Receive buffer unavailable interrupt enable. - if (int_sta & ETH_DMA_IT_RBU) - { - ETH->DMASR = ETH_DMA_IT_RBU; - if((INFO->CHIPID & 0xf0) == 0x10) - { - ((ETH_DMADESCTypeDef *)(((ETH_DMADESCTypeDef *)(ETH->DMACHRDR))->Buffer2NextDescAddr))->Status = ETH_DMARxDesc_OWN; - ETH->DMARPDR = 0; - } - } - ETH->DMASR = ETH_DMA_IT_AIS; - } + // Off nominal situations. + if (int_sta & ETH_DMA_IT_AIS) + { + // Receive buffer unavailable interrupt enable. + if (int_sta & ETH_DMA_IT_RBU) + { + ETH->DMASR = ETH_DMA_IT_RBU; + if ((INFO->CHIPID & 0xf0) == 0x10) + { + ((ETH_DMADESCTypeDef *)(((ETH_DMADESCTypeDef *)(ETH->DMACHRDR))->Buffer2NextDescAddr))->Status = ETH_DMARxDesc_OWN; + ETH->DMARPDR = 0; + } + } + ETH->DMASR = ETH_DMA_IT_AIS; + } - // Nominal interrupts. - if( int_sta & ETH_DMA_IT_NIS ) - { - if( int_sta & ETH_DMA_IT_R ) - { - // Received a packet, normally. - // Status is in Table 27-17 Definitions of RDes0 - do - { - // XXX TODO: Is this a good place to acknowledge? REVISIT: Should this go lower? - // XXX TODO: Restructure this to allow for - ETH->DMASR = ETH_DMA_IT_R; + // Nominal interrupts. + if (int_sta & ETH_DMA_IT_NIS) + { + if (int_sta & ETH_DMA_IT_R) + { + // Received a packet, normally. + // Status is in Table 27-17 Definitions of RDes0 + do + { + // XXX TODO: Is this a good place to acknowledge? REVISIT: Should this go lower? + // XXX TODO: Restructure this to allow for + ETH->DMASR = ETH_DMA_IT_R; - uint32_t status = pDMARxGet->Status; - if( status & ETH_DMARxDesc_OWN ) break; + uint32_t status = pDMARxGet->Status; + if (status & ETH_DMARxDesc_OWN) break; - // We only have a valid packet in a specific situation. - // So, we take the status, then mask off the bits we care about - // And see if they're equal to the ones that need to be set/unset. - const uint32_t mask = - ETH_DMARxDesc_OWN | - ETH_DMARxDesc_LS | - ETH_DMARxDesc_ES | - ETH_DMARxDesc_FS; - const uint32_t eq = - 0 | - ETH_DMARxDesc_LS | - 0 | - ETH_DMARxDesc_FS; + // We only have a valid packet in a specific situation. + // So, we take the status, then mask off the bits we care about + // And see if they're equal to the ones that need to be set/unset. + const uint32_t mask = + ETH_DMARxDesc_OWN | + ETH_DMARxDesc_LS | + ETH_DMARxDesc_ES | + ETH_DMARxDesc_FS; + const uint32_t eq = + 0 | + ETH_DMARxDesc_LS | + 0 | + ETH_DMARxDesc_FS; - int suppress_own = 0; + int suppress_own = 0; - if( ( status & mask ) == eq ) - { - int32_t frame_length = ((status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - if( frame_length > 0 ) - { - uint8_t * data = (uint8_t*)pDMARxGet->Buffer1Addr; - suppress_own = ch32v307ethInitHandlePacket( data, frame_length, pDMARxGet ); - } - } - // Otherwise, Invalid Packet + if ((status & mask) == eq) + { + int32_t frame_length = ((status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + if (frame_length > 0) + { + uint8_t *data = (uint8_t *)pDMARxGet->Buffer1Addr; + suppress_own = ch32v307ethInitHandlePacket(data, frame_length, pDMARxGet); + } + } + // Otherwise, Invalid Packet - // Relinquish control back to underlying hardware. - if( !suppress_own ) - pDMARxGet->Status = ETH_DMARxDesc_OWN; + // Relinquish control back to underlying hardware. + if (!suppress_own) + pDMARxGet->Status = ETH_DMARxDesc_OWN; - // Tricky logic for figuring out the next packet. Originally - // discussed in ch32v30x_eth.c in ETH_DropRxPkt - if((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - pDMARxGet = (ETH_DMADESCTypeDef *)(pDMARxGet->Buffer2NextDescAddr); - else - { - if((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - pDMARxGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); - else - pDMARxGet = (ETH_DMADESCTypeDef *)((uint32_t)pDMARxGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } while( 1 ); - } - if( int_sta & ETH_DMA_IT_T ) - { - ch32v307ethInitHandleTXC(); - ETH->DMASR = ETH_DMA_IT_T; - } - ETH->DMASR = ETH_DMA_IT_NIS; - } - } while( 1 ); + // Tricky logic for figuring out the next packet. Originally + // discussed in ch32v30x_eth.c in ETH_DropRxPkt + if ((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + pDMARxGet = (ETH_DMADESCTypeDef *)(pDMARxGet->Buffer2NextDescAddr); + else + { + if ((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + pDMARxGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + else + pDMARxGet = (ETH_DMADESCTypeDef *)((uint32_t)pDMARxGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } while (1); + } + if (int_sta & ETH_DMA_IT_T) + { + ch32v307ethInitHandleTXC(); + ETH->DMASR = ETH_DMA_IT_T; + } + ETH->DMASR = ETH_DMA_IT_NIS; + } + } while (1); } -static int ch32v307ethTransmitStatic(uint8_t * buffer, uint32_t length, int enable_txc) +static int ch32v307ethTransmitStatic(uint8_t *buffer, uint32_t length, int enable_txc) { - // The official SDK waits until ETH_DMATxDesc_TTSS is set. - // This also provides a transmit timestamp, which could be - // used for PTP. - // But we don't want to do that. - // We just want to go. If anyone cares, they can check later. + // The official SDK waits until ETH_DMATxDesc_TTSS is set. + // This also provides a transmit timestamp, which could be + // used for PTP. + // But we don't want to do that. + // We just want to go. If anyone cares, they can check later. - if( pDMATxSet->Status & ETH_DMATxDesc_OWN ) - { - ETH->DMATPDR = 0; - return -1; - } + if (pDMATxSet->Status & ETH_DMATxDesc_OWN) + { + ETH->DMATPDR = 0; + return -1; + } pDMATxSet->ControlBufferSize = (length & ETH_DMATxDesc_TBS1); - pDMATxSet->Buffer1Addr = (uint32_t)buffer; + pDMATxSet->Buffer1Addr = (uint32_t)buffer; - // Status is in Table 27-12 "Definitions of TDes0 bits" - enable_txc = enable_txc ? ETH_DMATxDesc_IC : 0; - pDMATxSet->Status = - ETH_DMATxDesc_LS | // Last Segment (This is all you need to have to transmit) - ETH_DMATxDesc_FS | // First Segment (Beginning of transmission) - enable_txc | // Interrupt when complete - ETH_DMATxDesc_TCH | // Next Descriptor Address Valid - ETH_DMATxDesc_CIC_TCPUDPICMP_Full | // Do all header checksums. - ETH_DMATxDesc_OWN; // Own back to hardware + // Status is in Table 27-12 "Definitions of TDes0 bits" + enable_txc = enable_txc ? ETH_DMATxDesc_IC : 0; + pDMATxSet->Status = + ETH_DMATxDesc_LS | // Last Segment (This is all you need to have to transmit) + ETH_DMATxDesc_FS | // First Segment (Beginning of transmission) + enable_txc | // Interrupt when complete + ETH_DMATxDesc_TCH | // Next Descriptor Address Valid + ETH_DMATxDesc_CIC_TCPUDPICMP_Full | // Do all header checksums. + ETH_DMATxDesc_OWN; // Own back to hardware - pDMATxSet = (ETH_DMADESCTypeDef*)pDMATxSet->Buffer2NextDescAddr; + pDMATxSet = (ETH_DMADESCTypeDef *)pDMATxSet->Buffer2NextDescAddr; - ETH->DMASR = ETH_DMASR_TBUS; // This resets the transmit process (or "starts" it) - ETH->DMATPDR = 0; + ETH->DMASR = ETH_DMASR_TBUS; // This resets the transmit process (or "starts" it) + ETH->DMATPDR = 0; - return 0; + return 0; } - #endif - diff --git a/src/extralibs/font_8x8.h b/src/extralibs/font_8x8.h index 815d5b2..4cf7511 100644 --- a/src/extralibs/font_8x8.h +++ b/src/extralibs/font_8x8.h @@ -6,2564 +6,2564 @@ const static unsigned char fontdata[] = { - /* 0 0x00 '^@' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 1 0x01 '^A' */ - 0x7e, /* 01111110 */ - 0x81, /* 10000001 */ - 0xa5, /* 10100101 */ - 0x81, /* 10000001 */ - 0xbd, /* 10111101 */ - 0x99, /* 10011001 */ - 0x81, /* 10000001 */ - 0x7e, /* 01111110 */ - - /* 2 0x02 '^B' */ - 0x7e, /* 01111110 */ - 0xff, /* 11111111 */ - 0xdb, /* 11011011 */ - 0xff, /* 11111111 */ - 0xc3, /* 11000011 */ - 0xe7, /* 11100111 */ - 0xff, /* 11111111 */ - 0x7e, /* 01111110 */ - - /* 3 0x03 '^C' */ - 0x6c, /* 01101100 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0x7c, /* 01111100 */ - 0x38, /* 00111000 */ - 0x10, /* 00010000 */ - 0x00, /* 00000000 */ - - /* 4 0x04 '^D' */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x7c, /* 01111100 */ - 0xfe, /* 11111110 */ - 0x7c, /* 01111100 */ - 0x38, /* 00111000 */ - 0x10, /* 00010000 */ - 0x00, /* 00000000 */ - - /* 5 0x05 '^E' */ - 0x38, /* 00111000 */ - 0x7c, /* 01111100 */ - 0x38, /* 00111000 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0xd6, /* 11010110 */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - - /* 6 0x06 '^F' */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x7c, /* 01111100 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0x7c, /* 01111100 */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - - /* 7 0x07 '^G' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 8 0x08 '^H' */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xe7, /* 11100111 */ - 0xc3, /* 11000011 */ - 0xc3, /* 11000011 */ - 0xe7, /* 11100111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - - /* 9 0x09 '^I' */ - 0x00, /* 00000000 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x42, /* 01000010 */ - 0x42, /* 01000010 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 10 0x0a '^J' */ - 0xff, /* 11111111 */ - 0xc3, /* 11000011 */ - 0x99, /* 10011001 */ - 0xbd, /* 10111101 */ - 0xbd, /* 10111101 */ - 0x99, /* 10011001 */ - 0xc3, /* 11000011 */ - 0xff, /* 11111111 */ - - /* 11 0x0b '^K' */ - 0x0f, /* 00001111 */ - 0x07, /* 00000111 */ - 0x0f, /* 00001111 */ - 0x7d, /* 01111101 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x78, /* 01111000 */ - - /* 12 0x0c '^L' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - - /* 13 0x0d '^M' */ - 0x3f, /* 00111111 */ - 0x33, /* 00110011 */ - 0x3f, /* 00111111 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x70, /* 01110000 */ - 0xf0, /* 11110000 */ - 0xe0, /* 11100000 */ - - /* 14 0x0e '^N' */ - 0x7f, /* 01111111 */ - 0x63, /* 01100011 */ - 0x7f, /* 01111111 */ - 0x63, /* 01100011 */ - 0x63, /* 01100011 */ - 0x67, /* 01100111 */ - 0xe6, /* 11100110 */ - 0xc0, /* 11000000 */ - - /* 15 0x0f '^O' */ - 0x18, /* 00011000 */ - 0xdb, /* 11011011 */ - 0x3c, /* 00111100 */ - 0xe7, /* 11100111 */ - 0xe7, /* 11100111 */ - 0x3c, /* 00111100 */ - 0xdb, /* 11011011 */ - 0x18, /* 00011000 */ - - /* 16 0x10 '^P' */ - 0x80, /* 10000000 */ - 0xe0, /* 11100000 */ - 0xf8, /* 11111000 */ - 0xfe, /* 11111110 */ - 0xf8, /* 11111000 */ - 0xe0, /* 11100000 */ - 0x80, /* 10000000 */ - 0x00, /* 00000000 */ - - /* 17 0x11 '^Q' */ - 0x02, /* 00000010 */ - 0x0e, /* 00001110 */ - 0x3e, /* 00111110 */ - 0xfe, /* 11111110 */ - 0x3e, /* 00111110 */ - 0x0e, /* 00001110 */ - 0x02, /* 00000010 */ - 0x00, /* 00000000 */ - - /* 18 0x12 '^R' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - - /* 19 0x13 '^S' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - - /* 20 0x14 '^T' */ - 0x7f, /* 01111111 */ - 0xdb, /* 11011011 */ - 0xdb, /* 11011011 */ - 0x7b, /* 01111011 */ - 0x1b, /* 00011011 */ - 0x1b, /* 00011011 */ - 0x1b, /* 00011011 */ - 0x00, /* 00000000 */ - - /* 21 0x15 '^U' */ - 0x3e, /* 00111110 */ - 0x61, /* 01100001 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x86, /* 10000110 */ - 0x7c, /* 01111100 */ - - /* 22 0x16 '^V' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x7e, /* 01111110 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 23 0x17 '^W' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - - /* 24 0x18 '^X' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 25 0x19 '^Y' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 26 0x1a '^Z' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0xfe, /* 11111110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 27 0x1b '^[' */ - 0x00, /* 00000000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0xfe, /* 11111110 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 28 0x1c '^\' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 29 0x1d '^]' */ - 0x00, /* 00000000 */ - 0x24, /* 00100100 */ - 0x66, /* 01100110 */ - 0xff, /* 11111111 */ - 0x66, /* 01100110 */ - 0x24, /* 00100100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 30 0x1e '^^' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 31 0x1f '^_' */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 32 0x20 ' ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 33 0x21 '!' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 34 0x22 '"' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x24, /* 00100100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 35 0x23 '#' */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 36 0x24 '$' */ - 0x18, /* 00011000 */ - 0x3e, /* 00111110 */ - 0x60, /* 01100000 */ - 0x3c, /* 00111100 */ - 0x06, /* 00000110 */ - 0x7c, /* 01111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 37 0x25 '%' */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xcc, /* 11001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x66, /* 01100110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 38 0x26 '&' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 39 0x27 ''' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 40 0x28 '(' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x00, /* 00000000 */ - - /* 41 0x29 ')' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - - /* 42 0x2a '*' */ - 0x00, /* 00000000 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0xff, /* 11111111 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 43 0x2b '+' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 44 0x2c ',' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - - /* 45 0x2d '-' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 46 0x2e '.' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 47 0x2f '/' */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0xc0, /* 11000000 */ - 0x80, /* 10000000 */ - 0x00, /* 00000000 */ - - /* 48 0x30 '0' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xd6, /* 11010110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 49 0x31 '1' */ - 0x18, /* 00011000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 50 0x32 '2' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0x06, /* 00000110 */ - 0x1c, /* 00011100 */ - 0x30, /* 00110000 */ - 0x66, /* 01100110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 51 0x33 '3' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0x06, /* 00000110 */ - 0x3c, /* 00111100 */ - 0x06, /* 00000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 52 0x34 '4' */ - 0x1c, /* 00011100 */ - 0x3c, /* 00111100 */ - 0x6c, /* 01101100 */ - 0xcc, /* 11001100 */ - 0xfe, /* 11111110 */ - 0x0c, /* 00001100 */ - 0x1e, /* 00011110 */ - 0x00, /* 00000000 */ - - /* 53 0x35 '5' */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xfc, /* 11111100 */ - 0x06, /* 00000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 54 0x36 '6' */ - 0x38, /* 00111000 */ - 0x60, /* 01100000 */ - 0xc0, /* 11000000 */ - 0xfc, /* 11111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 55 0x37 '7' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - - /* 56 0x38 '8' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 57 0x39 '9' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7e, /* 01111110 */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x78, /* 01111000 */ - 0x00, /* 00000000 */ - - /* 58 0x3a ':' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 59 0x3b ';' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - - /* 60 0x3c '<' */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x06, /* 00000110 */ - 0x00, /* 00000000 */ - - /* 61 0x3d '=' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 62 0x3e '>' */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0x00, /* 00000000 */ - - /* 63 0x3f '?' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 64 0x40 '@' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xde, /* 11011110 */ - 0xde, /* 11011110 */ - 0xde, /* 11011110 */ - 0xc0, /* 11000000 */ - 0x78, /* 01111000 */ - 0x00, /* 00000000 */ - - /* 65 0x41 'A' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 66 0x42 'B' */ - 0xfc, /* 11111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0xfc, /* 11111100 */ - 0x00, /* 00000000 */ - - /* 67 0x43 'C' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 68 0x44 'D' */ - 0xf8, /* 11111000 */ - 0x6c, /* 01101100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x6c, /* 01101100 */ - 0xf8, /* 11111000 */ - 0x00, /* 00000000 */ - - /* 69 0x45 'E' */ - 0xfe, /* 11111110 */ - 0x62, /* 01100010 */ - 0x68, /* 01101000 */ - 0x78, /* 01111000 */ - 0x68, /* 01101000 */ - 0x62, /* 01100010 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 70 0x46 'F' */ - 0xfe, /* 11111110 */ - 0x62, /* 01100010 */ - 0x68, /* 01101000 */ - 0x78, /* 01111000 */ - 0x68, /* 01101000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 71 0x47 'G' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xce, /* 11001110 */ - 0x66, /* 01100110 */ - 0x3a, /* 00111010 */ - 0x00, /* 00000000 */ - - /* 72 0x48 'H' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 73 0x49 'I' */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 74 0x4a 'J' */ - 0x1e, /* 00011110 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x78, /* 01111000 */ - 0x00, /* 00000000 */ - - /* 75 0x4b 'K' */ - 0xe6, /* 11100110 */ - 0x66, /* 01100110 */ - 0x6c, /* 01101100 */ - 0x78, /* 01111000 */ - 0x6c, /* 01101100 */ - 0x66, /* 01100110 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 76 0x4c 'L' */ - 0xf0, /* 11110000 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0x62, /* 01100010 */ - 0x66, /* 01100110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 77 0x4d 'M' */ - 0xc6, /* 11000110 */ - 0xee, /* 11101110 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0xd6, /* 11010110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 78 0x4e 'N' */ - 0xc6, /* 11000110 */ - 0xe6, /* 11100110 */ - 0xf6, /* 11110110 */ - 0xde, /* 11011110 */ - 0xce, /* 11001110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 79 0x4f 'O' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 80 0x50 'P' */ - 0xfc, /* 11111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 81 0x51 'Q' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xce, /* 11001110 */ - 0x7c, /* 01111100 */ - 0x0e, /* 00001110 */ - - /* 82 0x52 'R' */ - 0xfc, /* 11111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x6c, /* 01101100 */ - 0x66, /* 01100110 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 83 0x53 'S' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 84 0x54 'T' */ - 0x7e, /* 01111110 */ - 0x7e, /* 01111110 */ - 0x5a, /* 01011010 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 85 0x55 'U' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 86 0x56 'V' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 87 0x57 'W' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 88 0x58 'X' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 89 0x59 'Y' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 90 0x5a 'Z' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x8c, /* 10001100 */ - 0x18, /* 00011000 */ - 0x32, /* 00110010 */ - 0x66, /* 01100110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 91 0x5b '[' */ - 0x3c, /* 00111100 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 92 0x5c '\' */ - 0xc0, /* 11000000 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x06, /* 00000110 */ - 0x02, /* 00000010 */ - 0x00, /* 00000000 */ - - /* 93 0x5d ']' */ - 0x3c, /* 00111100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 94 0x5e '^' */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 95 0x5f '_' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - - /* 96 0x60 '`' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 97 0x61 'a' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 98 0x62 'b' */ - 0xe0, /* 11100000 */ - 0x60, /* 01100000 */ - 0x7c, /* 01111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - - /* 99 0x63 'c' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc0, /* 11000000 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 100 0x64 'd' */ - 0x1c, /* 00011100 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 101 0x65 'e' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 102 0x66 'f' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x60, /* 01100000 */ - 0xf8, /* 11111000 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 103 0x67 'g' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x7c, /* 01111100 */ - 0x0c, /* 00001100 */ - 0xf8, /* 11111000 */ - - /* 104 0x68 'h' */ - 0xe0, /* 11100000 */ - 0x60, /* 01100000 */ - 0x6c, /* 01101100 */ - 0x76, /* 01110110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 105 0x69 'i' */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 106 0x6a 'j' */ - 0x06, /* 00000110 */ - 0x00, /* 00000000 */ - 0x06, /* 00000110 */ - 0x06, /* 00000110 */ - 0x06, /* 00000110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - - /* 107 0x6b 'k' */ - 0xe0, /* 11100000 */ - 0x60, /* 01100000 */ - 0x66, /* 01100110 */ - 0x6c, /* 01101100 */ - 0x78, /* 01111000 */ - 0x6c, /* 01101100 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 108 0x6c 'l' */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 109 0x6d 'm' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xec, /* 11101100 */ - 0xfe, /* 11111110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0x00, /* 00000000 */ - - /* 110 0x6e 'n' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - - /* 111 0x6f 'o' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 112 0x70 'p' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - - /* 113 0x71 'q' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x7c, /* 01111100 */ - 0x0c, /* 00001100 */ - 0x1e, /* 00011110 */ - - /* 114 0x72 'r' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x76, /* 01110110 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 115 0x73 's' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x06, /* 00000110 */ - 0xfc, /* 11111100 */ - 0x00, /* 00000000 */ - - /* 116 0x74 't' */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0xfc, /* 11111100 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x36, /* 00110110 */ - 0x1c, /* 00011100 */ - 0x00, /* 00000000 */ - - /* 117 0x75 'u' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 118 0x76 'v' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 119 0x77 'w' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 120 0x78 'x' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 121 0x79 'y' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7e, /* 01111110 */ - 0x06, /* 00000110 */ - 0xfc, /* 11111100 */ - - /* 122 0x7a 'z' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x4c, /* 01001100 */ - 0x18, /* 00011000 */ - 0x32, /* 00110010 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 123 0x7b '{' */ - 0x0e, /* 00001110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x70, /* 01110000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x0e, /* 00001110 */ - 0x00, /* 00000000 */ - - /* 124 0x7c '|' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 125 0x7d '}' */ - 0x70, /* 01110000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x0e, /* 00001110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x70, /* 01110000 */ - 0x00, /* 00000000 */ - - /* 126 0x7e '~' */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 127 0x7f '' */ - 0x00, /* 00000000 */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 128 0x80 '€' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x0c, /* 00001100 */ - 0x78, /* 01111000 */ - - /* 129 0x81 '' */ - 0xcc, /* 11001100 */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 130 0x82 '‚' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 131 0x83 'ƒ' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 132 0x84 '„' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 133 0x85 '…' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 134 0x86 '†' */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 135 0x87 '‡' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x7e, /* 01111110 */ - 0x0c, /* 00001100 */ - 0x38, /* 00111000 */ - - /* 136 0x88 'ˆ' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 137 0x89 '‰' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 138 0x8a 'Š' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 139 0x8b '‹' */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 140 0x8c 'Œ' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 141 0x8d '' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 142 0x8e 'Ž' */ - 0xc6, /* 11000110 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 143 0x8f '' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 144 0x90 '' */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0xf8, /* 11111000 */ - 0xc0, /* 11000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 145 0x91 '‘' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0xd8, /* 11011000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 146 0x92 '’' */ - 0x3e, /* 00111110 */ - 0x6c, /* 01101100 */ - 0xcc, /* 11001100 */ - 0xfe, /* 11111110 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xce, /* 11001110 */ - 0x00, /* 00000000 */ - - /* 147 0x93 '“' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 148 0x94 '”' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 149 0x95 '•' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 150 0x96 '–' */ - 0x78, /* 01111000 */ - 0x84, /* 10000100 */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 151 0x97 '—' */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 152 0x98 '˜' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7e, /* 01111110 */ - 0x06, /* 00000110 */ - 0xfc, /* 11111100 */ - - /* 153 0x99 '™' */ - 0xc6, /* 11000110 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 154 0x9a 'š' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 155 0x9b '›' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 156 0x9c 'œ' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x64, /* 01100100 */ - 0xf0, /* 11110000 */ - 0x60, /* 01100000 */ - 0x66, /* 01100110 */ - 0xfc, /* 11111100 */ - 0x00, /* 00000000 */ - - /* 157 0x9d '' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 158 0x9e 'ž' */ - 0xf8, /* 11111000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xfa, /* 11111010 */ - 0xc6, /* 11000110 */ - 0xcf, /* 11001111 */ - 0xc6, /* 11000110 */ - 0xc7, /* 11000111 */ - - /* 159 0x9f 'Ÿ' */ - 0x0e, /* 00001110 */ - 0x1b, /* 00011011 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0xd8, /* 11011000 */ - 0x70, /* 01110000 */ - 0x00, /* 00000000 */ - - /* 160 0xa0 ' ' */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 161 0xa1 '¡' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 162 0xa2 '¢' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 163 0xa3 '£' */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 164 0xa4 '¤' */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - - /* 165 0xa5 '¥' */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0xe6, /* 11100110 */ - 0xf6, /* 11110110 */ - 0xde, /* 11011110 */ - 0xce, /* 11001110 */ - 0x00, /* 00000000 */ - - /* 166 0xa6 '¦' */ - 0x3c, /* 00111100 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x3e, /* 00111110 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 167 0xa7 '§' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 168 0xa8 '¨' */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x63, /* 01100011 */ - 0x3e, /* 00111110 */ - 0x00, /* 00000000 */ - - /* 169 0xa9 '©' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 170 0xaa 'ª' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x06, /* 00000110 */ - 0x06, /* 00000110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 171 0xab '«' */ - 0x63, /* 01100011 */ - 0xe6, /* 11100110 */ - 0x6c, /* 01101100 */ - 0x7e, /* 01111110 */ - 0x33, /* 00110011 */ - 0x66, /* 01100110 */ - 0xcc, /* 11001100 */ - 0x0f, /* 00001111 */ - - /* 172 0xac '¬' */ - 0x63, /* 01100011 */ - 0xe6, /* 11100110 */ - 0x6c, /* 01101100 */ - 0x7a, /* 01111010 */ - 0x36, /* 00110110 */ - 0x6a, /* 01101010 */ - 0xdf, /* 11011111 */ - 0x06, /* 00000110 */ - - /* 173 0xad '­' */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 174 0xae '®' */ - 0x00, /* 00000000 */ - 0x33, /* 00110011 */ - 0x66, /* 01100110 */ - 0xcc, /* 11001100 */ - 0x66, /* 01100110 */ - 0x33, /* 00110011 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 175 0xaf '¯' */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0x66, /* 01100110 */ - 0x33, /* 00110011 */ - 0x66, /* 01100110 */ - 0xcc, /* 11001100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 176 0xb0 '°' */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - - /* 177 0xb1 '±' */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - - /* 178 0xb2 '²' */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - - /* 179 0xb3 '³' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 180 0xb4 '´' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 181 0xb5 'µ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 182 0xb6 '¶' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf6, /* 11110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 183 0xb7 '·' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 184 0xb8 '¸' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 185 0xb9 '¹' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf6, /* 11110110 */ - 0x06, /* 00000110 */ - 0xf6, /* 11110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 186 0xba 'º' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 187 0xbb '»' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x06, /* 00000110 */ - 0xf6, /* 11110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 188 0xbc '¼' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf6, /* 11110110 */ - 0x06, /* 00000110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 189 0xbd '½' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 190 0xbe '¾' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 191 0xbf '¿' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 192 0xc0 'À' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 193 0xc1 'Á' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 194 0xc2 'Â' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 195 0xc3 'Ã' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 196 0xc4 'Ä' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 197 0xc5 'Å' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 198 0xc6 'Æ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 199 0xc7 'Ç' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x37, /* 00110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 200 0xc8 'È' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x37, /* 00110111 */ - 0x30, /* 00110000 */ - 0x3f, /* 00111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 201 0xc9 'É' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x3f, /* 00111111 */ - 0x30, /* 00110000 */ - 0x37, /* 00110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 202 0xca 'Ê' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf7, /* 11110111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 203 0xcb 'Ë' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xf7, /* 11110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 204 0xcc 'Ì' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x37, /* 00110111 */ - 0x30, /* 00110000 */ - 0x37, /* 00110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 205 0xcd 'Í' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 206 0xce 'Î' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf7, /* 11110111 */ - 0x00, /* 00000000 */ - 0xf7, /* 11110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 207 0xcf 'Ï' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 208 0xd0 'Ð' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 209 0xd1 'Ñ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 210 0xd2 'Ò' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 211 0xd3 'Ó' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x3f, /* 00111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 212 0xd4 'Ô' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 213 0xd5 'Õ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 214 0xd6 'Ö' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x3f, /* 00111111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 215 0xd7 '×' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xff, /* 11111111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 216 0xd8 'Ø' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 217 0xd9 'Ù' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 218 0xda 'Ú' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 219 0xdb 'Û' */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - - /* 220 0xdc 'Ü' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - - /* 221 0xdd 'Ý' */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - - /* 222 0xde 'Þ' */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - - /* 223 0xdf 'ß' */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 224 0xe0 'à' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0xc8, /* 11001000 */ - 0xdc, /* 11011100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 225 0xe1 'á' */ - 0x78, /* 01111000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xd8, /* 11011000 */ - 0xcc, /* 11001100 */ - 0xc6, /* 11000110 */ - 0xcc, /* 11001100 */ - 0x00, /* 00000000 */ - - /* 226 0xe2 'â' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x00, /* 00000000 */ - - /* 227 0xe3 'ã' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 228 0xe4 'ä' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 229 0xe5 'å' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xd8, /* 11011000 */ - 0xd8, /* 11011000 */ - 0xd8, /* 11011000 */ - 0x70, /* 01110000 */ - 0x00, /* 00000000 */ - - /* 230 0xe6 'æ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0xc0, /* 11000000 */ - - /* 231 0xe7 'ç' */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 232 0xe8 'è' */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - - /* 233 0xe9 'é' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 234 0xea 'ê' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0xee, /* 11101110 */ - 0x00, /* 00000000 */ - - /* 235 0xeb 'ë' */ - 0x0e, /* 00001110 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x3e, /* 00111110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 236 0xec 'ì' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xdb, /* 11011011 */ - 0xdb, /* 11011011 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 237 0xed 'í' */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x7e, /* 01111110 */ - 0xdb, /* 11011011 */ - 0xdb, /* 11011011 */ - 0x7e, /* 01111110 */ - 0x60, /* 01100000 */ - 0xc0, /* 11000000 */ - - /* 238 0xee 'î' */ - 0x1e, /* 00011110 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0x7e, /* 01111110 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x1e, /* 00011110 */ - 0x00, /* 00000000 */ - - /* 239 0xef 'ï' */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 240 0xf0 'ð' */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 241 0xf1 'ñ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 242 0xf2 'ò' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 243 0xf3 'ó' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 244 0xf4 'ô' */ - 0x0e, /* 00001110 */ - 0x1b, /* 00011011 */ - 0x1b, /* 00011011 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 245 0xf5 'õ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xd8, /* 11011000 */ - 0xd8, /* 11011000 */ - 0x70, /* 01110000 */ - - /* 246 0xf6 'ö' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 247 0xf7 '÷' */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 248 0xf8 'ø' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 249 0xf9 'ù' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 250 0xfa 'ú' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 251 0xfb 'û' */ - 0x0f, /* 00001111 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0xec, /* 11101100 */ - 0x6c, /* 01101100 */ - 0x3c, /* 00111100 */ - 0x1c, /* 00011100 */ - - /* 252 0xfc 'ü' */ - 0x6c, /* 01101100 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 253 0xfd 'ý' */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 254 0xfe 'þ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 255 0xff 'ÿ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ + /* 0 0x00 '^@' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 1 0x01 '^A' */ + 0x7e, /* 01111110 */ + 0x81, /* 10000001 */ + 0xa5, /* 10100101 */ + 0x81, /* 10000001 */ + 0xbd, /* 10111101 */ + 0x99, /* 10011001 */ + 0x81, /* 10000001 */ + 0x7e, /* 01111110 */ + + /* 2 0x02 '^B' */ + 0x7e, /* 01111110 */ + 0xff, /* 11111111 */ + 0xdb, /* 11011011 */ + 0xff, /* 11111111 */ + 0xc3, /* 11000011 */ + 0xe7, /* 11100111 */ + 0xff, /* 11111111 */ + 0x7e, /* 01111110 */ + + /* 3 0x03 '^C' */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + + /* 4 0x04 '^D' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + + /* 5 0x05 '^E' */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + + /* 6 0x06 '^F' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + + /* 7 0x07 '^G' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 8 0x08 '^H' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xe7, /* 11100111 */ + 0xc3, /* 11000011 */ + 0xc3, /* 11000011 */ + 0xe7, /* 11100111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 9 0x09 '^I' */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x42, /* 01000010 */ + 0x42, /* 01000010 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 10 0x0a '^J' */ + 0xff, /* 11111111 */ + 0xc3, /* 11000011 */ + 0x99, /* 10011001 */ + 0xbd, /* 10111101 */ + 0xbd, /* 10111101 */ + 0x99, /* 10011001 */ + 0xc3, /* 11000011 */ + 0xff, /* 11111111 */ + + /* 11 0x0b '^K' */ + 0x0f, /* 00001111 */ + 0x07, /* 00000111 */ + 0x0f, /* 00001111 */ + 0x7d, /* 01111101 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + + /* 12 0x0c '^L' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + + /* 13 0x0d '^M' */ + 0x3f, /* 00111111 */ + 0x33, /* 00110011 */ + 0x3f, /* 00111111 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x70, /* 01110000 */ + 0xf0, /* 11110000 */ + 0xe0, /* 11100000 */ + + /* 14 0x0e '^N' */ + 0x7f, /* 01111111 */ + 0x63, /* 01100011 */ + 0x7f, /* 01111111 */ + 0x63, /* 01100011 */ + 0x63, /* 01100011 */ + 0x67, /* 01100111 */ + 0xe6, /* 11100110 */ + 0xc0, /* 11000000 */ + + /* 15 0x0f '^O' */ + 0x18, /* 00011000 */ + 0xdb, /* 11011011 */ + 0x3c, /* 00111100 */ + 0xe7, /* 11100111 */ + 0xe7, /* 11100111 */ + 0x3c, /* 00111100 */ + 0xdb, /* 11011011 */ + 0x18, /* 00011000 */ + + /* 16 0x10 '^P' */ + 0x80, /* 10000000 */ + 0xe0, /* 11100000 */ + 0xf8, /* 11111000 */ + 0xfe, /* 11111110 */ + 0xf8, /* 11111000 */ + 0xe0, /* 11100000 */ + 0x80, /* 10000000 */ + 0x00, /* 00000000 */ + + /* 17 0x11 '^Q' */ + 0x02, /* 00000010 */ + 0x0e, /* 00001110 */ + 0x3e, /* 00111110 */ + 0xfe, /* 11111110 */ + 0x3e, /* 00111110 */ + 0x0e, /* 00001110 */ + 0x02, /* 00000010 */ + 0x00, /* 00000000 */ + + /* 18 0x12 '^R' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + + /* 19 0x13 '^S' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + + /* 20 0x14 '^T' */ + 0x7f, /* 01111111 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7b, /* 01111011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x00, /* 00000000 */ + + /* 21 0x15 '^U' */ + 0x3e, /* 00111110 */ + 0x61, /* 01100001 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x86, /* 10000110 */ + 0x7c, /* 01111100 */ + + /* 22 0x16 '^V' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 23 0x17 '^W' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + + /* 24 0x18 '^X' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 25 0x19 '^Y' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 26 0x1a '^Z' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0xfe, /* 11111110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 27 0x1b '^[' */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xfe, /* 11111110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 28 0x1c '^\' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 29 0x1d '^]' */ + 0x00, /* 00000000 */ + 0x24, /* 00100100 */ + 0x66, /* 01100110 */ + 0xff, /* 11111111 */ + 0x66, /* 01100110 */ + 0x24, /* 00100100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 30 0x1e '^^' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 31 0x1f '^_' */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 32 0x20 ' ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 33 0x21 '!' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 34 0x22 '"' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x24, /* 00100100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 35 0x23 '#' */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 36 0x24 '$' */ + 0x18, /* 00011000 */ + 0x3e, /* 00111110 */ + 0x60, /* 01100000 */ + 0x3c, /* 00111100 */ + 0x06, /* 00000110 */ + 0x7c, /* 01111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 37 0x25 '%' */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xcc, /* 11001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x66, /* 01100110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 38 0x26 '&' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 39 0x27 ''' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 40 0x28 '(' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + + /* 41 0x29 ')' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + + /* 42 0x2a '*' */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0xff, /* 11111111 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 43 0x2b '+' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 44 0x2c ',' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + + /* 45 0x2d '-' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 46 0x2e '.' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 47 0x2f '/' */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0x80, /* 10000000 */ + 0x00, /* 00000000 */ + + /* 48 0x30 '0' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 49 0x31 '1' */ + 0x18, /* 00011000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 50 0x32 '2' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x1c, /* 00011100 */ + 0x30, /* 00110000 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 51 0x33 '3' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x3c, /* 00111100 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 52 0x34 '4' */ + 0x1c, /* 00011100 */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xfe, /* 11111110 */ + 0x0c, /* 00001100 */ + 0x1e, /* 00011110 */ + 0x00, /* 00000000 */ + + /* 53 0x35 '5' */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfc, /* 11111100 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 54 0x36 '6' */ + 0x38, /* 00111000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0xfc, /* 11111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 55 0x37 '7' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + + /* 56 0x38 '8' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 57 0x39 '9' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 58 0x3a ':' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 59 0x3b ';' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + + /* 60 0x3c '<' */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + + /* 61 0x3d '=' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 62 0x3e '>' */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + + /* 63 0x3f '?' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 64 0x40 '@' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xde, /* 11011110 */ + 0xde, /* 11011110 */ + 0xde, /* 11011110 */ + 0xc0, /* 11000000 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 65 0x41 'A' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 66 0x42 'B' */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + + /* 67 0x43 'C' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 68 0x44 'D' */ + 0xf8, /* 11111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + + /* 69 0x45 'E' */ + 0xfe, /* 11111110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x62, /* 01100010 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 70 0x46 'F' */ + 0xfe, /* 11111110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 71 0x47 'G' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xce, /* 11001110 */ + 0x66, /* 01100110 */ + 0x3a, /* 00111010 */ + 0x00, /* 00000000 */ + + /* 72 0x48 'H' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 73 0x49 'I' */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 74 0x4a 'J' */ + 0x1e, /* 00011110 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 75 0x4b 'K' */ + 0xe6, /* 11100110 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 76 0x4c 'L' */ + 0xf0, /* 11110000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 77 0x4d 'M' */ + 0xc6, /* 11000110 */ + 0xee, /* 11101110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 78 0x4e 'N' */ + 0xc6, /* 11000110 */ + 0xe6, /* 11100110 */ + 0xf6, /* 11110110 */ + 0xde, /* 11011110 */ + 0xce, /* 11001110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 79 0x4f 'O' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 80 0x50 'P' */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 81 0x51 'Q' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xce, /* 11001110 */ + 0x7c, /* 01111100 */ + 0x0e, /* 00001110 */ + + /* 82 0x52 'R' */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 83 0x53 'S' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 84 0x54 'T' */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x5a, /* 01011010 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 85 0x55 'U' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 86 0x56 'V' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 87 0x57 'W' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 88 0x58 'X' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 89 0x59 'Y' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 90 0x5a 'Z' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x8c, /* 10001100 */ + 0x18, /* 00011000 */ + 0x32, /* 00110010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 91 0x5b '[' */ + 0x3c, /* 00111100 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 92 0x5c '\' */ + 0xc0, /* 11000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x02, /* 00000010 */ + 0x00, /* 00000000 */ + + /* 93 0x5d ']' */ + 0x3c, /* 00111100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 94 0x5e '^' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 95 0x5f '_' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + + /* 96 0x60 '`' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 97 0x61 'a' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 98 0x62 'b' */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x7c, /* 01111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + + /* 99 0x63 'c' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 100 0x64 'd' */ + 0x1c, /* 00011100 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 101 0x65 'e' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 102 0x66 'f' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x60, /* 01100000 */ + 0xf8, /* 11111000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 103 0x67 'g' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0xf8, /* 11111000 */ + + /* 104 0x68 'h' */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x6c, /* 01101100 */ + 0x76, /* 01110110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 105 0x69 'i' */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 106 0x6a 'j' */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + + /* 107 0x6b 'k' */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 108 0x6c 'l' */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 109 0x6d 'm' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xec, /* 11101100 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0x00, /* 00000000 */ + + /* 110 0x6e 'n' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + + /* 111 0x6f 'o' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 112 0x70 'p' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + + /* 113 0x71 'q' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0x1e, /* 00011110 */ + + /* 114 0x72 'r' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x76, /* 01110110 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 115 0x73 's' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x06, /* 00000110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + + /* 116 0x74 't' */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0xfc, /* 11111100 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x36, /* 00110110 */ + 0x1c, /* 00011100 */ + 0x00, /* 00000000 */ + + /* 117 0x75 'u' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 118 0x76 'v' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 119 0x77 'w' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 120 0x78 'x' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 121 0x79 'y' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0xfc, /* 11111100 */ + + /* 122 0x7a 'z' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x4c, /* 01001100 */ + 0x18, /* 00011000 */ + 0x32, /* 00110010 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 123 0x7b '{' */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x0e, /* 00001110 */ + 0x00, /* 00000000 */ + + /* 124 0x7c '|' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 125 0x7d '}' */ + 0x70, /* 01110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + + /* 126 0x7e '~' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 127 0x7f '' */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 128 0x80 '€' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0x78, /* 01111000 */ + + /* 129 0x81 '' */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 130 0x82 '‚' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 131 0x83 'ƒ' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 132 0x84 '„' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 133 0x85 '…' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 134 0x86 '†' */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 135 0x87 '‡' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x7e, /* 01111110 */ + 0x0c, /* 00001100 */ + 0x38, /* 00111000 */ + + /* 136 0x88 'ˆ' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 137 0x89 '‰' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 138 0x8a 'Š' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 139 0x8b '‹' */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 140 0x8c 'Œ' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 141 0x8d '' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 142 0x8e 'Ž' */ + 0xc6, /* 11000110 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 143 0x8f '' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 144 0x90 '' */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xf8, /* 11111000 */ + 0xc0, /* 11000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 145 0x91 '‘' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0xd8, /* 11011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 146 0x92 '’' */ + 0x3e, /* 00111110 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xfe, /* 11111110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xce, /* 11001110 */ + 0x00, /* 00000000 */ + + /* 147 0x93 '“' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 148 0x94 '”' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 149 0x95 '•' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 150 0x96 '–' */ + 0x78, /* 01111000 */ + 0x84, /* 10000100 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 151 0x97 '—' */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 152 0x98 '˜' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0xfc, /* 11111100 */ + + /* 153 0x99 '™' */ + 0xc6, /* 11000110 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 154 0x9a 'š' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 155 0x9b '›' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 156 0x9c 'œ' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x64, /* 01100100 */ + 0xf0, /* 11110000 */ + 0x60, /* 01100000 */ + 0x66, /* 01100110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + + /* 157 0x9d '' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 158 0x9e 'ž' */ + 0xf8, /* 11111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xfa, /* 11111010 */ + 0xc6, /* 11000110 */ + 0xcf, /* 11001111 */ + 0xc6, /* 11000110 */ + 0xc7, /* 11000111 */ + + /* 159 0x9f 'Ÿ' */ + 0x0e, /* 00001110 */ + 0x1b, /* 00011011 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + + /* 160 0xa0 ' ' */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 161 0xa1 '¡' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 162 0xa2 '¢' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 163 0xa3 '£' */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 164 0xa4 '¤' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + + /* 165 0xa5 '¥' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0xe6, /* 11100110 */ + 0xf6, /* 11110110 */ + 0xde, /* 11011110 */ + 0xce, /* 11001110 */ + 0x00, /* 00000000 */ + + /* 166 0xa6 '¦' */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x3e, /* 00111110 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 167 0xa7 '§' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 168 0xa8 '¨' */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x63, /* 01100011 */ + 0x3e, /* 00111110 */ + 0x00, /* 00000000 */ + + /* 169 0xa9 '©' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 170 0xaa 'ª' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 171 0xab '«' */ + 0x63, /* 01100011 */ + 0xe6, /* 11100110 */ + 0x6c, /* 01101100 */ + 0x7e, /* 01111110 */ + 0x33, /* 00110011 */ + 0x66, /* 01100110 */ + 0xcc, /* 11001100 */ + 0x0f, /* 00001111 */ + + /* 172 0xac '¬' */ + 0x63, /* 01100011 */ + 0xe6, /* 11100110 */ + 0x6c, /* 01101100 */ + 0x7a, /* 01111010 */ + 0x36, /* 00110110 */ + 0x6a, /* 01101010 */ + 0xdf, /* 11011111 */ + 0x06, /* 00000110 */ + + /* 173 0xad '­' */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 174 0xae '®' */ + 0x00, /* 00000000 */ + 0x33, /* 00110011 */ + 0x66, /* 01100110 */ + 0xcc, /* 11001100 */ + 0x66, /* 01100110 */ + 0x33, /* 00110011 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 175 0xaf '¯' */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0x66, /* 01100110 */ + 0x33, /* 00110011 */ + 0x66, /* 01100110 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 176 0xb0 '°' */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + + /* 177 0xb1 '±' */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + + /* 178 0xb2 '²' */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + + /* 179 0xb3 '³' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 180 0xb4 '´' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 181 0xb5 'µ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 182 0xb6 '¶' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 183 0xb7 '·' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 184 0xb8 '¸' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 185 0xb9 '¹' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x06, /* 00000110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 186 0xba 'º' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 187 0xbb '»' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x06, /* 00000110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 188 0xbc '¼' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x06, /* 00000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 189 0xbd '½' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 190 0xbe '¾' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 191 0xbf '¿' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 192 0xc0 'À' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 193 0xc1 'Á' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 194 0xc2 'Â' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 195 0xc3 'Ã' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 196 0xc4 'Ä' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 197 0xc5 'Å' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 198 0xc6 'Æ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 199 0xc7 'Ç' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 200 0xc8 'È' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x30, /* 00110000 */ + 0x3f, /* 00111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 201 0xc9 'É' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x30, /* 00110000 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 202 0xca 'Ê' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf7, /* 11110111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 203 0xcb 'Ë' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xf7, /* 11110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 204 0xcc 'Ì' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x30, /* 00110000 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 205 0xcd 'Í' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 206 0xce 'Î' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf7, /* 11110111 */ + 0x00, /* 00000000 */ + 0xf7, /* 11110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 207 0xcf 'Ï' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 208 0xd0 'Ð' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 209 0xd1 'Ñ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 210 0xd2 'Ò' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 211 0xd3 'Ó' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x3f, /* 00111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 212 0xd4 'Ô' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 213 0xd5 'Õ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 214 0xd6 'Ö' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 215 0xd7 '×' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xff, /* 11111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 216 0xd8 'Ø' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 217 0xd9 'Ù' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 218 0xda 'Ú' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 219 0xdb 'Û' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 220 0xdc 'Ü' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 221 0xdd 'Ý' */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + + /* 222 0xde 'Þ' */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + + /* 223 0xdf 'ß' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 224 0xe0 'à' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0xc8, /* 11001000 */ + 0xdc, /* 11011100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 225 0xe1 'á' */ + 0x78, /* 01111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xd8, /* 11011000 */ + 0xcc, /* 11001100 */ + 0xc6, /* 11000110 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + + /* 226 0xe2 'â' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + + /* 227 0xe3 'ã' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 228 0xe4 'ä' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 229 0xe5 'å' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + + /* 230 0xe6 'æ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0xc0, /* 11000000 */ + + /* 231 0xe7 'ç' */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 232 0xe8 'è' */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + + /* 233 0xe9 'é' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 234 0xea 'ê' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xee, /* 11101110 */ + 0x00, /* 00000000 */ + + /* 235 0xeb 'ë' */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x3e, /* 00111110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 236 0xec 'ì' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 237 0xed 'í' */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x7e, /* 01111110 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7e, /* 01111110 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + + /* 238 0xee 'î' */ + 0x1e, /* 00011110 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x7e, /* 01111110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x1e, /* 00011110 */ + 0x00, /* 00000000 */ + + /* 239 0xef 'ï' */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 240 0xf0 'ð' */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 241 0xf1 'ñ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 242 0xf2 'ò' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 243 0xf3 'ó' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 244 0xf4 'ô' */ + 0x0e, /* 00001110 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 245 0xf5 'õ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + + /* 246 0xf6 'ö' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 247 0xf7 '÷' */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 248 0xf8 'ø' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 249 0xf9 'ù' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 250 0xfa 'ú' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 251 0xfb 'û' */ + 0x0f, /* 00001111 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0xec, /* 11101100 */ + 0x6c, /* 01101100 */ + 0x3c, /* 00111100 */ + 0x1c, /* 00011100 */ + + /* 252 0xfc 'ü' */ + 0x6c, /* 01101100 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 253 0xfd 'ý' */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 254 0xfe 'þ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 255 0xff 'ÿ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ }; diff --git a/src/extralibs/hsusb_v30x.c b/src/extralibs/hsusb_v30x.c index 055375b..73aabfb 100644 --- a/src/extralibs/hsusb_v30x.c +++ b/src/extralibs/hsusb_v30x.c @@ -2,29 +2,29 @@ #include "ch32fun.h" #include -#define UEP_CTRL_H(n) (((uint16_t*)&USBHSD->UEP0_TX_CTRL)[n*2]) +#define UEP_CTRL_H(n) (((uint16_t *)&USBHSD->UEP0_TX_CTRL)[n * 2]) struct _USBState HSUSBCTX; // based on https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/USB/USBHS/DEVICE/CompositeKM // Mask for the combined USBHSD->INT_FG + USBHSD->INT_ST -#define CRB_U_IS_NAK (1<<7) -#define CTOG_MATCH_SYNC (1<<6) -#define CRB_UIF_SETUP_ACT (1<<5) // CRB_U_SIE_FREE on USBFS -#define CRB_UIF_FIFO_OV (1<<4) -#define CRB_UIF_HST_SOF (1<<3) -#define CRB_UIF_SUSPEND (1<<2) -#define CRB_UIF_TRANSFER (1<<1) -#define CRB_UIF_BUS_RST (1<<0) -#define CSETUP_ACT (1<<15) -#define CRB_UIS_TOG_OK (1<<14) -#define CMASK_UIS_TOKEN (3<<12) -#define CMASK_UIS_ENDP (0xf<<8) +#define CRB_U_IS_NAK (1 << 7) +#define CTOG_MATCH_SYNC (1 << 6) +#define CRB_UIF_SETUP_ACT (1 << 5) // CRB_U_SIE_FREE on USBFS +#define CRB_UIF_FIFO_OV (1 << 4) +#define CRB_UIF_HST_SOF (1 << 3) +#define CRB_UIF_SUSPEND (1 << 2) +#define CRB_UIF_TRANSFER (1 << 1) +#define CRB_UIF_BUS_RST (1 << 0) +#define CSETUP_ACT (1 << 15) +#define CRB_UIS_TOG_OK (1 << 14) +#define CMASK_UIS_TOKEN (3 << 12) +#define CMASK_UIS_ENDP (0xf << 8) -#define CUIS_TOKEN_OUT 0x0 -#define CUIS_TOKEN_SOF 0x1 -#define CUIS_TOKEN_IN 0x2 +#define CUIS_TOKEN_OUT 0x0 +#define CUIS_TOKEN_SOF 0x1 +#define CUIS_TOKEN_IN 0x2 #define CUIS_TOKEN_SETUP 0x3 #if 0 @@ -44,7 +44,7 @@ static inline void DMA7FastCopy( uint8_t * dest, const uint8_t * src, int len ) DMA_MemoryInc_Enable | DMA_PeripheralInc_Enable | DMA_Mode_Normal | DMA_CFGR1_EN; -#if !( FUSB_CURSED_TURBO_DMA == 1 ) +#if !(FUSB_CURSED_TURBO_DMA == 1) // Somehow, it seems to work (unsafely) without this. // Really, though, it's probably fine. while( DMA1_Channel7->CNTR ); @@ -57,607 +57,595 @@ static inline void DMA7FastCopyComplete() { while( DMA1_Channel7->CNTR ); } void USBHS_InternalFinishSetup(); -//void USBHSWakeUp_IRQHandler(void) __attribute((interrupt)); -//void USBHSWakeUp_IRQHandler(void) +// void USBHSWakeUp_IRQHandler(void) __attribute((interrupt)); +// void USBHSWakeUp_IRQHandler(void) //{ // printf( "USBHSWakeUp MSTATUS:%08x MTVAL:%08x MCAUSE:%08x MEPC:%08x\n", (int)__get_MSTATUS(), (int)__get_MTVAL(), (int)__get_MCAUSE(), (int)__get_MEPC() ); -//} +// } extern uint8_t scratchpad[]; -void USBHS_IRQHandler(void) __attribute((interrupt)); -void USBHS_IRQHandler(void) +void USBHS_IRQHandler(void) __attribute((interrupt)); +void USBHS_IRQHandler(void) { - // Based on https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/USB/USBHS/DEVICE/CompositeKM/User/ch32v30x_usbhs_device.c - // Combined FG + ST flag - uint16_t intfgst = *(uint16_t*)(&USBHSD->INT_FG); - int len = 0; - struct _USBState * ctx = &HSUSBCTX; - uint8_t * ctrl0buff = CTRL0BUFF; + // Based on https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/USB/USBHS/DEVICE/CompositeKM/User/ch32v30x_usbhs_device.c + // Combined FG + ST flag + uint16_t intfgst = *(uint16_t *)(&USBHSD->INT_FG); + int len = 0; + struct _USBState *ctx = &HSUSBCTX; + uint8_t *ctrl0buff = CTRL0BUFF; - if( intfgst & ( CRB_UIF_SETUP_ACT ) ) - { - // On the Chapter 22 USB, SETUP Requests are handled here instead of in UIF_TRANSFER, with TOKEN_SETUP. - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + if (intfgst & (CRB_UIF_SETUP_ACT)) + { + // On the Chapter 22 USB, SETUP Requests are handled here instead of in UIF_TRANSFER, with TOKEN_SETUP. + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - /* Store All Setup Values */ - int USBHS_SetupReqType = HSUSBCTX.USBHS_SetupReqType = pUSBHS_SetupReqPak->bmRequestType; - int USBHS_SetupReqCode = HSUSBCTX.USBHS_SetupReqCode = pUSBHS_SetupReqPak->bRequest; - int USBHS_SetupReqLen = HSUSBCTX.USBHS_SetupReqLen = pUSBHS_SetupReqPak->wLength; - int USBHS_SetupReqIndex = pUSBHS_SetupReqPak->wIndex; - int USBHS_IndexValue = HSUSBCTX.USBHS_IndexValue = ( pUSBHS_SetupReqPak->wIndex << 16 ) | pUSBHS_SetupReqPak->wValue; - len = 0; + /* Store All Setup Values */ + int USBHS_SetupReqType = HSUSBCTX.USBHS_SetupReqType = pUSBHS_SetupReqPak->bmRequestType; + int USBHS_SetupReqCode = HSUSBCTX.USBHS_SetupReqCode = pUSBHS_SetupReqPak->bRequest; + int USBHS_SetupReqLen = HSUSBCTX.USBHS_SetupReqLen = pUSBHS_SetupReqPak->wLength; + int USBHS_SetupReqIndex = pUSBHS_SetupReqPak->wIndex; + int USBHS_IndexValue = HSUSBCTX.USBHS_IndexValue = (pUSBHS_SetupReqPak->wIndex << 16) | pUSBHS_SetupReqPak->wValue; + len = 0; - //printf( "Setup: %d %d %d %d %d\n", USBHS_SetupReqType, USBHS_SetupReqCode, USBHS_SetupReqLen, - // USBHS_SetupReqIndex, USBHS_IndexValue ); + // printf( "Setup: %d %d %d %d %d\n", USBHS_SetupReqType, USBHS_SetupReqCode, USBHS_SetupReqLen, + // USBHS_SetupReqIndex, USBHS_IndexValue ); - if( ( USBHS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) - { -#if HUSB_HID_INTERFACES > 0 - if( ( USBHS_SetupReqType & USB_REQ_TYP_MASK ) == USB_REQ_TYP_CLASS ) - { - /* Class Request */ - //printf( "REQ: %d [%02x %02x %04x %04x]\n", USBHS_SetupReqCode, pUSBHS_SetupReqPak->bmRequestType, pUSBHS_SetupReqPak->bRequest, pUSBHS_SetupReqPak->wValue, pUSBHS_SetupReqPak->wLength ); - switch( USBHS_SetupReqCode ) - { - case HID_SET_REPORT: + if ((USBHS_SetupReqType & USB_REQ_TYP_MASK) != USB_REQ_TYP_STANDARD) + { +#if HUSB_HID_INTERFACES > 0 + if ((USBHS_SetupReqType & USB_REQ_TYP_MASK) == USB_REQ_TYP_CLASS) + { + /* Class Request */ + // printf( "REQ: %d [%02x %02x %04x %04x]\n", USBHS_SetupReqCode, pUSBHS_SetupReqPak->bmRequestType, pUSBHS_SetupReqPak->bRequest, pUSBHS_SetupReqPak->wValue, pUSBHS_SetupReqPak->wLength ); + switch (USBHS_SetupReqCode) + { + case HID_SET_REPORT: #if HUSB_HID_USER_REPORTS - len = HandleHidUserSetReportSetup( ctx, pUSBHS_SetupReqPak ); - if( len < 0 ) goto sendstall; - ctx->USBHS_SetupReqLen = len; - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1; - goto replycomplete; - case HID_GET_REPORT: - len = HandleHidUserGetReportSetup( ctx, pUSBHS_SetupReqPak ); - if( len < 0 ) goto sendstall; - ctx->USBHS_SetupReqLen = len; - len = len >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : len; - if( !ctx->pCtrlPayloadPtr ) - { - len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); - } - else - { - //DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); - memcpy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); - ctx->pCtrlPayloadPtr += len; - } - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - ctx->USBHS_SetupReqLen -= len; - goto replycomplete; + len = HandleHidUserSetReportSetup(ctx, pUSBHS_SetupReqPak); + if (len < 0) goto sendstall; + ctx->USBHS_SetupReqLen = len; + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1; + goto replycomplete; + case HID_GET_REPORT: + len = HandleHidUserGetReportSetup(ctx, pUSBHS_SetupReqPak); + if (len < 0) goto sendstall; + ctx->USBHS_SetupReqLen = len; + len = len >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : len; + if (!ctx->pCtrlPayloadPtr) + { + len = HandleHidUserReportDataIn(ctx, ctrl0buff, len); + } + else + { + // DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + memcpy(ctrl0buff, ctx->pCtrlPayloadPtr, len); + ctx->pCtrlPayloadPtr += len; + } + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + ctx->USBHS_SetupReqLen -= len; + goto replycomplete; #endif - break; + break; + case HID_SET_IDLE: + if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) + HSUSBCTX.USBHS_HidIdle[USBHS_SetupReqIndex] = (uint8_t)(USBHS_IndexValue >> 8); + break; + case HID_SET_PROTOCOL: + if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) + HSUSBCTX.USBHS_HidProtocol[USBHS_SetupReqIndex] = (uint8_t)USBHS_IndexValue; + break; - case HID_SET_IDLE: - if( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) - HSUSBCTX.USBHS_HidIdle[ USBHS_SetupReqIndex ] = (uint8_t)( USBHS_IndexValue >> 8 ); - break; - case HID_SET_PROTOCOL: - if ( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) - HSUSBCTX.USBHS_HidProtocol[USBHS_SetupReqIndex] = (uint8_t)USBHS_IndexValue; - break; + case HID_GET_IDLE: + if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) + { + ctrl0buff[0] = HSUSBCTX.USBHS_HidIdle[USBHS_SetupReqIndex]; + len = 1; + } + break; - case HID_GET_IDLE: - if( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) - { - ctrl0buff[0] = HSUSBCTX.USBHS_HidIdle[ USBHS_SetupReqIndex ]; - len = 1; - } - break; + case HID_GET_PROTOCOL: + if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) + { + ctrl0buff[0] = HSUSBCTX.USBHS_HidProtocol[USBHS_SetupReqIndex]; + len = 1; + } + break; - case HID_GET_PROTOCOL: - if( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) - { - ctrl0buff[0] = HSUSBCTX.USBHS_HidProtocol[ USBHS_SetupReqIndex ]; - len = 1; - } - break; - - default: - goto sendstall; - break; - } - } + default: + goto sendstall; + break; + } + } #else - ; + ; #endif - } - else - { - /* usb standard request processing */ - switch( USBHS_SetupReqCode ) - { - /* get device/configuration/string/report/... descriptors */ - case USB_GET_DESCRIPTOR: - { - const struct descriptor_list_struct * e = descriptor_list; - const struct descriptor_list_struct * e_end = e + DESCRIPTOR_LIST_ENTRIES; - for( ; e != e_end; e++ ) - { - if( e->lIndexValue == USBHS_IndexValue ) - { - ctx->pCtrlPayloadPtr = (uint8_t*)e->addr; - len = e->length; - break; - } - } - if( e == e_end ) - { - goto sendstall; - } + } + else + { + /* usb standard request processing */ + switch (USBHS_SetupReqCode) + { + /* get device/configuration/string/report/... descriptors */ + case USB_GET_DESCRIPTOR: + { + const struct descriptor_list_struct *e = descriptor_list; + const struct descriptor_list_struct *e_end = e + DESCRIPTOR_LIST_ENTRIES; + for (; e != e_end; e++) + { + if (e->lIndexValue == USBHS_IndexValue) + { + ctx->pCtrlPayloadPtr = (uint8_t *)e->addr; + len = e->length; + break; + } + } + if (e == e_end) + { + goto sendstall; + } + /* Copy Descriptors to Endp0 DMA buffer */ + int totalLen = USBHS_SetupReqLen; + if (totalLen > len) + { + totalLen = len; + } + len = (totalLen >= DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : totalLen; + // DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); //memcpy( CTRL0BUFF, ctx->pCtrlPayloadPtr, len ); + memcpy(ctrl0buff, ctx->pCtrlPayloadPtr, len); + ctx->USBHS_SetupReqLen = totalLen - len; + ctx->pCtrlPayloadPtr += len; + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + goto replycomplete; + } - /* Copy Descriptors to Endp0 DMA buffer */ - int totalLen = USBHS_SetupReqLen; - if( totalLen > len ) - { - totalLen = len; - } - len = ( totalLen >= DEF_USBD_UEP0_SIZE ) ? DEF_USBD_UEP0_SIZE : totalLen; - //DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); //memcpy( CTRL0BUFF, ctx->pCtrlPayloadPtr, len ); - memcpy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); - ctx->USBHS_SetupReqLen = totalLen - len; - ctx->pCtrlPayloadPtr += len; - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - goto replycomplete; - } + /* Set usb address */ + case USB_SET_ADDRESS: + ctx->USBHS_DevAddr = (uint16_t)(ctx->USBHS_IndexValue & 0xFF); + break; - /* Set usb address */ - case USB_SET_ADDRESS: - ctx->USBHS_DevAddr = (uint16_t)( ctx->USBHS_IndexValue & 0xFF ); - break; + /* Get usb configuration now set */ + case USB_GET_CONFIGURATION: + ctrl0buff[0] = ctx->USBHS_DevConfig; + if (ctx->USBHS_SetupReqLen > 1) + ctx->USBHS_SetupReqLen = 1; + break; - /* Get usb configuration now set */ - case USB_GET_CONFIGURATION: - ctrl0buff[0] = ctx->USBHS_DevConfig; - if( ctx->USBHS_SetupReqLen > 1 ) - ctx->USBHS_SetupReqLen = 1; - break; + /* Set usb configuration to use */ + case USB_SET_CONFIGURATION: + ctx->USBHS_DevConfig = (uint8_t)(ctx->USBHS_IndexValue & 0xFF); + ctx->USBHS_DevEnumStatus = 0x01; + break; - /* Set usb configuration to use */ - case USB_SET_CONFIGURATION: - ctx->USBHS_DevConfig = (uint8_t)( ctx->USBHS_IndexValue & 0xFF ); - ctx->USBHS_DevEnumStatus = 0x01; - break; - - /* Clear or disable one usb feature */ - case USB_CLEAR_FEATURE: + /* Clear or disable one usb feature */ + case USB_CLEAR_FEATURE: #if HUSB_SUPPORTS_SLEEP - if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) - { - /* clear one device feature */ - if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) - { - /* clear usb sleep status, device not prepare to sleep */ - ctx->USBHS_DevSleepStatus &= ~0x01; - } - else - { - goto sendstall; - } - } - else + if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_DEVICE) + { + /* clear one device feature */ + if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_REMOTE_WAKEUP) + { + /* clear usb sleep status, device not prepare to sleep */ + ctx->USBHS_DevSleepStatus &= ~0x01; + } + else + { + goto sendstall; + } + } + else #endif - if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) - { - if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) - { - /* Clear End-point Feature */ - int ep = USBHS_SetupReqIndex & 0xf; - if( ( USBHS_SetupReqIndex & DEF_UEP_IN ) && ep < HUSB_CONFIG_EPS ) - { - UEP_CTRL_H(ep) = USBHS_UEP_T_TOG_DATA0 | USBHS_UEP_T_RES_NAK; - } - else - { - goto sendstall; - } - } - else - { - goto sendstall; - } - } - else - { - goto sendstall; - } - break; + if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP) + { + if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_ENDP_HALT) + { + /* Clear End-point Feature */ + int ep = USBHS_SetupReqIndex & 0xf; + if ((USBHS_SetupReqIndex & DEF_UEP_IN) && ep < HUSB_CONFIG_EPS) + { + UEP_CTRL_H(ep) = USBHS_UEP_T_TOG_DATA0 | USBHS_UEP_T_RES_NAK; + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + break; - /* set or enable one usb feature */ - case USB_SET_FEATURE: - if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) - { + /* set or enable one usb feature */ + case USB_SET_FEATURE: + if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_DEVICE) + { #if HUSB_SUPPORTS_SLEEP - /* Set Device Feature */ - if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) - { - /* Set Wake-up flag, device prepare to sleep */ - USBHS_DevSleepStatus |= 0x01; - } - else + /* Set Device Feature */ + if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_REMOTE_WAKEUP) + { + /* Set Wake-up flag, device prepare to sleep */ + USBHS_DevSleepStatus |= 0x01; + } + else #endif - { - goto sendstall; - } - } - else if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) - { - /* Set Endpoint Feature */ - if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) - { - int ep = USBHS_SetupReqIndex & 0xf; - if( ( USBHS_SetupReqIndex & DEF_UEP_IN ) && ep < HUSB_CONFIG_EPS ) - UEP_CTRL_H(ep) = ( UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_STALL; - } - else - goto sendstall; - } - else - goto sendstall; - break; + { + goto sendstall; + } + } + else if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP) + { + /* Set Endpoint Feature */ + if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_ENDP_HALT) + { + int ep = USBHS_SetupReqIndex & 0xf; + if ((USBHS_SetupReqIndex & DEF_UEP_IN) && ep < HUSB_CONFIG_EPS) + UEP_CTRL_H(ep) = (UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_STALL; + } + else + goto sendstall; + } + else + goto sendstall; + break; - /* This request allows the host to select another setting for the specified interface */ - case USB_GET_INTERFACE: - ctrl0buff[0] = 0x00; - if( USBHS_SetupReqLen > 1 ) USBHS_SetupReqLen = 1; - break; + /* This request allows the host to select another setting for the specified interface */ + case USB_GET_INTERFACE: + ctrl0buff[0] = 0x00; + if (USBHS_SetupReqLen > 1) USBHS_SetupReqLen = 1; + break; - case USB_SET_INTERFACE: - break; + case USB_SET_INTERFACE: + break; - /* host get status of specified device/interface/end-points */ - case USB_GET_STATUS: - ctrl0buff[0] = 0x00; - ctrl0buff[1] = 0x00; - if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) - { + /* host get status of specified device/interface/end-points */ + case USB_GET_STATUS: + ctrl0buff[0] = 0x00; + ctrl0buff[1] = 0x00; + if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_DEVICE) + { #if FUSB_SUPPORTS_SLEEP - ctrl0buff[0] = (ctx->USBHS_DevSleepStatus & 0x01)<<1; + ctrl0buff[0] = (ctx->USBHS_DevSleepStatus & 0x01) << 1; #else - ctrl0buff[0] = 0x00; + ctrl0buff[0] = 0x00; #endif - } - else if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) - { - int ep = USBHS_SetupReqIndex & 0xf; - if( ( USBHS_SetupReqIndex & DEF_UEP_IN ) && ep < HUSB_CONFIG_EPS ) - ctrl0buff[0] = ( UEP_CTRL_H(ep) & USBHS_UEP_T_RES_MASK ) == USBHS_UEP_T_RES_STALL; - else - goto sendstall; - } - else - goto sendstall; - if( USBHS_SetupReqLen > 2 ) - USBHS_SetupReqLen = 2; - break; + } + else if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP) + { + int ep = USBHS_SetupReqIndex & 0xf; + if ((USBHS_SetupReqIndex & DEF_UEP_IN) && ep < HUSB_CONFIG_EPS) + ctrl0buff[0] = (UEP_CTRL_H(ep) & USBHS_UEP_T_RES_MASK) == USBHS_UEP_T_RES_STALL; + else + goto sendstall; + } + else + goto sendstall; + if (USBHS_SetupReqLen > 2) + USBHS_SetupReqLen = 2; + break; - default: - goto sendstall; - break; - } - } + default: + goto sendstall; + break; + } + } + { + /* end-point 0 data Tx/Rx */ + if (USBHS_SetupReqType & DEF_UEP_IN) + { + len = (USBHS_SetupReqLen > DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : USBHS_SetupReqLen; + USBHS_SetupReqLen -= len; + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + } + else + { + if (USBHS_SetupReqLen == 0) + { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + } + else + { + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + } + } + } - { - /* end-point 0 data Tx/Rx */ - if( USBHS_SetupReqType & DEF_UEP_IN ) - { - len = ( USBHS_SetupReqLen > DEF_USBD_UEP0_SIZE )? DEF_USBD_UEP0_SIZE : USBHS_SetupReqLen; - USBHS_SetupReqLen -= len; - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - } - else - { - if( USBHS_SetupReqLen == 0 ) - { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - } - else - { - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - } - } - } + goto replycomplete; - goto replycomplete; + // This might look a little weird, for error handling but it saves a nontrivial amount of storage, and simplifies + // control flow to hard-abort here. + sendstall: + // if one request not support, return stall. Stall means permanent error. + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_STALL; + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_STALL; + replycomplete:; + } + if (intfgst & (CRB_UIF_TRANSFER)) + { + int token = (intfgst & CMASK_UIS_TOKEN) >> 12; + int ep = (intfgst & CMASK_UIS_ENDP) >> 8; + switch (token) + { + case CUIS_TOKEN_IN: + if (ep) + { + if (ep < HUSB_CONFIG_EPS) + { + UEP_CTRL_H(ep) = (UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_NAK; + UEP_CTRL_H(ep) ^= USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_Endp_Busy[ep] = 0; + // Don't set EP in here. Wait for out. + // Optimization: Could we set EP here? + } + } + else + { + /* end-point 0 data in interrupt */ + if (ctx->USBHS_SetupReqLen == 0) + { + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + } - // This might look a little weird, for error handling but it saves a nontrivial amount of storage, and simplifies - // control flow to hard-abort here. - sendstall: - // if one request not support, return stall. Stall means permanent error. - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_STALL; - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_STALL; - replycomplete: - ; - } - if( intfgst & ( CRB_UIF_TRANSFER ) ) - { - int token = ( intfgst & CMASK_UIS_TOKEN) >> 12; - int ep = ( intfgst & CMASK_UIS_ENDP ) >> 8; - switch ( token ) - { - case CUIS_TOKEN_IN: - if( ep ) - { - if( ep < HUSB_CONFIG_EPS ) - { - UEP_CTRL_H(ep) = ( UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_NAK; - UEP_CTRL_H(ep) ^= USBHS_UEP_T_TOG_DATA1; - ctx->USBHS_Endp_Busy[ ep ] = 0; - // Don't set EP in here. Wait for out. - // Optimization: Could we set EP here? - } - } - else - { - /* end-point 0 data in interrupt */ - if( ctx->USBHS_SetupReqLen == 0 ) - { - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - } + if (ctx->pCtrlPayloadPtr) + { + // Shortcut mechanism, for descriptors or if the user wants it. + len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; + // DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); // FYI -> Would need to do this if using DMA + memcpy(ctrl0buff, ctx->pCtrlPayloadPtr, len); + ctx->USBHS_SetupReqLen -= len; + if (ctx->USBHS_SetupReqLen > 0) + ctx->pCtrlPayloadPtr += len; + else + ctx->pCtrlPayloadPtr = 0; - if( ctx->pCtrlPayloadPtr ) - { - // Shortcut mechanism, for descriptors or if the user wants it. - len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; - //DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); // FYI -> Would need to do this if using DMA - memcpy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); - ctx->USBHS_SetupReqLen -= len; - if( ctx->USBHS_SetupReqLen > 0 ) - ctx->pCtrlPayloadPtr += len; - else - ctx->pCtrlPayloadPtr = 0; + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; + } + else if ((ctx->USBHS_SetupReqType & USB_REQ_TYP_MASK) != USB_REQ_TYP_STANDARD) + { +#if HUSB_HID_USER_REPORTS + len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; + if (len && HSUSBCTX.USBHS_SetupReqCode == HID_GET_REPORT) + { + len = HandleHidUserReportDataIn(ctx, ctrl0buff, len); + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_SetupReqLen -= len; + ctx->pCtrlPayloadPtr += len; + } +#endif + } + else + { + switch (HSUSBCTX.USBHS_SetupReqCode) + { + case USB_GET_DESCRIPTOR: + break; - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; - } - else if ( ( ctx->USBHS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) - { + case USB_SET_ADDRESS: + USBHSD->DEV_AD = ctx->USBHS_DevAddr; + break; + + default: + break; + } + } + } + + /* data-out stage processing */ + case CUIS_TOKEN_OUT: + switch (ep) + { + /* end-point 0 data out interrupt */ + case DEF_UEP0: + { + // XXX WARNINGS: + // 1. intfgst & CRB_UIS_TOG_OK is not set for non-odd transactions, i.e. first, third, etc, are all fine. + // 2. HandleHidUserReportOutComplete doesn't seem to work. + // if( intfgst & CRB_UIS_TOG_OK ) #if HUSB_HID_USER_REPORTS - len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; - if( len && HSUSBCTX.USBHS_SetupReqCode == HID_GET_REPORT ) - { - len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; - ctx->USBHS_SetupReqLen -= len; - ctx->pCtrlPayloadPtr += len; - } + int len = USBHSD->RX_LEN; + uint8_t *cptr = ctx->pCtrlPayloadPtr; + if (!cptr) + { + HandleHidUserReportDataOut(ctx, ctrl0buff, len); + } + else + { + int remain = ctx->USBHS_SetupReqLen - len; + if (remain < 0) + { + len += remain; + remain = 0; + } + // DMA7FastCopy( cptr, ctrl0buff, len ); + memcpy(cptr, ctrl0buff, len); + ctx->USBHS_SetupReqLen = remain; + if (remain > 0) + ctx->pCtrlPayloadPtr = cptr + len; + else + ctx->pCtrlPayloadPtr = 0; + } #endif - } - else - { - switch( HSUSBCTX.USBHS_SetupReqCode ) - { - case USB_GET_DESCRIPTOR: - break; - - case USB_SET_ADDRESS: - USBHSD->DEV_AD = ctx->USBHS_DevAddr; - break; - - default: - break; - } - } - } - - /* data-out stage processing */ - case CUIS_TOKEN_OUT: - switch( ep ) - { - /* end-point 0 data out interrupt */ - case DEF_UEP0: - { - // XXX WARNINGS: - // 1. intfgst & CRB_UIS_TOG_OK is not set for non-odd transactions, i.e. first, third, etc, are all fine. - // 2. HandleHidUserReportOutComplete doesn't seem to work. - //if( intfgst & CRB_UIS_TOG_OK ) + if (ctx->USBHS_SetupReqLen == 0) + { #if HUSB_HID_USER_REPORTS - int len = USBHSD->RX_LEN; - uint8_t * cptr = ctx->pCtrlPayloadPtr; - if( !cptr ) - { - HandleHidUserReportDataOut( ctx, ctrl0buff, len ); - } - else - { - int remain = ctx->USBHS_SetupReqLen - len; - if( remain < 0 ) - { - len += remain; - remain = 0; - } - //DMA7FastCopy( cptr, ctrl0buff, len ); - memcpy( cptr, ctrl0buff, len ); - ctx->USBHS_SetupReqLen = remain; - if( remain > 0 ) - ctx->pCtrlPayloadPtr = cptr + len; - else - ctx->pCtrlPayloadPtr = 0; - } + // DMA7FastCopyComplete(); + HandleHidUserReportOutComplete(ctx); #endif + } - if( ctx->USBHS_SetupReqLen == 0 ) - { -#if HUSB_HID_USER_REPORTS - //DMA7FastCopyComplete(); - HandleHidUserReportOutComplete( ctx ); -#endif - } + // See above comment + // //USBHSD->UEP0_RX_CTRL ^= USBFS_UEP_R_TOG; - // See above comment - // //USBHSD->UEP0_RX_CTRL ^= USBFS_UEP_R_TOG; - - break; - } - default: - // Any other out. (also happens with In) - HSUSBCTX.USBHS_Endp_Busy[ ep ] = 0x02; - USBHSD_UEP_RXCTRL( ep ) = ((USBHSD_UEP_RXCTRL( ep )) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_NAK; + break; + } + default: + // Any other out. (also happens with In) + HSUSBCTX.USBHS_Endp_Busy[ep] = 0x02; + USBHSD_UEP_RXCTRL(ep) = ((USBHSD_UEP_RXCTRL(ep)) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_NAK; #if HUSB_BULK_USER_REPORTS - HandleGotEPComplete( ctx, ep ); + HandleGotEPComplete(ctx, ep); #endif - break; - } - break; - case CUIS_TOKEN_SETUP: // Not actually used on this chip (It's done as a separate flag) - case CUIS_TOKEN_SOF: // Sof pack processing - break; + break; + } + break; + case CUIS_TOKEN_SETUP: // Not actually used on this chip (It's done as a separate flag) + case CUIS_TOKEN_SOF: // Sof pack processing + break; - default : - break; - } - } - if(intfgst & USBHS_UIF_BUS_RST) - { - /* usb reset interrupt processing */ - ctx->USBHS_DevConfig = 0; - ctx->USBHS_DevAddr = 0; - ctx->USBHS_DevSleepStatus = 0; - ctx->USBHS_DevEnumStatus = 0; + default: + break; + } + } + if (intfgst & USBHS_UIF_BUS_RST) + { + /* usb reset interrupt processing */ + ctx->USBHS_DevConfig = 0; + ctx->USBHS_DevAddr = 0; + ctx->USBHS_DevSleepStatus = 0; + ctx->USBHS_DevEnumStatus = 0; - USBHSD->DEV_AD = 0; - USBHS_InternalFinishSetup( ); - } - if(intfgst & USBHS_UIF_SUSPEND) - { - USBHSD->INT_FG = USBHS_UIF_SUSPEND; - Delay_Us(10); + USBHSD->DEV_AD = 0; + USBHS_InternalFinishSetup(); + } + if (intfgst & USBHS_UIF_SUSPEND) + { + USBHSD->INT_FG = USBHS_UIF_SUSPEND; + Delay_Us(10); - // USB suspend interrupt processing - if(USBHSD->MIS_ST & USBHS_UMS_SUSPEND) - { - HSUSBCTX.USBHS_DevSleepStatus |= 0x02; - if(HSUSBCTX.USBHS_DevSleepStatus == 0x03) - { - // TODO: Handle usb sleep here - } - } - else - { - HSUSBCTX.USBHS_DevSleepStatus &= ~0x02; - } - } + // USB suspend interrupt processing + if (USBHSD->MIS_ST & USBHS_UMS_SUSPEND) + { + HSUSBCTX.USBHS_DevSleepStatus |= 0x02; + if (HSUSBCTX.USBHS_DevSleepStatus == 0x03) + { + // TODO: Handle usb sleep here + } + } + else + { + HSUSBCTX.USBHS_DevSleepStatus &= ~0x02; + } + } - USBHSD->INT_FG = intfgst; + USBHSD->INT_FG = intfgst; } void USBHS_InternalFinishSetup() { - - // To reconfigure your endpoints for TX/RX do it here. + // To reconfigure your endpoints for TX/RX do it here. #if HUSB_CONFIG_EPS > 5 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN - | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN | USBHS_UEP5_R_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN | USBHS_UEP5_R_EN; #elif HUSB_CONFIG_EPS > 4 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN - | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN; #elif HUSB_CONFIG_EPS > 3 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN - | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN; #elif HUSB_CONFIG_EPS > 2 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN - | USBHS_UEP2_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN; #elif HUSB_CONFIG_EPS > 1 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN; #else - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN; #endif - // This is really cursed. Somehow it doesn't explode. - // But, normally the USB wants a separate buffer here. + // This is really cursed. Somehow it doesn't explode. + // But, normally the USB wants a separate buffer here. #if HUSB_CONFIG_EPS > 5 - // Feel free to override any of these. - USBHSD->UEP5_MAX_LEN = 64; - USBHSD->UEP5_RX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[5]; - USBHSD->UEP5_RX_CTRL = USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_AUTO; // For bulk-out, I think you need to do this. + // Feel free to override any of these. + USBHSD->UEP5_MAX_LEN = 64; + USBHSD->UEP5_RX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[5]; + USBHSD->UEP5_RX_CTRL = USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_AUTO; // For bulk-out, I think you need to do this. #endif #if HUSB_CONFIG_EPS > 4 - USBHSD->UEP4_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP4_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[4]; + USBHSD->UEP4_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP4_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[4]; #endif #if HUSB_CONFIG_EPS > 3 - USBHSD->UEP3_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP3_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[3]; + USBHSD->UEP3_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP3_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[3]; #endif #if HUSB_CONFIG_EPS > 2 - USBHSD->UEP2_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP2_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[2]; + USBHSD->UEP2_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP2_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[2]; #endif #if HUSB_CONFIG_EPS > 1 - USBHSD->UEP1_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP1_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[1]; + USBHSD->UEP1_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP1_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[1]; #endif #if HUSB_CONFIG_EPS > 0 - USBHSD->UEP0_MAX_LEN = 64; - USBHSD->UEP0_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[0]; + USBHSD->UEP0_MAX_LEN = 64; + USBHSD->UEP0_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[0]; #else #error You must have at least EP0! #endif - UEP_CTRL_H(0) = USBHS_UEP_R_RES_ACK | USBHS_UEP_T_RES_NAK; - int i; - for( i = 1; i < HUSB_CONFIG_EPS; i++ ) - UEP_CTRL_H(i) = USBFS_UEP_T_RES_NAK; + UEP_CTRL_H(0) = USBHS_UEP_R_RES_ACK | USBHS_UEP_T_RES_NAK; + int i; + for (i = 1; i < HUSB_CONFIG_EPS; i++) + UEP_CTRL_H(i) = USBFS_UEP_T_RES_NAK; - for(uint8_t i=0; i< sizeof(HSUSBCTX.USBHS_Endp_Busy)/sizeof(HSUSBCTX.USBHS_Endp_Busy[0]); i++ ) - { - HSUSBCTX.USBHS_Endp_Busy[ i ] = 0; - } + for (uint8_t i = 0; i < sizeof(HSUSBCTX.USBHS_Endp_Busy) / sizeof(HSUSBCTX.USBHS_Endp_Busy[0]); i++) + { + HSUSBCTX.USBHS_Endp_Busy[i] = 0; + } } int HSUSBSetup() { - // Set USB clock source to USBPHY - RCC->CFGR2 &= ~(1 << 31); - RCC->CFGR2 |= RCC_USBCLK48MCLKSource_USBPHY << 31; + // Set USB clock source to USBPHY + RCC->CFGR2 &= ~(1 << 31); + RCC->CFGR2 |= RCC_USBCLK48MCLKSource_USBPHY << 31; - // Set PLL clock source to HSE - RCC->CFGR2 &= ~(1 << 27); - RCC->CFGR2 |= RCC_HSBHSPLLCLKSource_HSE << 27; + // Set PLL clock source to HSE + RCC->CFGR2 &= ~(1 << 27); + RCC->CFGR2 |= RCC_HSBHSPLLCLKSource_HSE << 27; - // Configure PLL for USB - RCC->CFGR2 &= ~(7 << 24); - RCC->CFGR2 |= RCC_USBPLL_Div2 << 24; + // Configure PLL for USB + RCC->CFGR2 &= ~(7 << 24); + RCC->CFGR2 |= RCC_USBPLL_Div2 << 24; - // Configure reference clock - RCC->CFGR2 &= ~(3 << 28); - RCC->CFGR2 |= RCC_USBHSPLLCKREFCLK_4M << 28; + // Configure reference clock + RCC->CFGR2 &= ~(3 << 28); + RCC->CFGR2 |= RCC_USBHSPLLCKREFCLK_4M << 28; - // Enable USB high-speed peripheral - RCC->CFGR2 |= (1 << 30); - RCC->AHBPCENR |= RCC_AHBPeriph_USBHS | RCC_AHBPeriph_DMA1; + // Enable USB high-speed peripheral + RCC->CFGR2 |= (1 << 30); + RCC->AHBPCENR |= RCC_AHBPeriph_USBHS | RCC_AHBPeriph_DMA1; - // Initialize USB module - USBHSD->CONTROL = USBHS_UC_CLR_ALL | USBHS_UC_RESET_SIE; - Delay_Us(10); - USBHSD->CONTROL = 0; + // Initialize USB module + USBHSD->CONTROL = USBHS_UC_CLR_ALL | USBHS_UC_RESET_SIE; + Delay_Us(10); + USBHSD->CONTROL = 0; - // Initialize USB device config - USBHSD->HOST_CTRL = USBHS_UH_PHY_SUSPENDM; - USBHSD->CONTROL = USBHS_UC_DMA_EN | USBHS_UC_INT_BUSY | USBHS_UC_SPEED_HIGH; - USBHSD->INT_EN = USBHS_UIE_SETUP_ACT | USBHS_UIE_TRANSFER | USBHS_UIE_DETECT | USBHS_UIE_SUSPEND; - - USBHS_InternalFinishSetup(); + // Initialize USB device config + USBHSD->HOST_CTRL = USBHS_UH_PHY_SUSPENDM; + USBHSD->CONTROL = USBHS_UC_DMA_EN | USBHS_UC_INT_BUSY | USBHS_UC_SPEED_HIGH; + USBHSD->INT_EN = USBHS_UIE_SETUP_ACT | USBHS_UIE_TRANSFER | USBHS_UIE_DETECT | USBHS_UIE_SUSPEND; - USBHSD->CONTROL |= USBHS_UC_DEV_PU_EN; - NVIC_EnableIRQ(USBHS_IRQn); + USBHS_InternalFinishSetup(); - // Go on-bus. - return 0; + USBHSD->CONTROL |= USBHS_UC_DEV_PU_EN; + NVIC_EnableIRQ(USBHS_IRQn); + + // Go on-bus. + return 0; } - - diff --git a/src/extralibs/hsusb_v30x.h b/src/extralibs/hsusb_v30x.h index 013eb7d..49584be 100644 --- a/src/extralibs/hsusb_v30x.h +++ b/src/extralibs/hsusb_v30x.h @@ -7,75 +7,74 @@ This is referenced in Chapter 22 USB Host/Device Controller (USBHD) of CH32FV2x_V3xRM.pdf */ -#include #include "ch32fun.h" -#include "usb_defines.h" #include "usb_config.h" +#include "usb_defines.h" +#include struct _USBState { - // Setup Request - uint8_t USBHS_SetupReqCode; - uint8_t USBHS_SetupReqType; - uint16_t USBHS_SetupReqLen; // Used for tracking place along send. - uint32_t USBHS_IndexValue; + // Setup Request + uint8_t USBHS_SetupReqCode; + uint8_t USBHS_SetupReqType; + uint16_t USBHS_SetupReqLen; // Used for tracking place along send. + uint32_t USBHS_IndexValue; - // USB Device Status - uint16_t USBHS_DevConfig; - uint16_t USBHS_DevAddr; - uint8_t USBHS_DevSleepStatus; - uint8_t USBHS_DevEnumStatus; + // USB Device Status + uint16_t USBHS_DevConfig; + uint16_t USBHS_DevAddr; + uint8_t USBHS_DevSleepStatus; + uint8_t USBHS_DevEnumStatus; - uint8_t * pCtrlPayloadPtr; + uint8_t *pCtrlPayloadPtr; - uint8_t ENDPOINTS[HUSB_CONFIG_EPS][64]; + uint8_t ENDPOINTS[HUSB_CONFIG_EPS][64]; - #define CTRL0BUFF (HSUSBCTX.ENDPOINTS[0]) - #define pUSBHS_SetupReqPak ((tusb_control_request_t*)CTRL0BUFF) +#define CTRL0BUFF (HSUSBCTX.ENDPOINTS[0]) +#define pUSBHS_SetupReqPak ((tusb_control_request_t *)CTRL0BUFF) #if HUSB_HID_INTERFACES > 0 - uint8_t USBHS_HidIdle[HUSB_HID_INTERFACES]; - uint8_t USBHS_HidProtocol[HUSB_HID_INTERFACES]; + uint8_t USBHS_HidIdle[HUSB_HID_INTERFACES]; + uint8_t USBHS_HidProtocol[HUSB_HID_INTERFACES]; #endif - volatile uint8_t USBHS_Endp_Busy[HUSB_CONFIG_EPS]; + volatile uint8_t USBHS_Endp_Busy[HUSB_CONFIG_EPS]; }; // Provided functions: -int HSUSBSetup(); +int HSUSBSetup(); uint8_t USBHS_Endp_DataUp(uint8_t endp, const uint8_t *pbuf, uint16_t len, uint8_t mod); // Implement the following: #if HUSB_HID_USER_REPORTS -int HandleHidUserGetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); -int HandleHidUserSetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); -void HandleHidUserReportDataOut( struct _USBState * ctx, uint8_t * data, int len ); -int HandleHidUserReportDataIn( struct _USBState * ctx, uint8_t * data, int len ); -void HandleHidUserReportOutComplete( struct _USBState * ctx ); +int HandleHidUserGetReportSetup(struct _USBState *ctx, tusb_control_request_t *req); +int HandleHidUserSetReportSetup(struct _USBState *ctx, tusb_control_request_t *req); +void HandleHidUserReportDataOut(struct _USBState *ctx, uint8_t *data, int len); +int HandleHidUserReportDataIn(struct _USBState *ctx, uint8_t *data, int len); +void HandleHidUserReportOutComplete(struct _USBState *ctx); #endif #if HUSB_BULK_USER_REPORTS -void HandleGotEPComplete( struct _USBState * ctx, int ep ); +void HandleGotEPComplete(struct _USBState *ctx, int ep); #endif extern struct _USBState HSUSBCTX; - // To TX, you can use USBFS_GetEPBufferIfAvailable or USBHSD_UEP_TXBUF( endp ) -static inline uint8_t * USBHS_GetEPBufferIfAvailable( int endp ) +static inline uint8_t *USBHS_GetEPBufferIfAvailable(int endp) { - if( HSUSBCTX.USBHS_Endp_Busy[ endp ] ) return 0; - return USBHSD_UEP_TXBUF( endp ); + if (HSUSBCTX.USBHS_Endp_Busy[endp]) return 0; + return USBHSD_UEP_TXBUF(endp); } -static inline void USBHS_SendEndpoint( int endp, int len, const uint8_t * data ) +static inline void USBHS_SendEndpoint(int endp, int len, const uint8_t *data) { - if( endp ) - { - (((uint32_t*)(&USBHSD->UEP1_TX_DMA))[2-1]) = (uintptr_t)data; - } - USBHSD_UEP_TLEN( endp ) = len; - USBHSD_UEP_TXCTRL( endp ) = ( USBHSD_UEP_TXCTRL( endp ) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_ACK; - HSUSBCTX.USBHS_Endp_Busy[ endp ] = 0x01; + if (endp) + { + (((uint32_t *)(&USBHSD->UEP1_TX_DMA))[2 - 1]) = (uintptr_t)data; + } + USBHSD_UEP_TLEN(endp) = len; + USBHSD_UEP_TXCTRL(endp) = (USBHSD_UEP_TXCTRL(endp) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_ACK; + HSUSBCTX.USBHS_Endp_Busy[endp] = 0x01; } #endif diff --git a/src/extralibs/lib_rand.h b/src/extralibs/lib_rand.h index a6bcf74..98889b4 100644 --- a/src/extralibs/lib_rand.h +++ b/src/extralibs/lib_rand.h @@ -1,30 +1,30 @@ /****************************************************************************** -* Psuedo Random Number Generator using a Linear Feedback Shift Register -* See the GitHub for more information: -* https://github.com/ADBeta/CH32V003_lib_rand -* -* Ver 1.1 09 Sep 2024 -* -* Released under the MIT Licence -* Copyright ADBeta (c) 2024 -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to -* deal in the Software without restriction, including without limitation the -* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -* sell copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -* USE OR OTHER DEALINGS IN THE SOFTWARE. -******************************************************************************/ + * Psuedo Random Number Generator using a Linear Feedback Shift Register + * See the GitHub for more information: + * https://github.com/ADBeta/CH32V003_lib_rand + * + * Ver 1.1 09 Sep 2024 + * + * Released under the MIT Licence + * Copyright ADBeta (c) 2024 + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + ******************************************************************************/ #ifndef CH32V003_LIB_RAND #define CH32V003_LIB_RAND @@ -34,14 +34,13 @@ // Strength 3: Genetate two 32bit values using the LFSR, then XOR them together // Example: #define RANDOM_STRENGTH 2 -#ifndef RANDOM_STRENGTH - #error "Error in lib_rand. Must define RANDOM_STRENGTH" +#ifndef RANDOM_STRENGTH +#error "Error in lib_rand. Must define RANDOM_STRENGTH" #endif // @brief set the random LFSR values seed by default to a known-good value static uint32_t _rand_lfsr = 0x747AA32F; - /*** Library specific Functions - Do Not Use *********************************/ /****************************************************************************/ /// @brief Updates the LFSR by getting a new tap bit, for MSB, then shifting @@ -51,63 +50,59 @@ static uint32_t _rand_lfsr = 0x747AA32F; /// @return 0x01 or 0x00, as a LSB translation of the tapped MSB for the LFSR uint8_t _rand_lfsr_update(void) { - // Shifting to MSB to make calculations more efficient later - uint32_t bit_31 = _rand_lfsr & 0x80000000; - uint32_t bit_21 = (_rand_lfsr << 10) & 0x80000000; - uint32_t bit_01 = (_rand_lfsr << 30) & 0x80000000; - uint32_t bit_00 = (_rand_lfsr << 31) & 0x80000000; + // Shifting to MSB to make calculations more efficient later + uint32_t bit_31 = _rand_lfsr & 0x80000000; + uint32_t bit_21 = (_rand_lfsr << 10) & 0x80000000; + uint32_t bit_01 = (_rand_lfsr << 30) & 0x80000000; + uint32_t bit_00 = (_rand_lfsr << 31) & 0x80000000; - // Calculate the MSB to be put into the LFSR - uint32_t msb = bit_31 ^ bit_21 ^ bit_01 ^ bit_00; - // Shift the lfsr and append the MSB to it - _rand_lfsr = (_rand_lfsr >> 1) | msb; - // Return the LSB instead of MSB - return msb >> 31; + // Calculate the MSB to be put into the LFSR + uint32_t msb = bit_31 ^ bit_21 ^ bit_01 ^ bit_00; + // Shift the lfsr and append the MSB to it + _rand_lfsr = (_rand_lfsr >> 1) | msb; + // Return the LSB instead of MSB + return msb >> 31; } - /// @brief Generates a Random 32-bit number, using the LFSR - by generating /// a random bit from LFSR taps, 32 times. /// @param None /// @return a (psuedo)random 32-bit value uint32_t _rand_gen_32b(void) { - uint32_t rand_out = 0; - - uint8_t bits = 32; - while(bits--) - { - // Shift the current rand value for the new LSB - rand_out = rand_out << 1; - // Append the LSB - rand_out |= _rand_lfsr_update(); - } - - return rand_out; + uint32_t rand_out = 0; + + uint8_t bits = 32; + while (bits--) + { + // Shift the current rand value for the new LSB + rand_out = rand_out << 1; + // Append the LSB + rand_out |= _rand_lfsr_update(); + } + + return rand_out; } - - /// @brief Generates a Random n-bit number, using the LFSR - by generating /// a random bit from LFSR taps, n times. /// @param None /// @return a (psuedo)random n-bit value -uint32_t _rand_gen_nb( int bits) +uint32_t _rand_gen_nb(int bits) { - uint32_t rand_out = 0; + uint32_t rand_out = 0; - while(bits--) - { - // Shift the current rand value for the new LSB - rand_out = rand_out << 1; - // Append the LSB - rand_out |= _rand_lfsr_update(); - } + while (bits--) + { + // Shift the current rand value for the new LSB + rand_out = rand_out << 1; + // Append the LSB + rand_out |= _rand_lfsr_update(); + } - return rand_out; + return rand_out; } - /*** API Functions ***********************************************************/ /*****************************************************************************/ /// @brief seeds the Random LFSR to the value passed @@ -115,40 +110,39 @@ uint32_t _rand_gen_nb( int bits) /// @return None void seed(const uint32_t seed_val) { - _rand_lfsr = seed_val; + _rand_lfsr = seed_val; } - /// @brief Generates a Random (32-bit) Number, based on the RANDOM_STRENGTH -/// you have selected +/// you have selected /// @param None /// @return 32bit Random value uint32_t rand(void) { - uint32_t rand_out = 0; + uint32_t rand_out = 0; - // If RANDOM_STRENGTH is level 1, Update LFSR Once, then return it - #if RANDOM_STRENGTH == 1 - // Update the LFSR, discard result, and return _lsfr raw - (void)_rand_lfsr_update(); - rand_out = _rand_lfsr; - #endif +// If RANDOM_STRENGTH is level 1, Update LFSR Once, then return it +#if RANDOM_STRENGTH == 1 + // Update the LFSR, discard result, and return _lsfr raw + (void)_rand_lfsr_update(); + rand_out = _rand_lfsr; +#endif - // If RANDOM_STRENGTH is level 2, generate a 32-bit output, using 32 random - // bits from the LFSR - #if RANDOM_STRENGTH == 2 - rand_out = _rand_gen_32b(); - #endif +// If RANDOM_STRENGTH is level 2, generate a 32-bit output, using 32 random +// bits from the LFSR +#if RANDOM_STRENGTH == 2 + rand_out = _rand_gen_32b(); +#endif - // If RANDOM_STRENGTH is level 3, generate 2 32-bit outputs, then XOR them - // together - #if RANDOM_STRENGTH == 3 - uint32_t rand_a = _rand_gen_32b(); - uint32_t rand_b = _rand_gen_32b(); - rand_out = rand_a ^ rand_b; - #endif +// If RANDOM_STRENGTH is level 3, generate 2 32-bit outputs, then XOR them +// together +#if RANDOM_STRENGTH == 3 + uint32_t rand_a = _rand_gen_32b(); + uint32_t rand_b = _rand_gen_32b(); + rand_out = rand_a ^ rand_b; +#endif - return rand_out; + return rand_out; } #endif diff --git a/src/extralibs/ssd1306.h b/src/extralibs/ssd1306.h index 3edfbc6..d51811f 100644 --- a/src/extralibs/ssd1306.h +++ b/src/extralibs/ssd1306.h @@ -6,19 +6,19 @@ #ifndef _SSD1306_H #define _SSD1306_H +#include "font_8x8.h" #include #include -#include "font_8x8.h" // comfortable packet size for this OLED #define SSD1306_PSZ 32 -#if defined (SSD1306_CUSTOM) +#if defined(SSD1306_CUSTOM) // Let the caller configure the OLED. #else // characteristics of each type -#if !defined (SSD1306_64X32) && !defined (SSD1306_128X32) && !defined (SSD1306_128X64) && !defined (SH1107_128x128) && !(defined(SSD1306_W) && defined(SSD1306_H) && defined(SSD1306_OFFSET) ) - #error "Please define the SSD1306_WXH resolution used in your application" +#if !defined(SSD1306_64X32) && !defined(SSD1306_128X32) && !defined(SSD1306_128X64) && !defined(SH1107_128x128) && !(defined(SSD1306_W) && defined(SSD1306_H) && defined(SSD1306_OFFSET)) +#error "Please define the SSD1306_WXH resolution used in your application" #endif #ifdef SSD1306_64X32 @@ -57,7 +57,7 @@ */ uint8_t ssd1306_cmd(uint8_t cmd) { - return ssd1306_pkt_send(&cmd, 1, 1); + return ssd1306_pkt_send(&cmd, 1, 1); } /* @@ -65,7 +65,7 @@ uint8_t ssd1306_cmd(uint8_t cmd) */ uint8_t ssd1306_data(uint8_t *data, int sz) { - return ssd1306_pkt_send(data, sz, 0); + return ssd1306_pkt_send(data, sz, 0); } #define SSD1306_SETCONTRAST 0x81 @@ -87,7 +87,7 @@ uint8_t ssd1306_data(uint8_t *data, int sz) #define SSD1306_SETSTARTLINE 0x40 #define SSD1306_MEMORYMODE 0x20 #define SSD1306_COLUMNADDR 0x21 -#define SSD1306_PAGEADDR 0x22 +#define SSD1306_PAGEADDR 0x22 #define SSD1306_COMSCANINC 0xC0 #define SSD1306_COMSCANDEC 0xC8 #define SSD1306_CHARGEPUMP 0x8D @@ -98,81 +98,81 @@ uint8_t ssd1306_data(uint8_t *data, int sz) /* choose VCC mode */ #define SSD1306_EXTERNALVCC 0x1 #define SSD1306_SWITCHCAPVCC 0x2 -//#define vccstate SSD1306_EXTERNALVCC +// #define vccstate SSD1306_EXTERNALVCC #define vccstate SSD1306_SWITCHCAPVCC #if !defined(SSD1306_CUSTOM_INIT_ARRAY) || !SSD1306_CUSTOM_INIT_ARRAY // OLED initialization commands for 128x32 const uint8_t ssd1306_init_array[] = -{ + { #ifdef SH1107 - SSD1306_DISPLAYOFF, // Turn OLED off - 0x00, // Low column - 0x10, // High column - 0xb0, // Page address - 0xdc, 0x00, // Set Display Start Line (Where in memory it reads from) - SSD1306_SETCONTRAST, 0x6f, // Set constrast - SSD1306_COLUMNADDR, // Set memory addressing mode - SSD1306_DISPLAYALLON_RESUME, // normal (as opposed to invert colors, always on or off.) - SSD1306_SETMULTIPLEX, (SSD1306_H-1), // Iterate over all 128 rows (Multiplex Ratio) - SSD1306_SETDISPLAYOFFSET, 0x00, // Set display offset // Where this appears on-screen (Some displays will be different) - SSD1306_SETDISPLAYCLOCKDIV, 0xf0, // Set precharge properties. THIS IS A LIE This has todo with timing. <<< This makes it go brrrrrrrrr - SSD1306_SETPRECHARGE, 0x1d, // Set pre-charge period (This controls brightness) - SSD1306_SETVCOMDETECT, 0x35, // Set vcomh - SSD1306_SETSTARTLINE | 0x0, // 0x40 | line - 0xad, 0x80, // Set Charge pump - SSD1306_SEGREMAP, 0x01, // Default mapping - SSD1306_SETPRECHARGE, 0x06, // ???? No idea what this does, but this looks best. - SSD1306_SETCONTRAST, 0xfe, // Set constrast - SSD1306_SETVCOMDETECT, 0xfe, // Set vcomh - SSD1306_SETMULTIPLEX, (SSD1306_H-1), // 128-wide. - SSD1306_DISPLAYON, // Display on. + SSD1306_DISPLAYOFF, // Turn OLED off + 0x00, // Low column + 0x10, // High column + 0xb0, // Page address + 0xdc, 0x00, // Set Display Start Line (Where in memory it reads from) + SSD1306_SETCONTRAST, 0x6f, // Set constrast + SSD1306_COLUMNADDR, // Set memory addressing mode + SSD1306_DISPLAYALLON_RESUME, // normal (as opposed to invert colors, always on or off.) + SSD1306_SETMULTIPLEX, (SSD1306_H - 1), // Iterate over all 128 rows (Multiplex Ratio) + SSD1306_SETDISPLAYOFFSET, 0x00, // Set display offset // Where this appears on-screen (Some displays will be different) + SSD1306_SETDISPLAYCLOCKDIV, 0xf0, // Set precharge properties. THIS IS A LIE This has todo with timing. <<< This makes it go brrrrrrrrr + SSD1306_SETPRECHARGE, 0x1d, // Set pre-charge period (This controls brightness) + SSD1306_SETVCOMDETECT, 0x35, // Set vcomh + SSD1306_SETSTARTLINE | 0x0, // 0x40 | line + 0xad, 0x80, // Set Charge pump + SSD1306_SEGREMAP, 0x01, // Default mapping + SSD1306_SETPRECHARGE, 0x06, // ???? No idea what this does, but this looks best. + SSD1306_SETCONTRAST, 0xfe, // Set constrast + SSD1306_SETVCOMDETECT, 0xfe, // Set vcomh + SSD1306_SETMULTIPLEX, (SSD1306_H - 1), // 128-wide. + SSD1306_DISPLAYON, // Display on. #else - SSD1306_DISPLAYOFF, // 0xAE - SSD1306_SETDISPLAYCLOCKDIV, // 0xD5 - 0x80, // the suggested ratio 0x80 - SSD1306_SETMULTIPLEX, // 0xA8 + SSD1306_DISPLAYOFF, // 0xAE + SSD1306_SETDISPLAYCLOCKDIV, // 0xD5 + 0x80, // the suggested ratio 0x80 + SSD1306_SETMULTIPLEX, // 0xA8 #ifdef SSD1306_64X32 - 0x1F, // for 64-wide displays + 0x1F, // for 64-wide displays #else - 0x3F, // for 128-wide displays + 0x3F, // for 128-wide displays #endif - SSD1306_SETDISPLAYOFFSET, // 0xD3 - 0x00, // no offset - SSD1306_SETSTARTLINE | 0x0, // 0x40 | line - SSD1306_CHARGEPUMP, // 0x8D - 0x14, // enable? - SSD1306_MEMORYMODE, // 0x20 - 0x00, // 0x0 act like ks0108 - SSD1306_SEGREMAP | 0x1, // 0xA0 | bit - SSD1306_COMSCANDEC, - SSD1306_SETCOMPINS, // 0xDA - 0x12, // - SSD1306_SETCONTRAST, // 0x81 - 0x8F, - SSD1306_SETPRECHARGE, // 0xd9 - 0xF1, - SSD1306_SETVCOMDETECT, // 0xDB - 0x40, - SSD1306_DISPLAYALLON_RESUME, // 0xA4 + SSD1306_SETDISPLAYOFFSET, // 0xD3 + 0x00, // no offset + SSD1306_SETSTARTLINE | 0x0, // 0x40 | line + SSD1306_CHARGEPUMP, // 0x8D + 0x14, // enable? + SSD1306_MEMORYMODE, // 0x20 + 0x00, // 0x0 act like ks0108 + SSD1306_SEGREMAP | 0x1, // 0xA0 | bit + SSD1306_COMSCANDEC, + SSD1306_SETCOMPINS, // 0xDA + 0x12, // + SSD1306_SETCONTRAST, // 0x81 + 0x8F, + SSD1306_SETPRECHARGE, // 0xd9 + 0xF1, + SSD1306_SETVCOMDETECT, // 0xDB + 0x40, + SSD1306_DISPLAYALLON_RESUME, // 0xA4 #ifndef SSD1327 - SSD1306_NORMALDISPLAY, // 0xA6 + SSD1306_NORMALDISPLAY, // 0xA6 #endif - SSD1306_DISPLAYON, // 0xAF --turn on oled panel + SSD1306_DISPLAYON, // 0xAF --turn on oled panel #endif - SSD1306_TERMINATE_CMDS // 0xFF --fake command to mark end + SSD1306_TERMINATE_CMDS // 0xFF --fake command to mark end }; #endif // the display buffer -uint8_t ssd1306_buffer[SSD1306_W*SSD1306_H/8]; +uint8_t ssd1306_buffer[SSD1306_W * SSD1306_H / 8]; /* * set the buffer to a color */ void ssd1306_setbuf(uint8_t color) { - memset(ssd1306_buffer, color ? 0xFF : 0x00, sizeof(ssd1306_buffer)); + memset(ssd1306_buffer, color ? 0xFF : 0x00, sizeof(ssd1306_buffer)); } #ifndef SSD1306_FULLUSE @@ -180,11 +180,23 @@ void ssd1306_setbuf(uint8_t color) * expansion array for OLED with every other row unused */ const uint8_t expand[16] = -{ - 0x00,0x02,0x08,0x0a, - 0x20,0x22,0x28,0x2a, - 0x80,0x82,0x88,0x8a, - 0xa0,0xa2,0xa8,0xaa, + { + 0x00, + 0x02, + 0x08, + 0x0a, + 0x20, + 0x22, + 0x28, + 0x2a, + 0x80, + 0x82, + 0x88, + 0x8a, + 0xa0, + 0xa2, + 0xa8, + 0xaa, }; #endif @@ -193,66 +205,65 @@ const uint8_t expand[16] = */ void ssd1306_refresh(void) { - uint16_t i; - + uint16_t i; + #ifdef SH1107 - ssd1306_cmd(SSD1306_MEMORYMODE); // vertical addressing mode. + ssd1306_cmd(SSD1306_MEMORYMODE); // vertical addressing mode. - for(i=0;i>4) ); - ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+0*SSD1306_PSZ], SSD1306_PSZ); - ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+1*SSD1306_PSZ], SSD1306_PSZ); - ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+2*SSD1306_PSZ], SSD1306_PSZ); - ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+3*SSD1306_PSZ], SSD1306_PSZ); - } + for (i = 0; i < SSD1306_H / 8; i++) + { + ssd1306_cmd(0xb0 | i); + ssd1306_cmd(0x00 | (0 & 0xf)); + ssd1306_cmd(0x10 | (0 >> 4)); + ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 0 * SSD1306_PSZ], SSD1306_PSZ); + ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 1 * SSD1306_PSZ], SSD1306_PSZ); + ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 2 * SSD1306_PSZ], SSD1306_PSZ); + ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 3 * SSD1306_PSZ], SSD1306_PSZ); + } #else - ssd1306_cmd(SSD1306_COLUMNADDR); - ssd1306_cmd(SSD1306_OFFSET); // Column start address (0 = reset) - ssd1306_cmd(SSD1306_OFFSET+SSD1306_W-1); // Column end address (127 = reset) - - ssd1306_cmd(SSD1306_PAGEADDR); - ssd1306_cmd(0); // Page start address (0 = reset) - ssd1306_cmd(7); // Page end address + ssd1306_cmd(SSD1306_COLUMNADDR); + ssd1306_cmd(SSD1306_OFFSET); // Column start address (0 = reset) + ssd1306_cmd(SSD1306_OFFSET + SSD1306_W - 1); // Column end address (127 = reset) + + ssd1306_cmd(SSD1306_PAGEADDR); + ssd1306_cmd(0); // Page start address (0 = reset) + ssd1306_cmd(7); // Page end address #ifdef SSD1306_FULLUSE - /* for fully used rows just plow thru everything */ - for(i=0;i>4)&0xf]; - - /* send PSZ block of data */ - ssd1306_data(tbuf, SSD1306_PSZ); - } - } -#endif -#endif + /* for displays with odd rows unused expand bytes */ + uint8_t tbuf[SSD1306_PSZ], j, k; + for (i = 0; i < sizeof(ssd1306_buffer); i += 128) + { + /* low nybble */ + for (j = 0; j < 128; j += SSD1306_PSZ) + { + for (k = 0; k < SSD1306_PSZ; k++) + tbuf[k] = expand[ssd1306_buffer[i + j + k] & 0xf]; + /* send PSZ block of data */ + ssd1306_data(tbuf, SSD1306_PSZ); + } + + /* high nybble */ + for (j = 0; j < 128; j += SSD1306_PSZ) + { + for (k = 0; k < SSD1306_PSZ; k++) + tbuf[k] = expand[(ssd1306_buffer[i + j + k] >> 4) & 0xf]; + + /* send PSZ block of data */ + ssd1306_data(tbuf, SSD1306_PSZ); + } + } +#endif +#endif } /* @@ -260,22 +271,22 @@ void ssd1306_refresh(void) */ void ssd1306_drawPixel(uint32_t x, uint32_t y, int color) { - uint32_t addr; - - /* clip */ - if(x >= SSD1306_W) - return; - if(y >= SSD1306_H) - return; - - /* compute buffer address */ - addr = x + SSD1306_W*(y/8); - - /* set/clear bit in buffer */ - if(color) - ssd1306_buffer[addr] |= (1<<(y&7)); - else - ssd1306_buffer[addr] &= ~(1<<(y&7)); + uint32_t addr; + + /* clip */ + if (x >= SSD1306_W) + return; + if (y >= SSD1306_H) + return; + + /* compute buffer address */ + addr = x + SSD1306_W * (y / 8); + + /* set/clear bit in buffer */ + if (color) + ssd1306_buffer[addr] |= (1 << (y & 7)); + else + ssd1306_buffer[addr] &= ~(1 << (y & 7)); } /* @@ -283,89 +294,96 @@ void ssd1306_drawPixel(uint32_t x, uint32_t y, int color) */ void ssd1306_xorPixel(uint32_t x, uint32_t y) { - uint32_t addr; - - /* clip */ - if(x >= SSD1306_W) - return; - if(y >= SSD1306_H) - return; - - /* compute buffer address */ - addr = x + SSD1306_W*(y/8); - - ssd1306_buffer[addr] ^= (1<<(y&7)); + uint32_t addr; + + /* clip */ + if (x >= SSD1306_W) + return; + if (y >= SSD1306_H) + return; + + /* compute buffer address */ + addr = x + SSD1306_W * (y / 8); + + ssd1306_buffer[addr] ^= (1 << (y & 7)); } /* * draw a an image from an array, directly into to the display buffer * the color modes allow for overwriting and even layering (sprites!) */ -void ssd1306_drawImage(uint32_t x, uint32_t y, const unsigned char* input, uint32_t width, uint32_t height, uint32_t color_mode) { - uint32_t x_absolute; - uint32_t y_absolute; - uint32_t pixel; - uint32_t bytes_to_draw = width / 8; - uint32_t buffer_addr; +void ssd1306_drawImage(uint32_t x, uint32_t y, const unsigned char *input, uint32_t width, uint32_t height, uint32_t color_mode) +{ + uint32_t x_absolute; + uint32_t y_absolute; + uint32_t pixel; + uint32_t bytes_to_draw = width / 8; + uint32_t buffer_addr; - for (uint32_t line = 0; line < height; line++) { - y_absolute = y + line; - if (y_absolute >= SSD1306_H) { - break; - } + for (uint32_t line = 0; line < height; line++) + { + y_absolute = y + line; + if (y_absolute >= SSD1306_H) + { + break; + } - // SSD1306 is in vertical mode, yet we want to draw horizontally, which necessitates assembling the output bytes from the input data - // bitmask for current pixel in vertical (output) byte - uint32_t v_mask = 1 << (y_absolute & 7); + // SSD1306 is in vertical mode, yet we want to draw horizontally, which necessitates assembling the output bytes from the input data + // bitmask for current pixel in vertical (output) byte + uint32_t v_mask = 1 << (y_absolute & 7); - for (uint32_t byte = 0; byte < bytes_to_draw; byte++) { - uint32_t input_byte = input[byte + line * bytes_to_draw]; + for (uint32_t byte = 0; byte < bytes_to_draw; byte++) + { + uint32_t input_byte = input[byte + line * bytes_to_draw]; - for (pixel = 0; pixel < 8; pixel++) { - x_absolute = x + 8 * (bytes_to_draw - byte) + pixel; - if (x_absolute >= SSD1306_W) { - break; - } - // looking at the horizontal display, we're drawing bytes bottom to top, not left to right, hence y / 8 - buffer_addr = x_absolute + SSD1306_W * (y_absolute / 8); - // state of current pixel - uint8_t input_pixel = input_byte & (1 << pixel); + for (pixel = 0; pixel < 8; pixel++) + { + x_absolute = x + 8 * (bytes_to_draw - byte) + pixel; + if (x_absolute >= SSD1306_W) + { + break; + } + // looking at the horizontal display, we're drawing bytes bottom to top, not left to right, hence y / 8 + buffer_addr = x_absolute + SSD1306_W * (y_absolute / 8); + // state of current pixel + uint8_t input_pixel = input_byte & (1 << pixel); - switch (color_mode) { - case 0: - // write pixels as they are - ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (input_pixel ? v_mask : 0); - break; - case 1: - // write pixels after inversion - ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (!input_pixel ? v_mask : 0); - break; - case 2: - // 0 clears pixel - ssd1306_buffer[buffer_addr] &= input_pixel ? 0xFF : ~v_mask; - break; - case 3: - // 1 sets pixel - ssd1306_buffer[buffer_addr] |= input_pixel ? v_mask : 0; - break; - case 4: - // 0 sets pixel - ssd1306_buffer[buffer_addr] |= !input_pixel ? v_mask : 0; - break; - case 5: - // 1 clears pixel - ssd1306_buffer[buffer_addr] &= input_pixel ? ~v_mask : 0xFF; - break; - } - } - #if SSD1306_LOG_IMAGE == 1 - printf("%02x ", input_byte); - #endif - } - #if SSD1306_LOG_IMAGE == 1 - printf("\n\r"); - #endif - } + switch (color_mode) + { + case 0: + // write pixels as they are + ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (input_pixel ? v_mask : 0); + break; + case 1: + // write pixels after inversion + ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (!input_pixel ? v_mask : 0); + break; + case 2: + // 0 clears pixel + ssd1306_buffer[buffer_addr] &= input_pixel ? 0xFF : ~v_mask; + break; + case 3: + // 1 sets pixel + ssd1306_buffer[buffer_addr] |= input_pixel ? v_mask : 0; + break; + case 4: + // 0 sets pixel + ssd1306_buffer[buffer_addr] |= !input_pixel ? v_mask : 0; + break; + case 5: + // 1 clears pixel + ssd1306_buffer[buffer_addr] &= input_pixel ? ~v_mask : 0xFF; + break; + } + } +#if SSD1306_LOG_IMAGE == 1 + printf("%02x ", input_byte); +#endif + } +#if SSD1306_LOG_IMAGE == 1 + printf("\n\r"); +#endif + } } /* @@ -373,13 +391,13 @@ void ssd1306_drawImage(uint32_t x, uint32_t y, const unsigned char* input, uint3 */ void ssd1306_drawFastVLine(int32_t x, int32_t y, int32_t h, uint32_t color) { - // clipping - if((x >= SSD1306_W) || (y >= SSD1306_H)) return; - if((y+h-1) >= SSD1306_H) h = SSD1306_H-y; - while(h--) - { + // clipping + if ((x >= SSD1306_W) || (y >= SSD1306_H)) return; + if ((y + h - 1) >= SSD1306_H) h = SSD1306_H - y; + while (h--) + { ssd1306_drawPixel(x, y++, color); - } + } } /* @@ -387,14 +405,14 @@ void ssd1306_drawFastVLine(int32_t x, int32_t y, int32_t h, uint32_t color) */ void ssd1306_drawFastHLine(uint32_t x, uint32_t y, uint32_t w, uint32_t color) { - // clipping - if((x >= SSD1306_W) || (y >= SSD1306_H)) return; - if((x+w-1) >= SSD1306_W) w = SSD1306_W-x; + // clipping + if ((x >= SSD1306_W) || (y >= SSD1306_H)) return; + if ((x + w - 1) >= SSD1306_W) w = SSD1306_W - x; - while (w--) - { + while (w--) + { ssd1306_drawPixel(x++, y, color); - } + } } /* @@ -402,7 +420,7 @@ void ssd1306_drawFastHLine(uint32_t x, uint32_t y, uint32_t w, uint32_t color) */ int gfx_abs(int x) { - return (x<0) ? -x : x; + return (x < 0) ? -x : x; } /* @@ -410,9 +428,9 @@ int gfx_abs(int x) */ void gfx_swap(int *z0, int *z1) { - uint16_t temp = *z0; - *z0 = *z1; - *z1 = temp; + uint16_t temp = *z0; + *z0 = *z1; + *z1 = temp; } /* @@ -420,56 +438,56 @@ void gfx_swap(int *z0, int *z1) */ void ssd1306_drawLine(int x0, int y0, int x1, int y1, uint32_t color) { - int32_t steep; - int32_t deltax, deltay, error, ystep, x, y; + int32_t steep; + int32_t deltax, deltay, error, ystep, x, y; - /* flip sense 45deg to keep error calc in range */ - steep = (gfx_abs(y1 - y0) > gfx_abs(x1 - x0)); + /* flip sense 45deg to keep error calc in range */ + steep = (gfx_abs(y1 - y0) > gfx_abs(x1 - x0)); - if(steep) - { - gfx_swap(&x0, &y0); - gfx_swap(&x1, &y1); - } + if (steep) + { + gfx_swap(&x0, &y0); + gfx_swap(&x1, &y1); + } - /* run low->high */ - if(x0 > x1) - { - gfx_swap(&x0, &x1); - gfx_swap(&y0, &y1); - } + /* run low->high */ + if (x0 > x1) + { + gfx_swap(&x0, &x1); + gfx_swap(&y0, &y1); + } - /* set up loop initial conditions */ - deltax = x1 - x0; - deltay = gfx_abs(y1 - y0); - error = deltax/2; - y = y0; - if(y0 < y1) - ystep = 1; - else - ystep = -1; + /* set up loop initial conditions */ + deltax = x1 - x0; + deltay = gfx_abs(y1 - y0); + error = deltax / 2; + y = y0; + if (y0 < y1) + ystep = 1; + else + ystep = -1; - /* loop x */ - for(x=x0;x<=x1;x++) - { - /* plot point */ - if(steep) - /* flip point & plot */ - ssd1306_drawPixel(y, x, color); - else - /* just plot */ - ssd1306_drawPixel(x, y, color); + /* loop x */ + for (x = x0; x <= x1; x++) + { + /* plot point */ + if (steep) + /* flip point & plot */ + ssd1306_drawPixel(y, x, color); + else + /* just plot */ + ssd1306_drawPixel(x, y, color); - /* update error */ - error = error - deltay; + /* update error */ + error = error - deltay; - /* update y */ - if(error < 0) - { - y = y + ystep; - error = error + deltax; - } - } + /* update y */ + if (error < 0) + { + y = y + ystep; + error = error + deltax; + } + } } /* @@ -480,22 +498,26 @@ void ssd1306_drawCircle(int x, int y, int radius, int color) /* Bresenham algorithm */ int x_pos = -radius; int y_pos = 0; - int err = 2 - 2 * radius; + int err = 2 - 2 * radius; int e2; - do { + do + { ssd1306_drawPixel(x - x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y - y_pos, color); ssd1306_drawPixel(x - x_pos, y - y_pos, color); e2 = err; - if (e2 <= y_pos) { + if (e2 <= y_pos) + { err += ++y_pos * 2 + 1; - if(-x_pos == y_pos && e2 <= x_pos) { - e2 = 0; + if (-x_pos == y_pos && e2 <= x_pos) + { + e2 = 0; } } - if (e2 > x_pos) { + if (e2 > x_pos) + { err += ++x_pos * 2 + 1; } } while (x_pos <= 0); @@ -509,10 +531,11 @@ void ssd1306_fillCircle(int x, int y, int radius, int color) /* Bresenham algorithm */ int x_pos = -radius; int y_pos = 0; - int err = 2 - 2 * radius; + int err = 2 - 2 * radius; int e2; - do { + do + { ssd1306_drawPixel(x - x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y - y_pos, color); @@ -520,16 +543,19 @@ void ssd1306_fillCircle(int x, int y, int radius, int color) ssd1306_drawFastHLine(x + x_pos, y + y_pos, 2 * (-x_pos) + 1, color); ssd1306_drawFastHLine(x + x_pos, y - y_pos, 2 * (-x_pos) + 1, color); e2 = err; - if (e2 <= y_pos) { + if (e2 <= y_pos) + { err += ++y_pos * 2 + 1; - if(-x_pos == y_pos && e2 <= x_pos) { + if (-x_pos == y_pos && e2 <= x_pos) + { e2 = 0; } } - if(e2 > x_pos) { + if (e2 > x_pos) + { err += ++x_pos * 2 + 1; } - } while(x_pos <= 0); + } while (x_pos <= 0); } /* @@ -537,10 +563,10 @@ void ssd1306_fillCircle(int x, int y, int radius, int color) */ void ssd1306_drawRect(int32_t x, int32_t y, uint32_t w, uint32_t h, uint32_t color) { - ssd1306_drawFastVLine(x, y, h, color); - ssd1306_drawFastVLine(x+w-1, y, h, color); - ssd1306_drawFastHLine(x, y, w, color); - ssd1306_drawFastHLine(x, y+h-1, w, color); + ssd1306_drawFastVLine(x, y, h, color); + ssd1306_drawFastVLine(x + w - 1, y, h, color); + ssd1306_drawFastHLine(x, y, w, color); + ssd1306_drawFastHLine(x, y + h - 1, w, color); } /* @@ -548,21 +574,21 @@ void ssd1306_drawRect(int32_t x, int32_t y, uint32_t w, uint32_t h, uint32_t col */ void ssd1306_fillRect(uint32_t x, uint32_t y, uint8_t w, uint32_t h, uint32_t color) { - uint32_t m, n=y, iw = w; - - /* scan vertical */ - while(h--) - { - m=x; - w=iw; - /* scan horizontal */ - while(w--) - { - /* invert pixels */ - ssd1306_drawPixel(m++, n, color); - } - n++; - } + uint32_t m, n = y, iw = w; + + /* scan vertical */ + while (h--) + { + m = x; + w = iw; + /* scan horizontal */ + while (w--) + { + /* invert pixels */ + ssd1306_drawPixel(m++, n, color); + } + n++; + } } /* @@ -570,21 +596,21 @@ void ssd1306_fillRect(uint32_t x, uint32_t y, uint8_t w, uint32_t h, uint32_t co */ void ssd1306_xorrect(uint8_t x, uint8_t y, uint8_t w, uint8_t h) { - uint8_t m, n=y, iw = w; - - /* scan vertical */ - while(h--) - { - m=x; - w=iw; - /* scan horizontal */ - while(w--) - { - /* invert pixels */ - ssd1306_xorPixel(m++, n); - } - n++; - } + uint8_t m, n = y, iw = w; + + /* scan vertical */ + while (h--) + { + m = x; + w = iw; + /* scan horizontal */ + while (w--) + { + /* invert pixels */ + ssd1306_xorPixel(m++, n); + } + n++; + } } /* @@ -592,25 +618,25 @@ void ssd1306_xorrect(uint8_t x, uint8_t y, uint8_t w, uint8_t h) */ void ssd1306_drawchar(uint8_t x, uint8_t y, uint8_t chr, uint8_t color) { - uint16_t i, j, col; - uint8_t d; - - for(i=0;i<8;i++) - { - d = fontdata[(chr<<3)+i]; - for(j=0;j<8;j++) - { - if(d&0x80) - col = color; - else - col = (~color)&1; - - ssd1306_drawPixel(x+j, y+i, col); - - // next bit - d <<= 1; - } - } + uint16_t i, j, col; + uint8_t d; + + for (i = 0; i < 8; i++) + { + d = fontdata[(chr << 3) + i]; + for (j = 0; j < 8; j++) + { + if (d & 0x80) + col = color; + else + col = (~color) & 1; + + ssd1306_drawPixel(x + j, y + i, col); + + // next bit + d <<= 1; + } + } } /* @@ -618,25 +644,26 @@ void ssd1306_drawchar(uint8_t x, uint8_t y, uint8_t chr, uint8_t color) */ void ssd1306_drawstr(uint8_t x, uint8_t y, char *str, uint8_t color) { - uint8_t c; - - while((c=*str++)) - { - ssd1306_drawchar(x, y, c, color); - x += 8; - if(x>120) - break; - } + uint8_t c; + + while ((c = *str++)) + { + ssd1306_drawchar(x, y, c, color); + x += 8; + if (x > 120) + break; + } } /* * enum for font size */ -typedef enum { - fontsize_8x8 = 1, +typedef enum +{ + fontsize_8x8 = 1, fontsize_16x16 = 2, fontsize_32x32 = 4, - fontsize_64x64 = 8, + fontsize_64x64 = 8, } font_size_t; /* @@ -645,7 +672,7 @@ typedef enum { void ssd1306_drawchar_sz(uint8_t x, uint8_t y, uint8_t chr, uint8_t color, font_size_t font_size) { uint16_t i, j, col; - uint8_t d; + uint8_t d; // Determine the font scale factor based on the font_size parameter uint8_t font_scale = (uint8_t)font_size; @@ -666,8 +693,10 @@ void ssd1306_drawchar_sz(uint8_t x, uint8_t y, uint8_t chr, uint8_t color, font_ col = (~color) & 1; // Draw the pixel at the original size and scaled size using nested for-loops - for (uint8_t k = 0; k < font_scale; k++) { - for (uint8_t l = 0; l < font_scale; l++) { + for (uint8_t k = 0; k < font_scale; k++) + { + for (uint8_t l = 0; l < font_scale; l++) + { ssd1306_drawPixel(x + (j * font_scale) + k, y + (i * font_scale) + l, col); } } @@ -683,15 +712,15 @@ void ssd1306_drawchar_sz(uint8_t x, uint8_t y, uint8_t chr, uint8_t color, font_ */ void ssd1306_drawstr_sz(uint8_t x, uint8_t y, char *str, uint8_t color, font_size_t font_size) { - uint8_t c; - - while((c=*str++)) - { - ssd1306_drawchar_sz(x, y, c, color, font_size); - x += 8 * font_size; - if(x>128 - 8 * font_size) - break; - } + uint8_t c; + + while ((c = *str++)) + { + ssd1306_drawchar_sz(x, y, c, color, font_size); + x += 8 * font_size; + if (x > 128 - 8 * font_size) + break; + } } /* @@ -699,25 +728,25 @@ void ssd1306_drawstr_sz(uint8_t x, uint8_t y, char *str, uint8_t color, font_siz */ uint8_t ssd1306_init(void) { - // pulse reset - ssd1306_rst(); + // pulse reset + ssd1306_rst(); - ssd1306_setbuf(0); - - // initialize OLED + ssd1306_setbuf(0); + + // initialize OLED #if !defined(SSD1306_CUSTOM_INIT_ARRAY) || !SSD1306_CUSTOM_INIT_ARRAY - uint8_t *cmd_list = (uint8_t *)ssd1306_init_array; - while(*cmd_list != SSD1306_TERMINATE_CMDS) - { - if(ssd1306_cmd(*cmd_list++)) - return 1; - } - - // clear display - ssd1306_refresh(); + uint8_t *cmd_list = (uint8_t *)ssd1306_init_array; + while (*cmd_list != SSD1306_TERMINATE_CMDS) + { + if (ssd1306_cmd(*cmd_list++)) + return 1; + } + + // clear display + ssd1306_refresh(); #endif - return 0; + return 0; } #endif diff --git a/src/extralibs/ssd1306_i2c.h b/src/extralibs/ssd1306_i2c.h index 41b265d..465985e 100644 --- a/src/extralibs/ssd1306_i2c.h +++ b/src/extralibs/ssd1306_i2c.h @@ -27,14 +27,14 @@ #define TIMEOUT_MAX 100000 // uncomment this to enable IRQ-driven operation -//#define SSD1306_I2C_IRQ +// #define SSD1306_I2C_IRQ #ifdef SSD1306_I2C_IRQ // some stuff that IRQ mode needs volatile uint8_t ssd1306_i2c_send_buffer[64], *ssd1306_i2c_send_ptr, ssd1306_i2c_send_sz, ssd1306_i2c_irq_state; // uncomment this to enable time diags in IRQ -//#define IRQ_DIAG +// #define IRQ_DIAG #endif /* @@ -42,62 +42,62 @@ volatile uint8_t ssd1306_i2c_send_buffer[64], *ssd1306_i2c_send_ptr, ssd1306_i2c */ void ssd1306_i2c_setup(void) { - uint16_t tempreg; - - // Reset I2C1 to init all regs - RCC->APB1PRSTR |= RCC_APB1Periph_I2C1; - RCC->APB1PRSTR &= ~RCC_APB1Periph_I2C1; - - // set freq - tempreg = I2C1->CTLR2; - tempreg &= ~I2C_CTLR2_FREQ; - tempreg |= (FUNCONF_SYSTEM_CORE_CLOCK/SSD1306_I2C_PRERATE)&I2C_CTLR2_FREQ; - I2C1->CTLR2 = tempreg; - - // Set clock config - tempreg = 0; + uint16_t tempreg; + + // Reset I2C1 to init all regs + RCC->APB1PRSTR |= RCC_APB1Periph_I2C1; + RCC->APB1PRSTR &= ~RCC_APB1Periph_I2C1; + + // set freq + tempreg = I2C1->CTLR2; + tempreg &= ~I2C_CTLR2_FREQ; + tempreg |= (FUNCONF_SYSTEM_CORE_CLOCK / SSD1306_I2C_PRERATE) & I2C_CTLR2_FREQ; + I2C1->CTLR2 = tempreg; + + // Set clock config + tempreg = 0; #if (SSD1306_I2C_CLKRATE <= 100000) - // standard mode good to 100kHz - tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(2*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR; + // standard mode good to 100kHz + tempreg = (FUNCONF_SYSTEM_CORE_CLOCK / (2 * SSD1306_I2C_CLKRATE)) & I2C_CKCFGR_CCR; #else - // fast mode over 100kHz + // fast mode over 100kHz #ifndef SSD1306_I2C_DUTY - // 33% duty cycle - tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(3*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR; + // 33% duty cycle + tempreg = (FUNCONF_SYSTEM_CORE_CLOCK / (3 * SSD1306_I2C_CLKRATE)) & I2C_CKCFGR_CCR; #else - // 36% duty cycle - tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(25*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR; - tempreg |= I2C_CKCFGR_DUTY; + // 36% duty cycle + tempreg = (FUNCONF_SYSTEM_CORE_CLOCK / (25 * SSD1306_I2C_CLKRATE)) & I2C_CKCFGR_CCR; + tempreg |= I2C_CKCFGR_DUTY; #endif - tempreg |= I2C_CKCFGR_FS; + tempreg |= I2C_CKCFGR_FS; #endif - I2C1->CKCFGR = tempreg; + I2C1->CKCFGR = tempreg; #ifdef SSD1306_I2C_IRQ - // enable IRQ driven operation - NVIC_EnableIRQ(I2C1_EV_IRQn); - - // initialize the state - ssd1306_i2c_irq_state = 0; -#endif - - // Enable I2C - I2C1->CTLR1 |= I2C_CTLR1_PE; + // enable IRQ driven operation + NVIC_EnableIRQ(I2C1_EV_IRQn); - // set ACK mode - I2C1->CTLR1 |= I2C_CTLR1_ACK; + // initialize the state + ssd1306_i2c_irq_state = 0; +#endif + + // Enable I2C + I2C1->CTLR1 |= I2C_CTLR1_PE; + + // set ACK mode + I2C1->CTLR1 |= I2C_CTLR1_ACK; } /* * error descriptions */ char *errstr[] = -{ - "not busy", - "master mode", - "transmit mode", - "tx empty", - "transmit complete", + { + "not busy", + "master mode", + "transmit mode", + "tx empty", + "transmit complete", }; /* @@ -105,28 +105,28 @@ char *errstr[] = */ uint8_t ssd1306_i2c_error(uint8_t err) { - // report error - printf("ssd1306_i2c_error - timeout waiting for %s\n\r", errstr[err]); - - // reset & initialize I2C - ssd1306_i2c_setup(); + // report error + printf("ssd1306_i2c_error - timeout waiting for %s\n\r", errstr[err]); - return 1; + // reset & initialize I2C + ssd1306_i2c_setup(); + + return 1; } // event codes we use -#define SSD1306_I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ -#define SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ +#define SSD1306_I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /* * check for 32-bit event codes */ uint8_t ssd1306_i2c_chk_evt(uint32_t event_mask) { - /* read order matters here! STAR1 before STAR2!! */ - uint32_t status = I2C1->STAR1 | (I2C1->STAR2<<16); - return (status & event_mask) == event_mask; + /* read order matters here! STAR1 before STAR2!! */ + uint32_t status = I2C1->STAR1 | (I2C1->STAR2 << 16); + return (status & event_mask) == event_mask; } #ifdef SSD1306_I2C_IRQ @@ -135,63 +135,67 @@ uint8_t ssd1306_i2c_chk_evt(uint32_t event_mask) */ uint8_t ssd1306_i2c_send(uint8_t addr, uint8_t *data, uint8_t sz) { - int32_t timeout; - -#ifdef IRQ_DIAG - GPIOC->BSHR = (1<<(3)); -#endif - - // error out if buffer under/overflow - if((sz > sizeof(ssd1306_i2c_send_buffer)) || !sz) - return 2; - - // wait for previous packet to finish - while(ssd1306_i2c_irq_state); - -#ifdef IRQ_DIAG - GPIOC->BSHR = (1<<(16+3)); - GPIOC->BSHR = (1<<(4)); -#endif - - // init buffer for sending - ssd1306_i2c_send_sz = sz; - ssd1306_i2c_send_ptr = ssd1306_i2c_send_buffer; - memcpy((uint8_t *)ssd1306_i2c_send_buffer, data, sz); - - // wait for not busy - timeout = TIMEOUT_MAX; - while((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(0); - - // Set START condition - I2C1->CTLR1 |= I2C_CTLR1_START; - - // wait for master mode select - timeout = TIMEOUT_MAX; - while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(1); - - // send 7-bit address + write flag - I2C1->DATAR = addr<<1; - - // wait for transmit condition - timeout = TIMEOUT_MAX; - while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(2); - - // Enable TXE interrupt - I2C1->CTLR2 |= I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN; - ssd1306_i2c_irq_state = 1; + int32_t timeout; #ifdef IRQ_DIAG - GPIOC->BSHR = (1<<(16+4)); + GPIOC->BSHR = (1 << (3)); #endif - - // exit - return 0; + + // error out if buffer under/overflow + if ((sz > sizeof(ssd1306_i2c_send_buffer)) || !sz) + return 2; + + // wait for previous packet to finish + while (ssd1306_i2c_irq_state) + ; + +#ifdef IRQ_DIAG + GPIOC->BSHR = (1 << (16 + 3)); + GPIOC->BSHR = (1 << (4)); +#endif + + // init buffer for sending + ssd1306_i2c_send_sz = sz; + ssd1306_i2c_send_ptr = ssd1306_i2c_send_buffer; + memcpy((uint8_t *)ssd1306_i2c_send_buffer, data, sz); + + // wait for not busy + timeout = TIMEOUT_MAX; + while ((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(0); + + // Set START condition + I2C1->CTLR1 |= I2C_CTLR1_START; + + // wait for master mode select + timeout = TIMEOUT_MAX; + while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(1); + + // send 7-bit address + write flag + I2C1->DATAR = addr << 1; + + // wait for transmit condition + timeout = TIMEOUT_MAX; + while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(2); + + // Enable TXE interrupt + I2C1->CTLR2 |= I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN; + ssd1306_i2c_irq_state = 1; + +#ifdef IRQ_DIAG + GPIOC->BSHR = (1 << (16 + 4)); +#endif + + // exit + return 0; } /* @@ -200,42 +204,43 @@ uint8_t ssd1306_i2c_send(uint8_t addr, uint8_t *data, uint8_t sz) void I2C1_EV_IRQHandler(void) __attribute__((interrupt)); void I2C1_EV_IRQHandler(void) { - uint16_t STAR1, STAR2 __attribute__((unused)); - + uint16_t STAR1, STAR2 __attribute__((unused)); + #ifdef IRQ_DIAG - GPIOC->BSHR = (1<<(4)); + GPIOC->BSHR = (1 << (4)); #endif - // read status, clear any events - STAR1 = I2C1->STAR1; - STAR2 = I2C1->STAR2; - - /* check for TXE */ - if(STAR1 & I2C_STAR1_TXE) - { - /* check for remaining data */ - if(ssd1306_i2c_send_sz--) - I2C1->DATAR = *ssd1306_i2c_send_ptr++; + // read status, clear any events + STAR1 = I2C1->STAR1; + STAR2 = I2C1->STAR2; - /* was that the last byte? */ - if(!ssd1306_i2c_send_sz) - { - // disable TXE interrupt - I2C1->CTLR2 &= ~(I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN); - - // reset IRQ state - ssd1306_i2c_irq_state = 0; - - // wait for tx complete - while(!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + /* check for TXE */ + if (STAR1 & I2C_STAR1_TXE) + { + /* check for remaining data */ + if (ssd1306_i2c_send_sz--) + I2C1->DATAR = *ssd1306_i2c_send_ptr++; - // set STOP condition - I2C1->CTLR1 |= I2C_CTLR1_STOP; - } - } + /* was that the last byte? */ + if (!ssd1306_i2c_send_sz) + { + // disable TXE interrupt + I2C1->CTLR2 &= ~(I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN); + + // reset IRQ state + ssd1306_i2c_irq_state = 0; + + // wait for tx complete + while (!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + ; + + // set STOP condition + I2C1->CTLR1 |= I2C_CTLR1_STOP; + } + } #ifdef IRQ_DIAG - GPIOC->BSHR = (1<<(16+4)); + GPIOC->BSHR = (1 << (16 + 4)); #endif } #else @@ -244,56 +249,61 @@ void I2C1_EV_IRQHandler(void) */ uint8_t ssd1306_i2c_send(uint8_t addr, const uint8_t *data, int sz) { - int32_t timeout; - - // wait for not busy - timeout = TIMEOUT_MAX; - while((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(0); + int32_t timeout; - // Set START condition - I2C1->CTLR1 |= I2C_CTLR1_START; - - // wait for master mode select - timeout = TIMEOUT_MAX; - while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(1); - - // send 7-bit address + write flag - I2C1->DATAR = addr<<1; + // wait for not busy + timeout = TIMEOUT_MAX; + while ((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(0); - // wait for transmit condition - timeout = TIMEOUT_MAX; - while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(2); + // Set START condition + I2C1->CTLR1 |= I2C_CTLR1_START; - // send data one byte at a time - while(sz--) - { - // wait for TX Empty - timeout = TIMEOUT_MAX; - while(!(I2C1->STAR1 & I2C_STAR1_TXE) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(3); - - // send command - I2C1->DATAR = *data++; - } + // wait for master mode select + timeout = TIMEOUT_MAX; + while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(1); - // wait for tx complete - timeout = TIMEOUT_MAX; - while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) && (timeout--)); - if(timeout==-1) - return ssd1306_i2c_error(4); + // send 7-bit address + write flag + I2C1->DATAR = addr << 1; - // set STOP condition - I2C1->CTLR1 |= I2C_CTLR1_STOP; - - // we're happy - return 0; + // wait for transmit condition + timeout = TIMEOUT_MAX; + while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(2); + + // send data one byte at a time + while (sz--) + { + // wait for TX Empty + timeout = TIMEOUT_MAX; + while (!(I2C1->STAR1 & I2C_STAR1_TXE) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(3); + + // send command + I2C1->DATAR = *data++; + } + + // wait for tx complete + timeout = TIMEOUT_MAX; + while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) && (timeout--)) + ; + if (timeout == -1) + return ssd1306_i2c_error(4); + + // set STOP condition + I2C1->CTLR1 |= I2C_CTLR1_STOP; + + // we're happy + return 0; } #endif @@ -302,20 +312,20 @@ uint8_t ssd1306_i2c_send(uint8_t addr, const uint8_t *data, int sz) */ uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) { - uint8_t pkt[33]; - - /* build command or data packets */ - if(cmd) - { - pkt[0] = 0; - pkt[1] = *data; - } - else - { - pkt[0] = 0x40; - memcpy(&pkt[1], data, sz); - } - return ssd1306_i2c_send(SSD1306_I2C_ADDR, pkt, sz+1); + uint8_t pkt[33]; + + /* build command or data packets */ + if (cmd) + { + pkt[0] = 0; + pkt[1] = *data; + } + else + { + pkt[0] = 0x40; + memcpy(&pkt[1], data, sz); + } + return ssd1306_i2c_send(SSD1306_I2C_ADDR, pkt, sz + 1); } /* @@ -323,51 +333,51 @@ uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) */ uint8_t ssd1306_i2c_init(void) { - // Enable GPIOC and I2C - RCC->APB1PCENR |= RCC_APB1Periph_I2C1; + // Enable GPIOC and I2C + RCC->APB1PCENR |= RCC_APB1Periph_I2C1; #ifdef CH32V20x - RCC->APB2PCENR |= RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO; + RCC->APB2PCENR |= RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO; #ifdef SSD1306_REMAP_I2C - AFIO->PCFR1 |= AFIO_PCFR1_I2C1_REMAP; - funPinMode( PB8, GPIO_CFGLR_OUT_10Mhz_AF_OD ); - funPinMode( PB9, GPIO_CFGLR_OUT_10Mhz_AF_OD ); + AFIO->PCFR1 |= AFIO_PCFR1_I2C1_REMAP; + funPinMode(PB8, GPIO_CFGLR_OUT_10Mhz_AF_OD); + funPinMode(PB9, GPIO_CFGLR_OUT_10Mhz_AF_OD); #else - funPinMode( PB6, GPIO_CFGLR_OUT_10Mhz_AF_OD ); - funPinMode( PB7, GPIO_CFGLR_OUT_10Mhz_AF_OD ); + funPinMode(PB6, GPIO_CFGLR_OUT_10Mhz_AF_OD); + funPinMode(PB7, GPIO_CFGLR_OUT_10Mhz_AF_OD); #endif #else - RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO; - // PC1 is SDA, 10MHz Output, alt func, open-drain - GPIOC->CFGLR &= ~(0xf<<(4*1)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*1); - - // PC2 is SCL, 10MHz Output, alt func, open-drain - GPIOC->CFGLR &= ~(0xf<<(4*2)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*2); + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO; + // PC1 is SDA, 10MHz Output, alt func, open-drain + GPIOC->CFGLR &= ~(0xf << (4 * 1)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF) << (4 * 1); + + // PC2 is SCL, 10MHz Output, alt func, open-drain + GPIOC->CFGLR &= ~(0xf << (4 * 2)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF) << (4 * 2); #endif #ifdef IRQ_DIAG - // GPIO diags on PC3/PC4 - GPIOC->CFGLR &= ~(0xf<<(4*3)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*3); - GPIOC->BSHR = (1<<(16+3)); - GPIOC->CFGLR &= ~(0xf<<(4*4)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*4); - GPIOC->BSHR = (1<<(16+4)); + // GPIO diags on PC3/PC4 + GPIOC->CFGLR &= ~(0xf << (4 * 3)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 3); + GPIOC->BSHR = (1 << (16 + 3)); + GPIOC->CFGLR &= ~(0xf << (4 * 4)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4); + GPIOC->BSHR = (1 << (16 + 4)); #endif - // load I2C regs - ssd1306_i2c_setup(); - + // load I2C regs + ssd1306_i2c_setup(); + #if 0 // test if SSD1306 is on the bus by sending display off command uint8_t command = 0xAF; return ssd1306_pkt_send(&command, 1, 1); #else - return 0; + return 0; #endif } diff --git a/src/extralibs/ssd1306_i2c_bitbang.h b/src/extralibs/ssd1306_i2c_bitbang.h index 7ab3334..92c3acf 100644 --- a/src/extralibs/ssd1306_i2c_bitbang.h +++ b/src/extralibs/ssd1306_i2c_bitbang.h @@ -26,111 +26,115 @@ */ void ssd1306_i2c_setup(void) { - funGpioInitAll(); - funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP ); - funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 1 ); - funPinMode( SSD1306_I2C_BITBANG_SCL, GPIO_CFGLR_OUT_10Mhz_PP ); - funDigitalWrite( SSD1306_I2C_BITBANG_SCL, 1 ); + funGpioInitAll(); + funPinMode(SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP); + funDigitalWrite(SSD1306_I2C_BITBANG_SDA, 1); + funPinMode(SSD1306_I2C_BITBANG_SCL, GPIO_CFGLR_OUT_10Mhz_PP); + funDigitalWrite(SSD1306_I2C_BITBANG_SCL, 1); } -#define SDA_HIGH funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 1 ); -#define SCL_HIGH funDigitalWrite( SSD1306_I2C_BITBANG_SCL, 1 ); -#define SDA_LOW funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 0 ); -#define SCL_LOW funDigitalWrite( SSD1306_I2C_BITBANG_SCL, 0 ); -#define SDA_IN funDigitalRead( SSD1306_I2C_BITBANG_SDA ); +#define SDA_HIGH funDigitalWrite(SSD1306_I2C_BITBANG_SDA, 1); +#define SCL_HIGH funDigitalWrite(SSD1306_I2C_BITBANG_SCL, 1); +#define SDA_LOW funDigitalWrite(SSD1306_I2C_BITBANG_SDA, 0); +#define SCL_LOW funDigitalWrite(SSD1306_I2C_BITBANG_SCL, 0); +#define SDA_IN funDigitalRead(SSD1306_I2C_BITBANG_SDA); #define I2CSPEEDBASE 1 -#define I2CDELAY_FUNC(x) ADD_N_NOPS(x*1) -//Delay_Us(x*1); +#define I2CDELAY_FUNC(x) ADD_N_NOPS(x * 1) +// Delay_Us(x*1); static void ssd1306_i2c_sendstart() { - SCL_HIGH - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SDA_LOW - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SCL_LOW - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_HIGH + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SDA_LOW + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SCL_LOW + I2CDELAY_FUNC(1 * I2CSPEEDBASE); } void ssd1306_i2c_sendstop() { - SDA_LOW - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SCL_LOW - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SCL_HIGH - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SDA_HIGH - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SDA_LOW + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SCL_LOW + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SCL_HIGH + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SDA_HIGH + I2CDELAY_FUNC(1 * I2CSPEEDBASE); } -//Return nonzero on failure. -unsigned char ssd1306_i2c_sendbyte( unsigned char data ) +// Return nonzero on failure. +unsigned char ssd1306_i2c_sendbyte(unsigned char data) { - unsigned int i; - for( i = 0; i < 8; i++ ) - { - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - if( data & 0x80 ) - { SDA_HIGH; } - else - { SDA_LOW; } - data<<=1; - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SCL_HIGH - I2CDELAY_FUNC( 2 * I2CSPEEDBASE ); - SCL_LOW - } + unsigned int i; + for (i = 0; i < 8; i++) + { + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + if (data & 0x80) + { + SDA_HIGH; + } + else + { + SDA_LOW; + } + data <<= 1; + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SCL_HIGH + I2CDELAY_FUNC(2 * I2CSPEEDBASE); + SCL_LOW + } - //Immediately after sending last bit, open up DDDR for control. - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_IN_PUPD ); - SDA_HIGH - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SCL_HIGH - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - i = SDA_IN; - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SCL_LOW - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - SDA_HIGH // Maybe? - funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP ); - I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); - return !!i; + // Immediately after sending last bit, open up DDDR for control. + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + funPinMode(SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_IN_PUPD); + SDA_HIGH + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SCL_HIGH + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + i = SDA_IN; + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SCL_LOW + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + SDA_HIGH // Maybe? + funPinMode(SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP); + I2CDELAY_FUNC(1 * I2CSPEEDBASE); + return !!i; } uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) { - ssd1306_i2c_sendstart(); - int r = ssd1306_i2c_sendbyte( SSD1306_I2C_ADDR<<1 ); - if( r ) return r; - //ssd1306_i2c_sendstart(); For some reason displays don't want repeated start - if(cmd) - { - if( ssd1306_i2c_sendbyte( 0x00 ) ) - return 1; // Control - } - else - { - if( ssd1306_i2c_sendbyte( 0x40 ) ) - return 1; // Data - } - for( int i = 0; i < sz; i++ ) - { - if( ssd1306_i2c_sendbyte( data[i] ) ) - return 1; - } - ssd1306_i2c_sendstop(); - return 0; + ssd1306_i2c_sendstart(); + int r = ssd1306_i2c_sendbyte(SSD1306_I2C_ADDR << 1); + if (r) return r; + // ssd1306_i2c_sendstart(); For some reason displays don't want repeated start + if (cmd) + { + if (ssd1306_i2c_sendbyte(0x00)) + return 1; // Control + } + else + { + if (ssd1306_i2c_sendbyte(0x40)) + return 1; // Data + } + for (int i = 0; i < sz; i++) + { + if (ssd1306_i2c_sendbyte(data[i])) + return 1; + } + ssd1306_i2c_sendstop(); + return 0; } void ssd1306_rst(void) { - funPinMode( SSD1306_RST_PIN, GPIO_CFGLR_OUT_10Mhz_PP ); - funDigitalWrite( SSD1306_RST_PIN, 0 ); - Delay_Ms(10); - funDigitalWrite( SSD1306_RST_PIN, 1 ); - Delay_Us(10); + funPinMode(SSD1306_RST_PIN, GPIO_CFGLR_OUT_10Mhz_PP); + funDigitalWrite(SSD1306_RST_PIN, 0); + Delay_Ms(10); + funDigitalWrite(SSD1306_RST_PIN, 1); + Delay_Us(10); } #endif diff --git a/src/extralibs/ssd1306_spi.h b/src/extralibs/ssd1306_spi.h index bc7468c..7112fe8 100644 --- a/src/extralibs/ssd1306_spi.h +++ b/src/extralibs/ssd1306_spi.h @@ -24,7 +24,7 @@ #endif #ifndef SSD1306_SCK_PIN -#define SSD1306_SCK_PIN PC5 +#define SSD1306_SCK_PIN PC5 #endif #ifndef SSD1306_BAUD_RATE_PRESCALER @@ -36,31 +36,31 @@ */ uint8_t ssd1306_spi_init(void) { - // Enable GPIOC and SPI - RCC->APB2PCENR |= RCC_APB2Periph_SPI1; - - funGpioInitAll(); - funPinMode( SSD1306_RST_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); - funPinMode( SSD1306_CS_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); - funPinMode( SSD1306_DC_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); - funPinMode( SSD1306_MOSI_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP ); - funPinMode( SSD1306_SCK_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP ); + // Enable GPIOC and SPI + RCC->APB2PCENR |= RCC_APB2Periph_SPI1; - funDigitalWrite( SSD1306_RST_PIN, FUN_HIGH ); - funDigitalWrite( SSD1306_CS_PIN, FUN_HIGH ); - funDigitalWrite( SSD1306_DC_PIN, FUN_LOW ); + funGpioInitAll(); + funPinMode(SSD1306_RST_PIN, GPIO_CFGLR_OUT_50Mhz_PP); + funPinMode(SSD1306_CS_PIN, GPIO_CFGLR_OUT_50Mhz_PP); + funPinMode(SSD1306_DC_PIN, GPIO_CFGLR_OUT_50Mhz_PP); + funPinMode(SSD1306_MOSI_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP); + funPinMode(SSD1306_SCK_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP); - // Configure SPI - SPI1->CTLR1 = - SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_8b | - SPI_Mode_Master | SPI_Direction_1Line_Tx | - SSD1306_BAUD_RATE_PRESCALER; + funDigitalWrite(SSD1306_RST_PIN, FUN_HIGH); + funDigitalWrite(SSD1306_CS_PIN, FUN_HIGH); + funDigitalWrite(SSD1306_DC_PIN, FUN_LOW); - // enable SPI port - SPI1->CTLR1 |= CTLR1_SPE_Set; - - // always succeed - return 0; + // Configure SPI + SPI1->CTLR1 = + SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_8b | + SPI_Mode_Master | SPI_Direction_1Line_Tx | + SSD1306_BAUD_RATE_PRESCALER; + + // enable SPI port + SPI1->CTLR1 |= CTLR1_SPE_Set; + + // always succeed + return 0; } /* @@ -68,9 +68,9 @@ uint8_t ssd1306_spi_init(void) */ void ssd1306_rst(void) { - funDigitalWrite( SSD1306_RST_PIN, FUN_LOW ); - Delay_Ms(10); - funDigitalWrite( SSD1306_RST_PIN, FUN_HIGH ); + funDigitalWrite(SSD1306_RST_PIN, FUN_LOW); + Delay_Ms(10); + funDigitalWrite(SSD1306_RST_PIN, FUN_HIGH); } /* @@ -78,34 +78,35 @@ void ssd1306_rst(void) */ uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) { - if(cmd) - { - funDigitalWrite( SSD1306_DC_PIN, FUN_LOW ); - } - else - { - funDigitalWrite( SSD1306_DC_PIN, FUN_HIGH ); - } + if (cmd) + { + funDigitalWrite(SSD1306_DC_PIN, FUN_LOW); + } + else + { + funDigitalWrite(SSD1306_DC_PIN, FUN_HIGH); + } - funDigitalWrite( SSD1306_CS_PIN, FUN_LOW ); - - // send data - while(sz--) - { - // wait for TXE - while(!(SPI1->STATR & SPI_STATR_TXE)); - - // Send byte - SPI1->DATAR = *data++; - } - - // wait for not busy before exiting - while(SPI1->STATR & SPI_STATR_BSY) { } - - funDigitalWrite( SSD1306_CS_PIN, FUN_HIGH ); - - // we're happy - return 0; + funDigitalWrite(SSD1306_CS_PIN, FUN_LOW); + + // send data + while (sz--) + { + // wait for TXE + while (!(SPI1->STATR & SPI_STATR_TXE)) + ; + + // Send byte + SPI1->DATAR = *data++; + } + + // wait for not busy before exiting + while (SPI1->STATR & SPI_STATR_BSY) {} + + funDigitalWrite(SSD1306_CS_PIN, FUN_HIGH); + + // we're happy + return 0; } #endif diff --git a/src/extralibs/usb_defines.h b/src/extralibs/usb_defines.h index 1e4b9a2..e588982 100644 --- a/src/extralibs/usb_defines.h +++ b/src/extralibs/usb_defines.h @@ -37,714 +37,721 @@ #include #include - /*------------------------------------------------------------------*/ /* From Linux *------------------------------------------------------------------*/ +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ -#define USB_DIR_OUT 0 /* to device */ -#define USB_DIR_IN 0x80 /* to host */ - -#define USB_TYPE_MASK (0x03 << 5) -#define USB_TYPE_STANDARD (0x00 << 5) -#define USB_TYPE_CLASS (0x01 << 5) -#define USB_TYPE_VENDOR (0x02 << 5) -#define USB_TYPE_RESERVED (0x03 << 5) - +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) /* * USB recipients, the third of three bRequestType fields */ -#define USB_RECIP_MASK 0x1f -#define USB_RECIP_DEVICE 0x00 -#define USB_RECIP_INTERFACE 0x01 -#define USB_RECIP_ENDPOINT 0x02 -#define USB_RECIP_OTHER 0x03 +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 /* From Wireless USB 1.0 */ -#define USB_RECIP_PORT 0x04 -#define USB_RECIP_RPIPE 0x05 +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05 #define TU_ATTR_PACKED __attribute__((packed)) #ifndef TU_BIT -#define TU_BIT(n) (1U << (n)) +#define TU_BIT(n) (1U << (n)) #endif #ifndef TU_STRCAT -#define TU_STRCAT(a, b) a##b ///< concat without expand -#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat +#define TU_STRCAT(a, b) a##b ///< concat without expand +#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat #endif #ifndef _TU_COUNTER_ #if defined __COUNTER__ && __COUNTER__ != __COUNTER__ - #define _TU_COUNTER_ __COUNTER__ +#define _TU_COUNTER_ __COUNTER__ #else - #define _TU_COUNTER_ __LINE__ +#define _TU_COUNTER_ __LINE__ #endif #endif // Compile-time Assert -#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L - #define TU_VERIFY_STATIC _Static_assert -#elif defined (__cplusplus) && __cplusplus >= 201103L - #define TU_VERIFY_STATIC static_assert +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define TU_VERIFY_STATIC _Static_assert +#elif defined(__cplusplus) && __cplusplus >= 201103L +#define TU_VERIFY_STATIC static_assert #else - #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) } +#define TU_VERIFY_STATIC(const_expr, _mess) \ + enum \ + { \ + TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1 / (!!(const_expr)) \ + } #endif #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif -/*------------------------------------------------------------------*/ -/* CONSTANTS - *------------------------------------------------------------------*/ - -/// defined base on EHCI specs value for Endpoint Speed -typedef enum -{ - TUSB_SPEED_FULL = 0, - TUSB_SPEED_LOW , - TUSB_SPEED_HIGH, - TUSB_SPEED_INVALID = 0xff, -}tusb_speed_t; - -/// defined base on USB Specs Endpoint's bmAttributes -typedef enum -{ - TUSB_XFER_CONTROL = 0 , - TUSB_XFER_ISOCHRONOUS , - TUSB_XFER_BULK , - TUSB_XFER_INTERRUPT -}tusb_xfer_type_t; - -typedef enum -{ - TUSB_DIR_OUT = 0, - TUSB_DIR_IN = 1, - - TUSB_DIR_IN_MASK = 0x80 -}tusb_dir_t; - -/// USB Descriptor Types -typedef enum -{ - TUSB_DESC_DEVICE = 0x01, - TUSB_DESC_CONFIGURATION = 0x02, - TUSB_DESC_STRING = 0x03, - TUSB_DESC_INTERFACE = 0x04, - TUSB_DESC_ENDPOINT = 0x05, - TUSB_DESC_DEVICE_QUALIFIER = 0x06, - TUSB_DESC_OTHER_SPEED_CONFIG = 0x07, - TUSB_DESC_INTERFACE_POWER = 0x08, - TUSB_DESC_OTG = 0x09, - TUSB_DESC_DEBUG = 0x0A, - TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B, - - TUSB_DESC_BOS = 0x0F, - TUSB_DESC_DEVICE_CAPABILITY = 0x10, - - TUSB_DESC_FUNCTIONAL = 0x21, - - // Class Specific Descriptor - TUSB_DESC_CS_DEVICE = 0x21, - TUSB_DESC_CS_CONFIGURATION = 0x22, - TUSB_DESC_CS_STRING = 0x23, - TUSB_DESC_CS_INTERFACE = 0x24, - TUSB_DESC_CS_ENDPOINT = 0x25, - - TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, - TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 -}tusb_desc_type_t; - -typedef enum -{ - TUSB_REQ_GET_STATUS = 0 , - TUSB_REQ_CLEAR_FEATURE = 1 , - TUSB_REQ_RESERVED = 2 , - TUSB_REQ_SET_FEATURE = 3 , - TUSB_REQ_RESERVED2 = 4 , - TUSB_REQ_SET_ADDRESS = 5 , - TUSB_REQ_GET_DESCRIPTOR = 6 , - TUSB_REQ_SET_DESCRIPTOR = 7 , - TUSB_REQ_GET_CONFIGURATION = 8 , - TUSB_REQ_SET_CONFIGURATION = 9 , - TUSB_REQ_GET_INTERFACE = 10 , - TUSB_REQ_SET_INTERFACE = 11 , - TUSB_REQ_SYNCH_FRAME = 12 -}tusb_request_code_t; - -typedef enum -{ - TUSB_REQ_FEATURE_EDPT_HALT = 0, - TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, - TUSB_REQ_FEATURE_TEST_MODE = 2 -}tusb_request_feature_selector_t; - -typedef enum -{ - TUSB_REQ_TYPE_STANDARD = 0, - TUSB_REQ_TYPE_CLASS, - TUSB_REQ_TYPE_VENDOR, - TUSB_REQ_TYPE_INVALID -} tusb_request_type_t; - -typedef enum -{ - TUSB_REQ_RCPT_DEVICE =0, - TUSB_REQ_RCPT_INTERFACE, - TUSB_REQ_RCPT_ENDPOINT, - TUSB_REQ_RCPT_OTHER -} tusb_request_recipient_t; - -// https://www.usb.org/defined-class-codes -typedef enum -{ - TUSB_CLASS_UNSPECIFIED = 0 , - TUSB_CLASS_AUDIO = 1 , - TUSB_CLASS_CDC = 2 , - TUSB_CLASS_HID = 3 , - TUSB_CLASS_RESERVED_4 = 4 , - TUSB_CLASS_PHYSICAL = 5 , - TUSB_CLASS_IMAGE = 6 , - TUSB_CLASS_PRINTER = 7 , - TUSB_CLASS_MSC = 8 , - TUSB_CLASS_HUB = 9 , - TUSB_CLASS_CDC_DATA = 10 , - TUSB_CLASS_SMART_CARD = 11 , - TUSB_CLASS_RESERVED_12 = 12 , - TUSB_CLASS_CONTENT_SECURITY = 13 , - TUSB_CLASS_VIDEO = 14 , - TUSB_CLASS_PERSONAL_HEALTHCARE = 15 , - TUSB_CLASS_AUDIO_VIDEO = 16 , - - TUSB_CLASS_DIAGNOSTIC = 0xDC , - TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0 , - TUSB_CLASS_MISC = 0xEF , - TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE , - TUSB_CLASS_VENDOR_SPECIFIC = 0xFF -}tusb_class_code_t; - -typedef enum -{ - MISC_SUBCLASS_COMMON = 2 -}misc_subclass_type_t; - -typedef enum -{ - MISC_PROTOCOL_IAD = 1 -}misc_protocol_type_t; - -typedef enum -{ - APP_SUBCLASS_USBTMC = 0x03, - APP_SUBCLASS_DFU_RUNTIME = 0x01 -} app_subclass_type_t; - -typedef enum -{ - DEVICE_CAPABILITY_WIRELESS_USB = 0x01, - DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, - DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, - DEVICE_CAPABILITY_CONTAINER_id = 0x04, - DEVICE_CAPABILITY_PLATFORM = 0x05, - DEVICE_CAPABILITY_POWER_DELIVERY = 0x06, - DEVICE_CAPABILITY_BATTERY_INFO = 0x07, - DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08, - DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09, - DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A, - DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B, - DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C, - DEVICE_CAPABILITY_BILLBOARD = 0x0D, - DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, - DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, - DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 -}device_capability_type_t; - -enum { - TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), - TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6), -}; - -#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2) - -/// Device State TODO remove -typedef enum -{ - TUSB_DEVICE_STATE_UNPLUG = 0 , - TUSB_DEVICE_STATE_CONFIGURED , - TUSB_DEVICE_STATE_SUSPENDED , -}tusb_device_state_t; - -typedef enum -{ - XFER_RESULT_SUCCESS, - XFER_RESULT_FAILED, - XFER_RESULT_STALLED, -}xfer_result_t; - -enum // TODO remove -{ - DESC_OFFSET_LEN = 0, - DESC_OFFSET_TYPE = 1 -}; - -enum -{ - INTERFACE_INVALID_NUMBER = 0xff -}; - - -typedef enum -{ - MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, - MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, - MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, - MS_OS_20_FEATURE_COMPATBLE_ID = 0x03, - MS_OS_20_FEATURE_REG_PROPERTY = 0x04, - MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05, - MS_OS_20_FEATURE_MODEL_ID = 0x06, - MS_OS_20_FEATURE_CCGP_DEVICE = 0x07, - MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 -} microsoft_os_20_type_t; - -enum -{ - CONTROL_STAGE_SETUP, - CONTROL_STAGE_DATA, - CONTROL_STAGE_ACK -}; - -//--------------------------------------------------------------------+ -// USB Descriptors -//--------------------------------------------------------------------+ - -/// USB Device Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType ; ///< DEVICE Descriptor Type. - uint16_t bcdUSB ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. - - uint8_t bDeviceClass ; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific. - uint8_t bDeviceSubClass ; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. - uint8_t bDeviceProtocol ; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis. - uint8_t bMaxPacketSize0 ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. - - uint16_t idVendor ; ///< Vendor ID (assigned by the USB-IF). - uint16_t idProduct ; ///< Product ID (assigned by the manufacturer). - uint16_t bcdDevice ; ///< Device release number in binary-coded decimal. - uint8_t iManufacturer ; ///< Index of string descriptor describing manufacturer. - uint8_t iProduct ; ///< Index of string descriptor describing product. - uint8_t iSerialNumber ; ///< Index of string descriptor describing the device's serial number. - - uint8_t bNumConfigurations ; ///< Number of possible configurations. -} tusb_desc_device_t; - -TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct"); - -// USB Binary Device Object Store (BOS) Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of this descriptor in bytes - uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type - uint16_t wTotalLength ; ///< Total length of data returned for this descriptor - uint8_t bNumDeviceCaps ; ///< Number of device capability descriptors in the BOS -} tusb_desc_bos_t; - -/// USB Configuration Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of this descriptor in bytes - uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type - uint16_t wTotalLength ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. - - uint8_t bNumInterfaces ; ///< Number of interfaces supported by this configuration - uint8_t bConfigurationValue ; ///< Value to use as an argument to the SetConfiguration() request to select this configuration. - uint8_t iConfiguration ; ///< Index of string descriptor describing this configuration - uint8_t bmAttributes ; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one. - uint8_t bMaxPower ; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA). -} tusb_desc_configuration_t; - -/// USB Interface Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of this descriptor in bytes - uint8_t bDescriptorType ; ///< INTERFACE Descriptor Type - - uint8_t bInterfaceNumber ; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. - uint8_t bAlternateSetting ; ///< Value used to select this alternate setting for the interface identified in the prior field - uint8_t bNumEndpoints ; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe. - uint8_t bInterfaceClass ; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF. - uint8_t bInterfaceSubClass ; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. - uint8_t bInterfaceProtocol ; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface. - uint8_t iInterface ; ///< Index of string descriptor describing this interface -} tusb_desc_interface_t; - -/// USB Endpoint Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of this descriptor in bytes - uint8_t bDescriptorType ; ///< ENDPOINT Descriptor Type - - uint8_t bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint. - - struct TU_ATTR_PACKED { - uint8_t xfer : 2; - uint8_t sync : 2; - uint8_t usage : 2; - uint8_t : 2; - } bmAttributes ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host. - - struct TU_ATTR_PACKED { - uint16_t size : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero. - uint16_t hs_period_mult : 2; - uint16_t TU_RESERVED : 3; - }wMaxPacketSize; - - uint8_t bInterval ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information. -} tusb_desc_endpoint_t; - -/// USB Other Speed Configuration Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of descriptor - uint8_t bDescriptorType ; ///< Other_speed_Configuration Type - uint16_t wTotalLength ; ///< Total length of data returned - - uint8_t bNumInterfaces ; ///< Number of interfaces supported by this speed configuration - uint8_t bConfigurationValue ; ///< Value to use to select configuration - uint8_t IConfiguration ; ///< Index of string descriptor - uint8_t bmAttributes ; ///< Same as Configuration descriptor - uint8_t bMaxPower ; ///< Same as Configuration descriptor -} tusb_desc_other_speed_t; - -/// USB Device Qualifier Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of descriptor - uint8_t bDescriptorType ; ///< Device Qualifier Type - uint16_t bcdUSB ; ///< USB specification version number (e.g., 0200H for V2.00) - - uint8_t bDeviceClass ; ///< Class Code - uint8_t bDeviceSubClass ; ///< SubClass Code - uint8_t bDeviceProtocol ; ///< Protocol Code - uint8_t bMaxPacketSize0 ; ///< Maximum packet size for other speed - uint8_t bNumConfigurations ; ///< Number of Other-speed Configurations - uint8_t bReserved ; ///< Reserved for future use, must be zero -} tusb_desc_device_qualifier_t; - -/// USB Interface Association Descriptor (IAD ECN) -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of descriptor - uint8_t bDescriptorType ; ///< Other_speed_Configuration Type - - uint8_t bFirstInterface ; ///< Index of the first associated interface. - uint8_t bInterfaceCount ; ///< Total number of associated interfaces. - - uint8_t bFunctionClass ; ///< Interface class ID. - uint8_t bFunctionSubClass ; ///< Interface subclass ID. - uint8_t bFunctionProtocol ; ///< Interface protocol ID. - - uint8_t iFunction ; ///< Index of the string descriptor describing the interface association. -} tusb_desc_interface_assoc_t; - -// USB String Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength ; ///< Size of this descriptor in bytes - uint8_t bDescriptorType ; ///< Descriptor Type - uint16_t unicode_string[]; -} tusb_desc_string_t; - -// USB Binary Device Object Store (BOS) -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength; - uint8_t bDescriptorType ; - uint8_t bDevCapabilityType; - uint8_t bReserved; - uint8_t PlatformCapabilityUUID[16]; - uint8_t CapabilityData[]; -} tusb_desc_bos_platform_t; - -// USB WebuSB URL Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bScheme; - char url[]; -} tusb_desc_webusb_url_t; - -/*------------------------------------------------------------------*/ -/* Types - *------------------------------------------------------------------*/ -typedef struct TU_ATTR_PACKED{ - union { - struct TU_ATTR_PACKED { - uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. - uint8_t type : 2; ///< Request type tusb_request_type_t. - uint8_t direction : 1; ///< Direction type. tusb_dir_t - } bmRequestType_bit; - - uint8_t bmRequestType; - }; - - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} tusb_control_request_t; - -TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); - -// TODO move to somewhere suitable -static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient) -{ - return ((uint8_t) (direction << 7)) | ((uint8_t) (type << 5)) | (recipient); -} - -//--------------------------------------------------------------------+ -// Endpoint helper -//--------------------------------------------------------------------+ - -// Get direction from Endpoint address -static inline tusb_dir_t tu_edpt_dir(uint8_t addr) -{ - return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; -} - -// Get Endpoint number from address -static inline uint8_t tu_edpt_number(uint8_t addr) -{ - return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); -} - -static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) -{ - return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); -} - -//--------------------------------------------------------------------+ -// Descriptor helper -//--------------------------------------------------------------------+ -static inline uint8_t const * tu_desc_next(void const* desc) -{ - uint8_t const* desc8 = (uint8_t const*) desc; - return desc8 + desc8[DESC_OFFSET_LEN]; -} - -static inline uint8_t tu_desc_type(void const* desc) -{ - return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; -} - -static inline uint8_t tu_desc_len(void const* desc) -{ - return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; -} + /*------------------------------------------------------------------*/ + /* CONSTANTS + *------------------------------------------------------------------*/ + + /// defined base on EHCI specs value for Endpoint Speed + typedef enum + { + TUSB_SPEED_FULL = 0, + TUSB_SPEED_LOW, + TUSB_SPEED_HIGH, + TUSB_SPEED_INVALID = 0xff, + } tusb_speed_t; + + /// defined base on USB Specs Endpoint's bmAttributes + typedef enum + { + TUSB_XFER_CONTROL = 0, + TUSB_XFER_ISOCHRONOUS, + TUSB_XFER_BULK, + TUSB_XFER_INTERRUPT + } tusb_xfer_type_t; + + typedef enum + { + TUSB_DIR_OUT = 0, + TUSB_DIR_IN = 1, + + TUSB_DIR_IN_MASK = 0x80 + } tusb_dir_t; + + /// USB Descriptor Types + typedef enum + { + TUSB_DESC_DEVICE = 0x01, + TUSB_DESC_CONFIGURATION = 0x02, + TUSB_DESC_STRING = 0x03, + TUSB_DESC_INTERFACE = 0x04, + TUSB_DESC_ENDPOINT = 0x05, + TUSB_DESC_DEVICE_QUALIFIER = 0x06, + TUSB_DESC_OTHER_SPEED_CONFIG = 0x07, + TUSB_DESC_INTERFACE_POWER = 0x08, + TUSB_DESC_OTG = 0x09, + TUSB_DESC_DEBUG = 0x0A, + TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B, + + TUSB_DESC_BOS = 0x0F, + TUSB_DESC_DEVICE_CAPABILITY = 0x10, + + TUSB_DESC_FUNCTIONAL = 0x21, + + // Class Specific Descriptor + TUSB_DESC_CS_DEVICE = 0x21, + TUSB_DESC_CS_CONFIGURATION = 0x22, + TUSB_DESC_CS_STRING = 0x23, + TUSB_DESC_CS_INTERFACE = 0x24, + TUSB_DESC_CS_ENDPOINT = 0x25, + + TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, + TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 + } tusb_desc_type_t; + + typedef enum + { + TUSB_REQ_GET_STATUS = 0, + TUSB_REQ_CLEAR_FEATURE = 1, + TUSB_REQ_RESERVED = 2, + TUSB_REQ_SET_FEATURE = 3, + TUSB_REQ_RESERVED2 = 4, + TUSB_REQ_SET_ADDRESS = 5, + TUSB_REQ_GET_DESCRIPTOR = 6, + TUSB_REQ_SET_DESCRIPTOR = 7, + TUSB_REQ_GET_CONFIGURATION = 8, + TUSB_REQ_SET_CONFIGURATION = 9, + TUSB_REQ_GET_INTERFACE = 10, + TUSB_REQ_SET_INTERFACE = 11, + TUSB_REQ_SYNCH_FRAME = 12 + } tusb_request_code_t; + + typedef enum + { + TUSB_REQ_FEATURE_EDPT_HALT = 0, + TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, + TUSB_REQ_FEATURE_TEST_MODE = 2 + } tusb_request_feature_selector_t; + + typedef enum + { + TUSB_REQ_TYPE_STANDARD = 0, + TUSB_REQ_TYPE_CLASS, + TUSB_REQ_TYPE_VENDOR, + TUSB_REQ_TYPE_INVALID + } tusb_request_type_t; + + typedef enum + { + TUSB_REQ_RCPT_DEVICE = 0, + TUSB_REQ_RCPT_INTERFACE, + TUSB_REQ_RCPT_ENDPOINT, + TUSB_REQ_RCPT_OTHER + } tusb_request_recipient_t; + + // https://www.usb.org/defined-class-codes + typedef enum + { + TUSB_CLASS_UNSPECIFIED = 0, + TUSB_CLASS_AUDIO = 1, + TUSB_CLASS_CDC = 2, + TUSB_CLASS_HID = 3, + TUSB_CLASS_RESERVED_4 = 4, + TUSB_CLASS_PHYSICAL = 5, + TUSB_CLASS_IMAGE = 6, + TUSB_CLASS_PRINTER = 7, + TUSB_CLASS_MSC = 8, + TUSB_CLASS_HUB = 9, + TUSB_CLASS_CDC_DATA = 10, + TUSB_CLASS_SMART_CARD = 11, + TUSB_CLASS_RESERVED_12 = 12, + TUSB_CLASS_CONTENT_SECURITY = 13, + TUSB_CLASS_VIDEO = 14, + TUSB_CLASS_PERSONAL_HEALTHCARE = 15, + TUSB_CLASS_AUDIO_VIDEO = 16, + + TUSB_CLASS_DIAGNOSTIC = 0xDC, + TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0, + TUSB_CLASS_MISC = 0xEF, + TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE, + TUSB_CLASS_VENDOR_SPECIFIC = 0xFF + } tusb_class_code_t; + + typedef enum + { + MISC_SUBCLASS_COMMON = 2 + } misc_subclass_type_t; + + typedef enum + { + MISC_PROTOCOL_IAD = 1 + } misc_protocol_type_t; + + typedef enum + { + APP_SUBCLASS_USBTMC = 0x03, + APP_SUBCLASS_DFU_RUNTIME = 0x01 + } app_subclass_type_t; + + typedef enum + { + DEVICE_CAPABILITY_WIRELESS_USB = 0x01, + DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, + DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, + DEVICE_CAPABILITY_CONTAINER_id = 0x04, + DEVICE_CAPABILITY_PLATFORM = 0x05, + DEVICE_CAPABILITY_POWER_DELIVERY = 0x06, + DEVICE_CAPABILITY_BATTERY_INFO = 0x07, + DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08, + DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09, + DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A, + DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B, + DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C, + DEVICE_CAPABILITY_BILLBOARD = 0x0D, + DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, + DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, + DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 + } device_capability_type_t; + + enum + { + TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), + TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6), + }; + +#define TUSB_DESC_CONFIG_POWER_MA(x) ((x) / 2) + + /// Device State TODO remove + typedef enum + { + TUSB_DEVICE_STATE_UNPLUG = 0, + TUSB_DEVICE_STATE_CONFIGURED, + TUSB_DEVICE_STATE_SUSPENDED, + } tusb_device_state_t; + + typedef enum + { + XFER_RESULT_SUCCESS, + XFER_RESULT_FAILED, + XFER_RESULT_STALLED, + } xfer_result_t; + + enum // TODO remove + { + DESC_OFFSET_LEN = 0, + DESC_OFFSET_TYPE = 1 + }; + + enum + { + INTERFACE_INVALID_NUMBER = 0xff + }; + + typedef enum + { + MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, + MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, + MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, + MS_OS_20_FEATURE_COMPATBLE_ID = 0x03, + MS_OS_20_FEATURE_REG_PROPERTY = 0x04, + MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05, + MS_OS_20_FEATURE_MODEL_ID = 0x06, + MS_OS_20_FEATURE_CCGP_DEVICE = 0x07, + MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 + } microsoft_os_20_type_t; + + enum + { + CONTROL_STAGE_SETUP, + CONTROL_STAGE_DATA, + CONTROL_STAGE_ACK + }; + + //--------------------------------------------------------------------+ + // USB Descriptors + //--------------------------------------------------------------------+ + + /// USB Device Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< DEVICE Descriptor Type. + uint16_t bcdUSB; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. + + uint8_t bDeviceClass; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific. + uint8_t bDeviceSubClass; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. + uint8_t bDeviceProtocol; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis. + uint8_t bMaxPacketSize0; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. + + uint16_t idVendor; ///< Vendor ID (assigned by the USB-IF). + uint16_t idProduct; ///< Product ID (assigned by the manufacturer). + uint16_t bcdDevice; ///< Device release number in binary-coded decimal. + uint8_t iManufacturer; ///< Index of string descriptor describing manufacturer. + uint8_t iProduct; ///< Index of string descriptor describing product. + uint8_t iSerialNumber; ///< Index of string descriptor describing the device's serial number. + + uint8_t bNumConfigurations; ///< Number of possible configurations. + } tusb_desc_device_t; + + TU_VERIFY_STATIC(sizeof(tusb_desc_device_t) == 18, "size is not correct"); + + // USB Binary Device Object Store (BOS) Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes + uint8_t bDescriptorType; ///< CONFIGURATION Descriptor Type + uint16_t wTotalLength; ///< Total length of data returned for this descriptor + uint8_t bNumDeviceCaps; ///< Number of device capability descriptors in the BOS + } tusb_desc_bos_t; + + /// USB Configuration Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes + uint8_t bDescriptorType; ///< CONFIGURATION Descriptor Type + uint16_t wTotalLength; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. + + uint8_t bNumInterfaces; ///< Number of interfaces supported by this configuration + uint8_t bConfigurationValue; ///< Value to use as an argument to the SetConfiguration() request to select this configuration. + uint8_t iConfiguration; ///< Index of string descriptor describing this configuration + uint8_t bmAttributes; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one. + uint8_t bMaxPower; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA). + } tusb_desc_configuration_t; + + /// USB Interface Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes + uint8_t bDescriptorType; ///< INTERFACE Descriptor Type + + uint8_t bInterfaceNumber; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. + uint8_t bAlternateSetting; ///< Value used to select this alternate setting for the interface identified in the prior field + uint8_t bNumEndpoints; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe. + uint8_t bInterfaceClass; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF. + uint8_t bInterfaceSubClass; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. + uint8_t bInterfaceProtocol; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface. + uint8_t iInterface; ///< Index of string descriptor describing this interface + } tusb_desc_interface_t; + + /// USB Endpoint Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes + uint8_t bDescriptorType; ///< ENDPOINT Descriptor Type + + uint8_t bEndpointAddress; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint. + + struct TU_ATTR_PACKED + { + uint8_t xfer : 2; + uint8_t sync : 2; + uint8_t usage : 2; + uint8_t : 2; + } bmAttributes; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host. + + struct TU_ATTR_PACKED + { + uint16_t size : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero. + uint16_t hs_period_mult : 2; + uint16_t TU_RESERVED : 3; + } wMaxPacketSize; + + uint8_t bInterval; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information. + } tusb_desc_endpoint_t; + + /// USB Other Speed Configuration Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of descriptor + uint8_t bDescriptorType; ///< Other_speed_Configuration Type + uint16_t wTotalLength; ///< Total length of data returned + + uint8_t bNumInterfaces; ///< Number of interfaces supported by this speed configuration + uint8_t bConfigurationValue; ///< Value to use to select configuration + uint8_t IConfiguration; ///< Index of string descriptor + uint8_t bmAttributes; ///< Same as Configuration descriptor + uint8_t bMaxPower; ///< Same as Configuration descriptor + } tusb_desc_other_speed_t; + + /// USB Device Qualifier Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of descriptor + uint8_t bDescriptorType; ///< Device Qualifier Type + uint16_t bcdUSB; ///< USB specification version number (e.g., 0200H for V2.00) + + uint8_t bDeviceClass; ///< Class Code + uint8_t bDeviceSubClass; ///< SubClass Code + uint8_t bDeviceProtocol; ///< Protocol Code + uint8_t bMaxPacketSize0; ///< Maximum packet size for other speed + uint8_t bNumConfigurations; ///< Number of Other-speed Configurations + uint8_t bReserved; ///< Reserved for future use, must be zero + } tusb_desc_device_qualifier_t; + + /// USB Interface Association Descriptor (IAD ECN) + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of descriptor + uint8_t bDescriptorType; ///< Other_speed_Configuration Type + + uint8_t bFirstInterface; ///< Index of the first associated interface. + uint8_t bInterfaceCount; ///< Total number of associated interfaces. + + uint8_t bFunctionClass; ///< Interface class ID. + uint8_t bFunctionSubClass; ///< Interface subclass ID. + uint8_t bFunctionProtocol; ///< Interface protocol ID. + + uint8_t iFunction; ///< Index of the string descriptor describing the interface association. + } tusb_desc_interface_assoc_t; + + // USB String Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes + uint8_t bDescriptorType; ///< Descriptor Type + uint16_t unicode_string[]; + } tusb_desc_string_t; + + // USB Binary Device Object Store (BOS) + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; + uint8_t CapabilityData[]; + } tusb_desc_bos_platform_t; + + // USB WebuSB URL Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char url[]; + } tusb_desc_webusb_url_t; + + /*------------------------------------------------------------------*/ + /* Types + *------------------------------------------------------------------*/ + typedef struct TU_ATTR_PACKED + { + union + { + struct TU_ATTR_PACKED + { + uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. + uint8_t type : 2; ///< Request type tusb_request_type_t. + uint8_t direction : 1; ///< Direction type. tusb_dir_t + } bmRequestType_bit; + + uint8_t bmRequestType; + }; + + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + } tusb_control_request_t; + + TU_VERIFY_STATIC(sizeof(tusb_control_request_t) == 8, "size is not correct"); + + // TODO move to somewhere suitable + static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient) + { + return ((uint8_t)(direction << 7)) | ((uint8_t)(type << 5)) | (recipient); + } + + //--------------------------------------------------------------------+ + // Endpoint helper + //--------------------------------------------------------------------+ + + // Get direction from Endpoint address + static inline tusb_dir_t tu_edpt_dir(uint8_t addr) + { + return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + } + + // Get Endpoint number from address + static inline uint8_t tu_edpt_number(uint8_t addr) + { + return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); + } + + static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) + { + return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); + } + + //--------------------------------------------------------------------+ + // Descriptor helper + //--------------------------------------------------------------------+ + static inline uint8_t const *tu_desc_next(void const *desc) + { + uint8_t const *desc8 = (uint8_t const *)desc; + return desc8 + desc8[DESC_OFFSET_LEN]; + } + + static inline uint8_t tu_desc_type(void const *desc) + { + return ((uint8_t const *)desc)[DESC_OFFSET_TYPE]; + } + + static inline uint8_t tu_desc_len(void const *desc) + { + return ((uint8_t const *)desc)[DESC_OFFSET_LEN]; + } #ifdef __cplusplus - } +} #endif - // from tinyusb_hid.h #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif -#define TU_U16_HIGH(u16) ((uint8_t) (((u16) >> 8) & 0x00ff)) -#define TU_U16_LOW(u16) ((uint8_t) ((u16) & 0x00ff)) -#define U16_TO_U8S_BE(u16) TU_U16_HIGH(u16), TU_U16_LOW(u16) -#define U16_TO_U8S_LE(u16) TU_U16_LOW(u16), TU_U16_HIGH(u16) +#define TU_U16_HIGH(u16) ((uint8_t)(((u16) >> 8) & 0x00ff)) +#define TU_U16_LOW(u16) ((uint8_t)((u16) & 0x00ff)) +#define U16_TO_U8S_BE(u16) TU_U16_HIGH(u16), TU_U16_LOW(u16) +#define U16_TO_U8S_LE(u16) TU_U16_LOW(u16), TU_U16_HIGH(u16) #ifndef TU_ATTR_PACKED #define TU_ATTR_PACKED __attribute__((packed)) #endif #ifndef TU_BIT -#define TU_BIT( x ) (1<<(x)) +#define TU_BIT(x) (1 << (x)) #endif /* USB constant and structure define */ /* USB PID */ #ifndef USB_PID_SETUP - #define USB_PID_NULL 0x00 /* reserved PID */ - #define USB_PID_SOF 0x05 - #define USB_PID_SETUP 0x0D - #define USB_PID_IN 0x09 - #define USB_PID_OUT 0x01 - #define USB_PID_ACK 0x02 - #define USB_PID_NAK 0x0A - #define USB_PID_STALL 0x0E - #define USB_PID_DATA0 0x03 - #define USB_PID_DATA1 0x0B - #define USB_PID_PRE 0x0C +#define USB_PID_NULL 0x00 /* reserved PID */ +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C #endif /* USB standard device request code */ #ifndef USB_GET_DESCRIPTOR - #define USB_GET_STATUS 0x00 - #define USB_CLEAR_FEATURE 0x01 - #define USB_SET_FEATURE 0x03 - #define USB_SET_ADDRESS 0x05 - #define USB_GET_DESCRIPTOR 0x06 - #define USB_SET_DESCRIPTOR 0x07 - #define USB_GET_CONFIGURATION 0x08 - #define USB_SET_CONFIGURATION 0x09 - #define USB_GET_INTERFACE 0x0A - #define USB_SET_INTERFACE 0x0B - #define USB_SYNCH_FRAME 0x0C +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C #endif /* USB hub class request code */ #ifndef HUB_GET_DESCRIPTOR - #define HUB_GET_STATUS 0x00 - #define HUB_CLEAR_FEATURE 0x01 - #define HUB_GET_STATE 0x02 - #define HUB_SET_FEATURE 0x03 - #define HUB_GET_DESCRIPTOR 0x06 - #define HUB_SET_DESCRIPTOR 0x07 +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 #endif /* USB HID class request code */ #ifndef HID_GET_REPORT - #define HID_GET_REPORT 0x01 - #define HID_GET_IDLE 0x02 - #define HID_GET_PROTOCOL 0x03 - #define HID_SET_REPORT 0x09 - #define HID_SET_IDLE 0x0A - #define HID_SET_PROTOCOL 0x0B +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B #endif /* USB CDC Class request code */ #ifndef CDC_GET_LINE_CODING -#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ -#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ -#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ -#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ #endif /* Bit define for USB request type */ #ifndef USB_REQ_TYP_MASK - #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ - #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ - #define USB_REQ_TYP_READ 0x80 /* control read, device to host */ - #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ - #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ - #define USB_REQ_TYP_STANDARD 0x00 - #define USB_REQ_TYP_CLASS 0x20 - #define USB_REQ_TYP_VENDOR 0x40 - #define USB_REQ_TYP_RESERVED 0x60 - #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ - #define USB_REQ_RECIP_DEVICE 0x00 - #define USB_REQ_RECIP_INTERF 0x01 - #define USB_REQ_RECIP_ENDP 0x02 - #define USB_REQ_RECIP_OTHER 0x03 - #define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 - #define USB_REQ_FEAT_ENDP_HALT 0x00 +#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ +#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ +#define USB_REQ_TYP_READ 0x80 /* control read, device to host */ +#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ +#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 #endif /* USB request type for hub class request */ #ifndef HUB_GET_HUB_DESCRIPTOR - #define HUB_CLEAR_HUB_FEATURE 0x20 - #define HUB_CLEAR_PORT_FEATURE 0x23 - #define HUB_GET_BUS_STATE 0xA3 - #define HUB_GET_HUB_DESCRIPTOR 0xA0 - #define HUB_GET_HUB_STATUS 0xA0 - #define HUB_GET_PORT_STATUS 0xA3 - #define HUB_SET_HUB_DESCRIPTOR 0x20 - #define HUB_SET_HUB_FEATURE 0x20 - #define HUB_SET_PORT_FEATURE 0x23 +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 #endif /* Hub class feature selectors */ #ifndef HUB_PORT_RESET - #define HUB_C_HUB_LOCAL_POWER 0 - #define HUB_C_HUB_OVER_CURRENT 1 - #define HUB_PORT_CONNECTION 0 - #define HUB_PORT_ENABLE 1 - #define HUB_PORT_SUSPEND 2 - #define HUB_PORT_OVER_CURRENT 3 - #define HUB_PORT_RESET 4 - #define HUB_PORT_POWER 8 - #define HUB_PORT_LOW_SPEED 9 - #define HUB_C_PORT_CONNECTION 16 - #define HUB_C_PORT_ENABLE 17 - #define HUB_C_PORT_SUSPEND 18 - #define HUB_C_PORT_OVER_CURRENT 19 - #define HUB_C_PORT_RESET 20 +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 #endif /* USB descriptor type */ #ifndef USB_DESCR_TYP_DEVICE - #define USB_DESCR_TYP_DEVICE 0x01 - #define USB_DESCR_TYP_CONFIG 0x02 - #define USB_DESCR_TYP_STRING 0x03 - #define USB_DESCR_TYP_INTERF 0x04 - #define USB_DESCR_TYP_ENDP 0x05 - #define USB_DESCR_TYP_QUALIF 0x06 - #define USB_DESCR_TYP_SPEED 0x07 - #define USB_DESCR_TYP_OTG 0x09 - #define USB_DESCR_TYP_HID 0x21 - #define USB_DESCR_TYP_REPORT 0x22 - #define USB_DESCR_TYP_PHYSIC 0x23 - #define USB_DESCR_TYP_CS_INTF 0x24 - #define USB_DESCR_TYP_CS_ENDP 0x25 - #define USB_DESCR_TYP_HUB 0x29 +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 #endif /* USB device class */ #ifndef USB_DEV_CLASS_HUB - #define USB_DEV_CLASS_RESERVED 0x00 - #define USB_DEV_CLASS_AUDIO 0x01 - #define USB_DEV_CLASS_COMMUNIC 0x02 - #define USB_DEV_CLASS_HID 0x03 - #define USB_DEV_CLASS_MONITOR 0x04 - #define USB_DEV_CLASS_PHYSIC_IF 0x05 - #define USB_DEV_CLASS_IMAGE 0x06 - #define USB_DEV_CLASS_PRINTER 0x07 - #define USB_DEV_CLASS_STORAGE 0x08 - #define USB_DEV_CLASS_HUB 0x09 - #define USB_DEV_CLASS_VEN_SPEC 0xFF +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF #endif /* USB endpoint type and attributes */ #ifndef USB_ENDP_TYPE_MASK - #define USB_ENDP_DIR_MASK 0x80 - #define USB_ENDP_ADDR_MASK 0x0F - #define USB_ENDP_TYPE_MASK 0x03 - #define USB_ENDP_TYPE_CTRL 0x00 - #define USB_ENDP_TYPE_ISOCH 0x01 - #define USB_ENDP_TYPE_BULK 0x02 - #define USB_ENDP_TYPE_INTER 0x03 +#define USB_ENDP_DIR_MASK 0x80 +#define USB_ENDP_ADDR_MASK 0x0F +#define USB_ENDP_TYPE_MASK 0x03 +#define USB_ENDP_TYPE_CTRL 0x00 +#define USB_ENDP_TYPE_ISOCH 0x01 +#define USB_ENDP_TYPE_BULK 0x02 +#define USB_ENDP_TYPE_INTER 0x03 #endif #ifndef USB_DEVICE_ADDR - #define USB_DEVICE_ADDR 0x02 +#define USB_DEVICE_ADDR 0x02 #endif #ifndef DEFAULT_ENDP0_SIZE - #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ +#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ #endif #ifndef MAX_PACKET_SIZE - #define MAX_PACKET_SIZE 64 /* maximum packet size */ +#define MAX_PACKET_SIZE 64 /* maximum packet size */ #endif #ifndef USB_BO_CBW_SIZE - #define USB_BO_CBW_SIZE 0x1F - #define USB_BO_CSW_SIZE 0x0D +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D #endif #ifndef USB_BO_CBW_SIG0 - #define USB_BO_CBW_SIG0 0x55 - #define USB_BO_CBW_SIG1 0x53 - #define USB_BO_CBW_SIG2 0x42 - #define USB_BO_CBW_SIG3 0x43 - #define USB_BO_CSW_SIG0 0x55 - #define USB_BO_CSW_SIG1 0x53 - #define USB_BO_CSW_SIG2 0x42 - #define USB_BO_CSW_SIG3 0x53 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 #endif #define DEF_STRING_DESC_LANG 0x00 @@ -752,492 +759,490 @@ static inline uint8_t tu_desc_len(void const* desc) #define DEF_STRING_DESC_PROD 0x02 #define DEF_STRING_DESC_SERN 0x03 + //--------------------------------------------------------------------+ + // Common Definitions + //--------------------------------------------------------------------+ + /** \defgroup ClassDriver_HID_Common Common Definitions + * @{ */ -//--------------------------------------------------------------------+ -// Common Definitions -//--------------------------------------------------------------------+ -/** \defgroup ClassDriver_HID_Common Common Definitions - * @{ */ + /// USB HID Descriptor + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; /**< Numeric expression that is the total size of the HID descriptor */ + uint8_t bDescriptorType; /**< Constant name specifying type of HID descriptor. */ - /// USB HID Descriptor -typedef struct TU_ATTR_PACKED -{ - uint8_t bLength; /**< Numeric expression that is the total size of the HID descriptor */ - uint8_t bDescriptorType; /**< Constant name specifying type of HID descriptor. */ + uint16_t bcdHID; /**< Numeric expression identifying the HID Class Specification release */ + uint8_t bCountryCode; /**< Numeric expression identifying country code of the localized hardware. */ + uint8_t bNumDescriptors; /**< Numeric expression specifying the number of class descriptors */ - uint16_t bcdHID; /**< Numeric expression identifying the HID Class Specification release */ - uint8_t bCountryCode; /**< Numeric expression identifying country code of the localized hardware. */ - uint8_t bNumDescriptors; /**< Numeric expression specifying the number of class descriptors */ + uint8_t bReportType; /**< Type of HID class report. */ + uint16_t wReportLength; /**< the total size of the Report descriptor. */ + } tusb_hid_descriptor_hid_t; - uint8_t bReportType; /**< Type of HID class report. */ - uint16_t wReportLength; /**< the total size of the Report descriptor. */ -} tusb_hid_descriptor_hid_t; + /// HID Subclass + typedef enum + { + HID_SUBCLASS_NONE = 0, ///< No Subclass + HID_SUBCLASS_BOOT = 1 ///< Boot Interface Subclass + } hid_subclass_type_t; -/// HID Subclass -typedef enum -{ - HID_SUBCLASS_NONE = 0, ///< No Subclass - HID_SUBCLASS_BOOT = 1 ///< Boot Interface Subclass -}hid_subclass_type_t; + /// HID Protocol + typedef enum + { + HID_PROTOCOL_NONE = 0, ///< None + HID_PROTOCOL_KEYBOARD = 1, ///< Keyboard + HID_PROTOCOL_MOUSE = 2 ///< Mouse + } hid_protocol_type_t; -/// HID Protocol -typedef enum -{ - HID_PROTOCOL_NONE = 0, ///< None - HID_PROTOCOL_KEYBOARD = 1, ///< Keyboard - HID_PROTOCOL_MOUSE = 2 ///< Mouse -}hid_protocol_type_t; + /// HID Descriptor Type + typedef enum + { + HID_DESC_TYPE_HID = 0x21, ///< HID Descriptor + HID_DESC_TYPE_REPORT = 0x22, ///< Report Descriptor + HID_DESC_TYPE_PHYSICAL = 0x23 ///< Physical Descriptor + } hid_descriptor_type_t; -/// HID Descriptor Type -typedef enum -{ - HID_DESC_TYPE_HID = 0x21, ///< HID Descriptor - HID_DESC_TYPE_REPORT = 0x22, ///< Report Descriptor - HID_DESC_TYPE_PHYSICAL = 0x23 ///< Physical Descriptor -}hid_descriptor_type_t; + /// HID Request Report Type + typedef enum + { + HID_REPORT_TYPE_INVALID = 0, + HID_REPORT_TYPE_INPUT, ///< Input + HID_REPORT_TYPE_OUTPUT, ///< Output + HID_REPORT_TYPE_FEATURE ///< Feature + } hid_report_type_t; -/// HID Request Report Type -typedef enum -{ - HID_REPORT_TYPE_INVALID = 0, - HID_REPORT_TYPE_INPUT, ///< Input - HID_REPORT_TYPE_OUTPUT, ///< Output - HID_REPORT_TYPE_FEATURE ///< Feature -}hid_report_type_t; + /// HID Class Specific Control Request + typedef enum + { + HID_REQ_CONTROL_GET_REPORT = 0x01, ///< Get Report + HID_REQ_CONTROL_GET_IDLE = 0x02, ///< Get Idle + HID_REQ_CONTROL_GET_PROTOCOL = 0x03, ///< Get Protocol + HID_REQ_CONTROL_SET_REPORT = 0x09, ///< Set Report + HID_REQ_CONTROL_SET_IDLE = 0x0a, ///< Set Idle + HID_REQ_CONTROL_SET_PROTOCOL = 0x0b ///< Set Protocol + } hid_request_type_t; -/// HID Class Specific Control Request -typedef enum -{ - HID_REQ_CONTROL_GET_REPORT = 0x01, ///< Get Report - HID_REQ_CONTROL_GET_IDLE = 0x02, ///< Get Idle - HID_REQ_CONTROL_GET_PROTOCOL = 0x03, ///< Get Protocol - HID_REQ_CONTROL_SET_REPORT = 0x09, ///< Set Report - HID_REQ_CONTROL_SET_IDLE = 0x0a, ///< Set Idle - HID_REQ_CONTROL_SET_PROTOCOL = 0x0b ///< Set Protocol -}hid_request_type_t; + /// HID Country Code + typedef enum + { + HID_LOCAL_NotSupported = 0, ///< NotSupported + HID_LOCAL_Arabic, ///< Arabic + HID_LOCAL_Belgian, ///< Belgian + HID_LOCAL_Canadian_Bilingual, ///< Canadian_Bilingual + HID_LOCAL_Canadian_French, ///< Canadian_French + HID_LOCAL_Czech_Republic, ///< Czech_Republic + HID_LOCAL_Danish, ///< Danish + HID_LOCAL_Finnish, ///< Finnish + HID_LOCAL_French, ///< French + HID_LOCAL_German, ///< German + HID_LOCAL_Greek, ///< Greek + HID_LOCAL_Hebrew, ///< Hebrew + HID_LOCAL_Hungary, ///< Hungary + HID_LOCAL_International, ///< International + HID_LOCAL_Italian, ///< Italian + HID_LOCAL_Japan_Katakana, ///< Japan_Katakana + HID_LOCAL_Korean, ///< Korean + HID_LOCAL_Latin_American, ///< Latin_American + HID_LOCAL_Netherlands_Dutch, ///< Netherlands/Dutch + HID_LOCAL_Norwegian, ///< Norwegian + HID_LOCAL_Persian_Farsi, ///< Persian (Farsi) + HID_LOCAL_Poland, ///< Poland + HID_LOCAL_Portuguese, ///< Portuguese + HID_LOCAL_Russia, ///< Russia + HID_LOCAL_Slovakia, ///< Slovakia + HID_LOCAL_Spanish, ///< Spanish + HID_LOCAL_Swedish, ///< Swedish + HID_LOCAL_Swiss_French, ///< Swiss/French + HID_LOCAL_Swiss_German, ///< Swiss/German + HID_LOCAL_Switzerland, ///< Switzerland + HID_LOCAL_Taiwan, ///< Taiwan + HID_LOCAL_Turkish_Q, ///< Turkish-Q + HID_LOCAL_UK, ///< UK + HID_LOCAL_US, ///< US + HID_LOCAL_Yugoslavia, ///< Yugoslavia + HID_LOCAL_Turkish_F ///< Turkish-F + } hid_country_code_t; -/// HID Country Code -typedef enum -{ - HID_LOCAL_NotSupported = 0 , ///< NotSupported - HID_LOCAL_Arabic , ///< Arabic - HID_LOCAL_Belgian , ///< Belgian - HID_LOCAL_Canadian_Bilingual , ///< Canadian_Bilingual - HID_LOCAL_Canadian_French , ///< Canadian_French - HID_LOCAL_Czech_Republic , ///< Czech_Republic - HID_LOCAL_Danish , ///< Danish - HID_LOCAL_Finnish , ///< Finnish - HID_LOCAL_French , ///< French - HID_LOCAL_German , ///< German - HID_LOCAL_Greek , ///< Greek - HID_LOCAL_Hebrew , ///< Hebrew - HID_LOCAL_Hungary , ///< Hungary - HID_LOCAL_International , ///< International - HID_LOCAL_Italian , ///< Italian - HID_LOCAL_Japan_Katakana , ///< Japan_Katakana - HID_LOCAL_Korean , ///< Korean - HID_LOCAL_Latin_American , ///< Latin_American - HID_LOCAL_Netherlands_Dutch , ///< Netherlands/Dutch - HID_LOCAL_Norwegian , ///< Norwegian - HID_LOCAL_Persian_Farsi , ///< Persian (Farsi) - HID_LOCAL_Poland , ///< Poland - HID_LOCAL_Portuguese , ///< Portuguese - HID_LOCAL_Russia , ///< Russia - HID_LOCAL_Slovakia , ///< Slovakia - HID_LOCAL_Spanish , ///< Spanish - HID_LOCAL_Swedish , ///< Swedish - HID_LOCAL_Swiss_French , ///< Swiss/French - HID_LOCAL_Swiss_German , ///< Swiss/German - HID_LOCAL_Switzerland , ///< Switzerland - HID_LOCAL_Taiwan , ///< Taiwan - HID_LOCAL_Turkish_Q , ///< Turkish-Q - HID_LOCAL_UK , ///< UK - HID_LOCAL_US , ///< US - HID_LOCAL_Yugoslavia , ///< Yugoslavia - HID_LOCAL_Turkish_F ///< Turkish-F -} hid_country_code_t; + /** @} */ -/** @} */ + //--------------------------------------------------------------------+ + // GAMEPAD + //--------------------------------------------------------------------+ + /** \addtogroup ClassDriver_HID_Gamepad Gamepad + * @{ */ -//--------------------------------------------------------------------+ -// GAMEPAD -//--------------------------------------------------------------------+ -/** \addtogroup ClassDriver_HID_Gamepad Gamepad - * @{ */ + /* From https://www.kernel.org/doc/html/latest/input/gamepad.html + ____________________________ __ + / [__ZL__] [__ZR__] \ | + / [__ TL __] [__ TR __] \ | Front Triggers + __/________________________________\__ __| + / _ \ | + / /\ __ (N) \ | + / || __ |MO| __ _ _ \ | Main Pad + | <===DP===> |SE| |ST| (W) -|- (E) | | + \ || ___ ___ _ / | + /\ \/ / \ / \ (S) /\ __| + / \________ | LS | ____ | RS | ________/ \ | + | / \ \___/ / \ \___/ / \ | | Control Sticks + | / \_____/ \_____/ \ | __| + | / \ | + \_____/ \_____/ -/* From https://www.kernel.org/doc/html/latest/input/gamepad.html - ____________________________ __ - / [__ZL__] [__ZR__] \ | - / [__ TL __] [__ TR __] \ | Front Triggers - __/________________________________\__ __| - / _ \ | - / /\ __ (N) \ | - / || __ |MO| __ _ _ \ | Main Pad - | <===DP===> |SE| |ST| (W) -|- (E) | | - \ || ___ ___ _ / | - /\ \/ / \ / \ (S) /\ __| - / \________ | LS | ____ | RS | ________/ \ | -| / \ \___/ / \ \___/ / \ | | Control Sticks -| / \_____/ \_____/ \ | __| -| / \ | - \_____/ \_____/ + |________|______| |______|___________| + D-Pad Left Right Action Pad + Stick Stick - |________|______| |______|___________| - D-Pad Left Right Action Pad - Stick Stick + |_____________| + Menu Pad - |_____________| - Menu Pad + Most gamepads have the following features: + - Action-Pad 4 buttons in diamonds-shape (on the right side) NORTH, SOUTH, WEST and EAST. + - D-Pad (Direction-pad) 4 buttons (on the left side) that point up, down, left and right. + - Menu-Pad Different constellations, but most-times 2 buttons: SELECT - START. + - Analog-Sticks provide freely moveable sticks to control directions, Analog-sticks may also + provide a digital button if you press them. + - Triggers are located on the upper-side of the pad in vertical direction. The upper buttons + are normally named Left- and Right-Triggers, the lower buttons Z-Left and Z-Right. + - Rumble Many devices provide force-feedback features. But are mostly just simple rumble motors. + */ - Most gamepads have the following features: - - Action-Pad 4 buttons in diamonds-shape (on the right side) NORTH, SOUTH, WEST and EAST. - - D-Pad (Direction-pad) 4 buttons (on the left side) that point up, down, left and right. - - Menu-Pad Different constellations, but most-times 2 buttons: SELECT - START. - - Analog-Sticks provide freely moveable sticks to control directions, Analog-sticks may also - provide a digital button if you press them. - - Triggers are located on the upper-side of the pad in vertical direction. The upper buttons - are normally named Left- and Right-Triggers, the lower buttons Z-Left and Z-Right. - - Rumble Many devices provide force-feedback features. But are mostly just simple rumble motors. - */ + /// HID Gamepad Protocol Report. + typedef struct TU_ATTR_PACKED + { + int8_t x; ///< Delta x movement of left analog-stick + int8_t y; ///< Delta y movement of left analog-stick + int8_t z; ///< Delta z movement of right analog-joystick + int8_t rz; ///< Delta Rz movement of right analog-joystick + int8_t rx; ///< Delta Rx movement of analog left trigger + int8_t ry; ///< Delta Ry movement of analog right trigger + uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat + uint16_t buttons; ///< Buttons mask for currently pressed buttons + } hid_gamepad_report_t; -/// HID Gamepad Protocol Report. -typedef struct TU_ATTR_PACKED -{ - int8_t x; ///< Delta x movement of left analog-stick - int8_t y; ///< Delta y movement of left analog-stick - int8_t z; ///< Delta z movement of right analog-joystick - int8_t rz; ///< Delta Rz movement of right analog-joystick - int8_t rx; ///< Delta Rx movement of analog left trigger - int8_t ry; ///< Delta Ry movement of analog right trigger - uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat - uint16_t buttons; ///< Buttons mask for currently pressed buttons -}hid_gamepad_report_t; + /// HID Switch Gamepad Protocol Report. + typedef struct TU_ATTR_PACKED + { + uint16_t buttons; ///< Buttons mask for currently pressed buttons + uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat + int8_t x; ///< Delta x movement of left analog-stick + int8_t y; ///< Delta y movement of left analog-stick + int8_t rx; ///< Delta Rx movement of analog left trigger + int8_t ry; ///< Delta Ry movement of analog right trigger + int8_t z; ///< Delta z movement of right analog-joystick + int8_t rz; ///< Delta Rz movement of right analog-joystick + } hid_gamepad_ns_report_t; -/// HID Switch Gamepad Protocol Report. -typedef struct TU_ATTR_PACKED -{ - uint16_t buttons; ///< Buttons mask for currently pressed buttons - uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat - int8_t x; ///< Delta x movement of left analog-stick - int8_t y; ///< Delta y movement of left analog-stick - int8_t rx; ///< Delta Rx movement of analog left trigger - int8_t ry; ///< Delta Ry movement of analog right trigger - int8_t z; ///< Delta z movement of right analog-joystick - int8_t rz; ///< Delta Rz movement of right analog-joystick -}hid_gamepad_ns_report_t; + /// Standard Gamepad Buttons Bitmap (from Linux input event codes) + typedef enum + { + GAMEPAD_BUTTON_A = TU_BIT(0), ///< A/South button + GAMEPAD_BUTTON_B = TU_BIT(1), ///< B/East button + GAMEPAD_BUTTON_C = TU_BIT(2), ///< C button + GAMEPAD_BUTTON_X = TU_BIT(3), ///< X/North button + GAMEPAD_BUTTON_Y = TU_BIT(4), ///< Y/West button + GAMEPAD_BUTTON_Z = TU_BIT(5), ///< Z button + GAMEPAD_BUTTON_TL = TU_BIT(6), ///< L1 button + GAMEPAD_BUTTON_TR = TU_BIT(7), ///< R1 button + GAMEPAD_BUTTON_TL2 = TU_BIT(8), ///< L2 button + GAMEPAD_BUTTON_TR2 = TU_BIT(9), ///< R2 button + GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button + GAMEPAD_BUTTON_START = TU_BIT(11), ///< Start button + GAMEPAD_BUTTON_MODE = TU_BIT(12), ///< Mode button + GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button + GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button + // GAMEPAD_BUTTON_ = TU_BIT(15), ///< Undefined button + } hid_gamepad_button_bm_t; -/// Standard Gamepad Buttons Bitmap (from Linux input event codes) -typedef enum -{ - GAMEPAD_BUTTON_A = TU_BIT(0), ///< A/South button - GAMEPAD_BUTTON_B = TU_BIT(1), ///< B/East button - GAMEPAD_BUTTON_C = TU_BIT(2), ///< C button - GAMEPAD_BUTTON_X = TU_BIT(3), ///< X/North button - GAMEPAD_BUTTON_Y = TU_BIT(4), ///< Y/West button - GAMEPAD_BUTTON_Z = TU_BIT(5), ///< Z button - GAMEPAD_BUTTON_TL = TU_BIT(6), ///< L1 button - GAMEPAD_BUTTON_TR = TU_BIT(7), ///< R1 button - GAMEPAD_BUTTON_TL2 = TU_BIT(8), ///< L2 button - GAMEPAD_BUTTON_TR2 = TU_BIT(9), ///< R2 button - GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button - GAMEPAD_BUTTON_START = TU_BIT(11), ///< Start button - GAMEPAD_BUTTON_MODE = TU_BIT(12), ///< Mode button - GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button - GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button -//GAMEPAD_BUTTON_ = TU_BIT(15), ///< Undefined button -}hid_gamepad_button_bm_t; + /// Switch Gamepad Buttons Bitmap + typedef enum + { + GAMEPAD_NS_BUTTON_Y = 0x01, + GAMEPAD_NS_BUTTON_B = 0x02, + GAMEPAD_NS_BUTTON_A = 0x04, + GAMEPAD_NS_BUTTON_X = 0x08, + GAMEPAD_NS_BUTTON_TL = 0x10, + GAMEPAD_NS_BUTTON_TR = 0x20, + GAMEPAD_NS_BUTTON_TL2 = 0x40, + GAMEPAD_NS_BUTTON_TR2 = 0x80, + GAMEPAD_NS_BUTTON_MINUS = 0x100, + GAMEPAD_NS_BUTTON_PLUS = 0x200, + GAMEPAD_NS_BUTTON_THUMBL = 0x400, + GAMEPAD_NS_BUTTON_THUMBR = 0x800, + GAMEPAD_NS_BUTTON_HOME = 0x1000, + GAMEPAD_NS_BUTTON_CAPTURE = 0x2000, + GAMEPAD_NS_BUTTON_Z = 0x4000, /// UNUSED? + } hid_gamepad_ns_button_bm_t; -/// Switch Gamepad Buttons Bitmap -typedef enum -{ - GAMEPAD_NS_BUTTON_Y = 0x01, - GAMEPAD_NS_BUTTON_B = 0x02, - GAMEPAD_NS_BUTTON_A = 0x04, - GAMEPAD_NS_BUTTON_X = 0x08, - GAMEPAD_NS_BUTTON_TL = 0x10, - GAMEPAD_NS_BUTTON_TR = 0x20, - GAMEPAD_NS_BUTTON_TL2 = 0x40, - GAMEPAD_NS_BUTTON_TR2 = 0x80, - GAMEPAD_NS_BUTTON_MINUS = 0x100, - GAMEPAD_NS_BUTTON_PLUS = 0x200, - GAMEPAD_NS_BUTTON_THUMBL = 0x400, - GAMEPAD_NS_BUTTON_THUMBR = 0x800, - GAMEPAD_NS_BUTTON_HOME = 0x1000, - GAMEPAD_NS_BUTTON_CAPTURE = 0x2000, - GAMEPAD_NS_BUTTON_Z = 0x4000, ///UNUSED? -}hid_gamepad_ns_button_bm_t; + /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes) + typedef enum + { + GAMEPAD_HAT_CENTERED = 0, ///< DPAD_CENTERED + GAMEPAD_HAT_UP = 1, ///< DPAD_UP + GAMEPAD_HAT_UP_RIGHT = 2, ///< DPAD_UP_RIGHT + GAMEPAD_HAT_RIGHT = 3, ///< DPAD_RIGHT + GAMEPAD_HAT_DOWN_RIGHT = 4, ///< DPAD_DOWN_RIGHT + GAMEPAD_HAT_DOWN = 5, ///< DPAD_DOWN + GAMEPAD_HAT_DOWN_LEFT = 6, ///< DPAD_DOWN_LEFT + GAMEPAD_HAT_LEFT = 7, ///< DPAD_LEFT + GAMEPAD_HAT_UP_LEFT = 8, ///< DPAD_UP_LEFT + } hid_gamepad_hat_t; -/// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes) -typedef enum -{ - GAMEPAD_HAT_CENTERED = 0, ///< DPAD_CENTERED - GAMEPAD_HAT_UP = 1, ///< DPAD_UP - GAMEPAD_HAT_UP_RIGHT = 2, ///< DPAD_UP_RIGHT - GAMEPAD_HAT_RIGHT = 3, ///< DPAD_RIGHT - GAMEPAD_HAT_DOWN_RIGHT = 4, ///< DPAD_DOWN_RIGHT - GAMEPAD_HAT_DOWN = 5, ///< DPAD_DOWN - GAMEPAD_HAT_DOWN_LEFT = 6, ///< DPAD_DOWN_LEFT - GAMEPAD_HAT_LEFT = 7, ///< DPAD_LEFT - GAMEPAD_HAT_UP_LEFT = 8, ///< DPAD_UP_LEFT -}hid_gamepad_hat_t; + /// Switch Gamepad HAT/DPAD Buttons (from Linux input event codes) + typedef enum + { + GAMEPAD_NS_HAT_CENTERED = 8, ///< DPAD_CENTERED + GAMEPAD_NS_HAT_UP = 0, ///< DPAD_UP + GAMEPAD_NS_HAT_UP_RIGHT = 1, ///< DPAD_UP_RIGHT + GAMEPAD_NS_HAT_RIGHT = 2, ///< DPAD_RIGHT + GAMEPAD_NS_HAT_DOWN_RIGHT = 3, ///< DPAD_DOWN_RIGHT + GAMEPAD_NS_HAT_DOWN = 4, ///< DPAD_DOWN + GAMEPAD_NS_HAT_DOWN_LEFT = 5, ///< DPAD_DOWN_LEFT + GAMEPAD_NS_HAT_LEFT = 6, ///< DPAD_LEFT + GAMEPAD_NS_HAT_UP_LEFT = 7, ///< DPAD_UP_LEFT + } hid_gamepad_ns_hat_t; -/// Switch Gamepad HAT/DPAD Buttons (from Linux input event codes) -typedef enum -{ - GAMEPAD_NS_HAT_CENTERED = 8, ///< DPAD_CENTERED - GAMEPAD_NS_HAT_UP = 0, ///< DPAD_UP - GAMEPAD_NS_HAT_UP_RIGHT = 1, ///< DPAD_UP_RIGHT - GAMEPAD_NS_HAT_RIGHT = 2, ///< DPAD_RIGHT - GAMEPAD_NS_HAT_DOWN_RIGHT = 3, ///< DPAD_DOWN_RIGHT - GAMEPAD_NS_HAT_DOWN = 4, ///< DPAD_DOWN - GAMEPAD_NS_HAT_DOWN_LEFT = 5, ///< DPAD_DOWN_LEFT - GAMEPAD_NS_HAT_LEFT = 6, ///< DPAD_LEFT - GAMEPAD_NS_HAT_UP_LEFT = 7, ///< DPAD_UP_LEFT -}hid_gamepad_ns_hat_t; + /// @} -/// @} + //--------------------------------------------------------------------+ + // MOUSE + //--------------------------------------------------------------------+ + /** \addtogroup ClassDriver_HID_Mouse Mouse + * @{ */ -//--------------------------------------------------------------------+ -// MOUSE -//--------------------------------------------------------------------+ -/** \addtogroup ClassDriver_HID_Mouse Mouse - * @{ */ + /// Standard HID Boot Protocol Mouse Report. + typedef struct TU_ATTR_PACKED + { + uint8_t buttons; /**< buttons mask for currently pressed buttons in the mouse. */ + int8_t x; /**< Current delta x movement of the mouse. */ + int8_t y; /**< Current delta y movement on the mouse. */ + int8_t wheel; /**< Current delta wheel movement on the mouse. */ + int8_t pan; // using AC Pan + } hid_mouse_report_t; -/// Standard HID Boot Protocol Mouse Report. -typedef struct TU_ATTR_PACKED -{ - uint8_t buttons; /**< buttons mask for currently pressed buttons in the mouse. */ - int8_t x; /**< Current delta x movement of the mouse. */ - int8_t y; /**< Current delta y movement on the mouse. */ - int8_t wheel; /**< Current delta wheel movement on the mouse. */ - int8_t pan; // using AC Pan -} hid_mouse_report_t; + /// Standard Mouse Buttons Bitmap + typedef enum + { + MOUSE_BUTTON_LEFT = TU_BIT(0), ///< Left button + MOUSE_BUTTON_RIGHT = TU_BIT(1), ///< Right button + MOUSE_BUTTON_MIDDLE = TU_BIT(2), ///< Middle button + MOUSE_BUTTON_BACKWARD = TU_BIT(3), ///< Backward button, + MOUSE_BUTTON_FORWARD = TU_BIT(4), ///< Forward button, + } hid_mouse_button_bm_t; -/// Standard Mouse Buttons Bitmap -typedef enum -{ - MOUSE_BUTTON_LEFT = TU_BIT(0), ///< Left button - MOUSE_BUTTON_RIGHT = TU_BIT(1), ///< Right button - MOUSE_BUTTON_MIDDLE = TU_BIT(2), ///< Middle button - MOUSE_BUTTON_BACKWARD = TU_BIT(3), ///< Backward button, - MOUSE_BUTTON_FORWARD = TU_BIT(4), ///< Forward button, -}hid_mouse_button_bm_t; + /// @} -/// @} + //--------------------------------------------------------------------+ + // Keyboard + //--------------------------------------------------------------------+ + /** \addtogroup ClassDriver_HID_Keyboard Keyboard + * @{ */ -//--------------------------------------------------------------------+ -// Keyboard -//--------------------------------------------------------------------+ -/** \addtogroup ClassDriver_HID_Keyboard Keyboard - * @{ */ + /// Standard HID Boot Protocol Keyboard Report. + typedef struct TU_ATTR_PACKED + { + uint8_t modifier; /**< Keyboard modifier (KEYBOARD_MODIFIER_* masks). */ + uint8_t reserved; /**< Reserved for OEM use, always set to 0. */ + uint8_t keycode[6]; /**< Key codes of the currently pressed keys. */ + } hid_keyboard_report_t; -/// Standard HID Boot Protocol Keyboard Report. -typedef struct TU_ATTR_PACKED -{ - uint8_t modifier; /**< Keyboard modifier (KEYBOARD_MODIFIER_* masks). */ - uint8_t reserved; /**< Reserved for OEM use, always set to 0. */ - uint8_t keycode[6]; /**< Key codes of the currently pressed keys. */ -} hid_keyboard_report_t; + /// Keyboard modifier codes bitmap + typedef enum + { + KEYBOARD_MODIFIER_LEFTCTRL = TU_BIT(0), ///< Left Control + KEYBOARD_MODIFIER_LEFTSHIFT = TU_BIT(1), ///< Left Shift + KEYBOARD_MODIFIER_LEFTALT = TU_BIT(2), ///< Left Alt + KEYBOARD_MODIFIER_LEFTGUI = TU_BIT(3), ///< Left Window + KEYBOARD_MODIFIER_RIGHTCTRL = TU_BIT(4), ///< Right Control + KEYBOARD_MODIFIER_RIGHTSHIFT = TU_BIT(5), ///< Right Shift + KEYBOARD_MODIFIER_RIGHTALT = TU_BIT(6), ///< Right Alt + KEYBOARD_MODIFIER_RIGHTGUI = TU_BIT(7) ///< Right Window + } hid_keyboard_modifier_bm_t; -/// Keyboard modifier codes bitmap -typedef enum -{ - KEYBOARD_MODIFIER_LEFTCTRL = TU_BIT(0), ///< Left Control - KEYBOARD_MODIFIER_LEFTSHIFT = TU_BIT(1), ///< Left Shift - KEYBOARD_MODIFIER_LEFTALT = TU_BIT(2), ///< Left Alt - KEYBOARD_MODIFIER_LEFTGUI = TU_BIT(3), ///< Left Window - KEYBOARD_MODIFIER_RIGHTCTRL = TU_BIT(4), ///< Right Control - KEYBOARD_MODIFIER_RIGHTSHIFT = TU_BIT(5), ///< Right Shift - KEYBOARD_MODIFIER_RIGHTALT = TU_BIT(6), ///< Right Alt - KEYBOARD_MODIFIER_RIGHTGUI = TU_BIT(7) ///< Right Window -}hid_keyboard_modifier_bm_t; - -typedef enum -{ - KEYBOARD_LED_NUMLOCK = TU_BIT(0), ///< Num Lock LED - KEYBOARD_LED_CAPSLOCK = TU_BIT(1), ///< Caps Lock LED - KEYBOARD_LED_SCROLLLOCK = TU_BIT(2), ///< Scroll Lock LED - KEYBOARD_LED_COMPOSE = TU_BIT(3), ///< Composition Mode - KEYBOARD_LED_KANA = TU_BIT(4) ///< Kana mode -}hid_keyboard_led_bm_t; + typedef enum + { + KEYBOARD_LED_NUMLOCK = TU_BIT(0), ///< Num Lock LED + KEYBOARD_LED_CAPSLOCK = TU_BIT(1), ///< Caps Lock LED + KEYBOARD_LED_SCROLLLOCK = TU_BIT(2), ///< Scroll Lock LED + KEYBOARD_LED_COMPOSE = TU_BIT(3), ///< Composition Mode + KEYBOARD_LED_KANA = TU_BIT(4) ///< Kana mode + } hid_keyboard_led_bm_t; /// @} //--------------------------------------------------------------------+ // HID KEYCODE //--------------------------------------------------------------------+ -#define HID_KEY_NONE 0x00 -#define HID_KEY_A 0x04 -#define HID_KEY_B 0x05 -#define HID_KEY_C 0x06 -#define HID_KEY_D 0x07 -#define HID_KEY_E 0x08 -#define HID_KEY_F 0x09 -#define HID_KEY_G 0x0A -#define HID_KEY_H 0x0B -#define HID_KEY_I 0x0C -#define HID_KEY_J 0x0D -#define HID_KEY_K 0x0E -#define HID_KEY_L 0x0F -#define HID_KEY_M 0x10 -#define HID_KEY_N 0x11 -#define HID_KEY_O 0x12 -#define HID_KEY_P 0x13 -#define HID_KEY_Q 0x14 -#define HID_KEY_R 0x15 -#define HID_KEY_S 0x16 -#define HID_KEY_T 0x17 -#define HID_KEY_U 0x18 -#define HID_KEY_V 0x19 -#define HID_KEY_W 0x1A -#define HID_KEY_X 0x1B -#define HID_KEY_Y 0x1C -#define HID_KEY_Z 0x1D -#define HID_KEY_1 0x1E -#define HID_KEY_2 0x1F -#define HID_KEY_3 0x20 -#define HID_KEY_4 0x21 -#define HID_KEY_5 0x22 -#define HID_KEY_6 0x23 -#define HID_KEY_7 0x24 -#define HID_KEY_8 0x25 -#define HID_KEY_9 0x26 -#define HID_KEY_0 0x27 -#define HID_KEY_ENTER 0x28 -#define HID_KEY_ESCAPE 0x29 -#define HID_KEY_BACKSPACE 0x2A -#define HID_KEY_TAB 0x2B -#define HID_KEY_SPACE 0x2C -#define HID_KEY_MINUS 0x2D -#define HID_KEY_EQUAL 0x2E -#define HID_KEY_BRACKET_LEFT 0x2F -#define HID_KEY_BRACKET_RIGHT 0x30 -#define HID_KEY_BACKSLASH 0x31 -#define HID_KEY_EUROPE_1 0x32 -#define HID_KEY_SEMICOLON 0x33 -#define HID_KEY_APOSTROPHE 0x34 -#define HID_KEY_GRAVE 0x35 -#define HID_KEY_COMMA 0x36 -#define HID_KEY_PERIOD 0x37 -#define HID_KEY_SLASH 0x38 -#define HID_KEY_CAPS_LOCK 0x39 -#define HID_KEY_F1 0x3A -#define HID_KEY_F2 0x3B -#define HID_KEY_F3 0x3C -#define HID_KEY_F4 0x3D -#define HID_KEY_F5 0x3E -#define HID_KEY_F6 0x3F -#define HID_KEY_F7 0x40 -#define HID_KEY_F8 0x41 -#define HID_KEY_F9 0x42 -#define HID_KEY_F10 0x43 -#define HID_KEY_F11 0x44 -#define HID_KEY_F12 0x45 -#define HID_KEY_PRINT_SCREEN 0x46 -#define HID_KEY_SCROLL_LOCK 0x47 -#define HID_KEY_PAUSE 0x48 -#define HID_KEY_INSERT 0x49 -#define HID_KEY_HOME 0x4A -#define HID_KEY_PAGE_UP 0x4B -#define HID_KEY_DELETE 0x4C -#define HID_KEY_END 0x4D -#define HID_KEY_PAGE_DOWN 0x4E -#define HID_KEY_ARROW_RIGHT 0x4F -#define HID_KEY_ARROW_LEFT 0x50 -#define HID_KEY_ARROW_DOWN 0x51 -#define HID_KEY_ARROW_UP 0x52 -#define HID_KEY_NUM_LOCK 0x53 -#define HID_KEY_KEYPAD_DIVIDE 0x54 -#define HID_KEY_KEYPAD_MULTIPLY 0x55 -#define HID_KEY_KEYPAD_SUBTRACT 0x56 -#define HID_KEY_KEYPAD_ADD 0x57 -#define HID_KEY_KEYPAD_ENTER 0x58 -#define HID_KEY_KEYPAD_1 0x59 -#define HID_KEY_KEYPAD_2 0x5A -#define HID_KEY_KEYPAD_3 0x5B -#define HID_KEY_KEYPAD_4 0x5C -#define HID_KEY_KEYPAD_5 0x5D -#define HID_KEY_KEYPAD_6 0x5E -#define HID_KEY_KEYPAD_7 0x5F -#define HID_KEY_KEYPAD_8 0x60 -#define HID_KEY_KEYPAD_9 0x61 -#define HID_KEY_KEYPAD_0 0x62 -#define HID_KEY_KEYPAD_DECIMAL 0x63 -#define HID_KEY_EUROPE_2 0x64 -#define HID_KEY_APPLICATION 0x65 -#define HID_KEY_POWER 0x66 -#define HID_KEY_KEYPAD_EQUAL 0x67 -#define HID_KEY_F13 0x68 -#define HID_KEY_F14 0x69 -#define HID_KEY_F15 0x6A -#define HID_KEY_F16 0x6B -#define HID_KEY_F17 0x6C -#define HID_KEY_F18 0x6D -#define HID_KEY_F19 0x6E -#define HID_KEY_F20 0x6F -#define HID_KEY_F21 0x70 -#define HID_KEY_F22 0x71 -#define HID_KEY_F23 0x72 -#define HID_KEY_F24 0x73 -#define HID_KEY_EXECUTE 0x74 -#define HID_KEY_HELP 0x75 -#define HID_KEY_MENU 0x76 -#define HID_KEY_SELECT 0x77 -#define HID_KEY_STOP 0x78 -#define HID_KEY_AGAIN 0x79 -#define HID_KEY_UNDO 0x7A -#define HID_KEY_CUT 0x7B -#define HID_KEY_COPY 0x7C -#define HID_KEY_PASTE 0x7D -#define HID_KEY_FIND 0x7E -#define HID_KEY_MUTE 0x7F -#define HID_KEY_VOLUME_UP 0x80 -#define HID_KEY_VOLUME_DOWN 0x81 -#define HID_KEY_LOCKING_CAPS_LOCK 0x82 -#define HID_KEY_LOCKING_NUM_LOCK 0x83 -#define HID_KEY_LOCKING_SCROLL_LOCK 0x84 -#define HID_KEY_KEYPAD_COMMA 0x85 -#define HID_KEY_KEYPAD_EQUAL_SIGN 0x86 -#define HID_KEY_KANJI1 0x87 -#define HID_KEY_KANJI2 0x88 -#define HID_KEY_KANJI3 0x89 -#define HID_KEY_KANJI4 0x8A -#define HID_KEY_KANJI5 0x8B -#define HID_KEY_KANJI6 0x8C -#define HID_KEY_KANJI7 0x8D -#define HID_KEY_KANJI8 0x8E -#define HID_KEY_KANJI9 0x8F -#define HID_KEY_LANG1 0x90 -#define HID_KEY_LANG2 0x91 -#define HID_KEY_LANG3 0x92 -#define HID_KEY_LANG4 0x93 -#define HID_KEY_LANG5 0x94 -#define HID_KEY_LANG6 0x95 -#define HID_KEY_LANG7 0x96 -#define HID_KEY_LANG8 0x97 -#define HID_KEY_LANG9 0x98 -#define HID_KEY_ALTERNATE_ERASE 0x99 -#define HID_KEY_SYSREQ_ATTENTION 0x9A -#define HID_KEY_CANCEL 0x9B -#define HID_KEY_CLEAR 0x9C -#define HID_KEY_PRIOR 0x9D -#define HID_KEY_RETURN 0x9E -#define HID_KEY_SEPARATOR 0x9F -#define HID_KEY_OUT 0xA0 -#define HID_KEY_OPER 0xA1 -#define HID_KEY_CLEAR_AGAIN 0xA2 -#define HID_KEY_CRSEL_PROPS 0xA3 -#define HID_KEY_EXSEL 0xA4 +#define HID_KEY_NONE 0x00 +#define HID_KEY_A 0x04 +#define HID_KEY_B 0x05 +#define HID_KEY_C 0x06 +#define HID_KEY_D 0x07 +#define HID_KEY_E 0x08 +#define HID_KEY_F 0x09 +#define HID_KEY_G 0x0A +#define HID_KEY_H 0x0B +#define HID_KEY_I 0x0C +#define HID_KEY_J 0x0D +#define HID_KEY_K 0x0E +#define HID_KEY_L 0x0F +#define HID_KEY_M 0x10 +#define HID_KEY_N 0x11 +#define HID_KEY_O 0x12 +#define HID_KEY_P 0x13 +#define HID_KEY_Q 0x14 +#define HID_KEY_R 0x15 +#define HID_KEY_S 0x16 +#define HID_KEY_T 0x17 +#define HID_KEY_U 0x18 +#define HID_KEY_V 0x19 +#define HID_KEY_W 0x1A +#define HID_KEY_X 0x1B +#define HID_KEY_Y 0x1C +#define HID_KEY_Z 0x1D +#define HID_KEY_1 0x1E +#define HID_KEY_2 0x1F +#define HID_KEY_3 0x20 +#define HID_KEY_4 0x21 +#define HID_KEY_5 0x22 +#define HID_KEY_6 0x23 +#define HID_KEY_7 0x24 +#define HID_KEY_8 0x25 +#define HID_KEY_9 0x26 +#define HID_KEY_0 0x27 +#define HID_KEY_ENTER 0x28 +#define HID_KEY_ESCAPE 0x29 +#define HID_KEY_BACKSPACE 0x2A +#define HID_KEY_TAB 0x2B +#define HID_KEY_SPACE 0x2C +#define HID_KEY_MINUS 0x2D +#define HID_KEY_EQUAL 0x2E +#define HID_KEY_BRACKET_LEFT 0x2F +#define HID_KEY_BRACKET_RIGHT 0x30 +#define HID_KEY_BACKSLASH 0x31 +#define HID_KEY_EUROPE_1 0x32 +#define HID_KEY_SEMICOLON 0x33 +#define HID_KEY_APOSTROPHE 0x34 +#define HID_KEY_GRAVE 0x35 +#define HID_KEY_COMMA 0x36 +#define HID_KEY_PERIOD 0x37 +#define HID_KEY_SLASH 0x38 +#define HID_KEY_CAPS_LOCK 0x39 +#define HID_KEY_F1 0x3A +#define HID_KEY_F2 0x3B +#define HID_KEY_F3 0x3C +#define HID_KEY_F4 0x3D +#define HID_KEY_F5 0x3E +#define HID_KEY_F6 0x3F +#define HID_KEY_F7 0x40 +#define HID_KEY_F8 0x41 +#define HID_KEY_F9 0x42 +#define HID_KEY_F10 0x43 +#define HID_KEY_F11 0x44 +#define HID_KEY_F12 0x45 +#define HID_KEY_PRINT_SCREEN 0x46 +#define HID_KEY_SCROLL_LOCK 0x47 +#define HID_KEY_PAUSE 0x48 +#define HID_KEY_INSERT 0x49 +#define HID_KEY_HOME 0x4A +#define HID_KEY_PAGE_UP 0x4B +#define HID_KEY_DELETE 0x4C +#define HID_KEY_END 0x4D +#define HID_KEY_PAGE_DOWN 0x4E +#define HID_KEY_ARROW_RIGHT 0x4F +#define HID_KEY_ARROW_LEFT 0x50 +#define HID_KEY_ARROW_DOWN 0x51 +#define HID_KEY_ARROW_UP 0x52 +#define HID_KEY_NUM_LOCK 0x53 +#define HID_KEY_KEYPAD_DIVIDE 0x54 +#define HID_KEY_KEYPAD_MULTIPLY 0x55 +#define HID_KEY_KEYPAD_SUBTRACT 0x56 +#define HID_KEY_KEYPAD_ADD 0x57 +#define HID_KEY_KEYPAD_ENTER 0x58 +#define HID_KEY_KEYPAD_1 0x59 +#define HID_KEY_KEYPAD_2 0x5A +#define HID_KEY_KEYPAD_3 0x5B +#define HID_KEY_KEYPAD_4 0x5C +#define HID_KEY_KEYPAD_5 0x5D +#define HID_KEY_KEYPAD_6 0x5E +#define HID_KEY_KEYPAD_7 0x5F +#define HID_KEY_KEYPAD_8 0x60 +#define HID_KEY_KEYPAD_9 0x61 +#define HID_KEY_KEYPAD_0 0x62 +#define HID_KEY_KEYPAD_DECIMAL 0x63 +#define HID_KEY_EUROPE_2 0x64 +#define HID_KEY_APPLICATION 0x65 +#define HID_KEY_POWER 0x66 +#define HID_KEY_KEYPAD_EQUAL 0x67 +#define HID_KEY_F13 0x68 +#define HID_KEY_F14 0x69 +#define HID_KEY_F15 0x6A +#define HID_KEY_F16 0x6B +#define HID_KEY_F17 0x6C +#define HID_KEY_F18 0x6D +#define HID_KEY_F19 0x6E +#define HID_KEY_F20 0x6F +#define HID_KEY_F21 0x70 +#define HID_KEY_F22 0x71 +#define HID_KEY_F23 0x72 +#define HID_KEY_F24 0x73 +#define HID_KEY_EXECUTE 0x74 +#define HID_KEY_HELP 0x75 +#define HID_KEY_MENU 0x76 +#define HID_KEY_SELECT 0x77 +#define HID_KEY_STOP 0x78 +#define HID_KEY_AGAIN 0x79 +#define HID_KEY_UNDO 0x7A +#define HID_KEY_CUT 0x7B +#define HID_KEY_COPY 0x7C +#define HID_KEY_PASTE 0x7D +#define HID_KEY_FIND 0x7E +#define HID_KEY_MUTE 0x7F +#define HID_KEY_VOLUME_UP 0x80 +#define HID_KEY_VOLUME_DOWN 0x81 +#define HID_KEY_LOCKING_CAPS_LOCK 0x82 +#define HID_KEY_LOCKING_NUM_LOCK 0x83 +#define HID_KEY_LOCKING_SCROLL_LOCK 0x84 +#define HID_KEY_KEYPAD_COMMA 0x85 +#define HID_KEY_KEYPAD_EQUAL_SIGN 0x86 +#define HID_KEY_KANJI1 0x87 +#define HID_KEY_KANJI2 0x88 +#define HID_KEY_KANJI3 0x89 +#define HID_KEY_KANJI4 0x8A +#define HID_KEY_KANJI5 0x8B +#define HID_KEY_KANJI6 0x8C +#define HID_KEY_KANJI7 0x8D +#define HID_KEY_KANJI8 0x8E +#define HID_KEY_KANJI9 0x8F +#define HID_KEY_LANG1 0x90 +#define HID_KEY_LANG2 0x91 +#define HID_KEY_LANG3 0x92 +#define HID_KEY_LANG4 0x93 +#define HID_KEY_LANG5 0x94 +#define HID_KEY_LANG6 0x95 +#define HID_KEY_LANG7 0x96 +#define HID_KEY_LANG8 0x97 +#define HID_KEY_LANG9 0x98 +#define HID_KEY_ALTERNATE_ERASE 0x99 +#define HID_KEY_SYSREQ_ATTENTION 0x9A +#define HID_KEY_CANCEL 0x9B +#define HID_KEY_CLEAR 0x9C +#define HID_KEY_PRIOR 0x9D +#define HID_KEY_RETURN 0x9E +#define HID_KEY_SEPARATOR 0x9F +#define HID_KEY_OUT 0xA0 +#define HID_KEY_OPER 0xA1 +#define HID_KEY_CLEAR_AGAIN 0xA2 +#define HID_KEY_CRSEL_PROPS 0xA3 +#define HID_KEY_EXSEL 0xA4 // RESERVED 0xA5-DF -#define HID_KEY_CONTROL_LEFT 0xE0 -#define HID_KEY_SHIFT_LEFT 0xE1 -#define HID_KEY_ALT_LEFT 0xE2 -#define HID_KEY_GUI_LEFT 0xE3 -#define HID_KEY_CONTROL_RIGHT 0xE4 -#define HID_KEY_SHIFT_RIGHT 0xE5 -#define HID_KEY_ALT_RIGHT 0xE6 -#define HID_KEY_GUI_RIGHT 0xE7 - +#define HID_KEY_CONTROL_LEFT 0xE0 +#define HID_KEY_SHIFT_LEFT 0xE1 +#define HID_KEY_ALT_LEFT 0xE2 +#define HID_KEY_GUI_LEFT 0xE3 +#define HID_KEY_CONTROL_RIGHT 0xE4 +#define HID_KEY_SHIFT_RIGHT 0xE5 +#define HID_KEY_ALT_RIGHT 0xE6 +#define HID_KEY_GUI_RIGHT 0xE7 //--------------------------------------------------------------------+ // REPORT DESCRIPTOR @@ -1249,267 +1254,269 @@ typedef enum #define HID_REPORT_DATA_3(data) , U32_TO_U8S_LE(data) #define HID_REPORT_ITEM(data, tag, type, size) \ - (((tag) << 4) | ((type) << 2) | (size)) HID_REPORT_DATA_##size(data) + (((tag) << 4) | ((type) << 2) | (size)) HID_REPORT_DATA_##size(data) -#define RI_TYPE_MAIN 0 +#define RI_TYPE_MAIN 0 #define RI_TYPE_GLOBAL 1 -#define RI_TYPE_LOCAL 2 +#define RI_TYPE_LOCAL 2 //------------- MAIN ITEMS 6.2.2.4 -------------// -#define HID_INPUT(x) HID_REPORT_ITEM(x, 8, RI_TYPE_MAIN, 1) -#define HID_OUTPUT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_MAIN, 1) -#define HID_COLLECTION(x) HID_REPORT_ITEM(x, 10, RI_TYPE_MAIN, 1) -#define HID_FEATURE(x) HID_REPORT_ITEM(x, 11, RI_TYPE_MAIN, 1) -#define HID_COLLECTION_END HID_REPORT_ITEM(x, 12, RI_TYPE_MAIN, 0) +#define HID_INPUT(x) HID_REPORT_ITEM(x, 8, RI_TYPE_MAIN, 1) +#define HID_OUTPUT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_MAIN, 1) +#define HID_COLLECTION(x) HID_REPORT_ITEM(x, 10, RI_TYPE_MAIN, 1) +#define HID_FEATURE(x) HID_REPORT_ITEM(x, 11, RI_TYPE_MAIN, 1) +#define HID_COLLECTION_END HID_REPORT_ITEM(x, 12, RI_TYPE_MAIN, 0) //------------- INPUT, OUTPUT, FEATURE 6.2.2.5 -------------// -#define HID_DATA (0<<0) -#define HID_CONSTANT (1<<0) +#define HID_DATA (0 << 0) +#define HID_CONSTANT (1 << 0) -#define HID_ARRAY (0<<1) -#define HID_VARIABLE (1<<1) +#define HID_ARRAY (0 << 1) +#define HID_VARIABLE (1 << 1) -#define HID_ABSOLUTE (0<<2) -#define HID_RELATIVE (1<<2) +#define HID_ABSOLUTE (0 << 2) +#define HID_RELATIVE (1 << 2) -#define HID_WRAP_NO (0<<3) -#define HID_WRAP (1<<3) +#define HID_WRAP_NO (0 << 3) +#define HID_WRAP (1 << 3) -#define HID_LINEAR (0<<4) -#define HID_NONLINEAR (1<<4) +#define HID_LINEAR (0 << 4) +#define HID_NONLINEAR (1 << 4) -#define HID_PREFERRED_STATE (0<<5) -#define HID_PREFERRED_NO (1<<5) +#define HID_PREFERRED_STATE (0 << 5) +#define HID_PREFERRED_NO (1 << 5) -#define HID_NO_NULL_POSITION (0<<6) -#define HID_NULL_STATE (1<<6) +#define HID_NO_NULL_POSITION (0 << 6) +#define HID_NULL_STATE (1 << 6) -#define HID_NON_VOLATILE (0<<7) -#define HID_VOLATILE (1<<7) +#define HID_NON_VOLATILE (0 << 7) +#define HID_VOLATILE (1 << 7) -#define HID_BITFIELD (0<<8) -#define HID_BUFFERED_BYTES (1<<8) +#define HID_BITFIELD (0 << 8) +#define HID_BUFFERED_BYTES (1 << 8) -//------------- COLLECTION ITEM 6.2.2.6 -------------// -enum { - HID_COLLECTION_PHYSICAL = 0, - HID_COLLECTION_APPLICATION, - HID_COLLECTION_LOGICAL, - HID_COLLECTION_REPORT, - HID_COLLECTION_NAMED_ARRAY, - HID_COLLECTION_USAGE_SWITCH, - HID_COLLECTION_USAGE_MODIFIER -}; + //------------- COLLECTION ITEM 6.2.2.6 -------------// + enum + { + HID_COLLECTION_PHYSICAL = 0, + HID_COLLECTION_APPLICATION, + HID_COLLECTION_LOGICAL, + HID_COLLECTION_REPORT, + HID_COLLECTION_NAMED_ARRAY, + HID_COLLECTION_USAGE_SWITCH, + HID_COLLECTION_USAGE_MODIFIER + }; //------------- GLOBAL ITEMS 6.2.2.7 -------------// -#define HID_USAGE_PAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, 1) -#define HID_USAGE_PAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, n) +#define HID_USAGE_PAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, 1) +#define HID_USAGE_PAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, n) -#define HID_LOGICAL_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, 1) -#define HID_LOGICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, n) +#define HID_LOGICAL_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, 1) +#define HID_LOGICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, n) -#define HID_LOGICAL_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, 1) -#define HID_LOGICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, n) +#define HID_LOGICAL_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, 1) +#define HID_LOGICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, n) -#define HID_PHYSICAL_MIN(x) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, 1) -#define HID_PHYSICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, n) +#define HID_PHYSICAL_MIN(x) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, 1) +#define HID_PHYSICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, n) -#define HID_PHYSICAL_MAX(x) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, 1) -#define HID_PHYSICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, n) +#define HID_PHYSICAL_MAX(x) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, 1) +#define HID_PHYSICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, n) -#define HID_UNIT_EXPONENT(x) HID_REPORT_ITEM(x, 5, RI_TYPE_GLOBAL, 1) +#define HID_UNIT_EXPONENT(x) HID_REPORT_ITEM(x, 5, RI_TYPE_GLOBAL, 1) #define HID_UNIT_EXPONENT_N(x, n) HID_REPORT_ITEM(x, 5, RI_TYPE_GLOBAL, n) -#define HID_UNIT(x) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, 1) -#define HID_UNIT_N(x, n) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, n) +#define HID_UNIT(x) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, 1) +#define HID_UNIT_N(x, n) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, n) -#define HID_REPORT_SIZE(x) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, 1) -#define HID_REPORT_SIZE_N(x, n) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, n) +#define HID_REPORT_SIZE(x) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, 1) +#define HID_REPORT_SIZE_N(x, n) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, n) -#define HID_REPORT_ID(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, 1), -#define HID_REPORT_ID_N(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, n), +#define HID_REPORT_ID(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, 1), +#define HID_REPORT_ID_N(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, n), -#define HID_REPORT_COUNT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, 1) -#define HID_REPORT_COUNT_N(x, n) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, n) +#define HID_REPORT_COUNT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, 1) +#define HID_REPORT_COUNT_N(x, n) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, n) -#define HID_PUSH HID_REPORT_ITEM(x, 10, RI_TYPE_GLOBAL, 0) -#define HID_POP HID_REPORT_ITEM(x, 11, RI_TYPE_GLOBAL, 0) +#define HID_PUSH HID_REPORT_ITEM(x, 10, RI_TYPE_GLOBAL, 0) +#define HID_POP HID_REPORT_ITEM(x, 11, RI_TYPE_GLOBAL, 0) //------------- LOCAL ITEMS 6.2.2.8 -------------// -#define HID_USAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, 1) -#define HID_USAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, n) +#define HID_USAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, 1) +#define HID_USAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, n) -#define HID_USAGE_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, 1) -#define HID_USAGE_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, n) +#define HID_USAGE_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, 1) +#define HID_USAGE_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, n) -#define HID_USAGE_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, 1) -#define HID_USAGE_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, n) +#define HID_USAGE_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, 1) +#define HID_USAGE_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, n) -//--------------------------------------------------------------------+ -// Usage Table -//--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Usage Table + //--------------------------------------------------------------------+ -/// HID Usage Table - Table 1: Usage Page Summary -enum { - HID_USAGE_PAGE_DESKTOP = 0x01, - HID_USAGE_PAGE_SIMULATE = 0x02, - HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03, - HID_USAGE_PAGE_SPORT = 0x04, - HID_USAGE_PAGE_GAME = 0x05, - HID_USAGE_PAGE_GENERIC_DEVICE = 0x06, - HID_USAGE_PAGE_KEYBOARD = 0x07, - HID_USAGE_PAGE_LED = 0x08, - HID_USAGE_PAGE_BUTTON = 0x09, - HID_USAGE_PAGE_ORDINAL = 0x0a, - HID_USAGE_PAGE_TELEPHONY = 0x0b, - HID_USAGE_PAGE_CONSUMER = 0x0c, - HID_USAGE_PAGE_DIGITIZER = 0x0d, - HID_USAGE_PAGE_PID = 0x0f, - HID_USAGE_PAGE_UNICODE = 0x10, - HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14, - HID_USAGE_PAGE_MEDICAL = 0x40, - HID_USAGE_PAGE_MONITOR = 0x80, //0x80 - 0x83 - HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87 - HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c, - HID_USAGE_PAGE_SCALE = 0x8d, - HID_USAGE_PAGE_MSR = 0x8e, - HID_USAGE_PAGE_CAMERA = 0x90, - HID_USAGE_PAGE_ARCADE = 0x91, - HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF -}; + /// HID Usage Table - Table 1: Usage Page Summary + enum + { + HID_USAGE_PAGE_DESKTOP = 0x01, + HID_USAGE_PAGE_SIMULATE = 0x02, + HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03, + HID_USAGE_PAGE_SPORT = 0x04, + HID_USAGE_PAGE_GAME = 0x05, + HID_USAGE_PAGE_GENERIC_DEVICE = 0x06, + HID_USAGE_PAGE_KEYBOARD = 0x07, + HID_USAGE_PAGE_LED = 0x08, + HID_USAGE_PAGE_BUTTON = 0x09, + HID_USAGE_PAGE_ORDINAL = 0x0a, + HID_USAGE_PAGE_TELEPHONY = 0x0b, + HID_USAGE_PAGE_CONSUMER = 0x0c, + HID_USAGE_PAGE_DIGITIZER = 0x0d, + HID_USAGE_PAGE_PID = 0x0f, + HID_USAGE_PAGE_UNICODE = 0x10, + HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14, + HID_USAGE_PAGE_MEDICAL = 0x40, + HID_USAGE_PAGE_MONITOR = 0x80, // 0x80 - 0x83 + HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87 + HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c, + HID_USAGE_PAGE_SCALE = 0x8d, + HID_USAGE_PAGE_MSR = 0x8e, + HID_USAGE_PAGE_CAMERA = 0x90, + HID_USAGE_PAGE_ARCADE = 0x91, + HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF + }; -/// HID Usage Table - Table 6: Generic Desktop Page -enum { - HID_USAGE_DESKTOP_POINTER = 0x01, - HID_USAGE_DESKTOP_MOUSE = 0x02, - HID_USAGE_DESKTOP_JOYSTICK = 0x04, - HID_USAGE_DESKTOP_GAMEPAD = 0x05, - HID_USAGE_DESKTOP_KEYBOARD = 0x06, - HID_USAGE_DESKTOP_KEYPAD = 0x07, - HID_USAGE_DESKTOP_MULTI_AXIS_CONTROLLER = 0x08, - HID_USAGE_DESKTOP_TABLET_PC_SYSTEM = 0x09, - HID_USAGE_DESKTOP_X = 0x30, - HID_USAGE_DESKTOP_Y = 0x31, - HID_USAGE_DESKTOP_Z = 0x32, - HID_USAGE_DESKTOP_RX = 0x33, - HID_USAGE_DESKTOP_RY = 0x34, - HID_USAGE_DESKTOP_RZ = 0x35, - HID_USAGE_DESKTOP_SLIDER = 0x36, - HID_USAGE_DESKTOP_DIAL = 0x37, - HID_USAGE_DESKTOP_WHEEL = 0x38, - HID_USAGE_DESKTOP_HAT_SWITCH = 0x39, - HID_USAGE_DESKTOP_COUNTED_BUFFER = 0x3a, - HID_USAGE_DESKTOP_BYTE_COUNT = 0x3b, - HID_USAGE_DESKTOP_MOTION_WAKEUP = 0x3c, - HID_USAGE_DESKTOP_START = 0x3d, - HID_USAGE_DESKTOP_SELECT = 0x3e, - HID_USAGE_DESKTOP_VX = 0x40, - HID_USAGE_DESKTOP_VY = 0x41, - HID_USAGE_DESKTOP_VZ = 0x42, - HID_USAGE_DESKTOP_VBRX = 0x43, - HID_USAGE_DESKTOP_VBRY = 0x44, - HID_USAGE_DESKTOP_VBRZ = 0x45, - HID_USAGE_DESKTOP_VNO = 0x46, - HID_USAGE_DESKTOP_FEATURE_NOTIFICATION = 0x47, - HID_USAGE_DESKTOP_RESOLUTION_MULTIPLIER = 0x48, - HID_USAGE_DESKTOP_SYSTEM_CONTROL = 0x80, - HID_USAGE_DESKTOP_SYSTEM_POWER_DOWN = 0x81, - HID_USAGE_DESKTOP_SYSTEM_SLEEP = 0x82, - HID_USAGE_DESKTOP_SYSTEM_WAKE_UP = 0x83, - HID_USAGE_DESKTOP_SYSTEM_CONTEXT_MENU = 0x84, - HID_USAGE_DESKTOP_SYSTEM_MAIN_MENU = 0x85, - HID_USAGE_DESKTOP_SYSTEM_APP_MENU = 0x86, - HID_USAGE_DESKTOP_SYSTEM_MENU_HELP = 0x87, - HID_USAGE_DESKTOP_SYSTEM_MENU_EXIT = 0x88, - HID_USAGE_DESKTOP_SYSTEM_MENU_SELECT = 0x89, - HID_USAGE_DESKTOP_SYSTEM_MENU_RIGHT = 0x8A, - HID_USAGE_DESKTOP_SYSTEM_MENU_LEFT = 0x8B, - HID_USAGE_DESKTOP_SYSTEM_MENU_UP = 0x8C, - HID_USAGE_DESKTOP_SYSTEM_MENU_DOWN = 0x8D, - HID_USAGE_DESKTOP_SYSTEM_COLD_RESTART = 0x8E, - HID_USAGE_DESKTOP_SYSTEM_WARM_RESTART = 0x8F, - HID_USAGE_DESKTOP_DPAD_UP = 0x90, - HID_USAGE_DESKTOP_DPAD_DOWN = 0x91, - HID_USAGE_DESKTOP_DPAD_RIGHT = 0x92, - HID_USAGE_DESKTOP_DPAD_LEFT = 0x93, - HID_USAGE_DESKTOP_SYSTEM_DOCK = 0xA0, - HID_USAGE_DESKTOP_SYSTEM_UNDOCK = 0xA1, - HID_USAGE_DESKTOP_SYSTEM_SETUP = 0xA2, - HID_USAGE_DESKTOP_SYSTEM_BREAK = 0xA3, - HID_USAGE_DESKTOP_SYSTEM_DEBUGGER_BREAK = 0xA4, - HID_USAGE_DESKTOP_APPLICATION_BREAK = 0xA5, - HID_USAGE_DESKTOP_APPLICATION_DEBUGGER_BREAK = 0xA6, - HID_USAGE_DESKTOP_SYSTEM_SPEAKER_MUTE = 0xA7, - HID_USAGE_DESKTOP_SYSTEM_HIBERNATE = 0xA8, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INVERT = 0xB0, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INTERNAL = 0xB1, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_EXTERNAL = 0xB2, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_BOTH = 0xB3, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_DUAL = 0xB4, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_TOGGLE_INT_EXT = 0xB5, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_SWAP_PRIMARY_SECONDARY = 0xB6, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_LCD_AUTOSCALE = 0xB7 -}; + /// HID Usage Table - Table 6: Generic Desktop Page + enum + { + HID_USAGE_DESKTOP_POINTER = 0x01, + HID_USAGE_DESKTOP_MOUSE = 0x02, + HID_USAGE_DESKTOP_JOYSTICK = 0x04, + HID_USAGE_DESKTOP_GAMEPAD = 0x05, + HID_USAGE_DESKTOP_KEYBOARD = 0x06, + HID_USAGE_DESKTOP_KEYPAD = 0x07, + HID_USAGE_DESKTOP_MULTI_AXIS_CONTROLLER = 0x08, + HID_USAGE_DESKTOP_TABLET_PC_SYSTEM = 0x09, + HID_USAGE_DESKTOP_X = 0x30, + HID_USAGE_DESKTOP_Y = 0x31, + HID_USAGE_DESKTOP_Z = 0x32, + HID_USAGE_DESKTOP_RX = 0x33, + HID_USAGE_DESKTOP_RY = 0x34, + HID_USAGE_DESKTOP_RZ = 0x35, + HID_USAGE_DESKTOP_SLIDER = 0x36, + HID_USAGE_DESKTOP_DIAL = 0x37, + HID_USAGE_DESKTOP_WHEEL = 0x38, + HID_USAGE_DESKTOP_HAT_SWITCH = 0x39, + HID_USAGE_DESKTOP_COUNTED_BUFFER = 0x3a, + HID_USAGE_DESKTOP_BYTE_COUNT = 0x3b, + HID_USAGE_DESKTOP_MOTION_WAKEUP = 0x3c, + HID_USAGE_DESKTOP_START = 0x3d, + HID_USAGE_DESKTOP_SELECT = 0x3e, + HID_USAGE_DESKTOP_VX = 0x40, + HID_USAGE_DESKTOP_VY = 0x41, + HID_USAGE_DESKTOP_VZ = 0x42, + HID_USAGE_DESKTOP_VBRX = 0x43, + HID_USAGE_DESKTOP_VBRY = 0x44, + HID_USAGE_DESKTOP_VBRZ = 0x45, + HID_USAGE_DESKTOP_VNO = 0x46, + HID_USAGE_DESKTOP_FEATURE_NOTIFICATION = 0x47, + HID_USAGE_DESKTOP_RESOLUTION_MULTIPLIER = 0x48, + HID_USAGE_DESKTOP_SYSTEM_CONTROL = 0x80, + HID_USAGE_DESKTOP_SYSTEM_POWER_DOWN = 0x81, + HID_USAGE_DESKTOP_SYSTEM_SLEEP = 0x82, + HID_USAGE_DESKTOP_SYSTEM_WAKE_UP = 0x83, + HID_USAGE_DESKTOP_SYSTEM_CONTEXT_MENU = 0x84, + HID_USAGE_DESKTOP_SYSTEM_MAIN_MENU = 0x85, + HID_USAGE_DESKTOP_SYSTEM_APP_MENU = 0x86, + HID_USAGE_DESKTOP_SYSTEM_MENU_HELP = 0x87, + HID_USAGE_DESKTOP_SYSTEM_MENU_EXIT = 0x88, + HID_USAGE_DESKTOP_SYSTEM_MENU_SELECT = 0x89, + HID_USAGE_DESKTOP_SYSTEM_MENU_RIGHT = 0x8A, + HID_USAGE_DESKTOP_SYSTEM_MENU_LEFT = 0x8B, + HID_USAGE_DESKTOP_SYSTEM_MENU_UP = 0x8C, + HID_USAGE_DESKTOP_SYSTEM_MENU_DOWN = 0x8D, + HID_USAGE_DESKTOP_SYSTEM_COLD_RESTART = 0x8E, + HID_USAGE_DESKTOP_SYSTEM_WARM_RESTART = 0x8F, + HID_USAGE_DESKTOP_DPAD_UP = 0x90, + HID_USAGE_DESKTOP_DPAD_DOWN = 0x91, + HID_USAGE_DESKTOP_DPAD_RIGHT = 0x92, + HID_USAGE_DESKTOP_DPAD_LEFT = 0x93, + HID_USAGE_DESKTOP_SYSTEM_DOCK = 0xA0, + HID_USAGE_DESKTOP_SYSTEM_UNDOCK = 0xA1, + HID_USAGE_DESKTOP_SYSTEM_SETUP = 0xA2, + HID_USAGE_DESKTOP_SYSTEM_BREAK = 0xA3, + HID_USAGE_DESKTOP_SYSTEM_DEBUGGER_BREAK = 0xA4, + HID_USAGE_DESKTOP_APPLICATION_BREAK = 0xA5, + HID_USAGE_DESKTOP_APPLICATION_DEBUGGER_BREAK = 0xA6, + HID_USAGE_DESKTOP_SYSTEM_SPEAKER_MUTE = 0xA7, + HID_USAGE_DESKTOP_SYSTEM_HIBERNATE = 0xA8, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INVERT = 0xB0, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INTERNAL = 0xB1, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_EXTERNAL = 0xB2, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_BOTH = 0xB3, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_DUAL = 0xB4, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_TOGGLE_INT_EXT = 0xB5, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_SWAP_PRIMARY_SECONDARY = 0xB6, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_LCD_AUTOSCALE = 0xB7 + }; + /// HID Usage Table: Consumer Page (0x0C) + /// Only contains controls that supported by Windows (whole list is too long) + enum + { + // Generic Control + HID_USAGE_CONSUMER_CONTROL = 0x0001, -/// HID Usage Table: Consumer Page (0x0C) -/// Only contains controls that supported by Windows (whole list is too long) -enum -{ - // Generic Control - HID_USAGE_CONSUMER_CONTROL = 0x0001, + // Power Control + HID_USAGE_CONSUMER_POWER = 0x0030, + HID_USAGE_CONSUMER_RESET = 0x0031, + HID_USAGE_CONSUMER_SLEEP = 0x0032, - // Power Control - HID_USAGE_CONSUMER_POWER = 0x0030, - HID_USAGE_CONSUMER_RESET = 0x0031, - HID_USAGE_CONSUMER_SLEEP = 0x0032, + // Screen Brightness + HID_USAGE_CONSUMER_BRIGHTNESS_INCREMENT = 0x006F, + HID_USAGE_CONSUMER_BRIGHTNESS_DECREMENT = 0x0070, - // Screen Brightness - HID_USAGE_CONSUMER_BRIGHTNESS_INCREMENT = 0x006F, - HID_USAGE_CONSUMER_BRIGHTNESS_DECREMENT = 0x0070, + // These HID usages operate only on mobile systems (battery powered) and + // require Windows 8 (build 8302 or greater). + HID_USAGE_CONSUMER_WIRELESS_RADIO_CONTROLS = 0x000C, + HID_USAGE_CONSUMER_WIRELESS_RADIO_BUTTONS = 0x00C6, + HID_USAGE_CONSUMER_WIRELESS_RADIO_LED = 0x00C7, + HID_USAGE_CONSUMER_WIRELESS_RADIO_SLIDER_SWITCH = 0x00C8, - // These HID usages operate only on mobile systems (battery powered) and - // require Windows 8 (build 8302 or greater). - HID_USAGE_CONSUMER_WIRELESS_RADIO_CONTROLS = 0x000C, - HID_USAGE_CONSUMER_WIRELESS_RADIO_BUTTONS = 0x00C6, - HID_USAGE_CONSUMER_WIRELESS_RADIO_LED = 0x00C7, - HID_USAGE_CONSUMER_WIRELESS_RADIO_SLIDER_SWITCH = 0x00C8, + // Media Control + HID_USAGE_CONSUMER_PLAY_PAUSE = 0x00CD, + HID_USAGE_CONSUMER_SCAN_NEXT = 0x00B5, + HID_USAGE_CONSUMER_SCAN_PREVIOUS = 0x00B6, + HID_USAGE_CONSUMER_STOP = 0x00B7, + HID_USAGE_CONSUMER_VOLUME = 0x00E0, + HID_USAGE_CONSUMER_MUTE = 0x00E2, + HID_USAGE_CONSUMER_BASS = 0x00E3, + HID_USAGE_CONSUMER_TREBLE = 0x00E4, + HID_USAGE_CONSUMER_BASS_BOOST = 0x00E5, + HID_USAGE_CONSUMER_VOLUME_INCREMENT = 0x00E9, + HID_USAGE_CONSUMER_VOLUME_DECREMENT = 0x00EA, + HID_USAGE_CONSUMER_BASS_INCREMENT = 0x0152, + HID_USAGE_CONSUMER_BASS_DECREMENT = 0x0153, + HID_USAGE_CONSUMER_TREBLE_INCREMENT = 0x0154, + HID_USAGE_CONSUMER_TREBLE_DECREMENT = 0x0155, - // Media Control - HID_USAGE_CONSUMER_PLAY_PAUSE = 0x00CD, - HID_USAGE_CONSUMER_SCAN_NEXT = 0x00B5, - HID_USAGE_CONSUMER_SCAN_PREVIOUS = 0x00B6, - HID_USAGE_CONSUMER_STOP = 0x00B7, - HID_USAGE_CONSUMER_VOLUME = 0x00E0, - HID_USAGE_CONSUMER_MUTE = 0x00E2, - HID_USAGE_CONSUMER_BASS = 0x00E3, - HID_USAGE_CONSUMER_TREBLE = 0x00E4, - HID_USAGE_CONSUMER_BASS_BOOST = 0x00E5, - HID_USAGE_CONSUMER_VOLUME_INCREMENT = 0x00E9, - HID_USAGE_CONSUMER_VOLUME_DECREMENT = 0x00EA, - HID_USAGE_CONSUMER_BASS_INCREMENT = 0x0152, - HID_USAGE_CONSUMER_BASS_DECREMENT = 0x0153, - HID_USAGE_CONSUMER_TREBLE_INCREMENT = 0x0154, - HID_USAGE_CONSUMER_TREBLE_DECREMENT = 0x0155, + // Application Launcher + HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL_CONFIGURATION = 0x0183, + HID_USAGE_CONSUMER_AL_EMAIL_READER = 0x018A, + HID_USAGE_CONSUMER_AL_CALCULATOR = 0x0192, + HID_USAGE_CONSUMER_AL_LOCAL_BROWSER = 0x0194, - // Application Launcher - HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL_CONFIGURATION = 0x0183, - HID_USAGE_CONSUMER_AL_EMAIL_READER = 0x018A, - HID_USAGE_CONSUMER_AL_CALCULATOR = 0x0192, - HID_USAGE_CONSUMER_AL_LOCAL_BROWSER = 0x0194, + // Browser/Explorer Specific + HID_USAGE_CONSUMER_AC_SEARCH = 0x0221, + HID_USAGE_CONSUMER_AC_HOME = 0x0223, + HID_USAGE_CONSUMER_AC_BACK = 0x0224, + HID_USAGE_CONSUMER_AC_FORWARD = 0x0225, + HID_USAGE_CONSUMER_AC_STOP = 0x0226, + HID_USAGE_CONSUMER_AC_REFRESH = 0x0227, + HID_USAGE_CONSUMER_AC_BOOKMARKS = 0x022A, - // Browser/Explorer Specific - HID_USAGE_CONSUMER_AC_SEARCH = 0x0221, - HID_USAGE_CONSUMER_AC_HOME = 0x0223, - HID_USAGE_CONSUMER_AC_BACK = 0x0224, - HID_USAGE_CONSUMER_AC_FORWARD = 0x0225, - HID_USAGE_CONSUMER_AC_STOP = 0x0226, - HID_USAGE_CONSUMER_AC_REFRESH = 0x0227, - HID_USAGE_CONSUMER_AC_BOOKMARKS = 0x022A, - - // Mouse Horizontal scroll - HID_USAGE_CONSUMER_AC_PAN = 0x0238, -}; + // Mouse Horizontal scroll + HID_USAGE_CONSUMER_AC_PAN = 0x0238, + }; /*-------------------------------------------------------------------- * ASCII to KEYCODE Conversion @@ -1527,138 +1534,140 @@ enum * tud_hid_keyboard_report(report_id, modifier, keycode); * *--------------------------------------------------------------------*/ -#define HID_ASCII_TO_KEYCODE \ - {0, 0 }, /* 0x00 Null */ \ - {0, 0 }, /* 0x01 */ \ - {0, 0 }, /* 0x02 */ \ - {0, 0 }, /* 0x03 */ \ - {0, 0 }, /* 0x04 */ \ - {0, 0 }, /* 0x05 */ \ - {0, 0 }, /* 0x06 */ \ - {0, 0 }, /* 0x07 */ \ - {0, HID_KEY_BACKSPACE }, /* 0x08 Backspace */ \ - {0, HID_KEY_TAB }, /* 0x09 Tab */ \ - {0, HID_KEY_RETURN }, /* 0x0A Line Feed */ \ - {0, 0 }, /* 0x0B */ \ - {0, 0 }, /* 0x0C */ \ - {0, HID_KEY_RETURN }, /* 0x0D CR */ \ - {0, 0 }, /* 0x0E */ \ - {0, 0 }, /* 0x0F */ \ - {0, 0 }, /* 0x10 */ \ - {0, 0 }, /* 0x11 */ \ - {0, 0 }, /* 0x12 */ \ - {0, 0 }, /* 0x13 */ \ - {0, 0 }, /* 0x14 */ \ - {0, 0 }, /* 0x15 */ \ - {0, 0 }, /* 0x16 */ \ - {0, 0 }, /* 0x17 */ \ - {0, 0 }, /* 0x18 */ \ - {0, 0 }, /* 0x19 */ \ - {0, 0 }, /* 0x1A */ \ - {0, HID_KEY_ESCAPE }, /* 0x1B Escape */ \ - {0, 0 }, /* 0x1C */ \ - {0, 0 }, /* 0x1D */ \ - {0, 0 }, /* 0x1E */ \ - {0, 0 }, /* 0x1F */ \ - \ - {0, HID_KEY_SPACE }, /* 0x20 */ \ - {1, HID_KEY_1 }, /* 0x21 ! */ \ - {1, HID_KEY_APOSTROPHE }, /* 0x22 " */ \ - {1, HID_KEY_3 }, /* 0x23 # */ \ - {1, HID_KEY_4 }, /* 0x24 $ */ \ - {1, HID_KEY_5 }, /* 0x25 % */ \ - {1, HID_KEY_7 }, /* 0x26 & */ \ - {0, HID_KEY_APOSTROPHE }, /* 0x27 ' */ \ - {1, HID_KEY_9 }, /* 0x28 ( */ \ - {1, HID_KEY_0 }, /* 0x29 ) */ \ - {1, HID_KEY_8 }, /* 0x2A * */ \ - {1, HID_KEY_EQUAL }, /* 0x2B + */ \ - {0, HID_KEY_COMMA }, /* 0x2C , */ \ - {0, HID_KEY_MINUS }, /* 0x2D - */ \ - {0, HID_KEY_PERIOD }, /* 0x2E . */ \ - {0, HID_KEY_SLASH }, /* 0x2F / */ \ - {0, HID_KEY_0 }, /* 0x30 0 */ \ - {0, HID_KEY_1 }, /* 0x31 1 */ \ - {0, HID_KEY_2 }, /* 0x32 2 */ \ - {0, HID_KEY_3 }, /* 0x33 3 */ \ - {0, HID_KEY_4 }, /* 0x34 4 */ \ - {0, HID_KEY_5 }, /* 0x35 5 */ \ - {0, HID_KEY_6 }, /* 0x36 6 */ \ - {0, HID_KEY_7 }, /* 0x37 7 */ \ - {0, HID_KEY_8 }, /* 0x38 8 */ \ - {0, HID_KEY_9 }, /* 0x39 9 */ \ - {1, HID_KEY_SEMICOLON }, /* 0x3A : */ \ - {0, HID_KEY_SEMICOLON }, /* 0x3B ; */ \ - {1, HID_KEY_COMMA }, /* 0x3C < */ \ - {0, HID_KEY_EQUAL }, /* 0x3D = */ \ - {1, HID_KEY_PERIOD }, /* 0x3E > */ \ - {1, HID_KEY_SLASH }, /* 0x3F ? */ \ - \ - {1, HID_KEY_2 }, /* 0x40 @ */ \ - {1, HID_KEY_A }, /* 0x41 A */ \ - {1, HID_KEY_B }, /* 0x42 B */ \ - {1, HID_KEY_C }, /* 0x43 C */ \ - {1, HID_KEY_D }, /* 0x44 D */ \ - {1, HID_KEY_E }, /* 0x45 E */ \ - {1, HID_KEY_F }, /* 0x46 F */ \ - {1, HID_KEY_G }, /* 0x47 G */ \ - {1, HID_KEY_H }, /* 0x48 H */ \ - {1, HID_KEY_I }, /* 0x49 I */ \ - {1, HID_KEY_J }, /* 0x4A J */ \ - {1, HID_KEY_K }, /* 0x4B K */ \ - {1, HID_KEY_L }, /* 0x4C L */ \ - {1, HID_KEY_M }, /* 0x4D M */ \ - {1, HID_KEY_N }, /* 0x4E N */ \ - {1, HID_KEY_O }, /* 0x4F O */ \ - {1, HID_KEY_P }, /* 0x50 P */ \ - {1, HID_KEY_Q }, /* 0x51 Q */ \ - {1, HID_KEY_R }, /* 0x52 R */ \ - {1, HID_KEY_S }, /* 0x53 S */ \ - {1, HID_KEY_T }, /* 0x55 T */ \ - {1, HID_KEY_U }, /* 0x55 U */ \ - {1, HID_KEY_V }, /* 0x56 V */ \ - {1, HID_KEY_W }, /* 0x57 W */ \ - {1, HID_KEY_X }, /* 0x58 X */ \ - {1, HID_KEY_Y }, /* 0x59 Y */ \ - {1, HID_KEY_Z }, /* 0x5A Z */ \ - {0, HID_KEY_BRACKET_LEFT }, /* 0x5B [ */ \ - {0, HID_KEY_BACKSLASH }, /* 0x5C '\' */ \ - {0, HID_KEY_BRACKET_RIGHT }, /* 0x5D ] */ \ - {1, HID_KEY_6 }, /* 0x5E ^ */ \ - {1, HID_KEY_MINUS }, /* 0x5F _ */ \ - \ - {0, HID_KEY_GRAVE }, /* 0x60 ` */ \ - {0, HID_KEY_A }, /* 0x61 a */ \ - {0, HID_KEY_B }, /* 0x62 b */ \ - {0, HID_KEY_C }, /* 0x63 c */ \ - {0, HID_KEY_D }, /* 0x66 d */ \ - {0, HID_KEY_E }, /* 0x65 e */ \ - {0, HID_KEY_F }, /* 0x66 f */ \ - {0, HID_KEY_G }, /* 0x67 g */ \ - {0, HID_KEY_H }, /* 0x68 h */ \ - {0, HID_KEY_I }, /* 0x69 i */ \ - {0, HID_KEY_J }, /* 0x6A j */ \ - {0, HID_KEY_K }, /* 0x6B k */ \ - {0, HID_KEY_L }, /* 0x6C l */ \ - {0, HID_KEY_M }, /* 0x6D m */ \ - {0, HID_KEY_N }, /* 0x6E n */ \ - {0, HID_KEY_O }, /* 0x6F o */ \ - {0, HID_KEY_P }, /* 0x70 p */ \ - {0, HID_KEY_Q }, /* 0x71 q */ \ - {0, HID_KEY_R }, /* 0x72 r */ \ - {0, HID_KEY_S }, /* 0x73 s */ \ - {0, HID_KEY_T }, /* 0x75 t */ \ - {0, HID_KEY_U }, /* 0x75 u */ \ - {0, HID_KEY_V }, /* 0x76 v */ \ - {0, HID_KEY_W }, /* 0x77 w */ \ - {0, HID_KEY_X }, /* 0x78 x */ \ - {0, HID_KEY_Y }, /* 0x79 y */ \ - {0, HID_KEY_Z }, /* 0x7A z */ \ - {1, HID_KEY_BRACKET_LEFT }, /* 0x7B { */ \ - {1, HID_KEY_BACKSLASH }, /* 0x7C | */ \ - {1, HID_KEY_BRACKET_RIGHT }, /* 0x7D } */ \ - {1, HID_KEY_GRAVE }, /* 0x7E ~ */ \ - {0, HID_KEY_DELETE } /* 0x7F Delete */ \ +#define HID_ASCII_TO_KEYCODE \ + {0, 0}, /* 0x00 Null */ \ + {0, 0}, /* 0x01 */ \ + {0, 0}, /* 0x02 */ \ + {0, 0}, /* 0x03 */ \ + {0, 0}, /* 0x04 */ \ + {0, 0}, /* 0x05 */ \ + {0, 0}, /* 0x06 */ \ + {0, 0}, /* 0x07 */ \ + {0, HID_KEY_BACKSPACE}, /* 0x08 Backspace */ \ + {0, HID_KEY_TAB}, /* 0x09 Tab */ \ + {0, HID_KEY_RETURN}, /* 0x0A Line Feed */ \ + {0, 0}, /* 0x0B */ \ + {0, 0}, /* 0x0C */ \ + {0, HID_KEY_RETURN}, /* 0x0D CR */ \ + {0, 0}, /* 0x0E */ \ + {0, 0}, /* 0x0F */ \ + {0, 0}, /* 0x10 */ \ + {0, 0}, /* 0x11 */ \ + {0, 0}, /* 0x12 */ \ + {0, 0}, /* 0x13 */ \ + {0, 0}, /* 0x14 */ \ + {0, 0}, /* 0x15 */ \ + {0, 0}, /* 0x16 */ \ + {0, 0}, /* 0x17 */ \ + {0, 0}, /* 0x18 */ \ + {0, 0}, /* 0x19 */ \ + {0, 0}, /* 0x1A */ \ + {0, HID_KEY_ESCAPE}, /* 0x1B Escape */ \ + {0, 0}, /* 0x1C */ \ + {0, 0}, /* 0x1D */ \ + {0, 0}, /* 0x1E */ \ + {0, 0}, /* 0x1F */ \ + \ + {0, HID_KEY_SPACE}, /* 0x20 */ \ + {1, HID_KEY_1}, /* 0x21 ! */ \ + {1, HID_KEY_APOSTROPHE}, /* 0x22 " */ \ + {1, HID_KEY_3}, /* 0x23 # */ \ + {1, HID_KEY_4}, /* 0x24 $ */ \ + {1, HID_KEY_5}, /* 0x25 % */ \ + {1, HID_KEY_7}, /* 0x26 & */ \ + {0, HID_KEY_APOSTROPHE}, /* 0x27 ' */ \ + {1, HID_KEY_9}, /* 0x28 ( */ \ + {1, HID_KEY_0}, /* 0x29 ) */ \ + {1, HID_KEY_8}, /* 0x2A * */ \ + {1, HID_KEY_EQUAL}, /* 0x2B + */ \ + {0, HID_KEY_COMMA}, /* 0x2C , */ \ + {0, HID_KEY_MINUS}, /* 0x2D - */ \ + {0, HID_KEY_PERIOD}, /* 0x2E . */ \ + {0, HID_KEY_SLASH}, /* 0x2F / */ \ + {0, HID_KEY_0}, /* 0x30 0 */ \ + {0, HID_KEY_1}, /* 0x31 1 */ \ + {0, HID_KEY_2}, /* 0x32 2 */ \ + {0, HID_KEY_3}, /* 0x33 3 */ \ + {0, HID_KEY_4}, /* 0x34 4 */ \ + {0, HID_KEY_5}, /* 0x35 5 */ \ + {0, HID_KEY_6}, /* 0x36 6 */ \ + {0, HID_KEY_7}, /* 0x37 7 */ \ + {0, HID_KEY_8}, /* 0x38 8 */ \ + {0, HID_KEY_9}, /* 0x39 9 */ \ + {1, HID_KEY_SEMICOLON}, /* 0x3A : */ \ + {0, HID_KEY_SEMICOLON}, /* 0x3B ; */ \ + {1, HID_KEY_COMMA}, /* 0x3C < */ \ + {0, HID_KEY_EQUAL}, /* 0x3D = */ \ + {1, HID_KEY_PERIOD}, /* 0x3E > */ \ + {1, HID_KEY_SLASH}, /* 0x3F ? */ \ + \ + {1, HID_KEY_2}, /* 0x40 @ */ \ + {1, HID_KEY_A}, /* 0x41 A */ \ + {1, HID_KEY_B}, /* 0x42 B */ \ + {1, HID_KEY_C}, /* 0x43 C */ \ + {1, HID_KEY_D}, /* 0x44 D */ \ + {1, HID_KEY_E}, /* 0x45 E */ \ + {1, HID_KEY_F}, /* 0x46 F */ \ + {1, HID_KEY_G}, /* 0x47 G */ \ + {1, HID_KEY_H}, /* 0x48 H */ \ + {1, HID_KEY_I}, /* 0x49 I */ \ + {1, HID_KEY_J}, /* 0x4A J */ \ + {1, HID_KEY_K}, /* 0x4B K */ \ + {1, HID_KEY_L}, /* 0x4C L */ \ + {1, HID_KEY_M}, /* 0x4D M */ \ + {1, HID_KEY_N}, /* 0x4E N */ \ + {1, HID_KEY_O}, /* 0x4F O */ \ + {1, HID_KEY_P}, /* 0x50 P */ \ + {1, HID_KEY_Q}, /* 0x51 Q */ \ + {1, HID_KEY_R}, /* 0x52 R */ \ + {1, HID_KEY_S}, /* 0x53 S */ \ + {1, HID_KEY_T}, /* 0x55 T */ \ + {1, HID_KEY_U}, /* 0x55 U */ \ + {1, HID_KEY_V}, /* 0x56 V */ \ + {1, HID_KEY_W}, /* 0x57 W */ \ + {1, HID_KEY_X}, /* 0x58 X */ \ + {1, HID_KEY_Y}, /* 0x59 Y */ \ + {1, HID_KEY_Z}, /* 0x5A Z */ \ + {0, HID_KEY_BRACKET_LEFT}, /* 0x5B [ */ \ + {0, HID_KEY_BACKSLASH}, /* 0x5C '\' */ \ + {0, HID_KEY_BRACKET_RIGHT}, /* 0x5D ] */ \ + {1, HID_KEY_6}, /* 0x5E ^ */ \ + {1, HID_KEY_MINUS}, /* 0x5F _ */ \ + \ + {0, HID_KEY_GRAVE}, /* 0x60 ` */ \ + {0, HID_KEY_A}, /* 0x61 a */ \ + {0, HID_KEY_B}, /* 0x62 b */ \ + {0, HID_KEY_C}, /* 0x63 c */ \ + {0, HID_KEY_D}, /* 0x66 d */ \ + {0, HID_KEY_E}, /* 0x65 e */ \ + {0, HID_KEY_F}, /* 0x66 f */ \ + {0, HID_KEY_G}, /* 0x67 g */ \ + {0, HID_KEY_H}, /* 0x68 h */ \ + {0, HID_KEY_I}, /* 0x69 i */ \ + {0, HID_KEY_J}, /* 0x6A j */ \ + {0, HID_KEY_K}, /* 0x6B k */ \ + {0, HID_KEY_L}, /* 0x6C l */ \ + {0, HID_KEY_M}, /* 0x6D m */ \ + {0, HID_KEY_N}, /* 0x6E n */ \ + {0, HID_KEY_O}, /* 0x6F o */ \ + {0, HID_KEY_P}, /* 0x70 p */ \ + {0, HID_KEY_Q}, /* 0x71 q */ \ + {0, HID_KEY_R}, /* 0x72 r */ \ + {0, HID_KEY_S}, /* 0x73 s */ \ + {0, HID_KEY_T}, /* 0x75 t */ \ + {0, HID_KEY_U}, /* 0x75 u */ \ + {0, HID_KEY_V}, /* 0x76 v */ \ + {0, HID_KEY_W}, /* 0x77 w */ \ + {0, HID_KEY_X}, /* 0x78 x */ \ + {0, HID_KEY_Y}, /* 0x79 y */ \ + {0, HID_KEY_Z}, /* 0x7A z */ \ + {1, HID_KEY_BRACKET_LEFT}, /* 0x7B { */ \ + {1, HID_KEY_BACKSLASH}, /* 0x7C | */ \ + {1, HID_KEY_BRACKET_RIGHT}, /* 0x7D } */ \ + {1, HID_KEY_GRAVE}, /* 0x7E ~ */ \ + { \ + 0, HID_KEY_DELETE \ + } /* 0x7F Delete */ /*-------------------------------------------------------------------- * KEYCODE to Ascii Conversion @@ -1671,120 +1680,113 @@ enum * char ch = shift ? conv_table[chr][1] : conv_table[chr][0]; * *--------------------------------------------------------------------*/ -#define HID_KEYCODE_TO_ASCII \ - {0 , 0 }, /* 0x00 */ \ - {0 , 0 }, /* 0x01 */ \ - {0 , 0 }, /* 0x02 */ \ - {0 , 0 }, /* 0x03 */ \ - {'a' , 'A' }, /* 0x04 */ \ - {'b' , 'B' }, /* 0x05 */ \ - {'c' , 'C' }, /* 0x06 */ \ - {'d' , 'D' }, /* 0x07 */ \ - {'e' , 'E' }, /* 0x08 */ \ - {'f' , 'F' }, /* 0x09 */ \ - {'g' , 'G' }, /* 0x0a */ \ - {'h' , 'H' }, /* 0x0b */ \ - {'i' , 'I' }, /* 0x0c */ \ - {'j' , 'J' }, /* 0x0d */ \ - {'k' , 'K' }, /* 0x0e */ \ - {'l' , 'L' }, /* 0x0f */ \ - {'m' , 'M' }, /* 0x10 */ \ - {'n' , 'N' }, /* 0x11 */ \ - {'o' , 'O' }, /* 0x12 */ \ - {'p' , 'P' }, /* 0x13 */ \ - {'q' , 'Q' }, /* 0x14 */ \ - {'r' , 'R' }, /* 0x15 */ \ - {'s' , 'S' }, /* 0x16 */ \ - {'t' , 'T' }, /* 0x17 */ \ - {'u' , 'U' }, /* 0x18 */ \ - {'v' , 'V' }, /* 0x19 */ \ - {'w' , 'W' }, /* 0x1a */ \ - {'x' , 'X' }, /* 0x1b */ \ - {'y' , 'Y' }, /* 0x1c */ \ - {'z' , 'Z' }, /* 0x1d */ \ - {'1' , '!' }, /* 0x1e */ \ - {'2' , '@' }, /* 0x1f */ \ - {'3' , '#' }, /* 0x20 */ \ - {'4' , '$' }, /* 0x21 */ \ - {'5' , '%' }, /* 0x22 */ \ - {'6' , '^' }, /* 0x23 */ \ - {'7' , '&' }, /* 0x24 */ \ - {'8' , '*' }, /* 0x25 */ \ - {'9' , '(' }, /* 0x26 */ \ - {'0' , ')' }, /* 0x27 */ \ - {'\r' , '\r' }, /* 0x28 */ \ - {'\x1b', '\x1b' }, /* 0x29 */ \ - {'\b' , '\b' }, /* 0x2a */ \ - {'\t' , '\t' }, /* 0x2b */ \ - {' ' , ' ' }, /* 0x2c */ \ - {'-' , '_' }, /* 0x2d */ \ - {'=' , '+' }, /* 0x2e */ \ - {'[' , '{' }, /* 0x2f */ \ - {']' , '}' }, /* 0x30 */ \ - {'\\' , '|' }, /* 0x31 */ \ - {'#' , '~' }, /* 0x32 */ \ - {';' , ':' }, /* 0x33 */ \ - {'\'' , '\"' }, /* 0x34 */ \ - {'`' , '~' }, /* 0x35 */ \ - {',' , '<' }, /* 0x36 */ \ - {'.' , '>' }, /* 0x37 */ \ - {'/' , '?' }, /* 0x38 */ \ - \ - {0 , 0 }, /* 0x39 */ \ - {0 , 0 }, /* 0x3a */ \ - {0 , 0 }, /* 0x3b */ \ - {0 , 0 }, /* 0x3c */ \ - {0 , 0 }, /* 0x3d */ \ - {0 , 0 }, /* 0x3e */ \ - {0 , 0 }, /* 0x3f */ \ - {0 , 0 }, /* 0x40 */ \ - {0 , 0 }, /* 0x41 */ \ - {0 , 0 }, /* 0x42 */ \ - {0 , 0 }, /* 0x43 */ \ - {0 , 0 }, /* 0x44 */ \ - {0 , 0 }, /* 0x45 */ \ - {0 , 0 }, /* 0x46 */ \ - {0 , 0 }, /* 0x47 */ \ - {0 , 0 }, /* 0x48 */ \ - {0 , 0 }, /* 0x49 */ \ - {0 , 0 }, /* 0x4a */ \ - {0 , 0 }, /* 0x4b */ \ - {0 , 0 }, /* 0x4c */ \ - {0 , 0 }, /* 0x4d */ \ - {0 , 0 }, /* 0x4e */ \ - {0 , 0 }, /* 0x4f */ \ - {0 , 0 }, /* 0x50 */ \ - {0 , 0 }, /* 0x51 */ \ - {0 , 0 }, /* 0x52 */ \ - {0 , 0 }, /* 0x53 */ \ - \ - {'/' , '/' }, /* 0x54 */ \ - {'*' , '*' }, /* 0x55 */ \ - {'-' , '-' }, /* 0x56 */ \ - {'+' , '+' }, /* 0x57 */ \ - {'\r' , '\r' }, /* 0x58 */ \ - {'1' , 0 }, /* 0x59 */ \ - {'2' , 0 }, /* 0x5a */ \ - {'3' , 0 }, /* 0x5b */ \ - {'4' , 0 }, /* 0x5c */ \ - {'5' , '5' }, /* 0x5d */ \ - {'6' , 0 }, /* 0x5e */ \ - {'7' , 0 }, /* 0x5f */ \ - {'8' , 0 }, /* 0x60 */ \ - {'9' , 0 }, /* 0x61 */ \ - {'0' , 0 }, /* 0x62 */ \ - {'0' , 0 }, /* 0x63 */ \ - {'=' , '=' }, /* 0x67 */ \ - +#define HID_KEYCODE_TO_ASCII \ + {0, 0}, /* 0x00 */ \ + {0, 0}, /* 0x01 */ \ + {0, 0}, /* 0x02 */ \ + {0, 0}, /* 0x03 */ \ + {'a', 'A'}, /* 0x04 */ \ + {'b', 'B'}, /* 0x05 */ \ + {'c', 'C'}, /* 0x06 */ \ + {'d', 'D'}, /* 0x07 */ \ + {'e', 'E'}, /* 0x08 */ \ + {'f', 'F'}, /* 0x09 */ \ + {'g', 'G'}, /* 0x0a */ \ + {'h', 'H'}, /* 0x0b */ \ + {'i', 'I'}, /* 0x0c */ \ + {'j', 'J'}, /* 0x0d */ \ + {'k', 'K'}, /* 0x0e */ \ + {'l', 'L'}, /* 0x0f */ \ + {'m', 'M'}, /* 0x10 */ \ + {'n', 'N'}, /* 0x11 */ \ + {'o', 'O'}, /* 0x12 */ \ + {'p', 'P'}, /* 0x13 */ \ + {'q', 'Q'}, /* 0x14 */ \ + {'r', 'R'}, /* 0x15 */ \ + {'s', 'S'}, /* 0x16 */ \ + {'t', 'T'}, /* 0x17 */ \ + {'u', 'U'}, /* 0x18 */ \ + {'v', 'V'}, /* 0x19 */ \ + {'w', 'W'}, /* 0x1a */ \ + {'x', 'X'}, /* 0x1b */ \ + {'y', 'Y'}, /* 0x1c */ \ + {'z', 'Z'}, /* 0x1d */ \ + {'1', '!'}, /* 0x1e */ \ + {'2', '@'}, /* 0x1f */ \ + {'3', '#'}, /* 0x20 */ \ + {'4', '$'}, /* 0x21 */ \ + {'5', '%'}, /* 0x22 */ \ + {'6', '^'}, /* 0x23 */ \ + {'7', '&'}, /* 0x24 */ \ + {'8', '*'}, /* 0x25 */ \ + {'9', '('}, /* 0x26 */ \ + {'0', ')'}, /* 0x27 */ \ + {'\r', '\r'}, /* 0x28 */ \ + {'\x1b', '\x1b'}, /* 0x29 */ \ + {'\b', '\b'}, /* 0x2a */ \ + {'\t', '\t'}, /* 0x2b */ \ + {' ', ' '}, /* 0x2c */ \ + {'-', '_'}, /* 0x2d */ \ + {'=', '+'}, /* 0x2e */ \ + {'[', '{'}, /* 0x2f */ \ + {']', '}'}, /* 0x30 */ \ + {'\\', '|'}, /* 0x31 */ \ + {'#', '~'}, /* 0x32 */ \ + {';', ':'}, /* 0x33 */ \ + {'\'', '\"'}, /* 0x34 */ \ + {'`', '~'}, /* 0x35 */ \ + {',', '<'}, /* 0x36 */ \ + {'.', '>'}, /* 0x37 */ \ + {'/', '?'}, /* 0x38 */ \ + \ + {0, 0}, /* 0x39 */ \ + {0, 0}, /* 0x3a */ \ + {0, 0}, /* 0x3b */ \ + {0, 0}, /* 0x3c */ \ + {0, 0}, /* 0x3d */ \ + {0, 0}, /* 0x3e */ \ + {0, 0}, /* 0x3f */ \ + {0, 0}, /* 0x40 */ \ + {0, 0}, /* 0x41 */ \ + {0, 0}, /* 0x42 */ \ + {0, 0}, /* 0x43 */ \ + {0, 0}, /* 0x44 */ \ + {0, 0}, /* 0x45 */ \ + {0, 0}, /* 0x46 */ \ + {0, 0}, /* 0x47 */ \ + {0, 0}, /* 0x48 */ \ + {0, 0}, /* 0x49 */ \ + {0, 0}, /* 0x4a */ \ + {0, 0}, /* 0x4b */ \ + {0, 0}, /* 0x4c */ \ + {0, 0}, /* 0x4d */ \ + {0, 0}, /* 0x4e */ \ + {0, 0}, /* 0x4f */ \ + {0, 0}, /* 0x50 */ \ + {0, 0}, /* 0x51 */ \ + {0, 0}, /* 0x52 */ \ + {0, 0}, /* 0x53 */ \ + \ + {'/', '/'}, /* 0x54 */ \ + {'*', '*'}, /* 0x55 */ \ + {'-', '-'}, /* 0x56 */ \ + {'+', '+'}, /* 0x57 */ \ + {'\r', '\r'}, /* 0x58 */ \ + {'1', 0}, /* 0x59 */ \ + {'2', 0}, /* 0x5a */ \ + {'3', 0}, /* 0x5b */ \ + {'4', 0}, /* 0x5c */ \ + {'5', '5'}, /* 0x5d */ \ + {'6', 0}, /* 0x5e */ \ + {'7', 0}, /* 0x5f */ \ + {'8', 0}, /* 0x60 */ \ + {'9', 0}, /* 0x61 */ \ + {'0', 0}, /* 0x62 */ \ + {'0', 0}, /* 0x63 */ \ + {'=', '='}, /* 0x67 */ #ifdef __cplusplus - } +} #endif - - - - #endif /* _TUSB_TYPES_H_ */ - - diff --git a/src/extralibs/ws2812b_dma_spi_led_driver.h b/src/extralibs/ws2812b_dma_spi_led_driver.h index 0c92112..4b083e4 100644 --- a/src/extralibs/ws2812b_dma_spi_led_driver.h +++ b/src/extralibs/ws2812b_dma_spi_led_driver.h @@ -2,28 +2,28 @@ I may write another version of this to use DMA to timer ports, but, the SPI port can be used to generate outputs very efficiently. So, for now, SPI Port. Additionally, it uses FAR less internal bus resources than to do the same thing with timers. - + **For the CH32V003 this means output will be on PORTC Pin 6** Copyright 2023 <>< Charles Lohr, under the MIT-x11 or NewBSD License, you choose! - If you are including this in main, simply - #define WS2812DMA_IMPLEMENTATION + If you are including this in main, simply + #define WS2812DMA_IMPLEMENTATION Other defines inclue: - #define WSRAW - #define WSRBG - #define WSGRB - #define WS2812B_ALLOW_INTERRUPT_NESTING + #define WSRAW + #define WSRBG + #define WSGRB + #define WS2812B_ALLOW_INTERRUPT_NESTING You will need to implement the following two functions, as callbacks from the ISR. - uint32_t WS2812BLEDCallback( int ledno ); + uint32_t WS2812BLEDCallback( int ledno ); You willalso need to call - WS2812BDMAInit(); + WS2812BDMAInit(); Then, whenyou want to update the LEDs, call: - WS2812BDMAStart( int num_leds ); + WS2812BDMAStart( int num_leds ); */ #ifndef _WS2812_LED_DRIVER_H @@ -32,11 +32,11 @@ #include // Use DMA and SPI to stream out WS2812B LED Data via the MOSI pin. -void WS2812BDMAInit( ); -void WS2812BDMAStart( int leds ); +void WS2812BDMAInit(); +void WS2812BDMAStart(int leds); // Callbacks that you must implement. -uint32_t WS2812BLEDCallback( int ledno ); +uint32_t WS2812BLEDCallback(int ledno); #ifdef WS2812DMA_IMPLEMENTATION @@ -46,230 +46,241 @@ uint32_t WS2812BLEDCallback( int ledno ); #endif // Note first n LEDs of DMA Buffer are 0's as a "break" -// Need one extra LED at end to leave line high. +// Need one extra LED at end to leave line high. // This must be greater than WS2812B_RESET_PERIOD. #define WS2812B_RESET_PERIOD 2 #ifdef WSRAW -#define DMA_BUFFER_LEN (((DMALEDS)/2)*8) +#define DMA_BUFFER_LEN (((DMALEDS) / 2) * 8) #else -#define DMA_BUFFER_LEN (((DMALEDS)/2)*6) +#define DMA_BUFFER_LEN (((DMALEDS) / 2) * 6) #endif -static uint16_t WS2812dmabuff[DMA_BUFFER_LEN]; +static uint16_t WS2812dmabuff[DMA_BUFFER_LEN]; static volatile int WS2812LEDs; static volatile int WS2812LEDPlace; static volatile int WS2812BLEDInUse; // This is the code that updates a portion of the WS2812dmabuff with new data. // This effectively creates the bitstream that outputs to the LEDs. -static void WS2812FillBuffSec( uint16_t * ptr, int numhalfwords, int tce ) +static void WS2812FillBuffSec(uint16_t *ptr, int numhalfwords, int tce) { - const static uint16_t bitquartets[16] = { - 0b1000100010001000, 0b1000100010001110, 0b1000100011101000, 0b1000100011101110, - 0b1000111010001000, 0b1000111010001110, 0b1000111011101000, 0b1000111011101110, - 0b1110100010001000, 0b1110100010001110, 0b1110100011101000, 0b1110100011101110, - 0b1110111010001000, 0b1110111010001110, 0b1110111011101000, 0b1110111011101110, }; + const static uint16_t bitquartets[16] = { + 0b1000100010001000, + 0b1000100010001110, + 0b1000100011101000, + 0b1000100011101110, + 0b1000111010001000, + 0b1000111010001110, + 0b1000111011101000, + 0b1000111011101110, + 0b1110100010001000, + 0b1110100010001110, + 0b1110100011101000, + 0b1110100011101110, + 0b1110111010001000, + 0b1110111010001110, + 0b1110111011101000, + 0b1110111011101110, + }; - int i; - uint16_t * end = ptr + numhalfwords; - int ledcount = WS2812LEDs; - int place = WS2812LEDPlace; + int i; + uint16_t *end = ptr + numhalfwords; + int ledcount = WS2812LEDs; + int place = WS2812LEDPlace; #ifdef WSRAW - while( place < 0 && ptr != end ) - { - uint32_t * lptr = (uint32_t *)ptr; - lptr[0] = 0; - lptr[1] = 0; - lptr[2] = 0; - lptr[3] = 0; - ptr += 8; - place++; - } + while (place < 0 && ptr != end) + { + uint32_t *lptr = (uint32_t *)ptr; + lptr[0] = 0; + lptr[1] = 0; + lptr[2] = 0; + lptr[3] = 0; + ptr += 8; + place++; + } #else - while( place < 0 && ptr != end ) - { - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - place++; - } + while (place < 0 && ptr != end) + { + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + place++; + } #endif - while( ptr != end ) - { - if( place >= ledcount ) - { - // Optionally, leave line high. - while( ptr != end ) - (*ptr++) = 0;//0xffff; + while (ptr != end) + { + if (place >= ledcount) + { + // Optionally, leave line high. + while (ptr != end) + (*ptr++) = 0; // 0xffff; - // Only safe to do this when we're on the second leg. - if( tce ) - { - if( place == ledcount ) - { - // Take the DMA out of circular mode and let it expire. - DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; - WS2812BLEDInUse = 0; - } - place++; - } + // Only safe to do this when we're on the second leg. + if (tce) + { + if (place == ledcount) + { + // Take the DMA out of circular mode and let it expire. + DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; + WS2812BLEDInUse = 0; + } + place++; + } - break; - } + break; + } #ifdef WSRAW - uint32_t ledval32bit = WS2812BLEDCallback( place++ ); + uint32_t ledval32bit = WS2812BLEDCallback(place++); - ptr[6] = bitquartets[(ledval32bit>>28)&0xf]; - ptr[7] = bitquartets[(ledval32bit>>24)&0xf]; - ptr[4] = bitquartets[(ledval32bit>>20)&0xf]; - ptr[5] = bitquartets[(ledval32bit>>16)&0xf]; - ptr[2] = bitquartets[(ledval32bit>>12)&0xf]; - ptr[3] = bitquartets[(ledval32bit>>8)&0xf]; - ptr[0] = bitquartets[(ledval32bit>>4)&0xf]; - ptr[1] = bitquartets[(ledval32bit>>0)&0xf]; + ptr[6] = bitquartets[(ledval32bit >> 28) & 0xf]; + ptr[7] = bitquartets[(ledval32bit >> 24) & 0xf]; + ptr[4] = bitquartets[(ledval32bit >> 20) & 0xf]; + ptr[5] = bitquartets[(ledval32bit >> 16) & 0xf]; + ptr[2] = bitquartets[(ledval32bit >> 12) & 0xf]; + ptr[3] = bitquartets[(ledval32bit >> 8) & 0xf]; + ptr[0] = bitquartets[(ledval32bit >> 4) & 0xf]; + ptr[1] = bitquartets[(ledval32bit >> 0) & 0xf]; - ptr += 8; - i += 8; + ptr += 8; + i += 8; #else - // Use a LUT to figure out how we should set the SPI line. - uint32_t ledval24bit = WS2812BLEDCallback( place++ ); + // Use a LUT to figure out how we should set the SPI line. + uint32_t ledval24bit = WS2812BLEDCallback(place++); #ifdef WSRBG - ptr[0] = bitquartets[(ledval24bit>>12)&0xf]; - ptr[1] = bitquartets[(ledval24bit>>8)&0xf]; - ptr[2] = bitquartets[(ledval24bit>>20)&0xf]; - ptr[3] = bitquartets[(ledval24bit>>16)&0xf]; - ptr[4] = bitquartets[(ledval24bit>>4)&0xf]; - ptr[5] = bitquartets[(ledval24bit>>0)&0xf]; -#elif defined( WSGRB ) - ptr[0] = bitquartets[(ledval24bit>>12)&0xf]; - ptr[1] = bitquartets[(ledval24bit>>8)&0xf]; - ptr[2] = bitquartets[(ledval24bit>>4)&0xf]; - ptr[3] = bitquartets[(ledval24bit>>0)&0xf]; - ptr[4] = bitquartets[(ledval24bit>>20)&0xf]; - ptr[5] = bitquartets[(ledval24bit>>16)&0xf]; + ptr[0] = bitquartets[(ledval24bit >> 12) & 0xf]; + ptr[1] = bitquartets[(ledval24bit >> 8) & 0xf]; + ptr[2] = bitquartets[(ledval24bit >> 20) & 0xf]; + ptr[3] = bitquartets[(ledval24bit >> 16) & 0xf]; + ptr[4] = bitquartets[(ledval24bit >> 4) & 0xf]; + ptr[5] = bitquartets[(ledval24bit >> 0) & 0xf]; +#elif defined(WSGRB) + ptr[0] = bitquartets[(ledval24bit >> 12) & 0xf]; + ptr[1] = bitquartets[(ledval24bit >> 8) & 0xf]; + ptr[2] = bitquartets[(ledval24bit >> 4) & 0xf]; + ptr[3] = bitquartets[(ledval24bit >> 0) & 0xf]; + ptr[4] = bitquartets[(ledval24bit >> 20) & 0xf]; + ptr[5] = bitquartets[(ledval24bit >> 16) & 0xf]; #else - ptr[0] = bitquartets[(ledval24bit>>20)&0xf]; - ptr[1] = bitquartets[(ledval24bit>>16)&0xf]; - ptr[2] = bitquartets[(ledval24bit>>12)&0xf]; - ptr[3] = bitquartets[(ledval24bit>>8)&0xf]; - ptr[4] = bitquartets[(ledval24bit>>4)&0xf]; - ptr[5] = bitquartets[(ledval24bit>>0)&0xf]; + ptr[0] = bitquartets[(ledval24bit >> 20) & 0xf]; + ptr[1] = bitquartets[(ledval24bit >> 16) & 0xf]; + ptr[2] = bitquartets[(ledval24bit >> 12) & 0xf]; + ptr[3] = bitquartets[(ledval24bit >> 8) & 0xf]; + ptr[4] = bitquartets[(ledval24bit >> 4) & 0xf]; + ptr[5] = bitquartets[(ledval24bit >> 0) & 0xf]; #endif - ptr += 6; - i += 6; + ptr += 6; + i += 6; #endif - - } - WS2812LEDPlace = place; + } + WS2812LEDPlace = place; } -void DMA1_Channel3_IRQHandler( void ) __attribute__((interrupt)); -void DMA1_Channel3_IRQHandler( void ) +void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt)); +void DMA1_Channel3_IRQHandler(void) { - //GPIOD->BSHR = 1; // Turn on GPIOD0 for profiling + // GPIOD->BSHR = 1; // Turn on GPIOD0 for profiling - // Backup flags. - volatile int intfr = DMA1->INTFR; - do - { - // Clear all possible flags. - DMA1->INTFCR = DMA1_IT_GL3; + // Backup flags. + volatile int intfr = DMA1->INTFR; + do + { + // Clear all possible flags. + DMA1->INTFCR = DMA1_IT_GL3; - // Strange note: These are backwards. DMA1_IT_HT3 should be HALF and - // DMA1_IT_TC3 should be COMPLETE. But for some reason, doing this causes - // LED jitter. I am henseforth flipping the order. + // Strange note: These are backwards. DMA1_IT_HT3 should be HALF and + // DMA1_IT_TC3 should be COMPLETE. But for some reason, doing this causes + // LED jitter. I am henseforth flipping the order. - if( intfr & DMA1_IT_HT3 ) - { - // Halfwaay (Fill in first part) - WS2812FillBuffSec( WS2812dmabuff, DMA_BUFFER_LEN / 2, 1 ); - } - if( intfr & DMA1_IT_TC3 ) - { - // Complete (Fill in second part) - WS2812FillBuffSec( WS2812dmabuff + DMA_BUFFER_LEN / 2, DMA_BUFFER_LEN / 2, 0 ); - } - intfr = DMA1->INTFR; - } while( intfr & DMA1_IT_GL3 ); + if (intfr & DMA1_IT_HT3) + { + // Halfwaay (Fill in first part) + WS2812FillBuffSec(WS2812dmabuff, DMA_BUFFER_LEN / 2, 1); + } + if (intfr & DMA1_IT_TC3) + { + // Complete (Fill in second part) + WS2812FillBuffSec(WS2812dmabuff + DMA_BUFFER_LEN / 2, DMA_BUFFER_LEN / 2, 0); + } + intfr = DMA1->INTFR; + } while (intfr & DMA1_IT_GL3); - //GPIOD->BSHR = 1<<16; // Turn off GPIOD0 for profiling + // GPIOD->BSHR = 1<<16; // Turn off GPIOD0 for profiling } -void WS2812BDMAStart( int leds ) +void WS2812BDMAStart(int leds) { - // Enter critical section. - __disable_irq(); - WS2812BLEDInUse = 1; - DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; - DMA1_Channel3->CNTR = 0; - DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; - WS2812LEDs = leds; - WS2812LEDPlace = -WS2812B_RESET_PERIOD; - __enable_irq(); + // Enter critical section. + __disable_irq(); + WS2812BLEDInUse = 1; + DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; + DMA1_Channel3->CNTR = 0; + DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; + WS2812LEDs = leds; + WS2812LEDPlace = -WS2812B_RESET_PERIOD; + __enable_irq(); - WS2812FillBuffSec( WS2812dmabuff, DMA_BUFFER_LEN, 0 ); + WS2812FillBuffSec(WS2812dmabuff, DMA_BUFFER_LEN, 0); - DMA1_Channel3->CNTR = DMA_BUFFER_LEN; // Number of unique uint16_t entries. - DMA1_Channel3->CFGR |= DMA_Mode_Circular; + DMA1_Channel3->CNTR = DMA_BUFFER_LEN; // Number of unique uint16_t entries. + DMA1_Channel3->CFGR |= DMA_Mode_Circular; } -void WS2812BDMAInit( ) +void WS2812BDMAInit() { - // Enable DMA + Peripherals - RCC->AHBPCENR |= RCC_AHBPeriph_DMA1; - RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; + // Enable DMA + Peripherals + RCC->AHBPCENR |= RCC_AHBPeriph_DMA1; + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; - // MOSI, Configure GPIO Pin - GPIOC->CFGLR &= ~(0xf<<(4*6)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*6); + // MOSI, Configure GPIO Pin + GPIOC->CFGLR &= ~(0xf << (4 * 6)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 6); - // Configure SPI - SPI1->CTLR1 = - SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_16b | - SPI_Mode_Master | SPI_Direction_1Line_Tx | - 3<<3; // Divisior = 16 (48/16 = 3MHz) + // Configure SPI + SPI1->CTLR1 = + SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_16b | + SPI_Mode_Master | SPI_Direction_1Line_Tx | + 3 << 3; // Divisior = 16 (48/16 = 3MHz) - SPI1->CTLR2 = SPI_CTLR2_TXDMAEN; - SPI1->HSCR = 1; + SPI1->CTLR2 = SPI_CTLR2_TXDMAEN; + SPI1->HSCR = 1; - SPI1->CTLR1 |= CTLR1_SPE_Set; + SPI1->CTLR1 |= CTLR1_SPE_Set; - SPI1->DATAR = 0; // Set SPI line Low. + SPI1->DATAR = 0; // Set SPI line Low. - //DMA1_Channel3 is for SPI1TX - DMA1_Channel3->PADDR = (uint32_t)&SPI1->DATAR; - DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; - DMA1_Channel3->CNTR = 0;// sizeof( bufferset )/2; // Number of unique copies. (Don't start, yet!) - DMA1_Channel3->CFGR = - DMA_M2M_Disable | - DMA_Priority_VeryHigh | - DMA_MemoryDataSize_HalfWord | - DMA_PeripheralDataSize_HalfWord | - DMA_MemoryInc_Enable | - DMA_Mode_Normal | // OR DMA_Mode_Circular or DMA_Mode_Normal - DMA_DIR_PeripheralDST | - DMA_IT_TC | DMA_IT_HT; // Transmission Complete + Half Empty Interrupts. + // DMA1_Channel3 is for SPI1TX + DMA1_Channel3->PADDR = (uint32_t)&SPI1->DATAR; + DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; + DMA1_Channel3->CNTR = 0; // sizeof( bufferset )/2; // Number of unique copies. (Don't start, yet!) + DMA1_Channel3->CFGR = + DMA_M2M_Disable | + DMA_Priority_VeryHigh | + DMA_MemoryDataSize_HalfWord | + DMA_PeripheralDataSize_HalfWord | + DMA_MemoryInc_Enable | + DMA_Mode_Normal | // OR DMA_Mode_Circular or DMA_Mode_Normal + DMA_DIR_PeripheralDST | + DMA_IT_TC | DMA_IT_HT; // Transmission Complete + Half Empty Interrupts. -// NVIC_SetPriority( DMA1_Channel3_IRQn, 0<<4 ); //We don't need to tweak priority. - NVIC_EnableIRQ( DMA1_Channel3_IRQn ); - DMA1_Channel3->CFGR |= DMA_CFGR1_EN; + // NVIC_SetPriority( DMA1_Channel3_IRQn, 0<<4 ); //We don't need to tweak priority. + NVIC_EnableIRQ(DMA1_Channel3_IRQn); + DMA1_Channel3->CFGR |= DMA_CFGR1_EN; #ifdef WS2812B_ALLOW_INTERRUPT_NESTING - __set_INTSYSCR( __get_INTSYSCR() | 2 ); // Enable interrupt nesting. - PFIC->IPRIOR[24] = 0b10000000; // Turn on preemption for DMA1Ch3 + __set_INTSYSCR(__get_INTSYSCR() | 2); // Enable interrupt nesting. + PFIC->IPRIOR[24] = 0b10000000; // Turn on preemption for DMA1Ch3 #endif } #endif #endif - diff --git a/src/extralibs/ws2812b_simple.h b/src/extralibs/ws2812b_simple.h index 0e35add..efc8c07 100644 --- a/src/extralibs/ws2812b_simple.h +++ b/src/extralibs/ws2812b_simple.h @@ -3,10 +3,10 @@ Copyright 2023 <>< Charles Lohr, under the MIT-x11 or NewBSD License, you choose! If you are including this in main, simply - #define WS2812BSIMPLE_IMPLEMENTATION + #define WS2812BSIMPLE_IMPLEMENTATION You may also want to define - #define WS2812BSIMPLE_NO_IRQ_TWEAKING + #define WS2812BSIMPLE_NO_IRQ_TWEAKING */ @@ -15,7 +15,7 @@ #include -void WS2812BSimpleSend( GPIO_TypeDef * port, int pin, uint8_t * data, int len_in_bytes ); +void WS2812BSimpleSend(GPIO_TypeDef *port, int pin, uint8_t *data, int len_in_bytes); #ifdef WS2812BSIMPLE_IMPLEMENTATION @@ -25,59 +25,58 @@ void WS2812BSimpleSend( GPIO_TypeDef * port, int pin, uint8_t * data, int len_in #error WS2812B Driver Requires FUNCONF_SYSTICK_USE_HCLK #endif -void WS2812BSimpleSend( GPIO_TypeDef * port, int pin, uint8_t * data, int len_in_bytes ) +void WS2812BSimpleSend(GPIO_TypeDef *port, int pin, uint8_t *data, int len_in_bytes) { - int port_id = (((intptr_t)port-(intptr_t)GPIOA)>>10); - RCC->APB2PCENR |= (RCC_APB2Periph_GPIOA<> 10); + RCC->APB2PCENR |= (RCC_APB2Periph_GPIOA << port_id); // Make sure port is enabled. - int poffset = (pin*4); - port->CFGLR = ( port->CFGLR & (~(0xf<CFGLR = (port->CFGLR & (~(0xf << poffset))) | ((GPIO_Speed_2MHz | GPIO_CNF_OUT_PP) << (poffset)); - int maskon = 1<BSHR = maskoff; + port->BSHR = maskoff; - uint8_t * end = data + len_in_bytes; - while( data != end ) - { - uint8_t byte = *data; + uint8_t *end = data + len_in_bytes; + while (data != end) + { + uint8_t byte = *data; - int i; - for( i = 0; i < 8; i++ ) - { - if( byte & 0x80 ) - { - // WS2812B's need AT LEAST 625ns for a logical "1" - port->BSHR = maskon; - DelaySysTick(25); - port->BSHR = maskoff; - DelaySysTick(1); - } - else - { - // WS2812B's need BETWEEN 62.5 to about 500 ns for a logical "0" + int i; + for (i = 0; i < 8; i++) + { + if (byte & 0x80) + { + // WS2812B's need AT LEAST 625ns for a logical "1" + port->BSHR = maskon; + DelaySysTick(25); + port->BSHR = maskoff; + DelaySysTick(1); + } + else + { + // WS2812B's need BETWEEN 62.5 to about 500 ns for a logical "0" #ifndef WS2812BSIMPLE_NO_IRQ_TWEAKING - __disable_irq(); + __disable_irq(); #endif - port->BSHR = maskon; - asm volatile( "nop\nnop\nnop\nnop" ); - port->BSHR = maskoff; + port->BSHR = maskon; + asm volatile("nop\nnop\nnop\nnop"); + port->BSHR = maskoff; #ifndef WS2812BSIMPLE_NO_IRQ_TWEAKING - __enable_irq(); + __enable_irq(); #endif - DelaySysTick(15); - } - byte <<= 1; - } + DelaySysTick(15); + } + byte <<= 1; + } - data++; - } + data++; + } - port->BSHR = maskoff; + port->BSHR = maskoff; } #endif #endif - diff --git a/src/misc/attic/.clang-format b/src/misc/attic/.clang-format new file mode 100644 index 0000000..659faab --- /dev/null +++ b/src/misc/attic/.clang-format @@ -0,0 +1,5 @@ +{ + "DisableFormat": true, + "SortIncludes": "Never" +} + diff --git a/src/misc/attic/temp_transition_helper.c b/src/misc/attic/temp_transition_helper.c index a05b193..267e02d 100644 --- a/src/misc/attic/temp_transition_helper.c +++ b/src/misc/attic/temp_transition_helper.c @@ -1,226 +1,244 @@ -#include #include -#include +#include #include +#include -const char * yes[] = { "SENTINEL_WILL_BE_REPLACED_BY_CMDLINE" }; // "CH32X03x", etc. element 0 is filled in by command-line -const char * no[] = { "CH32V10x", "CH32V30x", "CH32V20x", "CH32X03x", "CH32V003" }; +const char *yes[] = {"SENTINEL_WILL_BE_REPLACED_BY_CMDLINE"}; // "CH32X03x", etc. element 0 is filled in by command-line +const char *no[] = {"CH32V10x", "CH32V30x", "CH32V20x", "CH32X03x", "CH32V003"}; -char * WhitePull( const char ** sti ) +char *WhitePull(const char **sti) { - const char * st = *sti; - int len = 0; - while( ( *st == ' ' || *st == '\t' || *st == '(' ) && *st ) { st++; } - const char * sts = st; - while( *st != ' ' && *st != '\t' && *st != '\n' && *st != ')' && *st != '(' && *st != 0 ) { st++; len++; } - if( *st == ')' ) { st++; } - char * ret = malloc( len + 1 ); - memcpy( ret, sts, len ); - ret[len] = 0; - *sti = st; - return ret; + const char *st = *sti; + int len = 0; + while ((*st == ' ' || *st == '\t' || *st == '(') && *st) + { + st++; + } + const char *sts = st; + while (*st != ' ' && *st != '\t' && *st != '\n' && *st != ')' && *st != '(' && *st != 0) + { + st++; + len++; + } + if (*st == ')') { st++; } + char *ret = malloc(len + 1); + memcpy(ret, sts, len); + ret[len] = 0; + *sti = st; + return ret; } -int NYI( const char * s ) +int NYI(const char *s) { - int ret = 2; - char * wp = WhitePull( &s ); - int i; - for( i = 0; i < sizeof(yes)/sizeof(yes[0]); i++ ) - if( strcmp( yes[i], wp ) == 0 ) ret = 1; - if( ret != 1 ) - for( i = 0; i < sizeof(no)/sizeof(no[0]); i++ ) - if( strcmp( no[i], wp ) == 0 ) ret = 0; - free( wp ); - return ret; + int ret = 2; + char *wp = WhitePull(&s); + int i; + for (i = 0; i < sizeof(yes) / sizeof(yes[0]); i++) + if (strcmp(yes[i], wp) == 0) ret = 1; + if (ret != 1) + for (i = 0; i < sizeof(no) / sizeof(no[0]); i++) + if (strcmp(no[i], wp) == 0) ret = 0; + free(wp); + return ret; } -int EvalSpec( const char * spl ) +int EvalSpec(const char *spl) { - int rsofar = 0; - int i; - int lastv = 0; - int lasto = -1; - int ret = 0; + int rsofar = 0; + int i; + int lastv = 0; + int lasto = -1; + int ret = 0; cont: - char * wp = WhitePull( &spl ); - int def = -1; - if( strcmp( wp, "defined" ) == 0 ) def = 1; - if( strcmp( wp, "!defined" ) == 0 ) def = 2; - if( def < 0 ) return 2; - char * wpn = WhitePull( &spl ); - i = NYI( wpn ); -//printf( "SPIN: %s/%s/%d/%d/%d\n", wp, wpn, i, def, lasto ); - if( i == 2 ) return 2; + char *wp = WhitePull(&spl); + int def = -1; + if (strcmp(wp, "defined") == 0) def = 1; + if (strcmp(wp, "!defined") == 0) def = 2; + if (def < 0) return 2; + char *wpn = WhitePull(&spl); + i = NYI(wpn); + // printf( "SPIN: %s/%s/%d/%d/%d\n", wp, wpn, i, def, lasto ); + if (i == 2) return 2; - if( def == 2 ) i = !i; + if (def == 2) i = !i; - if( lasto == 1 ) - { - ret = lastv || i; - } - else if( lasto == 2 ) - ret = lastv && i; - else - ret = i; + if (lasto == 1) + { + ret = lastv || i; + } + else if (lasto == 2) + ret = lastv && i; + else + ret = i; - char * wpa = WhitePull( &spl ); -//printf( "WPA: \"%s\"\n", wpa ); - lastv = ret; - lasto = -1; -//printf( "RET: %d\n", ret ); - if( strcmp( wpa, "||" ) == 0 ) { lasto = 1; goto cont; } - else if( strcmp( wpa, "&&" ) == 0 ) { lasto = 2; goto cont; } - else return ret; + char *wpa = WhitePull(&spl); + // printf( "WPA: \"%s\"\n", wpa ); + lastv = ret; + lasto = -1; + // printf( "RET: %d\n", ret ); + if (strcmp(wpa, "||") == 0) + { + lasto = 1; + goto cont; + } + else if (strcmp(wpa, "&&") == 0) + { + lasto = 2; + goto cont; + } + else + return ret; } // 0 for no // 1 for yes // 2 for indeterminate -int NoYesInd( const char * preprocc ) +int NoYesInd(const char *preprocc) { - int ret; - int ofs = 0; - if( strncmp( preprocc, "#if ", 4 ) == 0 ) ofs = 4; - if( strncmp( preprocc, "#elif ", 6 ) == 0 ) ofs = 6; - if( ofs ) - { - ret = EvalSpec( preprocc + ofs ); - //printf( "SPEC: %d\n", ret ); - } - else if( strncmp( preprocc, "#ifdef ", 7 ) == 0 ) - { - const char * ep = preprocc + 6; - char * wp = WhitePull( &ep ); - ret = NYI( wp ); - free( wp ); - } - else if( strncmp( preprocc, "#ifndef ", 8 ) == 0 ) - { - const char * ep = preprocc + 6; - char * wp = WhitePull( &ep ); - ret = NYI( wp ); - if( ret < 2 ) ret = !ret; - free( wp ); - } - else - ret = 2; - //printf( "%d-> %s\n", ret, preprocc ); - return ret; + int ret; + int ofs = 0; + if (strncmp(preprocc, "#if ", 4) == 0) ofs = 4; + if (strncmp(preprocc, "#elif ", 6) == 0) ofs = 6; + if (ofs) + { + ret = EvalSpec(preprocc + ofs); + // printf( "SPEC: %d\n", ret ); + } + else if (strncmp(preprocc, "#ifdef ", 7) == 0) + { + const char *ep = preprocc + 6; + char *wp = WhitePull(&ep); + ret = NYI(wp); + free(wp); + } + else if (strncmp(preprocc, "#ifndef ", 8) == 0) + { + const char *ep = preprocc + 6; + char *wp = WhitePull(&ep); + ret = NYI(wp); + if (ret < 2) ret = !ret; + free(wp); + } + else + ret = 2; + // printf( "%d-> %s\n", ret, preprocc ); + return ret; } -const char * sslineis( const char * line, const char * match ) +const char *sslineis(const char *line, const char *match) { - while( *line == ' ' || *line == '\t' ) line++; - const char * linestart = line; - while( *line && *match == *line ) { line++; match++; } - if( *match == 0 ) - return linestart; - else - return 0; + while (*line == ' ' || *line == '\t') + line++; + const char *linestart = line; + while (*line && *match == *line) + { + line++; + match++; + } + if (*match == 0) + return linestart; + else + return 0; } -int main( int argc, char ** argv ) +int main(int argc, char **argv) { - if( argc != 3 ) - { - fprintf( stderr, "Syntax: transition [#define to trigger on] [file to convert]\nNo'd architectures:\n" ); - int i; - for( i = 0; i < sizeof(no)/sizeof(no[0]); i++ ) - { - fprintf( stderr, "\t%s\n", no[i] ); - } - return -1; - } + if (argc != 3) + { + fprintf(stderr, "Syntax: transition [#define to trigger on] [file to convert]\nNo'd architectures:\n"); + int i; + for (i = 0; i < sizeof(no) / sizeof(no[0]); i++) + { + fprintf(stderr, "\t%s\n", no[i]); + } + return -1; + } - yes[0] = argv[1]; + yes[0] = argv[1]; - FILE * f = fopen( argv[2], "r" ); - if( !f ) - { - fprintf( stderr, "Error: Could not open \"%s\"\n", argv[2] ); - return -2; - } - char line[1024]; - char * l; + FILE *f = fopen(argv[2], "r"); + if (!f) + { + fprintf(stderr, "Error: Could not open \"%s\"\n", argv[2]); + return -2; + } + char line[1024]; + char *l; + int depth = 0; - int depth = 0; + // 0 = no + // 1 = yes + // 2 = indeterminate + // 3 = super no. (I.e. after a true #if clause) + int yesnoind[1024]; + yesnoind[0] = 1; - // 0 = no - // 1 = yes - // 2 = indeterminate - // 3 = super no. (I.e. after a true #if clause) - int yesnoind[1024]; - yesnoind[0] = 1; + while (l = fgets(line, sizeof(line) - 1, f)) + { + const char *ss = 0; + int nyi = yesnoind[depth]; + int waspre = 0; - while( l = fgets( line, sizeof(line)-1, f ) ) - { - const char * ss = 0; - int nyi = yesnoind[depth]; - int waspre = 0; + if ((ss = sslineis(line, "#if ")) || (ss = sslineis(line, "#ifdef ")) || (ss = sslineis(line, "#ifndef "))) + { + waspre = 1; + // printf( "CHECK: %d/%s\n", depth, l ); + nyi = NoYesInd(ss); + depth++; + yesnoind[depth] = nyi; + } + else if ((ss = sslineis(line, "#elif "))) + { + if (nyi != 2) + { + waspre = 1; + if (nyi == 1) + { + nyi = 3; + } + else + { + nyi = NoYesInd(ss); + } + // printf( "ELIF check: %s %d\n", ss, nyi ); + yesnoind[depth] = nyi; + } + } + else if ((ss = sslineis(line, "#else"))) + { + if (nyi != 2) + { + waspre = 1; + if (yesnoind[depth] == 1) + nyi = 3; + else + nyi = !yesnoind[depth]; + yesnoind[depth] = nyi; + } + } + else if ((ss = sslineis(line, "#endif"))) + { + waspre = 1; + depth--; + if (depth < 0) + { + fprintf(stderr, "UNTERMD IF\n"); + } + } - if( (ss = sslineis( line, "#if " ) ) || (ss = sslineis( line, "#ifdef " ) ) || (ss = sslineis( line, "#ifndef " ) ) ) - { - waspre = 1; - //printf( "CHECK: %d/%s\n", depth, l ); - nyi = NoYesInd( ss ); - depth++; - yesnoind[depth] = nyi; - } - else if( (ss = sslineis( line, "#elif " ) ) ) - { - if( nyi != 2 ) - { - waspre = 1; - if( nyi == 1 ) - { - nyi = 3; - } - else - { - nyi = NoYesInd( ss ); - } - //printf( "ELIF check: %s %d\n", ss, nyi ); - yesnoind[depth] = nyi; - } - } - else if( (ss = sslineis( line, "#else" ) ) ) - { - if( nyi != 2 ) - { - waspre = 1; - if( yesnoind[depth] == 1 ) - nyi = 3; - else - nyi = !yesnoind[depth]; - yesnoind[depth] = nyi; - } - } - else if( (ss = sslineis( line, "#endif" ) ) ) - { - waspre = 1; - depth--; - if( depth < 0 ) - { - fprintf( stderr, "UNTERMD IF\n" ); - } - } + int thisv = nyi; + int i; + for (i = 0; i <= depth; i++) + { + // printf( "%d", yesnoind[i] ); + if (yesnoind[i] == 0 || yesnoind[i] == 3) thisv = 0; + } + // printf( ">>%s", l ); - int thisv = nyi; - int i; - for( i = 0; i <= depth; i++ ) - { - //printf( "%d", yesnoind[i] ); - if( yesnoind[i] == 0 || yesnoind[i] == 3 ) thisv = 0; - } - //printf( ">>%s", l ); - - if( thisv != 0 && thisv != 3 && ( thisv != 1 || !waspre ) ) - { - printf( "%s", l ); - } - } + if (thisv != 0 && thisv != 3 && (thisv != 1 || !waspre)) + { + printf("%s", l); + } + } } - - diff --git a/src/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt b/src/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt deleted file mode 100644 index 312ef5b..0000000 --- a/src/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt +++ /dev/null @@ -1,11 +0,0 @@ -This only works for the WCH LinkE in RISC-V mode. If your programmer has the BLUE light ON shortly after boot your programmer is in ARM mode. - -Please follow instructions here to convert your programmer to RISC-V mode from ARM mode. - -Basically press-and-hold the ModeS button while plugging in the USB. - -Once powered, it will store that to default. - -The blue light should be OFF. - -Once you are in RISC-V mode, you can install this driver by right-clicking on the driver and saying install. diff --git a/src/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).cat b/src/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).cat deleted file mode 100644 index 53493be00e17f8ae3ea2fbc95122fd8d7143b9fe..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5072 zcmeHLdpwj`A3x9Y%#3@46xA4axt6#@0{=NHV+i4)H7s^ zM6*Qw3WO9X7OGT1p~@MOAlQmffguwrnngrXG?JhLD3o2wkTGTuG(yOeCB#D65X1_E z@(kHgraVE=lupNpZFkd8&fT08Ew?e?#hr-?981XNaG)gzT3H3aabv_uysC^T6cWGC zd@O(ya6rupK;QzL0T0nU;E1{v-~(&axqt&)5rsL@3u+l8 zNdg%AX%CX1u>+w$v>d}xg!&Xo7mHbi%&aNEPSWOraC9jNk_$;jmofu4s0C#hbmMUp zsX+%cRlCF9y=m#o^F-!5gNfvEfx`)BpCecsX+Aup9~U(Y85il~fb`)23#6Mf;yEGx zolwJIb5Q4_6Ix2nhb6g44xfaJWHG3&=qZ791@!);v^;{<5zhP*tY)baIF}>c!~X(Y z&Oe}HEB`A{Gope8#X28@rqmT4D&OcHaX!B6!-%h9Q?!(TioxU{XdEO!IUumGkFq6P z4&q_T3c-s3#^&pUItHGH-msB0=KkZWU)5I+yZUQCKQA^{*1n*ZdbqM`!FbujBfjc{ zJP&)JlLR1Vq?MDz>u?moK5T*BLG-jj&^e-x`Hm7~L?r_$h0y{Sqh4UDc=$1$Vd>jY?h7tt;fLzmJjhBxaE-7!y$|x*+pSrb9 z`Y#f=GrH>$r@>K^BT3dS=+>RBcl;Xbf-aIXyFAtn6h9NSO8`t zBVv#0!XHV&K_CTTAwVm$5kgoqeULcH!FGpN)(7#3gOP&>F|m;TI~39fp^)kjQzSu> zN+~-9E*s)9L@p%N(PDOxk89M?>Xnc~)no!Y9>y^!KN`gp06$ccIf5WCU!o4)7Z(_K zU++=Q=Y2g9XJlU%vLx*O07Kk{f|}77Omcqt#eKozYyuw%li$c z+;-T^*ni~LnKwI@_)m8qY)$)Zpv0@Oby=^Esr= zk;2Kw>_>ZgFX-fLkI2h)n|7!!Liqc~xbg~JW~O?H{f?#8mR(X#O+7R8d7X2mwWSBx z2l+zxVvqe+O9PH#b0vrZ;%@j?A9vztNov0&8qfXD;F$)7_pgrg%rJ^k!1_ znNuU+jhIIb`n9{xrsw-52CZdBhjc8Qq8}bJjvGwncMp5SM>pT{s}g^k*Xe)geNAfe z>3&^%{VOvB-tSuPM11==kE;@`GG~A3@~Eto&0U%)9g|qTt!?wymcrrw#b)}*%IL5cg2fs zR(Bf`MvHV_w$8mce3Ny%+OXSg9P7cO_nSOd7SeV5Yr5+1SNvdX^qAz*GIym-I(j{$ z(56|ruFkUgcBP|++2%R>E7s4`SA1BK+Od;G+iNe!;5g)_{j6=2c&oKH|5WG&z3JYK z^M)o9jd?zCc4}E}M+-EHez9fE=TKhhHpj9r#j6@HHl_L&mk!(bdvw+5DL3b77eBju z;ap#DTDW(2sM*jtY4ybFyWMMT4wherjg$BdQQajA`XZajh{-&Y*?TmURD%>PTwYAp zjDFZ|pWYMk4NO^K__l}%5>AUcJXTSD_f+1lFEP;HGGrjj4CGI3()jzKo>o6$J z(}X1WSKy_Vs!YD4Zo|xlCp0eWUQO{VDh0zTLd~8>1NA-XO_^6G-H1D~_wa;EIWy1L zq`LVLyS;Xjxdzis(oM9M8tzd5S004;pz`e(2>$Y3Wg6bkDwd-j^M7P(R zsZHUrhhx2-jE}q5Ru*c~Br1$I{K>uEvq^KPdi`*~tCn>QNrL-OtN)HWb63tr=|=s* z`ibfR9us?mMbibD#;=R&E3}Ujrc}IKCo%7Ad*D8?lW*3$+CnqFS!>pZviwuI>n8`i zH%u!l(THhZz2n1;`vteH8``2m)_F|bC)4ivX5#j)*tPjGMCnzXMSZ@T7az}2v3pDS zh8&^uSM}Sq4JXf$x2s$yUD|lGu3ofWqnk?5)Y^OVYE7qkzk$z&?z(2bseMuV4$nC8 zj_RT`D0-a2gRSf8qH}$V4>-55^TD+qe+5g8+TtrW)Qa{8t^Qa+dGr-+8wg{rnb)=* zl-x4mWxOh|wK1GTqXvgUIKS%EJTW@=#=!mIcuKQ&uQESog=yJVOOq{a$_(Lfujt{L z?mbGobsqFTS!NPV)STb8iat=Q+dTc^K;zb4b){XNY9~YIhTWN0w0z?kX>J5Y{sv6~>K=9`QU^s1cUhn6vWB%oa3bGCw!rri_f-0L zdju}_8W6Fg zyW8?5l}1mU2z@?yic*hch_q<-j#^Ad9jqyB-F>Cu|=Elxt0Gt&4R!G4b6&uZju>?9&r6$5o~$(5tt_;iK@7}9{}TL*cWQ1<>WpPU=j=q zj-X<>l{AAqTZ%RDO0!5Gs}Potf!lngU@m{sO2lep7b{g<8#+0ivgmY+mZveBtPj7_ zUULOMg~=oI3{D^PwRtK*ZAegq*y+ajwNCC8xVYwCUva~vL7u@!FEO2QwsH^GG{ZPK zar(MMg@|_qZP#?y4tB6JO?A@aOvpFtYQ7J=Vu@R7C3#<^yGrN^b!7INj0Y;f))j8| z_#zA)1BZjOMn2VQHps;=Ai?p;Dii!oZ0D|>GWP?mj$X(cFwq>W3;16~{ z^9m)Lq|wgvtzhCl&h$R(X2!*^9#161Xm%bCvzXg)fXFOIV^(o~-vmx3u*&lM6#twt zI87(8lC!0Ey2Uyqhz>E5fR58L(ZJc4ozfBQn%=}d)787{avIH$^Q;6sf7rE}>oviD zalcuFKXy^;s1?lvdcvm|S{u$DW?6`(=N!*TMN}O`fIjzGCY-3kOvn1m+Pj#;JcWDu zI*Ytx{=cjW-S%fzZA6u4v3KM6sDk{$bG@U`Y>#VYF||vgjO%otx7BgWEN6zX7V&&yCqZ^t z&$VLt#oCAJ99QP}L~gzN95O@S4jElb^RI-CGk=1Qt4I9Z`MC!xX$`r#CxiB@DTkYT fwupma;OAO results/$(subst .,,$(subst /,_,$@)).txt 2> results/$(subst .,,$(subst /,_,$@)).warning && echo "success" > results/$(subst .,,$(subst /,_,$@)).result) || echo "failure" > results/$(subst .,,$(subst /,_,$@)).result - echo $(shell basename $(realpath $(lastword $@))).bin > results/$(subst .,,$(subst /,_,$@)).stat - sha1sum $@/$(shell basename $(realpath $(lastword $@))).bin | cut -d' ' -f 1 >> results/$(subst .,,$(subst /,_,$@)).stat - wc --bytes $@/$(shell basename $(realpath $(lastword $@))).bin | cut -d' ' -f 1 >> results/$(subst .,,$(subst /,_,$@)).stat - -tests : $(EXAMPLES) - -ci : install tests - -clean : - rm -rf results -