From 7e0b1e3244228576d1f74df7543e67c8f49a5910 Mon Sep 17 00:00:00 2001 From: jake-g00dwin Date: Tue, 23 Dec 2025 14:33:54 -0800 Subject: [PATCH] Refactored the included files from the ch32fun project. + updated as of 2025-12-23 --- inc/ch32fun.h | 1493 +- inc/ch32h41xhw.h | 18083 +++++++ inc/ch32l103hw.h | 9094 ++++ inc/ch32v003hw.h | 6484 ++- inc/ch32v10xhw.h | 6237 +++ inc/ch32v20xhw.h | 8450 +++ inc/ch32v30xhw.h | 10625 ++++ inc/ch32x00xhw.h | 5002 ++ inc/ch32x03xhw.h | 6245 +++ inc/ch5xxhw.h | 2645 + inc/ch641hw.h | 5187 ++ inc/extralibs/ch32v003_GPIO_branchless.h | 504 +- inc/extralibs/ch32v003_SPI.h | 402 +- inc/extralibs/ch32v003_touch.h | 276 +- inc/extralibs/ch32v208_eth.h | 944 + inc/extralibs/ch32v307gigabit.h | 796 +- inc/extralibs/font_8x8.h | 5118 +- inc/extralibs/fsusb.c | 1036 + inc/extralibs/fsusb.h | 419 + inc/extralibs/hsusb.c | 1022 + inc/extralibs/hsusb.h | 475 + inc/extralibs/hsusb_v30x.c | 1036 +- inc/extralibs/hsusb_v30x.h | 77 +- inc/extralibs/iSLER.h | 852 + inc/extralibs/lib_crc.h | 36 + inc/extralibs/lib_pvd.h | 26 + inc/extralibs/lib_rand.h | 172 +- inc/extralibs/register_debug_utilities.h | 142 + inc/extralibs/rtc_helper.h | 127 + inc/extralibs/ssd1306.h | 760 +- inc/extralibs/ssd1306_i2c.h | 456 +- inc/extralibs/ssd1306_i2c_bitbang.h | 179 +- inc/extralibs/ssd1306_spi.h | 148 +- inc/extralibs/static_i2c.h | 203 + inc/extralibs/usb_defines.h | 3040 +- inc/extralibs/ws2812b_dma_spi_led_driver.h | 452 +- inc/extralibs/ws2812b_simple.h | 83 +- inc/misc/attic/.clang-format | 5 - .../ch5xx_blobs_for_minichlink/build_blink.sh | 5 + .../build_verify.sh | 5 + .../build_write_block.sh | 5 + .../ch5xx_blink.asm | 23 + .../ch5xx_verify.asm | 10 + .../ch5xx_write_block.asm | 116 + inc/misc/attic/hardware_header_all_combined.h | 517 +- inc/misc/attic/temp_transition_helper.c | 398 +- .../drivers_for_WCH-LinkE/R0-1v3/README.txt | 11 + .../R0-1v3/WCH-Link_(Interface_0).cat | Bin 0 -> 5072 bytes .../R0-1v3/WCH-Link_(Interface_0).inf | Bin 0 -> 4858 bytes inc/misc/dumped_libgcc.S | 44121 ---------------- inc/misc/install_xpack_gcc.ps1 | 190 + inc/misc/minichlink-live/README.md | 37 + inc/misc/minichlink-live/batch_read.sh | 64 + inc/misc/minichlink-live/plot.py | 102 + inc/misc/minichlink-live/read.sh | 43 + inc/misc/minichlink-live/write.sh | 41 + inc/misc/tests/Makefile | 23 + src/ch32fun.c | 2757 +- 58 files changed, 90369 insertions(+), 56430 deletions(-) create mode 100644 inc/ch32h41xhw.h create mode 100644 inc/ch32l103hw.h create mode 100644 inc/ch32v10xhw.h create mode 100644 inc/ch32v20xhw.h create mode 100644 inc/ch32v30xhw.h create mode 100644 inc/ch32x00xhw.h create mode 100644 inc/ch32x03xhw.h create mode 100644 inc/ch5xxhw.h create mode 100644 inc/ch641hw.h create mode 100644 inc/extralibs/ch32v208_eth.h create mode 100644 inc/extralibs/fsusb.c create mode 100644 inc/extralibs/fsusb.h create mode 100644 inc/extralibs/hsusb.c create mode 100644 inc/extralibs/hsusb.h create mode 100644 inc/extralibs/iSLER.h create mode 100644 inc/extralibs/lib_crc.h create mode 100644 inc/extralibs/lib_pvd.h create mode 100644 inc/extralibs/register_debug_utilities.h create mode 100644 inc/extralibs/rtc_helper.h create mode 100644 inc/extralibs/static_i2c.h delete mode 100644 inc/misc/attic/.clang-format create mode 100755 inc/misc/attic/ch5xx_blobs_for_minichlink/build_blink.sh create mode 100755 inc/misc/attic/ch5xx_blobs_for_minichlink/build_verify.sh create mode 100755 inc/misc/attic/ch5xx_blobs_for_minichlink/build_write_block.sh create mode 100644 inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_blink.asm create mode 100644 inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_verify.asm create mode 100644 inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_write_block.asm create mode 100644 inc/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt create mode 100644 inc/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).cat create mode 100644 inc/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).inf delete mode 100644 inc/misc/dumped_libgcc.S create mode 100644 inc/misc/install_xpack_gcc.ps1 create mode 100644 inc/misc/minichlink-live/README.md create mode 100755 inc/misc/minichlink-live/batch_read.sh create mode 100755 inc/misc/minichlink-live/plot.py create mode 100755 inc/misc/minichlink-live/read.sh create mode 100755 inc/misc/minichlink-live/write.sh create mode 100644 inc/misc/tests/Makefile diff --git a/inc/ch32fun.h b/inc/ch32fun.h index e44018d..d1a0ba5 100644 --- a/inc/ch32fun.h +++ b/inc/ch32fun.h @@ -7,45 +7,45 @@ #include "funconfig.h" /***************************************************************************** - CH32V003 BASICS + CH32V003 BASICS - 1. Be sure to see configuration section below! + 1. Be sure to see configuration section below! - 2. Backend Initialization - SystemInit(); + 2. Backend Initialization + SystemInit(); - 3. Arduino-like I/O - funGpioInitAll(); - funPinMode( PA2, GPIO_CFGLR_OUT_10Mhz_PP ); - funDigitalWrite( PA2, FUN_HIGH ); - funDigitalWrite( PA2, FUN_LOW ); - funAnalogRead( 0 ); // Not Pin number, but rather analog number. + 3. Arduino-like I/O + funGpioInitAll(); + funPinMode( PA2, GPIO_CFGLR_OUT_10Mhz_PP ); + funDigitalWrite( PA2, FUN_HIGH ); + funDigitalWrite( PA2, FUN_LOW ); + funAnalogRead( 0 ); // Not Pin number, but rather analog number. - 4. Delays - Delay_Us(n) - Delay_Ms(n) - DelaySysTick( uint32_t n ); + 4. Delays + Delay_Us(n) + Delay_Ms(n) + DelaySysTick( uint32_t n ); - 5. printf - printf, _write may be semihosted, or printed to UART. + 5. printf + printf, _write may be semihosted, or printed to UART. - poll_input, handle_debug_input may be used with semihsoting to accept input from host. + poll_input, handle_debug_input may be used with semihsoting to accept input from host. - For UART printf, on: - CH32V003, Port D5, 115200 8n1 - CH32V203, Port A9, 115200 8n1 + For UART printf, on: + CH32V003, Port D5, 115200 8n1 + CH32V203, Port A9, 115200 8n1 - Modifications can be made to SetupUart, or your own version as desired. + Modifications can be made to SetupUart, or your own version as desired. 6. ISR Control Routines - __enable_irq(); // For global interrupt enable - __disable_irq(); // For global interrupt disable - __isenabled_irq(); // For seeing if interrupts are enabled. - NVIC_EnableIRQ(IRQn_Type IRQn) // To enable a specific interrupt + __enable_irq(); // For global interrupt enable + __disable_irq(); // For global interrupt disable + __isenabled_irq(); // For seeing if interrupts are enabled. + NVIC_EnableIRQ(IRQn_Type IRQn) // To enable a specific interrupt - 7. Hardware MMIO structs, i.e. - SysTick->CNT = current system tick counter (can be Hclk or Hclk/8) - TIM2->CH1CVR = direct control over a PWM output + 7. Hardware MMIO structs, i.e. + SysTick->CNT = current system tick counter (can be Hclk or Hclk/8) + TIM2->CH1CVR = direct control over a PWM output 8. Default debug behavior, when semihosting: a. You get access to DidDebuggerAttach() - so you can see if a debugger has attached. @@ -59,10 +59,12 @@ by setting FUNCONF_DEBUG_HARDFAULT to 0. */ + + /****************************************************************************** * CH32V003 Fun Configs; please define any non-default options in funconfig.h * -#define FUNCONF_USE_PLL 1 // Use built-in 2x PLL +#define FUNCONF_USE_PLL 1 // Use built-in 2x PLL #define FUNCONF_USE_HSI 1 // Use HSI Internal Oscillator #define FUNCONF_USE_HSE 0 // Use External Oscillator #define FUNCONF_HSITRIM 0x10 // Use factory calibration on HSI Trim. @@ -75,181 +77,228 @@ #define FUNCONF_SYSTICK_USE_HCLK 0 // Should systick be at 48 MHz (1) or 6MHz (0) on an '003. Typically set to 0 to divide HCLK by 8. #define FUNCONF_TINYVECTOR 0 // If enabled, Does not allow normal interrupts. #define FUNCONF_UART_PRINTF_BAUD 115200 // Only used if FUNCONF_USE_UARTPRINTF is set. -#define FUNCONF_DEBUGPRINTF_TIMEOUT 0x80000 // Arbitrary time units, this is around 120ms. -#define FUNCONF_ENABLE_HPE 1 // Enable hardware interrupt stack. Very good on QingKeV4, i.e. x035, v10x, v20x, v30x, but questionable on 003. +#define FUNCONF_DEBUGPRINTF_TIMEOUT 0x100000 // Arbitrary time units, this is around 200ms. +#define FUNCONF_ENABLE_HPE 1 // Enable hardware interrupt stack. Very good on QingKeV4, i.e. x035, v10x, v20x, v30x, but questionable on 003. // If you are using that, consider using INTERRUPT_DECORATOR as an attribute to your interrupt handlers. #define FUNCONF_USE_5V_VDD 0 // Enable this if you plan to use your part at 5V - affects USB and PD configration on the x035. #define FUNCONF_DEBUG_HARDFAULT 1 // Log fatal errors with "printf" +#define FUNCONF_ISR_IN_RAM 0 // Put the interrupt vector in RAM. +#define FUNCONF_SUPPORT_CONSTRUCTORS 0 // Call functions with __attribute__((constructor)) in SystemInit() +#define FUNCONF_ICACHE_EN 1 // Enables ICache on cores that support it, may require power-down + power up to work properly at flash time. */ // Sanity check for when porting old code. -#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) -#if defined(CH32V003) -#error Cannot define CH32V003 and another arch. -#endif +#if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) || defined(CH32L103) || defined(CH32H41x) + #if defined(CH32V003) + #error Cannot define CH32V003 and another arch. + #endif #endif #if !defined(FUNCONF_USE_DEBUGPRINTF) && !defined(FUNCONF_USE_UARTPRINTF) -#define FUNCONF_USE_DEBUGPRINTF 1 + #define FUNCONF_USE_DEBUGPRINTF 1 #endif #if defined(FUNCONF_USE_UARTPRINTF) && FUNCONF_USE_UARTPRINTF && !defined(FUNCONF_UART_PRINTF_BAUD) -#define FUNCONF_UART_PRINTF_BAUD 115200 + #define FUNCONF_UART_PRINTF_BAUD 115200 #endif #if defined(FUNCONF_USE_DEBUGPRINTF) && FUNCONF_USE_DEBUGPRINTF && !defined(FUNCONF_DEBUGPRINTF_TIMEOUT) -#define FUNCONF_DEBUGPRINTF_TIMEOUT 0x80000 + #define FUNCONF_DEBUGPRINTF_TIMEOUT 0x100000 #endif #if defined(FUNCONF_USE_HSI) && defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSI && FUNCONF_USE_HSE -#error FUNCONF_USE_HSI and FUNCONF_USE_HSE cannot both be set + #error FUNCONF_USE_HSI and FUNCONF_USE_HSE cannot both be set #endif -#if !defined(FUNCONF_USE_HSI) && !defined(FUNCONF_USE_HSE) -#define FUNCONF_USE_HSI 1 // Default to use HSI -#define FUNCONF_USE_HSE 0 +#if !defined( FUNCONF_USE_HSI ) && !defined( FUNCONF_USE_HSE ) + #define FUNCONF_USE_HSI 1 // Default to use HSI + #define FUNCONF_USE_HSE 0 #endif -#if defined(CH32X03x) && FUNCONF_USE_HSE -#error No HSE in CH32X03x +#if defined( CH32X03x ) && FUNCONF_USE_HSE + #error No HSE in CH32X03x #endif -#if !defined(FUNCONF_USE_PLL) -#if defined(CH32X03x) -#define FUNCONF_USE_PLL 0 // No PLL on X03x -#else -#define FUNCONF_USE_PLL 1 // Default to use PLL -#endif +#if !defined( FUNCONF_USE_PLL ) + #if defined( CH32X03x ) + #define FUNCONF_USE_PLL 0 // No PLL on X03x + #else + #define FUNCONF_USE_PLL 1 // Default to use PLL + #endif #endif -#if !defined(FUNCONF_DEBUG_HARDFAULT) -#define FUNCONF_DEBUG_HARDFAULT 1 +#if !defined( FUNCONF_DEBUG_HARDFAULT ) + #define FUNCONF_DEBUG_HARDFAULT 1 #endif -#if defined(CH32X03x) && FUNCONF_USE_PLL -#error No PLL on the X03x +#if defined( CH32X03x ) && FUNCONF_USE_PLL + #error No PLL on the X03x #endif #ifndef FUNCONF_ENABLE_HPE -#define FUNCONF_ENABLE_HPE 0 + #define FUNCONF_ENABLE_HPE 0 #endif #if FUNCONF_ENABLE_HPE == 1 -#define INTERRUPT_DECORATOR __attribute__((interrupt("WCH-Interrupt-fast"))) + #define INTERRUPT_DECORATOR __attribute__((interrupt("WCH-Interrupt-fast"))) #else -#define INTERRUPT_DECORATOR __attribute__((interrupt)) + #define INTERRUPT_DECORATOR __attribute__((interrupt)) #endif -#if !defined(FUNCONF_USE_CLK_SEC) -#define FUNCONF_USE_CLK_SEC 1 // use clock security system by default + +#if !defined( FUNCONF_USE_CLK_SEC ) + #define FUNCONF_USE_CLK_SEC 1// use clock security system by default #endif #ifndef HSE_VALUE -#if defined(CH32V003) -#define HSE_VALUE (24000000) // Value of the External oscillator in Hz, default -#elif defined(CH32V10x) -#define HSE_VALUE (8000000) -#elif defined(CH32V20x) -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -#define HSE_VALUE (32000000) -#else -#define HSE_VALUE (8000000) -#endif -#elif defined(CH32V30x) -#define HSE_VALUE (8000000) -#endif + #if defined(CH32V003) + #define HSE_VALUE (24000000) // Value of the External oscillator in Hz, default + #elif defined(CH32V10x) + #define HSE_VALUE (8000000) + #elif defined(CH32V20x) || defined(CH32L103) + #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define HSE_VALUE (32000000) + #else + #define HSE_VALUE (8000000) + #endif + #elif defined(CH32V30x) + #define HSE_VALUE (8000000) + #elif defined(CH57x) || defined(CH58x) || defined(CH59x) + #define HSE_VALUE (32000000) + #elif defined(CH32H41x) + #define HSE_VALUE (25000000) + #endif #endif +// Value of the Internal oscillator in Hz, default. #ifndef HSI_VALUE -#if defined(CH32V003) -#define HSI_VALUE (24000000) // Value of the Internal oscillator in Hz, default. -#elif defined(CH32X03x) -#define HSI_VALUE (48000000) -#elif defined(CH32V10x) -#define HSI_VALUE (8000000) -#elif defined(CH32V20x) -#define HSI_VALUE (8000000) -#elif defined(CH32V30x) -#define HSI_VALUE (8000000) -#endif + #if defined(CH32V003) || defined(CH32V00x) + #define HSI_VALUE (24000000) + #elif defined(CH32X03x) + #define HSI_VALUE (48000000) + #elif defined(CH32V10x) + #define HSI_VALUE (8000000) + #elif defined(CH32V20x) || defined(CH32L103) + #define HSI_VALUE (8000000) + #elif defined(CH32V30x) + #define HSI_VALUE (8000000) + #elif defined(CH32H41x) + #define HSI_VALUE (25000000) + #endif #endif #ifndef FUNCONF_HSITRIM -#define FUNCONF_HSITRIM 0x10 // Default (Chip default) + #define FUNCONF_HSITRIM 0x10 // Default (Chip default) #endif #ifndef FUNCONF_USE_PLL -#define FUNCONF_USE_PLL 1 // Default, Use PLL. + #define FUNCONF_USE_PLL 1 // Default, Use PLL. #endif -#if !defined(FUNCONF_PLL_MULTIPLIER) -#if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL -#if defined(CH32V10x) -#define FUNCONF_PLL_MULTIPLIER 10 // Default: 8 * 10 = 80 MHz -#elif defined(CH32V20x) -#define FUNCONF_PLL_MULTIPLIER 18 // Default: 8 * 18 = 144 MHz -#elif defined(CH32V30x) -#define FUNCONF_PLL_MULTIPLIER 18 // Default: 8 * 18 = 144 MHz -#else // CH32V003 -#define FUNCONF_PLL_MULTIPLIER 2 // Default: 24 * 2 = 48 MHz -#endif -#else -#define FUNCONF_PLL_MULTIPLIER 1 -#endif +#if !defined( FUNCONF_PLL_MULTIPLIER ) + #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL + #if defined(CH32V10x) + #define FUNCONF_PLL_MULTIPLIER 10 // Default: 8 * 10 = 80 MHz + #elif defined(CH32L103) + #define FUNCONF_PLL_MULTIPLIER 12 // Default: 8 * 12 = 96 MHz + // Note: Can be overclocked to 144 MHz + #elif defined(CH32V20x) + #define FUNCONF_PLL_MULTIPLIER 18 // Default: 8 * 18 = 144 MHz + #elif defined(CH32V30x) + #define FUNCONF_PLL_MULTIPLIER 18 // Default: 8 * 18 = 144 MHz + #elif defined(CH32H41x) + #define FUNCONF_PLL_MULTIPLIER 16 // Default: 25 * 16 = 400 MHz + #else // CH32V003 + #define FUNCONF_PLL_MULTIPLIER 2 // Default: 24 * 2 = 48 MHz + #endif + #else + #define FUNCONF_PLL_MULTIPLIER 1 + #endif #endif #ifndef FUNCONF_SYSTEM_CORE_CLOCK -#if defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI -#define FUNCONF_SYSTEM_CORE_CLOCK ((HSI_VALUE) * (FUNCONF_PLL_MULTIPLIER)) -#elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE -#define FUNCONF_SYSTEM_CORE_CLOCK ((HSE_VALUE) * (FUNCONF_PLL_MULTIPLIER)) -#else -#error Must define either FUNCONF_USE_HSI or FUNCONF_USE_HSE to be 1. -#endif + #if defined(CH57x) || defined(CH58x) || defined(CH59x) // no PLL multiplier, but a divider from the 480 MHz clock + #define FUNCONF_SYSTEM_CORE_CLOCK 60000000 // default in ch32fun.c using CLK_SOURCE_PLL_60MHz + #if defined(CLK_SOURCE_CH5XX) + #error Must define FUNCONF_SYSTEM_CORE_CLOCK too if CLK_SOURCE_CH5XX is defined + #endif + #elif defined(CH32H41x) + #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL + #if defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSI_VALUE / 4)*(FUNCONF_PLL_MULTIPLIER)) + #elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSE_VALUE / 4)*(FUNCONF_PLL_MULTIPLIER)) + #endif + #else + #if defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSI_VALUE)*(FUNCONF_PLL_MULTIPLIER)) + #elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSE_VALUE)*(FUNCONF_PLL_MULTIPLIER)) + #endif + #endif + #elif defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSI_VALUE)*(FUNCONF_PLL_MULTIPLIER)) + #elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE + #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSE_VALUE/4)*(FUNCONF_PLL_MULTIPLIER)) + #else + #define FUNCONF_SYSTEM_CORE_CLOCK ((HSE_VALUE)*(FUNCONF_PLL_MULTIPLIER)) + #endif + #else + #error Must define either FUNCONF_USE_HSI or FUNCONF_USE_HSE to be 1. + #endif #endif #ifndef FUNCONF_USE_5V_VDD -#define FUNCONF_USE_5V_VDD 0 + #define FUNCONF_USE_5V_VDD 0 +#endif + +#ifndef FUNCONF_ISR_IN_RAM + #define FUNCONF_ISR_IN_RAM 0 +#endif + +#ifndef FUNCONF_ICACHE_EN + #define FUNCONF_ICACHE_EN 1 #endif // Default package for CH32V20x #if defined(CH32V20x) #if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6) -#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 */ -// #define CH32V20x_D8 /* CH32V203RBT6 */ -// #define CH32V20x_D8W /* CH32V208 */ -#endif + #define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 */ + //#define CH32V20x_D8 /* CH32V203RBT6 */ + //#define CH32V20x_D8W /* CH32V208 */ + #endif #endif // Default package for CH32V30x #if defined(CH32V30x) #if !defined(CH32V30x_D8) && !defined(CH32V30x_D8C) -// #define CH32V30x_D8 /* CH32V303x */ -#define CH32V30x_D8C /* CH32V307x-CH32V305x */ -#endif + //#define CH32V30x_D8 /* CH32V303x */ + #define CH32V30x_D8C /* CH32V307x-CH32V305x */ + #endif #endif ///////////////////////////////////////////////////////////////////////////////////////////////// // Legacy, for EVT, CMSIS -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#ifndef __ASSEMBLER__ // Things before this can be used in assembly. +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. #include #ifdef __cplusplus -#define __I volatile /*!< defines 'read only' permissions */ + #define __I volatile /*!< defines 'read only' permissions */ #else -#define __I volatile const /*!< defines 'read only' permissions */ + #define __I volatile const /*!< defines 'read only' permissions */ #endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ #endif // __ASSEMBLER__ - -/////////////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////// // Code in this section was originally from __CORE_RISCV_H__ @@ -258,524 +307,513 @@ /* define compiler specific symbols */ #if defined(__CC_ARM) -#define __ASM __asm /*!< asm keyword for ARM Compiler */ -#define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #elif defined(__ICCARM__) -#define __ASM __asm /*!< asm keyword for IAR Compiler */ -#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined(__GNUC__) -#define __ASM __asm /*!< asm keyword for GNU Compiler */ -#define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined(__TASKING__) -#define __ASM __asm /*!< asm keyword for TASKING Compiler */ -#define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #endif +#ifndef WEAK +#define WEAK __attribute__((weak)) +#endif + #ifdef __cplusplus -extern "C" -{ + extern "C" { #endif - + #ifndef __ASSEMBLER__ - /* Standard Peripheral Library old types (maintained for legacy purpose) */ - typedef __I uint32_t vuc32; /* Read Only */ - typedef __I uint16_t vuc16; /* Read Only */ - typedef __I uint8_t vuc8; /* Read Only */ +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ - typedef const uint32_t uc32; /* Read Only */ - typedef const uint16_t uc16; /* Read Only */ - typedef const uint8_t uc8; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ - typedef __I int32_t vsc32; /* Read Only */ - typedef __I int16_t vsc16; /* Read Only */ - typedef __I int8_t vsc8; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ - typedef const int32_t sc32; /* Read Only */ - typedef const int16_t sc16; /* Read Only */ - typedef const int8_t sc8; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ - typedef __IO uint32_t vu32; - typedef __IO uint16_t vu16; - typedef __IO uint8_t vu8; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; - typedef uint32_t u32; - typedef uint16_t u16; - typedef uint8_t u8; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; - typedef __IO int32_t vs32; - typedef __IO int16_t vs16; - typedef __IO int8_t vs8; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; - typedef int32_t s32; - typedef int16_t s16; - typedef int8_t s8; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; - typedef __I uint64_t vuc64; /* Read Only */ - typedef const uint64_t uc64; /* Read Only */ - typedef __I int64_t vsc64; /* Read Only */ - typedef const int64_t sc64; /* Read Only */ - typedef __IO uint64_t vu64; - typedef uint64_t u64; - typedef __IO int64_t vs64; - typedef int64_t s64; +typedef __I uint64_t vuc64; /* Read Only */ +typedef const uint64_t uc64; /* Read Only */ +typedef __I int64_t vsc64; /* Read Only */ +typedef const int64_t sc64; /* Read Only */ +typedef __IO uint64_t vu64; +typedef uint64_t u64; +typedef __IO int64_t vs64; +typedef int64_t s64; - typedef enum - { - NoREADY = 0, - READY = !NoREADY - } ErrorStatus; +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - typedef enum - { - DISABLE = 0, - ENABLE = !DISABLE - } FunctionalState; +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - typedef enum - { - RESET = 0, - SET = !RESET - } FlagStatus, ITStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; -#define RV_STATIC_INLINE static inline -#endif // __ASSEMBLER__ +#define RV_STATIC_INLINE static inline + +#include // for memcpy in ch5xx hw.h files +#endif // ifndef __ASSEMBLER__ + +#if FUNCONF_ISR_IN_RAM + #define VECTOR_HANDLER_SECTION ".data.vector_handler" + #define ISR_HANDLER_INITIAL_JUMP ".word 0x00000000\n" +#else + #define VECTOR_HANDLER_SECTION ".text.vector_handler" + #define ISR_HANDLER_INITIAL_JUMP "j handle_reset\n" +#endif #ifdef CH32V003 -#include "ch32v003hw.h" -#elif defined(CH32X03x) -#include "ch32x03xhw.h" -#elif defined(CH32X03x) -#include "ch32x03xhw.h" -#elif defined(CH32V10x) -#include "ch32v10xhw.h" -#elif defined(CH32V20x) -#include "ch32v20xhw.h" -#elif defined(CH32V30x) -#include "ch32v30xhw.h" + #include "ch32v003hw.h" +#elif defined( CH32V002 ) || defined( CH32V00x ) + #include "ch32x00xhw.h" +#elif defined( CH32X03x ) + #include "ch32x03xhw.h" +#elif defined( CH32X03x ) + #include "ch32x03xhw.h" +#elif defined( CH32V10x ) + #include "ch32v10xhw.h" +#elif defined( CH32L103 ) + #include "ch32l103hw.h" +#elif defined( CH32V20x ) + #include "ch32v20xhw.h" +#elif defined( CH32V30x ) + #include "ch32v30xhw.h" +#elif defined( CH57x ) || defined( CH58x ) || defined( CH59x ) + #include "ch5xxhw.h" +#elif defined( CH32H41x ) + #include "ch32h41xhw.h" #endif -#if defined(__riscv) || defined(__riscv__) || defined(CH32V003FUN_BASE) +#if defined(__riscv) || defined(__riscv__) || defined( CH32V003FUN_BASE ) #if __GNUC__ > 10 -#define ADD_ARCH_ZICSR ".option arch, +zicsr\n" + #define ADD_ARCH_ZICSR ".option arch, +zicsr\n" #else -#define ADD_ARCH_ZICSR + #define ADD_ARCH_ZICSR #endif #ifndef __ASSEMBLER__ - // Enable Global Interrupt - RV_STATIC_INLINE void __enable_irq() - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mstatus" : "=r"(result)); - result |= 0x88; - __ASM volatile(ADD_ARCH_ZICSR "csrw mstatus, %0" : : "r"(result)); - } +// Enable Global Interrupt +RV_STATIC_INLINE void __enable_irq() +{ + uint32_t result; __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mstatus": "=r"(result) ); + result |= 0x88; __ASM volatile( ADD_ARCH_ZICSR "csrw mstatus, %0" : : "r" (result) ); +} - // Disable Global Interrupt - RV_STATIC_INLINE void __disable_irq() - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mstatus" : "=r"(result)); - result &= ~0x88; - __ASM volatile(ADD_ARCH_ZICSR "csrw mstatus, %0" : : "r"(result)); - } +// Disable Global Interrupt +RV_STATIC_INLINE void __disable_irq() +{ + uint32_t result; __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mstatus": "=r"(result) ); + result &= ~0x88; __ASM volatile( ADD_ARCH_ZICSR "csrw mstatus, %0" : : "r" (result) ); +} - // Is Global Interrupt enabled (1 = yes, 0 = no) - RV_STATIC_INLINE uint8_t __isenabled_irq(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mstatus" : "=r"(result)); - return (result & 0x08) != 0u; - } +// Is Global Interrupt enabled (1 = yes, 0 = no) +RV_STATIC_INLINE uint8_t __isenabled_irq(void) +{ + uint32_t result; __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mstatus": "=r"(result) ); + return (result & 0x08) != 0u; +} - // Get stack pointer (returns the stack pointer) - RV_STATIC_INLINE uint32_t __get_cpu_sp(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "mv %0, sp" : "=r"(result)); - return result; - } +// Get stack pointer (returns the stack pointer) +RV_STATIC_INLINE uint32_t __get_cpu_sp(void) +{ + uint32_t result; __ASM volatile( ADD_ARCH_ZICSR "mv %0, sp" : "=r"(result)); + return result; +} - // nop - RV_STATIC_INLINE void __NOP() - { - __ASM volatile("nop"); - } +// nop +RV_STATIC_INLINE void __NOP() +{ + __ASM volatile( "nop" ); +} - // Enable Interrupt (by interrupt number) - RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) - { - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); - } +// Enable Interrupt (by interrupt number) +RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} - // Disable Interrupt (by interrupt number) - RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) - { - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); - } +// Disable Interrupt (by interrupt number) +RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} - // Get Interrupt Enable State, (by number), 1 = Triggered 0 = Not triggered - RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) - { - return ((uint32_t)((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); - } +// Get Interrupt Enable State, (by number), 1 = Triggered 0 = Not triggered +RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} - // Get Interrupt Pending State, (by number), 1 = Pending 0 = Not pending - RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) - { - return ((uint32_t)((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); - } +// Get Interrupt Pending State, (by number), 1 = Pending 0 = Not pending +RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} - // "current number break hang" - RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) - { - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); - } +// "current number break hang" +RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} - // Clear Interrupt Pending - RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) - { - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); - } +// Clear Interrupt Pending +RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} - // Get Interrupt Active State (returns 1 if active) - RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) - { - return ((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); - } +// Get Interrupt Active State (returns 1 if active) +RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} - // Set Interrupt Priority (priority: bit7: pre-emption priority, bit6: subpriority, bit[5-0]: reserved - RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) - { - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; - } +// Set Interrupt Priority (priority: bit7: pre-emption priority, bit6: subpriority, bit[5-0]: reserved +RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} - /********************************************************************* - * SUSPEND ALL INTERRUPTS EXCEPT - * The following 3 functions serve to suspend all interrupts, except for the one you momentarily need. - * The purpose of this is to not disturb the one interrupt of interest and let it run unimpeded. - * procedure: - * 1. save the enabled IRQs: uint32_t IRQ_backup = NVIC_get_enabled_IRQs(); - * 2. disable all IRQs: NVIC_clear_all_IRQs_except(IRQ_of_interest); - * 3. restore the previously enabled IRQs: NVIC_restore_IRQs(IRQ_backup); - * - * bit layout of the IRQ backup - * bit 0 | 1 | 2 | 3 | 4 | 5 | 6 .. 22 | 23 .. 28 - * IRQn 2 | 3 | 12 | res | 14 | res | 16 .. 31 | 32 .. 38 - * IRQn 2 and 3 aren't actually user-settable (see RM). - * - * Specifying an invalid IRQn_to_keep like 0 will disable all interrupts. - */ +/********************************************************************* + * SUSPEND ALL INTERRUPTS EXCEPT + * The following 3 functions serve to suspend all interrupts, except for the one you momentarily need. + * The purpose of this is to not disturb the one interrupt of interest and let it run unimpeded. + * procedure: + * 1. save the enabled IRQs: uint32_t IRQ_backup = NVIC_get_enabled_IRQs(); + * 2. disable all IRQs: NVIC_clear_all_IRQs_except(IRQ_of_interest); + * 3. restore the previously enabled IRQs: NVIC_restore_IRQs(IRQ_backup); + * + * bit layout of the IRQ backup + * bit 0 | 1 | 2 | 3 | 4 | 5 | 6 .. 22 | 23 .. 28 + * IRQn 2 | 3 | 12 | res | 14 | res | 16 .. 31 | 32 .. 38 + * IRQn 2 and 3 aren't actually user-settable (see RM). + * + * Specifying an invalid IRQn_to_keep like 0 will disable all interrupts. + */ - RV_STATIC_INLINE uint32_t NVIC_get_enabled_IRQs() - { - return (((NVIC->ISR[0] >> 2) & 0b11) | ((NVIC->ISR[0] >> 12) << 2) | ((NVIC->ISR[1] & 0b1111111) << 23)); - } +RV_STATIC_INLINE uint32_t NVIC_get_enabled_IRQs() +{ + return ( ((NVIC->ISR[0] >> 2) & 0b11) | ((NVIC->ISR[0] >> 12) << 2) | ((NVIC->ISR[1] & 0b1111111) << 23) ); +} - RV_STATIC_INLINE void NVIC_clear_all_IRQs_except(uint8_t IRQn_to_keep) - { - if (!(IRQn_to_keep >> 5)) - { // IRQn_to_keep < 32 - NVIC->IRER[0] = (~0) & (~(1 << IRQn_to_keep)); - NVIC->IRER[1] = (~0); - } - else - { - IRQn_to_keep = IRQn_to_keep >> 5; - NVIC->IRER[0] = (~0); - NVIC->IRER[1] = (~0) & (~(1 << IRQn_to_keep)); - } - } +RV_STATIC_INLINE void NVIC_clear_all_IRQs_except(uint8_t IRQn_to_keep) +{ + if (!(IRQn_to_keep >> 5)) { // IRQn_to_keep < 32 + NVIC->IRER[0] = (~0) & (~(1 << IRQn_to_keep)); + NVIC->IRER[1] = (~0); + } + else { + IRQn_to_keep = IRQn_to_keep >> 5; + NVIC->IRER[0] = (~0); + NVIC->IRER[1] = (~0) & (~(1 << IRQn_to_keep)); + } +} - RV_STATIC_INLINE void NVIC_restore_IRQs(uint32_t old_state) - { - NVIC->IENR[0] = (old_state >> 2) << 12; - NVIC->IENR[1] = old_state >> 23; - } +RV_STATIC_INLINE void NVIC_restore_IRQs(uint32_t old_state) +{ + NVIC->IENR[0] = (old_state >> 2) << 12; + NVIC->IENR[1] = old_state >> 23; +} - // WFI - wait for interrupt (like a light sleep) - __attribute__((always_inline)) RV_STATIC_INLINE void __WFI(void) - { - NVIC->SCTLR &= ~(1 << 3); // wfi - __ASM volatile("wfi"); - } +// WFI - wait for interrupt (like a light sleep) +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + __ASM volatile ("wfi"); +} - // WFE - wait for events (more like a deeper sleep) - __attribute__((always_inline)) RV_STATIC_INLINE void __WFE(void) - { - uint32_t t; +// WFE - wait for events (more like a deeper sleep) +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + uint32_t t; - t = NVIC->SCTLR; - NVIC->SCTLR |= (1 << 3) | (1 << 5); // (wfi->wfe)+(__sev) - NVIC->SCTLR = (NVIC->SCTLR & ~(1 << 5)) | (t & (1 << 5)); - __ASM volatile("wfi"); - __ASM volatile("wfi"); - } + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); + __ASM volatile ("wfi"); + __ASM volatile ("wfi"); +} - /********************************************************************* - * @fn SetVTFIRQ - * @brief Set VTF Interrupt - * @param addr - VTF interrupt service function base address. - * IRQn - Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE - * - * @return none - */ - RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) - { - if (num > 1) return; +/********************************************************************* + * @fn SetVTFIRQ + * @brief Set VTF Interrupt + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ + if(num > 1) return ; - if (NewState != DISABLE) - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) | 0x1); - } - else - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) & (~0x1)); - } - } + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else{ + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} - // Initiate a system reset request - RV_STATIC_INLINE void NVIC_SystemReset(void) - { - NVIC->CFGR = NVIC_KEY3 | (1 << 7); - } +// Initiate a system reset request +RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} - // For reading INTSYSCR, for interrupt nesting + hardware stack enable. - static inline uint32_t __get_INTSYSCR(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, 0x804" : "=r"(result)); - return result; - } +// For reading INTSYSCR, for interrupt nesting + hardware stack enable. +static inline uint32_t __get_INTSYSCR(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, 0x804": "=r"(result)); + return result; +} - // For setting INTSYSCR, for interrupt nesting + hardware stack enable. - static inline void __set_INTSYSCR(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw 0x804, %0" : : "r"(value)); - } +// For setting INTSYSCR, for interrupt nesting + hardware stack enable. +static inline void __set_INTSYSCR( uint32_t value ) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw 0x804, %0" : : "r"(value)); +} #if defined(CH32V30x) - // Return the Floating-Point Accrued Exceptions - static inline uint32_t __get_FFLAGS(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "fflags" : "=r"(result)); - return (result); - } +// Return the Floating-Point Accrued Exceptions +static inline uint32_t __get_FFLAGS(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "fflags" : "=r" (result) ); + return (result); +} - // Set the Floating-Point Accrued Exceptions - static inline void __set_FFLAGS(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw fflags, %0" : : "r"(value)); - } +// Set the Floating-Point Accrued Exceptions +static inline void __set_FFLAGS(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw fflags, %0" : : "r" (value) ); +} - // Return the Floating-Point Dynamic Rounding Mode - static inline uint32_t __get_FRM(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "frm" : "=r"(result)); - return (result); - } +// Return the Floating-Point Dynamic Rounding Mode +static inline uint32_t __get_FRM(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "frm" : "=r" (result) ); + return (result); +} - // Set the Floating-Point Dynamic Rounding Mode - static inline void __set_FRM(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw frm, %0" : : "r"(value)); - } +// Set the Floating-Point Dynamic Rounding Mode +static inline void __set_FRM(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw frm, %0" : : "r" (value) ); +} - // Return the Floating-Point Control and Status Register - static inline uint32_t __get_FCSR(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "fcsr" : "=r"(result)); - return (result); - } +// Return the Floating-Point Control and Status Register +static inline uint32_t __get_FCSR(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "fcsr" : "=r" (result) ); + return (result); +} - // Set the Floating-Point Dynamic Rounding Mode - static inline void __set_FCSR(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw fcsr, %0" : : "r"(value)); - } +// Set the Floating-Point Dynamic Rounding Mode +static inline void __set_FCSR(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw fcsr, %0" : : "r" (value) ); +} #endif // CH32V30x - // Return the Machine Status Register (MSTATUS) - static inline uint32_t __get_MSTATUS(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, mstatus" : "=r"(result)); - return (result); - } +// Return the Machine Status Register (MSTATUS) +static inline uint32_t __get_MSTATUS(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, mstatus": "=r"(result) ); + return (result); +} - // Set the Machine Status Register (MSTATUS) - static inline void __set_MSTATUS(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw mstatus, %0" : : "r"(value)); - } +// Set the Machine Status Register (MSTATUS) +static inline void __set_MSTATUS(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw mstatus, %0" : : "r"(value) ); +} - // Return the Machine ISA Register (MISA) - static inline uint32_t __get_MISA(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, misa" : "=r"(result)); - return (result); - } +// Return the Machine ISA Register (MISA) +static inline uint32_t __get_MISA(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, misa" : "=r"(result)); + return (result); +} - // Set the Machine ISA Register (MISA) - static inline void __set_MISA(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw misa, %0" : : "r"(value)); - } +// Set the Machine ISA Register (MISA) +static inline void __set_MISA(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw misa, %0" : : "r"(value)); +} - // Return the Machine Trap-Vector Base-Address Register (MTVEC) - static inline uint32_t __get_MTVEC(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mtvec" : "=r"(result)); - return (result); - } +// Return the Machine Trap-Vector Base-Address Register (MTVEC) +static inline uint32_t __get_MTVEC(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mtvec": "=r"(result)); + return (result); +} - // * @brief Set the Machine Trap-Vector Base-Address Register (MTVEC) - static inline void __set_MTVEC(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw mtvec, %0" ::"r"(value)); - } +// * @brief Set the Machine Trap-Vector Base-Address Register (MTVEC) +static inline void __set_MTVEC(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw mtvec, %0":: "r"(value)); +} - // Return the Machine Seratch Register (MSCRATCH) - static inline uint32_t __get_MSCRATCH(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mscratch" : "=r"(result)); - return (result); - } +// Return the Machine Seratch Register (MSCRATCH) +static inline uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mscratch" : "=r"(result)); + return (result); +} - // Set the Machine Seratch Register (MSRATCH) - static inline void __set_MSCRATCH(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw mscratch, %0" : : "r"(value)); - } +// Set the Machine Seratch Register (MSRATCH) +static inline void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw mscratch, %0" : : "r"(value)); +} - // Return the Machine Exception Program Register (MEPC) - static inline uint32_t __get_MEPC(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mepc" : "=r"(result)); - return (result); - } +// Return the Machine Exception Program Register (MEPC) +static inline uint32_t __get_MEPC(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mepc" : "=r"(result)); + return (result); +} - // Set the Machine Exception Program Register (MEPC) - static inline void __set_MEPC(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw mepc, %0" : : "r"(value)); - } +// Set the Machine Exception Program Register (MEPC) +static inline void __set_MEPC(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw mepc, %0" : : "r"(value)); +} - // Return the Machine Cause Register (MCAUSE) - static inline uint32_t __get_MCAUSE(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mcause" : "=r"(result)); - return (result); - } +// Return the Machine Cause Register (MCAUSE) +static inline uint32_t __get_MCAUSE(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mcause": "=r"(result)); + return (result); +} - // Set the Machine Cause Register (MCAUSE) - static inline void __set_MCAUSE(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw mcause, %0" ::"r"(value)); - } +// Set the Machine Cause Register (MCAUSE) +static inline void __set_MCAUSE(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw mcause, %0":: "r"(value)); +} - // Return the Machine Trap Value Register (MTVAL) - static inline uint32_t __get_MTVAL(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0," - "mtval" : "=r"(result)); - return (result); - } +// Return the Machine Trap Value Register (MTVAL) +static inline uint32_t __get_MTVAL(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0," "mtval" : "=r" (result) ); + return (result); +} - // Set the Machine Trap Value Register (MTVAL) - static inline void __set_MTVAL(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw mtval, %0" : : "r"(value)); - } +// Set the Machine Trap Value Register (MTVAL) +static inline void __set_MTVAL(uint32_t value) +{ + __ASM volatile ( ADD_ARCH_ZICSR "csrw mtval, %0" : : "r" (value) ); +} - // Return Vendor ID Register (MVENDORID) - static inline uint32_t __get_MVENDORID(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, mvendorid" : "=r"(result)); - return (result); - } +// Return Vendor ID Register (MVENDORID) +static inline uint32_t __get_MVENDORID(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, mvendorid": "=r"(result)); + return (result); +} - // Return Machine Architecture ID Register (MARCHID) - static inline uint32_t __get_MARCHID(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, marchid" : "=r"(result)); - return (result); - } +// Return Machine Architecture ID Register (MARCHID) +static inline uint32_t __get_MARCHID(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, marchid": "=r"(result)); + return (result); +} - // Return Machine Implementation ID Register (MIPID) - static inline uint32_t __get_MIMPID(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, mimpid" : "=r"(result)); - return (result); - } +// Return Machine Implementation ID Register (MIPID) +static inline uint32_t __get_MIMPID(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, mimpid": "=r"(result)); + return (result); +} - // Return Hart ID Register MHARTID - static inline uint32_t __get_MHARTID(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, mhartid" : "=r"(result)); - return (result); - } +// Return Hart ID Register MHARTID +static inline uint32_t __get_MHARTID(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, mhartid": "=r"(result)); + return (result); +} + +// Return stack pointer register (SP) +static inline uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile( "mv %0,""sp": "=r"(result):); + return (result); +} #if defined(CH32V003) && CH32V003 - // Return DBGMCU_CR Register value - static inline uint32_t __get_DEBUG_CR(void) - { - uint32_t result; - __ASM volatile(ADD_ARCH_ZICSR "csrr %0, 0x7C0" : "=r"(result)); - return (result); - } +// Return DBGMCU_CR Register value +static inline uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + __ASM volatile( ADD_ARCH_ZICSR "csrr %0, 0x7C0" : "=r" (result) ); + return (result); +} - // Set the DBGMCU_CR Register value - static inline void __set_DEBUG_CR(uint32_t value) - { - __ASM volatile(ADD_ARCH_ZICSR "csrw 0x7C0, %0" : : "r"(value)); - } - // Return stack pointer register (SP) - static inline uint32_t __get_SP(void) - { - uint32_t result; - __ASM volatile("mv %0," - "sp" : "=r"(result) :); - return (result); - } +// Set the DBGMCU_CR Register value +static inline void __set_DEBUG_CR(uint32_t value) +{ + __ASM volatile( ADD_ARCH_ZICSR "csrw 0x7C0, %0" : : "r" (value) ); +} + #endif // CH32V003 #endif // !assembler @@ -783,27 +821,27 @@ extern "C" // _JBTYPE using long long to make sure the alignment is align to 8 byte, // otherwise in rv32imafd, store/restore FPR may mis-align. #define _JBTYPE long long -#if defined(__riscv_abi_rve) -#define _JBLEN ((4 * sizeof(long)) / sizeof(long)) -#elif defined(__riscv_float_abi_double) -#define _JBLEN ((14 * sizeof(long) + 12 * sizeof(double)) / sizeof(long)) -#elif defined(__riscv_float_abi_single) -#define _JBLEN ((14 * sizeof(long) + 12 * sizeof(float)) / sizeof(long)) +#if defined( __riscv_abi_rve ) +#define _JBLEN ((4*sizeof(long))/sizeof(long)) +#elif defined( __riscv_float_abi_double ) +#define _JBLEN ((14*sizeof(long) + 12*sizeof(double))/sizeof(long)) +#elif defined( __riscv_float_abi_single ) +#define _JBLEN ((14*sizeof(long) + 12*sizeof(float))/sizeof(long)) #else -#define _JBLEN ((14 * sizeof(long)) / sizeof(long)) +#define _JBLEN ((14*sizeof(long))/sizeof(long)) #endif #ifndef __ASSEMBLER__ #ifdef _JBLEN #ifdef _JBTYPE - typedef _JBTYPE jmp_buf[_JBLEN]; +typedef _JBTYPE jmp_buf[_JBLEN]; #else - typedef int jmp_buf[_JBLEN]; +typedef int jmp_buf[_JBLEN]; #endif // _JBTYPE #endif // _JBLEN - int setjmp(jmp_buf env); - void longjmp(jmp_buf env, int val); +int setjmp( jmp_buf env ); +void longjmp( jmp_buf env, int val ); #endif #endif // defined(__riscv) || defined(__riscv__) || defined( CH32V003FUN_BASE ) @@ -812,103 +850,137 @@ extern "C" } #endif -#endif /* __CORE_RISCV_H__ */ +#endif/* __CORE_RISCV_H__ */ + /////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////// #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - /* SYSTICK info - * time on the ch32v003 is kept by the SysTick counter (32bit) - * by default, it will operate at (FUNCONF_SYSTEM_CORE_CLOCK / 8) = 6MHz - * more info at https://github.com/cnlohr/ch32v003fun/wiki/Time - */ +/* SYSTICK info + * time on the ch32v003 is kept by the SysTick counter (32bit) + * by default, it will operate at (FUNCONF_SYSTEM_CORE_CLOCK / 8) = 6MHz + * more info at https://github.com/cnlohr/ch32v003fun/wiki/Time +*/ -#if defined(FUNCONF_SYSTICK_USE_HCLK) && FUNCONF_SYSTICK_USE_HCLK && !defined(CH32V10x) -#define DELAY_US_TIME ((FUNCONF_SYSTEM_CORE_CLOCK) / 1000000) -#define DELAY_MS_TIME ((FUNCONF_SYSTEM_CORE_CLOCK) / 1000) +#if defined( FUNCONF_SYSTICK_USE_HCLK ) && FUNCONF_SYSTICK_USE_HCLK && !defined(CH32V10x) +#define DELAY_US_TIME ((FUNCONF_SYSTEM_CORE_CLOCK)/1000000) +#define DELAY_MS_TIME ((FUNCONF_SYSTEM_CORE_CLOCK)/1000) #else // Use systick = hclk/8 -#define DELAY_US_TIME ((FUNCONF_SYSTEM_CORE_CLOCK) / 8000000) -#define DELAY_MS_TIME ((FUNCONF_SYSTEM_CORE_CLOCK) / 8000) +#define DELAY_US_TIME ((FUNCONF_SYSTEM_CORE_CLOCK)/8000000) +#define DELAY_MS_TIME ((FUNCONF_SYSTEM_CORE_CLOCK)/8000) #endif -#define Delay_Us(n) DelaySysTick((n) * DELAY_US_TIME) -#define Delay_Ms(n) DelaySysTick((n) * DELAY_MS_TIME) +#define DELAY_MSEC_COUNT(n) (DELAY_MS_TIME * n) +#define DELAY_SEC_COUNT(n) (DELAY_MS_TIME * 1000 * n) -#define Ticks_from_Us(n) (n * DELAY_US_TIME) -#define Ticks_from_Ms(n) (n * DELAY_MS_TIME) +#define Delay_Us(n) DelaySysTick( (n) * DELAY_US_TIME ) +#define Delay_Ms(n) DelaySysTick( (n) * DELAY_MS_TIME ) + +#define Ticks_from_Us(n) ((n) * DELAY_US_TIME) +#define Ticks_from_Ms(n) ((n) * DELAY_MS_TIME) + +#define TimeElapsed32(now,start) ((uint32_t)((uint32_t)(now)-(uint32_t)(start))) // Add a certain number of nops. Note: These are usually executed in pairs // and take two cycles, so you typically would use 0, 2, 4, etc. -#define ADD_N_NOPS(n) asm volatile(".rept " #n "\nc.nop\n.endr"); - -// Arduino-like GPIO Functionality -#define GpioOf(pin) ((GPIO_TypeDef *)(GPIOA_BASE + 0x400 * ((pin) >> 4))) +#define ADD_N_NOPS( n ) asm volatile( ".rept " #n "\nc.nop\n.endr" ); #define FUN_HIGH 0x1 #define FUN_LOW 0x0 +#if defined(CH57x) || defined(CH58x) || defined(CH59x) +#if defined( PB ) && defined( R32_PB_PIN ) +#define OFFSET_FOR_GPIOB(pin) (((pin & PB) >> 31) * (&R32_PB_PIN - &R32_PA_PIN)) // 0 if GPIOA, 0x20 if GPIOB +#else +#define PB 0 +#define OFFSET_FOR_GPIOB(pin) 0 +#endif +#define GPIO_ResetBits(pin) (*(&R32_PA_CLR + OFFSET_FOR_GPIOB(pin)) = (pin & ~PB)) +#define GPIO_SetBits(pin) (*(&R32_PA_SET + OFFSET_FOR_GPIOB(pin)) = (pin & ~PB)) +#define GPIO_InverseBits(pin) (*(&R32_PA_OUT + OFFSET_FOR_GPIOB(pin)) ^= (pin & ~PB)) +#define GPIO_ReadPortPin(pin) (*(&R32_PA_PIN + OFFSET_FOR_GPIOB(pin)) & (pin & ~PB)) +#define funDigitalRead(pin) GPIO_ReadPortPin(pin) +#define funDigitalWrite( pin, value ) do{ if((value)==FUN_HIGH){GPIO_SetBits(pin);} else if((value)==FUN_LOW){GPIO_ResetBits(pin);} }while(0) +#define funGpioInitAll() // funGpioInitAll() does not do anything on ch5xx, put here for consistency + +RV_STATIC_INLINE void funPinMode(u32 pin, GPIOModeTypeDef mode) +{ + switch(mode) { + case GPIO_ModeIN_Floating: + *(&R32_PA_PD_DRV + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + *(&R32_PA_PU + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + *(&R32_PA_DIR + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + break; + case GPIO_ModeIN_PU: + *(&R32_PA_PD_DRV + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + *(&R32_PA_PU + OFFSET_FOR_GPIOB(pin)) |= (pin & ~PB); + *(&R32_PA_DIR + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + break; + case GPIO_ModeIN_PD: + *(&R32_PA_PD_DRV + OFFSET_FOR_GPIOB(pin)) |= (pin & ~PB); + *(&R32_PA_PU + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + *(&R32_PA_DIR + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + break; + case GPIO_ModeOut_PP_5mA: + *(&R32_PA_PD_DRV + OFFSET_FOR_GPIOB(pin)) &= ~(pin & ~PB); + *(&R32_PA_DIR + OFFSET_FOR_GPIOB(pin)) |= (pin & ~PB); + break; + case GPIO_ModeOut_PP_20mA: + *(&R32_PA_PD_DRV + OFFSET_FOR_GPIOB(pin)) |= (pin & ~PB); + *(&R32_PA_DIR + OFFSET_FOR_GPIOB(pin)) |= (pin & ~PB); + break; + } +} +#else +// Arduino-like GPIO Functionality +#define GpioOf( pin ) ((GPIO_TypeDef *)(GPIOA_BASE + 0x400 * ((pin)>>4))) + #define FUN_OUTPUT (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) #define FUN_INPUT (GPIO_CNF_IN_FLOATING) - // For pins, use things like PA8, PB15 - // For configuration, use things like GPIO_CFGLR_OUT_10Mhz_PP +// For pins, use things like PA8, PB15 +// For configuration, use things like GPIO_CFGLR_OUT_10Mhz_PP -#define funDigitalWrite(pin, value) \ - { \ - GpioOf(pin)->BSHR = 1 << ((!(value)) * 16 + ((pin) & 0xf)); \ - } +#define funDigitalWrite( pin, value ) do{ GpioOf( pin )->BSHR = 1<<((!(value))*16 + ((pin) & 0xf)); }while(0) #if defined(CH32X03x) -#define funGpioInitAll() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC); \ - } -#define funPinMode(pin, mode) \ - { \ - *((&GpioOf(pin)->CFGLR) + ((pin & 0x8) >> 3)) = ((*((&GpioOf(pin)->CFGLR) + ((pin & 0x8) >> 3))) & (~(0xf << (4 * ((pin) & 0x7))))) | ((mode) << (4 * ((pin) & 0x7))); \ - } -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) -#define funGpioInitAll() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD); \ - } -#define funPinMode(pin, mode) \ - { \ - *((&GpioOf(pin)->CFGLR) + ((pin & 0x8) >> 3)) = ((*((&GpioOf(pin)->CFGLR) + ((pin & 0x8) >> 3))) & (~(0xf << (4 * ((pin) & 0x7))))) | ((mode) << (4 * ((pin) & 0x7))); \ - } -#define funGpioInitB() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB); \ - } +#define funGpioInitAll() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC ); } +#define funPinMode( pin, mode ) { *((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3)) = ( (*((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3))) & (~(0xf<<(4*((pin)&0x7))))) | ((mode)<<(4*((pin)&0x7))); } +#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32L103) +#define funGpioInitAll() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD ); } +#define funPinMode( pin, mode ) { *((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3)) = ( (*((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3))) & (~(0xf<<(4*((pin)&0x7))))) | ((mode)<<(4*((pin)&0x7))); } +#define funGpioInitB() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB ); } +#elif defined(CH32H41x) +#define funGpioInitAll() { RCC->HB2PCENR |= ( RCC_HB2Periph_AFIO | RCC_HB2Periph_GPIOA | RCC_HB2Periph_GPIOB | RCC_HB2Periph_GPIOC | RCC_HB2Periph_GPIOD | RCC_HB2Periph_GPIOE | RCC_HB2Periph_GPIOF ); } + +RV_STATIC_INLINE void funPinMode(u32 pin, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed) +{ + *((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3)) = ( (*((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3))) & (~(0xf<<(4*((pin)&0x7))))) | ((mode)<<(4*((pin)&0x7))); + GpioOf(pin)->SPEED = (GpioOf(pin)->SPEED & ~(0x3 << (2 * (pin & 0xF)))) | (speed << (2 * (pin & 0xF))); +} + +/* Helper for AF */ +RV_STATIC_INLINE void funPinAF(u32 pin, u32 af) +{ + volatile uint32_t* afio = (uint32_t*)(AFIO_BASE + 4U + 4U * (pin >> 3)); + *afio = (*afio & ~(0xf << (4U * (pin & 0x7)))) | (af << (4U * (pin & 0x7))); +} + #else -#define funGpioInitAll() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD); \ - } -#define funPinMode(pin, mode) \ - { \ - GpioOf(pin)->CFGLR = (GpioOf(pin)->CFGLR & (~(0xf << (4 * ((pin) & 0xf))))) | ((mode) << (4 * ((pin) & 0xf))); \ - } +#define funGpioInitAll() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD ); } +#define funPinMode( pin, mode ) { GpioOf(pin)->CFGLR = (GpioOf(pin)->CFGLR & (~(0xf<<(4*((pin)&0xf))))) | ((mode)<<(4*((pin)&0xf))); } +#endif + +#define funGpioInitA() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA ); } +#define funGpioInitC() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC ); } +#define funGpioInitD() { RCC->APB2PCENR |= ( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOD ); } +#define funDigitalRead( pin ) ((int)((GpioOf(pin)->INDR >> ((pin)&0xf)) & 1)) #endif -#define funGpioInitA() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA); \ - } -#define funGpioInitC() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC); \ - } -#define funGpioInitD() \ - { \ - RCC->APB2PCENR |= (RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOD); \ - } -#define funDigitalRead(pin) ((int)((GpioOf(pin)->INDR >> ((pin) & 0xf)) & 1)) #define ANALOG_0 0 #define ANALOG_1 1 @@ -925,64 +997,69 @@ extern "C" #ifndef __ASSEMBLER__ -#if defined(__riscv) || defined(__riscv__) || defined(CH32V003FUN_BASE) +#if defined(__riscv) || defined(__riscv__) || defined( CH32V003FUN_BASE ) - // Stuff that can only be compiled on device (not for the programmer, or other host programs) - // Initialize the ADC calibrate it and set some sane defaults. - void funAnalogInit(void); +// Stuff that can only be compiled on device (not for the programmer, or other host programs) - // Read an analog input (not a GPIO pin number) - // Be sure to call funAnalogInit first. - int funAnalogRead(int nAnalogNumber); +// Initialize the ADC calibrate it and set some sane defaults. +void funAnalogInit( void ); - void handle_reset() __attribute__((naked)) __attribute((section(".text.handle_reset"))) __attribute__((used)); - void DefaultIRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute__((naked)) __attribute__((used)); +// Read an analog input (not a GPIO pin number) +// Be sure to call funAnalogInit first. +int funAnalogRead( int nAnalogNumber ); + +void handle_reset() __attribute__((naked)) __attribute((section(".text.handle_reset"))) __attribute__((used)); +void DefaultIRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute__((naked)) __attribute__((used)); // used to clear the CSS flag in case of clock fail switch #if defined(FUNCONF_USE_CLK_SEC) && FUNCONF_USE_CLK_SEC - void NMI_RCC_CSS_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute__((naked)) __attribute__((used)); + void NMI_RCC_CSS_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute__((naked)) __attribute__((used)); #endif - void DelaySysTick(uint32_t n); +void DelaySysTick( uint32_t n ); + // Depending on a LOT of factors, it's about 6 cycles per n. // **DO NOT send it zero or less.** #ifndef __MACOSX__ #ifndef __DELAY_TINY_DEFINED__ #define __DELAY_TINY_DEFINED__ - static inline void Delay_Tiny(int n) - { - __ASM volatile("\ +static inline void Delay_Tiny( int n ) { + __ASM volatile( "\ mv a5, %[n]\n\ 1: \ c.addi a5, -1\n\ - c.bnez a5, 1b" : : [n] "r"(n) : "a5"); - } + c.bnez a5, 1b" : : [n]"r"(n) : "a5" ); +} #endif #endif -#endif // defined(__riscv) || defined(__riscv__) || defined( CH32V003FUN_BASE ) +#endif //defined(__riscv) || defined(__riscv__) || defined( CH32V003FUN_BASE ) - // Tricky: We need to make sure main and SystemInit() are preserved. - int main() __attribute__((used)); - void SystemInit(void); +// Tricky: We need to make sure main and SystemInit() are preserved. +#ifdef MINICHLINK +int main( int argc, char ** argv) __attribute__((used)); +#else +int main() __attribute__((used)); +#endif +void SystemInit(void); #ifdef FUNCONF_UART_PRINTF_BAUD -#define UART_BAUD_RATE FUNCONF_UART_PRINTF_BAUD + #define UART_BAUD_RATE FUNCONF_UART_PRINTF_BAUD #else -#define UART_BAUD_RATE 115200 + #define UART_BAUD_RATE 115200 #endif // Debug UART baud rate register calculation. Works assuming HCLK prescaler is off. // Computes UART_BRR = CORE_CLOCK / BAUD_RATE with rounding to closest integer -#define UART_BRR (((FUNCONF_SYSTEM_CORE_CLOCK) + (UART_BAUD_RATE) / 2) / (UART_BAUD_RATE)) - // Put an output debug UART on Pin D5. - // You can write to this with printf(...) or puts(...) +#define UART_BRR (((FUNCONF_SYSTEM_CORE_CLOCK) + (UART_BAUD_RATE)/2) / (UART_BAUD_RATE)) +// Put an output debug UART on Pin D5. +// You can write to this with printf(...) or puts(...) - void SetupUART(int uartBRR); +void SetupUART( int uartBRR ); - // Returns 1 if timeout reached, 0 otherwise. - // If timeout_ms == 0, wait indefinitely. - // Use DidDebuggerAttach() For a zero-wait way of seeing if it attached. - int WaitForDebuggerToAttach(int timeout_ms); +// Returns 1 if timeout reached, 0 otherwise. +// If timeout_ms == 0, wait indefinitely. +// Use DidDebuggerAttach() For a zero-wait way of seeing if it attached. +int WaitForDebuggerToAttach( int timeout_ms ); // Returns 1 if a debugger has activated the debug module. #define DidDebuggerAttach() (!*DMSTATUS_SENTINEL) @@ -990,63 +1067,73 @@ extern "C" // Returns 1 if a debugger has activated the debug module. #define DebugPrintfBufferFree() (!(*DMDATA0 & 0x80)) - // Just a definition to the internal _write function. - int _write(int fd, const char *buf, int size); +// Just a definition to the internal _write function. +int _write(int fd, const char *buf, int size); - // Call this to busy-wait the polling of input. - void poll_input(void); +// Print a hexadecimal value to the debug (or UART) depending on configuration. +void PrintHex( uint32_t n ); - // Receiving bytes from host. Override if you wish. - void handle_debug_input(int numbytes, uint8_t *data); +// Call this to busy-wait the polling of input. +void poll_input( void ); + +// Receiving bytes from host. Override if you wish. +void handle_debug_input( int numbytes, uint8_t * data ); + +// Call functions with __attribute__((constructor)). Defining FUNCONF_SUPPORT_CONSTRUCTORS 1 will do it for you +void CallConstructors( void ); // Functions from ch32fun.c #include - int mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va); - int mini_vpprintf(int (*puts)(char *s, int len, void *buf), void *buf, const char *fmt, va_list va); - int mini_snprintf(char *buffer, unsigned int buffer_len, const char *fmt, ...); - int mini_pprintf(int (*puts)(char *s, int len, void *buf), void *buf, const char *fmt, ...); +int mini_vsnprintf( char *buffer, unsigned int buffer_len, const char *fmt, va_list va ); +int mini_vpprintf( int (*puts)(char* s, int len, void* buf), void* buf, const char *fmt, va_list va ); +int mini_snprintf(char* buffer, unsigned int buffer_len, const char *fmt, ...); +int mini_pprintf(int (*puts)(char*s, int len, void* buf), void* buf, const char *fmt, ...); +int mini_itoa(long value, unsigned int radix, int uppercase, int unsig, char *buffer); #endif // __ASSEMBLER__ - /* - * This file contains various parts of the official WCH EVT Headers which - * were originally under a restrictive license. - * - * The collection of this file was generated by - * cnlohr, 2023-02-18 and - * AlexanderMandera, 2023-06-23 - * It was significantly reworked into several files cnlohr, 2025-01-29 - * - * While originally under a restrictive copyright, WCH has approved use - * under MIT-licensed use, because of inclusion in Zephyr, as well as other - * open-source licensed projects. - * - * These copies of the headers from WCH are available now under: - * - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the “Softwareâ€), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ #ifdef __cplusplus }; #endif + #endif // __CH32FUN_H + diff --git a/inc/ch32h41xhw.h b/inc/ch32h41xhw.h new file mode 100644 index 0000000..17b87ac --- /dev/null +++ b/inc/ch32h41xhw.h @@ -0,0 +1,18083 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick0_IRQn = 12, /* 12 System timer Interrupt */ + SysTick1_IRQn = 13, /* 13 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + IPC_CH0_IRQn = 16, /* 16 IPC CH0 Interrupt */ + IPC_CH1_IRQn = 17, /* 17 IPC CH1 Interrupt */ + IPC_CH2_IRQn = 18, /* 18 IPC CH2 Interrupt */ + IPC_CH3_IRQn = 19, /* 19 IPC CH3 Interrupt */ + HSEM_IRQn = 28, /* 28 HSEM Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 32, /* Window WatchDog Interrupt */ + EXTI15_8_IRQn = 33, /* External Line[15:8] Interrupts */ + FLASH_IRQn = 34, /* FLASH global Interrupt */ + RCC_IRQn = 35, /* RCC global Interrupt */ + EXTI7_0_IRQn = 36, /* External Line[7:0] Interrupts */ + SPI1_IRQn = 37, /* SPI1 global Interrupt */ + DMA1_Channel2_IRQn = 38, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 39, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 40, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 41, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 42, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 43, /* DMA1 Channel 7 global Interrupt */ + DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ + USART2_IRQn = 45, /* USART2 global Interrupt */ + I2C1_EV_IRQn = 46, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 47, /* I2C1 Error Interrupt */ + USART1_IRQn = 48, /* USART1 global Interrupt */ + SPI2_IRQn = 49, /* SPI2 global Interrupt */ + SPI3_IRQn = 50, /* SPI3 global Interrupt */ + SPI4_IRQn = 51, /* SPI4 global Interrupt */ + I2C2_EV_IRQn = 52, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 53, /* I2C2 Error Interrupt */ + USBPD_IRQn = 54, /* USBPD Interrupt */ + USBPDWakeUp_IRQn = 55, /* USBPD WakeUp Interrupt */ + USBHS_IRQn = 56, /* USBHS global Interrupt */ + DMA1_Channel1_IRQn = 57, /* DMA1 Channel 1 global Interrupt */ + CAN1_SCE_IRQn = 58, /* CAN1 SCE Interrupt */ + CAN1_TX_IRQn = 59, /* CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 60, /* CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 61, /* CAN1 RX1 Interrupts */ + USBSS_IRQn = 62, /* USBSS Interrupt */ + USBSS_LINK_IRQn = 63, /* USBSS LINK Interrupt */ + USBHSWakeup_IRQn = 64, /* USBHS WakeUp Interrupt */ + USBSSWakeup_IRQn = 65, /* USBSS WakeUp Interrupt */ + RTCAlarm_IRQn = 66, /* RTC Alarm through EXTI Line Interrupt */ + USBFS_IRQn = 67, /* USBFS global Interrupt */ + USBFSWakeUp_IRQn = 68, /* USBFS WakeUp Interrupt */ + ADC1_2_IRQn = 69, /* ADC1 and ADC2 global Interrupt */ + TIM1_BRK_IRQn = 70, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 71, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 72, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 73, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 74, /* TIM2 global Interrupt */ + TIM3_IRQn = 75, /* TIM3 global Interrupt */ + TIM4_IRQn = 76, /* TIM4 global Interrupt */ + TIM5_IRQn = 77, /* TIM5 global Interrupt */ + I2C3_EV_IRQn = 78, /* I2C3 Event Interrupt */ + I2C3_ER_IRQn = 79, /* I2C3 Error Interrupt */ + I2C4_EV_IRQn = 80, /* I2C4 Event Interrupt */ + I2C4_ER_IRQn = 81, /* I2C4 Error Interrupt */ + QSPI1_IRQn = 82, /* QSPI1 Interrupt */ + SERDES_IRQn = 83, /* SERDES Interrupt */ + USART3_IRQn = 84, /* USART3 global Interrupt */ + USART4_IRQn = 85, /* USART4 global Interrupt */ + TIM8_BRK_IRQn = 86, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 87, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 88, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 89, /* TIM8 Capture Compare Interrupt */ + TIM9_IRQn = 90, /* TIM9 global Interrupt */ + TIM10_IRQn = 91, /* TIM10 global Interrupt */ + TIM11_IRQn = 92, /* TIM11 global Interrupt */ + TIM12_IRQn = 93, /* TIM12 global Interrupt */ + FMC_IRQn = 94, /* FMC global Interrupt */ + SDMMC_IRQn = 95, /* SDMMC global Interrupt */ + LPTIM1_IRQn = 96, /* LPTIM1 global Interrupt */ + LPTIM2_IRQn = 97, /* LPTIM2 global Interrupt */ + USART5_IRQn = 98, /* USART5 global Interrupt */ + USART6_IRQn = 99, /* USART6 global Interrupt */ + TIM6_IRQn = 100, /* TIM6 global Interrupt */ + TIM7_IRQn = 101, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 102, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 103, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 104, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 105, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 106, /* DMA2 Channel 5 global Interrupt */ + DMA2_Channel6_IRQn = 107, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 108, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 109, /* DMA2 Channel 8 global Interrupt */ + ETH_IRQn = 110, /* ETH global Interrupt */ + ETH_WKUP_IRQn = 111, /* ETH WakeUp Interrupt */ + CAN2_SCE_IRQn = 112, /* CAN2 SCE Interrupt */ + CAN2_TX_IRQn = 113, /* CAN2 TX Interrupts */ + CAN2_RX0_IRQn = 114, /* CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 115, /* CAN2 RX1 Interrupts */ + USART7_IRQn = 116, /* USART7 global Interrupt */ + USART8_IRQn = 117, /* USART8 global Interrupt */ + I3C_EV_IRQn = 118, /* I3C Event Interrupt */ + I3C_ER_IRQn = 119, /* I3C Error Interrupt */ + DVP_IRQn = 120, /* DVP global Interrupt */ + ECDC_IRQn = 121, /* ECDC global Interrupt */ + PIOC_IRQn = 122, /* PIOC global Interrupt */ + SAI_IRQn = 123, /* SAI global Interrupt */ + LTDC_IRQn = 124, /* LTDC global Interrupt */ + GPHA_IRQn = 125, /* GPHA global Interrupt */ + DFSDM0_IRQn = 127, /* DFSDM0 global Interrupt */ + DFSDM1_IRQn = 128, /* DFSDM1 global Interrupt */ + SWPMI_IRQn = 131, /* SWPMI global Interrupt */ + QSPI2_IRQn = 134, /* QSPI2 Interrupt */ + SWPMI_WKUP_IRQn = 135, /* SWPMI WakeUp Interrupt */ + CAN3_SCE_IRQn = 136, /* CAN3 SCE Interrupt */ + CAN3_TX_IRQn = 137, /* CAN3 TX Interrupts */ + CAN3_RX0_IRQn = 138, /* CAN3 RX0 Interrupts */ + CAN3_RX1_IRQn = 139, /* CAN3 RX1 Interrupts */ + LPTIM2_WKUP_IRQn = 140, /* LPTIM2 WakeUp Interrupt */ + LPTIM1_WKUP_IRQn = 141, /* LPTIM1 WakeUp Interrupt */ + I3C_WKUP_IRQn = 142, /* I3C WakeUp Interrupt */ + RTC_IRQn = 143, /* RTC global Interrupt */ + HSADC_IRQn = 144, /* HSADC global Interrupt */ + UHSIF_IRQn = 145, /* UHSIF global Interrupt */ + RNG_IRQn = 146, /* RNG global Interrupt */ + SDIO_IRQn = 147, /* SDIO global Interrupt */ + USART_WKUP_IRQn = 148, /* USART wakeup Interrupt */ +} IRQn_Type; + +#define BASE_VECTOR "\n\ + .balign 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0 \n\ + .word NMI_Handler /* NMI */ \n\ + .word HardFault_Handler /* Hard Fault */ \n\ + .word 0 \n\ + .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\ + .word 0 \n\ + .word 0 \n\ + .word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\ + .word Break_Point_Handler /* Break Point */ \n\ + .word 0 \n\ + .word 0 \n\ + .word SysTick_Handler /* SysTick */ \n \ + .word SysTick_Handler /* SysTick */ \n \ + .word SW_Handler /* SW */ \n \ + .word 0 \n \ + .word IPC_CH0_Handler \n \ + .word IPC_CH1_Handler \n \ + .word IPC_CH2_Handler \n \ + .word IPC_CH3_Handler \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word HSEM_Handler \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + /* External Interrupts */ \n \ + .word WWDG_IRQHandler /* Window Watchdog */ \n \ + .word EXTI15_8_IRQHandler \n \ + .word FLASH_IRQHandler /* Flash */ \n \ + .word RCC_IRQHandler /* RCC */ \n \ + .word EXTI7_0_IRQHandler \n \ + .word SPI1_IRQHandler /* SPI1 */ \n \ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n \ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n \ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n \ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n \ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n \ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n \ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */ \n \ + .word USART2_IRQHandler /* USART2 */ \n \ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n \ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n \ + .word USART1_IRQHandler /* USART1 */ \n \ + .word SPI2_IRQHandler /* SPI2 */ \n \ + .word SPI3_IRQHandler /* SPI3 */ \n \ + .word SPI4_IRQHandler /* SPI4 */ \n \ + .word I2C2_EV_IRQHandler /* I2C2 Event */ \n \ + .word I2C2_ER_IRQHandler /* I2C2 Error */ \n \ + .word USBPD_IRQHandler \n \ + .word USBPDWakeUp_IRQHandler \n \ + .word USBHS_IRQHandler /* USBHS */ \n \ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n \ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n \ + .word CAN1_TX_IRQHandler /* CAN1 TX */ \n \ + .word CAN1_RX0_IRQHandler /* CAN1 RX1 */ \n \ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \n \ + .word USBSS_IRQHandler \n \ + .word USBSS_LINK_IRQHandler \n \ + .word USBHSWakeup_IRQHandler \n \ + .word USBSSWakeup_IRQHandler \n \ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n \ + .word USBFS_IRQHandler /* USBFS */ \n \ + .word USBFSWakeUp_IRQHandler /* USBFS Wakeup */ \n \ + .word ADC1_2_IRQHandler /* ADC1_2 */ \n \ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n \ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n \ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n \ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n \ + .word TIM2_IRQHandler /* TIM2 */ \n \ + .word TIM3_IRQHandler /* TIM3 */ \n \ + .word TIM4_IRQHandler /* TIM4 */ \n \ + .word TIM5_IRQHandler /* TIM5 */ \n \ + .word I2C3_EV_IRQHandler /* I2C3 Event */ \n \ + .word I2C3_ER_IRQHandler /* I2C3 Error */ \n \ + .word I2C4_EV_IRQHandler /* I2C4 Event */ \n \ + .word I2C4_ER_IRQHandler /* I2C4 Error */ \n \ + .word QSPI1_IRQHandler \n \ + .word SERDES_IRQHandler \n \ + .word USART3_IRQHandler /* USART3 */ \n \ + .word USART4_IRQHandler /* USART4 */ \n \ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ \n \ + .word TIM8_UP_IRQHandler /* TIM8 Update */ \n \ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ \n \ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ \n \ + .word TIM9_IRQHandler /* TIM9 */ \n \ + .word TIM10_IRQHandler /* TIM10 */ \n \ + .word TIM11_IRQHandler /* TIM11 */ \n \ + .word TIM12_IRQHandler /* TIM12 */ \n \ + .word FMC_IRQHandler \n \ + .word SDMMC_IRQHandler \n \ + .word LPTIM1_IRQHandler \n \ + .word LPTIM2_IRQHandler \n \ + .word USART5_IRQHandler /* USART5 */ \n \ + .word USART6_IRQHandler /* USART6 */ \n \ + .word TIM6_IRQHandler /* TIM6 */ \n \ + .word TIM7_IRQHandler /* TIM7 */ \n \ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ \n \ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ \n \ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ \n \ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ \n \ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ \n \ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ \n \ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ \n \ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ \n \ + .word ETH_IRQHandler /* ETH */ \n \ + .word ETHWakeUp_IRQHandler /* ETH WakeUp */ \n \ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ \n \ + .word CAN2_TX_IRQHandler /* CAN2 TX */ \n \ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ \n \ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ \n \ + .word USART7_IRQHandler /* USART7 */ \n \ + .word USART8_IRQHandler /* USART8 */ \n \ + .word I3C_EV_IRQHandler /* I3C Event */ \n \ + .word I3C_ER_IRQHandler /* I3C Error */ \n \ + .word DVP_IRQHandler /* DVP */ \n \ + .word ECDC_IRQHandler \n \ + .word PIOC_IRQHandler \n \ + .word SAI_IRQHandler \n \ + .word LTDC_IRQHandler \n \ + .word GPHA_IRQHandler \n \ + .word 0 \n \ + .word DFSDM0_IRQHandler \n \ + .word DFSDM1_IRQHandler \n \ + .word 0 \n \ + .word 0 \n \ + .word SWPMI_IRQHandler \n \ + .word 0 \n \ + .word 0 \n \ + .word QSPI2_IRQHandler \n \ + .word SWPMI_WKUP_IRQHandler \n \ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ \n \ + .word CAN3_TX_IRQHandler /* CAN3 TX */ \n \ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ \n \ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ \n \ + .word LPTIM2_WKUP_IRQHandler \n \ + .word LPTIM1_WKUP_IRQHandler \n \ + .word I3C_WKUP_IRQHandler \n \ + .word RTC_IRQHandler /* RTC */ \n \ + .word HSADC_IRQHandler \n \ + .word UHSIF_IRQHandler \n \ + .word RNG_IRQHandler /* RNG */ \n \ + .word SDIO_IRQHandler /* SDIO */ \n \ + .word USART_WKUP_IRQHandler \n " + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR "\n.option pop;\n" + + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + uint32_t RESERVED0; + __IO uint64_t CMP; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + #define ADC1_2_IRQn ADC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + uint32_t RESERVED0; + __IO uint32_t AUX; + __IO uint32_t DRV; +} ADC_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + __IO uint32_t TERR_CNT; + uint32_t RESERVED0[85]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + __IO uint32_t FMCFGR_CAN3; + __IO uint32_t FSCFGR; + __IO uint32_t FSCFGR_CAN3; + __IO uint32_t FAFIFOR; + __IO uint32_t FAFIFOR_CAN3; + __IO uint32_t FWR; + __IO uint32_t FWR_CAN3; + uint32_t RESERVED2[7]; + CAN_FilterRegister_TypeDef sFilterRegister[42]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; + __IO uint32_t M1ADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* DMA MUX Controller */ +typedef struct +{ + __IO uint32_t CFGR0_3; + __IO uint32_t CFGR4_7; + __IO uint32_t CFGR8_11; + __IO uint32_t CFGR12_15; +} DMAMUX_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* FMC Bank1 Registers */ +typedef struct +{ + __IO uint32_t BTCR[8]; +} FMC_Bank1_TypeDef; + +/* FMC Bank1E Registers */ +typedef struct +{ + __IO uint32_t BWTR[7]; +} FMC_Bank1E_TypeDef; + +/* FMC Bank3 Registers */ +typedef struct +{ + __IO uint32_t PCR; + __IO uint32_t SR; + __IO uint32_t PMEM; + __IO uint32_t PATT; + uint32_t RESERVED0; + __IO uint32_t ECCR; +} FMC_Bank3_TypeDef; + +/* FMC Bank5_6 Registers */ +typedef struct +{ + __IO uint32_t SDCR[2]; + __IO uint32_t SDTR[2]; + __IO uint32_t SDCMR; + __IO uint32_t SDRTR; + __IO uint32_t SDSR; + uint32_t RESERVED0[9]; + __IO uint32_t MISC; +} FMC_Bank5_6_TypeDef; + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_PP = 1, + GPIO_CFGLR_OUT_OD = 5, + GPIO_CFGLR_OUT_AF_PP = 9, + GPIO_CFGLR_OUT_AF_OD = 13, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t IDR8 :1; + uint32_t IDR9 :1; + uint32_t IDR10 :1; + uint32_t IDR11:1; + uint32_t IDR12 :1; + uint32_t IDR13 :1; + uint32_t IDR14 :1; + uint32_t IDR15 :1; + uint32_t :16; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t ODR8 :1; + uint32_t ODR9 :1; + uint32_t ODR10 :1; + uint32_t ODR11 :1; + uint32_t ODR12 :1; + uint32_t ODR13 :1; + uint32_t ODR14 :1; + uint32_t ODR15 :1; + uint32_t :16; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t BS8 :1; + uint32_t BS9 :1; + uint32_t BS10 :1; + uint32_t BS11 :1; + uint32_t BS12 :1; + uint32_t BS13 :1; + uint32_t BS14 :1; + uint32_t BS15 :1; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t BR8 :1; + uint32_t BR9 :1; + uint32_t BR10 :1; + uint32_t BR11 :1; + uint32_t BR12 :1; + uint32_t BR13 :1; + uint32_t BR14 :1; + uint32_t BR15 :1; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t BR8 :1; + uint32_t BR9 :1; + uint32_t BR10 :1; + uint32_t BR11 :1; + uint32_t BR12 :1; + uint32_t BR13 :1; + uint32_t BR14 :1; + uint32_t BR15 :1; + uint32_t :16; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCK8 :1; + uint32_t LCK9 :1; + uint32_t LCK10 :1; + uint32_t LCK11 :1; + uint32_t LCK12 :1; + uint32_t LCK13 :1; + uint32_t LCK14 :1; + uint32_t LCK15 :1; + uint32_t LCKK :1; + uint32_t :15; + }; +} GPIO_LCKR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t SPEED0 :1; + uint32_t SPEED1 :1; + uint32_t SPEED2 :1; + uint32_t SPEED3 :1; + uint32_t SPEED4 :1; + uint32_t SPEED5 :1; + uint32_t SPEED6 :1; + uint32_t SPEED7 :1; + uint32_t SPEED8 :1; + uint32_t SPEED9 :1; + uint32_t SPEED10 :1; + uint32_t SPEED11 :1; + uint32_t SPEED12 :1; + uint32_t SPEED13 :1; + uint32_t SPEED14 :1; + uint32_t SPEED15 :1; + uint32_t SPEED16 :1; + uint32_t SPEED17 :1; + uint32_t SPEED18 :1; + uint32_t SPEED19 :1; + uint32_t SPEED20 :1; + uint32_t SPEED21 :1; + uint32_t SPEED22 :1; + uint32_t SPEED23 :1; + uint32_t SPEED24 :1; + uint32_t SPEED25 :1; + uint32_t SPEED26 :1; + uint32_t SPEED27 :1; + uint32_t SPEED28 :1; + uint32_t SPEED29 :1; + uint32_t SPEED30 :1; + uint32_t SPEED31 :1; + }; +} GPIO_SPEED_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; + __IO uint32_t SPEED; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t PCFR1; + __IO uint32_t GPIOA_AFLR; + __IO uint32_t GPIOA_AFHR; + __IO uint32_t GPIOB_AFLR; + __IO uint32_t GPIOB_AFHR; + __IO uint32_t GPIOC_AFLR; + __IO uint32_t GPIOC_AFHR; + __IO uint32_t GPIOD_AFLR; + __IO uint32_t GPIOD_AFHR; + __IO uint32_t GPIOE_AFLR; + __IO uint32_t GPIOE_AFHR; + __IO uint32_t GPIOF_AFLR; + __IO uint32_t GPIOF_AFHR; + uint32_t RESERVED0[2]; + __IO uint32_t EXTICR1; + __IO uint32_t EXTICR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Inter Integrated 3 Circuit Interface */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2]; + __IO uint32_t RDBR; + __IO uint32_t RDWR; + __IO uint32_t TDBR; + __IO uint32_t TDWR; + __IO uint32_t IBIDR; + __IO uint32_t TGTTDR; + uint32_t RESERVED1; + __IO uint32_t RESET; + __IO uint32_t STATR; + __IO uint32_t STATER; + uint32_t RESERVED2[2]; + __IO uint32_t RMR; + uint32_t RESERVED3[3]; + __IO uint32_t EVR; + __IO uint32_t INTENR; + __IO uint32_t CEVR; + uint32_t RESERVED4; + __IO uint32_t DEVR0; + __IO uint32_t DEVR1; + __IO uint32_t DEVR2; + __IO uint32_t DEVR3; + __IO uint32_t DEVR4; + uint32_t RESERVED5[7]; + __IO uint32_t MAXRLR; + __IO uint32_t MAXWLR; + uint32_t RESERVED6[2]; + __IO uint32_t TIMINGR0; + __IO uint32_t TIMINGR1; + __IO uint32_t TIMINGR2; + uint32_t RESERVED7[5]; + __IO uint32_t BCR; + __IO uint32_t DCR; + __IO uint32_t GETCAPR; + __IO uint32_t CRCAPR; + __IO uint32_t GETMDSR; + __IO uint32_t EPIDR; +} I3C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t PLLCFGR; + __IO uint32_t INTR; + __IO uint32_t HB2PRSTR; + __IO uint32_t HB1PRSTR; + __IO uint32_t HBPCENR; + __IO uint32_t HB2PCENR; + __IO uint32_t HB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t HBRSTR; + __IO uint32_t CFGR2; + __IO uint32_t PLLCFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* SDIO Registers */ +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[5]; + __IO uint32_t DCTRL2; + uint32_t RESERVED2[7]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + union + { + __IO uint32_t CNT_32; //TIM9,10,11,12 + struct + { + __IO uint16_t CNT; + uint16_t RESERVED9; + }; + }; + __IO uint16_t PSC; + uint16_t RESERVED10; + union + { + __IO uint32_t ATRLR_32;//TIM9,10,11,12 + struct + { + __IO uint16_t ATRLR; + uint16_t RESERVED11; + }; + }; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_32; + struct + { + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + }; + }; + union + { + __IO uint32_t CH2CVR_32; + struct + { + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + }; + }; + union + { + __IO uint32_t CH3CVR_32; + struct + { + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + }; + }; + union + { + __IO uint32_t CH4CVR_32; + struct + { + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + }; + }; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; + __IO uint16_t AUX; + uint16_t RESERVED20; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; + __IO uint16_t CTLR4; + uint16_t RESERVED7; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t CTLR3; + __IO uint32_t CMP_CTLR; + __IO uint32_t CMP_STATR; +} OPA_TypeDef; + +/* RNG Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; +} RNG_TypeDef; + +/* LPTIM Registers */ +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t CFGR; + __IO uint32_t CR; + __IO uint16_t CMP; + uint16_t Reserved0; + __IO uint16_t ARR; + uint16_t Reserved1; + __IO uint16_t CNT; + uint16_t Reserved2; +} LPTIM_TypeDef; + +/* DVP Registers */ +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t IER; + __IO uint8_t Reserved0; + __IO uint16_t ROW_NUM; + __IO uint16_t COL_NUM; + __IO uint32_t DMA_BUF0; + __IO uint32_t DMA_BUF1; + __IO uint8_t IFR; + __IO uint8_t STATUS; + __IO uint16_t Reserved1; + __IO uint16_t ROW_CNT; + __IO uint16_t Reserved2; + __IO uint16_t HOFFCNT; + __IO uint16_t VST; + __IO uint16_t CAPCNT; + __IO uint16_t VLINE; + __IO uint32_t DR; +} DVP_TypeDef; + +/* PD Registers */ +typedef struct +{ + union + { + __IO uint32_t USBPD_CONFIG; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t USBPD_CONTROL; + struct + { + union + { + __IO uint16_t R16_CONTROL; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t USBPD_STATUS; + struct + { + union + { + __IO uint16_t R16_STATUS; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t USBPD_PORT; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + __IO uint32_t USBPD_DMA; +} USBPD_TypeDef; + +/* USBSS Deveice Registers */ +typedef struct +{ + __IO uint8_t UEP_TX_CFG; // 0x0 + __IO uint8_t UEP_TX_CR; // 0x1 + __IO uint8_t UEP_TX_SEQ; // 0x2 + __IO uint8_t UEP_TX_ST; // 0x3 + __IO uint8_t UEP_TX_CHAIN_CR; // 0x4 + __IO uint8_t UEP_TX_CHAIN_ST; // 0x5 + __IO uint16_t UEP_TX_CHAIN_LEN; // 0x6 + __IO uint8_t UEP_TX_CHAIN_EXP_NUMP; // 0x8 + __IO uint8_t UEP_TX_CHAIN_NUMP; // 0x9 + __IO uint16_t UEP_TX_DMA_OFS; // 0xA + __IO uint32_t UEP_TX_DMA; // 0xC +} USBSS_EP_TX_TypeDef; + +typedef struct +{ + __IO uint8_t UEP_RX_CFG; // 0x0 + __IO uint8_t UEP_RX_CR; // 0x1 + __IO uint8_t UEP_RX_SEQ; // 0x2 + __IO uint8_t UEP_RX_ST; // 0x3 + __IO uint8_t UEP_RX_CHAIN_CR; // 0x4 + __IO uint8_t UEP_RX_CHAIN_ST; // 0x5 + __IO uint16_t UEP_RX_CHAIN_LEN; // 0x6 + __IO uint8_t UEP_RX_CHAIN_MAX_NUMP; // 0x8 + __IO uint8_t UEP_RX_CHAIN_NUMP; // 0x9 + __IO uint16_t UEP_RX_DMA_OFS; // 0xA + __IO uint32_t UEP_RX_DMA; // 0xC +} USBSS_EP_RX_TypeDef; + +typedef struct +{ + __IO uint32_t LINK_CFG; + __IO uint32_t LINK_CTRL; + __IO uint32_t LINK_INT_CTRL; + __IO uint32_t LINK_INT_FLAG; + __IO uint32_t LINK_STATUS; + uint8_t Reserved0[3]; + __IO uint8_t LINK_ITP_PRE; + uint8_t Reserved1[5]; + __IO uint8_t LINK_U2_INACT_TIMER; + uint8_t Reserved2[10]; + __IO uint8_t LINK_U1_WKUP_FILTER; + uint8_t Reserved3[1]; + __IO uint16_t LINK_U1_WKUP_TMR; + __IO uint8_t LINK_U2_WKUP_FILTER; + uint8_t Reserved4[3]; + __IO uint8_t LINK_U3_WKUP_FILTER; + uint8_t Reserved5[1]; + __IO uint16_t LINK_U3_WKUP_TMR; + uint8_t Reserved6[12]; + __IO uint16_t LINK_ISO_DLY; + uint8_t Reserved7[14]; + __IO uint16_t LINK_LPM_CR; + uint8_t Reserved8[2]; + __IO uint32_t LINK_LMP_PORT_CAP; + __IO uint32_t LINK_LMP_RX_DATA0; + __IO uint32_t LINK_LMP_RX_DATA1; + __IO uint32_t LINK_LMP_RX_DATA2; + __IO uint32_t LINK_LMP_TX_DATA0; + __IO uint32_t LINK_LMP_TX_DATA1; + __IO uint32_t LINK_LMP_TX_DATA2; + __IO uint32_t USB_CONTROL; + __IO uint32_t USB_STATUS; + __IO uint32_t USB_ITP; + __IO uint32_t USB_ITP_ADJ; + __IO uint16_t UEP_TX_EN; + __IO uint16_t UEP_RX_EN; + __IO uint32_t UEP0_TX_CTRL; + __IO uint32_t UEP0_RX_CTRL; + __IO uint32_t UEP0_TX_DMA; + __IO uint32_t UEP0_RX_DMA; + __IO uint32_t UEP0_TX_DMA_OFS; + __IO uint32_t UEP0_RX_DMA_OFS; + uint8_t Reserved9[36]; + __IO USBSS_EP_TX_TypeDef EP1_TX; + __IO USBSS_EP_RX_TypeDef EP1_RX; + __IO USBSS_EP_TX_TypeDef EP2_TX; + __IO USBSS_EP_RX_TypeDef EP2_RX; + __IO USBSS_EP_TX_TypeDef EP3_TX; + __IO USBSS_EP_RX_TypeDef EP3_RX; + __IO USBSS_EP_TX_TypeDef EP4_TX; + __IO USBSS_EP_RX_TypeDef EP4_RX; + __IO USBSS_EP_TX_TypeDef EP5_TX; + __IO USBSS_EP_RX_TypeDef EP5_RX; + __IO USBSS_EP_TX_TypeDef EP6_TX; + __IO USBSS_EP_RX_TypeDef EP6_RX; + __IO USBSS_EP_TX_TypeDef EP7_TX; + __IO USBSS_EP_RX_TypeDef EP7_RX; +} USBSSD_TypeDef; + +typedef struct +{ + __IO uint32_t LINK_CFG; + __IO uint32_t LINK_CTRL; + __IO uint32_t LINK_INT_CTRL; + __IO uint32_t LINK_INT_FLAG; + __IO uint32_t LINK_STATUS; + uint8_t Reserved0[3]; + __IO uint8_t LINK_ITP_PRE; + uint8_t Reserved1[5]; + __IO uint8_t LINK_U2_INACT_TIMER; + uint8_t Reserved2[10]; + __IO uint8_t LINK_U1_WKUP_FILTER; + uint8_t Reserved3[3]; + __IO uint8_t LINK_U2_WKUP_FILTER; + uint8_t Reserved4[3]; + __IO uint8_t LINK_U3_WKUP_FILTER; + uint8_t Reserved5[15]; + __IO uint16_t LINK_ISO_DLY; + uint8_t Reserved6[14]; + __IO uint16_t LINK_LPM_CR; + uint8_t Reserved7[2]; + __IO uint32_t LINK_LMP_PORT_CAP; + __IO uint32_t LINK_LMP_RX_DATA0; + __IO uint32_t LINK_LMP_RX_DATA1; + __IO uint32_t LINK_LMP_RX_DATA2; + __IO uint32_t LINK_LMP_TX_DATA0; + __IO uint32_t LINK_LMP_TX_DATA1; + __IO uint32_t LINK_LMP_TX_DATA2; + + __IO uint32_t USB_CONTROL; + __IO uint32_t USB_STATUS; + __IO uint32_t USB_ITP; + __IO uint32_t USB_ITP_ADJ; + __IO uint16_t UEP_TX_EN; + __IO uint16_t UEP_RX_EN; + + __IO uint32_t UH_TX_CTRL; + __IO uint32_t UH_RX_CTRL; + __IO uint32_t UH_TX_DMA; + __IO uint32_t UH_RX_DMA; + __IO uint32_t UH_TX_DMA_OFS; + __IO uint32_t UH_RX_DMA_OFS; + __IO uint16_t HOST_TX_NUMP; + __IO uint16_t HOST_RX_NUMP; + __IO uint32_t HOST_STATUS; + __IO uint16_t HOST_TX_FC_STATUS; + __IO uint16_t HOST_RX_FC_STATUS; + __IO uint32_t TP_RX_DATA0; + __IO uint32_t TP_RX_DATA1; + __IO uint32_t TP_RX_DATA2; +} USBSSH_TypeDef; + +/* USBHS Device Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t BASE_MODE; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint8_t WAKE_CTRL; + __IO uint8_t TEST_MODE; + __IO uint16_t LPM_DATA; + + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint8_t MIS_ST; + uint8_t RESERVED0; + + __IO uint16_t FRAME_NO; + __IO uint16_t BUS; + + __IO uint16_t UEP_TX_EN; + __IO uint16_t UEP_RX_EN; + __IO uint16_t UEP_TX_TOG_AUTO; + __IO uint16_t UEP_RX_TOG_AUTO; + + __IO uint8_t UEP_TX_BURST; + __IO uint8_t UEP_TX_BURST_MODE; + __IO uint8_t UEP_RX_BURST; + __IO uint8_t UEP_RX_RES_MODE; + + __IO uint32_t UEP_AF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP0_MAX_LEN; + __IO uint32_t UEP1_MAX_LEN; + __IO uint32_t UEP2_MAX_LEN; + __IO uint32_t UEP3_MAX_LEN; + __IO uint32_t UEP4_MAX_LEN; + __IO uint32_t UEP5_MAX_LEN; + __IO uint32_t UEP6_MAX_LEN; + __IO uint32_t UEP7_MAX_LEN; + + __IO uint16_t UEP0_RX_LEN; + uint16_t RESERVED1; + __IO uint16_t UEP1_RX_LEN; + __IO uint16_t UEP1_RX_SIZE; + __IO uint16_t UEP2_RX_LEN; + __IO uint16_t UEP2_RX_SIZE; + __IO uint16_t UEP3_RX_LEN; + __IO uint16_t UEP3_RX_SIZE; + __IO uint16_t UEP4_RX_LEN; + __IO uint16_t UEP4_RX_SIZE; + __IO uint16_t UEP5_RX_LEN; + __IO uint16_t UEP5_RX_SIZE; + __IO uint16_t UEP6_RX_LEN; + __IO uint16_t UEP6_RX_SIZE; + __IO uint16_t UEP7_RX_LEN; + __IO uint16_t UEP7_RX_SIZE; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + + __IO uint16_t UEP_TX_ISO; + __IO uint16_t UEP_RX_ISO; + + __IO uint32_t UEP1_RX_FIFO; + __IO uint32_t UEP2_RX_FIFO; + __IO uint32_t UEP3_RX_FIFO; + __IO uint32_t UEP4_RX_FIFO; + __IO uint32_t UEP5_RX_FIFO; + __IO uint32_t UEP6_RX_FIFO; + __IO uint32_t UEP7_RX_FIFO; + __IO uint32_t UEP1_TX_FIFO; + __IO uint32_t UEP2_TX_FIFO; + __IO uint32_t UEP3_TX_FIFO; + __IO uint32_t UEP4_TX_FIFO; + __IO uint32_t UEP5_TX_FIFO; + __IO uint32_t UEP6_TX_FIFO; + __IO uint32_t UEP7_TX_FIFO; +} USBHSD_TypeDef; + +/* USBHS Host Registers */ +typedef struct __attribute__((packed)) +{ + __IO uint8_t CFG; + uint8_t RESERVED0; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint32_t CONTROL; + + __IO uint8_t INT_FLAG; + __IO uint8_t INT_ST; + __IO uint8_t MIS_ST; + uint8_t RESERVED1; + + __IO uint32_t LPM; + __IO uint32_t SPLIT; + __IO uint32_t FRAME; + __IO uint32_t TX_LEN; + __IO uint32_t RX_LEN; + __IO uint32_t RX_MAX_LEN; + __IO uint32_t RX_DMA; + __IO uint32_t TX_DMA; + __IO uint32_t PORT_CTRL; + __IO uint8_t PORT_CFG; + uint8_t RESERVED2; + __IO uint8_t PORT_INT_EN; + __IO uint8_t PORT_TEST_CT; + + __IO uint16_t PORT_STATUS; + __IO uint8_t PORT_STATUS_CHG; + uint8_t RESERVED3[5]; + __IO uint32_t ROOT_BC_CTRL; +} USBHSH_TypeDef; + +/* USBFS Device Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + + uint16_t RESERVED1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint8_t UEP0_TX_LEN; + uint8_t RESERVED2; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint8_t UEP1_TX_LEN; + uint8_t RESERVED3; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint8_t UEP2_TX_LEN; + uint8_t RESERVED4; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint8_t UEP4_TX_LEN; + uint8_t RESERVED5; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint8_t UEP5_TX_LEN; + uint8_t RESERVED6; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint8_t UEP6_TX_LEN; + uint8_t RESERVED7; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint8_t UEP7_TX_LEN; + uint8_t RESERVED8; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + uint32_t RESERVED9; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSD_TypeDef; + +/* USBFS Host Registers */ +typedef struct __attribute__((packed)) +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + + uint16_t RESERVED1; + uint8_t RESERVED2; + __IO uint8_t HOST_EP_MOD; + uint16_t RESERVED3; + uint32_t RESERVED4; + uint32_t RESERVED5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + uint32_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + uint32_t RESERVED9; + uint32_t RESERVED10; + uint16_t RESERVED11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + uint8_t RESERVED12; + uint8_t RESERVED13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + uint8_t RESERVED14; + uint32_t RESERVED15; + uint32_t RESERVED16; + uint32_t RESERVED17; + uint32_t RESERVED18; + uint32_t RESERVED19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSH_TypeDef; + +/* Ethernet MAC Registers */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[8]; + __IO uint32_t MACPHYCR; + uint32_t RESERVED3[5]; + __IO uint32_t MACCFG0; + uint32_t RESERVED4[25]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED5[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED6[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED7[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + __IO uint32_t MMCRAFCR; + uint32_t RESERVED8[9]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED9[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED10[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED11[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/* SDMMC Registers */ +typedef struct +{ + __IO uint32_t ARGUMENT; + __IO uint16_t CMD_SET; + uint16_t RESERVED0; + __IO uint32_t RESPONSE0; + __IO uint32_t RESPONSE1; + __IO uint32_t RESPONSE2; + union + { + __IO uint32_t RESPONSE3; + __IO uint32_t WRITE_CONT; + }; + __IO uint16_t CONTROL; + uint16_t RESERVED1; + __IO uint8_t TIMEOUT; + uint8_t RESERVED3[3]; + __IO uint32_t STATUS; + __IO uint16_t INT_FG; + uint16_t RESERVED4; + __IO uint16_t INT_EN; + uint16_t RESERVED5; + __IO uint32_t DMA_BEG1; + __IO uint32_t BLOCK_CFG; + __IO uint32_t TRAN_MODE; + __IO uint16_t CLK_DIV; + uint16_t RESERVED6; + __IO uint32_t DMA_BEG2; + __IO uint32_t TUNE_DATO; + __IO uint32_t TUNE_DATI; + __IO uint32_t TUNE_CLK_CMD; +} SDMMC_TypeDef; + +/* SAI Registers */ +typedef struct +{ + __IO uint32_t CFGR1; + __IO uint32_t CFGR2; + __IO uint32_t FRCR; + __IO uint32_t SLOTR; + __IO uint32_t INTENR; + __IO uint32_t SR; + uint32_t RESERVED0; + __IO uint32_t DATAR; +} SAI_Block_TypeDef; + +/* QSPI Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DCR; + __IO uint32_t SR; + __IO uint32_t FCR; + __IO uint32_t DLR; + __IO uint32_t CCR; + __IO uint32_t AR; + __IO uint32_t ABR; + __IO uint32_t DR; + __IO uint32_t PSMKR; + __IO uint32_t PSMAR; + __IO uint32_t PIR; + __IO uint32_t LPTR; +} QSPI_TypeDef; + +/* SWPMI Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t BRR; + uint32_t RESERVED0; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t RFL; + __IO uint32_t TDR; + __IO uint32_t RDR; + __IO uint32_t OR; +} SWPMI_TypeDef; + +/* ECDC Registers */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t INT_FG; + __IO uint32_t KEY_255T224; + __IO uint32_t KEY_223T192; + __IO uint32_t KEY_191T160; + __IO uint32_t KEY_159T128; + __IO uint32_t KEY_127T96; + __IO uint32_t KEY_95T64; + __IO uint32_t KEY_63T32; + __IO uint32_t KEY_31T0; + __IO uint32_t IV_127T96; + __IO uint32_t IV_95T64; + __IO uint32_t IV_63T32; + __IO uint32_t IV_31T0; + uint32_t RESERVED3[2]; + __IO uint32_t SGSD_127T96; + __IO uint32_t SGSD_95T64; + __IO uint32_t SGSD_63T32; + __IO uint32_t SGSD_31T0; + __IO uint32_t SGRT_127T96; + __IO uint32_t SGRT_95T64; + __IO uint32_t SGRT_63T32; + __IO uint32_t SGRT_31T0; + __IO uint32_t SRC_ADDR; + __IO uint32_t DST_ADDR; + __IO uint32_t SRAM_LEN; +} ECDC_TypeDef; + +/* DFSDM filter Registers */ +typedef struct +{ + __IO uint32_t CR1; + uint32_t RESERVED0; + __IO uint32_t CR2; + uint32_t RESERVED1; + __IO uint32_t ISR; + uint32_t RESERVED2; + __IO uint32_t ICR; + uint32_t RESERVED3; + __IO uint32_t JCHGR; + uint32_t RESERVED4; + __IO uint32_t FCR3; + uint32_t RESERVED5; + __IO uint32_t JDATAR; + uint32_t RESERVED6; + __IO uint32_t RDATAR; + uint32_t RESERVED7; + __IO uint32_t AWHTR; + uint32_t RESERVED8; + __IO uint32_t AWLTR; + uint32_t RESERVED9; + __IO uint32_t AWSR; + uint32_t RESERVED10; + __IO uint32_t AWCFR; + uint32_t RESERVED11; + __IO uint32_t EXMAX; + uint32_t RESERVED12; + __IO uint32_t EXMIN; + uint32_t RESERVED13; + __IO uint32_t NVTIMR; + uint32_t RESERVED14; +} DFSDM_FLT_TypeDef; + +/* DFSDM channel Registers */ +typedef struct +{ + __IO uint32_t CFGR1; + uint32_t RESERVED0; + __IO uint32_t CFGR2; + uint32_t RESERVED1; + __IO uint32_t AWSCDR; + uint32_t RESERVED2; + __IO uint32_t WDATR; + uint32_t RESERVED3; + union{ + __IO uint32_t DATINR; + struct{ + __IO int16_t DATINR0; + __IO int16_t DATINR1; + }; + }; +} DFSDM_Channel_TypeDef; + +/* LTDC Registers */ +typedef struct +{ + __IO uint32_t SSCR; + __IO uint32_t BPCR; + __IO uint32_t AWCR; + __IO uint32_t TWCR; + __IO uint32_t GCR; + __IO uint32_t SRCR; + __IO uint32_t BCCR; + __IO uint32_t IER; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t LIPCR; + __IO uint32_t CPSR; + __IO uint32_t CDSR; +} LTDC_TypeDef; + +/* LTDC Layer Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WHPCR; + __IO uint32_t WVPCR; + __IO uint32_t CKCR; + __IO uint32_t PFCR; + __IO uint32_t CACR; + __IO uint32_t DCCR; + __IO uint32_t BFCR; + __IO uint32_t CFBAR; + __IO uint32_t CFBLR; + __IO uint32_t CFBLNR; + __IO uint32_t CLUTWR; +} LTDC_Layer_TypeDef; + +/* GPHA Registers */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t ISR; + __IO uint32_t IFCR; + __IO uint32_t FGMAR; + __IO uint32_t FGOR; + __IO uint32_t BGMAR; + __IO uint32_t BGOR; + __IO uint32_t FGPFCCR; + __IO uint32_t FGCOLR; + __IO uint32_t BGPFCCR; + __IO uint32_t BGCOLR; + __IO uint32_t FGCMAR; + __IO uint32_t BGCMAR; + __IO uint32_t OPFCCR; + __IO uint32_t OCOLR; + __IO uint32_t OMAR; + __IO uint32_t OOR; + __IO uint32_t NLR; + __IO uint32_t LWR; + __IO uint32_t AMTCR; + __IO uint32_t FGCWRS; + __IO uint32_t FGCDAT; + __IO uint32_t BGCWRS; + __IO uint32_t BGCDAT; +} GPHA_TypeDef; + +/* HSADC Registers */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t STATR; + __IO uint32_t DATAR; + __IO uint32_t ADDR0; + __IO uint32_t ADDR1; +} HSADC_TypeDef; + +/* SerDes Registers */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t INT_EN; + __IO uint32_t STATUS; + __IO uint32_t RTX_CTRL; + __IO uint32_t RX_LEN0; + __IO uint32_t DATA0; + __IO uint32_t DMA_0; + __IO uint32_t RX_LEN1; + __IO uint32_t DATA1; + __IO uint32_t DMA_1; +} SDS_TypeDef; + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x100]; + __IO uint8_t IALLOCR[256]; + __I uint32_t IAUTR[8]; + __IO uint32_t WAKEIP[2]; + uint8_t RESERVED8[0x58]; + __I uint32_t CSTAR[2]; + uint8_t RESERVED9[0x4F8]; + __IO uint32_t EENR; + __IO uint32_t EPR; + __IO uint32_t EWUPR; + uint8_t RESERVED10[0x84]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif // !__ASSEMBLER__ + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define ITCM_BASE (0x200A0000) /* ITCM base address in the alias region */ +#define DTCM_BASE (0x200C0000) /* DTCM base address in the alias region */ +#define SRAM_BASE (0x20100000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define ITCM_BASE ((uint32_t)0x200A0000) /* ITCM base address in the alias region */ +#define DTCM_BASE ((uint32_t)0x200C0000) /* DTCM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20100000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + +#define HBPERIPH_BASE (PERIPH_BASE) + +#define TIM2_BASE (HBPERIPH_BASE + 0x00000) +#define TIM3_BASE (HBPERIPH_BASE + 0x00400) +#define TIM4_BASE (HBPERIPH_BASE + 0x00800) +#define TIM5_BASE (HBPERIPH_BASE + 0x00C00) +#define TIM6_BASE (HBPERIPH_BASE + 0x01000) +#define TIM7_BASE (HBPERIPH_BASE + 0x01400) +#define USART6_BASE (HBPERIPH_BASE + 0x01800) +#define USART7_BASE (HBPERIPH_BASE + 0x01C00) +#define USART8_BASE (HBPERIPH_BASE + 0x02000) +#define LPTIM1_BASE (HBPERIPH_BASE + 0x02400) +#define RTC_BASE (HBPERIPH_BASE + 0x02800) +#define WWDG_BASE (HBPERIPH_BASE + 0x02C00) +#define IWDG_BASE (HBPERIPH_BASE + 0x03000) +#define LPTIM2_BASE (HBPERIPH_BASE + 0x03400) +#define SPI2_BASE (HBPERIPH_BASE + 0x03800) +#define SPI3_BASE (HBPERIPH_BASE + 0x03C00) +#define SPI4_BASE (HBPERIPH_BASE + 0x04000) +#define USART2_BASE (HBPERIPH_BASE + 0x04400) +#define USART3_BASE (HBPERIPH_BASE + 0x04800) +#define USART4_BASE (HBPERIPH_BASE + 0x04C00) +#define USART5_BASE (HBPERIPH_BASE + 0x05000) +#define I2C1_BASE (HBPERIPH_BASE + 0x05400) +#define I2C2_BASE (HBPERIPH_BASE + 0x05800) +#define I2C3_BASE (HBPERIPH_BASE + 0x05C00) +#define CAN1_BASE (HBPERIPH_BASE + 0x06400) +#define CAN2_BASE (HBPERIPH_BASE + 0x06800) +#define PWR_BASE (HBPERIPH_BASE + 0x07000) +#define DAC_BASE (HBPERIPH_BASE + 0x07400) +#define CAN3_BASE (HBPERIPH_BASE + 0x07800) +#define SWPMI_BASE (HBPERIPH_BASE + 0x08400) + +#define AFIO_BASE (HBPERIPH_BASE + 0x10000) +#define EXTI_BASE (HBPERIPH_BASE + 0x10400) +#define GPIOA_BASE (HBPERIPH_BASE + 0x10800) +#define GPIOB_BASE (HBPERIPH_BASE + 0x10C00) +#define GPIOC_BASE (HBPERIPH_BASE + 0x11000) +#define GPIOD_BASE (HBPERIPH_BASE + 0x11400) +#define GPIOE_BASE (HBPERIPH_BASE + 0x11800) +#define GPIOF_BASE (HBPERIPH_BASE + 0x11C00) +#define ADC1_BASE (HBPERIPH_BASE + 0x12400) +#define ADC2_BASE (HBPERIPH_BASE + 0x12800) +#define TIM1_BASE (HBPERIPH_BASE + 0x12C00) +#define SPI1_BASE (HBPERIPH_BASE + 0x13000) +#define TIM8_BASE (HBPERIPH_BASE + 0x13400) +#define USART1_BASE (HBPERIPH_BASE + 0x13800) +#define TIM12_BASE (HBPERIPH_BASE + 0x13C00) +#define I2C4_BASE (HBPERIPH_BASE + 0x14000) +#define I3C_BASE (HBPERIPH_BASE + 0x14400) + +#define LTDC_BASE (HBPERIPH_BASE + 0x14800) +#define LTDC_L1_BASE (HBPERIPH_BASE + 0x14834) +#define LTDC_L2_BASE (HBPERIPH_BASE + 0x14864) + +#define TIM9_BASE (HBPERIPH_BASE + 0x14C00) +#define TIM10_BASE (HBPERIPH_BASE + 0x15000) +#define TIM11_BASE (HBPERIPH_BASE + 0x15400) + +#define SAI_BASE (HBPERIPH_BASE + 0x15800) +#define SAI_Block_A_BASE (SAI_BASE + 0x04) +#define SAI_Block_B_BASE (SAI_BASE + 0x24) + +#define GPHA_BASE (HBPERIPH_BASE + 0x16800) +#define ECDC_BASE (HBPERIPH_BASE + 0x16C00) + +#define DFSDM_BASE (HBPERIPH_BASE + 0x17000) +#define DFSDM_Channel0_BASE (HBPERIPH_BASE + 0x17000) +#define DFSDM_Channel1_BASE (HBPERIPH_BASE + 0x17004) +#define DFSDM_FLT0_BASE (HBPERIPH_BASE + 0x17028) +#define DFSDM_FLT1_BASE (HBPERIPH_BASE + 0x1702C) + +#define HSADC_BASE (HBPERIPH_BASE + 0x17400) +#define OPA_BASE (HBPERIPH_BASE + 0x17800) +#define SDIO_BASE (HBPERIPH_BASE + 0x18000) + +#define DMA1_BASE (HBPERIPH_BASE + 0x20000) +#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x20008) +#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x2001C) +#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x20030) +#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x20044) +#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x20058) +#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x2006C) +#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x20080) +#define DMA1_Channel8_BASE (HBPERIPH_BASE + 0x20094) + +#define DMA2_BASE (HBPERIPH_BASE + 0x20400) +#define DMA2_Channel1_BASE (HBPERIPH_BASE + 0x20408) +#define DMA2_Channel2_BASE (HBPERIPH_BASE + 0x2041C) +#define DMA2_Channel3_BASE (HBPERIPH_BASE + 0x20430) +#define DMA2_Channel4_BASE (HBPERIPH_BASE + 0x20444) +#define DMA2_Channel5_BASE (HBPERIPH_BASE + 0x20458) +#define DMA2_Channel6_BASE (HBPERIPH_BASE + 0x2046C) +#define DMA2_Channel7_BASE (HBPERIPH_BASE + 0x20480) +#define DMA2_Channel8_BASE (HBPERIPH_BASE + 0x20494) + +#define DMAMUX_BASE (HBPERIPH_BASE + 0x20800) +#define RCC_BASE (HBPERIPH_BASE + 0x21000) +#define FLASH_R_BASE (HBPERIPH_BASE + 0x22000) +#define CRC_BASE (HBPERIPH_BASE + 0x23000) +#define USBFS_BASE (HBPERIPH_BASE + 0x23400) +#define RNG_BASE (HBPERIPH_BASE + 0x23C00) +#define SDMMC_BASE (HBPERIPH_BASE + 0x24000) +#define USBPD_BASE (HBPERIPH_BASE + 0x24400) +#define QSPI1_BASE (HBPERIPH_BASE + 0x24C00) +#define QSPI2_BASE (HBPERIPH_BASE + 0x25000) +#define FMC_R_BASE (HBPERIPH_BASE + 0x25400) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + +#define DVP_BASE (HBPERIPH_BASE + 0x25800) +#define PIOC_BASE (HBPERIPH_BASE + 0x25C00) + +#define SERDES_BASE (HBPERIPH_BASE + 0x27C00) +#define SERDES1_BASE (SERDES_BASE) +#define SERDES2_BASE (SERDES_BASE+0x0040) + +#define ETH_BASE (HBPERIPH_BASE + 0x28000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define USBHS_BASE (HBPERIPH_BASE + 0x30000) +#define USBHSD_BASE (USBHS_BASE) +#define USBHSH_BASE (USBHS_BASE + 0x100) + +#define USBSS_BASE (HBPERIPH_BASE + 0x34000) +#define UHSIF_BASE (HBPERIPH_BASE + 0x38000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +#define FLASH_CFGR0_BASE ((uint32_t)0x4002202C) +#define SYS_CFGR0_BASE ((uint32_t)0x5003C000) +#define SYS_CFGR4_BASE ((uint32_t)0x5003C010) + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick0_BASE (CORE_PERIPH_BASE + 0xF000) +#define SysTick1_BASE (CORE_PERIPH_BASE + 0xF080) + +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART7 ((USART_TypeDef *) USART7_BASE) +#define USART8 ((USART_TypeDef *) USART8_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) + +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define USART5 ((USART_TypeDef *) USART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CAN3 ((CAN_TypeDef *) CAN3_BASE) +#define SWPMI ((SWPMI_TypeDef *) SWPMI_BASE) + +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TKey1 ((ADC_TypeDef *) ADC1_BASE) +#define TKey2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I3C ((I3C_TypeDef *) I3C_BASE) +#define LTDC ((LTDC_TypeDef *) LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *) LTDC_L1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *) LTDC_L2_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SAI_Block_A ((SAI_Block_TypeDef *) SAI_Block_A_BASE) +#define SAI_Block_B ((SAI_Block_TypeDef *) SAI_Block_B_BASE) +#define GPHA ((GPHA_TypeDef *) GPHA_BASE) +#define ECDC ((ECDC_TypeDef *) ECDC_BASE) +#define DFSDM_FLT0 ((DFSDM_FLT_TypeDef *) DFSDM_FLT0_BASE) +#define DFSDM_FLT1 ((DFSDM_FLT_TypeDef *) DFSDM_FLT1_BASE) +#define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE) +#define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE) +#define HSADC ((HSADC_TypeDef *) HSADC_BASE) +#define OPA ((OPA_TypeDef *) OPA_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) +#define USBPD ((USBPD_TypeDef *) USBPD_BASE) +#define QSPI1 ((QSPI_TypeDef *) QSPI1_BASE) +#define QSPI2 ((QSPI_TypeDef *) QSPI2_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define DVP ((DVP_TypeDef *) DVP_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHSD_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHSH_BASE) +#define USBSSD ((USBSSD_TypeDef *) USBSS_BASE) +#define USBSSH ((USBSSH_TypeDef *) USBSS_BASE) +#define SDS1 ((SDS_TypeDef *) SERDES1_BASE) +#define SDS2 ((SDS_TypeDef *) SERDES2_BASE) +#define UHSIF ((UHSIF_TypeDef *) UHSIF_BASE) +#define OB ((OB_TypeDef *) OB_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +#define ADC_RSTF ((uint16_t)0x8000) /* Reset flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) /*TKEY enable*/ +#define ADC_TKITUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) + +#define ADC_ANA_RST ((uint32_t)0x40000000) +#define ADC_SW_PRE ((uint32_t)0x80000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************** Bit definition for ADC_AUX register ********************/ +#define ADC_SMP_SEL_0 ((uint32_t)0x00000001) /* channel_0 */ +#define ADC_SMP_SEL_1 ((uint32_t)0x00000002) /* channel_1 */ +#define ADC_SMP_SEL_2 ((uint32_t)0x00000004) /* channel_2 */ +#define ADC_SMP_SEL_3 ((uint32_t)0x00000008) /* channel_3 */ +#define ADC_SMP_SEL_4 ((uint32_t)0x00000010) /* channel_4 */ +#define ADC_SMP_SEL_5 ((uint32_t)0x00000020) /* channel_5 */ +#define ADC_SMP_SEL_6 ((uint32_t)0x00000040) /* channel_6 */ +#define ADC_SMP_SEL_7 ((uint32_t)0x00000080) /* channel_7 */ +#define ADC_SMP_SEL_8 ((uint32_t)0x00000100) /* channel_8 */ +#define ADC_SMP_SEL_9 ((uint32_t)0x00000200) /* channel_9 */ +#define ADC_SMP_SEL_10 ((uint32_t)0x00000400) /* channel_10 */ +#define ADC_SMP_SEL_11 ((uint32_t)0x00000800) /* channel_11 */ +#define ADC_SMP_SEL_12 ((uint32_t)0x00001000) /* channel_12 */ +#define ADC_SMP_SEL_13 ((uint32_t)0x00002000) /* channel_13 */ +#define ADC_SMP_SEL_14 ((uint32_t)0x00004000) /* channel_14 */ +#define ADC_SMP_SEL_15 ((uint32_t)0x00008000) /* channel_15 */ +#define ADC_SMP_SEL_16 ((uint32_t)0x00010000) /* channel_16 */ +#define ADC_SMP_SEL_17 ((uint32_t)0x00020000) /* channel_17 */ + +#define ADC_TO_DFSDM ((uint32_t)0x80000000) + +/******************** Bit definition for ADC_DRV register ********************/ +#define ADC_DRV_TKEY_OUTEN ((uint32_t)0x0000FFFF) /* Touchkey enables multi-channel shielding of each channel */ +#define ADC_DRV_TKEY_EN ((uint32_t)0x00010000) /* Touchkey Multi Channel Shielding Enable */ + +/******************************************************************************/ +/* High Speed Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for HSADC_CFGR register ********************/ +#define HSADC_EN ((uint32_t)0x00000001) +#define HSADC_DMAEN ((uint32_t)0x00000002) + +#define HSADC_CHSEL ((uint32_t)0x0000001C) +#define HSADC_CHSEL_0 ((uint32_t)0x00000004) +#define HSADC_CHSEL_1 ((uint32_t)0x00000008) +#define HSADC_CHSEL_2 ((uint32_t)0x00000010) + +#define HSADC_SETUP ((uint32_t)0x00000060) +#define HSADC_SETUP_0 ((uint32_t)0x00000020) +#define HSADC_SETUP_1 ((uint32_t)0x00000040) + +#define HSADC_WIDTH ((uint32_t)0x00000080) + +#define HSADC_CLKDIV ((uint32_t)0x00003F00) +#define HSADC_CLKDIV_0 ((uint32_t)0x00000100) +#define HSADC_CLKDIV_1 ((uint32_t)0x00000200) +#define HSADC_CLKDIV_2 ((uint32_t)0x00000400) +#define HSADC_CLKDIV_3 ((uint32_t)0x00000800) +#define HSADC_CLKDIV_4 ((uint32_t)0x00001000) +#define HSADC_CLKDIV_5 ((uint32_t)0x00002000) + +#define HSADC_PPMODE ((uint32_t)0x00004000) +#define HSADC_BURST_EN ((uint32_t)0x00008000) + +#define HSADC_DMA_LEN ((uint32_t)0xFFFF0000) + +/******************** Bit definition for HSADC_CTLR1 register ********************/ +#define HSADC_START ((uint32_t)0x00000001) +#define HSADC_BURSTEND ((uint32_t)0x00000002) +#define HSADC_EOCIE ((uint32_t)0x00000100) +#define HSADC_DMAIE ((uint32_t)0x00000200) +#define HSADC_BURSTIE ((uint32_t)0x00000400) + +/******************** Bit definition for HSADC_CTLR2 register ********************/ +#define HSADC_BURST_LEN ((uint32_t)0x0000FFFF) +#define HSADC_BURST_DMA_LEN ((uint32_t)0xFFFF0000) + +/******************** Bit definition for HSADC_STATR register ********************/ +#define HSADC_EOCIF ((uint32_t)0x00000001) +#define HSADC_DMAIF ((uint32_t)0x00000002) +#define HSADC_BURSTIF ((uint32_t)0x00000004) +#define HSADC_RXNE ((uint32_t)0x00000008) +#define HSADC_PP_ADDR ((uint32_t)0x00000010) + +#define HSADC_FIFO_RDY ((uint32_t)0x00000100) +#define HSADC_FIFO_FULL ((uint32_t)0x00000200) +#define HSADC_FIFO_OV ((uint32_t)0x00000400) + +#define HSADC_FIFO_CNT ((uint32_t)0x00003800) + +/******************** Bit definition for HSADC_DATAR register ********************/ +#define HSADC_DR ((uint32_t)0x000003FF) + +/******************** Bit definition for HSADC_ADDR0 register ********************/ +#define HSADC_DMA_ADDR0 ((uint32_t)0xFFFFFFFF) + +/******************** Bit definition for HSADC_ADDR1 register ********************/ +#define HSADC_DMA_ADDR1 ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x10000) +#define CAN_CTLR_CFGCANM ((uint32_t)0x20000) + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EMPIE1 ((uint32_t)0x00000010) /* FIF1 Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIF1 Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIF1 Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************** Bit definition for CAN_BTIMR register *******************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) +#define CAN_BTIMR_BTR_TS1_T ((uint32_t)0x0000F000) +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) +#define CAN_BTIMR_TS2 ((uint32_t)0x00F00000) +#define CAN_BTIMR_SJW ((uint32_t)0x0F000000) + +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) + +/******************* Bit definition for CAN_TTCTLR register ********************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************* Bit definition for CAN_TTCNT register ********************/ +#define CAN_TIMCNT ((uint32_t)0x0000FFFF) + +/******************* Bit definition for CAN_TERR_CNT register ********************/ +#define CAN_TERR_CNT ((uint32_t)0x000001FF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH0R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH1R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register *******************/ +#define CAN_FCTLR_TINIT ((uint32_t)0x00000001) + +#define CAN_FCTLR_CAN2SB ((uint32_t)0x00001F00) +#define CAN_FCTLR_CAN3SB ((uint32_t)0x003F0000) + +/****************** Bit definition for CAN_FMCFGR register ******************/ +#define CAN_FMCFGR_FBM0 ((uint32_t)0x00000001) +#define CAN_FMCFGR_FBM1 ((uint32_t)0x00000002) +#define CAN_FMCFGR_FBM2 ((uint32_t)0x00000004) +#define CAN_FMCFGR_FBM3 ((uint32_t)0x00000008) +#define CAN_FMCFGR_FBM4 ((uint32_t)0x00000010) +#define CAN_FMCFGR_FBM5 ((uint32_t)0x00000020) +#define CAN_FMCFGR_FBM6 ((uint32_t)0x00000040) +#define CAN_FMCFGR_FBM7 ((uint32_t)0x00000080) +#define CAN_FMCFGR_FBM8 ((uint32_t)0x00000100) +#define CAN_FMCFGR_FBM9 ((uint32_t)0x00000200) +#define CAN_FMCFGR_FBM10 ((uint32_t)0x00000400) +#define CAN_FMCFGR_FBM11 ((uint32_t)0x00000800) +#define CAN_FMCFGR_FBM12 ((uint32_t)0x00001000) +#define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) +#define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) +#define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) +#define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) +#define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) +#define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) +#define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) +#define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) +#define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) +#define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) +#define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) +#define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) +#define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) +#define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) +#define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) + +/****************** Bit definition for CAN_FMCFGR1 register ******************/ +#define CAN_FMCFGR1_FBM28 ((uint32_t)0x00000001) +#define CAN_FMCFGR1_FBM29 ((uint32_t)0x00000002) +#define CAN_FMCFGR1_FBM30 ((uint32_t)0x00000004) +#define CAN_FMCFGR1_FBM31 ((uint32_t)0x00000008) +#define CAN_FMCFGR1_FBM32 ((uint32_t)0x00000010) +#define CAN_FMCFGR1_FBM33 ((uint32_t)0x00000020) +#define CAN_FMCFGR1_FBM34 ((uint32_t)0x00000040) +#define CAN_FMCFGR1_FBM35 ((uint32_t)0x00000080) +#define CAN_FMCFGR1_FBM36 ((uint32_t)0x00000100) +#define CAN_FMCFGR1_FBM37 ((uint32_t)0x00000200) +#define CAN_FMCFGR1_FBM38 ((uint32_t)0x00000400) +#define CAN_FMCFGR1_FBM39 ((uint32_t)0x00000800) +#define CAN_FMCFGR1_FBM40 ((uint32_t)0x00001000) +#define CAN_FMCFGR1_FBM41 ((uint32_t)0x00002000) + +/****************** Bit definition for CAN_FSCFGR register ******************/ +#define CAN_FSCFGR_FSC0 ((uint32_t)0x00000001) +#define CAN_FSCFGR_FSC1 ((uint32_t)0x00000002) +#define CAN_FSCFGR_FSC2 ((uint32_t)0x00000004) +#define CAN_FSCFGR_FSC3 ((uint32_t)0x00000008) +#define CAN_FSCFGR_FSC4 ((uint32_t)0x00000010) +#define CAN_FSCFGR_FSC5 ((uint32_t)0x00000020) +#define CAN_FSCFGR_FSC6 ((uint32_t)0x00000040) +#define CAN_FSCFGR_FSC7 ((uint32_t)0x00000080) +#define CAN_FSCFGR_FSC8 ((uint32_t)0x00000100) +#define CAN_FSCFGR_FSC9 ((uint32_t)0x00000200) +#define CAN_FSCFGR_FSC10 ((uint32_t)0x00000400) +#define CAN_FSCFGR_FSC11 ((uint32_t)0x00000800) +#define CAN_FSCFGR_FSC12 ((uint32_t)0x00001000) +#define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) +#define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) +#define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) +#define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) +#define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) +#define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) +#define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) +#define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) +#define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) +#define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) +#define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) +#define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) +#define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) +#define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) +#define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) + +/****************** Bit definition for CAN_FSCFGR1 register ******************/ +#define CAN_FSCFGR1_FSC28 ((uint32_t)0x00000001) +#define CAN_FSCFGR1_FSC29 ((uint32_t)0x00000002) +#define CAN_FSCFGR1_FSC30 ((uint32_t)0x00000004) +#define CAN_FSCFGR1_FSC31 ((uint32_t)0x00000008) +#define CAN_FSCFGR1_FSC32 ((uint32_t)0x00000010) +#define CAN_FSCFGR1_FSC33 ((uint32_t)0x00000020) +#define CAN_FSCFGR1_FSC34 ((uint32_t)0x00000040) +#define CAN_FSCFGR1_FSC35 ((uint32_t)0x00000080) +#define CAN_FSCFGR1_FSC36 ((uint32_t)0x00000100) +#define CAN_FSCFGR1_FSC37 ((uint32_t)0x00000200) +#define CAN_FSCFGR1_FSC38 ((uint32_t)0x00000400) +#define CAN_FSCFGR1_FSC39 ((uint32_t)0x00000800) +#define CAN_FSCFGR1_FSC40 ((uint32_t)0x00001000) +#define CAN_FSCFGR1_FSC41 ((uint32_t)0x00002000) + +/****************** Bit definition for CAN_FAFIFOR register ******************/ +#define CAN_FAFIFOR_FFA0 ((uint32_t)0x00000001) +#define CAN_FAFIFOR_FFA1 ((uint32_t)0x00000002) +#define CAN_FAFIFOR_FFA2 ((uint32_t)0x00000004) +#define CAN_FAFIFOR_FFA3 ((uint32_t)0x00000008) +#define CAN_FAFIFOR_FFA4 ((uint32_t)0x00000010) +#define CAN_FAFIFOR_FFA5 ((uint32_t)0x00000020) +#define CAN_FAFIFOR_FFA6 ((uint32_t)0x00000040) +#define CAN_FAFIFOR_FFA7 ((uint32_t)0x00000080) +#define CAN_FAFIFOR_FFA8 ((uint32_t)0x00000100) +#define CAN_FAFIFOR_FFA9 ((uint32_t)0x00000200) +#define CAN_FAFIFOR_FFA10 ((uint32_t)0x00000400) +#define CAN_FAFIFOR_FFA11 ((uint32_t)0x00000800) +#define CAN_FAFIFOR_FFA12 ((uint32_t)0x00001000) +#define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) + +/****************** Bit definition for CAN_FAFIFOR1 register ******************/ +#define CAN_FAFIFOR1_FFA28 ((uint32_t)0x00000001) +#define CAN_FAFIFOR1_FFA29 ((uint32_t)0x00000002) +#define CAN_FAFIFOR1_FFA30 ((uint32_t)0x00000004) +#define CAN_FAFIFOR1_FFA31 ((uint32_t)0x00000008) +#define CAN_FAFIFOR1_FFA32 ((uint32_t)0x00000010) +#define CAN_FAFIFOR1_FFA33 ((uint32_t)0x00000020) +#define CAN_FAFIFOR1_FFA34 ((uint32_t)0x00000040) +#define CAN_FAFIFOR1_FFA35 ((uint32_t)0x00000080) +#define CAN_FAFIFOR1_FFA36 ((uint32_t)0x00000100) +#define CAN_FAFIFOR1_FFA37 ((uint32_t)0x00000200) +#define CAN_FAFIFOR1_FFA38 ((uint32_t)0x00000400) +#define CAN_FAFIFOR1_FFA39 ((uint32_t)0x00000800) +#define CAN_FAFIFOR1_FFA40 ((uint32_t)0x00001000) +#define CAN_FAFIFOR1_FFA41 ((uint32_t)0x00002000) + +/******************** Bit definition for CAN_FWR register ********************/ +#define CAN_FWR_FACT0 ((uint32_t)0x00000001) +#define CAN_FWR_FACT1 ((uint32_t)0x00000002) +#define CAN_FWR_FACT2 ((uint32_t)0x00000004) +#define CAN_FWR_FACT3 ((uint32_t)0x00000008) +#define CAN_FWR_FACT4 ((uint32_t)0x00000010) +#define CAN_FWR_FACT5 ((uint32_t)0x00000020) +#define CAN_FWR_FACT6 ((uint32_t)0x00000040) +#define CAN_FWR_FACT7 ((uint32_t)0x00000080) +#define CAN_FWR_FACT8 ((uint32_t)0x00000100) +#define CAN_FWR_FACT9 ((uint32_t)0x00000200) +#define CAN_FWR_FACT10 ((uint32_t)0x00000400) +#define CAN_FWR_FACT11 ((uint32_t)0x00000800) +#define CAN_FWR_FACT12 ((uint32_t)0x00001000) +#define CAN_FWR_FACT13 ((uint32_t)0x00002000) +#define CAN_FWR_FACT14 ((uint32_t)0x00004000) +#define CAN_FWR_FACT15 ((uint32_t)0x00008000) +#define CAN_FWR_FACT16 ((uint32_t)0x00010000) +#define CAN_FWR_FACT17 ((uint32_t)0x00020000) +#define CAN_FWR_FACT18 ((uint32_t)0x00040000) +#define CAN_FWR_FACT19 ((uint32_t)0x00080000) +#define CAN_FWR_FACT20 ((uint32_t)0x00100000) +#define CAN_FWR_FACT21 ((uint32_t)0x00200000) +#define CAN_FWR_FACT22 ((uint32_t)0x00400000) +#define CAN_FWR_FACT23 ((uint32_t)0x00800000) +#define CAN_FWR_FACT24 ((uint32_t)0x01000000) +#define CAN_FWR_FACT25 ((uint32_t)0x02000000) +#define CAN_FWR_FACT26 ((uint32_t)0x04000000) +#define CAN_FWR_FACT27 ((uint32_t)0x08000000) + +/******************** Bit definition for CAN_FWR1 register ********************/ +#define CAN_FWR1_FACT28 ((uint32_t)0x00000001) +#define CAN_FWR1_FACT29 ((uint32_t)0x00000002) +#define CAN_FWR1_FACT30 ((uint32_t)0x00000004) +#define CAN_FWR1_FACT31 ((uint32_t)0x00000008) +#define CAN_FWR1_FACT32 ((uint32_t)0x00000010) +#define CAN_FWR1_FACT33 ((uint32_t)0x00000020) +#define CAN_FWR1_FACT34 ((uint32_t)0x00000040) +#define CAN_FWR1_FACT35 ((uint32_t)0x00000080) +#define CAN_FWR1_FACT36 ((uint32_t)0x00000100) +#define CAN_FWR1_FACT37 ((uint32_t)0x00000200) +#define CAN_FWR1_FACT38 ((uint32_t)0x00000400) +#define CAN_FWR1_FACT39 ((uint32_t)0x00000800) +#define CAN_FWR1_FACT40 ((uint32_t)0x00001000) +#define CAN_FWR1_FACT41 ((uint32_t)0x00002000) + +/******************** Bit definition for CAN_F0R1 register ********************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F1R1 register ********************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F2R1 register ********************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F3R1 register ********************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F4R1 register ********************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F5R1 register ********************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F6R1 register ********************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F7R1 register ********************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F8R1 register ********************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F9R1 register ********************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F10R1 register ********************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F11R1 register ********************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F12R1 register ********************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F13R1 register ********************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F14R1 register ********************/ +#define CAN_F14R1_FB0 ((uint32_t)0x00000001) +#define CAN_F14R1_FB1 ((uint32_t)0x00000002) +#define CAN_F14R1_FB2 ((uint32_t)0x00000004) +#define CAN_F14R1_FB3 ((uint32_t)0x00000008) +#define CAN_F14R1_FB4 ((uint32_t)0x00000010) +#define CAN_F14R1_FB5 ((uint32_t)0x00000020) +#define CAN_F14R1_FB6 ((uint32_t)0x00000040) +#define CAN_F14R1_FB7 ((uint32_t)0x00000080) +#define CAN_F14R1_FB8 ((uint32_t)0x00000100) +#define CAN_F14R1_FB9 ((uint32_t)0x00000200) +#define CAN_F14R1_FB10 ((uint32_t)0x00000400) +#define CAN_F14R1_FB11 ((uint32_t)0x00000800) +#define CAN_F14R1_FB12 ((uint32_t)0x00001000) +#define CAN_F14R1_FB13 ((uint32_t)0x00002000) +#define CAN_F14R1_FB14 ((uint32_t)0x00004000) +#define CAN_F14R1_FB15 ((uint32_t)0x00008000) +#define CAN_F14R1_FB16 ((uint32_t)0x00010000) +#define CAN_F14R1_FB17 ((uint32_t)0x00020000) +#define CAN_F14R1_FB18 ((uint32_t)0x00040000) +#define CAN_F14R1_FB19 ((uint32_t)0x00080000) +#define CAN_F14R1_FB20 ((uint32_t)0x00100000) +#define CAN_F14R1_FB21 ((uint32_t)0x00200000) +#define CAN_F14R1_FB22 ((uint32_t)0x00400000) +#define CAN_F14R1_FB23 ((uint32_t)0x00800000) +#define CAN_F14R1_FB24 ((uint32_t)0x01000000) +#define CAN_F14R1_FB25 ((uint32_t)0x02000000) +#define CAN_F14R1_FB26 ((uint32_t)0x04000000) +#define CAN_F14R1_FB27 ((uint32_t)0x08000000) +#define CAN_F14R1_FB28 ((uint32_t)0x10000000) +#define CAN_F14R1_FB29 ((uint32_t)0x20000000) +#define CAN_F14R1_FB30 ((uint32_t)0x40000000) +#define CAN_F14R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F15R1 register ********************/ +#define CAN_F15R1_FB0 ((uint32_t)0x00000001) +#define CAN_F15R1_FB1 ((uint32_t)0x00000002) +#define CAN_F15R1_FB2 ((uint32_t)0x00000004) +#define CAN_F15R1_FB3 ((uint32_t)0x00000008) +#define CAN_F15R1_FB4 ((uint32_t)0x00000010) +#define CAN_F15R1_FB5 ((uint32_t)0x00000020) +#define CAN_F15R1_FB6 ((uint32_t)0x00000040) +#define CAN_F15R1_FB7 ((uint32_t)0x00000080) +#define CAN_F15R1_FB8 ((uint32_t)0x00000100) +#define CAN_F15R1_FB9 ((uint32_t)0x00000200) +#define CAN_F15R1_FB10 ((uint32_t)0x00000400) +#define CAN_F15R1_FB11 ((uint32_t)0x00000800) +#define CAN_F15R1_FB12 ((uint32_t)0x00001000) +#define CAN_F15R1_FB13 ((uint32_t)0x00002000) +#define CAN_F15R1_FB14 ((uint32_t)0x00004000) +#define CAN_F15R1_FB15 ((uint32_t)0x00008000) +#define CAN_F15R1_FB16 ((uint32_t)0x00010000) +#define CAN_F15R1_FB17 ((uint32_t)0x00020000) +#define CAN_F15R1_FB18 ((uint32_t)0x00040000) +#define CAN_F15R1_FB19 ((uint32_t)0x00080000) +#define CAN_F15R1_FB20 ((uint32_t)0x00100000) +#define CAN_F15R1_FB21 ((uint32_t)0x00200000) +#define CAN_F15R1_FB22 ((uint32_t)0x00400000) +#define CAN_F15R1_FB23 ((uint32_t)0x00800000) +#define CAN_F15R1_FB24 ((uint32_t)0x01000000) +#define CAN_F15R1_FB25 ((uint32_t)0x02000000) +#define CAN_F15R1_FB26 ((uint32_t)0x04000000) +#define CAN_F15R1_FB27 ((uint32_t)0x08000000) +#define CAN_F15R1_FB28 ((uint32_t)0x10000000) +#define CAN_F15R1_FB29 ((uint32_t)0x20000000) +#define CAN_F15R1_FB30 ((uint32_t)0x40000000) +#define CAN_F15R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F16R1 register ********************/ +#define CAN_F16R1_FB0 ((uint32_t)0x00000001) +#define CAN_F16R1_FB1 ((uint32_t)0x00000002) +#define CAN_F16R1_FB2 ((uint32_t)0x00000004) +#define CAN_F16R1_FB3 ((uint32_t)0x00000008) +#define CAN_F16R1_FB4 ((uint32_t)0x00000010) +#define CAN_F16R1_FB5 ((uint32_t)0x00000020) +#define CAN_F16R1_FB6 ((uint32_t)0x00000040) +#define CAN_F16R1_FB7 ((uint32_t)0x00000080) +#define CAN_F16R1_FB8 ((uint32_t)0x00000100) +#define CAN_F16R1_FB9 ((uint32_t)0x00000200) +#define CAN_F16R1_FB10 ((uint32_t)0x00000400) +#define CAN_F16R1_FB11 ((uint32_t)0x00000800) +#define CAN_F16R1_FB12 ((uint32_t)0x00001000) +#define CAN_F16R1_FB13 ((uint32_t)0x00002000) +#define CAN_F16R1_FB14 ((uint32_t)0x00004000) +#define CAN_F16R1_FB15 ((uint32_t)0x00008000) +#define CAN_F16R1_FB16 ((uint32_t)0x00010000) +#define CAN_F16R1_FB17 ((uint32_t)0x00020000) +#define CAN_F16R1_FB18 ((uint32_t)0x00040000) +#define CAN_F16R1_FB19 ((uint32_t)0x00080000) +#define CAN_F16R1_FB20 ((uint32_t)0x00100000) +#define CAN_F16R1_FB21 ((uint32_t)0x00200000) +#define CAN_F16R1_FB22 ((uint32_t)0x00400000) +#define CAN_F16R1_FB23 ((uint32_t)0x00800000) +#define CAN_F16R1_FB24 ((uint32_t)0x01000000) +#define CAN_F16R1_FB25 ((uint32_t)0x02000000) +#define CAN_F16R1_FB26 ((uint32_t)0x04000000) +#define CAN_F16R1_FB27 ((uint32_t)0x08000000) +#define CAN_F16R1_FB28 ((uint32_t)0x10000000) +#define CAN_F16R1_FB29 ((uint32_t)0x20000000) +#define CAN_F16R1_FB30 ((uint32_t)0x40000000) +#define CAN_F16R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F17R1 register ********************/ +#define CAN_F17R1_FB0 ((uint32_t)0x00000001) +#define CAN_F17R1_FB1 ((uint32_t)0x00000002) +#define CAN_F17R1_FB2 ((uint32_t)0x00000004) +#define CAN_F17R1_FB3 ((uint32_t)0x00000008) +#define CAN_F17R1_FB4 ((uint32_t)0x00000010) +#define CAN_F17R1_FB5 ((uint32_t)0x00000020) +#define CAN_F17R1_FB6 ((uint32_t)0x00000040) +#define CAN_F17R1_FB7 ((uint32_t)0x00000080) +#define CAN_F17R1_FB8 ((uint32_t)0x00000100) +#define CAN_F17R1_FB9 ((uint32_t)0x00000200) +#define CAN_F17R1_FB10 ((uint32_t)0x00000400) +#define CAN_F17R1_FB11 ((uint32_t)0x00000800) +#define CAN_F17R1_FB12 ((uint32_t)0x00001000) +#define CAN_F17R1_FB13 ((uint32_t)0x00002000) +#define CAN_F17R1_FB14 ((uint32_t)0x00004000) +#define CAN_F17R1_FB15 ((uint32_t)0x00008000) +#define CAN_F17R1_FB16 ((uint32_t)0x00010000) +#define CAN_F17R1_FB17 ((uint32_t)0x00020000) +#define CAN_F17R1_FB18 ((uint32_t)0x00040000) +#define CAN_F17R1_FB19 ((uint32_t)0x00080000) +#define CAN_F17R1_FB20 ((uint32_t)0x00100000) +#define CAN_F17R1_FB21 ((uint32_t)0x00200000) +#define CAN_F17R1_FB22 ((uint32_t)0x00400000) +#define CAN_F17R1_FB23 ((uint32_t)0x00800000) +#define CAN_F17R1_FB24 ((uint32_t)0x01000000) +#define CAN_F17R1_FB25 ((uint32_t)0x02000000) +#define CAN_F17R1_FB26 ((uint32_t)0x04000000) +#define CAN_F17R1_FB27 ((uint32_t)0x08000000) +#define CAN_F17R1_FB28 ((uint32_t)0x10000000) +#define CAN_F17R1_FB29 ((uint32_t)0x20000000) +#define CAN_F17R1_FB30 ((uint32_t)0x40000000) +#define CAN_F17R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F18R1 register ********************/ +#define CAN_F18R1_FB0 ((uint32_t)0x00000001) +#define CAN_F18R1_FB1 ((uint32_t)0x00000002) +#define CAN_F18R1_FB2 ((uint32_t)0x00000004) +#define CAN_F18R1_FB3 ((uint32_t)0x00000008) +#define CAN_F18R1_FB4 ((uint32_t)0x00000010) +#define CAN_F18R1_FB5 ((uint32_t)0x00000020) +#define CAN_F18R1_FB6 ((uint32_t)0x00000040) +#define CAN_F18R1_FB7 ((uint32_t)0x00000080) +#define CAN_F18R1_FB8 ((uint32_t)0x00000100) +#define CAN_F18R1_FB9 ((uint32_t)0x00000200) +#define CAN_F18R1_FB10 ((uint32_t)0x00000400) +#define CAN_F18R1_FB11 ((uint32_t)0x00000800) +#define CAN_F18R1_FB12 ((uint32_t)0x00001000) +#define CAN_F18R1_FB13 ((uint32_t)0x00002000) +#define CAN_F18R1_FB14 ((uint32_t)0x00004000) +#define CAN_F18R1_FB15 ((uint32_t)0x00008000) +#define CAN_F18R1_FB16 ((uint32_t)0x00010000) +#define CAN_F18R1_FB17 ((uint32_t)0x00020000) +#define CAN_F18R1_FB18 ((uint32_t)0x00040000) +#define CAN_F18R1_FB19 ((uint32_t)0x00080000) +#define CAN_F18R1_FB20 ((uint32_t)0x00100000) +#define CAN_F18R1_FB21 ((uint32_t)0x00200000) +#define CAN_F18R1_FB22 ((uint32_t)0x00400000) +#define CAN_F18R1_FB23 ((uint32_t)0x00800000) +#define CAN_F18R1_FB24 ((uint32_t)0x01000000) +#define CAN_F18R1_FB25 ((uint32_t)0x02000000) +#define CAN_F18R1_FB26 ((uint32_t)0x04000000) +#define CAN_F18R1_FB27 ((uint32_t)0x08000000) +#define CAN_F18R1_FB28 ((uint32_t)0x10000000) +#define CAN_F18R1_FB29 ((uint32_t)0x20000000) +#define CAN_F18R1_FB30 ((uint32_t)0x40000000) +#define CAN_F18R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F19R1 register ********************/ +#define CAN_F19R1_FB0 ((uint32_t)0x00000001) +#define CAN_F19R1_FB1 ((uint32_t)0x00000002) +#define CAN_F19R1_FB2 ((uint32_t)0x00000004) +#define CAN_F19R1_FB3 ((uint32_t)0x00000008) +#define CAN_F19R1_FB4 ((uint32_t)0x00000010) +#define CAN_F19R1_FB5 ((uint32_t)0x00000020) +#define CAN_F19R1_FB6 ((uint32_t)0x00000040) +#define CAN_F19R1_FB7 ((uint32_t)0x00000080) +#define CAN_F19R1_FB8 ((uint32_t)0x00000100) +#define CAN_F19R1_FB9 ((uint32_t)0x00000200) +#define CAN_F19R1_FB10 ((uint32_t)0x00000400) +#define CAN_F19R1_FB11 ((uint32_t)0x00000800) +#define CAN_F19R1_FB12 ((uint32_t)0x00001000) +#define CAN_F19R1_FB13 ((uint32_t)0x00002000) +#define CAN_F19R1_FB14 ((uint32_t)0x00004000) +#define CAN_F19R1_FB15 ((uint32_t)0x00008000) +#define CAN_F19R1_FB16 ((uint32_t)0x00010000) +#define CAN_F19R1_FB17 ((uint32_t)0x00020000) +#define CAN_F19R1_FB18 ((uint32_t)0x00040000) +#define CAN_F19R1_FB19 ((uint32_t)0x00080000) +#define CAN_F19R1_FB20 ((uint32_t)0x00100000) +#define CAN_F19R1_FB21 ((uint32_t)0x00200000) +#define CAN_F19R1_FB22 ((uint32_t)0x00400000) +#define CAN_F19R1_FB23 ((uint32_t)0x00800000) +#define CAN_F19R1_FB24 ((uint32_t)0x01000000) +#define CAN_F19R1_FB25 ((uint32_t)0x02000000) +#define CAN_F19R1_FB26 ((uint32_t)0x04000000) +#define CAN_F19R1_FB27 ((uint32_t)0x08000000) +#define CAN_F19R1_FB28 ((uint32_t)0x10000000) +#define CAN_F19R1_FB29 ((uint32_t)0x20000000) +#define CAN_F19R1_FB30 ((uint32_t)0x40000000) +#define CAN_F19R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F20R1 register ********************/ +#define CAN_F20R1_FB0 ((uint32_t)0x00000001) +#define CAN_F20R1_FB1 ((uint32_t)0x00000002) +#define CAN_F20R1_FB2 ((uint32_t)0x00000004) +#define CAN_F20R1_FB3 ((uint32_t)0x00000008) +#define CAN_F20R1_FB4 ((uint32_t)0x00000010) +#define CAN_F20R1_FB5 ((uint32_t)0x00000020) +#define CAN_F20R1_FB6 ((uint32_t)0x00000040) +#define CAN_F20R1_FB7 ((uint32_t)0x00000080) +#define CAN_F20R1_FB8 ((uint32_t)0x00000100) +#define CAN_F20R1_FB9 ((uint32_t)0x00000200) +#define CAN_F20R1_FB10 ((uint32_t)0x00000400) +#define CAN_F20R1_FB11 ((uint32_t)0x00000800) +#define CAN_F20R1_FB12 ((uint32_t)0x00001000) +#define CAN_F20R1_FB13 ((uint32_t)0x00002000) +#define CAN_F20R1_FB14 ((uint32_t)0x00004000) +#define CAN_F20R1_FB15 ((uint32_t)0x00008000) +#define CAN_F20R1_FB16 ((uint32_t)0x00010000) +#define CAN_F20R1_FB17 ((uint32_t)0x00020000) +#define CAN_F20R1_FB18 ((uint32_t)0x00040000) +#define CAN_F20R1_FB19 ((uint32_t)0x00080000) +#define CAN_F20R1_FB20 ((uint32_t)0x00100000) +#define CAN_F20R1_FB21 ((uint32_t)0x00200000) +#define CAN_F20R1_FB22 ((uint32_t)0x00400000) +#define CAN_F20R1_FB23 ((uint32_t)0x00800000) +#define CAN_F20R1_FB24 ((uint32_t)0x01000000) +#define CAN_F20R1_FB25 ((uint32_t)0x02000000) +#define CAN_F20R1_FB26 ((uint32_t)0x04000000) +#define CAN_F20R1_FB27 ((uint32_t)0x08000000) +#define CAN_F20R1_FB28 ((uint32_t)0x10000000) +#define CAN_F20R1_FB29 ((uint32_t)0x20000000) +#define CAN_F20R1_FB30 ((uint32_t)0x40000000) +#define CAN_F20R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F21R1 register ********************/ +#define CAN_F21R1_FB0 ((uint32_t)0x00000001) +#define CAN_F21R1_FB1 ((uint32_t)0x00000002) +#define CAN_F21R1_FB2 ((uint32_t)0x00000004) +#define CAN_F21R1_FB3 ((uint32_t)0x00000008) +#define CAN_F21R1_FB4 ((uint32_t)0x00000010) +#define CAN_F21R1_FB5 ((uint32_t)0x00000020) +#define CAN_F21R1_FB6 ((uint32_t)0x00000040) +#define CAN_F21R1_FB7 ((uint32_t)0x00000080) +#define CAN_F21R1_FB8 ((uint32_t)0x00000100) +#define CAN_F21R1_FB9 ((uint32_t)0x00000200) +#define CAN_F21R1_FB10 ((uint32_t)0x00000400) +#define CAN_F21R1_FB11 ((uint32_t)0x00000800) +#define CAN_F21R1_FB12 ((uint32_t)0x00001000) +#define CAN_F21R1_FB13 ((uint32_t)0x00002000) +#define CAN_F21R1_FB14 ((uint32_t)0x00004000) +#define CAN_F21R1_FB15 ((uint32_t)0x00008000) +#define CAN_F21R1_FB16 ((uint32_t)0x00010000) +#define CAN_F21R1_FB17 ((uint32_t)0x00020000) +#define CAN_F21R1_FB18 ((uint32_t)0x00040000) +#define CAN_F21R1_FB19 ((uint32_t)0x00080000) +#define CAN_F21R1_FB20 ((uint32_t)0x00100000) +#define CAN_F21R1_FB21 ((uint32_t)0x00200000) +#define CAN_F21R1_FB22 ((uint32_t)0x00400000) +#define CAN_F21R1_FB23 ((uint32_t)0x00800000) +#define CAN_F21R1_FB24 ((uint32_t)0x01000000) +#define CAN_F21R1_FB25 ((uint32_t)0x02000000) +#define CAN_F21R1_FB26 ((uint32_t)0x04000000) +#define CAN_F21R1_FB27 ((uint32_t)0x08000000) +#define CAN_F21R1_FB28 ((uint32_t)0x10000000) +#define CAN_F21R1_FB29 ((uint32_t)0x20000000) +#define CAN_F21R1_FB30 ((uint32_t)0x40000000) +#define CAN_F21R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F22R1 register ********************/ +#define CAN_F22R1_FB0 ((uint32_t)0x00000001) +#define CAN_F22R1_FB1 ((uint32_t)0x00000002) +#define CAN_F22R1_FB2 ((uint32_t)0x00000004) +#define CAN_F22R1_FB3 ((uint32_t)0x00000008) +#define CAN_F22R1_FB4 ((uint32_t)0x00000010) +#define CAN_F22R1_FB5 ((uint32_t)0x00000020) +#define CAN_F22R1_FB6 ((uint32_t)0x00000040) +#define CAN_F22R1_FB7 ((uint32_t)0x00000080) +#define CAN_F22R1_FB8 ((uint32_t)0x00000100) +#define CAN_F22R1_FB9 ((uint32_t)0x00000200) +#define CAN_F22R1_FB10 ((uint32_t)0x00000400) +#define CAN_F22R1_FB11 ((uint32_t)0x00000800) +#define CAN_F22R1_FB12 ((uint32_t)0x00001000) +#define CAN_F22R1_FB13 ((uint32_t)0x00002000) +#define CAN_F22R1_FB14 ((uint32_t)0x00004000) +#define CAN_F22R1_FB15 ((uint32_t)0x00008000) +#define CAN_F22R1_FB16 ((uint32_t)0x00010000) +#define CAN_F22R1_FB17 ((uint32_t)0x00020000) +#define CAN_F22R1_FB18 ((uint32_t)0x00040000) +#define CAN_F22R1_FB19 ((uint32_t)0x00080000) +#define CAN_F22R1_FB20 ((uint32_t)0x00100000) +#define CAN_F22R1_FB21 ((uint32_t)0x00200000) +#define CAN_F22R1_FB22 ((uint32_t)0x00400000) +#define CAN_F22R1_FB23 ((uint32_t)0x00800000) +#define CAN_F22R1_FB24 ((uint32_t)0x01000000) +#define CAN_F22R1_FB25 ((uint32_t)0x02000000) +#define CAN_F22R1_FB26 ((uint32_t)0x04000000) +#define CAN_F22R1_FB27 ((uint32_t)0x08000000) +#define CAN_F22R1_FB28 ((uint32_t)0x10000000) +#define CAN_F22R1_FB29 ((uint32_t)0x20000000) +#define CAN_F22R1_FB30 ((uint32_t)0x40000000) +#define CAN_F22R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F23R1 register ********************/ +#define CAN_F23R1_FB0 ((uint32_t)0x00000001) +#define CAN_F23R1_FB1 ((uint32_t)0x00000002) +#define CAN_F23R1_FB2 ((uint32_t)0x00000004) +#define CAN_F23R1_FB3 ((uint32_t)0x00000008) +#define CAN_F23R1_FB4 ((uint32_t)0x00000010) +#define CAN_F23R1_FB5 ((uint32_t)0x00000020) +#define CAN_F23R1_FB6 ((uint32_t)0x00000040) +#define CAN_F23R1_FB7 ((uint32_t)0x00000080) +#define CAN_F23R1_FB8 ((uint32_t)0x00000100) +#define CAN_F23R1_FB9 ((uint32_t)0x00000200) +#define CAN_F23R1_FB10 ((uint32_t)0x00000400) +#define CAN_F23R1_FB11 ((uint32_t)0x00000800) +#define CAN_F23R1_FB12 ((uint32_t)0x00001000) +#define CAN_F23R1_FB13 ((uint32_t)0x00002000) +#define CAN_F23R1_FB14 ((uint32_t)0x00004000) +#define CAN_F23R1_FB15 ((uint32_t)0x00008000) +#define CAN_F23R1_FB16 ((uint32_t)0x00010000) +#define CAN_F23R1_FB17 ((uint32_t)0x00020000) +#define CAN_F23R1_FB18 ((uint32_t)0x00040000) +#define CAN_F23R1_FB19 ((uint32_t)0x00080000) +#define CAN_F23R1_FB20 ((uint32_t)0x00100000) +#define CAN_F23R1_FB21 ((uint32_t)0x00200000) +#define CAN_F23R1_FB22 ((uint32_t)0x00400000) +#define CAN_F23R1_FB23 ((uint32_t)0x00800000) +#define CAN_F23R1_FB24 ((uint32_t)0x01000000) +#define CAN_F23R1_FB25 ((uint32_t)0x02000000) +#define CAN_F23R1_FB26 ((uint32_t)0x04000000) +#define CAN_F23R1_FB27 ((uint32_t)0x08000000) +#define CAN_F23R1_FB28 ((uint32_t)0x10000000) +#define CAN_F23R1_FB29 ((uint32_t)0x20000000) +#define CAN_F23R1_FB30 ((uint32_t)0x40000000) +#define CAN_F23R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F24R1 register ********************/ +#define CAN_F24R1_FB0 ((uint32_t)0x00000001) +#define CAN_F24R1_FB1 ((uint32_t)0x00000002) +#define CAN_F24R1_FB2 ((uint32_t)0x00000004) +#define CAN_F24R1_FB3 ((uint32_t)0x00000008) +#define CAN_F24R1_FB4 ((uint32_t)0x00000010) +#define CAN_F24R1_FB5 ((uint32_t)0x00000020) +#define CAN_F24R1_FB6 ((uint32_t)0x00000040) +#define CAN_F24R1_FB7 ((uint32_t)0x00000080) +#define CAN_F24R1_FB8 ((uint32_t)0x00000100) +#define CAN_F24R1_FB9 ((uint32_t)0x00000200) +#define CAN_F24R1_FB10 ((uint32_t)0x00000400) +#define CAN_F24R1_FB11 ((uint32_t)0x00000800) +#define CAN_F24R1_FB12 ((uint32_t)0x00001000) +#define CAN_F24R1_FB13 ((uint32_t)0x00002000) +#define CAN_F24R1_FB14 ((uint32_t)0x00004000) +#define CAN_F24R1_FB15 ((uint32_t)0x00008000) +#define CAN_F24R1_FB16 ((uint32_t)0x00010000) +#define CAN_F24R1_FB17 ((uint32_t)0x00020000) +#define CAN_F24R1_FB18 ((uint32_t)0x00040000) +#define CAN_F24R1_FB19 ((uint32_t)0x00080000) +#define CAN_F24R1_FB20 ((uint32_t)0x00100000) +#define CAN_F24R1_FB21 ((uint32_t)0x00200000) +#define CAN_F24R1_FB22 ((uint32_t)0x00400000) +#define CAN_F24R1_FB23 ((uint32_t)0x00800000) +#define CAN_F24R1_FB24 ((uint32_t)0x01000000) +#define CAN_F24R1_FB25 ((uint32_t)0x02000000) +#define CAN_F24R1_FB26 ((uint32_t)0x04000000) +#define CAN_F24R1_FB27 ((uint32_t)0x08000000) +#define CAN_F24R1_FB28 ((uint32_t)0x10000000) +#define CAN_F24R1_FB29 ((uint32_t)0x20000000) +#define CAN_F24R1_FB30 ((uint32_t)0x40000000) +#define CAN_F24R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F25R1 register ********************/ +#define CAN_F25R1_FB0 ((uint32_t)0x00000001) +#define CAN_F25R1_FB1 ((uint32_t)0x00000002) +#define CAN_F25R1_FB2 ((uint32_t)0x00000004) +#define CAN_F25R1_FB3 ((uint32_t)0x00000008) +#define CAN_F25R1_FB4 ((uint32_t)0x00000010) +#define CAN_F25R1_FB5 ((uint32_t)0x00000020) +#define CAN_F25R1_FB6 ((uint32_t)0x00000040) +#define CAN_F25R1_FB7 ((uint32_t)0x00000080) +#define CAN_F25R1_FB8 ((uint32_t)0x00000100) +#define CAN_F25R1_FB9 ((uint32_t)0x00000200) +#define CAN_F25R1_FB10 ((uint32_t)0x00000400) +#define CAN_F25R1_FB11 ((uint32_t)0x00000800) +#define CAN_F25R1_FB12 ((uint32_t)0x00001000) +#define CAN_F25R1_FB13 ((uint32_t)0x00002000) +#define CAN_F25R1_FB14 ((uint32_t)0x00004000) +#define CAN_F25R1_FB15 ((uint32_t)0x00008000) +#define CAN_F25R1_FB16 ((uint32_t)0x00010000) +#define CAN_F25R1_FB17 ((uint32_t)0x00020000) +#define CAN_F25R1_FB18 ((uint32_t)0x00040000) +#define CAN_F25R1_FB19 ((uint32_t)0x00080000) +#define CAN_F25R1_FB20 ((uint32_t)0x00100000) +#define CAN_F25R1_FB21 ((uint32_t)0x00200000) +#define CAN_F25R1_FB22 ((uint32_t)0x00400000) +#define CAN_F25R1_FB23 ((uint32_t)0x00800000) +#define CAN_F25R1_FB24 ((uint32_t)0x01000000) +#define CAN_F25R1_FB25 ((uint32_t)0x02000000) +#define CAN_F25R1_FB26 ((uint32_t)0x04000000) +#define CAN_F25R1_FB27 ((uint32_t)0x08000000) +#define CAN_F25R1_FB28 ((uint32_t)0x10000000) +#define CAN_F25R1_FB29 ((uint32_t)0x20000000) +#define CAN_F25R1_FB30 ((uint32_t)0x40000000) +#define CAN_F25R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F26R1 register ********************/ +#define CAN_F26R1_FB0 ((uint32_t)0x00000001) +#define CAN_F26R1_FB1 ((uint32_t)0x00000002) +#define CAN_F26R1_FB2 ((uint32_t)0x00000004) +#define CAN_F26R1_FB3 ((uint32_t)0x00000008) +#define CAN_F26R1_FB4 ((uint32_t)0x00000010) +#define CAN_F26R1_FB5 ((uint32_t)0x00000020) +#define CAN_F26R1_FB6 ((uint32_t)0x00000040) +#define CAN_F26R1_FB7 ((uint32_t)0x00000080) +#define CAN_F26R1_FB8 ((uint32_t)0x00000100) +#define CAN_F26R1_FB9 ((uint32_t)0x00000200) +#define CAN_F26R1_FB10 ((uint32_t)0x00000400) +#define CAN_F26R1_FB11 ((uint32_t)0x00000800) +#define CAN_F26R1_FB12 ((uint32_t)0x00001000) +#define CAN_F26R1_FB13 ((uint32_t)0x00002000) +#define CAN_F26R1_FB14 ((uint32_t)0x00004000) +#define CAN_F26R1_FB15 ((uint32_t)0x00008000) +#define CAN_F26R1_FB16 ((uint32_t)0x00010000) +#define CAN_F26R1_FB17 ((uint32_t)0x00020000) +#define CAN_F26R1_FB18 ((uint32_t)0x00040000) +#define CAN_F26R1_FB19 ((uint32_t)0x00080000) +#define CAN_F26R1_FB20 ((uint32_t)0x00100000) +#define CAN_F26R1_FB21 ((uint32_t)0x00200000) +#define CAN_F26R1_FB22 ((uint32_t)0x00400000) +#define CAN_F26R1_FB23 ((uint32_t)0x00800000) +#define CAN_F26R1_FB24 ((uint32_t)0x01000000) +#define CAN_F26R1_FB25 ((uint32_t)0x02000000) +#define CAN_F26R1_FB26 ((uint32_t)0x04000000) +#define CAN_F26R1_FB27 ((uint32_t)0x08000000) +#define CAN_F26R1_FB28 ((uint32_t)0x10000000) +#define CAN_F26R1_FB29 ((uint32_t)0x20000000) +#define CAN_F26R1_FB30 ((uint32_t)0x40000000) +#define CAN_F26R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F27R1 register ********************/ +#define CAN_F27R1_FB0 ((uint32_t)0x00000001) +#define CAN_F27R1_FB1 ((uint32_t)0x00000002) +#define CAN_F27R1_FB2 ((uint32_t)0x00000004) +#define CAN_F27R1_FB3 ((uint32_t)0x00000008) +#define CAN_F27R1_FB4 ((uint32_t)0x00000010) +#define CAN_F27R1_FB5 ((uint32_t)0x00000020) +#define CAN_F27R1_FB6 ((uint32_t)0x00000040) +#define CAN_F27R1_FB7 ((uint32_t)0x00000080) +#define CAN_F27R1_FB8 ((uint32_t)0x00000100) +#define CAN_F27R1_FB9 ((uint32_t)0x00000200) +#define CAN_F27R1_FB10 ((uint32_t)0x00000400) +#define CAN_F27R1_FB11 ((uint32_t)0x00000800) +#define CAN_F27R1_FB12 ((uint32_t)0x00001000) +#define CAN_F27R1_FB13 ((uint32_t)0x00002000) +#define CAN_F27R1_FB14 ((uint32_t)0x00004000) +#define CAN_F27R1_FB15 ((uint32_t)0x00008000) +#define CAN_F27R1_FB16 ((uint32_t)0x00010000) +#define CAN_F27R1_FB17 ((uint32_t)0x00020000) +#define CAN_F27R1_FB18 ((uint32_t)0x00040000) +#define CAN_F27R1_FB19 ((uint32_t)0x00080000) +#define CAN_F27R1_FB20 ((uint32_t)0x00100000) +#define CAN_F27R1_FB21 ((uint32_t)0x00200000) +#define CAN_F27R1_FB22 ((uint32_t)0x00400000) +#define CAN_F27R1_FB23 ((uint32_t)0x00800000) +#define CAN_F27R1_FB24 ((uint32_t)0x01000000) +#define CAN_F27R1_FB25 ((uint32_t)0x02000000) +#define CAN_F27R1_FB26 ((uint32_t)0x04000000) +#define CAN_F27R1_FB27 ((uint32_t)0x08000000) +#define CAN_F27R1_FB28 ((uint32_t)0x10000000) +#define CAN_F27R1_FB29 ((uint32_t)0x20000000) +#define CAN_F27R1_FB30 ((uint32_t)0x40000000) +#define CAN_F27R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F28R1 register ********************/ +#define CAN_F28R1_FB0 ((uint32_t)0x00000001) +#define CAN_F28R1_FB1 ((uint32_t)0x00000002) +#define CAN_F28R1_FB2 ((uint32_t)0x00000004) +#define CAN_F28R1_FB3 ((uint32_t)0x00000008) +#define CAN_F28R1_FB4 ((uint32_t)0x00000010) +#define CAN_F28R1_FB5 ((uint32_t)0x00000020) +#define CAN_F28R1_FB6 ((uint32_t)0x00000040) +#define CAN_F28R1_FB7 ((uint32_t)0x00000080) +#define CAN_F28R1_FB8 ((uint32_t)0x00000100) +#define CAN_F28R1_FB9 ((uint32_t)0x00000200) +#define CAN_F28R1_FB10 ((uint32_t)0x00000400) +#define CAN_F28R1_FB11 ((uint32_t)0x00000800) +#define CAN_F28R1_FB12 ((uint32_t)0x00001000) +#define CAN_F28R1_FB13 ((uint32_t)0x00002000) +#define CAN_F28R1_FB14 ((uint32_t)0x00004000) +#define CAN_F28R1_FB15 ((uint32_t)0x00008000) +#define CAN_F28R1_FB16 ((uint32_t)0x00010000) +#define CAN_F28R1_FB17 ((uint32_t)0x00020000) +#define CAN_F28R1_FB18 ((uint32_t)0x00040000) +#define CAN_F28R1_FB19 ((uint32_t)0x00080000) +#define CAN_F28R1_FB20 ((uint32_t)0x00100000) +#define CAN_F28R1_FB21 ((uint32_t)0x00200000) +#define CAN_F28R1_FB22 ((uint32_t)0x00400000) +#define CAN_F28R1_FB23 ((uint32_t)0x00800000) +#define CAN_F28R1_FB24 ((uint32_t)0x01000000) +#define CAN_F28R1_FB25 ((uint32_t)0x02000000) +#define CAN_F28R1_FB26 ((uint32_t)0x04000000) +#define CAN_F28R1_FB27 ((uint32_t)0x08000000) +#define CAN_F28R1_FB28 ((uint32_t)0x10000000) +#define CAN_F28R1_FB29 ((uint32_t)0x20000000) +#define CAN_F28R1_FB30 ((uint32_t)0x40000000) +#define CAN_F28R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F29R1 register ********************/ +#define CAN_F29R1_FB0 ((uint32_t)0x00000001) +#define CAN_F29R1_FB1 ((uint32_t)0x00000002) +#define CAN_F29R1_FB2 ((uint32_t)0x00000004) +#define CAN_F29R1_FB3 ((uint32_t)0x00000008) +#define CAN_F29R1_FB4 ((uint32_t)0x00000010) +#define CAN_F29R1_FB5 ((uint32_t)0x00000020) +#define CAN_F29R1_FB6 ((uint32_t)0x00000040) +#define CAN_F29R1_FB7 ((uint32_t)0x00000080) +#define CAN_F29R1_FB8 ((uint32_t)0x00000100) +#define CAN_F29R1_FB9 ((uint32_t)0x00000200) +#define CAN_F29R1_FB10 ((uint32_t)0x00000400) +#define CAN_F29R1_FB11 ((uint32_t)0x00000800) +#define CAN_F29R1_FB12 ((uint32_t)0x00001000) +#define CAN_F29R1_FB13 ((uint32_t)0x00002000) +#define CAN_F29R1_FB14 ((uint32_t)0x00004000) +#define CAN_F29R1_FB15 ((uint32_t)0x00008000) +#define CAN_F29R1_FB16 ((uint32_t)0x00010000) +#define CAN_F29R1_FB17 ((uint32_t)0x00020000) +#define CAN_F29R1_FB18 ((uint32_t)0x00040000) +#define CAN_F29R1_FB19 ((uint32_t)0x00080000) +#define CAN_F29R1_FB20 ((uint32_t)0x00100000) +#define CAN_F29R1_FB21 ((uint32_t)0x00200000) +#define CAN_F29R1_FB22 ((uint32_t)0x00400000) +#define CAN_F29R1_FB23 ((uint32_t)0x00800000) +#define CAN_F29R1_FB24 ((uint32_t)0x01000000) +#define CAN_F29R1_FB25 ((uint32_t)0x02000000) +#define CAN_F29R1_FB26 ((uint32_t)0x04000000) +#define CAN_F29R1_FB27 ((uint32_t)0x08000000) +#define CAN_F29R1_FB28 ((uint32_t)0x10000000) +#define CAN_F29R1_FB29 ((uint32_t)0x20000000) +#define CAN_F29R1_FB30 ((uint32_t)0x40000000) +#define CAN_F29R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F30R1 register ********************/ +#define CAN_F30R1_FB0 ((uint32_t)0x00000001) +#define CAN_F30R1_FB1 ((uint32_t)0x00000002) +#define CAN_F30R1_FB2 ((uint32_t)0x00000004) +#define CAN_F30R1_FB3 ((uint32_t)0x00000008) +#define CAN_F30R1_FB4 ((uint32_t)0x00000010) +#define CAN_F30R1_FB5 ((uint32_t)0x00000020) +#define CAN_F30R1_FB6 ((uint32_t)0x00000040) +#define CAN_F30R1_FB7 ((uint32_t)0x00000080) +#define CAN_F30R1_FB8 ((uint32_t)0x00000100) +#define CAN_F30R1_FB9 ((uint32_t)0x00000200) +#define CAN_F30R1_FB10 ((uint32_t)0x00000400) +#define CAN_F30R1_FB11 ((uint32_t)0x00000800) +#define CAN_F30R1_FB12 ((uint32_t)0x00001000) +#define CAN_F30R1_FB13 ((uint32_t)0x00002000) +#define CAN_F30R1_FB14 ((uint32_t)0x00004000) +#define CAN_F30R1_FB15 ((uint32_t)0x00008000) +#define CAN_F30R1_FB16 ((uint32_t)0x00010000) +#define CAN_F30R1_FB17 ((uint32_t)0x00020000) +#define CAN_F30R1_FB18 ((uint32_t)0x00040000) +#define CAN_F30R1_FB19 ((uint32_t)0x00080000) +#define CAN_F30R1_FB20 ((uint32_t)0x00100000) +#define CAN_F30R1_FB21 ((uint32_t)0x00200000) +#define CAN_F30R1_FB22 ((uint32_t)0x00400000) +#define CAN_F30R1_FB23 ((uint32_t)0x00800000) +#define CAN_F30R1_FB24 ((uint32_t)0x01000000) +#define CAN_F30R1_FB25 ((uint32_t)0x02000000) +#define CAN_F30R1_FB26 ((uint32_t)0x04000000) +#define CAN_F30R1_FB27 ((uint32_t)0x08000000) +#define CAN_F30R1_FB28 ((uint32_t)0x10000000) +#define CAN_F30R1_FB29 ((uint32_t)0x20000000) +#define CAN_F30R1_FB30 ((uint32_t)0x40000000) +#define CAN_F30R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F31R1 register ********************/ +#define CAN_F31R1_FB0 ((uint32_t)0x00000001) +#define CAN_F31R1_FB1 ((uint32_t)0x00000002) +#define CAN_F31R1_FB2 ((uint32_t)0x00000004) +#define CAN_F31R1_FB3 ((uint32_t)0x00000008) +#define CAN_F31R1_FB4 ((uint32_t)0x00000010) +#define CAN_F31R1_FB5 ((uint32_t)0x00000020) +#define CAN_F31R1_FB6 ((uint32_t)0x00000040) +#define CAN_F31R1_FB7 ((uint32_t)0x00000080) +#define CAN_F31R1_FB8 ((uint32_t)0x00000100) +#define CAN_F31R1_FB9 ((uint32_t)0x00000200) +#define CAN_F31R1_FB10 ((uint32_t)0x00000400) +#define CAN_F31R1_FB11 ((uint32_t)0x00000800) +#define CAN_F31R1_FB12 ((uint32_t)0x00001000) +#define CAN_F31R1_FB13 ((uint32_t)0x00002000) +#define CAN_F31R1_FB14 ((uint32_t)0x00004000) +#define CAN_F31R1_FB15 ((uint32_t)0x00008000) +#define CAN_F31R1_FB16 ((uint32_t)0x00010000) +#define CAN_F31R1_FB17 ((uint32_t)0x00020000) +#define CAN_F31R1_FB18 ((uint32_t)0x00040000) +#define CAN_F31R1_FB19 ((uint32_t)0x00080000) +#define CAN_F31R1_FB20 ((uint32_t)0x00100000) +#define CAN_F31R1_FB21 ((uint32_t)0x00200000) +#define CAN_F31R1_FB22 ((uint32_t)0x00400000) +#define CAN_F31R1_FB23 ((uint32_t)0x00800000) +#define CAN_F31R1_FB24 ((uint32_t)0x01000000) +#define CAN_F31R1_FB25 ((uint32_t)0x02000000) +#define CAN_F31R1_FB26 ((uint32_t)0x04000000) +#define CAN_F31R1_FB27 ((uint32_t)0x08000000) +#define CAN_F31R1_FB28 ((uint32_t)0x10000000) +#define CAN_F31R1_FB29 ((uint32_t)0x20000000) +#define CAN_F31R1_FB30 ((uint32_t)0x40000000) +#define CAN_F31R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F32R1 register ********************/ +#define CAN_F32R1_FB0 ((uint32_t)0x00000001) +#define CAN_F32R1_FB1 ((uint32_t)0x00000002) +#define CAN_F32R1_FB2 ((uint32_t)0x00000004) +#define CAN_F32R1_FB3 ((uint32_t)0x00000008) +#define CAN_F32R1_FB4 ((uint32_t)0x00000010) +#define CAN_F32R1_FB5 ((uint32_t)0x00000020) +#define CAN_F32R1_FB6 ((uint32_t)0x00000040) +#define CAN_F32R1_FB7 ((uint32_t)0x00000080) +#define CAN_F32R1_FB8 ((uint32_t)0x00000100) +#define CAN_F32R1_FB9 ((uint32_t)0x00000200) +#define CAN_F32R1_FB10 ((uint32_t)0x00000400) +#define CAN_F32R1_FB11 ((uint32_t)0x00000800) +#define CAN_F32R1_FB12 ((uint32_t)0x00001000) +#define CAN_F32R1_FB13 ((uint32_t)0x00002000) +#define CAN_F32R1_FB14 ((uint32_t)0x00004000) +#define CAN_F32R1_FB15 ((uint32_t)0x00008000) +#define CAN_F32R1_FB16 ((uint32_t)0x00010000) +#define CAN_F32R1_FB17 ((uint32_t)0x00020000) +#define CAN_F32R1_FB18 ((uint32_t)0x00040000) +#define CAN_F32R1_FB19 ((uint32_t)0x00080000) +#define CAN_F32R1_FB20 ((uint32_t)0x00100000) +#define CAN_F32R1_FB21 ((uint32_t)0x00200000) +#define CAN_F32R1_FB22 ((uint32_t)0x00400000) +#define CAN_F32R1_FB23 ((uint32_t)0x00800000) +#define CAN_F32R1_FB24 ((uint32_t)0x01000000) +#define CAN_F32R1_FB25 ((uint32_t)0x02000000) +#define CAN_F32R1_FB26 ((uint32_t)0x04000000) +#define CAN_F32R1_FB27 ((uint32_t)0x08000000) +#define CAN_F32R1_FB28 ((uint32_t)0x10000000) +#define CAN_F32R1_FB29 ((uint32_t)0x20000000) +#define CAN_F32R1_FB30 ((uint32_t)0x40000000) +#define CAN_F32R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F33R1 register ********************/ +#define CAN_F33R1_FB0 ((uint32_t)0x00000001) +#define CAN_F33R1_FB1 ((uint32_t)0x00000002) +#define CAN_F33R1_FB2 ((uint32_t)0x00000004) +#define CAN_F33R1_FB3 ((uint32_t)0x00000008) +#define CAN_F33R1_FB4 ((uint32_t)0x00000010) +#define CAN_F33R1_FB5 ((uint32_t)0x00000020) +#define CAN_F33R1_FB6 ((uint32_t)0x00000040) +#define CAN_F33R1_FB7 ((uint32_t)0x00000080) +#define CAN_F33R1_FB8 ((uint32_t)0x00000100) +#define CAN_F33R1_FB9 ((uint32_t)0x00000200) +#define CAN_F33R1_FB10 ((uint32_t)0x00000400) +#define CAN_F33R1_FB11 ((uint32_t)0x00000800) +#define CAN_F33R1_FB12 ((uint32_t)0x00001000) +#define CAN_F33R1_FB13 ((uint32_t)0x00002000) +#define CAN_F33R1_FB14 ((uint32_t)0x00004000) +#define CAN_F33R1_FB15 ((uint32_t)0x00008000) +#define CAN_F33R1_FB16 ((uint32_t)0x00010000) +#define CAN_F33R1_FB17 ((uint32_t)0x00020000) +#define CAN_F33R1_FB18 ((uint32_t)0x00040000) +#define CAN_F33R1_FB19 ((uint32_t)0x00080000) +#define CAN_F33R1_FB20 ((uint32_t)0x00100000) +#define CAN_F33R1_FB21 ((uint32_t)0x00200000) +#define CAN_F33R1_FB22 ((uint32_t)0x00400000) +#define CAN_F33R1_FB23 ((uint32_t)0x00800000) +#define CAN_F33R1_FB24 ((uint32_t)0x01000000) +#define CAN_F33R1_FB25 ((uint32_t)0x02000000) +#define CAN_F33R1_FB26 ((uint32_t)0x04000000) +#define CAN_F33R1_FB27 ((uint32_t)0x08000000) +#define CAN_F33R1_FB28 ((uint32_t)0x10000000) +#define CAN_F33R1_FB29 ((uint32_t)0x20000000) +#define CAN_F33R1_FB30 ((uint32_t)0x40000000) +#define CAN_F33R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F34R1 register ********************/ +#define CAN_F34R1_FB0 ((uint32_t)0x00000001) +#define CAN_F34R1_FB1 ((uint32_t)0x00000002) +#define CAN_F34R1_FB2 ((uint32_t)0x00000004) +#define CAN_F34R1_FB3 ((uint32_t)0x00000008) +#define CAN_F34R1_FB4 ((uint32_t)0x00000010) +#define CAN_F34R1_FB5 ((uint32_t)0x00000020) +#define CAN_F34R1_FB6 ((uint32_t)0x00000040) +#define CAN_F34R1_FB7 ((uint32_t)0x00000080) +#define CAN_F34R1_FB8 ((uint32_t)0x00000100) +#define CAN_F34R1_FB9 ((uint32_t)0x00000200) +#define CAN_F34R1_FB10 ((uint32_t)0x00000400) +#define CAN_F34R1_FB11 ((uint32_t)0x00000800) +#define CAN_F34R1_FB12 ((uint32_t)0x00001000) +#define CAN_F34R1_FB13 ((uint32_t)0x00002000) +#define CAN_F34R1_FB14 ((uint32_t)0x00004000) +#define CAN_F34R1_FB15 ((uint32_t)0x00008000) +#define CAN_F34R1_FB16 ((uint32_t)0x00010000) +#define CAN_F34R1_FB17 ((uint32_t)0x00020000) +#define CAN_F34R1_FB18 ((uint32_t)0x00040000) +#define CAN_F34R1_FB19 ((uint32_t)0x00080000) +#define CAN_F34R1_FB20 ((uint32_t)0x00100000) +#define CAN_F34R1_FB21 ((uint32_t)0x00200000) +#define CAN_F34R1_FB22 ((uint32_t)0x00400000) +#define CAN_F34R1_FB23 ((uint32_t)0x00800000) +#define CAN_F34R1_FB24 ((uint32_t)0x01000000) +#define CAN_F34R1_FB25 ((uint32_t)0x02000000) +#define CAN_F34R1_FB26 ((uint32_t)0x04000000) +#define CAN_F34R1_FB27 ((uint32_t)0x08000000) +#define CAN_F34R1_FB28 ((uint32_t)0x10000000) +#define CAN_F34R1_FB29 ((uint32_t)0x20000000) +#define CAN_F34R1_FB30 ((uint32_t)0x40000000) +#define CAN_F34R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F35R1 register ********************/ +#define CAN_F35R1_FB0 ((uint32_t)0x00000001) +#define CAN_F35R1_FB1 ((uint32_t)0x00000002) +#define CAN_F35R1_FB2 ((uint32_t)0x00000004) +#define CAN_F35R1_FB3 ((uint32_t)0x00000008) +#define CAN_F35R1_FB4 ((uint32_t)0x00000010) +#define CAN_F35R1_FB5 ((uint32_t)0x00000020) +#define CAN_F35R1_FB6 ((uint32_t)0x00000040) +#define CAN_F35R1_FB7 ((uint32_t)0x00000080) +#define CAN_F35R1_FB8 ((uint32_t)0x00000100) +#define CAN_F35R1_FB9 ((uint32_t)0x00000200) +#define CAN_F35R1_FB10 ((uint32_t)0x00000400) +#define CAN_F35R1_FB11 ((uint32_t)0x00000800) +#define CAN_F35R1_FB12 ((uint32_t)0x00001000) +#define CAN_F35R1_FB13 ((uint32_t)0x00002000) +#define CAN_F35R1_FB14 ((uint32_t)0x00004000) +#define CAN_F35R1_FB15 ((uint32_t)0x00008000) +#define CAN_F35R1_FB16 ((uint32_t)0x00010000) +#define CAN_F35R1_FB17 ((uint32_t)0x00020000) +#define CAN_F35R1_FB18 ((uint32_t)0x00040000) +#define CAN_F35R1_FB19 ((uint32_t)0x00080000) +#define CAN_F35R1_FB20 ((uint32_t)0x00100000) +#define CAN_F35R1_FB21 ((uint32_t)0x00200000) +#define CAN_F35R1_FB22 ((uint32_t)0x00400000) +#define CAN_F35R1_FB23 ((uint32_t)0x00800000) +#define CAN_F35R1_FB24 ((uint32_t)0x01000000) +#define CAN_F35R1_FB25 ((uint32_t)0x02000000) +#define CAN_F35R1_FB26 ((uint32_t)0x04000000) +#define CAN_F35R1_FB27 ((uint32_t)0x08000000) +#define CAN_F35R1_FB28 ((uint32_t)0x10000000) +#define CAN_F35R1_FB29 ((uint32_t)0x20000000) +#define CAN_F35R1_FB30 ((uint32_t)0x40000000) +#define CAN_F35R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F36R1 register ********************/ +#define CAN_F36R1_FB0 ((uint32_t)0x00000001) +#define CAN_F36R1_FB1 ((uint32_t)0x00000002) +#define CAN_F36R1_FB2 ((uint32_t)0x00000004) +#define CAN_F36R1_FB3 ((uint32_t)0x00000008) +#define CAN_F36R1_FB4 ((uint32_t)0x00000010) +#define CAN_F36R1_FB5 ((uint32_t)0x00000020) +#define CAN_F36R1_FB6 ((uint32_t)0x00000040) +#define CAN_F36R1_FB7 ((uint32_t)0x00000080) +#define CAN_F36R1_FB8 ((uint32_t)0x00000100) +#define CAN_F36R1_FB9 ((uint32_t)0x00000200) +#define CAN_F36R1_FB10 ((uint32_t)0x00000400) +#define CAN_F36R1_FB11 ((uint32_t)0x00000800) +#define CAN_F36R1_FB12 ((uint32_t)0x00001000) +#define CAN_F36R1_FB13 ((uint32_t)0x00002000) +#define CAN_F36R1_FB14 ((uint32_t)0x00004000) +#define CAN_F36R1_FB15 ((uint32_t)0x00008000) +#define CAN_F36R1_FB16 ((uint32_t)0x00010000) +#define CAN_F36R1_FB17 ((uint32_t)0x00020000) +#define CAN_F36R1_FB18 ((uint32_t)0x00040000) +#define CAN_F36R1_FB19 ((uint32_t)0x00080000) +#define CAN_F36R1_FB20 ((uint32_t)0x00100000) +#define CAN_F36R1_FB21 ((uint32_t)0x00200000) +#define CAN_F36R1_FB22 ((uint32_t)0x00400000) +#define CAN_F36R1_FB23 ((uint32_t)0x00800000) +#define CAN_F36R1_FB24 ((uint32_t)0x01000000) +#define CAN_F36R1_FB25 ((uint32_t)0x02000000) +#define CAN_F36R1_FB26 ((uint32_t)0x04000000) +#define CAN_F36R1_FB27 ((uint32_t)0x08000000) +#define CAN_F36R1_FB28 ((uint32_t)0x10000000) +#define CAN_F36R1_FB29 ((uint32_t)0x20000000) +#define CAN_F36R1_FB30 ((uint32_t)0x40000000) +#define CAN_F36R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F37R1 register ********************/ +#define CAN_F37R1_FB0 ((uint32_t)0x00000001) +#define CAN_F37R1_FB1 ((uint32_t)0x00000002) +#define CAN_F37R1_FB2 ((uint32_t)0x00000004) +#define CAN_F37R1_FB3 ((uint32_t)0x00000008) +#define CAN_F37R1_FB4 ((uint32_t)0x00000010) +#define CAN_F37R1_FB5 ((uint32_t)0x00000020) +#define CAN_F37R1_FB6 ((uint32_t)0x00000040) +#define CAN_F37R1_FB7 ((uint32_t)0x00000080) +#define CAN_F37R1_FB8 ((uint32_t)0x00000100) +#define CAN_F37R1_FB9 ((uint32_t)0x00000200) +#define CAN_F37R1_FB10 ((uint32_t)0x00000400) +#define CAN_F37R1_FB11 ((uint32_t)0x00000800) +#define CAN_F37R1_FB12 ((uint32_t)0x00001000) +#define CAN_F37R1_FB13 ((uint32_t)0x00002000) +#define CAN_F37R1_FB14 ((uint32_t)0x00004000) +#define CAN_F37R1_FB15 ((uint32_t)0x00008000) +#define CAN_F37R1_FB16 ((uint32_t)0x00010000) +#define CAN_F37R1_FB17 ((uint32_t)0x00020000) +#define CAN_F37R1_FB18 ((uint32_t)0x00040000) +#define CAN_F37R1_FB19 ((uint32_t)0x00080000) +#define CAN_F37R1_FB20 ((uint32_t)0x00100000) +#define CAN_F37R1_FB21 ((uint32_t)0x00200000) +#define CAN_F37R1_FB22 ((uint32_t)0x00400000) +#define CAN_F37R1_FB23 ((uint32_t)0x00800000) +#define CAN_F37R1_FB24 ((uint32_t)0x01000000) +#define CAN_F37R1_FB25 ((uint32_t)0x02000000) +#define CAN_F37R1_FB26 ((uint32_t)0x04000000) +#define CAN_F37R1_FB27 ((uint32_t)0x08000000) +#define CAN_F37R1_FB28 ((uint32_t)0x10000000) +#define CAN_F37R1_FB29 ((uint32_t)0x20000000) +#define CAN_F37R1_FB30 ((uint32_t)0x40000000) +#define CAN_F37R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F38R1 register ********************/ +#define CAN_F38R1_FB0 ((uint32_t)0x00000001) +#define CAN_F38R1_FB1 ((uint32_t)0x00000002) +#define CAN_F38R1_FB2 ((uint32_t)0x00000004) +#define CAN_F38R1_FB3 ((uint32_t)0x00000008) +#define CAN_F38R1_FB4 ((uint32_t)0x00000010) +#define CAN_F38R1_FB5 ((uint32_t)0x00000020) +#define CAN_F38R1_FB6 ((uint32_t)0x00000040) +#define CAN_F38R1_FB7 ((uint32_t)0x00000080) +#define CAN_F38R1_FB8 ((uint32_t)0x00000100) +#define CAN_F38R1_FB9 ((uint32_t)0x00000200) +#define CAN_F38R1_FB10 ((uint32_t)0x00000400) +#define CAN_F38R1_FB11 ((uint32_t)0x00000800) +#define CAN_F38R1_FB12 ((uint32_t)0x00001000) +#define CAN_F38R1_FB13 ((uint32_t)0x00002000) +#define CAN_F38R1_FB14 ((uint32_t)0x00004000) +#define CAN_F38R1_FB15 ((uint32_t)0x00008000) +#define CAN_F38R1_FB16 ((uint32_t)0x00010000) +#define CAN_F38R1_FB17 ((uint32_t)0x00020000) +#define CAN_F38R1_FB18 ((uint32_t)0x00040000) +#define CAN_F38R1_FB19 ((uint32_t)0x00080000) +#define CAN_F38R1_FB20 ((uint32_t)0x00100000) +#define CAN_F38R1_FB21 ((uint32_t)0x00200000) +#define CAN_F38R1_FB22 ((uint32_t)0x00400000) +#define CAN_F38R1_FB23 ((uint32_t)0x00800000) +#define CAN_F38R1_FB24 ((uint32_t)0x01000000) +#define CAN_F38R1_FB25 ((uint32_t)0x02000000) +#define CAN_F38R1_FB26 ((uint32_t)0x04000000) +#define CAN_F38R1_FB27 ((uint32_t)0x08000000) +#define CAN_F38R1_FB28 ((uint32_t)0x10000000) +#define CAN_F38R1_FB29 ((uint32_t)0x20000000) +#define CAN_F38R1_FB30 ((uint32_t)0x40000000) +#define CAN_F38R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F39R1 register ********************/ +#define CAN_F39R1_FB0 ((uint32_t)0x00000001) +#define CAN_F39R1_FB1 ((uint32_t)0x00000002) +#define CAN_F39R1_FB2 ((uint32_t)0x00000004) +#define CAN_F39R1_FB3 ((uint32_t)0x00000008) +#define CAN_F39R1_FB4 ((uint32_t)0x00000010) +#define CAN_F39R1_FB5 ((uint32_t)0x00000020) +#define CAN_F39R1_FB6 ((uint32_t)0x00000040) +#define CAN_F39R1_FB7 ((uint32_t)0x00000080) +#define CAN_F39R1_FB8 ((uint32_t)0x00000100) +#define CAN_F39R1_FB9 ((uint32_t)0x00000200) +#define CAN_F39R1_FB10 ((uint32_t)0x00000400) +#define CAN_F39R1_FB11 ((uint32_t)0x00000800) +#define CAN_F39R1_FB12 ((uint32_t)0x00001000) +#define CAN_F39R1_FB13 ((uint32_t)0x00002000) +#define CAN_F39R1_FB14 ((uint32_t)0x00004000) +#define CAN_F39R1_FB15 ((uint32_t)0x00008000) +#define CAN_F39R1_FB16 ((uint32_t)0x00010000) +#define CAN_F39R1_FB17 ((uint32_t)0x00020000) +#define CAN_F39R1_FB18 ((uint32_t)0x00040000) +#define CAN_F39R1_FB19 ((uint32_t)0x00080000) +#define CAN_F39R1_FB20 ((uint32_t)0x00100000) +#define CAN_F39R1_FB21 ((uint32_t)0x00200000) +#define CAN_F39R1_FB22 ((uint32_t)0x00400000) +#define CAN_F39R1_FB23 ((uint32_t)0x00800000) +#define CAN_F39R1_FB24 ((uint32_t)0x01000000) +#define CAN_F39R1_FB25 ((uint32_t)0x02000000) +#define CAN_F39R1_FB26 ((uint32_t)0x04000000) +#define CAN_F39R1_FB27 ((uint32_t)0x08000000) +#define CAN_F39R1_FB28 ((uint32_t)0x10000000) +#define CAN_F39R1_FB29 ((uint32_t)0x20000000) +#define CAN_F39R1_FB30 ((uint32_t)0x40000000) +#define CAN_F39R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F40R1 register ********************/ +#define CAN_F40R1_FB0 ((uint32_t)0x00000001) +#define CAN_F40R1_FB1 ((uint32_t)0x00000002) +#define CAN_F40R1_FB2 ((uint32_t)0x00000004) +#define CAN_F40R1_FB3 ((uint32_t)0x00000008) +#define CAN_F40R1_FB4 ((uint32_t)0x00000010) +#define CAN_F40R1_FB5 ((uint32_t)0x00000020) +#define CAN_F40R1_FB6 ((uint32_t)0x00000040) +#define CAN_F40R1_FB7 ((uint32_t)0x00000080) +#define CAN_F40R1_FB8 ((uint32_t)0x00000100) +#define CAN_F40R1_FB9 ((uint32_t)0x00000200) +#define CAN_F40R1_FB10 ((uint32_t)0x00000400) +#define CAN_F40R1_FB11 ((uint32_t)0x00000800) +#define CAN_F40R1_FB12 ((uint32_t)0x00001000) +#define CAN_F40R1_FB13 ((uint32_t)0x00002000) +#define CAN_F40R1_FB14 ((uint32_t)0x00004000) +#define CAN_F40R1_FB15 ((uint32_t)0x00008000) +#define CAN_F40R1_FB16 ((uint32_t)0x00010000) +#define CAN_F40R1_FB17 ((uint32_t)0x00020000) +#define CAN_F40R1_FB18 ((uint32_t)0x00040000) +#define CAN_F40R1_FB19 ((uint32_t)0x00080000) +#define CAN_F40R1_FB20 ((uint32_t)0x00100000) +#define CAN_F40R1_FB21 ((uint32_t)0x00200000) +#define CAN_F40R1_FB22 ((uint32_t)0x00400000) +#define CAN_F40R1_FB23 ((uint32_t)0x00800000) +#define CAN_F40R1_FB24 ((uint32_t)0x01000000) +#define CAN_F40R1_FB25 ((uint32_t)0x02000000) +#define CAN_F40R1_FB26 ((uint32_t)0x04000000) +#define CAN_F40R1_FB27 ((uint32_t)0x08000000) +#define CAN_F40R1_FB28 ((uint32_t)0x10000000) +#define CAN_F40R1_FB29 ((uint32_t)0x20000000) +#define CAN_F40R1_FB30 ((uint32_t)0x40000000) +#define CAN_F40R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F41R1 register ********************/ +#define CAN_F41R1_FB0 ((uint32_t)0x00000001) +#define CAN_F41R1_FB1 ((uint32_t)0x00000002) +#define CAN_F41R1_FB2 ((uint32_t)0x00000004) +#define CAN_F41R1_FB3 ((uint32_t)0x00000008) +#define CAN_F41R1_FB4 ((uint32_t)0x00000010) +#define CAN_F41R1_FB5 ((uint32_t)0x00000020) +#define CAN_F41R1_FB6 ((uint32_t)0x00000040) +#define CAN_F41R1_FB7 ((uint32_t)0x00000080) +#define CAN_F41R1_FB8 ((uint32_t)0x00000100) +#define CAN_F41R1_FB9 ((uint32_t)0x00000200) +#define CAN_F41R1_FB10 ((uint32_t)0x00000400) +#define CAN_F41R1_FB11 ((uint32_t)0x00000800) +#define CAN_F41R1_FB12 ((uint32_t)0x00001000) +#define CAN_F41R1_FB13 ((uint32_t)0x00002000) +#define CAN_F41R1_FB14 ((uint32_t)0x00004000) +#define CAN_F41R1_FB15 ((uint32_t)0x00008000) +#define CAN_F41R1_FB16 ((uint32_t)0x00010000) +#define CAN_F41R1_FB17 ((uint32_t)0x00020000) +#define CAN_F41R1_FB18 ((uint32_t)0x00040000) +#define CAN_F41R1_FB19 ((uint32_t)0x00080000) +#define CAN_F41R1_FB20 ((uint32_t)0x00100000) +#define CAN_F41R1_FB21 ((uint32_t)0x00200000) +#define CAN_F41R1_FB22 ((uint32_t)0x00400000) +#define CAN_F41R1_FB23 ((uint32_t)0x00800000) +#define CAN_F41R1_FB24 ((uint32_t)0x01000000) +#define CAN_F41R1_FB25 ((uint32_t)0x02000000) +#define CAN_F41R1_FB26 ((uint32_t)0x04000000) +#define CAN_F41R1_FB27 ((uint32_t)0x08000000) +#define CAN_F41R1_FB28 ((uint32_t)0x10000000) +#define CAN_F41R1_FB29 ((uint32_t)0x20000000) +#define CAN_F41R1_FB30 ((uint32_t)0x40000000) +#define CAN_F41R1_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F0R2 register ********************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F1R2 register ********************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F2R2 register ********************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F3R2 register ********************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F4R2 register ********************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F5R2 register ********************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F6R2 register ********************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F7R2 register ********************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F8R2 register ********************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F9R2 register ********************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F10R2 register ********************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F11R2 register ********************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F12R2 register ********************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F13R2 register ********************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F14R2 register ********************/ +#define CAN_F14R2_FB0 ((uint32_t)0x00000001) +#define CAN_F14R2_FB1 ((uint32_t)0x00000002) +#define CAN_F14R2_FB2 ((uint32_t)0x00000004) +#define CAN_F14R2_FB3 ((uint32_t)0x00000008) +#define CAN_F14R2_FB4 ((uint32_t)0x00000010) +#define CAN_F14R2_FB5 ((uint32_t)0x00000020) +#define CAN_F14R2_FB6 ((uint32_t)0x00000040) +#define CAN_F14R2_FB7 ((uint32_t)0x00000080) +#define CAN_F14R2_FB8 ((uint32_t)0x00000100) +#define CAN_F14R2_FB9 ((uint32_t)0x00000200) +#define CAN_F14R2_FB10 ((uint32_t)0x00000400) +#define CAN_F14R2_FB11 ((uint32_t)0x00000800) +#define CAN_F14R2_FB12 ((uint32_t)0x00001000) +#define CAN_F14R2_FB13 ((uint32_t)0x00002000) +#define CAN_F14R2_FB14 ((uint32_t)0x00004000) +#define CAN_F14R2_FB15 ((uint32_t)0x00008000) +#define CAN_F14R2_FB16 ((uint32_t)0x00010000) +#define CAN_F14R2_FB17 ((uint32_t)0x00020000) +#define CAN_F14R2_FB18 ((uint32_t)0x00040000) +#define CAN_F14R2_FB19 ((uint32_t)0x00080000) +#define CAN_F14R2_FB20 ((uint32_t)0x00100000) +#define CAN_F14R2_FB21 ((uint32_t)0x00200000) +#define CAN_F14R2_FB22 ((uint32_t)0x00400000) +#define CAN_F14R2_FB23 ((uint32_t)0x00800000) +#define CAN_F14R2_FB24 ((uint32_t)0x01000000) +#define CAN_F14R2_FB25 ((uint32_t)0x02000000) +#define CAN_F14R2_FB26 ((uint32_t)0x04000000) +#define CAN_F14R2_FB27 ((uint32_t)0x08000000) +#define CAN_F14R2_FB28 ((uint32_t)0x10000000) +#define CAN_F14R2_FB29 ((uint32_t)0x20000000) +#define CAN_F14R2_FB30 ((uint32_t)0x40000000) +#define CAN_F14R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F15R2 register ********************/ +#define CAN_F15R2_FB0 ((uint32_t)0x00000001) +#define CAN_F15R2_FB1 ((uint32_t)0x00000002) +#define CAN_F15R2_FB2 ((uint32_t)0x00000004) +#define CAN_F15R2_FB3 ((uint32_t)0x00000008) +#define CAN_F15R2_FB4 ((uint32_t)0x00000010) +#define CAN_F15R2_FB5 ((uint32_t)0x00000020) +#define CAN_F15R2_FB6 ((uint32_t)0x00000040) +#define CAN_F15R2_FB7 ((uint32_t)0x00000080) +#define CAN_F15R2_FB8 ((uint32_t)0x00000100) +#define CAN_F15R2_FB9 ((uint32_t)0x00000200) +#define CAN_F15R2_FB10 ((uint32_t)0x00000400) +#define CAN_F15R2_FB11 ((uint32_t)0x00000800) +#define CAN_F15R2_FB12 ((uint32_t)0x00001000) +#define CAN_F15R2_FB13 ((uint32_t)0x00002000) +#define CAN_F15R2_FB14 ((uint32_t)0x00004000) +#define CAN_F15R2_FB15 ((uint32_t)0x00008000) +#define CAN_F15R2_FB16 ((uint32_t)0x00010000) +#define CAN_F15R2_FB17 ((uint32_t)0x00020000) +#define CAN_F15R2_FB18 ((uint32_t)0x00040000) +#define CAN_F15R2_FB19 ((uint32_t)0x00080000) +#define CAN_F15R2_FB20 ((uint32_t)0x00100000) +#define CAN_F15R2_FB21 ((uint32_t)0x00200000) +#define CAN_F15R2_FB22 ((uint32_t)0x00400000) +#define CAN_F15R2_FB23 ((uint32_t)0x00800000) +#define CAN_F15R2_FB24 ((uint32_t)0x01000000) +#define CAN_F15R2_FB25 ((uint32_t)0x02000000) +#define CAN_F15R2_FB26 ((uint32_t)0x04000000) +#define CAN_F15R2_FB27 ((uint32_t)0x08000000) +#define CAN_F15R2_FB28 ((uint32_t)0x10000000) +#define CAN_F15R2_FB29 ((uint32_t)0x20000000) +#define CAN_F15R2_FB30 ((uint32_t)0x40000000) +#define CAN_F15R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F16R2 register ********************/ +#define CAN_F16R2_FB0 ((uint32_t)0x00000001) +#define CAN_F16R2_FB1 ((uint32_t)0x00000002) +#define CAN_F16R2_FB2 ((uint32_t)0x00000004) +#define CAN_F16R2_FB3 ((uint32_t)0x00000008) +#define CAN_F16R2_FB4 ((uint32_t)0x00000010) +#define CAN_F16R2_FB5 ((uint32_t)0x00000020) +#define CAN_F16R2_FB6 ((uint32_t)0x00000040) +#define CAN_F16R2_FB7 ((uint32_t)0x00000080) +#define CAN_F16R2_FB8 ((uint32_t)0x00000100) +#define CAN_F16R2_FB9 ((uint32_t)0x00000200) +#define CAN_F16R2_FB10 ((uint32_t)0x00000400) +#define CAN_F16R2_FB11 ((uint32_t)0x00000800) +#define CAN_F16R2_FB12 ((uint32_t)0x00001000) +#define CAN_F16R2_FB13 ((uint32_t)0x00002000) +#define CAN_F16R2_FB14 ((uint32_t)0x00004000) +#define CAN_F16R2_FB15 ((uint32_t)0x00008000) +#define CAN_F16R2_FB16 ((uint32_t)0x00010000) +#define CAN_F16R2_FB17 ((uint32_t)0x00020000) +#define CAN_F16R2_FB18 ((uint32_t)0x00040000) +#define CAN_F16R2_FB19 ((uint32_t)0x00080000) +#define CAN_F16R2_FB20 ((uint32_t)0x00100000) +#define CAN_F16R2_FB21 ((uint32_t)0x00200000) +#define CAN_F16R2_FB22 ((uint32_t)0x00400000) +#define CAN_F16R2_FB23 ((uint32_t)0x00800000) +#define CAN_F16R2_FB24 ((uint32_t)0x01000000) +#define CAN_F16R2_FB25 ((uint32_t)0x02000000) +#define CAN_F16R2_FB26 ((uint32_t)0x04000000) +#define CAN_F16R2_FB27 ((uint32_t)0x08000000) +#define CAN_F16R2_FB28 ((uint32_t)0x10000000) +#define CAN_F16R2_FB29 ((uint32_t)0x20000000) +#define CAN_F16R2_FB30 ((uint32_t)0x40000000) +#define CAN_F16R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F17R2 register ********************/ +#define CAN_F17R2_FB0 ((uint32_t)0x00000001) +#define CAN_F17R2_FB1 ((uint32_t)0x00000002) +#define CAN_F17R2_FB2 ((uint32_t)0x00000004) +#define CAN_F17R2_FB3 ((uint32_t)0x00000008) +#define CAN_F17R2_FB4 ((uint32_t)0x00000010) +#define CAN_F17R2_FB5 ((uint32_t)0x00000020) +#define CAN_F17R2_FB6 ((uint32_t)0x00000040) +#define CAN_F17R2_FB7 ((uint32_t)0x00000080) +#define CAN_F17R2_FB8 ((uint32_t)0x00000100) +#define CAN_F17R2_FB9 ((uint32_t)0x00000200) +#define CAN_F17R2_FB10 ((uint32_t)0x00000400) +#define CAN_F17R2_FB11 ((uint32_t)0x00000800) +#define CAN_F17R2_FB12 ((uint32_t)0x00001000) +#define CAN_F17R2_FB13 ((uint32_t)0x00002000) +#define CAN_F17R2_FB14 ((uint32_t)0x00004000) +#define CAN_F17R2_FB15 ((uint32_t)0x00008000) +#define CAN_F17R2_FB16 ((uint32_t)0x00010000) +#define CAN_F17R2_FB17 ((uint32_t)0x00020000) +#define CAN_F17R2_FB18 ((uint32_t)0x00040000) +#define CAN_F17R2_FB19 ((uint32_t)0x00080000) +#define CAN_F17R2_FB20 ((uint32_t)0x00100000) +#define CAN_F17R2_FB21 ((uint32_t)0x00200000) +#define CAN_F17R2_FB22 ((uint32_t)0x00400000) +#define CAN_F17R2_FB23 ((uint32_t)0x00800000) +#define CAN_F17R2_FB24 ((uint32_t)0x01000000) +#define CAN_F17R2_FB25 ((uint32_t)0x02000000) +#define CAN_F17R2_FB26 ((uint32_t)0x04000000) +#define CAN_F17R2_FB27 ((uint32_t)0x08000000) +#define CAN_F17R2_FB28 ((uint32_t)0x10000000) +#define CAN_F17R2_FB29 ((uint32_t)0x20000000) +#define CAN_F17R2_FB30 ((uint32_t)0x40000000) +#define CAN_F17R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F18R2 register ********************/ +#define CAN_F18R2_FB0 ((uint32_t)0x00000001) +#define CAN_F18R2_FB1 ((uint32_t)0x00000002) +#define CAN_F18R2_FB2 ((uint32_t)0x00000004) +#define CAN_F18R2_FB3 ((uint32_t)0x00000008) +#define CAN_F18R2_FB4 ((uint32_t)0x00000010) +#define CAN_F18R2_FB5 ((uint32_t)0x00000020) +#define CAN_F18R2_FB6 ((uint32_t)0x00000040) +#define CAN_F18R2_FB7 ((uint32_t)0x00000080) +#define CAN_F18R2_FB8 ((uint32_t)0x00000100) +#define CAN_F18R2_FB9 ((uint32_t)0x00000200) +#define CAN_F18R2_FB10 ((uint32_t)0x00000400) +#define CAN_F18R2_FB11 ((uint32_t)0x00000800) +#define CAN_F18R2_FB12 ((uint32_t)0x00001000) +#define CAN_F18R2_FB13 ((uint32_t)0x00002000) +#define CAN_F18R2_FB14 ((uint32_t)0x00004000) +#define CAN_F18R2_FB15 ((uint32_t)0x00008000) +#define CAN_F18R2_FB16 ((uint32_t)0x00010000) +#define CAN_F18R2_FB17 ((uint32_t)0x00020000) +#define CAN_F18R2_FB18 ((uint32_t)0x00040000) +#define CAN_F18R2_FB19 ((uint32_t)0x00080000) +#define CAN_F18R2_FB20 ((uint32_t)0x00100000) +#define CAN_F18R2_FB21 ((uint32_t)0x00200000) +#define CAN_F18R2_FB22 ((uint32_t)0x00400000) +#define CAN_F18R2_FB23 ((uint32_t)0x00800000) +#define CAN_F18R2_FB24 ((uint32_t)0x01000000) +#define CAN_F18R2_FB25 ((uint32_t)0x02000000) +#define CAN_F18R2_FB26 ((uint32_t)0x04000000) +#define CAN_F18R2_FB27 ((uint32_t)0x08000000) +#define CAN_F18R2_FB28 ((uint32_t)0x10000000) +#define CAN_F18R2_FB29 ((uint32_t)0x20000000) +#define CAN_F18R2_FB30 ((uint32_t)0x40000000) +#define CAN_F18R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F19R2 register ********************/ +#define CAN_F19R2_FB0 ((uint32_t)0x00000001) +#define CAN_F19R2_FB1 ((uint32_t)0x00000002) +#define CAN_F19R2_FB2 ((uint32_t)0x00000004) +#define CAN_F19R2_FB3 ((uint32_t)0x00000008) +#define CAN_F19R2_FB4 ((uint32_t)0x00000010) +#define CAN_F19R2_FB5 ((uint32_t)0x00000020) +#define CAN_F19R2_FB6 ((uint32_t)0x00000040) +#define CAN_F19R2_FB7 ((uint32_t)0x00000080) +#define CAN_F19R2_FB8 ((uint32_t)0x00000100) +#define CAN_F19R2_FB9 ((uint32_t)0x00000200) +#define CAN_F19R2_FB10 ((uint32_t)0x00000400) +#define CAN_F19R2_FB11 ((uint32_t)0x00000800) +#define CAN_F19R2_FB12 ((uint32_t)0x00001000) +#define CAN_F19R2_FB13 ((uint32_t)0x00002000) +#define CAN_F19R2_FB14 ((uint32_t)0x00004000) +#define CAN_F19R2_FB15 ((uint32_t)0x00008000) +#define CAN_F19R2_FB16 ((uint32_t)0x00010000) +#define CAN_F19R2_FB17 ((uint32_t)0x00020000) +#define CAN_F19R2_FB18 ((uint32_t)0x00040000) +#define CAN_F19R2_FB19 ((uint32_t)0x00080000) +#define CAN_F19R2_FB20 ((uint32_t)0x00100000) +#define CAN_F19R2_FB21 ((uint32_t)0x00200000) +#define CAN_F19R2_FB22 ((uint32_t)0x00400000) +#define CAN_F19R2_FB23 ((uint32_t)0x00800000) +#define CAN_F19R2_FB24 ((uint32_t)0x01000000) +#define CAN_F19R2_FB25 ((uint32_t)0x02000000) +#define CAN_F19R2_FB26 ((uint32_t)0x04000000) +#define CAN_F19R2_FB27 ((uint32_t)0x08000000) +#define CAN_F19R2_FB28 ((uint32_t)0x10000000) +#define CAN_F19R2_FB29 ((uint32_t)0x20000000) +#define CAN_F19R2_FB30 ((uint32_t)0x40000000) +#define CAN_F19R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F20R2 register ********************/ +#define CAN_F20R2_FB0 ((uint32_t)0x00000001) +#define CAN_F20R2_FB1 ((uint32_t)0x00000002) +#define CAN_F20R2_FB2 ((uint32_t)0x00000004) +#define CAN_F20R2_FB3 ((uint32_t)0x00000008) +#define CAN_F20R2_FB4 ((uint32_t)0x00000010) +#define CAN_F20R2_FB5 ((uint32_t)0x00000020) +#define CAN_F20R2_FB6 ((uint32_t)0x00000040) +#define CAN_F20R2_FB7 ((uint32_t)0x00000080) +#define CAN_F20R2_FB8 ((uint32_t)0x00000100) +#define CAN_F20R2_FB9 ((uint32_t)0x00000200) +#define CAN_F20R2_FB10 ((uint32_t)0x00000400) +#define CAN_F20R2_FB11 ((uint32_t)0x00000800) +#define CAN_F20R2_FB12 ((uint32_t)0x00001000) +#define CAN_F20R2_FB13 ((uint32_t)0x00002000) +#define CAN_F20R2_FB14 ((uint32_t)0x00004000) +#define CAN_F20R2_FB15 ((uint32_t)0x00008000) +#define CAN_F20R2_FB16 ((uint32_t)0x00010000) +#define CAN_F20R2_FB17 ((uint32_t)0x00020000) +#define CAN_F20R2_FB18 ((uint32_t)0x00040000) +#define CAN_F20R2_FB19 ((uint32_t)0x00080000) +#define CAN_F20R2_FB20 ((uint32_t)0x00100000) +#define CAN_F20R2_FB21 ((uint32_t)0x00200000) +#define CAN_F20R2_FB22 ((uint32_t)0x00400000) +#define CAN_F20R2_FB23 ((uint32_t)0x00800000) +#define CAN_F20R2_FB24 ((uint32_t)0x01000000) +#define CAN_F20R2_FB25 ((uint32_t)0x02000000) +#define CAN_F20R2_FB26 ((uint32_t)0x04000000) +#define CAN_F20R2_FB27 ((uint32_t)0x08000000) +#define CAN_F20R2_FB28 ((uint32_t)0x10000000) +#define CAN_F20R2_FB29 ((uint32_t)0x20000000) +#define CAN_F20R2_FB30 ((uint32_t)0x40000000) +#define CAN_F20R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F21R2 register ********************/ +#define CAN_F21R2_FB0 ((uint32_t)0x00000001) +#define CAN_F21R2_FB1 ((uint32_t)0x00000002) +#define CAN_F21R2_FB2 ((uint32_t)0x00000004) +#define CAN_F21R2_FB3 ((uint32_t)0x00000008) +#define CAN_F21R2_FB4 ((uint32_t)0x00000010) +#define CAN_F21R2_FB5 ((uint32_t)0x00000020) +#define CAN_F21R2_FB6 ((uint32_t)0x00000040) +#define CAN_F21R2_FB7 ((uint32_t)0x00000080) +#define CAN_F21R2_FB8 ((uint32_t)0x00000100) +#define CAN_F21R2_FB9 ((uint32_t)0x00000200) +#define CAN_F21R2_FB10 ((uint32_t)0x00000400) +#define CAN_F21R2_FB11 ((uint32_t)0x00000800) +#define CAN_F21R2_FB12 ((uint32_t)0x00001000) +#define CAN_F21R2_FB13 ((uint32_t)0x00002000) +#define CAN_F21R2_FB14 ((uint32_t)0x00004000) +#define CAN_F21R2_FB15 ((uint32_t)0x00008000) +#define CAN_F21R2_FB16 ((uint32_t)0x00010000) +#define CAN_F21R2_FB17 ((uint32_t)0x00020000) +#define CAN_F21R2_FB18 ((uint32_t)0x00040000) +#define CAN_F21R2_FB19 ((uint32_t)0x00080000) +#define CAN_F21R2_FB20 ((uint32_t)0x00100000) +#define CAN_F21R2_FB21 ((uint32_t)0x00200000) +#define CAN_F21R2_FB22 ((uint32_t)0x00400000) +#define CAN_F21R2_FB23 ((uint32_t)0x00800000) +#define CAN_F21R2_FB24 ((uint32_t)0x01000000) +#define CAN_F21R2_FB25 ((uint32_t)0x02000000) +#define CAN_F21R2_FB26 ((uint32_t)0x04000000) +#define CAN_F21R2_FB27 ((uint32_t)0x08000000) +#define CAN_F21R2_FB28 ((uint32_t)0x10000000) +#define CAN_F21R2_FB29 ((uint32_t)0x20000000) +#define CAN_F21R2_FB30 ((uint32_t)0x40000000) +#define CAN_F21R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F22R2 register ********************/ +#define CAN_F22R2_FB0 ((uint32_t)0x00000001) +#define CAN_F22R2_FB1 ((uint32_t)0x00000002) +#define CAN_F22R2_FB2 ((uint32_t)0x00000004) +#define CAN_F22R2_FB3 ((uint32_t)0x00000008) +#define CAN_F22R2_FB4 ((uint32_t)0x00000010) +#define CAN_F22R2_FB5 ((uint32_t)0x00000020) +#define CAN_F22R2_FB6 ((uint32_t)0x00000040) +#define CAN_F22R2_FB7 ((uint32_t)0x00000080) +#define CAN_F22R2_FB8 ((uint32_t)0x00000100) +#define CAN_F22R2_FB9 ((uint32_t)0x00000200) +#define CAN_F22R2_FB10 ((uint32_t)0x00000400) +#define CAN_F22R2_FB11 ((uint32_t)0x00000800) +#define CAN_F22R2_FB12 ((uint32_t)0x00001000) +#define CAN_F22R2_FB13 ((uint32_t)0x00002000) +#define CAN_F22R2_FB14 ((uint32_t)0x00004000) +#define CAN_F22R2_FB15 ((uint32_t)0x00008000) +#define CAN_F22R2_FB16 ((uint32_t)0x00010000) +#define CAN_F22R2_FB17 ((uint32_t)0x00020000) +#define CAN_F22R2_FB18 ((uint32_t)0x00040000) +#define CAN_F22R2_FB19 ((uint32_t)0x00080000) +#define CAN_F22R2_FB20 ((uint32_t)0x00100000) +#define CAN_F22R2_FB21 ((uint32_t)0x00200000) +#define CAN_F22R2_FB22 ((uint32_t)0x00400000) +#define CAN_F22R2_FB23 ((uint32_t)0x00800000) +#define CAN_F22R2_FB24 ((uint32_t)0x01000000) +#define CAN_F22R2_FB25 ((uint32_t)0x02000000) +#define CAN_F22R2_FB26 ((uint32_t)0x04000000) +#define CAN_F22R2_FB27 ((uint32_t)0x08000000) +#define CAN_F22R2_FB28 ((uint32_t)0x10000000) +#define CAN_F22R2_FB29 ((uint32_t)0x20000000) +#define CAN_F22R2_FB30 ((uint32_t)0x40000000) +#define CAN_F22R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F23R2 register ********************/ +#define CAN_F23R2_FB0 ((uint32_t)0x00000001) +#define CAN_F23R2_FB1 ((uint32_t)0x00000002) +#define CAN_F23R2_FB2 ((uint32_t)0x00000004) +#define CAN_F23R2_FB3 ((uint32_t)0x00000008) +#define CAN_F23R2_FB4 ((uint32_t)0x00000010) +#define CAN_F23R2_FB5 ((uint32_t)0x00000020) +#define CAN_F23R2_FB6 ((uint32_t)0x00000040) +#define CAN_F23R2_FB7 ((uint32_t)0x00000080) +#define CAN_F23R2_FB8 ((uint32_t)0x00000100) +#define CAN_F23R2_FB9 ((uint32_t)0x00000200) +#define CAN_F23R2_FB10 ((uint32_t)0x00000400) +#define CAN_F23R2_FB11 ((uint32_t)0x00000800) +#define CAN_F23R2_FB12 ((uint32_t)0x00001000) +#define CAN_F23R2_FB13 ((uint32_t)0x00002000) +#define CAN_F23R2_FB14 ((uint32_t)0x00004000) +#define CAN_F23R2_FB15 ((uint32_t)0x00008000) +#define CAN_F23R2_FB16 ((uint32_t)0x00010000) +#define CAN_F23R2_FB17 ((uint32_t)0x00020000) +#define CAN_F23R2_FB18 ((uint32_t)0x00040000) +#define CAN_F23R2_FB19 ((uint32_t)0x00080000) +#define CAN_F23R2_FB20 ((uint32_t)0x00100000) +#define CAN_F23R2_FB21 ((uint32_t)0x00200000) +#define CAN_F23R2_FB22 ((uint32_t)0x00400000) +#define CAN_F23R2_FB23 ((uint32_t)0x00800000) +#define CAN_F23R2_FB24 ((uint32_t)0x01000000) +#define CAN_F23R2_FB25 ((uint32_t)0x02000000) +#define CAN_F23R2_FB26 ((uint32_t)0x04000000) +#define CAN_F23R2_FB27 ((uint32_t)0x08000000) +#define CAN_F23R2_FB28 ((uint32_t)0x10000000) +#define CAN_F23R2_FB29 ((uint32_t)0x20000000) +#define CAN_F23R2_FB30 ((uint32_t)0x40000000) +#define CAN_F23R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F24R2 register ********************/ +#define CAN_F24R2_FB0 ((uint32_t)0x00000001) +#define CAN_F24R2_FB1 ((uint32_t)0x00000002) +#define CAN_F24R2_FB2 ((uint32_t)0x00000004) +#define CAN_F24R2_FB3 ((uint32_t)0x00000008) +#define CAN_F24R2_FB4 ((uint32_t)0x00000010) +#define CAN_F24R2_FB5 ((uint32_t)0x00000020) +#define CAN_F24R2_FB6 ((uint32_t)0x00000040) +#define CAN_F24R2_FB7 ((uint32_t)0x00000080) +#define CAN_F24R2_FB8 ((uint32_t)0x00000100) +#define CAN_F24R2_FB9 ((uint32_t)0x00000200) +#define CAN_F24R2_FB10 ((uint32_t)0x00000400) +#define CAN_F24R2_FB11 ((uint32_t)0x00000800) +#define CAN_F24R2_FB12 ((uint32_t)0x00001000) +#define CAN_F24R2_FB13 ((uint32_t)0x00002000) +#define CAN_F24R2_FB14 ((uint32_t)0x00004000) +#define CAN_F24R2_FB15 ((uint32_t)0x00008000) +#define CAN_F24R2_FB16 ((uint32_t)0x00010000) +#define CAN_F24R2_FB17 ((uint32_t)0x00020000) +#define CAN_F24R2_FB18 ((uint32_t)0x00040000) +#define CAN_F24R2_FB19 ((uint32_t)0x00080000) +#define CAN_F24R2_FB20 ((uint32_t)0x00100000) +#define CAN_F24R2_FB21 ((uint32_t)0x00200000) +#define CAN_F24R2_FB22 ((uint32_t)0x00400000) +#define CAN_F24R2_FB23 ((uint32_t)0x00800000) +#define CAN_F24R2_FB24 ((uint32_t)0x01000000) +#define CAN_F24R2_FB25 ((uint32_t)0x02000000) +#define CAN_F24R2_FB26 ((uint32_t)0x04000000) +#define CAN_F24R2_FB27 ((uint32_t)0x08000000) +#define CAN_F24R2_FB28 ((uint32_t)0x10000000) +#define CAN_F24R2_FB29 ((uint32_t)0x20000000) +#define CAN_F24R2_FB30 ((uint32_t)0x40000000) +#define CAN_F24R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F25R2 register ********************/ +#define CAN_F25R2_FB0 ((uint32_t)0x00000001) +#define CAN_F25R2_FB1 ((uint32_t)0x00000002) +#define CAN_F25R2_FB2 ((uint32_t)0x00000004) +#define CAN_F25R2_FB3 ((uint32_t)0x00000008) +#define CAN_F25R2_FB4 ((uint32_t)0x00000010) +#define CAN_F25R2_FB5 ((uint32_t)0x00000020) +#define CAN_F25R2_FB6 ((uint32_t)0x00000040) +#define CAN_F25R2_FB7 ((uint32_t)0x00000080) +#define CAN_F25R2_FB8 ((uint32_t)0x00000100) +#define CAN_F25R2_FB9 ((uint32_t)0x00000200) +#define CAN_F25R2_FB10 ((uint32_t)0x00000400) +#define CAN_F25R2_FB11 ((uint32_t)0x00000800) +#define CAN_F25R2_FB12 ((uint32_t)0x00001000) +#define CAN_F25R2_FB13 ((uint32_t)0x00002000) +#define CAN_F25R2_FB14 ((uint32_t)0x00004000) +#define CAN_F25R2_FB15 ((uint32_t)0x00008000) +#define CAN_F25R2_FB16 ((uint32_t)0x00010000) +#define CAN_F25R2_FB17 ((uint32_t)0x00020000) +#define CAN_F25R2_FB18 ((uint32_t)0x00040000) +#define CAN_F25R2_FB19 ((uint32_t)0x00080000) +#define CAN_F25R2_FB20 ((uint32_t)0x00100000) +#define CAN_F25R2_FB21 ((uint32_t)0x00200000) +#define CAN_F25R2_FB22 ((uint32_t)0x00400000) +#define CAN_F25R2_FB23 ((uint32_t)0x00800000) +#define CAN_F25R2_FB24 ((uint32_t)0x01000000) +#define CAN_F25R2_FB25 ((uint32_t)0x02000000) +#define CAN_F25R2_FB26 ((uint32_t)0x04000000) +#define CAN_F25R2_FB27 ((uint32_t)0x08000000) +#define CAN_F25R2_FB28 ((uint32_t)0x10000000) +#define CAN_F25R2_FB29 ((uint32_t)0x20000000) +#define CAN_F25R2_FB30 ((uint32_t)0x40000000) +#define CAN_F25R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F26R2 register ********************/ +#define CAN_F26R2_FB0 ((uint32_t)0x00000001) +#define CAN_F26R2_FB1 ((uint32_t)0x00000002) +#define CAN_F26R2_FB2 ((uint32_t)0x00000004) +#define CAN_F26R2_FB3 ((uint32_t)0x00000008) +#define CAN_F26R2_FB4 ((uint32_t)0x00000010) +#define CAN_F26R2_FB5 ((uint32_t)0x00000020) +#define CAN_F26R2_FB6 ((uint32_t)0x00000040) +#define CAN_F26R2_FB7 ((uint32_t)0x00000080) +#define CAN_F26R2_FB8 ((uint32_t)0x00000100) +#define CAN_F26R2_FB9 ((uint32_t)0x00000200) +#define CAN_F26R2_FB10 ((uint32_t)0x00000400) +#define CAN_F26R2_FB11 ((uint32_t)0x00000800) +#define CAN_F26R2_FB12 ((uint32_t)0x00001000) +#define CAN_F26R2_FB13 ((uint32_t)0x00002000) +#define CAN_F26R2_FB14 ((uint32_t)0x00004000) +#define CAN_F26R2_FB15 ((uint32_t)0x00008000) +#define CAN_F26R2_FB16 ((uint32_t)0x00010000) +#define CAN_F26R2_FB17 ((uint32_t)0x00020000) +#define CAN_F26R2_FB18 ((uint32_t)0x00040000) +#define CAN_F26R2_FB19 ((uint32_t)0x00080000) +#define CAN_F26R2_FB20 ((uint32_t)0x00100000) +#define CAN_F26R2_FB21 ((uint32_t)0x00200000) +#define CAN_F26R2_FB22 ((uint32_t)0x00400000) +#define CAN_F26R2_FB23 ((uint32_t)0x00800000) +#define CAN_F26R2_FB24 ((uint32_t)0x01000000) +#define CAN_F26R2_FB25 ((uint32_t)0x02000000) +#define CAN_F26R2_FB26 ((uint32_t)0x04000000) +#define CAN_F26R2_FB27 ((uint32_t)0x08000000) +#define CAN_F26R2_FB28 ((uint32_t)0x10000000) +#define CAN_F26R2_FB29 ((uint32_t)0x20000000) +#define CAN_F26R2_FB30 ((uint32_t)0x40000000) +#define CAN_F26R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F27R2 register ********************/ +#define CAN_F27R2_FB0 ((uint32_t)0x00000001) +#define CAN_F27R2_FB1 ((uint32_t)0x00000002) +#define CAN_F27R2_FB2 ((uint32_t)0x00000004) +#define CAN_F27R2_FB3 ((uint32_t)0x00000008) +#define CAN_F27R2_FB4 ((uint32_t)0x00000010) +#define CAN_F27R2_FB5 ((uint32_t)0x00000020) +#define CAN_F27R2_FB6 ((uint32_t)0x00000040) +#define CAN_F27R2_FB7 ((uint32_t)0x00000080) +#define CAN_F27R2_FB8 ((uint32_t)0x00000100) +#define CAN_F27R2_FB9 ((uint32_t)0x00000200) +#define CAN_F27R2_FB10 ((uint32_t)0x00000400) +#define CAN_F27R2_FB11 ((uint32_t)0x00000800) +#define CAN_F27R2_FB12 ((uint32_t)0x00001000) +#define CAN_F27R2_FB13 ((uint32_t)0x00002000) +#define CAN_F27R2_FB14 ((uint32_t)0x00004000) +#define CAN_F27R2_FB15 ((uint32_t)0x00008000) +#define CAN_F27R2_FB16 ((uint32_t)0x00010000) +#define CAN_F27R2_FB17 ((uint32_t)0x00020000) +#define CAN_F27R2_FB18 ((uint32_t)0x00040000) +#define CAN_F27R2_FB19 ((uint32_t)0x00080000) +#define CAN_F27R2_FB20 ((uint32_t)0x00100000) +#define CAN_F27R2_FB21 ((uint32_t)0x00200000) +#define CAN_F27R2_FB22 ((uint32_t)0x00400000) +#define CAN_F27R2_FB23 ((uint32_t)0x00800000) +#define CAN_F27R2_FB24 ((uint32_t)0x01000000) +#define CAN_F27R2_FB25 ((uint32_t)0x02000000) +#define CAN_F27R2_FB26 ((uint32_t)0x04000000) +#define CAN_F27R2_FB27 ((uint32_t)0x08000000) +#define CAN_F27R2_FB28 ((uint32_t)0x10000000) +#define CAN_F27R2_FB29 ((uint32_t)0x20000000) +#define CAN_F27R2_FB30 ((uint32_t)0x40000000) +#define CAN_F27R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F28R2 register ********************/ +#define CAN_F28R2_FB0 ((uint32_t)0x00000001) +#define CAN_F28R2_FB1 ((uint32_t)0x00000002) +#define CAN_F28R2_FB2 ((uint32_t)0x00000004) +#define CAN_F28R2_FB3 ((uint32_t)0x00000008) +#define CAN_F28R2_FB4 ((uint32_t)0x00000010) +#define CAN_F28R2_FB5 ((uint32_t)0x00000020) +#define CAN_F28R2_FB6 ((uint32_t)0x00000040) +#define CAN_F28R2_FB7 ((uint32_t)0x00000080) +#define CAN_F28R2_FB8 ((uint32_t)0x00000100) +#define CAN_F28R2_FB9 ((uint32_t)0x00000200) +#define CAN_F28R2_FB10 ((uint32_t)0x00000400) +#define CAN_F28R2_FB11 ((uint32_t)0x00000800) +#define CAN_F28R2_FB12 ((uint32_t)0x00001000) +#define CAN_F28R2_FB13 ((uint32_t)0x00002000) +#define CAN_F28R2_FB14 ((uint32_t)0x00004000) +#define CAN_F28R2_FB15 ((uint32_t)0x00008000) +#define CAN_F28R2_FB16 ((uint32_t)0x00010000) +#define CAN_F28R2_FB17 ((uint32_t)0x00020000) +#define CAN_F28R2_FB18 ((uint32_t)0x00040000) +#define CAN_F28R2_FB19 ((uint32_t)0x00080000) +#define CAN_F28R2_FB20 ((uint32_t)0x00100000) +#define CAN_F28R2_FB21 ((uint32_t)0x00200000) +#define CAN_F28R2_FB22 ((uint32_t)0x00400000) +#define CAN_F28R2_FB23 ((uint32_t)0x00800000) +#define CAN_F28R2_FB24 ((uint32_t)0x01000000) +#define CAN_F28R2_FB25 ((uint32_t)0x02000000) +#define CAN_F28R2_FB26 ((uint32_t)0x04000000) +#define CAN_F28R2_FB27 ((uint32_t)0x08000000) +#define CAN_F28R2_FB28 ((uint32_t)0x10000000) +#define CAN_F28R2_FB29 ((uint32_t)0x20000000) +#define CAN_F28R2_FB30 ((uint32_t)0x40000000) +#define CAN_F28R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F29R2 register ********************/ +#define CAN_F29R2_FB0 ((uint32_t)0x00000001) +#define CAN_F29R2_FB1 ((uint32_t)0x00000002) +#define CAN_F29R2_FB2 ((uint32_t)0x00000004) +#define CAN_F29R2_FB3 ((uint32_t)0x00000008) +#define CAN_F29R2_FB4 ((uint32_t)0x00000010) +#define CAN_F29R2_FB5 ((uint32_t)0x00000020) +#define CAN_F29R2_FB6 ((uint32_t)0x00000040) +#define CAN_F29R2_FB7 ((uint32_t)0x00000080) +#define CAN_F29R2_FB8 ((uint32_t)0x00000100) +#define CAN_F29R2_FB9 ((uint32_t)0x00000200) +#define CAN_F29R2_FB10 ((uint32_t)0x00000400) +#define CAN_F29R2_FB11 ((uint32_t)0x00000800) +#define CAN_F29R2_FB12 ((uint32_t)0x00001000) +#define CAN_F29R2_FB13 ((uint32_t)0x00002000) +#define CAN_F29R2_FB14 ((uint32_t)0x00004000) +#define CAN_F29R2_FB15 ((uint32_t)0x00008000) +#define CAN_F29R2_FB16 ((uint32_t)0x00010000) +#define CAN_F29R2_FB17 ((uint32_t)0x00020000) +#define CAN_F29R2_FB18 ((uint32_t)0x00040000) +#define CAN_F29R2_FB19 ((uint32_t)0x00080000) +#define CAN_F29R2_FB20 ((uint32_t)0x00100000) +#define CAN_F29R2_FB21 ((uint32_t)0x00200000) +#define CAN_F29R2_FB22 ((uint32_t)0x00400000) +#define CAN_F29R2_FB23 ((uint32_t)0x00800000) +#define CAN_F29R2_FB24 ((uint32_t)0x01000000) +#define CAN_F29R2_FB25 ((uint32_t)0x02000000) +#define CAN_F29R2_FB26 ((uint32_t)0x04000000) +#define CAN_F29R2_FB27 ((uint32_t)0x08000000) +#define CAN_F29R2_FB28 ((uint32_t)0x10000000) +#define CAN_F29R2_FB29 ((uint32_t)0x20000000) +#define CAN_F29R2_FB30 ((uint32_t)0x40000000) +#define CAN_F29R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F30R2 register ********************/ +#define CAN_F30R2_FB0 ((uint32_t)0x00000001) +#define CAN_F30R2_FB1 ((uint32_t)0x00000002) +#define CAN_F30R2_FB2 ((uint32_t)0x00000004) +#define CAN_F30R2_FB3 ((uint32_t)0x00000008) +#define CAN_F30R2_FB4 ((uint32_t)0x00000010) +#define CAN_F30R2_FB5 ((uint32_t)0x00000020) +#define CAN_F30R2_FB6 ((uint32_t)0x00000040) +#define CAN_F30R2_FB7 ((uint32_t)0x00000080) +#define CAN_F30R2_FB8 ((uint32_t)0x00000100) +#define CAN_F30R2_FB9 ((uint32_t)0x00000200) +#define CAN_F30R2_FB10 ((uint32_t)0x00000400) +#define CAN_F30R2_FB11 ((uint32_t)0x00000800) +#define CAN_F30R2_FB12 ((uint32_t)0x00001000) +#define CAN_F30R2_FB13 ((uint32_t)0x00002000) +#define CAN_F30R2_FB14 ((uint32_t)0x00004000) +#define CAN_F30R2_FB15 ((uint32_t)0x00008000) +#define CAN_F30R2_FB16 ((uint32_t)0x00010000) +#define CAN_F30R2_FB17 ((uint32_t)0x00020000) +#define CAN_F30R2_FB18 ((uint32_t)0x00040000) +#define CAN_F30R2_FB19 ((uint32_t)0x00080000) +#define CAN_F30R2_FB20 ((uint32_t)0x00100000) +#define CAN_F30R2_FB21 ((uint32_t)0x00200000) +#define CAN_F30R2_FB22 ((uint32_t)0x00400000) +#define CAN_F30R2_FB23 ((uint32_t)0x00800000) +#define CAN_F30R2_FB24 ((uint32_t)0x01000000) +#define CAN_F30R2_FB25 ((uint32_t)0x02000000) +#define CAN_F30R2_FB26 ((uint32_t)0x04000000) +#define CAN_F30R2_FB27 ((uint32_t)0x08000000) +#define CAN_F30R2_FB28 ((uint32_t)0x10000000) +#define CAN_F30R2_FB29 ((uint32_t)0x20000000) +#define CAN_F30R2_FB30 ((uint32_t)0x40000000) +#define CAN_F30R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F31R2 register ********************/ +#define CAN_F31R2_FB0 ((uint32_t)0x00000001) +#define CAN_F31R2_FB1 ((uint32_t)0x00000002) +#define CAN_F31R2_FB2 ((uint32_t)0x00000004) +#define CAN_F31R2_FB3 ((uint32_t)0x00000008) +#define CAN_F31R2_FB4 ((uint32_t)0x00000010) +#define CAN_F31R2_FB5 ((uint32_t)0x00000020) +#define CAN_F31R2_FB6 ((uint32_t)0x00000040) +#define CAN_F31R2_FB7 ((uint32_t)0x00000080) +#define CAN_F31R2_FB8 ((uint32_t)0x00000100) +#define CAN_F31R2_FB9 ((uint32_t)0x00000200) +#define CAN_F31R2_FB10 ((uint32_t)0x00000400) +#define CAN_F31R2_FB11 ((uint32_t)0x00000800) +#define CAN_F31R2_FB12 ((uint32_t)0x00001000) +#define CAN_F31R2_FB13 ((uint32_t)0x00002000) +#define CAN_F31R2_FB14 ((uint32_t)0x00004000) +#define CAN_F31R2_FB15 ((uint32_t)0x00008000) +#define CAN_F31R2_FB16 ((uint32_t)0x00010000) +#define CAN_F31R2_FB17 ((uint32_t)0x00020000) +#define CAN_F31R2_FB18 ((uint32_t)0x00040000) +#define CAN_F31R2_FB19 ((uint32_t)0x00080000) +#define CAN_F31R2_FB20 ((uint32_t)0x00100000) +#define CAN_F31R2_FB21 ((uint32_t)0x00200000) +#define CAN_F31R2_FB22 ((uint32_t)0x00400000) +#define CAN_F31R2_FB23 ((uint32_t)0x00800000) +#define CAN_F31R2_FB24 ((uint32_t)0x01000000) +#define CAN_F31R2_FB25 ((uint32_t)0x02000000) +#define CAN_F31R2_FB26 ((uint32_t)0x04000000) +#define CAN_F31R2_FB27 ((uint32_t)0x08000000) +#define CAN_F31R2_FB28 ((uint32_t)0x10000000) +#define CAN_F31R2_FB29 ((uint32_t)0x20000000) +#define CAN_F31R2_FB30 ((uint32_t)0x40000000) +#define CAN_F31R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F32R2 register ********************/ +#define CAN_F32R2_FB0 ((uint32_t)0x00000001) +#define CAN_F32R2_FB1 ((uint32_t)0x00000002) +#define CAN_F32R2_FB2 ((uint32_t)0x00000004) +#define CAN_F32R2_FB3 ((uint32_t)0x00000008) +#define CAN_F32R2_FB4 ((uint32_t)0x00000010) +#define CAN_F32R2_FB5 ((uint32_t)0x00000020) +#define CAN_F32R2_FB6 ((uint32_t)0x00000040) +#define CAN_F32R2_FB7 ((uint32_t)0x00000080) +#define CAN_F32R2_FB8 ((uint32_t)0x00000100) +#define CAN_F32R2_FB9 ((uint32_t)0x00000200) +#define CAN_F32R2_FB10 ((uint32_t)0x00000400) +#define CAN_F32R2_FB11 ((uint32_t)0x00000800) +#define CAN_F32R2_FB12 ((uint32_t)0x00001000) +#define CAN_F32R2_FB13 ((uint32_t)0x00002000) +#define CAN_F32R2_FB14 ((uint32_t)0x00004000) +#define CAN_F32R2_FB15 ((uint32_t)0x00008000) +#define CAN_F32R2_FB16 ((uint32_t)0x00010000) +#define CAN_F32R2_FB17 ((uint32_t)0x00020000) +#define CAN_F32R2_FB18 ((uint32_t)0x00040000) +#define CAN_F32R2_FB19 ((uint32_t)0x00080000) +#define CAN_F32R2_FB20 ((uint32_t)0x00100000) +#define CAN_F32R2_FB21 ((uint32_t)0x00200000) +#define CAN_F32R2_FB22 ((uint32_t)0x00400000) +#define CAN_F32R2_FB23 ((uint32_t)0x00800000) +#define CAN_F32R2_FB24 ((uint32_t)0x01000000) +#define CAN_F32R2_FB25 ((uint32_t)0x02000000) +#define CAN_F32R2_FB26 ((uint32_t)0x04000000) +#define CAN_F32R2_FB27 ((uint32_t)0x08000000) +#define CAN_F32R2_FB28 ((uint32_t)0x10000000) +#define CAN_F32R2_FB29 ((uint32_t)0x20000000) +#define CAN_F32R2_FB30 ((uint32_t)0x40000000) +#define CAN_F32R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F33R2 register ********************/ +#define CAN_F33R2_FB0 ((uint32_t)0x00000001) +#define CAN_F33R2_FB1 ((uint32_t)0x00000002) +#define CAN_F33R2_FB2 ((uint32_t)0x00000004) +#define CAN_F33R2_FB3 ((uint32_t)0x00000008) +#define CAN_F33R2_FB4 ((uint32_t)0x00000010) +#define CAN_F33R2_FB5 ((uint32_t)0x00000020) +#define CAN_F33R2_FB6 ((uint32_t)0x00000040) +#define CAN_F33R2_FB7 ((uint32_t)0x00000080) +#define CAN_F33R2_FB8 ((uint32_t)0x00000100) +#define CAN_F33R2_FB9 ((uint32_t)0x00000200) +#define CAN_F33R2_FB10 ((uint32_t)0x00000400) +#define CAN_F33R2_FB11 ((uint32_t)0x00000800) +#define CAN_F33R2_FB12 ((uint32_t)0x00001000) +#define CAN_F33R2_FB13 ((uint32_t)0x00002000) +#define CAN_F33R2_FB14 ((uint32_t)0x00004000) +#define CAN_F33R2_FB15 ((uint32_t)0x00008000) +#define CAN_F33R2_FB16 ((uint32_t)0x00010000) +#define CAN_F33R2_FB17 ((uint32_t)0x00020000) +#define CAN_F33R2_FB18 ((uint32_t)0x00040000) +#define CAN_F33R2_FB19 ((uint32_t)0x00080000) +#define CAN_F33R2_FB20 ((uint32_t)0x00100000) +#define CAN_F33R2_FB21 ((uint32_t)0x00200000) +#define CAN_F33R2_FB22 ((uint32_t)0x00400000) +#define CAN_F33R2_FB23 ((uint32_t)0x00800000) +#define CAN_F33R2_FB24 ((uint32_t)0x01000000) +#define CAN_F33R2_FB25 ((uint32_t)0x02000000) +#define CAN_F33R2_FB26 ((uint32_t)0x04000000) +#define CAN_F33R2_FB27 ((uint32_t)0x08000000) +#define CAN_F33R2_FB28 ((uint32_t)0x10000000) +#define CAN_F33R2_FB29 ((uint32_t)0x20000000) +#define CAN_F33R2_FB30 ((uint32_t)0x40000000) +#define CAN_F33R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F34R2 register ********************/ +#define CAN_F34R2_FB0 ((uint32_t)0x00000001) +#define CAN_F34R2_FB1 ((uint32_t)0x00000002) +#define CAN_F34R2_FB2 ((uint32_t)0x00000004) +#define CAN_F34R2_FB3 ((uint32_t)0x00000008) +#define CAN_F34R2_FB4 ((uint32_t)0x00000010) +#define CAN_F34R2_FB5 ((uint32_t)0x00000020) +#define CAN_F34R2_FB6 ((uint32_t)0x00000040) +#define CAN_F34R2_FB7 ((uint32_t)0x00000080) +#define CAN_F34R2_FB8 ((uint32_t)0x00000100) +#define CAN_F34R2_FB9 ((uint32_t)0x00000200) +#define CAN_F34R2_FB10 ((uint32_t)0x00000400) +#define CAN_F34R2_FB11 ((uint32_t)0x00000800) +#define CAN_F34R2_FB12 ((uint32_t)0x00001000) +#define CAN_F34R2_FB13 ((uint32_t)0x00002000) +#define CAN_F34R2_FB14 ((uint32_t)0x00004000) +#define CAN_F34R2_FB15 ((uint32_t)0x00008000) +#define CAN_F34R2_FB16 ((uint32_t)0x00010000) +#define CAN_F34R2_FB17 ((uint32_t)0x00020000) +#define CAN_F34R2_FB18 ((uint32_t)0x00040000) +#define CAN_F34R2_FB19 ((uint32_t)0x00080000) +#define CAN_F34R2_FB20 ((uint32_t)0x00100000) +#define CAN_F34R2_FB21 ((uint32_t)0x00200000) +#define CAN_F34R2_FB22 ((uint32_t)0x00400000) +#define CAN_F34R2_FB23 ((uint32_t)0x00800000) +#define CAN_F34R2_FB24 ((uint32_t)0x01000000) +#define CAN_F34R2_FB25 ((uint32_t)0x02000000) +#define CAN_F34R2_FB26 ((uint32_t)0x04000000) +#define CAN_F34R2_FB27 ((uint32_t)0x08000000) +#define CAN_F34R2_FB28 ((uint32_t)0x10000000) +#define CAN_F34R2_FB29 ((uint32_t)0x20000000) +#define CAN_F34R2_FB30 ((uint32_t)0x40000000) +#define CAN_F34R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F35R2 register ********************/ +#define CAN_F35R2_FB0 ((uint32_t)0x00000001) +#define CAN_F35R2_FB1 ((uint32_t)0x00000002) +#define CAN_F35R2_FB2 ((uint32_t)0x00000004) +#define CAN_F35R2_FB3 ((uint32_t)0x00000008) +#define CAN_F35R2_FB4 ((uint32_t)0x00000010) +#define CAN_F35R2_FB5 ((uint32_t)0x00000020) +#define CAN_F35R2_FB6 ((uint32_t)0x00000040) +#define CAN_F35R2_FB7 ((uint32_t)0x00000080) +#define CAN_F35R2_FB8 ((uint32_t)0x00000100) +#define CAN_F35R2_FB9 ((uint32_t)0x00000200) +#define CAN_F35R2_FB10 ((uint32_t)0x00000400) +#define CAN_F35R2_FB11 ((uint32_t)0x00000800) +#define CAN_F35R2_FB12 ((uint32_t)0x00001000) +#define CAN_F35R2_FB13 ((uint32_t)0x00002000) +#define CAN_F35R2_FB14 ((uint32_t)0x00004000) +#define CAN_F35R2_FB15 ((uint32_t)0x00008000) +#define CAN_F35R2_FB16 ((uint32_t)0x00010000) +#define CAN_F35R2_FB17 ((uint32_t)0x00020000) +#define CAN_F35R2_FB18 ((uint32_t)0x00040000) +#define CAN_F35R2_FB19 ((uint32_t)0x00080000) +#define CAN_F35R2_FB20 ((uint32_t)0x00100000) +#define CAN_F35R2_FB21 ((uint32_t)0x00200000) +#define CAN_F35R2_FB22 ((uint32_t)0x00400000) +#define CAN_F35R2_FB23 ((uint32_t)0x00800000) +#define CAN_F35R2_FB24 ((uint32_t)0x01000000) +#define CAN_F35R2_FB25 ((uint32_t)0x02000000) +#define CAN_F35R2_FB26 ((uint32_t)0x04000000) +#define CAN_F35R2_FB27 ((uint32_t)0x08000000) +#define CAN_F35R2_FB28 ((uint32_t)0x10000000) +#define CAN_F35R2_FB29 ((uint32_t)0x20000000) +#define CAN_F35R2_FB30 ((uint32_t)0x40000000) +#define CAN_F35R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F36R2 register ********************/ +#define CAN_F36R2_FB0 ((uint32_t)0x00000001) +#define CAN_F36R2_FB1 ((uint32_t)0x00000002) +#define CAN_F36R2_FB2 ((uint32_t)0x00000004) +#define CAN_F36R2_FB3 ((uint32_t)0x00000008) +#define CAN_F36R2_FB4 ((uint32_t)0x00000010) +#define CAN_F36R2_FB5 ((uint32_t)0x00000020) +#define CAN_F36R2_FB6 ((uint32_t)0x00000040) +#define CAN_F36R2_FB7 ((uint32_t)0x00000080) +#define CAN_F36R2_FB8 ((uint32_t)0x00000100) +#define CAN_F36R2_FB9 ((uint32_t)0x00000200) +#define CAN_F36R2_FB10 ((uint32_t)0x00000400) +#define CAN_F36R2_FB11 ((uint32_t)0x00000800) +#define CAN_F36R2_FB12 ((uint32_t)0x00001000) +#define CAN_F36R2_FB13 ((uint32_t)0x00002000) +#define CAN_F36R2_FB14 ((uint32_t)0x00004000) +#define CAN_F36R2_FB15 ((uint32_t)0x00008000) +#define CAN_F36R2_FB16 ((uint32_t)0x00010000) +#define CAN_F36R2_FB17 ((uint32_t)0x00020000) +#define CAN_F36R2_FB18 ((uint32_t)0x00040000) +#define CAN_F36R2_FB19 ((uint32_t)0x00080000) +#define CAN_F36R2_FB20 ((uint32_t)0x00100000) +#define CAN_F36R2_FB21 ((uint32_t)0x00200000) +#define CAN_F36R2_FB22 ((uint32_t)0x00400000) +#define CAN_F36R2_FB23 ((uint32_t)0x00800000) +#define CAN_F36R2_FB24 ((uint32_t)0x01000000) +#define CAN_F36R2_FB25 ((uint32_t)0x02000000) +#define CAN_F36R2_FB26 ((uint32_t)0x04000000) +#define CAN_F36R2_FB27 ((uint32_t)0x08000000) +#define CAN_F36R2_FB28 ((uint32_t)0x10000000) +#define CAN_F36R2_FB29 ((uint32_t)0x20000000) +#define CAN_F36R2_FB30 ((uint32_t)0x40000000) +#define CAN_F36R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F37R2 register ********************/ +#define CAN_F37R2_FB0 ((uint32_t)0x00000001) +#define CAN_F37R2_FB1 ((uint32_t)0x00000002) +#define CAN_F37R2_FB2 ((uint32_t)0x00000004) +#define CAN_F37R2_FB3 ((uint32_t)0x00000008) +#define CAN_F37R2_FB4 ((uint32_t)0x00000010) +#define CAN_F37R2_FB5 ((uint32_t)0x00000020) +#define CAN_F37R2_FB6 ((uint32_t)0x00000040) +#define CAN_F37R2_FB7 ((uint32_t)0x00000080) +#define CAN_F37R2_FB8 ((uint32_t)0x00000100) +#define CAN_F37R2_FB9 ((uint32_t)0x00000200) +#define CAN_F37R2_FB10 ((uint32_t)0x00000400) +#define CAN_F37R2_FB11 ((uint32_t)0x00000800) +#define CAN_F37R2_FB12 ((uint32_t)0x00001000) +#define CAN_F37R2_FB13 ((uint32_t)0x00002000) +#define CAN_F37R2_FB14 ((uint32_t)0x00004000) +#define CAN_F37R2_FB15 ((uint32_t)0x00008000) +#define CAN_F37R2_FB16 ((uint32_t)0x00010000) +#define CAN_F37R2_FB17 ((uint32_t)0x00020000) +#define CAN_F37R2_FB18 ((uint32_t)0x00040000) +#define CAN_F37R2_FB19 ((uint32_t)0x00080000) +#define CAN_F37R2_FB20 ((uint32_t)0x00100000) +#define CAN_F37R2_FB21 ((uint32_t)0x00200000) +#define CAN_F37R2_FB22 ((uint32_t)0x00400000) +#define CAN_F37R2_FB23 ((uint32_t)0x00800000) +#define CAN_F37R2_FB24 ((uint32_t)0x01000000) +#define CAN_F37R2_FB25 ((uint32_t)0x02000000) +#define CAN_F37R2_FB26 ((uint32_t)0x04000000) +#define CAN_F37R2_FB27 ((uint32_t)0x08000000) +#define CAN_F37R2_FB28 ((uint32_t)0x10000000) +#define CAN_F37R2_FB29 ((uint32_t)0x20000000) +#define CAN_F37R2_FB30 ((uint32_t)0x40000000) +#define CAN_F37R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F38R2 register ********************/ +#define CAN_F38R2_FB0 ((uint32_t)0x00000001) +#define CAN_F38R2_FB1 ((uint32_t)0x00000002) +#define CAN_F38R2_FB2 ((uint32_t)0x00000004) +#define CAN_F38R2_FB3 ((uint32_t)0x00000008) +#define CAN_F38R2_FB4 ((uint32_t)0x00000010) +#define CAN_F38R2_FB5 ((uint32_t)0x00000020) +#define CAN_F38R2_FB6 ((uint32_t)0x00000040) +#define CAN_F38R2_FB7 ((uint32_t)0x00000080) +#define CAN_F38R2_FB8 ((uint32_t)0x00000100) +#define CAN_F38R2_FB9 ((uint32_t)0x00000200) +#define CAN_F38R2_FB10 ((uint32_t)0x00000400) +#define CAN_F38R2_FB11 ((uint32_t)0x00000800) +#define CAN_F38R2_FB12 ((uint32_t)0x00001000) +#define CAN_F38R2_FB13 ((uint32_t)0x00002000) +#define CAN_F38R2_FB14 ((uint32_t)0x00004000) +#define CAN_F38R2_FB15 ((uint32_t)0x00008000) +#define CAN_F38R2_FB16 ((uint32_t)0x00010000) +#define CAN_F38R2_FB17 ((uint32_t)0x00020000) +#define CAN_F38R2_FB18 ((uint32_t)0x00040000) +#define CAN_F38R2_FB19 ((uint32_t)0x00080000) +#define CAN_F38R2_FB20 ((uint32_t)0x00100000) +#define CAN_F38R2_FB21 ((uint32_t)0x00200000) +#define CAN_F38R2_FB22 ((uint32_t)0x00400000) +#define CAN_F38R2_FB23 ((uint32_t)0x00800000) +#define CAN_F38R2_FB24 ((uint32_t)0x01000000) +#define CAN_F38R2_FB25 ((uint32_t)0x02000000) +#define CAN_F38R2_FB26 ((uint32_t)0x04000000) +#define CAN_F38R2_FB27 ((uint32_t)0x08000000) +#define CAN_F38R2_FB28 ((uint32_t)0x10000000) +#define CAN_F38R2_FB29 ((uint32_t)0x20000000) +#define CAN_F38R2_FB30 ((uint32_t)0x40000000) +#define CAN_F38R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F39R2 register ********************/ +#define CAN_F39R2_FB0 ((uint32_t)0x00000001) +#define CAN_F39R2_FB1 ((uint32_t)0x00000002) +#define CAN_F39R2_FB2 ((uint32_t)0x00000004) +#define CAN_F39R2_FB3 ((uint32_t)0x00000008) +#define CAN_F39R2_FB4 ((uint32_t)0x00000010) +#define CAN_F39R2_FB5 ((uint32_t)0x00000020) +#define CAN_F39R2_FB6 ((uint32_t)0x00000040) +#define CAN_F39R2_FB7 ((uint32_t)0x00000080) +#define CAN_F39R2_FB8 ((uint32_t)0x00000100) +#define CAN_F39R2_FB9 ((uint32_t)0x00000200) +#define CAN_F39R2_FB10 ((uint32_t)0x00000400) +#define CAN_F39R2_FB11 ((uint32_t)0x00000800) +#define CAN_F39R2_FB12 ((uint32_t)0x00001000) +#define CAN_F39R2_FB13 ((uint32_t)0x00002000) +#define CAN_F39R2_FB14 ((uint32_t)0x00004000) +#define CAN_F39R2_FB15 ((uint32_t)0x00008000) +#define CAN_F39R2_FB16 ((uint32_t)0x00010000) +#define CAN_F39R2_FB17 ((uint32_t)0x00020000) +#define CAN_F39R2_FB18 ((uint32_t)0x00040000) +#define CAN_F39R2_FB19 ((uint32_t)0x00080000) +#define CAN_F39R2_FB20 ((uint32_t)0x00100000) +#define CAN_F39R2_FB21 ((uint32_t)0x00200000) +#define CAN_F39R2_FB22 ((uint32_t)0x00400000) +#define CAN_F39R2_FB23 ((uint32_t)0x00800000) +#define CAN_F39R2_FB24 ((uint32_t)0x01000000) +#define CAN_F39R2_FB25 ((uint32_t)0x02000000) +#define CAN_F39R2_FB26 ((uint32_t)0x04000000) +#define CAN_F39R2_FB27 ((uint32_t)0x08000000) +#define CAN_F39R2_FB28 ((uint32_t)0x10000000) +#define CAN_F39R2_FB29 ((uint32_t)0x20000000) +#define CAN_F39R2_FB30 ((uint32_t)0x40000000) +#define CAN_F39R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F40R2 register ********************/ +#define CAN_F40R2_FB0 ((uint32_t)0x00000001) +#define CAN_F40R2_FB1 ((uint32_t)0x00000002) +#define CAN_F40R2_FB2 ((uint32_t)0x00000004) +#define CAN_F40R2_FB3 ((uint32_t)0x00000008) +#define CAN_F40R2_FB4 ((uint32_t)0x00000010) +#define CAN_F40R2_FB5 ((uint32_t)0x00000020) +#define CAN_F40R2_FB6 ((uint32_t)0x00000040) +#define CAN_F40R2_FB7 ((uint32_t)0x00000080) +#define CAN_F40R2_FB8 ((uint32_t)0x00000100) +#define CAN_F40R2_FB9 ((uint32_t)0x00000200) +#define CAN_F40R2_FB10 ((uint32_t)0x00000400) +#define CAN_F40R2_FB11 ((uint32_t)0x00000800) +#define CAN_F40R2_FB12 ((uint32_t)0x00001000) +#define CAN_F40R2_FB13 ((uint32_t)0x00002000) +#define CAN_F40R2_FB14 ((uint32_t)0x00004000) +#define CAN_F40R2_FB15 ((uint32_t)0x00008000) +#define CAN_F40R2_FB16 ((uint32_t)0x00010000) +#define CAN_F40R2_FB17 ((uint32_t)0x00020000) +#define CAN_F40R2_FB18 ((uint32_t)0x00040000) +#define CAN_F40R2_FB19 ((uint32_t)0x00080000) +#define CAN_F40R2_FB20 ((uint32_t)0x00100000) +#define CAN_F40R2_FB21 ((uint32_t)0x00200000) +#define CAN_F40R2_FB22 ((uint32_t)0x00400000) +#define CAN_F40R2_FB23 ((uint32_t)0x00800000) +#define CAN_F40R2_FB24 ((uint32_t)0x01000000) +#define CAN_F40R2_FB25 ((uint32_t)0x02000000) +#define CAN_F40R2_FB26 ((uint32_t)0x04000000) +#define CAN_F40R2_FB27 ((uint32_t)0x08000000) +#define CAN_F40R2_FB28 ((uint32_t)0x10000000) +#define CAN_F40R2_FB29 ((uint32_t)0x20000000) +#define CAN_F40R2_FB30 ((uint32_t)0x40000000) +#define CAN_F40R2_FB31 ((uint32_t)0x80000000) + +/******************** Bit definition for CAN_F41R2 register ********************/ +#define CAN_F41R2_FB0 ((uint32_t)0x00000001) +#define CAN_F41R2_FB1 ((uint32_t)0x00000002) +#define CAN_F41R2_FB2 ((uint32_t)0x00000004) +#define CAN_F41R2_FB3 ((uint32_t)0x00000008) +#define CAN_F41R2_FB4 ((uint32_t)0x00000010) +#define CAN_F41R2_FB5 ((uint32_t)0x00000020) +#define CAN_F41R2_FB6 ((uint32_t)0x00000040) +#define CAN_F41R2_FB7 ((uint32_t)0x00000080) +#define CAN_F41R2_FB8 ((uint32_t)0x00000100) +#define CAN_F41R2_FB9 ((uint32_t)0x00000200) +#define CAN_F41R2_FB10 ((uint32_t)0x00000400) +#define CAN_F41R2_FB11 ((uint32_t)0x00000800) +#define CAN_F41R2_FB12 ((uint32_t)0x00001000) +#define CAN_F41R2_FB13 ((uint32_t)0x00002000) +#define CAN_F41R2_FB14 ((uint32_t)0x00004000) +#define CAN_F41R2_FB15 ((uint32_t)0x00008000) +#define CAN_F41R2_FB16 ((uint32_t)0x00010000) +#define CAN_F41R2_FB17 ((uint32_t)0x00020000) +#define CAN_F41R2_FB18 ((uint32_t)0x00040000) +#define CAN_F41R2_FB19 ((uint32_t)0x00080000) +#define CAN_F41R2_FB20 ((uint32_t)0x00100000) +#define CAN_F41R2_FB21 ((uint32_t)0x00200000) +#define CAN_F41R2_FB22 ((uint32_t)0x00400000) +#define CAN_F41R2_FB23 ((uint32_t)0x00800000) +#define CAN_F41R2_FB24 ((uint32_t)0x01000000) +#define CAN_F41R2_FB25 ((uint32_t)0x02000000) +#define CAN_F41R2_FB26 ((uint32_t)0x04000000) +#define CAN_F41R2_FB27 ((uint32_t)0x08000000) +#define CAN_F41R2_FB28 ((uint32_t)0x10000000) +#define CAN_F41R2_FB29 ((uint32_t)0x20000000) +#define CAN_F41R2_FB30 ((uint32_t)0x40000000) +#define CAN_F41R2_FB31 ((uint32_t)0x80000000) + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCFGR_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR8 register *******************/ +#define DMA_CFGR8_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR8_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR8_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR8_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR8_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR8_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR1 register *******************/ +#define DMA_M1ADDR1_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR2 register *******************/ +#define DMA_M1ADDR2_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR3 register *******************/ +#define DMA_M1ADDR3_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR4 register *******************/ +#define DMA_M1ADDR4_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR5 register *******************/ +#define DMA_M1ADDR5_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR6 register *******************/ +#define DMA_M1ADDR6_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR7 register *******************/ +#define DMA_M1ADDR7_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_M1ADDR8 register *******************/ +#define DMA_M1ADDR8_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MUX0_3_CFGR register *******************/ +#define DMA_MUX_CH0 ((uint32_t)0x0000007F) +#define DMA_MUX_CH1 ((uint32_t)0x00007F00) +#define DMA_MUX_CH2 ((uint32_t)0x007F0000) +#define DMA_MUX_CH3 ((uint32_t)0x7F000000) + +/****************** Bit definition for DMA_MUX4_7_CFGR register *******************/ +#define DMA_MUX_CH4 ((uint32_t)0x0000007F) +#define DMA_MUX_CH5 ((uint32_t)0x00007F00) +#define DMA_MUX_CH6 ((uint32_t)0x007F0000) +#define DMA_MUX_CH7 ((uint32_t)0x7F000000) + +/****************** Bit definition for DMA_MUX8_11_CFGR register *******************/ +#define DMA_MUX_CH8 ((uint32_t)0x0000007F) +#define DMA_MUX_CH9 ((uint32_t)0x00007F00) +#define DMA_MUX_CH10 ((uint32_t)0x007F0000) +#define DMA_MUX_CH11 ((uint32_t)0x7F000000) + +/****************** Bit definition for DMA_MUX12_15_CFGR register *******************/ +#define DMA_MUX_CH12 ((uint32_t)0x0000007F) +#define DMA_MUX_CH13 ((uint32_t)0x00007F00) +#define DMA_MUX_CH14 ((uint32_t)0x007F0000) +#define DMA_MUX_CH15 ((uint32_t)0x7F000000) + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ +#define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */ +#define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */ +#define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ +#define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */ +#define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */ +#define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ +#define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */ +#define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */ +#define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ +#define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */ +#define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */ +#define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ +#define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */ +#define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */ +#define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ +#define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */ +#define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */ +#define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ + +/****************** Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_SCK_CFG ((uint32_t)0x00000003) +#define FLASH_ACTLR_SCK_CFG_0 ((uint32_t)0x00000001) +#define FLASH_ACTLR_SCK_CFG_1 ((uint32_t)0x00000002) + +#define FLASH_ACTLR_LATENCY_HCLK_DIV1 ((uint32_t)0x00000000) +#define FLASH_ACTLR_LATENCY_HCLK_DIV2 ((uint32_t)0x00000001) +#define FLASH_ACTLR_LATENCY_HCLK_DIV4 ((uint32_t)0x00000002) + +#define FLASH_ACTLR_ENHANCE_STATUS ((uint32_t)0x00000040) +#define FLASH_ACTLR_EHMOD ((uint32_t)0x00000080) + +#define FLASH_ACTLR_LP ((uint32_t)0x00000100) +#define FLASH_ACTLR_RD_MD ((uint32_t)0x00000800) +#define FLASH_ACTLR_READY ((uint32_t)0x00004000) +#define FLASH_ACTLR_ST ((uint32_t)0x00008000) + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRBSY ((uint8_t)0x02) +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) +#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) +#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) +#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ +#define FLASH_CTLR_RSENACT ((uint32_t)0x00400000) + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x0304) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* nRST_STOP */ + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_PCFR1 register ******************/ +#define AFIO_PCFR1_PD0_1_REMAP ((uint32_t)0x00000001) +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00000002) +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00000004) +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00000008) +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00000010) + +#define AFIO_PCFR1_UHSIF_CLK_REMAP ((uint32_t)0x000000C0) +#define AFIO_PCFR1_UHSIF_CLK_REMAP_0 ((uint32_t)0x00000040) +#define AFIO_PCFR1_UHSIF_CLK_REMAP_1 ((uint32_t)0x00000080) + +#define AFIO_PCFR1_UHSIF_PORT_REMAP ((uint32_t)0x00000300) +#define AFIO_PCFR1_UHSIF_PORT_REMAP_0 ((uint32_t)0x00000100) +#define AFIO_PCFR1_UHSIF_PORT_REMAP_1 ((uint32_t)0x00000200) + +#define AFIO_PCFR1_SDMMC_REMAP ((uint32_t)0x00000C00) +#define AFIO_PCFR1_SDMMC_REMAP_0 ((uint32_t)0x00000400) +#define AFIO_PCFR1_SDMMC_REMAP_1 ((uint32_t)0x00000800) + +#define AFIO_PCFR1_TIM2ITR1_REMAP ((uint32_t)0x00001000) + +#define AFIO_PCFR1_VIO18_IO_HSLV ((uint32_t)0x00010000) +#define AFIO_PCFR1_VIO33_IO_HSLV ((uint32_t)0x00020000) +#define AFIO_PCFR1_VDD33_IO_HSLV ((uint32_t)0x00040000) + +#define AFIO_PCFR1_USBPD_CC_HVT ((uint32_t)0x00100000) + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/****************** Bit definition for AFIO_AFLR register *******************/ +#define AFIO_AFLR_AFR0 ((uint32_t)0x0000000F) +#define AFIO_AFLR_AFR0_0 ((uint32_t)0x00000001) +#define AFIO_AFLR_AFR0_1 ((uint32_t)0x00000002) +#define AFIO_AFLR_AFR0_2 ((uint32_t)0x00000004) +#define AFIO_AFLR_AFR0_3 ((uint32_t)0x00000008) + +#define AFIO_AFLR_AFR1 ((uint32_t)0x000000F0) +#define AFIO_AFLR_AFR1_0 ((uint32_t)0x00000010) +#define AFIO_AFLR_AFR1_1 ((uint32_t)0x00000020) +#define AFIO_AFLR_AFR1_2 ((uint32_t)0x00000040) +#define AFIO_AFLR_AFR1_3 ((uint32_t)0x00000080) + +#define AFIO_AFLR_AFR2 ((uint32_t)0x00000F00) +#define AFIO_AFLR_AFR2_0 ((uint32_t)0x00000100) +#define AFIO_AFLR_AFR2_1 ((uint32_t)0x00000200) +#define AFIO_AFLR_AFR2_2 ((uint32_t)0x00000400) +#define AFIO_AFLR_AFR2_3 ((uint32_t)0x00000800) + +#define AFIO_AFLR_AFR3 ((uint32_t)0x0000F000) +#define AFIO_AFLR_AFR3_0 ((uint32_t)0x00001000) +#define AFIO_AFLR_AFR3_1 ((uint32_t)0x00002000) +#define AFIO_AFLR_AFR3_2 ((uint32_t)0x00004000) +#define AFIO_AFLR_AFR3_3 ((uint32_t)0x00008000) + +#define AFIO_AFLR_AFR4 ((uint32_t)0x000F0000) +#define AFIO_AFLR_AFR4_0 ((uint32_t)0x00010000) +#define AFIO_AFLR_AFR4_1 ((uint32_t)0x00020000) +#define AFIO_AFLR_AFR4_2 ((uint32_t)0x00040000) +#define AFIO_AFLR_AFR4_3 ((uint32_t)0x00080000) + +#define AFIO_AFLR_AFR5 ((uint32_t)0x00F00000) +#define AFIO_AFLR_AFR5_0 ((uint32_t)0x00100000) +#define AFIO_AFLR_AFR5_1 ((uint32_t)0x00200000) +#define AFIO_AFLR_AFR5_2 ((uint32_t)0x00400000) +#define AFIO_AFLR_AFR5_3 ((uint32_t)0x00800000) + +#define AFIO_AFLR_AFR6 ((uint32_t)0x0F000000) +#define AFIO_AFLR_AFR6_0 ((uint32_t)0x01000000) +#define AFIO_AFLR_AFR6_1 ((uint32_t)0x02000000) +#define AFIO_AFLR_AFR6_2 ((uint32_t)0x04000000) +#define AFIO_AFLR_AFR6_3 ((uint32_t)0x08000000) + +#define AFIO_AFLR_AFR7 ((uint32_t)0xF0000000) +#define AFIO_AFLR_AFR7_0 ((uint32_t)0x10000000) +#define AFIO_AFLR_AFR7_1 ((uint32_t)0x20000000) +#define AFIO_AFLR_AFR7_2 ((uint32_t)0x40000000) +#define AFIO_AFLR_AFR7_3 ((uint32_t)0x80000000) + +/****************** Bit definition for AFIO_AFHR register *******************/ +#define AFIO_AFHR_AFR8 ((uint32_t)0x0000000F) +#define AFIO_AFHR_AFR8_0 ((uint32_t)0x00000001) +#define AFIO_AFHR_AFR8_1 ((uint32_t)0x00000002) +#define AFIO_AFHR_AFR8_2 ((uint32_t)0x00000004) +#define AFIO_AFHR_AFR8_3 ((uint32_t)0x00000008) + +#define AFIO_AFHR_AFR9 ((uint32_t)0x000000F0) +#define AFIO_AFHR_AFR9_0 ((uint32_t)0x00000010) +#define AFIO_AFHR_AFR9_1 ((uint32_t)0x00000020) +#define AFIO_AFHR_AFR9_2 ((uint32_t)0x00000040) +#define AFIO_AFHR_AFR9_3 ((uint32_t)0x00000080) + +#define AFIO_AFHR_AFR10 ((uint32_t)0x00000F00) +#define AFIO_AFHR_AFR10_0 ((uint32_t)0x00000100) +#define AFIO_AFHR_AFR10_1 ((uint32_t)0x00000200) +#define AFIO_AFHR_AFR10_2 ((uint32_t)0x00000400) +#define AFIO_AFHR_AFR10_3 ((uint32_t)0x00000800) + +#define AFIO_AFHR_AFR11 ((uint32_t)0x0000F000) +#define AFIO_AFHR_AFR11_0 ((uint32_t)0x00001000) +#define AFIO_AFHR_AFR11_1 ((uint32_t)0x00002000) +#define AFIO_AFHR_AFR11_2 ((uint32_t)0x00004000) +#define AFIO_AFHR_AFR11_3 ((uint32_t)0x00008000) + +#define AFIO_AFHR_AFR12 ((uint32_t)0x000F0000) +#define AFIO_AFHR_AFR12_0 ((uint32_t)0x00010000) +#define AFIO_AFHR_AFR12_1 ((uint32_t)0x00020000) +#define AFIO_AFHR_AFR12_2 ((uint32_t)0x00040000) +#define AFIO_AFHR_AFR12_3 ((uint32_t)0x00080000) + +#define AFIO_AFHR_AFR13 ((uint32_t)0x00F00000) +#define AFIO_AFHR_AFR13_0 ((uint32_t)0x00100000) +#define AFIO_AFHR_AFR13_1 ((uint32_t)0x00200000) +#define AFIO_AFHR_AFR13_2 ((uint32_t)0x00400000) +#define AFIO_AFHR_AFR13_3 ((uint32_t)0x00800000) + +#define AFIO_AFHR_AFR14 ((uint32_t)0x0F000000) +#define AFIO_AFHR_AFR14_0 ((uint32_t)0x01000000) +#define AFIO_AFHR_AFR14_1 ((uint32_t)0x02000000) +#define AFIO_AFHR_AFR14_2 ((uint32_t)0x04000000) +#define AFIO_AFHR_AFR14_3 ((uint32_t)0x08000000) + +#define AFIO_AFHR_AFR15 ((uint32_t)0xF0000000) +#define AFIO_AFHR_AFR15_0 ((uint32_t)0x10000000) +#define AFIO_AFHR_AFR15_1 ((uint32_t)0x20000000) +#define AFIO_AFHR_AFR15_2 ((uint32_t)0x40000000) +#define AFIO_AFHR_AFR15_3 ((uint32_t)0x80000000) + +/****************** Bit definition for AFIO_EXTICR1 register *******************/ +#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint32_t)0x000F0000) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00F00000) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint32_t)0x0F000000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint32_t)0xF0000000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_CMPOUT ((uint32_t)0x00000006) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_CMPOUT ((uint32_t)0x00000060) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_CMPOUT ((uint32_t)0x00000600) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_CMPOUT ((uint32_t)0x00006000) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00010000) /* PB[4] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00020000) /* PC[4] pin */ +#define AFIO_EXTICR1_EXTI4_PD ((uint32_t)0x00030000) /* PD[4] pin */ +#define AFIO_EXTICR1_EXTI4_PE ((uint32_t)0x00040000) /* PE[4] pin */ +#define AFIO_EXTICR1_EXTI4_PF ((uint32_t)0x00050000) /* PF[4] pin */ +#define AFIO_EXTICR1_EXTI4_CMPOUT ((uint32_t)0x00060000) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00100000) /* PB[5] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00200000) /* PC[5] pin */ +#define AFIO_EXTICR1_EXTI5_PD ((uint32_t)0x00300000) /* PD[5] pin */ +#define AFIO_EXTICR1_EXTI5_PE ((uint32_t)0x00400000) /* PE[5] pin */ +#define AFIO_EXTICR1_EXTI5_PF ((uint32_t)0x00500000) /* PF[5] pin */ +#define AFIO_EXTICR1_EXTI5_CMPOUT ((uint32_t)0x00600000) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x01000000) /* PB[6] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x02000000) /* PC[6] pin */ +#define AFIO_EXTICR1_EXTI6_PD ((uint32_t)0x03000000) /* PD[6] pin */ +#define AFIO_EXTICR1_EXTI6_PE ((uint32_t)0x04000000) /* PE[6] pin */ +#define AFIO_EXTICR1_EXTI6_PF ((uint32_t)0x05000000) /* PF[6] pin */ +#define AFIO_EXTICR1_EXTI6_CMPOUT ((uint32_t)0x06000000) /* CMP OUT */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x10000000) /* PB[7] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x20000000) /* PC[7] pin */ +#define AFIO_EXTICR1_EXTI7_PD ((uint32_t)0x30000000) /* PD[7] pin */ +#define AFIO_EXTICR1_EXTI7_PE ((uint32_t)0x40000000) /* PE[7] pin */ +#define AFIO_EXTICR1_EXTI7_PF ((uint32_t)0x50000000) /* PF[7] pin */ +#define AFIO_EXTICR1_EXTI7_CMPOUT ((uint32_t)0x60000000) /* CMP OUT */ + +/****************** Bit definition for AFIO_EXTICR2 register *******************/ +#define AFIO_EXTICR2_EXTI8 ((uint32_t)0x0000000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR2_EXTI9 ((uint32_t)0x000000F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR2_EXTI10 ((uint32_t)0x00000F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR2_EXTI11 ((uint32_t)0x0000F000) /* EXTI 3 configuration */ +#define AFIO_EXTICR2_EXTI12 ((uint32_t)0x000F0000) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI13 ((uint32_t)0x00F00000) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI14 ((uint32_t)0x0F000000) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI15 ((uint32_t)0xF0000000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI8_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR2_EXTI8_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR2_EXTI8_PC ((uint32_t)0x00000002) /* PC[0] pin */ +#define AFIO_EXTICR2_EXTI8_PD ((uint32_t)0x00000003) /* PD[0] pin */ +#define AFIO_EXTICR2_EXTI8_PE ((uint32_t)0x00000004) /* PE[0] pin */ +#define AFIO_EXTICR2_EXTI8_PF ((uint32_t)0x00000005) /* PF[0] pin */ +#define AFIO_EXTICR2_EXTI8_CMPOUT ((uint32_t)0x00000006) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI9_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR2_EXTI9_PB ((uint32_t)0x00000010) /* PB[1] pin */ +#define AFIO_EXTICR2_EXTI9_PC ((uint32_t)0x00000020) /* PC[1] pin */ +#define AFIO_EXTICR2_EXTI9_PD ((uint32_t)0x00000030) /* PD[1] pin */ +#define AFIO_EXTICR2_EXTI9_PE ((uint32_t)0x00000040) /* PE[1] pin */ +#define AFIO_EXTICR2_EXTI9_PF ((uint32_t)0x00000050) /* PF[1] pin */ +#define AFIO_EXTICR2_EXTI9_CMPOUT ((uint32_t)0x00000060) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI10_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR2_EXTI10_PB ((uint32_t)0x00000100) /* PB[2] pin */ +#define AFIO_EXTICR2_EXTI10_PC ((uint32_t)0x00000200) /* PC[2] pin */ +#define AFIO_EXTICR2_EXTI10_PD ((uint32_t)0x00000300) /* PD[2] pin */ +#define AFIO_EXTICR2_EXTI10_PE ((uint32_t)0x00000400) /* PE[2] pin */ +#define AFIO_EXTICR2_EXTI10_PF ((uint32_t)0x00000500) /* PF[2] pin */ +#define AFIO_EXTICR2_EXTI10_CMPOUT ((uint32_t)0x00000600) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI11_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR2_EXTI11_PB ((uint32_t)0x00001000) /* PB[3] pin */ +#define AFIO_EXTICR2_EXTI11_PC ((uint32_t)0x00002000) /* PC[3] pin */ +#define AFIO_EXTICR2_EXTI11_PD ((uint32_t)0x00003000) /* PD[3] pin */ +#define AFIO_EXTICR2_EXTI11_PE ((uint32_t)0x00004000) /* PE[3] pin */ +#define AFIO_EXTICR2_EXTI11_PF ((uint32_t)0x00005000) /* PF[3] pin */ +#define AFIO_EXTICR2_EXTI11_CMPOUT ((uint32_t)0x00006000) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI12_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI12_PB ((uint32_t)0x00010000) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI12_PC ((uint32_t)0x00020000) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI12_PD ((uint32_t)0x00030000) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI12_PE ((uint32_t)0x00040000) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI12_PF ((uint32_t)0x00050000) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI12_CMPOUT ((uint32_t)0x00060000) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI13_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI13_PB ((uint32_t)0x00100000) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI13_PC ((uint32_t)0x00200000) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI13_PD ((uint32_t)0x00300000) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI13_PE ((uint32_t)0x00400000) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI13_PF ((uint32_t)0x00500000) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI13_CMPOUT ((uint32_t)0x00600000) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI14_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI14_PB ((uint32_t)0x01000000) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI14_PC ((uint32_t)0x02000000) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI14_PD ((uint32_t)0x03000000) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI14_PE ((uint32_t)0x04000000) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI14_PF ((uint32_t)0x05000000) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI14_CMPOUT ((uint32_t)0x06000000) /* CMP OUT */ + +#define AFIO_EXTICR2_EXTI15_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI15_PB ((uint32_t)0x10000000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI15_PC ((uint32_t)0x20000000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI15_PD ((uint32_t)0x30000000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI15_PE ((uint32_t)0x40000000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI15_PF ((uint32_t)0x50000000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI15_CMPOUT ((uint32_t)0x60000000) /* CMP OUT */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Improved Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I3C_CTLR register ********************/ +#define I3C_CTLR_DCNT ((uint32_t)0x0000FFFF) +#define I3C_CTLR_RNW ((uint32_t)0x00010000) +#define I3C_CTLR_ADD ((uint32_t)0x00FE0000) + +#define I3C_CTLR_CCC ((uint32_t)0x00FF0000) + +#define I3C_CTLR_MTYPE ((uint32_t)0x78000000) +#define I3C_CTLR_MTYPE_0 ((uint32_t)0x08000000) +#define I3C_CTLR_MTYPE_1 ((uint32_t)0x10000000) +#define I3C_CTLR_MTYPE_2 ((uint32_t)0x20000000) +#define I3C_CTLR_MTYPE_3 ((uint32_t)0x40000000) + +#define I3C_CTLR_MEND ((uint32_t)0x80000000) + +/******************* Bit definition for I3C_CFGR register ********************/ +#define I3C_CFGR_EN ((uint32_t)0x00000001) +#define I3C_CFGR_CRINIT ((uint32_t)0x00000002) +#define I3C_CFGR_NOARBH ((uint32_t)0x00000004) +#define I3C_CFGR_RSTPTRN ((uint32_t)0x00000008) +#define I3C_CFGR_EXITPTRN ((uint32_t)0x00000010) + +#define I3C_CFGR_HJACK ((uint32_t)0x00000080) +#define I3C_CFGR_RXDMAEN ((uint32_t)0x00000100) +#define I3C_CFGR_RXFLUSH ((uint32_t)0x00000200) +#define I3C_CFGR_RXTHRES ((uint32_t)0x00000400) + +#define I3C_CFGR_TXMAEN ((uint32_t)0x00001000) +#define I3C_CFGR_TXFLUSH ((uint32_t)0x00002000) +#define I3C_CFGR_TXTHRES ((uint32_t)0x00004000) + +#define I3C_CFGR_SDMAEN ((uint32_t)0x00010000) +#define I3C_CFGR_SFLUSH ((uint32_t)0x00020000) +#define I3C_CFGR_SMODE ((uint32_t)0x00040000) +#define I3C_CFGR_TMODE ((uint32_t)0x00080000) +#define I3C_CFGR_CDMAEN ((uint32_t)0x00010000) +#define I3C_CFGR_CFLUSH ((uint32_t)0x00020000) + +#define I3C_CFGR_TSFSET ((uint32_t)0x40000000) + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0 ((uint32_t)0x000000FF) + +/******************* Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDB0 ((uint32_t)0x000000FF) +#define I3C_RDWR_RDB1 ((uint32_t)0x0000FF00) +#define I3C_RDWR_RDB2 ((uint32_t)0x00FF0000) +#define I3C_RDWR_RDB3 ((uint32_t)0xFF000000) + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0 ((uint32_t)0x000000FF) + +/******************* Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDB0 ((uint32_t)0x000000FF) +#define I3C_TDWR_TDB1 ((uint32_t)0x0000FF00) +#define I3C_TDWR_TDB2 ((uint32_t)0x00FF0000) +#define I3C_TDWR_TDB3 ((uint32_t)0xFF000000) + +/******************* Bit definition for I3C_IBIDR register ********************/ +#define I3C_IBIDR_IBIDB0 ((uint32_t)0x000000FF) +#define I3C_IBIDR_IBIDB1 ((uint32_t)0x0000FF00) +#define I3C_IBIDR_IBIDB2 ((uint32_t)0x00FF0000) +#define I3C_IBIDR_IBIDB3 ((uint32_t)0xFF000000) + +/******************* Bit definition for I3C_TGTTDR register ********************/ +#define I3C_TGTTDR_TGTTDCNT ((uint32_t)0x0000FFFF) +#define I3C_TGTTDR_PRELOAD ((uint32_t)0x00010000) + +/******************* Bit definition for I3C_RESET register ********************/ +#define I3C_RESET_HST_SIE_RST ((uint32_t)0x01000000) +#define I3C_RESET_TGT_SIE_RST ((uint32_t)0x02000000) + +/******************* Bit definition for I3C_STATR register ********************/ +#define I3C_STATR_XDCNT ((uint32_t)0x0000FFFF) +#define I3C_STATR_ABT ((uint32_t)0x00020000) +#define I3C_STATR_DIR ((uint32_t)0x00040000) + +#define I3C_STATR_MID ((uint32_t)0xFF000000) + +/******************* Bit definition for I3C_STATER register ********************/ +#define I3C_STATER_CODERR ((uint32_t)0x0000000F) +#define I3C_STATER_PERR ((uint32_t)0x00000010) +#define I3C_STATER_STALL ((uint32_t)0x00000020) +#define I3C_STATER_DOVR ((uint32_t)0x00000040) +#define I3C_STATER_COVR ((uint32_t)0x00000080) +#define I3C_STATER_ANACK ((uint32_t)0x00000100) +#define I3C_STATER_DNACK ((uint32_t)0x00000200) +#define I3C_STATER_DERR ((uint32_t)0x00000400) + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT ((uint32_t)0x00000007) +#define I3C_RMR_RCODE ((uint32_t)0x0000FF00) +#define I3C_RMR_RADD ((uint32_t)0x00FE0000) + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF ((uint32_t)0x00000001) +#define I3C_EVR_TXFEF ((uint32_t)0x00000002) +#define I3C_EVR_CFNFF ((uint32_t)0x00000004) +#define I3C_EVR_SFNEF ((uint32_t)0x00000008) +#define I3C_EVR_TXFNFF ((uint32_t)0x00000010) +#define I3C_EVR_RXFNEF ((uint32_t)0x00000020) +#define I3C_EVR_TXLASTF ((uint32_t)0x00000040) +#define I3C_EVR_RXLASTF ((uint32_t)0x00000080) + +#define I3C_EVR_FCF ((uint32_t)0x00000200) +#define I3C_EVR_RXTGTENDF ((uint32_t)0x00000400) +#define I3C_EVR_ERRF ((uint32_t)0x00000800) + +#define I3C_EVR_IBIF ((uint32_t)0x00008000) +#define I3C_EVR_IBIENDF ((uint32_t)0x00010000) +#define I3C_EVR_CRF ((uint32_t)0x00020000) +#define I3C_EVR_CRUPDF ((uint32_t)0x00040000) +#define I3C_EVR_HJF ((uint32_t)0x00080000) +#define I3C_EVR_WKPF ((uint32_t)0x00200000) +#define I3C_EVR_GETF ((uint32_t)0x00400000) +#define I3C_EVR_STAF ((uint32_t)0x00800000) +#define I3C_EVR_DAUPDF ((uint32_t)0x01000000) +#define I3C_EVR_MWLUPDF ((uint32_t)0x02000000) +#define I3C_EVR_MRLUPDF ((uint32_t)0x04000000) +#define I3C_EVR_RSTF ((uint32_t)0x08000000) +#define I3C_EVR_ASUPDF ((uint32_t)0x10000000) +#define I3C_EVR_INTUPDF ((uint32_t)0x20000000) +#define I3C_EVR_DEFF ((uint32_t)0x40000000) +#define I3C_EVR_GRPF ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_INTENR register ******************/ +#define I3C_INTENR_CFNFIE ((uint32_t)0x00000004) +#define I3C_INTENR_SFNEIE ((uint32_t)0x00000008) +#define I3C_INTENR_TXFNEIE ((uint32_t)0x00000010) +#define I3C_INTENR_RXFNEIE ((uint32_t)0x00000020) + +#define I3C_INTENR_FCIE ((uint32_t)0x00000200) +#define I3C_INTENR_RXTGTENDIE ((uint32_t)0x00000400) +#define I3C_INTENR_ERRIE ((uint32_t)0x00000800) + +#define I3C_INTENR_IBIIE ((uint32_t)0x00008000) +#define I3C_INTENR_IBIENDIE ((uint32_t)0x00010000) +#define I3C_INTENR_CRIE ((uint32_t)0x00020000) +#define I3C_INTENR_CRUPDIE ((uint32_t)0x00040000) +#define I3C_INTENR_HJIE ((uint32_t)0x00080000) + +#define I3C_INTENR_WKPIE ((uint32_t)0x00200000) +#define I3C_INTENR_GETIE ((uint32_t)0x00400000) +#define I3C_INTENR_STAIE ((uint32_t)0x00800000) +#define I3C_INTENR_DAUPDIE ((uint32_t)0x01000000) +#define I3C_INTENR_MWLUPDIE ((uint32_t)0x02000000) +#define I3C_INTENR_MRLUPDIE ((uint32_t)0x04000000) +#define I3C_INTENR_RSTIE ((uint32_t)0x08000000) +#define I3C_INTENR_ASUPDIE ((uint32_t)0x10000000) +#define I3C_INTENR_INTUPDIE ((uint32_t)0x20000000) +#define I3C_INTENR_DEFIE ((uint32_t)0x40000000) +#define I3C_INTENR_GRPIE ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_CEVR register ******************/ +#define I3C_CEVR_CFCR ((uint32_t)0x00000200) +#define I3C_CEVR_CRXTGTENDF ((uint32_t)0x00000400) +#define I3C_CEVR_CERRF ((uint32_t)0x00000800) + +#define I3C_CEVR_CIBIF ((uint32_t)0x00008000) +#define I3C_CEVR_CIBIENDF ((uint32_t)0x00010000) +#define I3C_CEVR_CCRF ((uint32_t)0x00020000) +#define I3C_CEVR_CCRUPDF ((uint32_t)0x00040000) +#define I3C_CEVR_CHJF ((uint32_t)0x00080000) + +#define I3C_CEVR_CWKPF ((uint32_t)0x00200000) +#define I3C_CEVR_CGETF ((uint32_t)0x00400000) +#define I3C_CEVR_CSTAF ((uint32_t)0x00800000) +#define I3C_CEVR_CDAUPDF ((uint32_t)0x01000000) +#define I3C_CEVR_CMWLUPDF ((uint32_t)0x02000000) +#define I3C_CEVR_CMRLUPDF ((uint32_t)0x04000000) +#define I3C_CEVR_CRSTF ((uint32_t)0x08000000) +#define I3C_CEVR_CASUPDF ((uint32_t)0x10000000) +#define I3C_CEVR_CINTUPDF ((uint32_t)0x20000000) +#define I3C_CEVR_CDEFF ((uint32_t)0x40000000) +#define I3C_CEVR_CGRPF ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_DEVR0 register ******************/ +#define I3C_DEVR0_DAVAL ((uint32_t)0x00000001) +#define I3C_DEVR0_DA ((uint32_t)0x000000FE) + +#define I3C_DEVR0_IBIEN ((uint32_t)0x00010000) +#define I3C_DEVR0_CREN ((uint32_t)0x00020000) + +#define I3C_DEVR0_HJEN ((uint32_t)0x00080000) + +#define I3C_DEVR0_AS ((uint32_t)0x00300000) +#define I3C_DEVR0_AS_0 ((uint32_t)0x00100000) +#define I3C_DEVR0_AS_1 ((uint32_t)0x00200000) + +#define I3C_DEVR0_RSTACT ((uint32_t)0x00C00000) +#define I3C_DEVR0_RSTACT_0 ((uint32_t)0x00400000) +#define I3C_DEVR0_RSTACT_1 ((uint32_t)0x00800000) + +#define I3C_DEVR0_RSTVAL ((uint32_t)0x01000000) + +/***************** Bit definition for I3C_DEVR1 register ******************/ +#define I3C_DEVR1_DA ((uint32_t)0x000000FE) + +#define I3C_DEVR1_IBIACK ((uint32_t)0x00010000) +#define I3C_DEVR1_CRACK ((uint32_t)0x00020000) +#define I3C_DEVR1_IBIDEN ((uint32_t)0x00040000) +#define I3C_DEVR1_SUSP ((uint32_t)0x00080000) + +#define I3C_DEVR1_DIS ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_DEVR2 register ******************/ +#define I3C_DEVR2_DA ((uint32_t)0x000000FE) + +#define I3C_DEVR2_IBIACK ((uint32_t)0x00010000) +#define I3C_DEVR2_CRACK ((uint32_t)0x00020000) +#define I3C_DEVR2_IBIDEN ((uint32_t)0x00040000) +#define I3C_DEVR2_SUSP ((uint32_t)0x00080000) + +#define I3C_DEVR2_DIS ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_DEVR3 register ******************/ +#define I3C_DEVR3_DA ((uint32_t)0x000000FE) + +#define I3C_DEVR3_IBIACK ((uint32_t)0x00010000) +#define I3C_DEVR3_CRACK ((uint32_t)0x00020000) +#define I3C_DEVR3_IBIDEN ((uint32_t)0x00040000) +#define I3C_DEVR3_SUSP ((uint32_t)0x00080000) + +#define I3C_DEVR3_DIS ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_DEVR4 register ******************/ +#define I3C_DEVR4_DA ((uint32_t)0x000000FE) + +#define I3C_DEVR4_IBIACK ((uint32_t)0x00010000) +#define I3C_DEVR4_CRACK ((uint32_t)0x00020000) +#define I3C_DEVR4_IBIDEN ((uint32_t)0x00040000) +#define I3C_DEVR4_SUSP ((uint32_t)0x00080000) + +#define I3C_DEVR4_DIS ((uint32_t)0x80000000) + +/***************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL ((uint32_t)0x0000FFFF) + +#define I3C_MAXRLR_IBIP ((uint32_t)0x00070000) +#define I3C_MAXRLR_IBIP_0 ((uint32_t)0x00010000) +#define I3C_MAXRLR_IBIP_1 ((uint32_t)0x00020000) +#define I3C_MAXRLR_IBIP_2 ((uint32_t)0x00040000) + +/***************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL ((uint32_t)0x0000FFFF) + +/***************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP ((uint32_t)0x000000FF) +#define I3C_TIMINGR0_SCLH_I3C ((uint32_t)0x0000FF00) +#define I3C_TIMINGR0_SCLL_OD ((uint32_t)0x00FF0000) +#define I3C_TIMINGR0_SCLH_I2C ((uint32_t)0xFF000000) + +/***************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL ((uint32_t)0x000000FF) +#define I3C_TIMINGR1_ASNCR ((uint32_t)0x00000300) + +#define I3C_TIMINGR1_FREE ((uint32_t)0x007F0000) +#define I3C_TIMINGR1_SDA_HD ((uint32_t)0x10000000) + +/***************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT ((uint32_t)0x00000001) +#define I3C_TIMINGR2_STALLD ((uint32_t)0x00000002) +#define I3C_TIMINGR2_STALLC ((uint32_t)0x00000004) +#define I3C_TIMINGR2_STALLA ((uint32_t)0x00000008) + +#define I3C_TIMINGR2_STALL ((uint32_t)0x0000FF00) + +/***************** Bit definition for I3C_DCR register ******************/ +#define I3C_DCR ((uint32_t)0x000000FF) + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND ((uint32_t)0x00004000) + +/***************** Bit definition for I3C_CRCAPR register ******************/ +#define I3C_CRCAPR_CAPDHOFF ((uint32_t)0x00000008) +#define I3C_CRCAPR_CAPGRP ((uint32_t)0x00000200) + +/***************** Bit definition for I3C_GETMDSR register ******************/ +#define I3C_GETMDSR_HOFFAS ((uint32_t)0x00000003) +#define I3C_GETMDSR_HOFFAS_0 ((uint32_t)0x00000001) +#define I3C_GETMDSR_HOFFAS_1 ((uint32_t)0x00000002) + +#define I3C_GETMDSR_FMT ((uint32_t)0x00000300) +#define I3C_GETMDSR_FMT_0 ((uint32_t)0x00000100) +#define I3C_GETMDSR_FMT_1 ((uint32_t)0x00000200) + +#define I3C_GETMDSR_RDTURN ((uint32_t)0x00FF0000) +#define I3C_GETMDSR_TSCO ((uint32_t)0x01000000) + +/***************** Bit definition for I3C_EPIDR register ******************/ +#define I3C_EPIDR_MIPIID ((uint32_t)0x0000F000) +#define I3C_EPIDR_IDTSEL ((uint32_t)0x00010000) +#define I3C_EPIDR_MIPIMID ((uint32_t)0xFFFE0000) + +/******************************************************************************/ +/* LOW POWER TIM */ +/******************************************************************************/ +/******************* Bit definition for LPTIM_ISR register *******************/ +#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) +#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) +#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) +#define LPTIM_ISR_ARROK ((uint32_t)0000000010) +#define LPTIM_ISR_UP ((uint32_t)0x00000020) +#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) +#define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) + +/******************* Bit definition for LPTIM_ICR register *******************/ +#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) +#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) +#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) +#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) +#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) +#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) +#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_IER register *******************/ +#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) +#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) +#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) +#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) +#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) +#define LPTIM_IER_UPIE ((uint32_t)0x00000020) +#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_CFGR register *******************/ +#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) +#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) +#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) +#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) +#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) +#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) +#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) +#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) +#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) +#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) +#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) +#define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) +#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) +#define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) +#define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) + +/******************* Bit definition for LPTIM_CR register *******************/ +#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) +#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) +#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) +#define LPTIM_CR_OUTEN ((uint32_t)0x00000008) +#define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) + +/******************* Bit definition for LPTIM_CMP register *******************/ +#define LPTIM_CMP ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_ARR register *******************/ +#define LPTIM_ARR ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_COUNT ((uint32_t)0x0000FFFF) + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ +#define PWR_CTLR_VIO_SWCR ((uint16_t)0x0200) + +#define PWR_CTLR_VSEL_VIO18 ((uint16_t)0x1C00) +#define PWR_CTLR_VSEL_VIO18_0 ((uint16_t)0x0400) +#define PWR_CTLR_VSEL_VIO18_1 ((uint16_t)0x0800) +#define PWR_CTLR_VSEL_VIO18_2 ((uint16_t)0x1000) + +#define PWR_CTLR_VSEL_VIO18_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_VSEL_VIO18_MODE1 ((uint16_t)0x0400) +#define PWR_CTLR_VSEL_VIO18_MODE2 ((uint16_t)0x0800) +#define PWR_CTLR_VSEL_VIO18_MODE3 ((uint16_t)0x0C00) +#define PWR_CTLR_VSEL_VIO18_MODE4 ((uint16_t)0x1000) +#define PWR_CTLR_VSEL_VIO18_MODE5 ((uint16_t)0x1400) +#define PWR_CTLR_VSEL_VIO18_MODE6 ((uint16_t)0x1800) +#define PWR_CTLR_VSEL_VIO18_MODE7 ((uint16_t)0x1C00) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0001) + +#define PWR_CSR_VIO18_SR ((uint16_t)0x0300) +#define PWR_CSR_VIO18_SR_0 ((uint16_t)0x0100) +#define PWR_CSR_VIO18_SR_1 ((uint16_t)0x0200) + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_USBHS_PLLON ((uint32_t)0x00100000) +#define RCC_USBHS_PLLRDY ((uint32_t)0x00200000) +#define RCC_USBSS_PLLON ((uint32_t)0x00400000) +#define RCC_USBSS_PLLRDY ((uint32_t)0x00800000) +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ +#define RCC_ETH_PLLON ((uint32_t)0x04000000) +#define RCC_ETH_PLLRDY ((uint32_t)0x08000000) +#define RCC_SERDES_PLLON ((uint32_t)0x10000000) +#define RCC_SERDES_PLLRDY ((uint32_t)0x20000000) +#define RCC_CSS_HSE_DIS ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000500) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000600) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000700) /* HCLK divided by 8 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_TIM_DIV1 ((uint32_t)0x00000000) /* HCLK divided by 1 for TIM1,8,9,10*/ +#define RCC_PPRE2_TIM_DIV2 ((uint32_t)0x00002800) /* HCLK divided by 2 for TIM1,8,9,10*/ +#define RCC_PPRE2_TIM_DIV4 ((uint32_t)0x00003000) /* HCLK divided by 4 for TIM1,8,9,10*/ +#define RCC_PPRE2_TIM_DIV8 ((uint32_t)0x00003800) /* HCLK divided by 8 for TIM1,8,9,10*/ + +#define RCC_PPRE2_ADCL_DIV1 ((uint32_t)0x00000000) /* HCLK divided by 1 for ADC*/ +#define RCC_PPRE2_ADCL_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 for ADC*/ +#define RCC_PPRE2_ADCL_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 for ADC*/ +#define RCC_PPRE2_ADCL_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 for ADC*/ +#define RCC_PPRE2_ADCL_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 for ADC*/ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_ADCH_DIV2 ((uint32_t)0x00000000) /* HCLK divided by 2 for ADC*/ +#define RCC_ADCPRE_ADCH_DIV4 ((uint32_t)0x00001000) /* HCLK divided by 4 for ADC*/ +#define RCC_ADCPRE_ADCH_DIV6 ((uint32_t)0x00002000) /* HCLK divided by 6 for ADC*/ +#define RCC_ADCPRE_ADCH_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 for ADC*/ + +#define RCC_ADCPRE_DIV5 ((uint32_t)0x00000000) /* USBHS PLL divided by 5 for ADC */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00000800) /* USBHS PLL divided by 6 for ADC */ +#define RCC_ADCPRE_DIV7 ((uint32_t)0x00001000) /* USBHS PLL divided by 7 for ADC */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x00001800) /* USBHS PLL divided by 8 for ADC */ +#define RCC_ADCPRE_DIV9 ((uint32_t)0x00002000) /* USBHS PLL divided by 9 for ADC */ +#define RCC_ADCPRE_DIV10 ((uint32_t)0x00002800) /* USBHS PLL divided by 10 for ADC */ +#define RCC_ADCPRE_DIV11 ((uint32_t)0x00003000) /* USBHS PLL divided by 11 for ADC */ +#define RCC_ADCPRE_DIV12 ((uint32_t)0x00003800) /* USBHS PLL divided by 12 for ADC */ +#define RCC_ADCPRE_DIV13 ((uint32_t)0x00004000) /* USBHS PLL divided by 13 for ADC */ +#define RCC_ADCPRE_DIV14 ((uint32_t)0x00004800) /* USBHS PLL divided by 14 for ADC */ +#define RCC_ADCPRE_DIV15 ((uint32_t)0x00005000) /* USBHS PLL divided by 15 for ADC */ +#define RCC_ADCPRE_DIV16 ((uint32_t)0x00005800) /* USBHS PLL divided by 16 for ADC */ +#define RCC_ADCPRE_DIV17 ((uint32_t)0x00006000) /* USBHS PLL divided by 17 for ADC */ +#define RCC_ADCPRE_DIV18 ((uint32_t)0x00006800) /* USBHS PLL divided by 18 for ADC */ +#define RCC_ADCPRE_DIV19 ((uint32_t)0x00007000) /* USBHS PLL divided by 19 for ADC */ +#define RCC_ADCPRE_DIV20 ((uint32_t)0x00007800) /* USBHS PLL divided by 20 for ADC */ +#define RCC_ADCPRE_DIV21 ((uint32_t)0x00008000) /* USBHS PLL divided by 21 for ADC */ +#define RCC_ADCPRE_DIV22 ((uint32_t)0x00008800) /* USBHS PLL divided by 22 for ADC */ +#define RCC_ADCPRE_DIV23 ((uint32_t)0x00009000) /* USBHS PLL divided by 23 for ADC */ +#define RCC_ADCPRE_DIV24 ((uint32_t)0x00009800) /* USBHS PLL divided by 24 for ADC */ +#define RCC_ADCPRE_DIV25 ((uint32_t)0x0000A000) /* USBHS PLL divided by 25 for ADC */ +#define RCC_ADCPRE_DIV26 ((uint32_t)0x0000A800) /* USBHS PLL divided by 26 for ADC */ +#define RCC_ADCPRE_DIV27 ((uint32_t)0x0000B000) /* USBHS PLL divided by 27 for ADC */ +#define RCC_ADCPRE_DIV28 ((uint32_t)0x0000B800) /* USBHS PLL divided by 28 for ADC */ +#define RCC_ADCPRE_DIV29 ((uint32_t)0x0000C000) /* USBHS PLL divided by 29 for ADC */ +#define RCC_ADCPRE_DIV30 ((uint32_t)0x0000C800) /* USBHS PLL divided by 30 for ADC */ +#define RCC_ADCPRE_DIV31 ((uint32_t)0x0000D000) /* USBHS PLL divided by 31 for ADC */ +#define RCC_ADCPRE_DIV32 ((uint32_t)0x0000D800) /* USBHS PLL divided by 32 for ADC */ +#define RCC_ADCPRE_DIV33 ((uint32_t)0x0000E000) /* USBHS PLL divided by 33 for ADC */ +#define RCC_ADCPRE_DIV34 ((uint32_t)0x0000E800) /* USBHS PLL divided by 34 for ADC */ +#define RCC_ADCPRE_DIV35 ((uint32_t)0x0000F000) /* USBHS PLL divided by 35 for ADC */ +#define RCC_ADCPRE_DIV36 ((uint32_t)0x0000F800) /* USBHS PLL divided by 36 for ADC */ + +#define RCC_FPRE ((uint32_t)0x00030000) +#define RCC_FPRE_0 ((uint32_t)0x00010000) +#define RCC_FPRE_1 ((uint32_t)0x00020000) + +#define RCC_FPRE_DIV1 ((uint32_t)0x00000000) +#define RCC_FPRE_DIV2 ((uint32_t)0x00010000) +#define RCC_FPRE_DIV4 ((uint32_t)0x00020000) + +#define RCC_RGMIION ((uint32_t)0x00200000) + +#define RCC_PIPEON ((uint32_t)0x00400000) +#define RCC_UTMION ((uint32_t)0x00800000) + +#define RCC_CFGR0_MCO ((uint32_t)0x0F000000) +#define RCC_MCO_0 ((uint32_t)0x01000000) +#define RCC_MCO_1 ((uint32_t)0x02000000) +#define RCC_MCO_2 ((uint32_t)0x04000000) +#define RCC_MCO_3 ((uint32_t)0x08000000) + +#define RCC_CFGR0_MCO_NOCLOCK ((uint32_t)0x00000000) +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) +#define RCC_CFGR0_MCO_PLL_DIV2 ((uint32_t)0x07000000) +#define RCC_CFGR0_MCO_UTMI ((uint32_t)0x08000000) +#define RCC_CFGR0_MCO_USBSS_PLL_DIV2 ((uint32_t)0x09000000) +#define RCC_CFGR0_MCO_ETH_PLL_DIV8 ((uint32_t)0x0A000000) +#define RCC_CFGR0_MCO_SERDES_DIV16 ((uint32_t)0x0B000000) + +#define RCC_ADC_DUTY_SEL ((uint32_t)0x40000000) +#define RCC_ADCSRC ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_PLLCFGR register *******************/ +#define RCC_PLLMUL ((uint32_t)0x0000001F) +#define RCC_PLLMUL_0 ((uint32_t)0x00000001) +#define RCC_PLLMUL_1 ((uint32_t)0x00000002) +#define RCC_PLLMUL_2 ((uint32_t)0x00000004) +#define RCC_PLLMUL_3 ((uint32_t)0x00000008) +#define RCC_PLLMUL_4 ((uint32_t)0x00000010) + +#define RCC_PLLMUL4 ((uint32_t)0x00000000) +#define RCC_PLLMUL6 ((uint32_t)0x00000001) +#define RCC_PLLMUL7 ((uint32_t)0x00000002) +#define RCC_PLLMUL8 ((uint32_t)0x00000003) +#define RCC_PLLMUL8_5 ((uint32_t)0x00000004) +#define RCC_PLLMUL9 ((uint32_t)0x00000005) +#define RCC_PLLMUL9_5 ((uint32_t)0x00000006) +#define RCC_PLLMUL10 ((uint32_t)0x00000007) +#define RCC_PLLMUL10_5 ((uint32_t)0x00000008) +#define RCC_PLLMUL11 ((uint32_t)0x00000009) +#define RCC_PLLMUL11_5 ((uint32_t)0x0000000A) +#define RCC_PLLMUL12 ((uint32_t)0x0000000B) +#define RCC_PLLMUL12_5 ((uint32_t)0x0000000C) +#define RCC_PLLMUL13 ((uint32_t)0x0000000D) +#define RCC_PLLMUL14 ((uint32_t)0x0000000E) +#define RCC_PLLMUL15 ((uint32_t)0x0000000F) +#define RCC_PLLMUL16 ((uint32_t)0x00000010) +#define RCC_PLLMUL17 ((uint32_t)0x00000011) +#define RCC_PLLMUL18 ((uint32_t)0x00000012) +#define RCC_PLLMUL19 ((uint32_t)0x00000013) +#define RCC_PLLMUL20 ((uint32_t)0x00000014) +#define RCC_PLLMUL22 ((uint32_t)0x00000015) +#define RCC_PLLMUL24 ((uint32_t)0x00000016) +#define RCC_PLLMUL26 ((uint32_t)0x00000017) +#define RCC_PLLMUL28 ((uint32_t)0x00000018) +#define RCC_PLLMUL30 ((uint32_t)0x00000019) +#define RCC_PLLMUL32 ((uint32_t)0x0000001A) +#define RCC_PLLMUL34 ((uint32_t)0x0000001B) +#define RCC_PLLMUL36 ((uint32_t)0x0000001C) +#define RCC_PLLMUL38 ((uint32_t)0x0000001D) +#define RCC_PLLMUL40 ((uint32_t)0x0000001E) +#define RCC_PLLMUL59 ((uint32_t)0x0000001F) + +#define RCC_PLLSRC ((uint32_t)0x000000E0) +#define RCC_PLLSRC_0 ((uint32_t)0x00000020) +#define RCC_PLLSRC_2 ((uint32_t)0x00000040) +#define RCC_PLLSRC_4 ((uint32_t)0x00000080) + +#define RCC_PLLSRC_HSI ((uint32_t)0x00000000) +#define RCC_PLLSRC_HSE ((uint32_t)0x00000020) +#define RCC_PLLSRC_USBHS_PLL ((uint32_t)0x00000080) +#define RCC_PLLSRC_ETH_PLL ((uint32_t)0x000000A0) +#define RCC_PLLSRC_USBSS_PLL ((uint32_t)0x000000C0) +#define RCC_PLLSRC_SERDES_PLL ((uint32_t)0x000000E0) + +#define RCC_PLL_SRC_DIV ((uint32_t)0x00003F00) +#define RCC_PLL_SRC_DIV_0 ((uint32_t)0x00000100) +#define RCC_PLL_SRC_DIV_1 ((uint32_t)0x00000200) +#define RCC_PLL_SRC_DIV_2 ((uint32_t)0x00000400) +#define RCC_PLL_SRC_DIV_3 ((uint32_t)0x00000800) +#define RCC_PLL_SRC_DIV_4 ((uint32_t)0x00001000) +#define RCC_PLL_SRC_DIV_5 ((uint32_t)0x00002000) + +#define RCC_PLL_SRC_DIV1 ((uint32_t)0x00000000) +#define RCC_PLL_SRC_DIV2 ((uint32_t)0x00000100) +#define RCC_PLL_SRC_DIV3 ((uint32_t)0x00000200) +#define RCC_PLL_SRC_DIV4 ((uint32_t)0x00000300) +#define RCC_PLL_SRC_DIV5 ((uint32_t)0x00000400) +#define RCC_PLL_SRC_DIV6 ((uint32_t)0x00000500) +#define RCC_PLL_SRC_DIV7 ((uint32_t)0x00000600) +#define RCC_PLL_SRC_DIV8 ((uint32_t)0x00000700) +#define RCC_PLL_SRC_DIV9 ((uint32_t)0x00000800) +#define RCC_PLL_SRC_DIV10 ((uint32_t)0x00000900) +#define RCC_PLL_SRC_DIV11 ((uint32_t)0x00000A00) +#define RCC_PLL_SRC_DIV12 ((uint32_t)0x00000B00) +#define RCC_PLL_SRC_DIV13 ((uint32_t)0x00000C00) +#define RCC_PLL_SRC_DIV14 ((uint32_t)0x00000D00) +#define RCC_PLL_SRC_DIV15 ((uint32_t)0x00000E00) +#define RCC_PLL_SRC_DIV16 ((uint32_t)0x00000F00) +#define RCC_PLL_SRC_DIV17 ((uint32_t)0x00001000) +#define RCC_PLL_SRC_DIV18 ((uint32_t)0x00001100) +#define RCC_PLL_SRC_DIV19 ((uint32_t)0x00001200) +#define RCC_PLL_SRC_DIV20 ((uint32_t)0x00001300) +#define RCC_PLL_SRC_DIV21 ((uint32_t)0x00001400) +#define RCC_PLL_SRC_DIV22 ((uint32_t)0x00001500) +#define RCC_PLL_SRC_DIV23 ((uint32_t)0x00001600) +#define RCC_PLL_SRC_DIV24 ((uint32_t)0x00001700) +#define RCC_PLL_SRC_DIV25 ((uint32_t)0x00001800) +#define RCC_PLL_SRC_DIV26 ((uint32_t)0x00001900) +#define RCC_PLL_SRC_DIV27 ((uint32_t)0x00001A00) +#define RCC_PLL_SRC_DIV28 ((uint32_t)0x00001B00) +#define RCC_PLL_SRC_DIV29 ((uint32_t)0x00001C00) +#define RCC_PLL_SRC_DIV30 ((uint32_t)0x00001D00) +#define RCC_PLL_SRC_DIV31 ((uint32_t)0x00001E00) +#define RCC_PLL_SRC_DIV32 ((uint32_t)0x00001F00) +#define RCC_PLL_SRC_DIV33 ((uint32_t)0x00002000) +#define RCC_PLL_SRC_DIV34 ((uint32_t)0x00002100) +#define RCC_PLL_SRC_DIV35 ((uint32_t)0x00002200) +#define RCC_PLL_SRC_DIV36 ((uint32_t)0x00002300) +#define RCC_PLL_SRC_DIV37 ((uint32_t)0x00002400) +#define RCC_PLL_SRC_DIV38 ((uint32_t)0x00002500) +#define RCC_PLL_SRC_DIV39 ((uint32_t)0x00002600) +#define RCC_PLL_SRC_DIV40 ((uint32_t)0x00002700) +#define RCC_PLL_SRC_DIV41 ((uint32_t)0x00002800) +#define RCC_PLL_SRC_DIV42 ((uint32_t)0x00002900) +#define RCC_PLL_SRC_DIV43 ((uint32_t)0x00002A00) +#define RCC_PLL_SRC_DIV44 ((uint32_t)0x00002B00) +#define RCC_PLL_SRC_DIV45 ((uint32_t)0x00002C00) +#define RCC_PLL_SRC_DIV46 ((uint32_t)0x00002D00) +#define RCC_PLL_SRC_DIV47 ((uint32_t)0x00002E00) +#define RCC_PLL_SRC_DIV48 ((uint32_t)0x00002F00) +#define RCC_PLL_SRC_DIV49 ((uint32_t)0x00003000) +#define RCC_PLL_SRC_DIV50 ((uint32_t)0x00003100) +#define RCC_PLL_SRC_DIV51 ((uint32_t)0x00003200) +#define RCC_PLL_SRC_DIV52 ((uint32_t)0x00003300) +#define RCC_PLL_SRC_DIV53 ((uint32_t)0x00003400) +#define RCC_PLL_SRC_DIV54 ((uint32_t)0x00003500) +#define RCC_PLL_SRC_DIV55 ((uint32_t)0x00003600) +#define RCC_PLL_SRC_DIV56 ((uint32_t)0x00003700) +#define RCC_PLL_SRC_DIV57 ((uint32_t)0x00003800) +#define RCC_PLL_SRC_DIV58 ((uint32_t)0x00003900) +#define RCC_PLL_SRC_DIV59 ((uint32_t)0x00003A00) +#define RCC_PLL_SRC_DIV60 ((uint32_t)0x00003B00) +#define RCC_PLL_SRC_DIV61 ((uint32_t)0x00003C00) +#define RCC_PLL_SRC_DIV62 ((uint32_t)0x00003D00) +#define RCC_PLL_SRC_DIV63 ((uint32_t)0x00003E00) +#define RCC_PLL_SRC_DIV64 ((uint32_t)0x00003F00) + +#define RCC_SYSPLL_SEL ((uint32_t)0x70000000) +#define RCC_SYSPLL_SEL_0 ((uint32_t)0x10000000) +#define RCC_SYSPLL_SEL_1 ((uint32_t)0x20000000) +#define RCC_SYSPLL_SEL_2 ((uint32_t)0x40000000) + +#define RCC_SYSPLL_PLL ((uint32_t)0x00000000) +#define RCC_SYSPLL_USBHS ((uint32_t)0x40000000) +#define RCC_SYSPLL_ETH ((uint32_t)0x50000000) +#define RCC_SYSPLL_SERDES ((uint32_t)0x60000000) +#define RCC_SYSPLL_USBSS ((uint32_t)0x70000000) + +#define RCC_SYSPLL_GATE ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_ETHPLLRDYF ((uint32_t)0x00000020) +#define RCC_SERDESPLLRDYF ((uint32_t)0x00000040) +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_ETHPLLRDYIE ((uint32_t)0x00002000) +#define RCC_SERDESPLLRDYIE ((uint32_t)0x00004000) +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_ETHPLLRDYC ((uint32_t)0x00200000) +#define RCC_SERDESPLLRDYC ((uint32_t)0x00400000) +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_HB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_HSADCRST ((uint32_t)0x00000002) +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_IOPERST ((uint32_t)0x00000040) +#define RCC_IOPFRST ((uint32_t)0x00000080) + +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_TIM8RST ((uint32_t)0x00002000) +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ +#define RCC_I2C4RST ((uint32_t)0x00008000) +#define RCC_SAIRST ((uint32_t)0x00010000) +#define RCC_SDIORST ((uint32_t)0x00040000) +#define RCC_TIM9RST ((uint32_t)0x00080000) +#define RCC_TIM10RST ((uint32_t)0x00100000) +#define RCC_TIM11RST ((uint32_t)0x00200000) +#define RCC_TIM12RST ((uint32_t)0x00400000) +#define RCC_OPCMRST ((uint32_t)0x00800000) +#define RCC_DFSDMRST ((uint32_t)0x02000000) +#define RCC_ECDCRST ((uint32_t)0x04000000) +#define RCC_GPHARST ((uint32_t)0x08000000) +#define RCC_LTDCRST ((uint32_t)0x40000000) +#define RCC_I3CRST ((uint32_t)0x80000000) + +/***************** Bit definition for RCC_HB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_TIM5RST ((uint32_t)0x00000008) /* Timer 5 reset */ +#define RCC_TIM6RST ((uint32_t)0x00000010) /* Timer 6 reset */ +#define RCC_TIM7RST ((uint32_t)0x00000020) /* Timer 7 reset */ +#define RCC_USART6RST ((uint32_t)0x00000040) /* USART 2 reset */ +#define RCC_USART7RST ((uint32_t)0x00000080) /* USART 2 reset */ +#define RCC_USART8RST ((uint32_t)0x00000100) /* USART 2 reset */ +#define RCC_LPTIM1RST ((uint32_t)0x00000200) +#define RCC_LPTIM2RST ((uint32_t)0x00000400) +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_QSPI1RST ((uint32_t)0x00001000) +#define RCC_QSPI2RST ((uint32_t)0x00002000) +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_SPI3RST ((uint32_t)0x00008000) /* SPI 3 reset */ +#define RCC_SPI4RST ((uint32_t)0x00010000) +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ +#define RCC_USART5RST ((uint32_t)0x00100000) /* USART 5 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ +#define RCC_CAN3RST ((uint32_t)0x01000000) +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ +#define RCC_CAN2RST ((uint32_t)0x04000000) /* CAN2 reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_DACRST ((uint32_t)0x20000000) /* DAC reset */ +#define RCC_I2C3RST ((uint32_t)0x40000000) +#define RCC_SWPMIRST ((uint32_t)0x80000000) + +/****************** Bit definition for RCC_HBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_DMA2EN ((uint16_t)0x0002) +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_FMCEN ((uint16_t)0x0100) +#define RCC_RNGEN ((uint16_t)0x0200) +#define RCC_SDMMCEN ((uint16_t)0x0400) +#define RCC_USBHSEN ((uint16_t)0x0800) +#define RCC_USBSSEN ((uint16_t)0x1000) +#define RCC_DVPEN ((uint16_t)0x2000) +#define RCC_ETHEN ((uint16_t)0x4000) + +#define RCC_USBOTGEN ((uint32_t)0x00020000) +#define RCC_UHSIFEN ((uint32_t)0x00040000) +#define RCC_USBPDEN ((uint32_t)0x00080000) +#define RCC_SERDESEN ((uint32_t)0x00100000) +#define RCC_PIOCEN ((uint32_t)0x00400000) + +/****************** Bit definition for RCC_HB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_HSADCEN ((uint32_t)0x00000002) +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_IOPEEN ((uint32_t)0x00000040) +#define RCC_IOPFEN ((uint32_t)0x00000080) + +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_TIM8EN ((uint32_t)0x00002000) +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ +#define RCC_I2C4EN ((uint32_t)0x00008000) + +#define RCC_SAIEN ((uint32_t)0x00010000) +#define RCC_SDIOEN ((uint32_t)0x00040000) +#define RCC_TIM9EN ((uint32_t)0x00080000) +#define RCC_TIM10EN ((uint32_t)0x00100000) +#define RCC_TIM11EN ((uint32_t)0x00200000) +#define RCC_TIM12EN ((uint32_t)0x00400000) +#define RCC_OPCMEN ((uint32_t)0x00800000) + +#define RCC_DFSDMEN ((uint32_t)0x02000000) +#define RCC_ECDCEN ((uint32_t)0x04000000) +#define RCC_GPHAEN ((uint32_t)0x08000000) +#define RCC_LTDCEN ((uint32_t)0x40000000) +#define RCC_I3CEN ((uint32_t)0x80000000) + +/***************** Bit definition for RCC_HB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_TIM5EN ((uint32_t)0x00000008) +#define RCC_TIM6EN ((uint32_t)0x00000010) +#define RCC_TIM7EN ((uint32_t)0x00000020) +#define RCC_USART6EN ((uint32_t)0x00000040) +#define RCC_USART7EN ((uint32_t)0x00000080) +#define RCC_USART8EN ((uint32_t)0x00000100) +#define RCC_LPTIM1EN ((uint32_t)0x00000200) +#define RCC_LPTIM2EN ((uint32_t)0x00000400) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ + +#define RCC_QSPI1EN ((uint32_t)0x00001000) +#define RCC_QSPI2EN ((uint32_t)0x00002000) +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_SPI3EN ((uint32_t)0x00008000) +#define RCC_SPI4EN ((uint32_t)0x00010000) + +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) +#define RCC_USART4EN ((uint32_t)0x00080000) +#define RCC_USART5EN ((uint32_t)0x00100000) +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) +#define RCC_CAN3EN ((uint32_t)0x01000000) /* USB Device clock enable */ +#define RCC_CAN1EN ((uint32_t)0x02000000) +#define RCC_CAN2EN ((uint32_t)0x04000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_DACEN ((uint32_t)0x20000000) +#define RCC_I2C3EN ((uint32_t)0x40000000) +#define RCC_SWPMIEN ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ +#define RCC_CCO ((uint32_t)0x00000008) +#define RCC_ASOE ((uint32_t)0x00000010) +#define RCC_ASOS ((uint32_t)0x00000020) + +#define RCC_RTCSEL ((uint32_t)0x000000C0) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000040) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000080) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x000000C0) + +#define RCC_RTCEN ((uint32_t)0x00000100) /* RTC clock enable */ +#define RCC_RTCCAL ((uint32_t)0x0000FE00) +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LOCKUPRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************* Bit definition for RCC_HBRSTR register ********************/ +#define RCC_DMA1RST ((uint32_t)0x00000001) +#define RCC_DMA2RST ((uint32_t)0x00000002) +#define RCC_FMCRST ((uint32_t)0x00000100) +#define RCC_RNGRST ((uint32_t)0x00000200) +#define RCC_SDMMCRST ((uint32_t)0x00000400) +#define RCC_USBHSRST ((uint32_t)0x00000800) + +#define RCC_USBSSRST ((uint32_t)0x00001000) +#define RCC_DVPRST ((uint32_t)0x00002000) +#define RCC_ETHRST ((uint32_t)0x00004000) + +#define RCC_USBOTGRST ((uint32_t)0x00020000) +#define RCC_UHSIFRST ((uint32_t)0x00040000) +#define RCC_USBPDRST ((uint32_t)0x00080000) +#define RCC_SERDESRST ((uint32_t)0x00100000) +#define RCC_PIOCRST ((uint32_t)0x00400000) + +/******************* Bit definition for RCC_CFGR2 register ********************/ +#define RCC_UHSIFDIV ((uint32_t)0x0000003F) +#define RCC_UHSIFDIV_0 ((uint32_t)0x00000001) +#define RCC_UHSIFDIV_1 ((uint32_t)0x00000002) +#define RCC_UHSIFDIV_2 ((uint32_t)0x00000004) +#define RCC_UHSIFDIV_3 ((uint32_t)0x00000008) +#define RCC_UHSIFDIV_4 ((uint32_t)0x00000010) +#define RCC_UHSIFDIV_5 ((uint32_t)0x00000020) + +#define RCC_UHSIFDIV_DIV1 ((uint32_t)0x00000000) +#define RCC_UHSIFDIV_DIV2 ((uint32_t)0x00000001) +#define RCC_UHSIFDIV_DIV3 ((uint32_t)0x00000002) +#define RCC_UHSIFDIV_DIV4 ((uint32_t)0x00000003) +#define RCC_UHSIFDIV_DIV5 ((uint32_t)0x00000004) +#define RCC_UHSIFDIV_DIV6 ((uint32_t)0x00000005) +#define RCC_UHSIFDIV_DIV7 ((uint32_t)0x00000006) +#define RCC_UHSIFDIV_DIV8 ((uint32_t)0x00000007) +#define RCC_UHSIFDIV_DIV9 ((uint32_t)0x00000008) +#define RCC_UHSIFDIV_DIV10 ((uint32_t)0x00000009) +#define RCC_UHSIFDIV_DIV11 ((uint32_t)0x0000000A) +#define RCC_UHSIFDIV_DIV12 ((uint32_t)0x0000000B) +#define RCC_UHSIFDIV_DIV13 ((uint32_t)0x0000000C) +#define RCC_UHSIFDIV_DIV14 ((uint32_t)0x0000000D) +#define RCC_UHSIFDIV_DIV15 ((uint32_t)0x0000000E) +#define RCC_UHSIFDIV_DIV16 ((uint32_t)0x0000000F) +#define RCC_UHSIFDIV_DIV17 ((uint32_t)0x00000010) +#define RCC_UHSIFDIV_DIV18 ((uint32_t)0x00000011) +#define RCC_UHSIFDIV_DIV19 ((uint32_t)0x00000012) +#define RCC_UHSIFDIV_DIV20 ((uint32_t)0x00000013) +#define RCC_UHSIFDIV_DIV21 ((uint32_t)0x00000014) +#define RCC_UHSIFDIV_DIV22 ((uint32_t)0x00000015) +#define RCC_UHSIFDIV_DIV23 ((uint32_t)0x00000016) +#define RCC_UHSIFDIV_DIV24 ((uint32_t)0x00000017) +#define RCC_UHSIFDIV_DIV25 ((uint32_t)0x00000018) +#define RCC_UHSIFDIV_DIV26 ((uint32_t)0x00000019) +#define RCC_UHSIFDIV_DIV27 ((uint32_t)0x0000001A) +#define RCC_UHSIFDIV_DIV28 ((uint32_t)0x0000001B) +#define RCC_UHSIFDIV_DIV29 ((uint32_t)0x0000001C) +#define RCC_UHSIFDIV_DIV30 ((uint32_t)0x0000001D) +#define RCC_UHSIFDIV_DIV31 ((uint32_t)0x0000001E) +#define RCC_UHSIFDIV_DIV32 ((uint32_t)0x0000001F) +#define RCC_UHSIFDIV_DIV33 ((uint32_t)0x00000020) +#define RCC_UHSIFDIV_DIV34 ((uint32_t)0x00000021) +#define RCC_UHSIFDIV_DIV35 ((uint32_t)0x00000022) +#define RCC_UHSIFDIV_DIV36 ((uint32_t)0x00000023) +#define RCC_UHSIFDIV_DIV37 ((uint32_t)0x00000024) +#define RCC_UHSIFDIV_DIV38 ((uint32_t)0x00000025) +#define RCC_UHSIFDIV_DIV39 ((uint32_t)0x00000026) +#define RCC_UHSIFDIV_DIV40 ((uint32_t)0x00000027) +#define RCC_UHSIFDIV_DIV41 ((uint32_t)0x00000028) +#define RCC_UHSIFDIV_DIV42 ((uint32_t)0x00000029) +#define RCC_UHSIFDIV_DIV43 ((uint32_t)0x0000002A) +#define RCC_UHSIFDIV_DIV44 ((uint32_t)0x0000002B) +#define RCC_UHSIFDIV_DIV45 ((uint32_t)0x0000002C) +#define RCC_UHSIFDIV_DIV46 ((uint32_t)0x0000002D) +#define RCC_UHSIFDIV_DIV47 ((uint32_t)0x0000002E) +#define RCC_UHSIFDIV_DIV48 ((uint32_t)0x0000002F) +#define RCC_UHSIFDIV_DIV49 ((uint32_t)0x00000030) +#define RCC_UHSIFDIV_DIV50 ((uint32_t)0x00000031) +#define RCC_UHSIFDIV_DIV51 ((uint32_t)0x00000032) +#define RCC_UHSIFDIV_DIV52 ((uint32_t)0x00000033) +#define RCC_UHSIFDIV_DIV53 ((uint32_t)0x00000034) +#define RCC_UHSIFDIV_DIV54 ((uint32_t)0x00000035) +#define RCC_UHSIFDIV_DIV55 ((uint32_t)0x00000036) +#define RCC_UHSIFDIV_DIV56 ((uint32_t)0x00000037) +#define RCC_UHSIFDIV_DIV57 ((uint32_t)0x00000038) +#define RCC_UHSIFDIV_DIV58 ((uint32_t)0x00000039) +#define RCC_UHSIFDIV_DIV59 ((uint32_t)0x0000003A) +#define RCC_UHSIFDIV_DIV60 ((uint32_t)0x0000003B) +#define RCC_UHSIFDIV_DIV61 ((uint32_t)0x0000003C) +#define RCC_UHSIFDIV_DIV62 ((uint32_t)0x0000003D) +#define RCC_UHSIFDIV_DIV63 ((uint32_t)0x0000003E) +#define RCC_UHSIFDIV_DIV64 ((uint32_t)0x0000003F) + +#define RCC_UHSIFSRC ((uint32_t)0x000000C0) +#define RCC_UHSIFSRC_0 ((uint32_t)0x00000040) +#define RCC_UHSIFSRC_1 ((uint32_t)0x00000080) + +#define RCC_UHSIFSRC_SYSCLK ((uint32_t)0x00000000) +#define RCC_UHSIFSRC_PLLCLK ((uint32_t)0x00000040) +#define RCC_UHSIFSRC_USBHSPLL ((uint32_t)0x00000080) +#define RCC_UHSIFSRC_ETHPLL ((uint32_t)0x000000C0) + +#define RCC_LTDCDIV ((uint32_t)0x00003F00) +#define RCC_LTDCDIV_0 ((uint32_t)0x00000100) +#define RCC_LTDCDIV_1 ((uint32_t)0x00000200) +#define RCC_LTDCDIV_2 ((uint32_t)0x00000400) +#define RCC_LTDCDIV_3 ((uint32_t)0x00000800) +#define RCC_LTDCDIV_4 ((uint32_t)0x00001000) +#define RCC_LTDCDIV_5 ((uint32_t)0x00002000) + +#define RCC_LTDCDIV_DIV1 ((uint32_t)0x00000000) +#define RCC_LTDCDIV_DIV2 ((uint32_t)0x00000100) +#define RCC_LTDCDIV_DIV3 ((uint32_t)0x00000200) +#define RCC_LTDCDIV_DIV4 ((uint32_t)0x00000300) +#define RCC_LTDCDIV_DIV5 ((uint32_t)0x00000400) +#define RCC_LTDCDIV_DIV6 ((uint32_t)0x00000500) +#define RCC_LTDCDIV_DIV7 ((uint32_t)0x00000600) +#define RCC_LTDCDIV_DIV8 ((uint32_t)0x00000700) +#define RCC_LTDCDIV_DIV9 ((uint32_t)0x00000800) +#define RCC_LTDCDIV_DIV10 ((uint32_t)0x00000900) +#define RCC_LTDCDIV_DIV11 ((uint32_t)0x00000A00) +#define RCC_LTDCDIV_DIV12 ((uint32_t)0x00000B00) +#define RCC_LTDCDIV_DIV13 ((uint32_t)0x00000C00) +#define RCC_LTDCDIV_DIV14 ((uint32_t)0x00000D00) +#define RCC_LTDCDIV_DIV15 ((uint32_t)0x00000E00) +#define RCC_LTDCDIV_DIV16 ((uint32_t)0x00000F00) +#define RCC_LTDCDIV_DIV17 ((uint32_t)0x00001000) +#define RCC_LTDCDIV_DIV18 ((uint32_t)0x00001100) +#define RCC_LTDCDIV_DIV19 ((uint32_t)0x00001200) +#define RCC_LTDCDIV_DIV20 ((uint32_t)0x00001300) +#define RCC_LTDCDIV_DIV21 ((uint32_t)0x00001400) +#define RCC_LTDCDIV_DIV22 ((uint32_t)0x00001500) +#define RCC_LTDCDIV_DIV23 ((uint32_t)0x00001600) +#define RCC_LTDCDIV_DIV24 ((uint32_t)0x00001700) +#define RCC_LTDCDIV_DIV25 ((uint32_t)0x00001800) +#define RCC_LTDCDIV_DIV26 ((uint32_t)0x00001900) +#define RCC_LTDCDIV_DIV27 ((uint32_t)0x00001A00) +#define RCC_LTDCDIV_DIV28 ((uint32_t)0x00001B00) +#define RCC_LTDCDIV_DIV29 ((uint32_t)0x00001C00) +#define RCC_LTDCDIV_DIV30 ((uint32_t)0x00001D00) +#define RCC_LTDCDIV_DIV31 ((uint32_t)0x00001E00) +#define RCC_LTDCDIV_DIV32 ((uint32_t)0x00001F00) +#define RCC_LTDCDIV_DIV33 ((uint32_t)0x00002000) +#define RCC_LTDCDIV_DIV34 ((uint32_t)0x00002100) +#define RCC_LTDCDIV_DIV35 ((uint32_t)0x00002200) +#define RCC_LTDCDIV_DIV36 ((uint32_t)0x00002300) +#define RCC_LTDCDIV_DIV37 ((uint32_t)0x00002400) +#define RCC_LTDCDIV_DIV38 ((uint32_t)0x00002500) +#define RCC_LTDCDIV_DIV39 ((uint32_t)0x00002600) +#define RCC_LTDCDIV_DIV40 ((uint32_t)0x00002700) +#define RCC_LTDCDIV_DIV41 ((uint32_t)0x00002800) +#define RCC_LTDCDIV_DIV42 ((uint32_t)0x00002900) +#define RCC_LTDCDIV_DIV43 ((uint32_t)0x00002A00) +#define RCC_LTDCDIV_DIV44 ((uint32_t)0x00002B00) +#define RCC_LTDCDIV_DIV45 ((uint32_t)0x00002C00) +#define RCC_LTDCDIV_DIV46 ((uint32_t)0x00002D00) +#define RCC_LTDCDIV_DIV47 ((uint32_t)0x00002E00) +#define RCC_LTDCDIV_DIV48 ((uint32_t)0x00002F00) +#define RCC_LTDCDIV_DIV49 ((uint32_t)0x00003000) +#define RCC_LTDCDIV_DIV50 ((uint32_t)0x00003100) +#define RCC_LTDCDIV_DIV51 ((uint32_t)0x00003200) +#define RCC_LTDCDIV_DIV52 ((uint32_t)0x00003300) +#define RCC_LTDCDIV_DIV53 ((uint32_t)0x00003400) +#define RCC_LTDCDIV_DIV54 ((uint32_t)0x00003500) +#define RCC_LTDCDIV_DIV55 ((uint32_t)0x00003600) +#define RCC_LTDCDIV_DIV56 ((uint32_t)0x00003700) +#define RCC_LTDCDIV_DIV57 ((uint32_t)0x00003800) +#define RCC_LTDCDIV_DIV58 ((uint32_t)0x00003900) +#define RCC_LTDCDIV_DIV59 ((uint32_t)0x00003A00) +#define RCC_LTDCDIV_DIV60 ((uint32_t)0x00003B00) +#define RCC_LTDCDIV_DIV61 ((uint32_t)0x00003C00) +#define RCC_LTDCDIV_DIV62 ((uint32_t)0x00003D00) +#define RCC_LTDCDIV_DIV63 ((uint32_t)0x00003E00) +#define RCC_LTDCDIV_DIV64 ((uint32_t)0x00003F00) + +#define RCC_LTDCSRC ((uint32_t)0x0000C000) +#define RCC_LTDCSRC_0 ((uint32_t)0x00004000) +#define RCC_LTDCSRC_1 ((uint32_t)0x00008000) + +#define RCC_LTDCSRC_PLLCLK ((uint32_t)0x00000000) +#define RCC_LTDCSRC_SERDESPLL ((uint32_t)0x00004000) +#define RCC_LTDCSRC_ETHPLL ((uint32_t)0x00008000) +#define RCC_LTDCSRC_USBHSPLL ((uint32_t)0x0000C000) + +#define RCC_USBFSDIV ((uint32_t)0x000F0000) +#define RCC_USBFSDIV_0 ((uint32_t)0x00010000) +#define RCC_USBFSDIV_1 ((uint32_t)0x00020000) +#define RCC_USBFSDIV_2 ((uint32_t)0x00040000) +#define RCC_USBFSDIV_3 ((uint32_t)0x00080000) + +#define RCC_USBFSDIV_DIV1 ((uint32_t)0x00000000) +#define RCC_USBFSDIV_DIV2 ((uint32_t)0x00010000) +#define RCC_USBFSDIV_DIV3 ((uint32_t)0x00020000) +#define RCC_USBFSDIV_DIV4 ((uint32_t)0x00030000) +#define RCC_USBFSDIV_DIV5 ((uint32_t)0x00040000) +#define RCC_USBFSDIV_DIV6 ((uint32_t)0x00050000) +#define RCC_USBFSDIV_DIV8 ((uint32_t)0x00060000) +#define RCC_USBFSDIV_DIV10 ((uint32_t)0x00070000) +#define RCC_USBFSDIV_DIV1_5 ((uint32_t)0x00080000) +#define RCC_USBFSDIV_DIV2_5 ((uint32_t)0x00090000) +#define RCC_USBFSDIV_DIV3_5 ((uint32_t)0x000A0000) +#define RCC_USBFSDIV_DIV4_5 ((uint32_t)0x000B0000) +#define RCC_USBFSDIV_DIV5_5 ((uint32_t)0x000C0000) +#define RCC_USBFSDIV_DIV6_5 ((uint32_t)0x000D0000) +#define RCC_USBFSDIV_DIV7_5 ((uint32_t)0x000E0000) +#define RCC_USBFSDIV_DIV9_5 ((uint32_t)0x000F0000) + +#define RCC_USBFSSRC ((uint32_t)0x00100000) + +#define RCC_USBFSSRC_PLLCLK ((uint32_t)0x00000000) +#define RCC_USBFSSRC_USBHSPLL ((uint32_t)0x00100000) + +#define RCC_RNGSRC ((uint32_t)0x00800000) + +#define RCC_RNGSRC_SYSCLK ((uint32_t)0x00000000) +#define RCC_RNGSRC_PLLCLK ((uint32_t)0x00800000) + +#define RCC_I2S2SRC ((uint32_t)0x01000000) + +#define RCC_I2S2SRC_SYSCLK ((uint32_t)0x00000000) +#define RCC_I2S2SRC_PLLCLK ((uint32_t)0x01000000) + +#define RCC_I2S3SRC ((uint32_t)0x02000000) + +#define RCC_I2S3SRC_SYSCLK ((uint32_t)0x00000000) +#define RCC_I2S3SRC_PLLCLK ((uint32_t)0x02000000) + +#define RCC_HSADCSRC ((uint32_t)0x30000000) +#define RCC_HSADCSRC_0 ((uint32_t)0x10000000) +#define RCC_HSADCSRC_1 ((uint32_t)0x20000000) + +#define RCC_HSADCSRC_SYSCLK ((uint32_t)0x00000000) +#define RCC_HSADCSRC_PLLCLK ((uint32_t)0x10000000) +#define RCC_HSADCSRC_USBHSPLL ((uint32_t)0x20000000) +#define RCC_HSADCSRC_ETHPLL ((uint32_t)0x30000000) + +#define RCC_ETH1GSRC ((uint32_t)0xC0000000) +#define RCC_ETH1GSRC_0 ((uint32_t)0x40000000) +#define RCC_ETH1GSRC_1 ((uint32_t)0x80000000) + +#define RCC_ETH1GSRC_PLLCLK ((uint32_t)0x00000000) +#define RCC_ETH1GSRC_USBSSPLL ((uint32_t)0x40000000) +#define RCC_ETH1GSRC_ETHPLL_DIV4 ((uint32_t)0x80000000) +#define RCC_ETH1GSRC_SERDESPLL_DIV8 ((uint32_t)0xC0000000) + +/******************* Bit definition for RCC_PLLCFGR2 register ********************/ +#define RCC_USBHSPLLSRC ((uint32_t)0x00000003) +#define RCC_USBHSPLLSRC_0 ((uint32_t)0x00000001) +#define RCC_USBHSPLLSRC_1 ((uint32_t)0x00000002) + +#define RCC_USBHSPLLSRC_HSE ((uint32_t)0x00000000) +#define RCC_USBHSPLLSRC_HSI ((uint32_t)0x00000001) +#define RCC_USBHSPLLSRC_ETHCLK_20M ((uint32_t)0x00000002) +#define RCC_USBHSPLLSRC_PLLCLK ((uint32_t)0x00000003) + +#define RCC_USBHSPLL_REFSEL ((uint32_t)0x0000000C) +#define RCC_USBHSPLL_REFSEL_0 ((uint32_t)0x00000004) +#define RCC_USBHSPLL_REFSEL_1 ((uint32_t)0x00000008) + +#define RCC_USBHSPLL_REFSEL_25MHZ ((uint32_t)0x00000000) +#define RCC_USBHSPLL_REFSEL_20MHZ ((uint32_t)0x00000004) +#define RCC_USBHSPLL_REFSEL_24MHZ ((uint32_t)0x00000008) +#define RCC_USBHSPLL_REFSEL_32MHZ ((uint32_t)0x0000000C) + +#define RCC_USBSSPLL_REFSEL ((uint32_t)0x00000070) +#define RCC_USBSSPLL_REFSEL_0 ((uint32_t)0x00000010) +#define RCC_USBSSPLL_REFSEL_1 ((uint32_t)0x00000020) +#define RCC_USBSSPLL_REFSEL_2 ((uint32_t)0x00000030) + +#define RCC_USBSSPLL_REFSEL_20MHz ((uint32_t)0x00000000) +#define RCC_USBSSPLL_REFSEL_24MHz ((uint32_t)0x00000010) +#define RCC_USBSSPLL_REFSEL_25MHz ((uint32_t)0x00000020) +#define RCC_USBSSPLL_REFSEL_30MHz ((uint32_t)0x00000030) +#define RCC_USBSSPLL_REFSEL_32MHz ((uint32_t)0x00000040) +#define RCC_USBSSPLL_REFSEL_40MHz ((uint32_t)0x00000050) +#define RCC_USBSSPLL_REFSEL_60MHz ((uint32_t)0x00000060) +#define RCC_USBSSPLL_REFSEL_80MHz ((uint32_t)0x00000070) + +#define RCC_USBHSPLL_IN_DIV ((uint32_t)0x00001F00) +#define RCC_USBHSPLL_IN_DIV_0 ((uint32_t)0x00000100) +#define RCC_USBHSPLL_IN_DIV_1 ((uint32_t)0x00000200) +#define RCC_USBHSPLL_IN_DIV_2 ((uint32_t)0x00000400) +#define RCC_USBHSPLL_IN_DIV_3 ((uint32_t)0x00000800) +#define RCC_USBHSPLL_IN_DIV_4 ((uint32_t)0x00001000) + +#define RCC_USBHSPLL_IN_DIV1 ((uint32_t)0x00000000) +#define RCC_USBHSPLL_IN_DIV2 ((uint32_t)0x00000100) +#define RCC_USBHSPLL_IN_DIV3 ((uint32_t)0x00000200) +#define RCC_USBHSPLL_IN_DIV4 ((uint32_t)0x00000300) +#define RCC_USBHSPLL_IN_DIV5 ((uint32_t)0x00000400) +#define RCC_USBHSPLL_IN_DIV6 ((uint32_t)0x00000500) +#define RCC_USBHSPLL_IN_DIV7 ((uint32_t)0x00000600) +#define RCC_USBHSPLL_IN_DIV8 ((uint32_t)0x00000700) +#define RCC_USBHSPLL_IN_DIV9 ((uint32_t)0x00000800) +#define RCC_USBHSPLL_IN_DIV10 ((uint32_t)0x00000900) +#define RCC_USBHSPLL_IN_DIV11 ((uint32_t)0x00000A00) +#define RCC_USBHSPLL_IN_DIV12 ((uint32_t)0x00000B00) +#define RCC_USBHSPLL_IN_DIV13 ((uint32_t)0x00000C00) +#define RCC_USBHSPLL_IN_DIV14 ((uint32_t)0x00000D00) +#define RCC_USBHSPLL_IN_DIV15 ((uint32_t)0x00000E00) +#define RCC_USBHSPLL_IN_DIV16 ((uint32_t)0x00000F00) +#define RCC_USBHSPLL_IN_DIV17 ((uint32_t)0x00001000) +#define RCC_USBHSPLL_IN_DIV18 ((uint32_t)0x00001100) +#define RCC_USBHSPLL_IN_DIV19 ((uint32_t)0x00001200) +#define RCC_USBHSPLL_IN_DIV20 ((uint32_t)0x00001300) +#define RCC_USBHSPLL_IN_DIV21 ((uint32_t)0x00001400) +#define RCC_USBHSPLL_IN_DIV22 ((uint32_t)0x00001500) +#define RCC_USBHSPLL_IN_DIV23 ((uint32_t)0x00001600) +#define RCC_USBHSPLL_IN_DIV24 ((uint32_t)0x00001700) +#define RCC_USBHSPLL_IN_DIV25 ((uint32_t)0x00001800) +#define RCC_USBHSPLL_IN_DIV26 ((uint32_t)0x00001900) +#define RCC_USBHSPLL_IN_DIV27 ((uint32_t)0x00001A00) +#define RCC_USBHSPLL_IN_DIV28 ((uint32_t)0x00001B00) +#define RCC_USBHSPLL_IN_DIV29 ((uint32_t)0x00001C00) +#define RCC_USBHSPLL_IN_DIV30 ((uint32_t)0x00001D00) +#define RCC_USBHSPLL_IN_DIV31 ((uint32_t)0x00001E00) +#define RCC_USBHSPLL_IN_DIV32 ((uint32_t)0x00001F00) + +#define RCC_SERDESPLL_MUL ((uint32_t)0x000F0000) +#define RCC_SERDESPLL_MUL_0 ((uint32_t)0x00010000) +#define RCC_SERDESPLL_MUL_1 ((uint32_t)0x00020000) +#define RCC_SERDESPLL_MUL_2 ((uint32_t)0x00040000) +#define RCC_SERDESPLL_MUL_3 ((uint32_t)0x00080000) + +#define RCC_SERDESPLL_MUL25 ((uint32_t)0x00000000) +#define RCC_SERDESPLL_MUL28 ((uint32_t)0x00010000) +#define RCC_SERDESPLL_MUL30 ((uint32_t)0x00020000) +#define RCC_SERDESPLL_MUL32 ((uint32_t)0x00030000) +#define RCC_SERDESPLL_MUL35 ((uint32_t)0x00040000) +#define RCC_SERDESPLL_MUL38 ((uint32_t)0x00050000) +#define RCC_SERDESPLL_MUL40 ((uint32_t)0x00060000) +#define RCC_SERDESPLL_MUL45 ((uint32_t)0x00070000) +#define RCC_SERDESPLL_MUL50 ((uint32_t)0x00080000) +#define RCC_SERDESPLL_MUL56 ((uint32_t)0x00090000) +#define RCC_SERDESPLL_MUL60 ((uint32_t)0x000A0000) +#define RCC_SERDESPLL_MUL64 ((uint32_t)0x000B0000) +#define RCC_SERDESPLL_MUL70 ((uint32_t)0x000C0000) +#define RCC_SERDESPLL_MUL76 ((uint32_t)0x000D0000) +#define RCC_SERDESPLL_MUL80 ((uint32_t)0x000E0000) +#define RCC_SERDESPLL_MUL90 ((uint32_t)0x000F0000) + +/******************************************************************************/ +/* RNG */ +/******************************************************************************/ +/******************** Bit definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN ((uint32_t)0x00000004) +#define RNG_CR_IE ((uint32_t)0x00000008) + +/******************** Bit definition for RNG_SR register *******************/ +#define RNG_SR_DRDY ((uint32_t)0x00000001) +#define RNG_SR_CECS ((uint32_t)0x00000002) +#define RNG_SR_SECS ((uint32_t)0x00000004) +#define RNG_SR_CEIS ((uint32_t)0x00000020) +#define RNG_SR_SEIS ((uint32_t)0x00000040) + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCRH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PSCRL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/****************** Bit definition for SPI_HSCR register *******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) +#define SPI_HSCR_HSRXEN2 ((uint16_t)0x0004) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CAPOV ((uint16_t)0x4000) +#define TIM_CAPLVL ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************* Bit definition for TIM_AUX register *******************/ +#define TIM_AUX_CAPCH2_ED ((uint16_t)0x0001) +#define TIM_AUX_CAPCH3_ED ((uint16_t)0x0002) +#define TIM_AUX_CAPCH4_ED ((uint16_t)0x0004) + +#define TIM_AUX_BK_SEL ((uint16_t)0x0038) +#define TIM_AUX_BK_SEL_0 ((uint16_t)0x0008) +#define TIM_AUX_BK_SEL_1 ((uint16_t)0x0010) +#define TIM_AUX_BK_SEL_2 ((uint16_t)0x0020) + +#define TIM_AUX_DT_MODE ((uint16_t)0x0040) +#define TIM_AUX_DTN_MODE ((uint16_t)0x0080) + +#define TIM_AUX_DT_VLU2 ((uint16_t)0xFF00) + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ +#define USART_STATR_RX_BUSY ((uint16_t)0x0400) +#define USART_STATR_MS_ERR ((uint16_t)0x0800) +#define USART_STATR_USART_WKUP ((uint16_t)0x8000) + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +#define USART_CTLR1_M_EXT ((uint16_t)0xC000) +#define USART_CTLR1_M_EXT_0 ((uint16_t)0x4000) +#define USART_CTLR1_M_EXT_1 ((uint16_t)0x8000) + +#define USART_CTLR1_M_EXT5 ((uint16_t)0xC000) +#define USART_CTLR1_M_EXT6 ((uint16_t)0x8000) +#define USART_CTLR1_M_EXT7 ((uint16_t)0x4000) + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_LPWKUP_EN ((uint16_t)0x0800) +#define USART_CTLR3_LPWKUP_CK_SRC ((uint16_t)0x1000) +#define USART_CTLR3_LPWKUP_DLY_CFG ((uint16_t)0xE000) + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/****************** Bit definition for USART_CTLR4 register ******************/ +#define USART_CTLR4_MS_ERRIE ((uint16_t)0x0002) +#define USART_CTLR4_CHECK_SEL ((uint16_t)0x000C) +#define USART_CTLR4_CHECK_MARKENABLE ((uint16_t)0x0008) +#define USART_CTLR4_CHECK_APACEENABLE ((uint16_t)0x000C) + +/******************************************************************************/ +/* OPA */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CTLR1 register ********************/ +#define OPA_CTLR1_EN1 ((uint16_t)0x0001) + +#define OPA_CTLR1_MODE1 ((uint16_t)0x0006) +#define OPA_CTLR1_MODE1_0 ((uint16_t)0x0002) +#define OPA_CTLR1_MODE1_1 ((uint16_t)0x0004) + +#define OPA_CTLR1_PSEL1 ((uint16_t)0x0008) + +#define OPA_CTLR1_NSEL1 ((uint16_t)0x0070) +#define OPA_CTLR1_NSEL1_0 ((uint16_t)0x0010) +#define OPA_CTLR1_NSEL1_1 ((uint16_t)0x0020) +#define OPA_CTLR1_NSEL1_2 ((uint16_t)0x0030) + +#define OPA_CTLR1_FBEN1 ((uint16_t)0x0100) +#define OPA_CTLR1_PGADIF1 ((uint16_t)0x0200) +#define OPA_CTLR1_HS1 ((uint16_t)0x0400) + +/******************* Bit definition for OPA_CTLR2 register ********************/ +#define OPA_CTLR2_EN2 ((uint16_t)0x0001) + +#define OPA_CTLR2_MODE2 ((uint16_t)0x0006) +#define OPA_CTLR2_MODE2_0 ((uint16_t)0x0002) +#define OPA_CTLR2_MODE2_1 ((uint16_t)0x0004) + +#define OPA_CTLR2_PSEL2 ((uint16_t)0x0008) + +#define OPA_CTLR2_NSEL2 ((uint16_t)0x0070) +#define OPA_CTLR2_NSEL2_0 ((uint16_t)0x0010) +#define OPA_CTLR2_NSEL2_1 ((uint16_t)0x0020) +#define OPA_CTLR2_NSEL2_2 ((uint16_t)0x0030) + +#define OPA_CTLR2_FBEN2 ((uint16_t)0x0100) +#define OPA_CTLR2_PGADIF2 ((uint16_t)0x0200) +#define OPA_CTLR2_HS2 ((uint16_t)0x0400) + +/******************* Bit definition for OPA_CTLR3 register ********************/ +#define OPA_CTLR3_EN3 ((uint16_t)0x0001) + +#define OPA_CTLR3_MODE3 ((uint16_t)0x0006) +#define OPA_CTLR3_MODE3_0 ((uint16_t)0x0002) +#define OPA_CTLR3_MODE3_1 ((uint16_t)0x0004) + +#define OPA_CTLR3_PSEL3 ((uint16_t)0x0008) + +#define OPA_CTLR3_NSEL3 ((uint16_t)0x0070) +#define OPA_CTLR3_NSEL3_0 ((uint16_t)0x0010) +#define OPA_CTLR3_NSEL3_1 ((uint16_t)0x0020) +#define OPA_CTLR3_NSEL3_2 ((uint16_t)0x0030) + +#define OPA_CTLR3_FBEN3 ((uint16_t)0x0100) +#define OPA_CTLR3_PGADIF3 ((uint16_t)0x0200) +#define OPA_CTLR3_HS3 ((uint16_t)0x0400) + +/******************* Bit definition for CMP_CTLR register ********************/ +#define OPA_CMP_CTLR_PSEL ((uint32_t)0x00000003) +#define OPA_CMP_CTLR_PSEL_0 ((uint32_t)0x00000001) +#define OPA_CMP_CTLR_PSEL_1 ((uint32_t)0x00000002) + +#define OPA_CMP_CTLR_NSEL ((uint32_t)0x0000000C) +#define OPA_CMP_CTLR_NSEL_0 ((uint32_t)0x00000004) +#define OPA_CMP_CTLR_NSEL_1 ((uint32_t)0x00000008) + +#define OPA_CMP_CTLR_MODE ((uint32_t)0x000000F0) +#define OPA_CMP_CTLR_MODE_0 ((uint32_t)0x00000010) +#define OPA_CMP_CTLR_MODE_1 ((uint32_t)0x00000020) +#define OPA_CMP_CTLR_MODE_2 ((uint32_t)0x00000040) +#define OPA_CMP_CTLR_MODE_3 ((uint32_t)0x00000080) + +#define OPA_CMP_CTLR_EN ((uint32_t)0x00000100) + +#define OPA_CMP_CTLR_HYPSEL ((uint32_t)0x00000600) +#define OPA_CMP_CTLR_HYPSEL_0 ((uint32_t)0x00000200) +#define OPA_CMP_CTLR_HYPSEL_1 ((uint32_t)0x00000400) + +#define OPA_CMP_CTLR_VREF ((uint32_t)0x00001800) +#define OPA_CMP_CTLR_VREF_0 ((uint32_t)0x00000800) +#define OPA_CMP_CTLR_VREF_1 ((uint32_t)0x00001000) + +#define OPA_CMP_CTLR_FILT_EN ((uint32_t)0x00002000) + +#define OPA_CMP_CTLR_FILT_CFG ((uint32_t)0x01FF0000) +#define OPA_CMP_CTLR_FILT_BASE ((uint32_t)0x70000000) + +/******************* Bit definition for CMP_STATR register ********************/ +#define OPA_CMP_STATR_OUTFILT ((uint8_t)0x01) + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 // 00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 // 01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 // 10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_ROW_NUM register ********************/ +#define RB_DVP_ROW_NUM ((uint16_t)0xFFFF) + +/******************* Bit definition for DVP_COL_NUM register ********************/ +#define RB_DVP_COL_NUM ((uint16_t)0xFFFF) + +/******************* Bit definition for DVP_DMA_BUF0 register ********************/ +#define RB_DVP_DMA_BUF0 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for DVP_DMA_BUF1 register ********************/ +#define RB_DVP_DMA_BUF1 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + +/******************* Bit definition for DVP_ROW_CNT register ********************/ +#define RB_DVP_ROW_CNT ((uint16_t)0xFF) + +/******************* Bit definition for DVP_HOFFCNT register ********************/ +#define RB_DVP_HOFFCNT ((uint16_t)0xFF) + +/******************* Bit definition for DVP_VST register ********************/ +#define RB_DVP_VST ((uint16_t)0xFF) + +/******************* Bit definition for DVP_CAPCNT register ********************/ +#define RB_DVP_CAPCNT ((uint16_t)0xFF) + +/******************* Bit definition for DVP_VLINE register ********************/ +#define RB_DVP_VLINE ((uint16_t)0xFF) + +/******************* Bit definition for DVP_DR register ********************/ +#define RB_DVP_DR ((uint16_t)0xFF) + +/******************************************************************************/ +/* TKEY */ +/******************************************************************************/ + +/******************* Bit definition for TKEY_CHARGE1 register *******************/ +#define TKEY_CHARGE1_TKCG10 ((uint32_t)0x0007) +#define TKEY_CHARGE1_TKCG10_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG10_7C5 ((uint32_t)0x0001) +#define TKEY_CHARGE1_TKCG10_13C5 ((uint32_t)0x0002) +#define TKEY_CHARGE1_TKCG10_28C5 ((uint32_t)0x0003) +#define TKEY_CHARGE1_TKCG10_41C5 ((uint32_t)0x0004) +#define TKEY_CHARGE1_TKCG10_55C5 ((uint32_t)0x0005) +#define TKEY_CHARGE1_TKCG10_71C5 ((uint32_t)0x0006) +#define TKEY_CHARGE1_TKCG10_239C5 ((uint32_t)0x0007) + +#define TKEY_CHARGE1_TKCG11 ((uint32_t)0x0038) +#define TKEY_CHARGE1_TKCG11_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG11_7C5 ((uint32_t)0x0008) +#define TKEY_CHARGE1_TKCG11_13C5 ((uint32_t)0x0010) +#define TKEY_CHARGE1_TKCG11_28C5 ((uint32_t)0x0018) +#define TKEY_CHARGE1_TKCG11_41C5 ((uint32_t)0x0020) +#define TKEY_CHARGE1_TKCG11_55C5 ((uint32_t)0x0028) +#define TKEY_CHARGE1_TKCG11_71C5 ((uint32_t)0x0030) +#define TKEY_CHARGE1_TKCG11_239C5 ((uint32_t)0x0038) + +#define TKEY_CHARGE1_TKCG12 ((uint32_t)0x01C0) +#define TKEY_CHARGE1_TKCG12_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG12_7C5 ((uint32_t)0x0040) +#define TKEY_CHARGE1_TKCG12_13C5 ((uint32_t)0x0080) +#define TKEY_CHARGE1_TKCG12_28C5 ((uint32_t)0x00C0) +#define TKEY_CHARGE1_TKCG12_41C5 ((uint32_t)0x0100) +#define TKEY_CHARGE1_TKCG12_55C5 ((uint32_t)0x0140) +#define TKEY_CHARGE1_TKCG12_71C5 ((uint32_t)0x0180) +#define TKEY_CHARGE1_TKCG12_239C5 ((uint32_t)0x01C0) + +#define TKEY_CHARGE1_TKCG13 ((uint32_t)0x0E00) +#define TKEY_CHARGE1_TKCG13_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG13_7C5 ((uint32_t)0x0200) +#define TKEY_CHARGE1_TKCG13_13C5 ((uint32_t)0x0400) +#define TKEY_CHARGE1_TKCG13_28C5 ((uint32_t)0x0600) +#define TKEY_CHARGE1_TKCG13_41C5 ((uint32_t)0x0800) +#define TKEY_CHARGE1_TKCG13_55C5 ((uint32_t)0x0A00) +#define TKEY_CHARGE1_TKCG13_71C5 ((uint32_t)0x0C00) +#define TKEY_CHARGE1_TKCG13_239C5 ((uint32_t)0x0E00) + +#define TKEY_CHARGE1_TKCG14 ((uint32_t)0x7000) +#define TKEY_CHARGE1_TKCG15 ((uint32_t)0x38000) + +/******************************************************************************/ +/* SDMMC */ +/******************************************************************************/ +/******************* Bit definition for SDMMC_ARGUMENT register *******************/ +#define SDMMC_ARGUMENT ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_CMD_SET register *******************/ +#define SDMMC_CMDIDX_MASK ((uint16_t)0x003F) +#define SDMMC_RPTY_MASK ((uint16_t)0x0300) +#define SDMMC_CKCRC ((uint16_t)0x0400) +#define SDMMC_CKIDX ((uint16_t)0x0800) + +/******************* Bit definition for SDMMC_RESPONSE0 register *******************/ +#define SDMMC_RESPONSE0 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_RESPONSE1 register *******************/ +#define SDMMC_RESPONSE1 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_RESPONSE2 register *******************/ +#define SDMMC_RESPONSE2 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_RESPONSE3 register *******************/ +#define SDMMC_RESPONSE3 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_WRITE_CONT register *******************/ +#define SDMMC_WRITE_CONT ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_CONTROL register *******************/ +#define SDMMC_LW_MASK ((uint16_t)0x0003) +#define SDMMC_LW_MASK_0 ((uint16_t)0x0001) +#define SDMMC_LW_MASK_1 ((uint16_t)0x0002) + +#define SDMMC_ALL_CLR ((uint16_t)0x0004) +#define SDMMC_DMAEN ((uint16_t)0x0008) +#define SDMMC_RST_LGC ((uint16_t)0x0010) +#define SDMMC_NEGSMP ((uint16_t)0x0020) +#define SDMMC_SLV_MODE ((uint16_t)0x0100) +#define SDMMC_SLV_FORCE_ERR ((uint16_t)000200) + +/******************* Bit definition for SDMMC_TIMEOUT register *******************/ +#define SDMMC_TOCNT_MASK ((uint8_t)0x0F) + +/******************* Bit definition for SDMMC_STATUS register *******************/ +#define SDMMC_MASK_BLOCK_NUM ((uint16_t)0xFFFF) +#define SDMMC_CMDSTA ((uint32_t)0x00010000) +#define SDMMC_DAT0STA ((uint32_t)0x00020000) + +/******************* Bit definition for SDMMC_INT_FG register *******************/ +#define SDMMC_IF_RE_TMOUT ((uint16_t)0x0001) +#define SDMMC_IF_RECRC_WR ((uint16_t)0x0002) +#define SDMMC_IF_REIDX_ER ((uint16_t)0x0004) +#define SDMMC_IF_CMDDONE ((uint16_t)0x0008) +#define SDMMC_IF_DATTMO ((uint16_t)0x0010) +#define SDMMC_IF_TRANERR ((uint16_t)0x0020) +#define SDMMC_IF_TRANDONE ((uint16_t)0x0040) +#define SDMMC_IF_BKGAP ((uint16_t)0x0080) +#define SDMMC_IF_FIFO_OV ((uint16_t)0x0100) +#define SDMMC_IF_SDIOINT ((uint16_t)0x0200) +#define SDMMC_SIF_SLV_BUF_RELEAS ((uint16_t)0x0400) + +/******************* Bit definition for SDMMC_INT_EN register *******************/ +#define SDMMC_IE_RE_TMOUT ((uint16_t)0x0001) +#define SDMMC_IE_RECRC_WR ((uint16_t)0x0002) +#define SDMMC_IE_REIDX_ER ((uint16_t)0x0004) +#define SDMMC_IE_CMDDONE ((uint16_t)0x0008) +#define SDMMC_IE_DATTMO ((uint16_t)0x0010) +#define SDMMC_IE_TRANERR ((uint16_t)0x0020) +#define SDMMC_IE_TRANDONE ((uint16_t)0x0040) +#define SDMMC_IE_FIFO_OV ((uint16_t)0x0080) +#define SDMMC_IE_SDIOINT ((uint16_t)0x0100) + +/******************* Bit definition for SDMMC_DMA_BEG1 register *******************/ +#define SDMMC_DMAAD1_MASK ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_BLOCK_CFG register *******************/ +#define SDMMC_BKNUM_MASK ((uint32_t)0x0000FFFF) +#define SDMMC_BKSIZE_MASK ((uint32_t)0x0FFF0000) + +/******************* Bit definition for SDMMC_TRAN_MODE register *******************/ +#define SDMMC_DMA_DIR ((uint32_t)0x00000001) +#define SDMMC_GAP_STOP ((uint32_t)0x00000002) +#define SDMMC_MODE_BOOT ((uint32_t)0x00000004) +#define SDMMC_AUTOGAPSTOP ((uint32_t)0x00000010) + +#define SDMMC_DMATN_CNT ((uint32_t)0x00007F00) + +#define SDMMC_DULEDMA_EN ((uint32_t)0x00010000) +#define SDMMC_DDR_MODE ((uint32_t)0x00020000) +#define SDMMC_CARE_NEG ((uint32_t)0x00040000) + +#define SDMMC_SW ((uint32_t)0x00180000) +#define SDMMC_SW_0 ((uint32_t)0x00080000) +#define SDMMC_SW_1 ((uint32_t)0x00100000) + +/******************* Bit definition for SDMMC_CLK_DIV register *******************/ +#define SDMMC_DIV_MASK ((uint32_t)0x0000001F) +#define SDMMC_CLKOE ((uint32_t)0x00000100) +#define SDMMC_CLKMode ((uint32_t)0x00000200) +#define SDMMC_PHASEINV ((uint32_t)0x00000400) + +/******************* Bit definition for SDMMC_DMA_BEG2 register *******************/ +#define SDMMC_DMAAD2_MASK ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SDMMC_TUNE_DATO register *******************/ +#define SDMMC_TUNNE_DAT0_O ((uint32_t)0x0000000F) +#define SDMMC_TUNNE_DAT1_O ((uint32_t)0x000000F0) +#define SDMMC_TUNNE_DAT2_O ((uint32_t)0x00000F00) +#define SDMMC_TUNNE_DAT3_O ((uint32_t)0x0000F000) +#define SDMMC_TUNNE_DAT4_O ((uint32_t)0x000F0000) +#define SDMMC_TUNNE_DAT5_O ((uint32_t)0x00F00000) +#define SDMMC_TUNNE_DAT6_O ((uint32_t)0x0F000000) +#define SDMMC_TUNNE_DAT7_O ((uint32_t)0xF0000000) + +/******************* Bit definition for SDMMC_TUNE_DATI register *******************/ +#define SDMMC_TUNNE_DAT0_I ((uint32_t)0x0000000F) +#define SDMMC_TUNNE_DAT1_I ((uint32_t)0x000000F0) +#define SDMMC_TUNNE_DAT2_I ((uint32_t)0x00000F00) +#define SDMMC_TUNNE_DAT3_I ((uint32_t)0x0000F000) +#define SDMMC_TUNNE_DAT4_I ((uint32_t)0x000F0000) +#define SDMMC_TUNNE_DAT5_I ((uint32_t)0x00F00000) +#define SDMMC_TUNNE_DAT6_I ((uint32_t)0x0F000000) +#define SDMMC_TUNNE_DAT7_I ((uint32_t)0xF0000000) + +/******************* Bit definition for SDMMC_TUNE_CLK_CMD register *******************/ +#define SDMMC_TUNNE_CLK_O ((uint32_t)0x0000000F) +#define SDMMC_TUNNE_CLK_I ((uint32_t)0x000000F0) +#define SDMMC_TUNNE_CMD_O ((uint32_t)0x000F0000) +#define SDMMC_TUNNE_CMD_I ((uint32_t)0x00F00000) + +/******************* Bit definition for SDMMC_ARGUMENT register *******************/ +#define EMMC_ARGUMENT SDMMC_ARGUMENT +/******************* Bit definition for SDMMC_CMD_SET register *******************/ +#define EMMC_CMDIDX_MASK SDMMC_CMDIDX_MASK +#define EMMC_RPTY_MASK SDMMC_RPTY_MASK +#define EMMC_CKCRC SDMMC_CKCRC +#define EMMC_CKIDX SDMMC_CKIDX + +/******************* Bit definition for SDMMC_RESPONSE0 register *******************/ +#define EMMC_RESPONSE0 SDMMC_RESPONSE0 + +/******************* Bit definition for SDMMC_RESPONSE1 register *******************/ +#define EMMC_RESPONSE1 SDMMC_RESPONSE1 + +/******************* Bit definition for SDMMC_RESPONSE2 register *******************/ +#define EMMC_RESPONSE2 SDMMC_RESPONSE2 + +/******************* Bit definition for SDMMC_RESPONSE3 register *******************/ +#define EMMC_RESPONSE3 SDMMC_RESPONSE3 + +/******************* Bit definition for SDMMC_WRITE_CONT register *******************/ +#define EMMC_WRITE_CONT SDMMC_WRITE_CONT + +/******************* Bit definition for SDMMC_CONTROL register *******************/ +#define EMMC_LW_MASK SDMMC_LW_MASK +#define EMMC_LW_MASK_0 SDMMC_LW_MASK_0 +#define EMMC_LW_MASK_1 SDMMC_LW_MASK_1 + +#define EMMC_ALL_CLR SDMMC_ALL_CLR +#define EMMC_DMAEN SDMMC_DMAEN +#define EMMC_RST_LGC SDMMC_RST_LGC +#define EMMC_NEGSMP SDMMC_NEGSMP +#define EMMC_SLV_MODE SDMMC_SLV_MODE +#define EMMC_SLV_FORCE_ERR SDMMC_SLV_FORCE_ERR + +/******************* Bit definition for SDMMC_TIMEOUT register *******************/ +#define EMMC_TOCNT_MASK SDMMC_TOCNT_MASK + +/******************* Bit definition for SDMMC_STATUS register *******************/ +#define EMMC_MASK_BLOCK_NUM SDMMC_MASK_BLOCK_NUM +#define EMMC_CMDSTA SDMMC_CMDSTA +#define EMMC_DAT0STA SDMMC_DAT0STA + +/******************* Bit definition for SDMMC_INT_FG register *******************/ +#define EMMC_IF_RE_TMOUT SDMMC_IF_RE_TMOUT +#define EMMC_IF_RECRC_WR SDMMC_IF_RECRC_WR +#define EMMC_IF_REIDX_ER SDMMC_IF_REIDX_ER +#define EMMC_IF_CMDDONE SDMMC_IF_CMDDONE +#define EMMC_IF_DATTMO SDMMC_IF_DATTMO +#define EMMC_IF_TRANERR SDMMC_IF_TRANERR +#define EMMC_IF_TRANDONE SDMMC_IF_TRANDONE +#define EMMC_IF_BKGAP SDMMC_IF_BKGAP +#define EMMC_IF_FIFO_OV SDMMC_IF_FIFO_OV +#define EMMC_IF_SDIOINT SDMMC_IF_SDIOINT +#define EMMC_SIF_SLV_BUF_RELEAS SDMMC_SIF_SLV_BUF_RELEAS + +/******************* Bit definition for SDMMC_INT_EN register *******************/ +#define EMMC_IE_RE_TMOUT SDMMC_IE_RE_TMOUT +#define EMMC_IE_RECRC_WR SDMMC_IE_RECRC_WR +#define EMMC_IE_REIDX_ER SDMMC_IE_REIDX_ER +#define EMMC_IE_CMDDONE SDMMC_IE_CMDDONE +#define EMMC_IE_DATTMO SDMMC_IE_DATTMO +#define EMMC_IE_TRANERR SDMMC_IE_TRANERR +#define EMMC_IE_TRANDONE SDMMC_IE_TRANDONE +#define EMMC_IE_FIFO_OV SDMMC_IE_FIFO_OV +#define EMMC_IE_SDIOINT SDMMC_IE_SDIOINT + +/******************* Bit definition for SDMMC_DMA_BEG1 register *******************/ +#define EMMC_DMAAD1_MASK SDMMC_DMAAD1_MASK + +/******************* Bit definition for SDMMC_BLOCK_CFG register *******************/ +#define EMMC_BKNUM_MASK SDMMC_BKNUM_MASK +#define EMMC_BKSIZE_MASK SDMMC_BKSIZE_MASK + +/******************* Bit definition for SDMMC_TRAN_MODE register *******************/ +#define EMMC_DMA_DIR SDMMC_DMA_DIR +#define EMMC_GAP_STOP SDMMC_GAP_STOP +#define EMMC_MODE_BOOT SDMMC_MODE_BOOT +#define EMMC_AUTOGAPSTOP SDMMC_AUTOGAPSTOP + +#define EMMC_DMATN_CNT SDMMC_DMATN_CNT + +#define EMMC_DULEDMA_EN SDMMC_DULEDMA_EN +#define EMMC_DDR_MODE SDMMC_DDR_MODE +#define EMMC_CARE_NEG SDMMC_CARE_NEG + +#define EMMC_SW SDMMC_SW +#define EMMC_SW_0 SDMMC_SW_0 +#define EMMC_SW_1 SDMMC_SW_1 + +/******************* Bit definition for SDMMC_CLK_DIV register *******************/ +#define EMMC_DIV_MASK SDMMC_DIV_MASK +#define EMMC_CLKOE SDMMC_CLKOE +#define EMMC_CLKMode SDMMC_CLKMode +#define EMMC_PHASEINV SDMMC_PHASEINV + +/******************* Bit definition for SDMMC_DMA_BEG2 register *******************/ +#define EMMC_DMAAD2_MASK SDMMC_DMAAD2_MASK + +/******************* Bit definition for SDMMC_TUNE_DATO register *******************/ +#define EMMC_TUNNE_DAT0_O SDMMC_TUNNE_DAT0_O +#define EMMC_TUNNE_DAT1_O SDMMC_TUNNE_DAT1_O +#define EMMC_TUNNE_DAT2_O SDMMC_TUNNE_DAT2_O +#define EMMC_TUNNE_DAT3_O SDMMC_TUNNE_DAT3_O +#define EMMC_TUNNE_DAT4_O SDMMC_TUNNE_DAT4_O +#define EMMC_TUNNE_DAT5_O SDMMC_TUNNE_DAT5_O +#define EMMC_TUNNE_DAT6_O SDMMC_TUNNE_DAT6_O +#define EMMC_TUNNE_DAT7_O SDMMC_TUNNE_DAT7_O + +/******************* Bit definition for SDMMC_TUNE_DATI register *******************/ +#define EMMC_TUNNE_DAT0_I SDMMC_TUNNE_DAT0_I +#define EMMC_TUNNE_DAT1_I SDMMC_TUNNE_DAT1_I +#define EMMC_TUNNE_DAT2_I SDMMC_TUNNE_DAT2_I +#define EMMC_TUNNE_DAT3_I SDMMC_TUNNE_DAT3_I +#define EMMC_TUNNE_DAT4_I SDMMC_TUNNE_DAT4_I +#define EMMC_TUNNE_DAT5_I SDMMC_TUNNE_DAT5_I +#define EMMC_TUNNE_DAT6_I SDMMC_TUNNE_DAT6_I +#define EMMC_TUNNE_DAT7_I SDMMC_TUNNE_DAT7_I + +/******************* Bit definition for SDMMC_TUNE_CLK_CMD register *******************/ +#define EMMC_TUNNE_CLK_O SDMMC_TUNNE_CLK_O +#define EMMC_TUNNE_CLK_I SDMMC_TUNNE_CLK_I +#define EMMC_TUNNE_CMD_O SDMMC_TUNNE_CMD_O +#define EMMC_TUNNE_CMD_I SDMMC_TUNNE_CMD_I + +/******************************************************************************/ +/* SAI */ +/******************************************************************************/ +/******************* Bit definition for SAI_xCFGR1 register *******************/ +#define SAI_CFGR1_MODE ((uint32_t)0x00000003) +#define SAI_CFGR1_MODE_0 ((uint32_t)0x00000001) +#define SAI_CFGR1_MODE_1 ((uint32_t)0x00000002) + +#define SAI_CFGR1_PRTCFG ((uint32_t)0x0000000C) +#define SAI_CFGR1_PRTCFG_0 ((uint32_t)0x00000004) +#define SAI_CFGR1_PRTCFG_1 ((uint32_t)0x00000008) + +#define SAI_CFGR1_DS ((uint32_t)0x000000E0) +#define SAI_CFGR1_DS_0 ((uint32_t)0x00000020) +#define SAI_CFGR1_DS_1 ((uint32_t)0x00000040) +#define SAI_CFGR1_DS_2 ((uint32_t)0x00000080) + +#define SAI_CFGR1_LSBFIRST ((uint32_t)0x00000100) +#define SAI_CFGR1_CKSTR ((uint32_t)0x00000200) + +#define SAI_CFGR1_SYNCEN ((uint32_t)0x00000C00) +#define SAI_CFGR1_SYNCEN_0 ((uint32_t)0x00000400) +#define SAI_CFGR1_SYNCEN_1 ((uint32_t)0x00000800) +#define SAI_CFGR1_MONO ((uint32_t)0x00001000) +#define SAI_CFGR1_EN ((uint32_t)0x00010000) +#define SAI_CFGR1_DMAEN ((uint32_t)0x00020000) +#define SAI_CFGR1_NODIV ((uint32_t)0x00080000) +#define SAI_CFGR1_MCKDIV ((uint32_t)0x03F00000) +#define SAI_CFGR1_OSR ((uint32_t)0x04000000) + +/******************* Bit definition for SAI_xCFGR2 register *******************/ +#define SAI_CFGR2_FTH ((uint32_t)0x00000007) +#define SAI_CFGR2_FTH_0 ((uint32_t)0x00000001) +#define SAI_CFGR2_FTH_1 ((uint32_t)0x00000002) +#define SAI_CFGR2_FTH_2 ((uint32_t)0x00000004) + +#define SAI_CFGR2_FFLUSH ((uint32_t)0x00000008) +#define SAI_CFGR2_TRIS ((uint32_t)0x00000010) +#define SAI_CFGR2_MUTE ((uint32_t)0x00000020) +#define SAI_CFGR2_MUTEVAL ((uint32_t)0x00000040) + +#define SAI_CFGR2_MUTECNT ((uint32_t)0x00001F80) + +#define SAI_CFGR2_CPL ((uint32_t)0x00002000) +#define SAI_CFGR2_COMP ((uint32_t)0x0000C000) + +/******************* Bit definition for SAI_xFRCR register *******************/ +#define SAI_FRCR_FRL ((uint32_t)0x000000FF) + +#define SAI_FRCR_FSALL ((uint32_t)0x00007F00) +#define SAI_FRCR_FSDEF ((uint32_t)0x00010000) +#define SAI_FRCR_FSPOL ((uint32_t)0x00020000) +#define SAI_FRCR_FSOFF ((uint32_t)0x00040000) + +/******************* Bit definition for SAI_xSLOTR register *******************/ +#define SAI_SLOTR_FBOFF ((uint32_t)0x0000001F) +#define SAI_SLOTR_SLOTSZ ((uint32_t)0x000000C0) +#define SAI_SLOTR_NBSLOT ((uint32_t)0x00000F00) +#define SAI_SLOTR_SLOTEN ((uint32_t)0xFFFF0000) + +/******************* Bit definition for SAI_xINTENR register *******************/ +#define SAI_INTENR_OVRUDRIE ((uint32_t)0x00000001) +#define SAI_INTENR_MUTEDETIE ((uint32_t)0x00000002) +#define SAI_INTENR_WCKCFGIE ((uint32_t)0x00000004) +#define SAI_INTENR_FREQIE ((uint32_t)0x00000008) +#define SAI_INTENR_CNRDYIE ((uint32_t)0x00000010) +#define SAI_INTENR_AFSDETIE ((uint32_t)0x00000020) +#define SAI_INTENR_LFSDETIE ((uint32_t)0x00000040) + +/********************* Bit definition for SAI_xSR register *********************/ +#define SAI_SR_OVRUDR ((uint32_t)0x00000001) +#define SAI_SR_MUTEDET ((uint32_t)0x00000002) +#define SAI_SR_WCKCFG ((uint32_t)0x00000004) +#define SAI_SR_FREQ ((uint32_t)0x00000008) +#define SAI_SR_CNRDY ((uint32_t)0x00000010) +#define SAI_SR_AFSDET ((uint32_t)0x00000020) +#define SAI_SR_LFSDET ((uint32_t)0x00000040) + +#define SAI_SR_FLTH ((uint32_t)0x00070000) +#define SAI_SR_FLTH_0 ((uint32_t)0x00010000) +#define SAI_SR_FLTH_1 ((uint32_t)0x00020000) +#define SAI_SR_FLTH_2 ((uint32_t)0x00030000) + +/********************* Bit definition for SAI_xDATAR register *********************/ +#define SAI_DATAR_DR ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* SERDES */ +/******************************************************************************/ +/********************* Bit definition for SERDES_CTRL register *********************/ +#define SDS_CLR_ALL ((uint32_t)0x00000001) +#define SDS_RESET_LINK ((uint32_t)0x00000002) +#define SDS_RESET_PHY ((uint32_t)0x00000004) +#define SDS_INT_BUSY_EN ((uint32_t)0x00000008) +#define SDS_RX_POLARITY ((uint32_t)0x00000010) +#define SDS_RX_EN ((uint32_t)0x00000020) +#define SDS_TX_EN ((uint32_t)0x00000040) +#define SDS_DMA_EN ((uint32_t)0x00000080) +#define SDS_PLL_FACTOR ((uint32_t)0x00001F00) +#define SDS_PLL_PWR_UP ((uint32_t)0x00002000) +#define SDS_RX_PWR_UP ((uint32_t)0x00004000) +#define SDS_TX_PWR_UP ((uint32_t)0x00008000) +#define SDS_PHY_PWR_UP ((uint32_t)0x00010000) +#define SDS_CONT_EN ((uint32_t)0x00020000) +#define SDS_ALIGN_EN ((uint32_t)0x00040000) + + + +/********************* Bit definition for SERDES_INT_EN register *********************/ +#define SDS_PHYRDY_IE ((uint32_t)0x00000001) +#define SDS_RECV_ERR_IE ((uint32_t)0x00000002) +#define SDS_TRAN_DONE_IE ((uint32_t)0x00000002) +#define SDS_RECV_DONE_IE ((uint32_t)0x00000004) +#define SDS_FIFO_OV_IE ((uint32_t)0x00000008) +#define SDS_COMINIT_IE ((uint32_t)0x00000020) + +/********************* Bit definition for SERDES_INT_FG register *********************/ +#define SDS_PHYRDY_IF ((uint32_t)0x00000001) +#define SDS_RECV_ERR_IF ((uint32_t)0x00000002) +#define SDS_TRAN_DONE_IF ((uint32_t)0x00000002) +#define SDS_RECV_DONE_IF ((uint32_t)0x00000004) +#define SDS_FIFO_OV_IF ((uint32_t)0x00000008) +#define SDS_COMINIT_IF ((uint32_t)0x00000020) +#define SDS_PHYRDY ((uint32_t)0x00010000) +#define SDS_RX_SEQ_MATCH ((uint32_t)0x00020000) +#define SDS_RECV_CRC_OK ((uint32_t)0x00040000) +#define SDS_PLL_LOCK ((uint32_t)0x00080000) +#define SDS_LINK_FREE ((uint32_t)0x00100000) +#define SDS_R_FIFO_RDY ((uint32_t)0x00200000) +#define SDS_RX_SEQ_NUM ((uint32_t)0x0F000000) +#define SDS_TX_SEQ_NUM ((uint32_t)0xF0000000) + +/********************* Bit definition for SERDES_RTX_CTRL register *********************/ +#define SDS_SERDES_TX_LEN ((uint32_t)0x0000FFFF) +#define SDS_LINK_INIT ((uint32_t)0x00010000) +#define SDS_TX_VLD ((uint32_t)0x00020000) +#define SDS_BUF_MODE ((uint32_t)0x00040000) + +/********************* Bit definition for SERDES_RX_LEN0 register *********************/ +#define SDS_SERDES_RX_LEN0 ((uint32_t)0x0000FFFF) + +/********************* Bit definition for SERDES_DATA0 register *********************/ +#define SDS_SERDES_DATA0 ((uint32_t)0xFFFFFFFF) + +/********************* Bit definition for SERDES_DMA0 register *********************/ +#define SDS_SERDES_DMA0 ((uint32_t)0xFFFFFFFF) + +/********************* Bit definition for SERDES_RX_LEN1 register *********************/ +#define SDS_SERDES_RX_LEN1 ((uint32_t)0x0000FFFF) + +/********************* Bit definition for SERDES_DATA1 register *********************/ +#define SDS_SERDES_DATA1 ((uint32_t)0xFFFFFFFF) + +/********************* Bit definition for SERDES_DMA1 register *********************/ +#define SDS_SERDES_DMA1 ((uint32_t)0xFFFFFFFF) + + +/******************************************************************************/ +/* SWPMI */ +/******************************************************************************/ +/******************* Bit definition for SWPMI_CR register *******************/ +#define SWPMI_RXDMA ((uint32_t)0x00000001) +#define SWPMI_TXDMA ((uint32_t)0x00000002) +#define SWPMI_RXMODE ((uint32_t)0x00000004) +#define SWPMI_TXMODE ((uint32_t)0x00000008) +#define SWPMI_LPBK ((uint32_t)0x00000010) +#define SWPMI_SWPACT ((uint32_t)0x00000020) +#define SWPMI_DEACT ((uint32_t)0x00000400) +#define SWPMI_SWPTEN ((uint32_t)0x00000800) + +/******************* Bit definition for SWPMI_BRR register *******************/ +#define SWPMI_BR ((uint32_t)0x000000FF) + +/******************* Bit definition for SWPMI_ISR register *******************/ +#define SWPMI_RXBFF ((uint32_t)0x00000001) +#define SWPMI_TXBEF ((uint32_t)0x00000002) +#define SWPMI_RXBERF ((uint32_t)0x00000004) +#define SWPMI_RXOVRF ((uint32_t)0x00000008) +#define SWPMI_TXUNRF ((uint32_t)0x00000010) +#define SWPMI_RXNE ((uint32_t)0x00000020) +#define SWPMI_TXE ((uint32_t)0x00000040) +#define SWPMI_TCF ((uint32_t)0x00000080) +#define SWPMI_SRF ((uint32_t)0x00000100) +#define SWPMI_SUSP ((uint32_t)0x00000200) +#define SWPMI_DEACTF ((uint32_t)0x00000400) +#define SWPMI_RDYF ((uint32_t)0x00000800) + +/******************* Bit definition for SWPMI_ICR register *******************/ +#define SWPMI_CRXBFF ((uint32_t)0x00000001) +#define SWPMI_CTXBEF ((uint32_t)0x00000002) +#define SWPMI_CRXBERF ((uint32_t)0x00000004) +#define SWPMI_CRXOVRF ((uint32_t)0x00000008) +#define SWPMI_CTXUNRF ((uint32_t)0x00000010) +#define SWPMI_CTCF ((uint32_t)0x00000080) +#define SWPMI_CSRF ((uint32_t)0x00000100) +#define SWPMI_CRDYF ((uint32_t)0x00000800) + +/******************* Bit definition for SWPMI_IER register *******************/ +#define SWPMI_RXBFIE ((uint32_t)0x00000001) +#define SWPMI_TXBEIE ((uint32_t)0x00000002) +#define SWPMI_RXBERIE ((uint32_t)0x00000004) +#define SWPMI_RXOVRIE ((uint32_t)0x00000008) +#define SWPMI_TXUNRIE ((uint32_t)0x00000010) +#define SWPMI_RIE ((uint32_t)0x00000020) +#define SWPMI_TIE ((uint32_t)0x00000040) +#define SWPMI_TCIE ((uint32_t)0x00000080) +#define SWPMI_SRIE ((uint32_t)0x00000100) +#define SWPMI_RDYIE ((uint32_t)0x00000800) + +/******************* Bit definition for SWPMI_RFL register *******************/ +#define SWPMI_RFL ((uint32_t)0x0000001F) + +/******************* Bit definition for SWPMI_TDR register *******************/ +#define SWPMI_TD ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for SWPMI_OR register *******************/ +#define SWPMI_SWP_TBYP ((uint32_t)0x00000001) + +#define SWPMI_SWP_ISEL ((uint32_t)0x0000000C) +#define SWPMI_SWP_ISEL_0 ((uint32_t)0x00000004) +#define SWPMI_SWP_ISEL_1 ((uint32_t)0x00000008) + +/******************************************************************************/ +/* FMC */ +/******************************************************************************/ +/******************* Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) +#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) + +#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) +#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) +#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) + +#define FMC_BCR1_MWID ((uint32_t)0x00000030) +#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) +#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) + +#define FMC_BCR1_MFACCEN ((uint32_t)0x00000040) +#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) +#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) +#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) + +#define FMC_BCR1_WREN ((uint32_t)0x00001000) +#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) +#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) +#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) + +#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) +#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) +#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) +#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) + +#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) + +#define FMC_BCR1_BMP ((uint32_t)0x03000000) +#define FMC_BCR1_BMP_0 ((uint32_t)0x01000000) +#define FMC_BCR1_BMP_1 ((uint32_t)0x02000000) + +#define FMC_BCR1_FMCEN ((uint32_t)0x80000000) + +/******************* Bit definition for FMC_BCR2 register *******************/ +#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) +#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) + +#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) +#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) +#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) + +#define FMC_BCR2_MWID ((uint32_t)0x00000030) +#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) +#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) + +#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) +#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) +#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) +#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) +#define FMC_BCR2_WREN ((uint32_t)0x00001000) +#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) +#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) +#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) + +#define FMC_BCR2_CPSZIE ((uint32_t)0x00070000) +#define FMC_BCR2_CPSZIE_0 ((uint32_t)0x00010000) +#define FMC_BCR2_CPSZIE_1 ((uint32_t)0x00020000) +#define FMC_BCR2_CPSZIE_2 ((uint32_t)0x00040000) + +#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) +#define FMC_BCR2_BMP ((uint32_t)0x03000000) +#define FMC_BCR2_BMP_0 ((uint32_t)0x01000000) +#define FMC_BCR2_BMP_1 ((uint32_t)0x02000000) + +#define FMC_BCR2_FMCEN ((uint32_t)0x80000000) + +/******************* Bit definition for FMC_BCR3 register *******************/ +#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) +#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) + +#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) +#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) +#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) + +#define FMC_BCR3_MWID ((uint32_t)0x00000030) +#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) +#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) + +#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) +#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) +#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) +#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) +#define FMC_BCR3_WREN ((uint32_t)0x00001000) +#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) +#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) +#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) + +#define FMC_BCR3_CPSZIE ((uint32_t)0x00070000) +#define FMC_BCR3_CPSZIE_0 ((uint32_t)0x00010000) +#define FMC_BCR3_CPSZIE_1 ((uint32_t)0x00020000) +#define FMC_BCR3_CPSZIE_2 ((uint32_t)0x00040000) + +#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) +#define FMC_BCR3_BMP ((uint32_t)0x03000000) +#define FMC_BCR3_BMP_0 ((uint32_t)0x01000000) +#define FMC_BCR3_BMP_1 ((uint32_t)0x02000000) + +#define FMC_BCR3_FMCEN ((uint32_t)0x80000000) + +/******************* Bit definition for FMC_BCR4 register *******************/ +#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) +#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) + +#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) +#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) +#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) + +#define FMC_BCR4_MWID ((uint32_t)0x00000030) +#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) +#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) + +#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) +#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) +#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) +#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) +#define FMC_BCR4_WREN ((uint32_t)0x00001000) +#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) +#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) +#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) + +#define FMC_BCR4_CPSZIE ((uint32_t)0x00070000) +#define FMC_BCR4_CPSZIE_0 ((uint32_t)0x00010000) +#define FMC_BCR4_CPSZIE_1 ((uint32_t)0x00020000) +#define FMC_BCR4_CPSZIE_2 ((uint32_t)0x00040000) + +#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) +#define FMC_BCR4_BMP ((uint32_t)0x03000000) +#define FMC_BCR4_BMP_0 ((uint32_t)0x01000000) +#define FMC_BCR4_BMP_1 ((uint32_t)0x02000000) + +#define FMC_BCR4_FMCEN ((uint32_t)0x80000000) + +/******************* Bit definition for FMC_BTR1 register *******************/ +#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) +#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) +#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) +#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) +#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) +#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) +#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) + +#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) +#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) +#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) +#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) +#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) + +#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) +#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BTR2 register *******************/ +#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) +#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) +#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) +#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) +#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) +#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) +#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) + +#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) +#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) +#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) +#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) +#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) + +#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) +#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BTR3 register *******************/ +#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) +#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) +#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) +#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) +#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) +#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) +#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) + +#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) +#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) +#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) +#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) +#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) + +#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) +#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BTR4 register *******************/ +#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) +#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) +#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) +#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) +#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) +#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) +#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) + +#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) +#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) +#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) +#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) +#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) + +#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) +#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BWTR1 register *******************/ +#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) +#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) +#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) +#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BWTR2 register *******************/ +#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) +#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) +#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) +#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BWTR3 register *******************/ +#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) +#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) +#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) +#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_BWTR4 register *******************/ +#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) +#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) +#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) +#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) +#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) + +#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) +#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) +#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) +#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) +#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) + +#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) +#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) +#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) +#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) +#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) +#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) +#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) +#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) +#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) + +#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) +#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) +#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) +#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) +#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) + +#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) +#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) +#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) + +/******************* Bit definition for FMC_PCR register *******************/ +#define FMC_PCR_PWAITEN ((uint32_t)0x00000020) +#define FMC_PCR_PBKEN ((uint32_t)0x00000040) +#define FMC_PCR_PTYP ((uint32_t)0x00000080) +#define FMC_PCR_PWID ((uint32_t)0x00000300) +#define FMC_PCR_PWID_0 ((uint32_t)0x00000100) +#define FMC_PCR_PWID_1 ((uint32_t)0x00000200) + +#define FMC_PCR_ECCEN ((uint32_t)0x00000400) + +#define FMC_PCR_TCLR ((uint32_t)0x00001E00) +#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) +#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) +#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) +#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) + +#define FMC_PCR_TAR ((uint32_t)0x0001E000) +#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) +#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) +#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) +#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) + +#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) +#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) +#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) +#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) + +/******************* Bit definition for FMC_SR register *******************/ +#define FMC_SR_IRS ((uint32_t)0x00000001) +#define FMC_SR_ILS ((uint32_t)0x00000002) +#define FMC_SR_IFS ((uint32_t)0x00000004) +#define FMC_SR_IREN ((uint32_t)0x00000008) +#define FMC_SR_ILEN ((uint32_t)0x00000010) +#define FMC_SR_IFEN ((uint32_t)0x00000020) +#define FMC_SR_FEMPT ((uint32_t)0x00000040) + +/******************* Bit definition for FMC_PMEM register *******************/ +#define FMC_PMEM_MEMSET ((uint32_t)0x000000FF) +#define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00) +#define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000) +#define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000) + +/******************* Bit definition for FMC_PATT register *******************/ +#define FMC_PATT_ATTSET ((uint32_t)0x000000FF) +#define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00) +#define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000) +#define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000) + +/******************* Bit definition for FMC_ECCR register *******************/ +#define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for FMC_SDCR1 register *******************/ +#define FMC_SDCR1_NC ((uint32_t)0x00000003) +#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) +#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) + +#define FMC_SDCR1_NR ((uint32_t)0x0000000C) +#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) +#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) + +#define FMC_SDCR1_MWID ((uint32_t)0x00000030) +#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) +#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) + +#define FMC_SDCR1_NB ((uint32_t)0x00000040) +#define FMC_SDCR1_CAS ((uint32_t)0x00000180) +#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) +#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) + +#define FMC_SDCR1_WP ((uint32_t)0x00000200) +#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) +#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) +#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) + +#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) + +#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) +#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) +#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) + +/******************* Bit definition for FMC_SDCR2 register *******************/ +#define FMC_SDCR2_NC ((uint32_t)0x00000003) +#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) +#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) + +#define FMC_SDCR2_NR ((uint32_t)0x0000000C) +#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) +#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) + +#define FMC_SDCR2_MWID ((uint32_t)0x00000030) +#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) +#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) + +#define FMC_SDCR2_NB ((uint32_t)0x00000040) +#define FMC_SDCR2_CAS ((uint32_t)0x00000180) +#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) +#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) + +#define FMC_SDCR2_WP ((uint32_t)0x00000200) +#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) +#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) +#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) + +#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) + +#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) +#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) +#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) + +/******************* Bit definition for FMC_SDTR1 register *******************/ +#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) +#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) +#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) +#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) +#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) + +#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) +#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) +#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000020) +#define FMC_SDTR1_TXSR_4 ((uint32_t)0x00000040) +#define FMC_SDTR1_TXSR_8 ((uint32_t)0x00000080) + +#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) +#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) +#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) +#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) +#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) + +#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) +#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) +#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) +#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) +#define FMC_SDTR1_TRC_3 ((uint32_t)0x00008000) + +#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) +#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) +#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) +#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) +#define FMC_SDTR1_TWR_3 ((uint32_t)0x00080000) + +#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) +#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) +#define FMC_SDTR1_TRP_2 ((uint32_t)0x00200000) +#define FMC_SDTR1_TRP_3 ((uint32_t)0x00400000) +#define FMC_SDTR1_TRP_4 ((uint32_t)0x00800000) + +#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) +#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) +#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) +#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) +#define FMC_SDTR1_TRCD_3 ((uint32_t)0x08000000) + +/******************* Bit definition for FMC_SDTR2 register *******************/ +#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) +#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) +#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) +#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) +#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) + +#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) +#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) +#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000020) +#define FMC_SDTR2_TXSR_4 ((uint32_t)0x00000040) +#define FMC_SDTR2_TXSR_8 ((uint32_t)0x00000080) + +#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) +#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) +#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) +#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) +#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) + +#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) +#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) +#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) +#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) +#define FMC_SDTR2_TRC_3 ((uint32_t)0x00008000) + +#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) +#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) +#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) +#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) +#define FMC_SDTR2_TWR_3 ((uint32_t)0x00080000) + +#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) +#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) +#define FMC_SDTR2_TRP_2 ((uint32_t)0x00200000) +#define FMC_SDTR2_TRP_3 ((uint32_t)0x00400000) +#define FMC_SDTR2_TRP_4 ((uint32_t)0x00800000) + +#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) +#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) +#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) +#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) +#define FMC_SDTR2_TRCD_3 ((uint32_t)0x08000000) + +/******************* Bit definition for FMC_SDCMR register *******************/ +#define FMC_SDCMR_MODE ((uint32_t)0x00000007) +#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) +#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) +#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) + +#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) +#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) + +#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) +#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) +#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) +#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) +#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) + +#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) + +/******************* Bit definition for FMC_SDRTR register *******************/ +#define FMC_SDRTR_CRE ((uint32_t)0x00000001) +#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) +#define FMC_SDRTR_REIE ((uint32_t)0x00004000) + +/******************* Bit definition for FMC_SDSR register *******************/ +#define FMC_SDSR_RE ((uint32_t)0x00000001) + +#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) +#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) +#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) + +#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) +#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) +#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) + +#define FMC_SDSR_BUSY ((uint32_t)0x00000020) + +/******************* Bit definition for FMC_MISC register *******************/ +#define FMC_MISC_NRFS_CNT ((uint32_t)0x0000000F) +#define FMC_MISC_NRFS_CNT_0 ((uint32_t)0x00000001) +#define FMC_MISC_NRFS_CNT_1 ((uint32_t)0x00000002) +#define FMC_MISC_NRFS_CNT_2 ((uint32_t)0x00000004) +#define FMC_MISC_NRFS_CNT_3 ((uint32_t)0x00000008) + +#define FMC_MISC_Phase_Sel ((uint32_t)0x000000F0) +#define FMC_MISC_Phase_Sel_0 ((uint32_t)0x00000010) +#define FMC_MISC_Phase_Sel_1 ((uint32_t)0x00000020) +#define FMC_MISC_Phase_Sel_2 ((uint32_t)0x00000040) +#define FMC_MISC_Phase_Sel_3 ((uint32_t)0x00000080) + +#define FMC_MISC_Enhance_read_mode ((uint32_t)0x00001000) +#define FMC_MISC_En_Bank1 ((uint32_t)0x00010000) +#define FMC_MISC_En_Bank2 ((uint32_t)0x00020000) + +/******************************************************************************/ +/* ECDC */ +/******************************************************************************/ +/******************* Bit definition for ECDC_CTRL register *******************/ +#define ECDC_KEYEX_EN ((uint32_t)0x00000001) +#define ECDC_NORMAL_EN ((uint32_t)0x00000002) +#define ECDC_MODE_SEL ((uint32_t)0x00000008) + +#define ECDC_CLKDIV_MASK ((uint32_t)0x00000070) + +#define ECDC_WRSRAM_EN ((uint32_t)0x00000080) +#define ECDC_ALGRM_MOD ((uint32_t)0x00000100) +#define ECDC_CIPHER_MOD ((uint32_t)0x00000200) + +#define ECDC_KLEN_MASK ((uint32_t)0x00000C00) + +#define ECDC_DAT_MOD ((uint32_t)0x00002000) + +#define ECDC_IE_SINGLE ((uint32_t)0x00020000) +#define ECDC_IE_WRSRAM ((uint32_t)0x00040000) + +#define ECDC_CLOCK_SELECT ((uint32_t)0x01000000) +#define ECDC_ECDC_SM4_CLOCK_EN ((uint32_t)0x02000000) + +/******************* Bit definition for ECDC_INT_FG register *******************/ +#define ECDC_IF_EKDONE ((uint32_t)0x00010000) +#define ECDC_IF_SINGLE ((uint32_t)0x00020000) +#define ECDC_IF_WRSRAM ((uint32_t)0x00040000) + +/******************* Bit definition for ECDC_KEY register *******************/ +#define ECDC_KEY_255T224 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_223T192 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_191T160 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_159T128 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_127T96 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_95T64 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_63T32 ((uint32_t)0xFFFFFFFF) +#define ECDC_KEY_31T0 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for ECDC_IV register *******************/ +#define ECDC_IV_127T96 ((uint32_t)0xFFFFFFFF) +#define ECDC_IV_95T64 ((uint32_t)0xFFFFFFFF) +#define ECDC_IV_63T32 ((uint32_t)0xFFFFFFFF) +#define ECDC_IV_31T0 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for ECDC_SGSD register *******************/ +#define ECDC_SGSD_127T96 ((uint32_t)0xFFFFFFFF) +#define ECDC_SGSD_95T64 ((uint32_t)0xFFFFFFFF) +#define ECDC_SGSD_63T32 ((uint32_t)0xFFFFFFFF) +#define ECDC_SGSD_31T0 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for ECDC_SGRT register *******************/ +#define ECDC_SGRT_127T96 ((uint32_t)0xFFFFFFFF) +#define ECDC_SGRT_95T64 ((uint32_t)0xFFFFFFFF) +#define ECDC_SGRT_63T32 ((uint32_t)0xFFFFFFFF) +#define ECDC_SGRT_31T0 ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for ECDC_SRC_ADDR register *******************/ +#define ECDC_SRAM_SRC_ADDR ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for ECDC_DST_ADDR register *******************/ +#define ECDC_SRAM_DST_ADDR ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for ECDC_SRAM_LEN register *******************/ +#define ECDC_SRAM_LEN ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* DFSDM */ +/******************************************************************************/ +/******************* Bit definition for DFSDM_CFGR1 register *******************/ +#define DFSDM_CFGR1_SITP ((uint32_t)0x00000003) +#define DFSDM_CFGR1_SITP_0 ((uint32_t)0x00000001) +#define DFSDM_CFGR1_SITP_1 ((uint32_t)0x00000002) + +#define DFSDM_CFGR1_SPICKSEL ((uint32_t)0x0000000C) +#define DFSDM_CFGR1_SPICKSEL_0 ((uint32_t)0x00000004) +#define DFSDM_CFGR1_SPICKSEL_1 ((uint32_t)0x00000008) + +#define DFSDM_CFGR1_SCDEN ((uint32_t)0x00000020) +#define DFSDM_CFGR1_CKABEN ((uint32_t)0x00000040) +#define DFSDM_CFGR1_CHEN ((uint32_t)0x00000080) +#define DFSDM_CFGR1_CHINSEL ((uint32_t)0x00000100) + +#define DFSDM_CFGR1_DATMPX ((uint32_t)0x00003000) +#define DFSDM_CFGR1_DATMPX_0 ((uint32_t)0x00001000) +#define DFSDM_CFGR1_DATMPX_1 ((uint32_t)0x00002000) + +#define DFSDM_CFGR1_DATPACK ((uint32_t)0x0000C000) +#define DFSDM_CFGR1_DATPACK_0 ((uint32_t)0x00004000) +#define DFSDM_CFGR1_DATPACK_1 ((uint32_t)0x00008000) + +#define DFSDM_CFGR1_CKOUTDIV ((uint32_t)0x00FF0000) + +#define DFSDM_CFGR1_CKOUTSRC ((uint32_t)0x40000000) +#define DFSDM_CFGR1_DFSDMEN ((uint32_t)0x80000000) + +/******************* Bit definition for DFSDM_CFGR2 register *******************/ +#define DFSDM_CFGR2_DTRBS ((uint32_t)0x000000F8) +#define DFSDM_CFGR2_OFFSET ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_AWSCDR register *******************/ +#define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FF) + +#define DFSDM_AWSCDR_BKSCD ((uint32_t)0x00003000) +#define DFSDM_AWSCDR_BKSCD_0 ((uint32_t)0x00001000) +#define DFSDM_AWSCDR_BKSCD_1 ((uint32_t)0x00002000) + +#define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000) +#define DFSDM_AWSCDR_AWFOSR_0 ((uint32_t)0x00010000) +#define DFSDM_AWSCDR_AWFOSR_1 ((uint32_t)0x00020000) +#define DFSDM_AWSCDR_AWFOSR_2 ((uint32_t)0x00040000) +#define DFSDM_AWSCDR_AWFOSR_3 ((uint32_t)0x00080000) +#define DFSDM_AWSCDR_AWFOSR_4 ((uint32_t)0x00100000) + +#define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000) +#define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000) +#define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000) + +/******************* Bit definition for DFSDM_WDATR register *******************/ +#define DFSDM_WDATR ((uint16_t)0xFFFF) + +/******************* Bit definition for DFSDM_DATINR register *******************/ +#define DFSDM_DATINR_INDAT0 ((uint32_t)0x0000FFFF) +#define DFSDM_DATINR_INDAT1 ((uint32_t)0xFFFF0000) + +/******************* Bit definition for DFSDM_FLTCR1 register *******************/ +#define DFSDM_FLTCR1_DFEN ((uint32_t)0x00000001) +#define DFSDM_FLTCR1_JSWSTART ((uint32_t)0x00000002) +#define DFSDM_FLTCR1_JSYNC ((uint32_t)0x00000008) +#define DFSDM_FLTCR1_JSCAN ((uint32_t)0x00000010) +#define DFSDM_FLTCR1_JDMAEN ((uint32_t)0x00000020) + +#define DFSDM_FLTCR1_JEXTSEL ((uint32_t)0x00000F00) +#define DFSDM_FLTCR1_JEXTSEL_0 ((uint32_t)0x00000100) +#define DFSDM_FLTCR1_JEXTSEL_1 ((uint32_t)0x00000200) +#define DFSDM_FLTCR1_JEXTSEL_2 ((uint32_t)0x00000400) +#define DFSDM_FLTCR1_JEXTSEL_3 ((uint32_t)0x00000800) + +#define DFSDM_FLTCR1_JEXTEN ((uint32_t)0x00006000) +#define DFSDM_FLTCR1_JEXTEN_0 ((uint32_t)0x00002000) +#define DFSDM_FLTCR1_JEXTEN_1 ((uint32_t)0x00004000) + +#define DFSDM_FLTCR1_RSWSTART ((uint32_t)0x00020000) +#define DFSDM_FLTCR1_RCONT ((uint32_t)0x00040000) +#define DFSDM_FLTCR1_RSYNC ((uint32_t)0x00080000) + +#define DFSDM_FLTCR1_RDMAEN ((uint32_t)0x00200000) + +#define DFSDM_FLTCR1_RCH ((uint32_t)0x01000000) + +#define DFSDM_FLTCR1_FAST ((uint32_t)0x20000000) +#define DFSDM_FLTCR1_AWFSEL ((uint32_t)0x40000000) + +/******************* Bit definition for DFSDM_FLTCR2 register *******************/ +#define DFSDM_FLTCR2_JEOCIE ((uint32_t)0x00000001) +#define DFSDM_FLTCR2_REOCIE ((uint32_t)0x00000002) +#define DFSDM_FLTCR2_JOVRIE ((uint32_t)0x00000004) +#define DFSDM_FLTCR2_ROVRIE ((uint32_t)0x00000008) +#define DFSDM_FLTCR2_AWDIE ((uint32_t)0x00000010) +#define DFSDM_FLTCR2_SCDIE ((uint32_t)0x00000020) +#define DFSDM_FLTCR2_CKABIE ((uint32_t)0x00000040) + +#define DFSDM_FLTCR2_EXCH ((uint32_t)0x00000300) +#define DFSDM_FLTCR2_EXCH_0 ((uint32_t)0x00000100) +#define DFSDM_FLTCR2_EXCH_1 ((uint32_t)0x00000200) + +#define DFSDM_FLTCR2_AWDCH ((uint32_t)0x00030000) +#define DFSDM_FLTCR2_AWDCH_0 ((uint32_t)0x00010000) +#define DFSDM_FLTCR2_AWDCH_1 ((uint32_t)0x00020000) + +/******************* Bit definition for DFSDM_FLTISR register *******************/ +#define DFSDM_FLTISR_JEOCF ((uint32_t)0x00000001) +#define DFSDM_FLTISR_REOCF ((uint32_t)0x00000002) +#define DFSDM_FLTISR_JOVRF ((uint32_t)0x00000004) +#define DFSDM_FLTISR_ROVRF ((uint32_t)0x00000008) +#define DFSDM_FLTISR_AWDF ((uint32_t)0x00000010) + +#define DFSDM_FLTISR_JCIP ((uint32_t)0x00002000) +#define DFSDM_FLTISR_RCIP ((uint32_t)0x00004000) + +#define DFSDM_FLTISR_CKABF ((uint32_t)0x00030000) +#define DFSDM_FLTISR_CKABF_0 ((uint32_t)0x00010000) +#define DFSDM_FLTISR_CKABF_1 ((uint32_t)0x00020000) + +#define DFSDM_FLTISR_SCDF ((uint32_t)0x03000000) +#define DFSDM_FLTISR_SCDF_0 ((uint32_t)0x01000000) +#define DFSDM_FLTISR_SCDF_1 ((uint32_t)0x02000000) + +/******************* Bit definition for DFSDM_FLTICR register *******************/ +#define DFSDM_FLTICR_CLRJOVRF ((uint32_t)0x00000004) +#define DFSDM_FLTICR_CLRROVRF ((uint32_t)0x00000008) + +#define DFSDM_FLTICR_CLRCKABF ((uint32_t)0x00030000) +#define DFSDM_FLTICR_CLRCKABF_0 ((uint32_t)0x00010000) +#define DFSDM_FLTICR_CLRCKABF_1 ((uint32_t)0x00020000) + +#define DFSDM_FLTICR_CLRSCDF ((uint32_t)0x03000000) +#define DFSDM_FLTICR_CLRSCDF_0 ((uint32_t)0x01000000) +#define DFSDM_FLTICR_CLRSCDF_1 ((uint32_t)0x02000000) + +/******************* Bit definition for DFSDM_FLTJCHGR register *******************/ +#define DFSDM_FLTJCHGR_JCHG ((uint32_t)0x00000003) + +/******************* Bit definition for DFSDM_FLTFCR3 register *******************/ +#define DFSDM_FLTFCR3_IOSR ((uint32_t)0x000000FF) +#define DFSDM_FLTFCR3_IOSR_0 ((uint32_t)0x00000001) +#define DFSDM_FLTFCR3_IOSR_1 ((uint32_t)0x00000002) +#define DFSDM_FLTFCR3_IOSR_2 ((uint32_t)0x00000004) +#define DFSDM_FLTFCR3_IOSR_3 ((uint32_t)0x00000008) +#define DFSDM_FLTFCR3_IOSR_4 ((uint32_t)0x00000010) +#define DFSDM_FLTFCR3_IOSR_5 ((uint32_t)0x00000020) +#define DFSDM_FLTFCR3_IOSR_6 ((uint32_t)0x00000040) +#define DFSDM_FLTFCR3_IOSR_7 ((uint32_t)0x00000080) + + +#define DFSDM_FLTFCR3_FOSR ((uint32_t)0x03FF0000) +#define DFSDM_FLTFCR3_FOSR_0 ((uint32_t)0x00010000) +#define DFSDM_FLTFCR3_FOSR_1 ((uint32_t)0x00020000) +#define DFSDM_FLTFCR3_FOSR_2 ((uint32_t)0x00040000) +#define DFSDM_FLTFCR3_FOSR_3 ((uint32_t)0x00080000) +#define DFSDM_FLTFCR3_FOSR_4 ((uint32_t)0x00100000) +#define DFSDM_FLTFCR3_FOSR_5 ((uint32_t)0x00200000) +#define DFSDM_FLTFCR3_FOSR_6 ((uint32_t)0x00400000) +#define DFSDM_FLTFCR3_FOSR_7 ((uint32_t)0x00800000) +#define DFSDM_FLTFCR3_FOSR_8 ((uint32_t)0x01000000) +#define DFSDM_FLTFCR3_FOSR_9 ((uint32_t)0x03FF0000) + +#define DFSDM_FLTFCR3_FORD ((uint32_t)0xE0000000) +#define DFSDM_FLTFCR3_FORD_0 ((uint32_t)0x20000000) +#define DFSDM_FLTFCR3_FORD_1 ((uint32_t)0x40000000) +#define DFSDM_FLTFCR3_FORD_2 ((uint32_t)0x80000000) + +/******************* Bit definition for DFSDM_FLTJDATAR register *******************/ +#define DFSDM_FLTJDATAR_JDATACH ((uint32_t)0x00000001) +#define DFSDM_FLTJDATAR_JDATA ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_FLTRDATAR register *******************/ +#define DFSDM_FLTRDATAR_RDATACH ((uint32_t)0x00000001) +#define DFSDM_FLTRDATAR_RPEND ((uint32_t)0x00000010) +#define DFSDM_FLTRDATAR_RDATA ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_FLTAWHTR register *******************/ +#define DFSDM_FLTAWHTR_BKAWH ((uint32_t)0x0000000F) +#define DFSDM_FLTAWHTR_BKAWH_0 ((uint32_t)0x00000001) +#define DFSDM_FLTAWHTR_BKAWH_1 ((uint32_t)0x00000002) +#define DFSDM_FLTAWHTR_BKAWH_2 ((uint32_t)0x00000004) +#define DFSDM_FLTAWHTR_BKAWH_3 ((uint32_t)0x00000008) + +#define DFSDM_FLTAWHTR_AWHT ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_FLTAWLTR register *******************/ +#define DFSDM_FLTAWLTR_BKAWL ((uint32_t)0x0000000F) +#define DFSDM_FLTAWLTR_BKAWL_0 ((uint32_t)0x00000001) +#define DFSDM_FLTAWLTR_BKAWL_1 ((uint32_t)0x00000002) +#define DFSDM_FLTAWLTR_BKAWL_2 ((uint32_t)0x00000004) +#define DFSDM_FLTAWLTR_BKAWL_3 ((uint32_t)0x00000008) + +#define DFSDM_FLTAWLTR_AWLT ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_FLTAWSR register *******************/ +#define DFSDM_FLTAWSR_AWLTF ((uint32_t)0x00000003) +#define DFSDM_FLTAWSR_AWHTF ((uint32_t)0x00000300) + +/******************* Bit definition for DFSDM_FLTAWCFR register *******************/ +#define DFSDM_FLTAWCFR_CLRAWLTF ((uint32_t)0x00000003) +#define DFSDM_FLTAWCFR_CLRAWLTF_0 ((uint32_t)0x00000001) +#define DFSDM_FLTAWCFR_CLRAWLTF_1 ((uint32_t)0x00000002) + +#define DFSDM_FLTAWCFR_CLRAWHTF ((uint32_t)0x00000300) +#define DFSDM_FLTAWCFR_CLRAWHTF_0 ((uint32_t)0x00000100) +#define DFSDM_FLTAWCFR_CLRAWHTF_1 ((uint32_t)0x00000200) + +/******************* Bit definition for DFSDM_FLTEXMAX register *******************/ +#define DFSDM_FLTEXMAX_EXMAXCH ((uint32_t)0x00000001) +#define DFSDM_FLTEXMAX_EXMAX ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_FLTEXMIN register *******************/ +#define DFSDM_FLTEXMIN_EXMINCH ((uint32_t)0x00000001) +#define DFSDM_FLTEXMIN_EXMIN ((uint32_t)0xFFFFFF00) + +/******************* Bit definition for DFSDM_FLTCNVTIMR register *******************/ +#define DFSDM_FLTCNVTIMR_CNVCNT ((uint32_t)0xFFFFFF00) + +/******************************************************************************/ +/* LTDC */ +/******************************************************************************/ +/******************* Bit definition for LTDC_SSCR register *******************/ +#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) +#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) + +/******************* Bit definition for LTDC_BPCR register *******************/ +#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) +#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) + +/******************* Bit definition for LTDC_AWCR register *******************/ +#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) +#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) + +/******************* Bit definition for LTDC_TWCR register *******************/ +#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) +#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) + +/******************* Bit definition for LTDC_GCR register *******************/ +#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) + +#define LTDC_GCR_DBW ((uint32_t)0x00000070) +#define LTDC_GCR_DBW_0 ((uint32_t)0x00000010) +#define LTDC_GCR_DBW_1 ((uint32_t)0x00000020) +#define LTDC_GCR_DBW_2 ((uint32_t)0x00000040) + +#define LTDC_GCR_DGW ((uint32_t)0x00000700) +#define LTDC_GCR_DGW_0 ((uint32_t)0x00000100) +#define LTDC_GCR_DGW_1 ((uint32_t)0x00000200) +#define LTDC_GCR_DGW_2 ((uint32_t)0x00000400) + +#define LTDC_GCR_DRW ((uint32_t)0x00007000) +#define LTDC_GCR_DRW_0 ((uint32_t)0x00001000) +#define LTDC_GCR_DRW_1 ((uint32_t)0x00002000) +#define LTDC_GCR_DRW_2 ((uint32_t)0x00004000) + +#define LTDC_GCR_DEN ((uint32_t)0x00010000) + +#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) +#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) +#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) +#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) + +/******************* Bit definition for LTDC_SRCR register *******************/ +#define LTDC_SRCR_IMR ((uint32_t)0x00000001) +#define LTDC_SRCR_VBR ((uint32_t)0x00000002) + +/******************* Bit definition for LTDC_BCCR register *******************/ +#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) +#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) +#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) + +/******************* Bit definition for LTDC_IER register *******************/ +#define LTDC_IER_LIE ((uint32_t)0x00000001) +#define LTDC_IER_FUIE ((uint32_t)0x00000002) + +#define LTDC_IER_RRIE ((uint32_t)0x00000008) + +/******************* Bit definition for LTDC_ISR register *******************/ +#define LTDC_ISR_LIF ((uint32_t)0x00000001) +#define LTDC_ISR_FUIF ((uint32_t)0x00000002) + +#define LTDC_ISR_RRIF ((uint32_t)0x00000008) + +/******************* Bit definition for LTDC_ICR register *******************/ +#define LTDC_ICR_CLIF ((uint32_t)0x00000001) +#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) + +#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) + +/******************* Bit definition for LTDC_LIPCR register *******************/ +#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) + +/******************* Bit definition for LTDC_CPSR register *******************/ +#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) +#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) + +/******************* Bit definition for LTDC_CDSR register *******************/ +#define LTDC_CDSR_VDES ((uint32_t)0x00000001) +#define LTDC_CDSR_HDES ((uint32_t)0x00000002) +#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) +#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) + +/******************* Bit definition for LTDC_CR register *******************/ +#define LTDC_CR_LEN ((uint32_t)0x00000001) +#define LTDC_CR_COLKEN ((uint32_t)0x00000002) + +#define LTDC_CR_CLUTEN ((uint32_t)0x00000010) + +/******************* Bit definition for LTDC_WHPCR register *******************/ +#define LTDC_WHPCR_WHSTPOS ((uint32_t)0x00000FFF) +#define LTDC_WHPCR_WHSPPOS ((uint32_t)0x0FFF0000) + +/******************* Bit definition for LTDC_WVPCR register *******************/ +#define LTDC_WVPCR_WVSTPOS ((uint32_t)0x000007FF) +#define LTDC_WVPCR_WVSPPOS ((uint32_t)0x07FF0000) + +/******************* Bit definition for LTDC_CKCR register *******************/ +#define LTDC_CKCR_CKBLUE ((uint32_t)0x000000FF) +#define LTDC_CKCR_CKGREEN ((uint32_t)0x0000FF00) +#define LTDC_CKCR_CKRED ((uint32_t)0x00FF0000) + +/******************* Bit definition for LTDC_PFCR register *******************/ +#define LTDC_PFCR_PF ((uint32_t)0x00000007) +#define LTDC_PFCR_PF_0 ((uint32_t)0x00000001) +#define LTDC_PFCR_PF_1 ((uint32_t)0x00000002) +#define LTDC_PFCR_PF_2 ((uint32_t)0x00000004) + +#define LTDC_PFCR_PF_ARGB8888 ((uint32_t)0x00000000) +#define LTDC_PFCR_PF_RGB888 ((uint32_t)0x00000001) +#define LTDC_PFCR_PF_RGB565 ((uint32_t)0x00000002) +#define LTDC_PFCR_PF_ARGB1555 ((uint32_t)0x00000003) +#define LTDC_PFCR_PF_ARGB4444 ((uint32_t)0x00000004) +#define LTDC_PFCR_PF_L8 ((uint32_t)0x00000005) +#define LTDC_PFCR_PF_AL44 ((uint32_t)0x00000006) +#define LTDC_PFCR_PF_AL88 ((uint32_t)0x00000007) + +/******************* Bit definition for LTDC_CACR register *******************/ +#define LTDC_CACR_CONSTA ((uint32_t)0x000000FF) + +/******************* Bit definition for LTDC_DCCR register *******************/ +#define LTDC_DCCR_DCBLUE ((uint32_t)0x000000FF) +#define LTDC_DCCR_DCGREEN ((uint32_t)0x0000FF00) +#define LTDC_DCCR_DCRED ((uint32_t)0x00FF0000) +#define LTDC_DCCR_DCALPHA ((uint32_t)0xFF000000) + +/******************* Bit definition for LTDC_BFCR register *******************/ +#define LTDC_BFCR_BF2 ((uint32_t)0x00000007) +#define LTDC_BFCR_BF2_0 ((uint32_t)0x00000001) +#define LTDC_BFCR_BF2_1 ((uint32_t)0x00000002) +#define LTDC_BFCR_BF2_2 ((uint32_t)0x00000004) + +#define LTDC_BFCR_BF1 ((uint32_t)0x00000700) +#define LTDC_BFCR_BF1_0 ((uint32_t)0x00000100) +#define LTDC_BFCR_BF1_1 ((uint32_t)0x00000200) +#define LTDC_BFCR_BF1_2 ((uint32_t)0x00000400) + +/******************* Bit definition for LTDC_CFBAR register *******************/ +#define LTDC_CFBAR_CFBADD ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for LTDC_CFBLR register *******************/ +#define LTDC_CFBLR_CFBLL ((uint32_t)0x00001FFF) +#define LTDC_CFBLR_CFBP ((uint32_t)0x1FFF0000) + +/******************* Bit definition for LTDC_CFBLNR register *******************/ +#define LTDC_CFBLNR_CFBLNBR ((uint32_t)0x000007FF) + +/******************* Bit definition for LTDC_CLUTWR register *******************/ +#define LTDC_CLUTWR_BLUE ((uint32_t)0x000000FF) +#define LTDC_CLUTWR_GREEN ((uint32_t)0x0000FF00) +#define LTDC_CLUTWR_RED ((uint32_t)0x00FF0000) +#define LTDC_CLUTWR_CLUTADD ((uint32_t)0xFF000000) + +/******************************************************************************/ +/* GPHA */ +/******************************************************************************/ +/******************* Bit definition for GPHA_CTLR register *******************/ +#define GPHA_CTLR_START ((uint32_t)0x00000001) +#define GPHA_CTLR_SUSP ((uint32_t)0x00000002) +#define GPHA_CTLR_ABORT ((uint32_t)0x00000004) + +#define GPHA_CTLR_TCIE ((uint32_t)0x00000200) +#define GPHA_CTLR_TWIE ((uint32_t)0x00000400) +#define GPHA_CTLR_CAEIE ((uint32_t)0x00000800) +#define GPHA_CTLR_CTCIE ((uint32_t)0x00001000) +#define GPHA_CTLR_CEIE ((uint32_t)0x00002000) + +#define GPHA_CTLR_MODE ((uint32_t)0x00070000) +#define GPHA_CTLR_MODE_0 ((uint32_t)0x00010000) +#define GPHA_CTLR_MODE_1 ((uint32_t)0x00020000) +#define GPHA_CTLR_MODE_2 ((uint32_t)0x00040000) + +/******************* Bit definition for GPHA_ISR register *******************/ +#define GPHA_ISR_TCIF ((uint32_t)0x00000002) +#define GPHA_ISR_TWIF ((uint32_t)0x00000004) +#define GPHA_ISR_CAEIF ((uint32_t)0x00000008) +#define GPHA_ISR_CTCIF ((uint32_t)0x00000010) +#define GPHA_ISR_CEIF ((uint32_t)0x00000020) + +/******************* Bit definition for GPHA_IFCR register *******************/ +#define GPHA_IFCR_CTCIF ((uint32_t)0x00000002) +#define GPHA_IFCR_CTWIF ((uint32_t)0x00000004) +#define GPHA_IFCR_CAECIF ((uint32_t)0x00000008) +#define GPHA_IFCR_CCTCIF ((uint32_t)0x00000010) +#define GPHA_IFCR_CCEIF ((uint32_t)0x00000020) + +/******************* Bit definition for GPHA_FGMAR register *******************/ +#define GPHA_FGMAR_MA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for GPHA_FGOR register *******************/ +#define GPHA_FGOR_LO ((uint32_t)0x00003FFF) + +/******************* Bit definition for GPHA_BGMAR register *******************/ +#define GPHA_BGMAR_MA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for GPHA_BGOR register *******************/ +#define GPHA_BGOR_LO ((uint32_t)0x00003FFF) + +/******************* Bit definition for GPHA_FGPFCCR register *******************/ +#define GPHA_FGPFCCR_CM ((uint32_t)0x0000000F) +#define GPHA_FGPFCCR_CM_0 ((uint32_t)0x00000001) +#define GPHA_FGPFCCR_CM_1 ((uint32_t)0x00000002) +#define GPHA_FGPFCCR_CM_2 ((uint32_t)0x00000004) +#define GPHA_FGPFCCR_CM_3 ((uint32_t)0x00000008) + +#define GPHA_FGPFCCR_CM_ARGB8888 ((uint32_t)0x00000000) +#define GPHA_FGPFCCR_CM_RGB888 ((uint32_t)0x00000001) +#define GPHA_FGPFCCR_CM_RGB565 ((uint32_t)0x00000002) +#define GPHA_FGPFCCR_CM_ARGB1555 ((uint32_t)0x00000003) +#define GPHA_FGPFCCR_CM_ARGB4444 ((uint32_t)0x00000004) +#define GPHA_FGPFCCR_CM_L8 ((uint32_t)0x00000005) +#define GPHA_FGPFCCR_CM_AL44 ((uint32_t)0x00000006) +#define GPHA_FGPFCCR_CM_AL88 ((uint32_t)0x00000007) +#define GPHA_FGPFCCR_CM_L4 ((uint32_t)0x00000008) +#define GPHA_FGPFCCR_CM_A8 ((uint32_t)0x00000009) +#define GPHA_FGPFCCR_CM_A4 ((uint32_t)0x0000000A) +#define GPHA_FGPFCCR_CM_YcbCr ((uint32_t)0x0000000B) + +#define GPHA_FGPFCCR_CCM ((uint32_t)0x00000010) +#define GPHA_FGPFCCR_START ((uint32_t)0x00000020) + +#define GPHA_FGPFCCR_CS ((uint32_t)0x0000FF00) + +#define GPHA_FGPFCCR_AM ((uint32_t)0x00030000) +#define GPHA_FGPFCCR_AM_0 ((uint32_t)0x00010000) +#define GPHA_FGPFCCR_AM_1 ((uint32_t)0x00020000) + +#define GPHA_FGPFCCR_CSS ((uint32_t)0x000C0000) +#define GPHA_FGPFCCR_CSS_0 ((uint32_t)0x00040000) +#define GPHA_FGPFCCR_CSS_1 ((uint32_t)0x00080000) + +#define GPHA_FGPFCCR_AI ((uint32_t)0x00100000) +#define GPHA_FGPFCCR_RBS ((uint32_t)0x00200000) + +#define GPHA_FGPFCCR_ALPHA ((uint32_t)0xFF000000) + +/******************* Bit definition for GPHA_FGCOLR register *******************/ +#define GPHA_FGCOLR_BLUE ((uint32_t)0x000000FF) +#define GPHA_FGCOLR_GREEN ((uint32_t)0x0000FF00) +#define GPHA_FGCOLR_RED ((uint32_t)0x00FF0000) + +/******************* Bit definition for GPHA_BGPFCCR register *******************/ +#define GPHA_BGPFCCR_CM ((uint32_t)0x0000000F) +#define GPHA_BGPFCCR_CM_0 ((uint32_t)0x00000001) +#define GPHA_BGPFCCR_CM_1 ((uint32_t)0x00000002) +#define GPHA_BGPFCCR_CM_2 ((uint32_t)0x00000004) +#define GPHA_BGPFCCR_CM_3 ((uint32_t)0x00000008) + +#define GPHA_BGPFCCR_CM_ARGB8888 ((uint32_t)0x00000000) +#define GPHA_BGPFCCR_CM_RGB888 ((uint32_t)0x00000001) +#define GPHA_BGPFCCR_CM_RGB565 ((uint32_t)0x00000002) +#define GPHA_BGPFCCR_CM_ARGB1555 ((uint32_t)0x00000003) +#define GPHA_BGPFCCR_CM_ARGB4444 ((uint32_t)0x00000004) +#define GPHA_BGPFCCR_CM_L8 ((uint32_t)0x00000005) +#define GPHA_BGPFCCR_CM_AL44 ((uint32_t)0x00000006) +#define GPHA_BGPFCCR_CM_AL88 ((uint32_t)0x00000007) +#define GPHA_BGPFCCR_CM_L4 ((uint32_t)0x00000008) +#define GPHA_BGPFCCR_CM_A8 ((uint32_t)0x00000009) +#define GPHA_BGPFCCR_CM_A4 ((uint32_t)0x0000000A) + +#define GPHA_BGPFCCR_CCM ((uint32_t)0x00000010) +#define GPHA_BGPFCCR_START ((uint32_t)0x00000020) + +#define GPHA_BGPFCCR_CS ((uint32_t)0x0000FF00) + +#define GPHA_BGPFCCR_AM ((uint32_t)0x00030000) +#define GPHA_BGPFCCR_AM_0 ((uint32_t)0x00010000) +#define GPHA_BGPFCCR_AM_1 ((uint32_t)0x00020000) + +#define GPHA_BGPFCCR_AI ((uint32_t)0x00100000) +#define GPHA_BGPFCCR_RBS ((uint32_t)0x00200000) + +#define GPHA_BGPFCCR_ALPHA ((uint32_t)0xFF000000) + +/******************* Bit definition for GPHA_BGCOLR register *******************/ +#define GPHA_BGCOLR_BLUE ((uint32_t)0x000000FF) +#define GPHA_BGCOLR_GREEN ((uint32_t)0x0000FF00) +#define GPHA_BGCOLR_RED ((uint32_t)0x00FF0000) + +/******************* Bit definition for GPHA_FGCMAR register *******************/ +#define GPHA_FGCMAR_MA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for GPHA_BGCMAR register *******************/ +#define GPHA_BGCMAR_MA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for GPHA_OPFCCR register *******************/ +#define GPHA_OPFCCR_CM ((uint32_t)0x00000007) +#define GPHA_OPFCCR_CM_0 ((uint32_t)0x00000001) +#define GPHA_OPFCCR_CM_1 ((uint32_t)0x00000002) +#define GPHA_OPFCCR_CM_2 ((uint32_t)0x00000004) + +#define GPHA_OPFCCR_CM_ARGB8888 ((uint32_t)0x00000000) +#define GPHA_OPFCCR_CM_RGB888 ((uint32_t)0x00000001) +#define GPHA_OPFCCR_CM_RGB565 ((uint32_t)0x00000002) +#define GPHA_OPFCCR_CM_ARGB1555 ((uint32_t)0x00000003) +#define GPHA_OPFCCR_CM_ARGB4444 ((uint32_t)0x00000004) + +#define GPHA_OPFCCR_AI ((uint32_t)0x00100000) +#define GPHA_OPFCCR_RBS ((uint32_t)0x00200000) + +/******************* Bit definition for GPHA_OCOLR register *******************/ +#define GPHA_OCOLR_BLUE ((uint32_t)0x000000FF) +#define GPHA_OCOLR_GREEN ((uint32_t)0x0000FF00) +#define GPHA_OCOLR_RED ((uint32_t)0x00FF0000) +#define GPHA_OCOLR_ALPHA ((uint32_t)0xFF000000) + +/******************* Bit definition for GPHA_OMAR register *******************/ +#define GPHA_OMAR_MA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for GPHA_OOR register *******************/ +#define GPHA_OOR_LO ((uint32_t)0x00003FFF) + +/******************* Bit definition for GPHA_NLR register *******************/ +#define GPHA_NLR_NL ((uint32_t)0x0000FFFF) +#define GPHA_NLR_PL ((uint32_t)0x3FFF0000) + +/******************* Bit definition for GPHA_LWR register *******************/ +#define GPHA_LWR_LW ((uint32_t)0x0000FFFF) + +/******************* Bit definition for GPHA_AMTCR register *******************/ +#define GPHA_AMTCR_EN ((uint32_t)0x00000001) +#define GPHA_AMTCR_DT ((uint32_t)0x0000FF00) + +/******************* Bit definition for GPHA_FGCWRS register *******************/ +#define GPHA_FGCWRS_FG_CLUT_INDEX ((uint32_t)0x000000FF) +#define GPHA_FGCWRS_FG_CLUT_EN ((uint32_t)0x00000100) + +/******************* Bit definition for GPHA_FGCDAT register *******************/ +#define GPHA_FGCDAT_FG_CLUT_DATA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for GPHA_BGCWRS register *******************/ +#define GPHA_BGCWRS_BG_CLUT_INDEX ((uint32_t)0x000000FF) +#define GPHA_BGCWRS_BG_CLUT_EN ((uint32_t)0x00000100) + +/******************* Bit definition for GPHA_BGCDAT register *******************/ +#define GPHA_BGCDAT_BG_CLUT_DATA ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* QSPI */ +/******************************************************************************/ +/******************* Bit definition for QSPI_CR register *******************/ +#define QSPI_CR_EN ((uint32_t)0x00000001) +#define QSPI_CR_ABORT ((uint32_t)0x00000002) +#define QSPI_CR_DMAEN ((uint32_t)0x00000004) +#define QSPI_CR_TCEN ((uint32_t)0x00000008) + +#define QSPI_CR_START ((uint32_t)0x00000020) +#define QSPI_CR_DFM ((uint32_t)0x00000040) +#define QSPI_CR_FSEL ((uint32_t)0x00000080) + +#define QSPI_CR_FTHRES ((uint32_t)0x00001F00) +#define QSPI_CR_FTHRES_0 ((uint32_t)0x00000100) +#define QSPI_CR_FTHRES_1 ((uint32_t)0x00000200) +#define QSPI_CR_FTHRES_2 ((uint32_t)0x00000400) +#define QSPI_CR_FTHRES_3 ((uint32_t)0x00000800) +#define QSPI_CR_FTHRES_4 ((uint32_t)0x00001000) + +#define QSPI_CR_TEIE ((uint32_t)0x00010000) +#define QSPI_CR_TCIE ((uint32_t)0x00020000) +#define QSPI_CR_FTIE ((uint32_t)0x00040000) +#define QSPI_CR_SMIE ((uint32_t)0x00080000) +#define QSPI_CR_TOIE ((uint32_t)0x00100000) +#define QSPI_CR_APMS ((uint32_t)0x00400000) +#define QSPI_CR_PMM ((uint32_t)0x00800000) + +#define QSPI_CR_PRESCALER ((uint32_t)0xFF000000) +#define QSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) +#define QSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) +#define QSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) +#define QSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) +#define QSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) +#define QSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) +#define QSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) +#define QSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) + +/******************* Bit definition for QSPI_DCR register *******************/ +#define QSPI_DCR_CKMODE ((uint32_t)0x00000001) + +#define QSPI_DCR_CSHT ((uint32_t)0x00000700) +#define QSPI_DCR_CSHT_0 ((uint32_t)0x00000100) +#define QSPI_DCR_CSHT_1 ((uint32_t)0x00000200) +#define QSPI_DCR_CSHT_2 ((uint32_t)0x00000400) + +#define QSPI_DCR_FSIZE ((uint32_t)0x001F0000) +#define QSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) +#define QSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) +#define QSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) +#define QSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) +#define QSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) + +/******************* Bit definition for QSPI_SR register *******************/ +#define QSPI_SR_TEF ((uint32_t)0x00000001) +#define QSPI_SR_TCF ((uint32_t)0x00000002) +#define QSPI_SR_FTF ((uint32_t)0x00000004) +#define QSPI_SR_SMF ((uint32_t)0x00000008) +#define QSPI_SR_TOF ((uint32_t)0x00000010) +#define QSPI_SR_BUSY ((uint32_t)0x00000020) + +#define QSPI_SR_FLEVEL ((uint32_t)0x00003F00) +#define QSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) +#define QSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) +#define QSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) +#define QSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) +#define QSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) +#define QSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) + +#define QSPI_SR_IDLEF ((uint32_t)0x00010000) + +/******************* Bit definition for QSPI_FCR register *******************/ +#define QSPI_FCR_CTEF ((uint32_t)0x00000001) +#define QSPI_FCR_CTCF ((uint32_t)0x00000002) +#define QSPI_FCR_CSMF ((uint32_t)0x00000008) +#define QSPI_FCR_CTOF ((uint32_t)0x00000010) + +/******************* Bit definition for QSPI_DLR register *******************/ +#define QSPI_DLR_DL ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for QSPI_CCR register *******************/ +#define QSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) +#define QSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) +#define QSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) +#define QSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) +#define QSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) +#define QSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) +#define QSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) +#define QSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) +#define QSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) + +#define QSPI_CCR_IMODE ((uint32_t)0x00000300) +#define QSPI_CCR_IMODE_0 ((uint32_t)0x00000100) +#define QSPI_CCR_IMODE_1 ((uint32_t)0x00000200) + +#define QSPI_CCR_ADMODE ((uint32_t)0x00000C00) +#define QSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) +#define QSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) + +#define QSPI_CCR_ADSIZE ((uint32_t)0x00003000) +#define QSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) +#define QSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) + +#define QSPI_CCR_ABMODE ((uint32_t)0x0000C000) +#define QSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) +#define QSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) + +#define QSPI_CCR_ABSIZE ((uint32_t)0x00030000) +#define QSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) +#define QSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) + +#define QSPI_CCR_DCYC ((uint32_t)0x007C0000) +#define QSPI_CCR_DCYC_0 ((uint32_t)0x00040000) +#define QSPI_CCR_DCYC_1 ((uint32_t)0x00080000) +#define QSPI_CCR_DCYC_2 ((uint32_t)0x00100000) +#define QSPI_CCR_DCYC_3 ((uint32_t)0x00200000) +#define QSPI_CCR_DCYC_4 ((uint32_t)0x00400000) + +#define QSPI_CCR_DMODE ((uint32_t)0x03000000) +#define QSPI_CCR_DMODE_0 ((uint32_t)0x01000000) +#define QSPI_CCR_DMODE_1 ((uint32_t)0x02000000) + +#define QSPI_CCR_FMODE ((uint32_t)0x0C000000) +#define QSPI_CCR_FMODE_0 ((uint32_t)0x04000000) +#define QSPI_CCR_FMODE_1 ((uint32_t)0x08000000) + +#define QSPI_CCR_SIOO ((uint32_t)0x10000000) + +/******************* Bit definition for QSPI_AR register *******************/ +#define QSPI_AR_ADDR ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for QSPI_ABR register *******************/ +#define QSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for QSPI_DR register *******************/ +#define QSPI_DR_DATA ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for QSPI_PSMKR register *******************/ +#define QSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for QSPI_PSMAR register *******************/ +#define QSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for QSPI_PIR register *******************/ +#define QSPI_PIR_INTERVAL ((uint16_t)0xFFFF) + +/******************* Bit definition for QSPI_LPIR register *******************/ +#define QSPI_LPIR_TIMEOUT ((uint16_t)0xFFFF) + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* ch32h417_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32h417_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +/* CTLR1_CLEAR_Mask -> ADC_CTLR1_CLEAR_Mask */ +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + + +/* ch32h417_can.c ------------------------------------------------------------*/ +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + + +/* ch32v417_dac.c ------------------------------------------------------------*/ + +/* CTLR register Mask */ +#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTR masks */ +#define DUAL_SWTR_SET ((uint32_t)0x00000003) +#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32h417_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFE000F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32h417_flash.c ----------------------------------------------------------*/ + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_BER ((uint32_t)0x00040000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x0A000000) +#define ProgramTimeout ((uint32_t)0x0A000000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd_Dual (FLASH_BASE + 0xF0000) +#define ValidAddrEnd_Signal (FLASH_BASE + 0x78000) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_4KB 0x1000 +#define Size_8KB 0x2000 +#define Size_32KB 0x8000 +#define Size_64KB 0x10000 + + +/* ch32h417_fmc.c -----------------------------------------------------------*/ + +/* FMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) + + +/* ch32h417_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +/* CTLR1_CLEAR_Mask -> I2C_CTLR1_CLEAR_Mask */ +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +/* FLAG_Mask -> I2C_FLAG_Mask*/ +#define I2C_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/* ch32h417_pwr.c ------------------------------------------------------------*/ + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFE) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* ch32h417_rcc.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR0 register bit mask */ +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +/* FLAG_Mask -> RCC_FLAG_Mask */ +#define RCC_FLAG_Mask ((uint8_t)0x1F) + +#ifndef __ASSEMBLER__ +static __I uint8_t PLLMULTable[32] = {4,6,7,8,17,9,19,10,21,11,23,12,25,13,14,15,16,17,18,19,20,22,24,26,28,30,32,34,36,38,40,59}; +static __I uint8_t HBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t SERDESPLLMULTable[16] = {25, 28, 30, 32, 35, 38, 40, 45, 50, 56, 60, 64, 70, 76, 80, 90}; +static __I uint8_t FPRETable[4] = {0, 1, 2, 2}; +static __I uint8_t PPRE2Table[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +static __I uint8_t ADCPRETable[4] = {2, 4, 6, 8}; +#endif + + +/* ch32v20x_rtc.c ------------------------------------------------------------*/ + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + + + +/* ch32v00x_sdio.c -----------------------------------------------------------*/ + +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32h417_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +/* CTLR1_CLEAR_Mask -> USART_CTLR1_CLEAR_Mask */ +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0x29F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + + +/* ch32h417_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) +#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) +#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) +#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) +#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) +#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) +#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) +#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint16_t)0x0001) +#define ADC_FLAG_EOC ((uint16_t)0x0002) +#define ADC_FLAG_JEOC ((uint16_t)0x0004) +#define ADC_FLAG_JSTRT ((uint16_t)0x0008) +#define ADC_FLAG_STRT ((uint16_t)0x0010) +#define ADC_FLAG_RST ((uint16_t)0x8000) + +/* ADC_SMP_CFG_MODE_definition */ +#define ADC_SMP_CFG_MODE0 ((uint8_t)0x00) +#define ADC_SMP_CFG_MODE1 ((uint8_t)0x01) + +/* ADC_CalibrationVoltage_Mode_definition */ +#define ADC_CalibrationVoltage_Mode0 ((uint32_t)0x00000000) +#define ADC_CalibrationVoltage_Mode1 ((uint32_t)0x00000010) +#define ADC_CalibrationVoltage_Mode2 ((uint32_t)0x00000020) +#define ADC_CalibrationVoltage_Mode3 ((uint32_t)0x00000030) + + +/* ch32h417_dbgmcu.h ---------------------------------------------------------*/ + +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00100000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x00800000) +#define DBGMCU_LPTIM1_STOP ((uint32_t)0x01000000) +#define DBGMCU_LPTIM2_STOP ((uint32_t)0x02000000) +#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x04000000) +#define DBGMCU_I2C4_SMBUS_TIMEOUT ((uint32_t)0x08000000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x10000000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x20000000) +#define DBGMCU_CAN3_STOP ((uint32_t)0x40000000) + +/* ch32h417_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define DMA_PeripheralDataSize_256 ((uint32_t)0x00000300) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define DMA_MemoryDataSize_256 ((uint32_t)0x00000C00) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +#define DMA2_IT_GL1 ((uint32_t)0x00000001) +#define DMA2_IT_TC1 ((uint32_t)0x00000002) +#define DMA2_IT_HT1 ((uint32_t)0x00000004) +#define DMA2_IT_TE1 ((uint32_t)0x00000008) +#define DMA2_IT_GL2 ((uint32_t)0x00000010) +#define DMA2_IT_TC2 ((uint32_t)0x00000020) +#define DMA2_IT_HT2 ((uint32_t)0x00000040) +#define DMA2_IT_TE2 ((uint32_t)0x00000080) +#define DMA2_IT_GL3 ((uint32_t)0x00000100) +#define DMA2_IT_TC3 ((uint32_t)0x00000200) +#define DMA2_IT_HT3 ((uint32_t)0x00000400) +#define DMA2_IT_TE3 ((uint32_t)0x00000800) +#define DMA2_IT_GL4 ((uint32_t)0x00001000) +#define DMA2_IT_TC4 ((uint32_t)0x00002000) +#define DMA2_IT_HT4 ((uint32_t)0x00004000) +#define DMA2_IT_TE4 ((uint32_t)0x00008000) +#define DMA2_IT_GL5 ((uint32_t)0x00010000) +#define DMA2_IT_TC5 ((uint32_t)0x00020000) +#define DMA2_IT_HT5 ((uint32_t)0x00040000) +#define DMA2_IT_TE5 ((uint32_t)0x00080000) +#define DMA2_IT_GL6 ((uint32_t)0x00100000) +#define DMA2_IT_TC6 ((uint32_t)0x00200000) +#define DMA2_IT_HT6 ((uint32_t)0x00400000) +#define DMA2_IT_TE6 ((uint32_t)0x00800000) +#define DMA2_IT_GL7 ((uint32_t)0x01000000) +#define DMA2_IT_TC7 ((uint32_t)0x02000000) +#define DMA2_IT_HT7 ((uint32_t)0x04000000) +#define DMA2_IT_TE7 ((uint32_t)0x08000000) +#define DMA2_IT_GL8 ((uint32_t)0x10000000) +#define DMA2_IT_TC8 ((uint32_t)0x20000000) +#define DMA2_IT_HT8 ((uint32_t)0x40000000) +#define DMA2_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA2_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA2_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA2_FLAG_TE8 ((uint32_t)0x80000000) + +/* DMA_MuxChannel_definition */ +#define DMA_MuxChannel1 ((uint8_t)0x00) +#define DMA_MuxChannel2 ((uint8_t)0x01) +#define DMA_MuxChannel3 ((uint8_t)0x02) +#define DMA_MuxChannel4 ((uint8_t)0x03) +#define DMA_MuxChannel5 ((uint8_t)0x04) +#define DMA_MuxChannel6 ((uint8_t)0x05) +#define DMA_MuxChannel7 ((uint8_t)0x06) +#define DMA_MuxChannel8 ((uint8_t)0x07) +#define DMA_MuxChannel9 ((uint8_t)0x08) +#define DMA_MuxChannel10 ((uint8_t)0x09) +#define DMA_MuxChannel11 ((uint8_t)0x0A) +#define DMA_MuxChannel12 ((uint8_t)0x0B) +#define DMA_MuxChannel13 ((uint8_t)0x0C) +#define DMA_MuxChannel14 ((uint8_t)0x0D) +#define DMA_MuxChannel15 ((uint8_t)0x0E) +#define DMA_MuxChannel16 ((uint8_t)0x0F) + +/* DMA_BufferMode_Memory */ +#define DMA_SingleBufferMode ((uint32_t)0x00000000) +#define DMA_DoubleBufferMode ((uint32_t)0x00008000) + +/* DMA_DoubleBufferMode_Memory */ +#define DMA_DoubleBufferMode_Memory_0 ((uint32_t)0x00000000) +#define DMA_DoubleBufferMode_Memory_1 ((uint32_t)0x00010000) + +/* ch32h417_eth.h ------------------------------------------------------------*/ + +#define PHY_10BASE_T_LINKED 1 +#define PHY_10BASE_T_NOT_LINKED 0 + +#define DMA_TPS_Mask ((uint32_t)0x00700000) +#define DMA_RPS_Mask ((uint32_t)0x000E0000) + +/* ETH delay.Just for Ethernet */ +#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ + +/* definition for Ethernet frame */ +#define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* Timeout threshold of Reading or writing PHY registers */ +#define PHY_READ_TO ((uint32_t)0x004FFFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/* Delay time after reset PHY */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + +/* Delay time after configure PHY */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ +#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR + +/* Bit or field definition for PHY basic control register */ +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ +#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ + + +/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ +#define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) +#define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) + +/* MAC autoNegotiation enable or disable */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) + +/* MAC watchdog enable or disable */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) + +/* Bit description - MAC jabber enable or disable */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) + +/* Value of minimum IFG between frames during transmission */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +/* MAC carrier sense enable or disable */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) + +/* MAC speed */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define ETH_Speed_1000M ((uint32_t)0x00008000) + +/* MAC receive own enable or disable */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) + +/* MAC Loopback mode enable or disable */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) + +/* MAC fullDuplex or halfDuplex */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) + +/* MAC offload checksum enable or disable */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) + +/* MAC transmission retry enable or disable */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) + +/* MAC automatic pad CRC strip enable or disable */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) + +/* MAC deferral check enable or disable */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) + +/* Bit description : MAC receive all frame enable or disable */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) + +/* MAC Pass control frames */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +/* MAC broadcast frames reception */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) + +/* MAC destination address filter */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) + +/* MAC Promiscuous mode enable or disable */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) + +/* MAC multicast frames filter */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) + +/* MAC unicast frames filter */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) + +/* Bit description : MAC zero quanta pause */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) + +/* Field description : MAC pause low threshold */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ + +/* MAC unicast pause frame detect enable or disable*/ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) + +/* MAC receive flow control frame enable or disable */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC transmit flow control enable or disable */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC VLAN tag comparison */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) + +/* MAC flag */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ + +/* MAC interrupt */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ + +/* MAC address */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) + +/* MAC address filter select */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) + +/* MAC address mask */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ + + +/******************************************************************************/ +/* */ +/* MAC Descriptor Register */ +/* */ +/******************************************************************************/ + +/* DMA descriptor segment */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ + +/* DMA descriptor checksum setting */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +/* DMA RX & TX buffer */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ + + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ + +/* DMA drop TCPIP checksum error frame enable or disable */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) + +/* DMA receive store forward enable or disable */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA flush received frame enable or disable */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) + +/* DMA transmit store forward enable or disable */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA transmit threshold control */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +/* DMA forward error frames */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) + +/* DMA forward undersized good frames enable or disable */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) + +/* DMA receive threshold control */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +/* DMA second frame operate enable or disable */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) + +/* Address aligned beats enable or disable */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) + +/* DMA Fixed burst enable or disable */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) + + +/* RX DMA burst length */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + + +/* TX DMA burst length */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +/* DMA arbitration_round robin */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) + +/* DMA interrupt FALG */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_PHYSR ((uint32_t)0x00000800) /* PHY interrupt */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ + +/* DMA interrupt */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_PHYSR ((uint32_t)0x00000800) /* Internal PHY link status change interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ + +/* DMA transmit process */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ + +/* DMA receive Process */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* DMA overflow */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ + + +/********************************************************************************* +* Ethernet PMT defines +**********************************************************************************/ + +/* PMT flag */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ + +/********************************************************************************* +* Ethernet MMC defines +**********************************************************************************/ + +/* MMC TX interrupt flag */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* MMC RX interrupt flag */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + + +/* MMC description */ +#define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ + + +/********************************************************************************* +* Ethernet PTP defines +**********************************************************************************/ + +/* PTP fine update method or coarse Update method */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ + + +/* PTP time stamp control */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ + +/* PTP positive/negative time value */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ + + +/******************************************************************************/ +/* */ +/* PTP Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + + +/******************************************************************************/ +/* */ +/* ETH MAC Register */ +/* */ +/******************************************************************************/ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ + +/* +Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ + +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ + +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +/****************************************************************************** + * + * ETH MMC Register + * + ******************************************************************************/ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ + +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + + +/****************************************************************************** + * + * ETH Precise Clock Protocol Register + * + ******************************************************************************/ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ + +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ + +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ + +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ + +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ + +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ + +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ + +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +/****************************************************************************** + * + * ETH DMA Register + * + ******************************************************************************/ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ + +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ + +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ + +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_PLS ((unsigned int)0x00000800) /* PHY interrupt status*/ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_PLE ((unsigned int)0x00000800) /* PHY interrupt enable*/ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + + +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) + +#define PHY_REG_PAGE0 0x00 +#define PHY_REG_PAGE4 0x04 +#define PHY_REG_PAGE7 0x07 +#define PHY_REG_PAGE17 0x11 +#define PHY_REG_PAGE18 0x12 + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR +#define PHY_PHYIDR1 0x02 /*PHY Identifier Register*/ +#define PHY_PHYIDR2 0x03 /*PHY Identifier Register*/ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ +#define PHY_PAG_SEL 0x1F + +/****************Page 0********************/ +#define PHY_CONTROL1 0x19 +#define PHY_STATUS 0x1A +#define PHY_INTERRUPT_IND 0x1E + +/****************Page 7********************/ +#define PHY_INTERRUPT_MASK 0x13 + + + +#define PHY_SPEED_100M_MODE (1<<3) +#define PHY_SPEED_10M_MODE (1<<2) +#define PHY_FULL_DUPLEX_MODE (1<<1) +#define PHY_HALF_DUPLEX_MODE (1<<1) + + +/* ch32h417_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 Connected to the USBHS wakeup event */ +#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 Connected to the SWPMI wakeup event*/ +#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 Connected to the USBFSOTG Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 Connected to the USBPD Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 Connected to the ETH Wakeup event */ +#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 Connected to the USBSS Wakeup event */ +#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 Connected to the LPTIM1 Wakeup event */ +#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the LPTIM2 Wakeup event */ +#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the I3C Wakeup event */ + + +/* ch32h417_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +}FLASH_Status; + +#endif + +/* Write Protect (dual flash mode - 8K bytes/sector) (single flash mode - 4K bytes/sector)*/ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 */ +#define FLASH_WRProt_Sectors31to119 ((uint32_t)0x80000000) /* Write protection of setor 31 to 119*/ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_USBFSDLEN */ +#define OB_USBFSDL_EN ((uint16_t)0x0040) /* Boot Enable USBFS Download */ +#define OB_USBFSDL_NoEN ((uint16_t)0x0000) /* Boot Disable USBFS Download */ + +/* Option_Bytes_USARTDLEN */ +#define OB_USARTDL_EN ((uint16_t)0x0080) /* Boot Enable USART Download*/ +#define OB_USARTDL_NoEN ((uint16_t)0x0000) /* Boot Disable USART Download */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) +#define FLASH_IT_EOP ((uint32_t)0x00001000) + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) +#define FLASH_FLAG_OPTERR ((uint32_t)0x80000001) +#define FLASH_FLAG_ENHANCE ((uint32_t)0x00000040) +#define FLASH_FLAG_READY ((uint32_t)0x00004000) +#define FLASH_FLAG_LPMODE ((uint32_t)0x00008000) + +/* FLASH_Access_CLK */ +#define FLASH_CLK_HCLKDIV1 ((uint32_t)0x00000000) +#define FLASH_CLK_HCLKDIV2 ((uint32_t)0x00000001) +#define FLASH_CLK_HCLKDIV4 ((uint32_t)0x00000002) +#define FLASH_CLK_HCLKDIV8 ((uint32_t)0x00000003) + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + + +/* ch32h417_fmc.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* FMC SDRAM BANK Status enumeration */ +typedef enum +{ + FMC_SDRAM_Normal = 0, + FMC_SDRAM_SelfRefresh, + FMC_SDRAM_PowerOff +}FMC_SDRAM_BANK_Sta_TypeDef; + +#endif + +/* FMC_NORSRAM_Bank */ +#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) + +/* FMC_NAND_Bank */ +#define FMC_Bank3_NAND ((uint32_t)0x00000000) + +/* FMC_SDRAM_Bank */ +#define FMC_Bank5_SDRAM ((uint32_t)0x00000000) +#define FMC_Bank6_SDRAM ((uint32_t)0x00000002) + +/* FMC_Data_Address_Bus_Multiplexing */ +#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +/* FMC_Memory_Type */ +#define FMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FMC_MemoryType_NOR ((uint32_t)0x00000008) + +/* FMC_Data_Width */ +#define FMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define FMC_MemoryDataWidth_32b ((uint32_t)0x00000020) + +/* FMC_NAND_Data_Width */ +#define FMC_NAND_MemDataWidth_8b ((uint32_t)0x00000000) +#define FMC_NAND_MemDataWidth_16b ((uint32_t)0x00000010) + +/* FMC_CPSIZE */ +#define FMC_CPSIZE_None ((uint32_t)0x00000000) +#define FMC_CPSIZE_128Bytes ((uint32_t)0x00010000) +#define FMC_CPSIZE_256Bytes ((uint32_t)0x00020000) +#define FMC_CPSIZE_512Bytes ((uint32_t)0x00030000) +#define FMC_CPSIZE_1024Bytes ((uint32_t)0x00040000) + +/* FMC_BMP */ +#define FMC_BMP_Mode0 ((uint32_t)0x00000000) +#define FMC_BMP_Mode1 ((uint32_t)0x00010000) + +/* FMC_Burst_Access_Mode */ +#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +/* FMC_AsynchronousWait */ +#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +/* FMC_Wait_Signal_Polarity */ +#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +/* FMC_Wait_Timing */ +#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +/* FMC_Write_Operation */ +#define FMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FMC_WriteOperation_Enable ((uint32_t)0x00001000) + +/* FMC_Wait_Signal */ +#define FMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FMC_WaitSignal_Enable ((uint32_t)0x00002000) + +/* FMC_Extended_Mode */ +#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +/* FMC_Write_Burst */ +#define FMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FMC_WriteBurst_Enable ((uint32_t)0x00080000) + +/* FMC_Access_Mode */ +#define FMC_AccessMode_A ((uint32_t)0x00000000) +#define FMC_AccessMode_B ((uint32_t)0x10000000) +#define FMC_AccessMode_C ((uint32_t)0x20000000) +#define FMC_AccessMode_D ((uint32_t)0x30000000) + +/* FMC_Wait_feature */ +#define FMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FMC_Waitfeature_Enable ((uint32_t)0x00000002) + +/* FMC_ECC */ +#define FMC_ECC_Disable ((uint32_t)0x00000000) +#define FMC_ECC_Enable ((uint32_t)0x00000040) + +/* FMC_ECC_Page_Size */ +#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +/* FMC_ColumnBitsNumber */ +#define FMC_ColumnBitsNumber_8 ((uint32_t)0x00000000) +#define FMC_ColumnBitsNumber_9 ((uint32_t)0x00000001) +#define FMC_ColumnBitsNumber_10 ((uint32_t)0x00000002) +#define FMC_ColumnBitsNumber_11 ((uint32_t)0x00000003) + +/* FMC_RowBitsNumber */ +#define FMC_ROWBitsNumber_11 ((uint32_t)0x00000000) +#define FMC_ROWBitsNumber_12 ((uint32_t)0x00000001) +#define FMC_ROWBitsNumber_13 ((uint32_t)0x00000002) + +/* FMC_MemoryDataWidth */ +#define FMC_MemoryDataWidth_8 ((uint32_t)0x00000000) +#define FMC_MemoryDataWidth_16 ((uint32_t)0x00000001) +#define FMC_MemoryDataWidth_32 ((uint32_t)0x00000002) + +/* FMC_InternalBankNumber */ +#define FMC_InternalBankNumber_2 ((uint32_t)0x00000000) +#define FMC_InternalBankNumber_4 ((uint32_t)0x00000001) + +/* FMC_CASLatency */ +#define FMC_CASLatency_1CLk ((uint32_t)0x00000001) +#define FMC_CASLatency_2CLk ((uint32_t)0x00000002) +#define FMC_CASLatency_3CLk ((uint32_t)0x00000003) + +/* FMC_WriteProtection */ +#define FMC_WriteProtection_Enable ((uint32_t)0x00000001) +#define FMC_WriteProtection_Disable ((uint32_t)0x00000000) + +/* FMC_SDClockPeriod */ +#define FMC_SDClockPeriod_Disable ((uint32_t)0x00000000) +#define FMC_SDClockPeriod_2HCLK ((uint32_t)0x00000002) +#define FMC_SDClockPeriod_3HCLK ((uint32_t)0x00000003) + +/* FMC_ReadBurst */ +#define FMC_ReadBurst_Disable ((uint32_t)0x00000000) +#define FMC_ReadBurst_Enable ((uint32_t)0x00000001) + +/* FMC_ReadPipeDelay */ +#define FMC_ReadPipeDelay_none ((uint32_t)0x00000000) +#define FMC_ReadPipeDelay_1HCLK ((uint32_t)0x00000001) +#define FMC_ReadPipeDelay_2HCLK ((uint32_t)0x00000002) + +/* FMC_ENHANCE_READ_MODE */ +#define FMC_ENHANCE_READ_MODE_Enable ((uint32_t)0x00000000) +#define FMC_ENHANCE_READ_MODE_Disable ((uint32_t)0x00008000) + +/* FMC_SDRAM_SEL */ +#define FMC_SDRAM_SEL_None ((uint32_t)0x00000000) +#define FMC_SDRAM_SEL_Bank5 ((uint32_t)0x00000010) +#define FMC_SDRAM_SEL_Bank6 ((uint32_t)0x00000008) +#define FMC_SDRAM_SEL_Bank5_6 ((uint32_t)0x00000018) + +/* FMC_SDRAM_CMD_Mode */ +#define FMC_SDRAM_CMD_Mode0 ((uint32_t)0x00000000) +#define FMC_SDRAM_CMD_Mode1 ((uint32_t)0x00000001) +#define FMC_SDRAM_CMD_Mode2 ((uint32_t)0x00000002) +#define FMC_SDRAM_CMD_Mode3 ((uint32_t)0x00000003) +#define FMC_SDRAM_CMD_Mode4 ((uint32_t)0x00000004) +#define FMC_SDRAM_CMD_Mode5 ((uint32_t)0x00000005) +#define FMC_SDRAM_CMD_Mode6 ((uint32_t)0x00000006) + +/* FMC_interrupts_definition */ +#define FMC_IT_RE ((uint32_t)0x00004000)) + +/* FMC_flags_definition */ +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_FLAG_BUSY ((uint32_t)0x10000020)) +#define FMC_FLAG_RE ((uint32_t)0x10000001)) + + +/* ch32h417_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +#warning "Speeds on H41x have their own register, dont concat in CFGLR" +typedef enum +{ + GPIO_Speed_10MHz = 0, + GPIO_Speed_50MHz, + GPIO_Speed_100MHz, + GPIO_Speed_180MHz, +} GPIOSpeed_TypeDef; + +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 1 +#define GPIO_CNF_OUT_OD 5 +#define GPIO_CNF_OUT_PP_AF 9 +#define GPIO_CNF_OUT_OD_AF 13 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00000001) /* PD0 and PD1 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00000002) /* ADC1 external trigger regular conversion mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00000004) /* ADC1 external trigger injection conversion mapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00000008) /* ADC2 external trigger regular conversion mapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00000010) /* ADC2 external trigger injection conversion mapping */ +#define GPIO_PartialRemap_UHSIF_CLK ((uint32_t)0x00160040) /* UHSIF CLK Partial Alternate Function mapping */ +#define GPIO_PartialRemap1_UHSIF_CLK ((uint32_t)0x00160080) /* UHSIF CLK Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_UHSIF_CLK ((uint32_t)0x001600C0) /* UHSIF CLK Full Alternate Function mapping */ +#define GPIO_PartialRemap_UHSIF_PORT ((uint32_t)0x00180100) /* UHSIF Port Partial Alternate Function mapping */ +#define GPIO_PartialFullRemap_UHSIF_PORT ((uint32_t)0x00180300) /* UHSIF Port Full Alternate Function mapping */ +#define GPIO_PartialRemap_SDMMC ((uint32_t)0x001A0400) /* SDMMC Partial Alternate Function mapping */ +#define GPIO_PartialFullRemap_SDMMC ((uint32_t)0x001A0C00) /* SDMMC Full Alternate Function mapping */ +#define GPIO_Remap_TIM2ITR1 ((uint32_t)0x00001000) /* TIM2 TRIG Alternate Function mapping */ +#define GPIO_Remap_VIO1V8_IO_HSLV ((uint32_t)0x00200002) /* VIO(1.8V) GPIO speed configration Alternate Function mapping */ +#define GPIO_Remap_VIO3V3_IO_HSLV ((uint32_t)0x00200004) /* VIO(3.3V) GPIO speed configration Alternate Function mapping */ +#define GPIO_Remap_VDD3V3_IO_HSLV ((uint32_t)0x00200008) /* VDD(3.3V) GPIO speed configration Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* SWJ Disable Function mapping */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceCMP ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* GPIO_AF_Define */ +#define GPIO_AF0 ((uint8_t)0x00) +#define GPIO_AF1 ((uint8_t)0x01) +#define GPIO_AF2 ((uint8_t)0x02) +#define GPIO_AF3 ((uint8_t)0x03) +#define GPIO_AF4 ((uint8_t)0x04) +#define GPIO_AF5 ((uint8_t)0x05) +#define GPIO_AF6 ((uint8_t)0x06) +#define GPIO_AF7 ((uint8_t)0x07) +#define GPIO_AF8 ((uint8_t)0x08) +#define GPIO_AF9 ((uint8_t)0x09) +#define GPIO_AF10 ((uint8_t)0x0A) +#define GPIO_AF11 ((uint8_t)0x0B) +#define GPIO_AF12 ((uint8_t)0x0C) +#define GPIO_AF13 ((uint8_t)0x0D) +#define GPIO_AF14 ((uint8_t)0x0E) +#define GPIO_AF15 ((uint8_t)0x0F) + + +/* ch32h417_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +/* ch32h417_opa.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* OPA member enumeration */ +typedef enum +{ + OPA1 = 0, + OPA2, + OPA3, +}OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1, + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_PGA_64xIN, + CHN_OFF = 0x7 +}OPA_NSEL_TypeDef; + +/* OPA out channel enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1, + OUT_TO_CMP /* only for OPA1 */ +}OPA_Mode_TypeDef; + + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_HS_enumeration */ +typedef enum +{ + HS_OFF = 0, + HS_ON +} OPA_HS_TypeDef; + +/* OPA_PFG_DIF_enumeration */ +typedef enum +{ + DIF_OFF = 0, + DIF_ON +} OPA_PGADIF_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_PGADIF_TypeDef PGADIF; /* Specifies the internal PGADIF of OPA */ + OPA_HS_TypeDef HS; /* specifies high speed mode enable of OPA */ +}OPA_InitTypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_TO_IO = 0, + OUT_TIM1_BKIN, + OUT_TIM8_BKIN, + OUT_TIM1_CH4, + OUT_TIM2_CH4, + OUT_TIM3_CH4, + OUT_TIM4_CH4, + OUT_TIM5_CH4, + OUT_TIM8_CH4, + OUT_TIM9_CH4, + OUT_TIM10_CH4, + OUT_TIM11_CH4, + OUT_TIM12_CH4, + OUT_LPTIM1_CH1, + OUT_LPTIM2_CH1, + OUT_FLOAT +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, + CMP_DAC2, + CMP_VREF, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP_0 = 0, + CMP_CHP_1, + CMP_OPA1 +} CMP_PSEL_TypeDef; + +#define CMP_CHP1 CMP_CHP_0 +#define CMP_CHP2 CMP_CHP_1 + +/* CMP_VREF_enumeration */ +typedef enum +{ + CMP_VREF_OFF = 0, + CMP_VREF_25PER_VDD, + CMP_VREF_50PERT_VDD, + CMP_VREF_75PERC_VDD +} CMP_VREF_TypeDef; + +/* CMP_HYPSEL_enumeration */ +typedef enum +{ + CMP_HYPSEL_OFF = 0, + CMP_HYPSEL_10mV, + CMP_HYPSEL_20mV, + CMP_HYPSEL_30mV, +} CMP_HYPSEL_TypeDef; + +/* CMP Init structure definition */ +typedef struct +{ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_VREF_TypeDef VREF; /* Specifies the positive VREF of CMP */ + CMP_HYPSEL_TypeDef HYPSEL; /* Specifies the HYEN of CMP */ +} CMP_InitTypeDef; + +/* CMP FILT_TimeBase division definition */ +#define CMP_FILT_TimeBase_Div1 ((uint8_t)0x00) +#define CMP_FILT_TimeBase_Div2 ((uint8_t)0x01) +#define CMP_FILT_TimeBase_Div3 ((uint8_t)0x02) +#define CMP_FILT_TimeBase_Div4 ((uint8_t)0x03) + +#endif + +/* ch32h417_pwr.h ------------------------------------------------------------*/ + +/* PVD_detection_level */ +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + +/* PWR_detection_level */ +#define PWR_VIO18Level_MODE0 ((uint32_t)0x00000000) +#define PWR_VIO18Level_MODE1 ((uint32_t)0x00000400) +#define PWR_VIO18Level_MODE2 ((uint32_t)0x00000800) +#define PWR_VIO18Level_MODE3 ((uint32_t)0x00000C00) +#define PWR_VIO18Level_MODE4 ((uint32_t)0x00001000) +#define PWR_VIO18Level_MODE5 ((uint32_t)0x00001400) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000001) + +/* PWR_VIO18CFGMODE */ +#define PWR_VIO18CFGMODE_HW ((uint32_t)0x00000000) +#define PWR_VIO18CFGMODE_SW ((uint32_t)0x00000200) + + +/* ch32h417_rcc.h ------------------------------------------------------------*/ + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00000020) +#define RCC_PLLSource_USBHS ((uint32_t)0x00000080) +#define RCC_PLLSource_ETH ((uint32_t)0x000000A0) +#define RCC_PLLSource_USBSS ((uint32_t)0x000000C0) +#define RCC_PLLSource_SERDES ((uint32_t)0x000000E0) + +/* PLL_multiplication_factor */ +#define RCC_PLLMul_4 ((uint32_t)0x00000000) +#define RCC_PLLMul_6 ((uint32_t)0x00000001) +#define RCC_PLLMul_7 ((uint32_t)0x00000002) +#define RCC_PLLMul_8 ((uint32_t)0x00000003) +#define RCC_PLLMul_8_5 ((uint32_t)0x00000004) +#define RCC_PLLMul_9 ((uint32_t)0x00000005) +#define RCC_PLLMul_9_5 ((uint32_t)0x00000006) +#define RCC_PLLMul_10 ((uint32_t)0x00000007) +#define RCC_PLLMul_10_5 ((uint32_t)0x00000008) +#define RCC_PLLMul_11 ((uint32_t)0x00000009) +#define RCC_PLLMul_11_5 ((uint32_t)0x0000000A) +#define RCC_PLLMul_12 ((uint32_t)0x0000000B) +#define RCC_PLLMul_12_5 ((uint32_t)0x0000000C) +#define RCC_PLLMul_13 ((uint32_t)0x0000000D) +#define RCC_PLLMul_14 ((uint32_t)0x0000000E) +#define RCC_PLLMul_15 ((uint32_t)0x0000000F) +#define RCC_PLLMul_16 ((uint32_t)0x00000010) +#define RCC_PLLMul_17 ((uint32_t)0x00000011) +#define RCC_PLLMul_18 ((uint32_t)0x00000012) +#define RCC_PLLMul_19 ((uint32_t)0x00000013) +#define RCC_PLLMul_20 ((uint32_t)0x00000014) +#define RCC_PLLMul_22 ((uint32_t)0x00000015) +#define RCC_PLLMul_24 ((uint32_t)0x00000016) +#define RCC_PLLMul_26 ((uint32_t)0x00000017) +#define RCC_PLLMul_28 ((uint32_t)0x00000018) +#define RCC_PLLMul_30 ((uint32_t)0x00000019) +#define RCC_PLLMul_32 ((uint32_t)0x0000001A) +#define RCC_PLLMul_34 ((uint32_t)0x0000001B) +#define RCC_PLLMul_36 ((uint32_t)0x0000001C) +#define RCC_PLLMul_38 ((uint32_t)0x0000001D) +#define RCC_PLLMul_40 ((uint32_t)0x0000001E) +#define RCC_PLLMul_59 ((uint32_t)0x0000001F) + +/* PLL_division_factor */ +#define RCC_PLLDiv_1 ((uint32_t)0x00000000) +#define RCC_PLLDiv_2 ((uint32_t)0x00000001) +#define RCC_PLLDiv_3 ((uint32_t)0x00000002) +#define RCC_PLLDiv_4 ((uint32_t)0x00000003) +#define RCC_PLLDiv_5 ((uint32_t)0x00000004) +#define RCC_PLLDiv_6 ((uint32_t)0x00000005) +#define RCC_PLLDiv_7 ((uint32_t)0x00000006) +#define RCC_PLLDiv_8 ((uint32_t)0x00000007) +#define RCC_PLLDiv_9 ((uint32_t)0x00000008) +#define RCC_PLLDiv_10 ((uint32_t)0x00000009) +#define RCC_PLLDiv_11 ((uint32_t)0x0000000A) +#define RCC_PLLDiv_12 ((uint32_t)0x0000000B) +#define RCC_PLLDiv_13 ((uint32_t)0x0000000C) +#define RCC_PLLDiv_14 ((uint32_t)0x0000000D) +#define RCC_PLLDiv_15 ((uint32_t)0x0000000E) +#define RCC_PLLDiv_16 ((uint32_t)0x0000000F) +#define RCC_PLLDiv_17 ((uint32_t)0x00000010) +#define RCC_PLLDiv_18 ((uint32_t)0x00000011) +#define RCC_PLLDiv_19 ((uint32_t)0x00000012) +#define RCC_PLLDiv_20 ((uint32_t)0x00000013) +#define RCC_PLLDiv_21 ((uint32_t)0x00000014) +#define RCC_PLLDiv_22 ((uint32_t)0x00000015) +#define RCC_PLLDiv_23 ((uint32_t)0x00000016) +#define RCC_PLLDiv_24 ((uint32_t)0x00000017) +#define RCC_PLLDiv_25 ((uint32_t)0x00000018) +#define RCC_PLLDiv_26 ((uint32_t)0x00000019) +#define RCC_PLLDiv_27 ((uint32_t)0x0000001A) +#define RCC_PLLDiv_28 ((uint32_t)0x0000001B) +#define RCC_PLLDiv_29 ((uint32_t)0x0000001C) +#define RCC_PLLDiv_30 ((uint32_t)0x0000001D) +#define RCC_PLLDiv_31 ((uint32_t)0x0000001E) +#define RCC_PLLDiv_32 ((uint32_t)0x0000001F) +#define RCC_PLLDiv_33 ((uint32_t)0x00000020) +#define RCC_PLLDiv_34 ((uint32_t)0x00000021) +#define RCC_PLLDiv_35 ((uint32_t)0x00000022) +#define RCC_PLLDiv_36 ((uint32_t)0x00000023) +#define RCC_PLLDiv_37 ((uint32_t)0x00000024) +#define RCC_PLLDiv_38 ((uint32_t)0x00000025) +#define RCC_PLLDiv_39 ((uint32_t)0x00000026) +#define RCC_PLLDiv_40 ((uint32_t)0x00000027) +#define RCC_PLLDiv_41 ((uint32_t)0x00000028) +#define RCC_PLLDiv_42 ((uint32_t)0x00000029) +#define RCC_PLLDiv_43 ((uint32_t)0x0000002A) +#define RCC_PLLDiv_44 ((uint32_t)0x0000002B) +#define RCC_PLLDiv_45 ((uint32_t)0x0000002C) +#define RCC_PLLDiv_46 ((uint32_t)0x0000002D) +#define RCC_PLLDiv_47 ((uint32_t)0x0000002E) +#define RCC_PLLDiv_48 ((uint32_t)0x0000002F) +#define RCC_PLLDiv_49 ((uint32_t)0x00000030) +#define RCC_PLLDiv_50 ((uint32_t)0x00000031) +#define RCC_PLLDiv_51 ((uint32_t)0x00000032) +#define RCC_PLLDiv_52 ((uint32_t)0x00000033) +#define RCC_PLLDiv_53 ((uint32_t)0x00000034) +#define RCC_PLLDiv_54 ((uint32_t)0x00000035) +#define RCC_PLLDiv_55 ((uint32_t)0x00000036) +#define RCC_PLLDiv_56 ((uint32_t)0x00000037) +#define RCC_PLLDiv_57 ((uint32_t)0x00000038) +#define RCC_PLLDiv_58 ((uint32_t)0x00000039) +#define RCC_PLLDiv_59 ((uint32_t)0x0000003A) +#define RCC_PLLDiv_60 ((uint32_t)0x0000003B) +#define RCC_PLLDiv_61 ((uint32_t)0x0000003C) +#define RCC_PLLDiv_62 ((uint32_t)0x0000003D) +#define RCC_PLLDiv_63 ((uint32_t)0x0000003E) +#define RCC_PLLDiv_64 ((uint32_t)0x0000003F) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* Core1_division_factor */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000008) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000009) +#define RCC_SYSCLK_Div8 ((uint32_t)0x0000000A) +#define RCC_SYSCLK_Div16 ((uint32_t)0x0000000B) +#define RCC_SYSCLK_Div64 ((uint32_t)0x0000000C) +#define RCC_SYSCLK_Div128 ((uint32_t)0x0000000D) +#define RCC_SYSCLK_Div256 ((uint32_t)0x0000000E) +#define RCC_SYSCLK_Div512 ((uint32_t)0x0000000F) + +/* HCLK_division_factor */ +#define RCC_SYSCLKFPRE_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLKFPRE_Div2 ((uint32_t)0x00010000) +#define RCC_SYSCLKFPRE_Div4 ((uint32_t)0x00020000) + +/* TIM_Clock_division_factor */ +#define TIM_Clock_Div2 ((uint32_t)0x00000005) +#define TIM_Clock_Div4 ((uint32_t)0x00000006) +#define TIM_Clock_Div8 ((uint32_t)0x00000007) + +/* LPTIM_Clock_division_factor */ +#define LPTIM_Clock_Div2 ((uint32_t)0x00000005) +#define LPTIM_Clock_Div4 ((uint32_t)0x00000006) +#define LPTIM_Clock_Div8 ((uint32_t)0x00000007) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_ETHPLLRDY ((uint8_t)0x20) +#define RCC_IT_SERDESPLLRDY ((uint8_t)0x40) +#define RCC_IT_CSSF ((uint8_t)0x80) + +/* ADC_Clock_source= USBHS/Divx */ +#define RCC_USBHS_Div5 ((uint8_t)0x00) +#define RCC_USBHS_Div6 ((uint8_t)0x01) +#define RCC_USBHS_Div7 ((uint8_t)0x02) +#define RCC_USBHS_Div8 ((uint8_t)0x03) +#define RCC_USBHS_Div9 ((uint8_t)0x04) +#define RCC_USBHS_Div10 ((uint8_t)0x05) +#define RCC_USBHS_Div11 ((uint8_t)0x06) +#define RCC_USBHS_Div12 ((uint8_t)0x07) +#define RCC_USBHS_Div13 ((uint8_t)0x08) +#define RCC_USBHS_Div14 ((uint8_t)0x09) +#define RCC_USBHS_Div15 ((uint8_t)0x0A) +#define RCC_USBHS_Div16 ((uint8_t)0x0B) +#define RCC_USBHS_Div17 ((uint8_t)0x0C) +#define RCC_USBHS_Div18 ((uint8_t)0x0D) +#define RCC_USBHS_Div19 ((uint8_t)0x0E) +#define RCC_USBHS_Div20 ((uint8_t)0x0F) +#define RCC_USBHS_Div21 ((uint8_t)0x10) +#define RCC_USBHS_Div22 ((uint8_t)0x11) +#define RCC_USBHS_Div23 ((uint8_t)0x12) +#define RCC_USBHS_Div24 ((uint8_t)0x13) +#define RCC_USBHS_Div25 ((uint8_t)0x14) +#define RCC_USBHS_Div26 ((uint8_t)0x15) +#define RCC_USBHS_Div27 ((uint8_t)0x16) +#define RCC_USBHS_Div28 ((uint8_t)0x17) +#define RCC_USBHS_Div29 ((uint8_t)0x18) +#define RCC_USBHS_Div30 ((uint8_t)0x19) +#define RCC_USBHS_Div31 ((uint8_t)0x1A) +#define RCC_USBHS_Div32 ((uint8_t)0x1B) +#define RCC_USBHS_Div33 ((uint8_t)0x1C) +#define RCC_USBHS_Div34 ((uint8_t)0x1D) +#define RCC_USBHS_Div35 ((uint8_t)0x1E) +#define RCC_USBHS_Div36 ((uint8_t)0x1F) + +/* ADC_Clock_source = HCLK/(RCC_PPRE2*RCC_ADCPRE) */ +#define RCC_PPRE2_DIV0 ((uint8_t)0x00) +#define RCC_PPRE2_DIV2 ((uint8_t)0x04) +#define RCC_PPRE2_DIV4 ((uint8_t)0x05) +#define RCC_PPRE2_DIV8 ((uint8_t)0x06) +#define RCC_PPRE2_DIV16 ((uint8_t)0x07) + +#define RCC_HCLK_ADCPRE_DIV2 ((uint8_t)0x00) +#define RCC_HCLK_ADCPRE_DIV4 ((uint8_t)0x01) +#define RCC_HCLK_ADCPRE_DIV6 ((uint8_t)0x02) +#define RCC_HCLK_ADCPRE_DIV8 ((uint8_t)0x03) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000040) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000080) +#define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x000000C0) + +/* HB_peripheral */ +#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_HBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_HBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_HBPeriph_FMC ((uint32_t)0x00000100) +#define RCC_HBPeriph_RNG ((uint32_t)0x00000200) +#define RCC_HBPeriph_SDMMC ((uint32_t)0x00000400) +#define RCC_HBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_HBPeriph_USBSS ((uint32_t)0x00001000) +#define RCC_HBPeriph_DVP ((uint32_t)0x00002000) +#define RCC_HBPeriph_ETH ((uint32_t)0x00004000) +#define RCC_HBPeriph_OTG_FS ((uint32_t)0x00020000) +#define RCC_HBPeriph_UHSIF ((uint32_t)0x00040000) +#define RCC_HBPeriph_USBPD ((uint32_t)0x00080000) +#define RCC_HBPeriph_SERDES ((uint32_t)0x00100000) +#define RCC_HBPeriph_PIOC ((uint32_t)0x00400000) + +/* HB2_peripheral */ +#define RCC_HB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_HB2Periph_HSADC ((uint32_t)0x00000002) +#define RCC_HB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_HB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_HB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_HB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_HB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_HB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_HB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_HB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_HB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_HB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_HB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_HB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_HB2Periph_I2C4 ((uint32_t)0x00008000) +#define RCC_HB2Periph_SAI ((uint32_t)0x00010000) +#define RCC_HB2Periph_SDIO ((uint32_t)0x00040000) +#define RCC_HB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_HB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_HB2Periph_TIM11 ((uint32_t)0x00200000) +#define RCC_HB2Periph_TIM12 ((uint32_t)0x00400000) +#define RCC_HB2Periph_OPCM ((uint32_t)0x00800000) +#define RCC_HB2Periph_DFSDM ((uint32_t)0x02000000) +#define RCC_HB2Periph_ECDC ((uint32_t)0x04000000) +#define RCC_HB2Periph_GPHA ((uint32_t)0x08000000) +#define RCC_HB2Periph_LTDC ((uint32_t)0x40000000) +#define RCC_HB2Periph_I3C ((uint32_t)0x80000000) + +/* HB1_peripheral */ +#define RCC_HB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_HB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_HB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_HB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_HB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_HB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_HB1Periph_USART6 ((uint32_t)0x00000040) +#define RCC_HB1Periph_USART7 ((uint32_t)0x00000080) +#define RCC_HB1Periph_USART8 ((uint32_t)0x00000100) +#define RCC_HB1Periph_LPTIM1 ((uint32_t)0x00000200) +#define RCC_HB1Periph_LPTIM2 ((uint32_t)0x00000400) +#define RCC_HB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_HB1Periph_QSPI1 ((uint32_t)0x00001000) +#define RCC_HB1Periph_QSPI2 ((uint32_t)0x00002000) +#define RCC_HB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_HB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_HB1Periph_SPI4 ((uint32_t)0x00010000) +#define RCC_HB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_HB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_HB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_HB1Periph_USART5 ((uint32_t)0x00100000) +#define RCC_HB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_HB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_HB1Periph_CAN3 ((uint32_t)0x01000000) +#define RCC_HB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_HB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_HB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_HB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_HB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_HB1Periph_I2C3 ((uint32_t)0x40000000) +#define RCC_HB1Periph_SWPMI ((uint32_t)0x80000000) + +/* CSSON */ +#define RCC_CSSON_DISABLE (uint8_t)0x00 +#define RCC_CSSON_ENABLE (uint8_t)0x01 + +/* CSSHSEDIS */ +#define RCC_CSSHSEDIS_DISABLE (uint8_t)0x00 +#define RCC_CSSHSEDIS_ENABLE (uint8_t)0x01 + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) +#define RCC_MCO_UTMI ((uint8_t)0x08) +#define RCC_MCO_USBSSPLL_Div2 ((uint8_t)0x09) +#define RCC_MCO_ETHPLL_Div8 ((uint8_t)0x0A) +#define RCC_MCO_SERDESPLL_Div16 ((uint8_t)0x0B) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_USBHSPLLRDY ((uint8_t)0x35) +#define RCC_FLAG_USBSSPLLRDY ((uint8_t)0x37) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_ETHPLLRDY ((uint8_t)0x3B) +#define RCC_FLAG_SERDESPLLRDY ((uint8_t)0x3D) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LKUPRSTF ((uint8_t)0x7F) + +/*ETH 125M clock source*/ +#define RCC_ETH125MSource_PLLCLK ((uint8_t)0x00) +#define RCC_ETH125MSource_USBSS ((uint8_t)0x01) +#define RCC_ETH125MSource_ETH_Div4 ((uint8_t)0x02) +#define RCC_ETH125MSource_SERDES_Div8 ((uint8_t)0x03) + +/*HSADC clock source*/ +#define RCC_HSADCSource_PLLCLK ((uint8_t)0x00) +#define RCC_HSADCSource_SYSCLK ((uint8_t)0x01) +#define RCC_HSADCSource_USBHS ((uint8_t)0x02) +#define RCC_HSADCSource_ETH ((uint8_t)0x03) + +/* I2S2_clock_source */ +#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S2CLKSource_PLLCLK ((uint8_t)0x01) + +/* I2S3_clock_source */ +#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S3CLKSource_PLLCLK ((uint8_t)0x01) + +/* RNG_clock_source */ +#define RCC_RNGCLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_RNGCLKSource_PLLCLK ((uint8_t)0x01) + +/* USBFS_clock_source */ +#define RCC_USBFSCLKSource_PLL ((uint8_t)0x00) +#define RCC_USBFSCLKSource_USBHSPLL ((uint8_t)0x01) + +/* USBFS_division_factor */ +#define RCC_USBFS_Div1 ((uint8_t)0x00) +#define RCC_USBFS_Div2 ((uint8_t)0x01) +#define RCC_USBFS_Div3 ((uint8_t)0x02) +#define RCC_USBFS_Div4 ((uint8_t)0x03) +#define RCC_USBFS_Div5 ((uint8_t)0x04) +#define RCC_USBFS_Div6 ((uint8_t)0x05) +#define RCC_USBFS_Div8 ((uint8_t)0x06) +#define RCC_USBFS_Div10 ((uint8_t)0x07) +#define RCC_USBFS_1Div5 ((uint8_t)0x08) +#define RCC_USBFS_2Div5 ((uint8_t)0x09) +#define RCC_USBFS_3Div5 ((uint8_t)0x0A) +#define RCC_USBFS_4Div5 ((uint8_t)0x0B) +#define RCC_USBFS_5Div5 ((uint8_t)0x0C) +#define RCC_USBFS_6Div5 ((uint8_t)0x0D) +#define RCC_USBFS_7Div5 ((uint8_t)0x0E) +#define RCC_USBFS_9Div5 ((uint8_t)0x0F) + +/* LTDC_clock_source */ +#define RCC_LTDCClockSource_PLL ((uint8_t)0x00) +#define RCC_LTDCClockSource_SERDESPLL ((uint8_t)0x01) +#define RCC_LTDCClockSource_ETHPLL ((uint8_t)0x02) +#define RCC_LTDCClockSource_USBHSPLL ((uint8_t)0x03) + +/* LTDC_division_factor */ +#define RCC_LTDCClockSource_Div1 ((uint8_t)0x00) +#define RCC_LTDCClockSource_Div2 ((uint8_t)0x01) +#define RCC_LTDCClockSource_Div3 ((uint8_t)0x02) +#define RCC_LTDCClockSource_Div4 ((uint8_t)0x03) +#define RCC_LTDCClockSource_Div5 ((uint8_t)0x04) +#define RCC_LTDCClockSource_Div6 ((uint8_t)0x05) +#define RCC_LTDCClockSource_Div7 ((uint8_t)0x06) +#define RCC_LTDCClockSource_Div8 ((uint8_t)0x07) +#define RCC_LTDCClockSource_Div9 ((uint8_t)0x08) +#define RCC_LTDCClockSource_Div10 ((uint8_t)0x09) +#define RCC_LTDCClockSource_Div11 ((uint8_t)0x0A) +#define RCC_LTDCClockSource_Div12 ((uint8_t)0x0B) +#define RCC_LTDCClockSource_Div13 ((uint8_t)0x0C) +#define RCC_LTDCClockSource_Div14 ((uint8_t)0x0D) +#define RCC_LTDCClockSource_Div15 ((uint8_t)0x0E) +#define RCC_LTDCClockSource_Div16 ((uint8_t)0x0F) +#define RCC_LTDCClockSource_Div17 ((uint8_t)0x10) +#define RCC_LTDCClockSource_Div18 ((uint8_t)0x11) +#define RCC_LTDCClockSource_Div19 ((uint8_t)0x12) +#define RCC_LTDCClockSource_Div20 ((uint8_t)0x13) +#define RCC_LTDCClockSource_Div21 ((uint8_t)0x14) +#define RCC_LTDCClockSource_Div22 ((uint8_t)0x15) +#define RCC_LTDCClockSource_Div23 ((uint8_t)0x16) +#define RCC_LTDCClockSource_Div24 ((uint8_t)0x17) +#define RCC_LTDCClockSource_Div25 ((uint8_t)0x18) +#define RCC_LTDCClockSource_Div26 ((uint8_t)0x19) +#define RCC_LTDCClockSource_Div27 ((uint8_t)0x1A) +#define RCC_LTDCClockSource_Div28 ((uint8_t)0x1B) +#define RCC_LTDCClockSource_Div29 ((uint8_t)0x1C) +#define RCC_LTDCClockSource_Div30 ((uint8_t)0x1D) +#define RCC_LTDCClockSource_Div31 ((uint8_t)0x1E) +#define RCC_LTDCClockSource_Div32 ((uint8_t)0x1F) +#define RCC_LTDCClockSource_Div33 ((uint8_t)0x20) +#define RCC_LTDCClockSource_Div34 ((uint8_t)0x21) +#define RCC_LTDCClockSource_Div35 ((uint8_t)0x22) +#define RCC_LTDCClockSource_Div36 ((uint8_t)0x23) +#define RCC_LTDCClockSource_Div37 ((uint8_t)0x24) +#define RCC_LTDCClockSource_Div38 ((uint8_t)0x25) +#define RCC_LTDCClockSource_Div39 ((uint8_t)0x26) +#define RCC_LTDCClockSource_Div40 ((uint8_t)0x27) +#define RCC_LTDCClockSource_Div41 ((uint8_t)0x28) +#define RCC_LTDCClockSource_Div42 ((uint8_t)0x29) +#define RCC_LTDCClockSource_Div43 ((uint8_t)0x2A) +#define RCC_LTDCClockSource_Div44 ((uint8_t)0x2B) +#define RCC_LTDCClockSource_Div45 ((uint8_t)0x2C) +#define RCC_LTDCClockSource_Div46 ((uint8_t)0x2D) +#define RCC_LTDCClockSource_Div47 ((uint8_t)0x2E) +#define RCC_LTDCClockSource_Div48 ((uint8_t)0x2F) +#define RCC_LTDCClockSource_Div49 ((uint8_t)0x30) +#define RCC_LTDCClockSource_Div50 ((uint8_t)0x31) +#define RCC_LTDCClockSource_Div51 ((uint8_t)0x32) +#define RCC_LTDCClockSource_Div52 ((uint8_t)0x33) +#define RCC_LTDCClockSource_Div53 ((uint8_t)0x34) +#define RCC_LTDCClockSource_Div54 ((uint8_t)0x35) +#define RCC_LTDCClockSource_Div55 ((uint8_t)0x36) +#define RCC_LTDCClockSource_Div56 ((uint8_t)0x37) +#define RCC_LTDCClockSource_Div57 ((uint8_t)0x38) +#define RCC_LTDCClockSource_Div58 ((uint8_t)0x39) +#define RCC_LTDCClockSource_Div59 ((uint8_t)0x3A) +#define RCC_LTDCClockSource_Div60 ((uint8_t)0x3B) +#define RCC_LTDCClockSource_Div61 ((uint8_t)0x3C) +#define RCC_LTDCClockSource_Div62 ((uint8_t)0x3D) +#define RCC_LTDCClockSource_Div63 ((uint8_t)0x3E) +#define RCC_LTDCClockSource_Div64 ((uint8_t)0x3F) + +/* UHSIF_clock_source */ +#define RCC_UHSIFClockSource_SYSCLK ((uint8_t)0x00) +#define RCC_UHSIFClockSource_PLL ((uint8_t)0x01) +#define RCC_UHSIFClockSource_USBHSPLL ((uint8_t)0x02) +#define RCC_UHSIFClockSource_ETHPLL ((uint8_t)0x03) + +/* UHSIF_division_factor */ +#define RCC_UHSIFClockSource_Div1 ((uint8_t)0x00) +#define RCC_UHSIFClockSource_Div2 ((uint8_t)0x01) +#define RCC_UHSIFClockSource_Div3 ((uint8_t)0x02) +#define RCC_UHSIFClockSource_Div4 ((uint8_t)0x03) +#define RCC_UHSIFClockSource_Div5 ((uint8_t)0x04) +#define RCC_UHSIFClockSource_Div6 ((uint8_t)0x05) +#define RCC_UHSIFClockSource_Div7 ((uint8_t)0x06) +#define RCC_UHSIFClockSource_Div8 ((uint8_t)0x07) +#define RCC_UHSIFClockSource_Div9 ((uint8_t)0x08) +#define RCC_UHSIFClockSource_Div10 ((uint8_t)0x09) +#define RCC_UHSIFClockSource_Div11 ((uint8_t)0x0A) +#define RCC_UHSIFClockSource_Div12 ((uint8_t)0x0B) +#define RCC_UHSIFClockSource_Div13 ((uint8_t)0x0C) +#define RCC_UHSIFClockSource_Div14 ((uint8_t)0x0D) +#define RCC_UHSIFClockSource_Div15 ((uint8_t)0x0E) +#define RCC_UHSIFClockSource_Div16 ((uint8_t)0x0F) +#define RCC_UHSIFClockSource_Div17 ((uint8_t)0x10) +#define RCC_UHSIFClockSource_Div18 ((uint8_t)0x11) +#define RCC_UHSIFClockSource_Div19 ((uint8_t)0x12) +#define RCC_UHSIFClockSource_Div20 ((uint8_t)0x13) +#define RCC_UHSIFClockSource_Div21 ((uint8_t)0x14) +#define RCC_UHSIFClockSource_Div22 ((uint8_t)0x15) +#define RCC_UHSIFClockSource_Div23 ((uint8_t)0x16) +#define RCC_UHSIFClockSource_Div24 ((uint8_t)0x17) +#define RCC_UHSIFClockSource_Div25 ((uint8_t)0x18) +#define RCC_UHSIFClockSource_Div26 ((uint8_t)0x19) +#define RCC_UHSIFClockSource_Div27 ((uint8_t)0x1A) +#define RCC_UHSIFClockSource_Div28 ((uint8_t)0x1B) +#define RCC_UHSIFClockSource_Div29 ((uint8_t)0x1C) +#define RCC_UHSIFClockSource_Div30 ((uint8_t)0x1D) +#define RCC_UHSIFClockSource_Div31 ((uint8_t)0x1E) +#define RCC_UHSIFClockSource_Div32 ((uint8_t)0x1F) +#define RCC_UHSIFClockSource_Div33 ((uint8_t)0x20) +#define RCC_UHSIFClockSource_Div34 ((uint8_t)0x21) +#define RCC_UHSIFClockSource_Div35 ((uint8_t)0x22) +#define RCC_UHSIFClockSource_Div36 ((uint8_t)0x23) +#define RCC_UHSIFClockSource_Div37 ((uint8_t)0x24) +#define RCC_UHSIFClockSource_Div38 ((uint8_t)0x25) +#define RCC_UHSIFClockSource_Div39 ((uint8_t)0x26) +#define RCC_UHSIFClockSource_Div40 ((uint8_t)0x27) +#define RCC_UHSIFClockSource_Div41 ((uint8_t)0x28) +#define RCC_UHSIFClockSource_Div42 ((uint8_t)0x29) +#define RCC_UHSIFClockSource_Div43 ((uint8_t)0x2A) +#define RCC_UHSIFClockSource_Div44 ((uint8_t)0x2B) +#define RCC_UHSIFClockSource_Div45 ((uint8_t)0x2C) +#define RCC_UHSIFClockSource_Div46 ((uint8_t)0x2D) +#define RCC_UHSIFClockSource_Div47 ((uint8_t)0x2E) +#define RCC_UHSIFClockSource_Div48 ((uint8_t)0x2F) +#define RCC_UHSIFClockSource_Div49 ((uint8_t)0x30) +#define RCC_UHSIFClockSource_Div50 ((uint8_t)0x31) +#define RCC_UHSIFClockSource_Div51 ((uint8_t)0x32) +#define RCC_UHSIFClockSource_Div52 ((uint8_t)0x33) +#define RCC_UHSIFClockSource_Div53 ((uint8_t)0x34) +#define RCC_UHSIFClockSource_Div54 ((uint8_t)0x35) +#define RCC_UHSIFClockSource_Div55 ((uint8_t)0x36) +#define RCC_UHSIFClockSource_Div56 ((uint8_t)0x37) +#define RCC_UHSIFClockSource_Div57 ((uint8_t)0x38) +#define RCC_UHSIFClockSource_Div58 ((uint8_t)0x39) +#define RCC_UHSIFClockSource_Div59 ((uint8_t)0x3A) +#define RCC_UHSIFClockSource_Div60 ((uint8_t)0x3B) +#define RCC_UHSIFClockSource_Div61 ((uint8_t)0x3C) +#define RCC_UHSIFClockSource_Div62 ((uint8_t)0x3D) +#define RCC_UHSIFClockSource_Div63 ((uint8_t)0x3E) +#define RCC_UHSIFClockSource_Div64 ((uint8_t)0x3F) + +/* USBHSPLL_clock_source */ +#define RCC_USBHSPLLSource_HSE ((uint8_t)0x00) +#define RCC_USBHSPLLSource_HSI ((uint8_t)0x01) +#define RCC_USBHSPLLSource_20METH ((uint8_t)0x02) +#define RCC_USBHSPLLSource_PLL_CLK_DIV ((uint8_t)0x03) + +/* USBHS PLL Refer clock */ +#define RCC_USBHSPLLRefer_25M ((uint8_t)0x00) +#define RCC_USBHSPLLRefer_20M ((uint8_t)0x01) +#define RCC_USBHSPLLRefer_24M ((uint8_t)0x02) +#define RCC_USBHSPLLRefer_32M ((uint8_t)0x03) + +/* USBSS PLL Refer clock */ +#define RCC_USBSSPLLRefer_20M ((uint8_t)0x00) +#define RCC_USBSSPLLRefer_24M ((uint8_t)0x10) +#define RCC_USBSSPLLRefer_25M ((uint8_t)0x20) +#define RCC_USBSSPLLRefer_30M ((uint8_t)0x30) +#define RCC_USBSSPLLRefer_32M ((uint8_t)0x40) +#define RCC_USBSSPLLRefer_40M ((uint8_t)0x50) +#define RCC_USBSSPLLRefer_60M ((uint8_t)0x60) +#define RCC_USBSSPLLRefer_80M ((uint8_t)0x70) + +/* USBHS PLL Source clock Division*/ +#define RCC_USBHSPLL_IN_Div1 ((uint32_t)0x0000) +#define RCC_USBHSPLL_IN_Div2 ((uint32_t)0x0100) +#define RCC_USBHSPLL_IN_Div3 ((uint32_t)0x0200) +#define RCC_USBHSPLL_IN_Div4 ((uint32_t)0x0300) +#define RCC_USBHSPLL_IN_Div5 ((uint32_t)0x0400) +#define RCC_USBHSPLL_IN_Div6 ((uint32_t)0x0500) +#define RCC_USBHSPLL_IN_Div7 ((uint32_t)0x0600) +#define RCC_USBHSPLL_IN_Div8 ((uint32_t)0x0700) +#define RCC_USBHSPLL_IN_Div9 ((uint32_t)0x0800) +#define RCC_USBHSPLL_IN_Div10 ((uint32_t)0x0900) +#define RCC_USBHSPLL_IN_Div11 ((uint32_t)0x0A00) +#define RCC_USBHSPLL_IN_Div12 ((uint32_t)0x0B00) +#define RCC_USBHSPLL_IN_Div13 ((uint32_t)0x0C00) +#define RCC_USBHSPLL_IN_Div14 ((uint32_t)0x0D00) +#define RCC_USBHSPLL_IN_Div15 ((uint32_t)0x0E00) +#define RCC_USBHSPLL_IN_Div16 ((uint32_t)0x0F00) +#define RCC_USBHSPLL_IN_Div17 ((uint32_t)0x1000) +#define RCC_USBHSPLL_IN_Div18 ((uint32_t)0x1100) +#define RCC_USBHSPLL_IN_Div19 ((uint32_t)0x1200) +#define RCC_USBHSPLL_IN_Div20 ((uint32_t)0x1300) +#define RCC_USBHSPLL_IN_Div21 ((uint32_t)0x1400) +#define RCC_USBHSPLL_IN_Div22 ((uint32_t)0x1500) +#define RCC_USBHSPLL_IN_Div23 ((uint32_t)0x1600) +#define RCC_USBHSPLL_IN_Div24 ((uint32_t)0x1700) +#define RCC_USBHSPLL_IN_Div25 ((uint32_t)0x1800) +#define RCC_USBHSPLL_IN_Div26 ((uint32_t)0x1900) +#define RCC_USBHSPLL_IN_Div27 ((uint32_t)0x1A00) +#define RCC_USBHSPLL_IN_Div28 ((uint32_t)0x1B00) +#define RCC_USBHSPLL_IN_Div29 ((uint32_t)0x1C00) +#define RCC_USBHSPLL_IN_Div30 ((uint32_t)0x1D00) +#define RCC_USBHSPLL_IN_Div31 ((uint32_t)0x1E00) +#define RCC_USBHSPLL_IN_Div32 ((uint32_t)0x1F00) + +/* SERDES PLL clock Mul*/ +#define RCC_SERDESPLLMul_25 ((uint32_t)0x0000) +#define RCC_SERDESPLLMul_28 ((uint32_t)0x0001) +#define RCC_SERDESPLLMul_30 ((uint32_t)0x0002) +#define RCC_SERDESPLLMul_32 ((uint32_t)0x0003) +#define RCC_SERDESPLLMul_35 ((uint32_t)0x0004) +#define RCC_SERDESPLLMul_38 ((uint32_t)0x0005) +#define RCC_SERDESPLLMul_40 ((uint32_t)0x0006) +#define RCC_SERDESPLLMul_45 ((uint32_t)0x0007) +#define RCC_SERDESPLLMul_50 ((uint32_t)0x0008) +#define RCC_SERDESPLLMul_56 ((uint32_t)0x0009) +#define RCC_SERDESPLLMul_60 ((uint32_t)0x000A) +#define RCC_SERDESPLLMul_64 ((uint32_t)0x000B) +#define RCC_SERDESPLLMul_70 ((uint32_t)0x000C) +#define RCC_SERDESPLLMul_76 ((uint32_t)0x000D) +#define RCC_SERDESPLLMul_80 ((uint32_t)0x000E) +#define RCC_SERDESPLLMul_90 ((uint32_t)0x000F) + +/* ADC_clock_H_Level_Duty_Cycle */ +#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) +#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x40000000) + +/* ADC_clock_source */ +#define RCC_ADCCLKSource_HCLK ((uint8_t)0x00) +#define RCC_ADCCLKSource_USBHSPLL ((uint8_t)0x01) + +/* SYSPLL_clock_source */ +#define RCC_SYSPLLClockSource_PLL ((uint8_t)0x00) +#define RCC_SYSPLLClockSource_USBHSPLL ((uint8_t)0x04) +#define RCC_SYSPLLClockSource_ETHPLL ((uint8_t)0x05) +#define RCC_SYSPLLClockSource_SERDESPLL ((uint8_t)0x06) +#define RCC_SYSPLLClockSource_USBSSPLL ((uint8_t)0x07) + +#define RCC_RTCOutputSource_CalibClock ((uint16_t)0x0008) +#define RCC_RTCOutputSource_Alarm ((uint16_t)0x0010) +#define RCC_RTCOutputSource_Second ((uint16_t)0x0030) +#define RCC_RTCOutputSource_None ((uint16_t)0x0000) + +/* ch32v00x_rng.h ------------------------------------------------------------*/ + +/* RNG_flags_definition*/ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ + +/* RNG_interrupts_definition */ +#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ + + + +/* ch32h417_rtc.h ------------------------------------------------------------*/ + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +/* ch32h417_sdio.h -----------------------------------------------------------*/ + +/* SDIO_Clock_Edge */ +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) + +/* SDIO_Clock_Bypass */ +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) + +/* SDIO_Clock_Power_Save */ +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) + +/* SDIO_Bus_Wide */ +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) + +/* SDIO_Hardware_Flow_Control */ +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) + +/* SDIO_Power_State */ +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) + +/* SDIO_Interrupt_sources */ +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Response_Type */ +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) + +/* SDIO_Wait_Interrupt_State */ +#define SDIO_Wait_No ((uint32_t)0x00000000) +#define SDIO_Wait_IT ((uint32_t)0x00000100) +#define SDIO_Wait_Pend ((uint32_t)0x00000200) + +/* SDIO_CPSM_State */ +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) + +/* SDIO_Response_Registers */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +/* SDIO_Data_Block_Size */ +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) + +/* SDIO_Transfer_Direction */ +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) + +/* SDIO_Transfer_Type */ +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) + +/* SDIO_DPSM_State */ +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) + +/* SDIO_Flags */ +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Read_Wait_Mode */ +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) + +#define SDIO_DataControl_DTEN ((uint32_t)0x00000001) +#define SDIO_DataControl_DTDIR ((uint32_t)0x00000002) +#define SDIO_DataControl_DTMODE ((uint32_t)0x00000004) +#define SDIO_DataControl_DMAEN ((uint32_t)0x00000008) +#define SDIO_DataControl_DBLOCKSIZE ((uint32_t)0x000000F0) +#define SDIO_DataControl_RWSTART ((uint32_t)0x00000100) +#define SDIO_DataControl_RWSTOP ((uint32_t)0x00000200) +#define SDIO_DataControl_RWMOD ((uint32_t)0x00000400) +#define SDIO_DataControl_SDIOEN ((uint32_t)0x00000800) + + +/* ch32h417_spi.h ------------------------------------------------------------*/ + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_Mode0 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_Mode1 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_Mode2 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_Mode3 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_Mode4 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_Mode5 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_Mode6 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_Mode7 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +/* SPI_HIGH_SPEED_MODE_definition */ +#define SPI_HIGH_SPEED_MODE1 ((uint16_t)0x0001) +#define SPI_HIGH_SPEED_MODE2 ((uint16_t)0x0005) + + +/* ch32h417_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_DT_MODE */ +#define TIM_DT_MODE_Disable ((uint16_t)0x0000) +#define TIM_DT_MODE_Rising ((uint16_t)0x0040) +#define TIM_DT_MODE_Falling ((uint16_t)0x0080) +#define TIM_DT_MODE_BothEdge ((uint16_t)0x00C0) + +/* TIM_Brake Select */ +#define TIM_BKIN1 ((uint16_t)0x0000) +#define TIM_BKIN2 ((uint16_t)0x0001) +#define TIM_BKIN1_2 ((uint16_t)0x0002) +#define TIM_DFSDM_BK0 ((uint16_t)0x0004) +#define TIM_DFSDM_BK1 ((uint16_t)0x0005) + +/* TIM_IC_OverflowMode */ +#define TIM_IC_OV_Mode0 ((uint16_t)0x0000) +#define TIM_IC_OV_Mode1 ((uint16_t)0x4000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +/* ch32h417_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_5b ((uint16_t)0xC000) +#define USART_WordLength_6b ((uint16_t)0x8000) +#define USART_WordLength_7b ((uint16_t)0x4000) +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) +#define USART_IT_MS_ER ((uint16_t)0x0B81) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_LPWKUP ((uint16_t)0x8000) +#define USART_FLAG_MS_ERR ((uint16_t)0x0800) +#define USART_FLAG_RX_BUSY ((uint16_t)0x0400) +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +/* USART_LPWKUP_DLY */ +#define USART_LPWKUP_DLY_0_CLKCycle ((uint16_t)0x0000) +#define USART_LPWKUP_DLY_1_CLKCycle ((uint16_t)0x2000) +#define USART_LPWKUP_DLY_2_CLKCycle ((uint16_t)0x4000) +#define USART_LPWKUP_DLY_3_CLKCycle ((uint16_t)0x6000) +#define USART_LPWKUP_DLY_4_CLKCycle ((uint16_t)0x8000) +#define USART_LPWKUP_DLY_5_CLKCycle ((uint16_t)0xA000) +#define USART_LPWKUP_DLY_6_CLKCycle ((uint16_t)0xC000) +#define USART_LPWKUP_DLY_7_CLKCycle ((uint16_t)0xE000) + +/* USART_LPWKUP_CLK_SRC */ +#define USART_LPWKUP_CLK_SRC_LSI ((uint16_t)0x0000) +#define USART_LPWKUP_CLK_SRC_LSE ((uint16_t)0x1000) + +/* USART_MARKorSPACE_Mode */ +#define USART_VerifyMode_NoMARKorSPACE ((uint16_t)0x0000) +#define USART_VerifyMode_MARK ((uint16_t)0x0008) +#define USART_VerifyMode_SPACE ((uint16_t)0x000C) + +/* ch32h417_usb.h ------------------------------------------------------------*/ + + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 +#endif +#ifndef MAX_PACKET_SIZE +#define MAX_PACKET_SIZE 64 // maximum packet size +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_DATA2 0x07 +#define USB_PID_MDATA 0x0F +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_ENDPOINT 0x02 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#define USB_SET_SEL 0x30 +#define USB_SET_ISOCH_DLY 0x31 +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 +#define DEF_STRING_DESC_OS 0xEE + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* USB UVC device request code */ +#define UVC_GET_CUR 0x81 +#define UVC_GET_MIN 0x82 +#define UVC_GET_MAX 0x83 +#define UVC_GET_RES 0x84 +#define UVC_GET_LEN 0x85 +#define UVC_GET_INFO 0x86 +#define UVC_GET_DEF 0x87 + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +#define USB_U1_ENABLE 0x30 +#define USB_U2_ENABLE 0x31 +/*******************************************************************************/ +/* USBSS Related Register Macro Definition */ + +/* LINK_CFG */ +#define U3_LINK_RESET 0x80000000 +#define LINK_FORCE_RXTERM 0x00800000 +#define LINK_FORCE_POLLING 0x00400000 +#define LINK_TOUT_MODE 0x00200000 +#define LINK_U1_PING_EN 0x00100000 +#define LINK_U2_ALLOW 0x00020000 +#define LINK_U1_ALLOW 0x00010000 +#define LINK_LTSSM_MODE 0x00008000 +#define LINK_LOOPBACK_ACT 0x00004000 +#define LINK_LOOPBACK_EN 0x00002000 +#define LINK_U2_RXDET 0x00001000 +#define LINK_CP78_SEL_MASK 0x00000C00 + #define LINK_CP78_SEL_190BITS 0x00000000 + #define LINK_CP78_SEL_120BITS 0x00000400 + #define LINK_CP78_SEL_50BITS 0x00000800 + #define LINK_CP78_SEL_250BITS 0x00000C00 +#define LINK_TX_DEEMPH_MASK 0x00000300 + #define LINK_TX_DEEMPH_6DB 0x00000000 + #define LINK_TX_DEEMPH_3_5DB 0x00000100 +#define LINK_TX_SWING 0x00000080 +#define LINK_RX_EQ_EN 0x00000040 +#define LINK_LFPS_RX_PD 0x00000020 +#define LINK_COMPLIANCE_EN 0x00000010 +#define LINK_PHY_RESET 0x00000008 +#define LINK_SS_PLR_SWAP 0x00000004 +#define LINK_RX_TERM_EN 0x00000002 +#define LINK_DOWN_MODE 0x00000001 + +/* LINK_CTRL */ +#define LINK_RX_TS_CFG_MASK 0xFF000000 +#define LINK_TX_TS_CFG_MASK 0x00FF0000 + #define LINK_HOT_RESET 0x00010000 +#define LINK_TX_LGO_U3 0x00008000 +#define LINK_TX_LGO_U2 0x00004000 +#define LINK_TX_LGO_U1 0x00002000 +#define LINK_POLLING_EN 0x00001000 +#define LINK_REG_ROUT_EN 0x00000800 +#define LINK_LUP_LDN_EN 0x00000400 +#define LINK_TX_UX_EXIT 0x00000200 +#define LINK_TX_WARM_RESET 0x00000100 +#define LINK_GO_RX_DET 0x00000080 +#define LINK_GO_RECOVERY 0x00000040 +#define LINK_GO_INACTIVE 0x00000020 +#define LINK_GO_DISABLED 0x00000010 + #define LINK_PD_MODE_MASK 0x00000003 +#define LINK_P0_MODE 0x00000000 +#define LINK_P1_MODE 0x00000001 +#define LINK_P2_MODE 0x00000002 +#define LINK_P3_MODE 0x00000003 + +/* LINK_INT_CTRL */ +#define LINK_IE_STATE_CHG 0x80000000 +#define LINK_IE_U1_TOUT 0x40000000 +#define LINK_IE_U2_TOUT 0x20000000 +#define LINK_IE_UX_FAIL 0x10000000 +#define LINK_IE_TX_WARMRST 0x08000000 +#define LINK_IE_UX_EXIT_FAIL 0x04000000 +#define LINK_IE_RX_LMP_TOUT 0x00800000 +#define LINK_IE_TX_LMP 0x00400000 +#define LINK_IE_RX_LMP 0x00200000 +#define LINK_IE_RX_DET 0x00100000 +#define LINK_IE_LOOPBACK 0x00080000 +#define LINK_IE_COMPLIANCE 0x00040000 +#define LINK_IE_HPBUF_FULL 0x00020000 +#define LINK_IE_HPBUF_EMPTY 0x00010000 +#define LINK_IE_HOT_RST 0x00008000 +#define LINK_IE_WAKEUP 0x00004000 +#define LINK_IE_WARM_RST 0x00002000 +#define LINK_IE_UX_EXIT 0x00001000 +#define LINK_IE_TXEQ 0x00000800 +#define LINK_IE_TERM_PRES 0x00000400 +#define LINK_IE_UX_REJ 0x00000200 +#define LINK_IE_U3_WK_TOUT 0x00000100 +#define LINK_IE_GO_U0 0x00000080 +#define LINK_IE_GO_U1 0x00000040 +#define LINK_IE_GO_U2 0x00000020 +#define LINK_IE_GO_U3 0x00000010 +#define LINK_IE_DISABLE 0x00000008 +#define LINK_IE_INACTIVE 0x00000004 +#define LINK_IE_RECOVERY 0x00000002 +#define LINK_IE_READY 0x00000001 + +/* LINK_INT_FLAG */ +#define LINK_IF_STATE_CHG 0x80000000 +#define LINK_IF_U1_TOUT 0x40000000 +#define LINK_IF_U2_TOUT 0x20000000 +#define LINK_IF_UX_FAIL 0x10000000 +#define LINK_IF_TX_WARMRST 0x08000000 +#define LINK_IF_UX_EXIT_FAIL 0x04000000 +#define LINK_IF_RX_LMP_TOUT 0x00800000 +#define LINK_IF_TX_LMP 0x00400000 +#define LINK_IF_RX_LMP 0x00200000 +#define LINK_IF_RX_DET 0x00100000 +#define LINK_IF_LOOPBACK 0x00080000 +#define LINK_IF_COMPLIANCE 0x00040000 +#define LINK_IF_HPBUF_FULL 0x00020000 +#define LINK_IF_HPBUF_EMPTY 0x00010000 +#define LINK_IF_HOT_RST 0x00008000 +#define LINK_IF_WAKEUP 0x00004000 +#define LINK_IF_WARM_RST 0x00002000 +#define LINK_IF_UX_EXIT 0x00001000 +#define LINK_IF_TXEQ 0x00000800 +#define LINK_IF_TERM_PRES 0x00000400 +#define LINK_IF_UX_REJ 0x00000200 +#define LINK_IF_U3_WK_TOUT 0x00000100 +#define LINK_IF_GO_U0 0x00000080 +#define LINK_IF_GO_U1 0x00000040 +#define LINK_IF_GO_U2 0x00000020 +#define LINK_IF_GO_U3 0x00000010 +#define LINK_IF_DISABLE 0x00000008 +#define LINK_IF_INACTIVE 0x00000004 +#define LINK_IF_RECOVERY 0x00000002 +#define LINK_IF_READY 0x00000001 + +/* LINK_STATUS */ +#define LINK_HPBUF_EMPTY 0x80000000 +#define LINK_HPBUF_FULL 0x40000000 +#define LINK_HPBUF_IDLE 0x20000000 +#define LINK_U3_SLEEP_ALLOW 0x00400000 +#define LINK_U2_SLEEP_ALLOW 0x00200000 +#define LINK_RXDET_SLEEP_ALLOW 0x00100000 +#define LINK_WAKUP 0x00080000 +#define LINK_RX_LFPS 0x00040000 +#define LINK_RX_DETECT 0x00020000 +#define LINK_RX_UX_EXIT_REQ 0x00010000 +#define LINK_STATE_MASK 0x00000F00 + #define LINK_STATE_U0 0x00000000 + #define LINK_STATE_U1 0x00000100 + #define LINK_STATE_U2 0x00000200 + #define LINK_STATE_U3 0x00000300 + #define LINK_STATE_DISABLE 0x00000400 + #define LINK_STATE_RXDET 0x00000500 + #define LINK_STATE_INACTIVE 0x00000600 + #define LINK_STATE_POLLING 0x00000700 + #define LINK_STATE_RECOVERY 0x00000800 + #define LINK_STATE_HOTRST 0x00000900 + #define LINK_STATE_COMPLIANCE 0x00000A00 + #define LINK_STATE_LOOPBACK 0x00000B00 +#define LINK_TXEQ 0x00000040 +#define LINK_PD_MODE_ST_MASK 0x00000030 + #define LINK_PD_MODE_ST_P0 0x00000000 + #define LINK_PD_MODE_ST_P1 0x00000010 + #define LINK_PD_MODE_ST_P2 0x00000020 + #define LINK_PD_MODE_ST_P3 0x00000030 +#define LINK_READY 0x00000008 +#define LINK_BUSY 0x00000004 +#define LINK_RX_WARM_RST 0x00000002 +#define LINK_RX_TERM_PRES 0x00000001 + +/* LINK_LPM_CR */ +#define LINK_LPM_TERM_PRESENT 0x00000800 +#define LINK_LPM_TERM_CHG 0x00000400 +#define LINK_LPM_EN 0x00000200 +#define LINK_LPM_RST 0x00000100 + +/* LINK_PORT_CAP */ +#define LINK_LMP_RX_CAP_VLD 0x80000000 +#define LINK_LMP_TX_CAP_VLD 0x40000000 +#define LINK_SPEED_MASK 0x3F000000 +#define LINK_PORT_CAP_MASK 0x00FFFFFF + +/* USB_CONTROL */ +#define USBSS_DEV_ADDR_MASK 0x7F000000 +#define USBSS_UIE_FIFO_RXOV 0x00800000 +#define USBSS_UIE_FIFO_TXOV 0x00400000 +#define USBSS_UIE_ITP 0x00100000 +#define USBSS_UIE_RX_PING 0x00080000 +#define USBSS_UDIE_STATUS 0x00040000 +#define USBSS_UHIE_NOTIF 0x00040000 +#define USBSS_UDIE_SETUP 0x00020000 +#define USBSS_UHIE_ERDY 0x00020000 +#define USBSS_UIE_TRANSFER 0x00010000 +#define USBSS_CHAIN_CONFLICT 0x00008000 +#define USBSS_TX_ERDY_MODE 0x00004000 +#define USBSS_HP_PEND_MASK 0x00000300 + #define USBSS_HP_PENDING 0x00000200 +#define USBSS_HOST_MODE 0x00000080 +#define USBSS_ITP_EN 0x00000040 +#define USBSS_SETUP_FLOW 0x00000020 +#define USBSS_DIR_ABORT 0x00000010 +#define USBSS_DMA_MODE 0x00000008 +#define USBSS_FORCE_RST 0x00000004 +#define USBSS_USB_CLR_ALL 0x00000002 +#define USBSS_DMA_EN 0x00000001 + +/* USB_STATUS */ +#define USBSS_HRX_RES_MASK 0xC0000000 +#define USBSS_HTX_RES_MASK 0x00C00000 +#define USBSS_EP_DIR_MASK 0x00001000 +#define USBSS_EP_ID_MASK 0x00000700 +#define USBSS_UIF_FIFO_RXOV 0x00000080 +#define USBSS_UIF_FIFO_TXOV 0x00000040 +#define USBSS_UIF_ITP 0x00000010 +#define USBSS_UIF_RX_PING 0x00000008 +#define USBSS_UDIF_STATUS 0x00000004 +#define USBSS_UHIF_NOTIF 0x00000004 +#define USBSS_UDIF_SETUP 0x00000002 +#define USBSS_UHIF_ERDY 0x00000002 +#define USBSS_UIF_TRANSFER 0x00000001 + +/* USB_ITP */ +#define USBSS_ITP_INTERVAL_MASK 0x00003FFF + +/* USB_ITP_ADJ */ +#define USBSS_ITP_DELTA 0x001FFF00 +#define USBSS_ITP_DELAYED 0x00000080 +#define USBSS_ITP_ADJ_CR_MASK 0x0000007F + +/* UEP_TX_EN */ +#define USBSS_EP15_TX_EN 0x00008000 +#define USBSS_EP14_TX_EN 0x00004000 +#define USBSS_EP13_TX_EN 0x00002000 +#define USBSS_EP12_TX_EN 0x00001000 +#define USBSS_EP11_TX_EN 0x00000800 +#define USBSS_EP10_TX_EN 0x00000400 +#define USBSS_EP9_TX_EN 0x00000200 +#define USBSS_EP8_TX_EN 0x00000100 +#define USBSS_EP7_TX_EN 0x00000080 +#define USBSS_EP6_TX_EN 0x00000040 +#define USBSS_EP5_TX_EN 0x00000020 +#define USBSS_EP4_TX_EN 0x00000010 +#define USBSS_EP3_TX_EN 0x00000008 +#define USBSS_EP2_TX_EN 0x00000004 +#define USBSS_EP1_TX_EN 0x00000002 +#define USBSS_UH_TX_EN 0x00000002 + +/* UEP_RX_EN */ +#define USBSS_EP15_RX_EN 0x00008000 +#define USBSS_EP14_RX_EN 0x00004000 +#define USBSS_EP13_RX_EN 0x00002000 +#define USBSS_EP12_RX_EN 0x00001000 +#define USBSS_EP11_RX_EN 0x00000800 +#define USBSS_EP10_RX_EN 0x00000400 +#define USBSS_EP9_RX_EN 0x00000200 +#define USBSS_EP8_RX_EN 0x00000100 +#define USBSS_EP7_RX_EN 0x00000080 +#define USBSS_EP6_RX_EN 0x00000040 +#define USBSS_EP5_RX_EN 0x00000020 +#define USBSS_EP4_RX_EN 0x00000010 +#define USBSS_EP3_RX_EN 0x00000008 +#define USBSS_EP2_RX_EN 0x00000004 +#define USBSS_EP1_RX_EN 0x00000002 +#define USBSS_UH_RX_EN 0x00000002 + +/* UEP0_TX_CTRL */ +#define USBSS_UIF_EP0_TX_ACT 0x80000000 +#define USBSS_EP0_TX_FLOW 0x02000000 +#define USBSS_EP0_TX_PP 0x01000000 +#define USBSS_EP0_TX_ERDY 0x00800000 +#define USBSS_EP0_TX_RES 0x00600000 + #define USBSS_EP0_TX_NRDY 0x00000000 + #define USBSS_EP0_TX_DPH 0x00200000 + #define USBSS_EP0_TX_STALL 0x00400000 +#define USBSS_EP0_TX_SEQ_MASK 0x001F0000 + #define USBSS_NUMP_1 0x00010000 + #define USBSS_NUMP_2 0x00020000 + #define USBSS_NUMP_3 0x00030000 + #define USBSS_NUMP_4 0x00040000 + #define USBSS_NUMP_5 0x00050000 + #define USBSS_NUMP_6 0x00060000 + #define USBSS_NUMP_7 0x00070000 + #define USBSS_NUMP_8 0x00080000 + #define USBSS_NUMP_9 0x00090000 + #define USBSS_NUMP_10 0x000A0000 + #define USBSS_NUMP_11 0x000B0000 + #define USBSS_NUMP_12 0x000C0000 + #define USBSS_NUMP_13 0x000D0000 + #define USBSS_NUMP_14 0x000E0000 + #define USBSS_NUMP_15 0x000F0000 + #define USBSS_NUMP_16 0x00100000 +#define USBSS_EP0_TX_LEN_MASK 0x000007FF + +/* UEP0_RX_CTRL */ +#define USBSS_UIF_EP0_RX_ACT 0x80000000 +#define USBSS_EP0_RX_PP 0x01000000 +#define USBSS_EP0_RX_ERDY 0x00800000 +#define USBSS_EP0_RX_RES 0x00600000 + #define USBSS_EP0_RX_NRDY 0x00000000 + #define USBSS_EP0_RX_ACK 0x00200000 + #define USBSS_EP0_RX_STALL 0x00400000 +#define USBSS_EP0_RX_SEQ_MASK 0x001F0000 +#define USBSS_EP0_RX_LEN_MASK 0x000007FF + +/* R8_UEPn_TX_CFG */ +#define USBSS_EP_TX_CHAIN_AUTO 0x80 +#define USBSS_EP_TX_FIFO_MODE 0x40 +#define USBSS_EP_TX_FIFO_CFG 0x20 +#define USBSS_EP_TX_EOB_MODE 0x08 +#define USBSS_EP_TX_ERDY_AUTO 0x04 +#define USBSS_EP_TX_SEQ_AUTO 0x02 +#define USBSS_EP_TX_ISO_MODE 0x01 + +/* R8_UEPn_TX_CR */ +#define USBSS_EP_TX_HALT 0x80 +#define USBSS_EP_TX_CLR 0x40 +#define USBSS_EP_TX_CHAIN_CLR 0x20 +#define USBSS_EP_TX_ERDY_NUMP_MASK 0x1F + + +/* R8_UEPn_TX_SEQ */ +#define USBSS_EP_TX_SEQ_NUM_MASK 0x1F + +/* R8_UEPn_TX_ST */ +#define USBSS_EP_TX_INT_FLAG 0x80 +#define USBSS_EP_TX_FC_ST 0x40 +#define USBSS_EP_TX_ERDY_REQ 0x20 +#define USBSS_EP_TX_CHAIN_RES 0x10 +#define USBSS_EP_TX_CHAIN_EN_MASK 0x0F + +/* R8_UEPn_TX_CHAIN_CR */ +#define USBSS_EP_TX_CUR_USE 0xC0 +#define USBSS_EP_TX_CUR_CFG 0x30 +#define USBSS_EP_TX_FORCE_RET 0x04 +#define USBSS_EP_TX_RET_SEL 0x03 + +/* R8_UEPn_TX_CHAIN_ST */ +#define USBSS_EP_TX_CHAIN_EN 0x80 +#define USBSS_EP_TX_CHAIN_IF 0x40 +#define USBSS_EP_TX_EOB_LPF 0x20 +#define USBSS_EP_TX_NUMP_EMPTY 0x08 +#define USBSS_EP_TX_DPH_PP 0x04 +#define USBSS_EP_TX_CHAIN_NO_MASK 0x03 + +/* R8_UEPn_RX_CFG */ +#define USBSS_EP_RX_CHAIN_AUTO 0x80 +#define USBSS_EP_RX_FIFO_MODE 0x40 +#define USBSS_EP_RX_FIFO_CFG 0x20 +#define USBSS_EP_RX_EOB_MODE 0x08 +#define USBSS_EP_RX_ERDY_AUTO 0x04 +#define USBSS_EP_RX_SEQ_AUTO 0x02 +#define USBSS_EP_RX_ISO_MODE 0x01 + +/* R8_UEPn_RX_CR */ +#define USBSS_EP_RX_HALT 0x80 +#define USBSS_EP_RX_CLR 0x40 +#define USBSS_EP_RX_CHAIN_CLR 0x20 +#define USBSS_EP_RX_ERDY_NUMP_MASK 0x1F + +/* R8_UEPn_RX_SEQ */ +#define USBSS_EP_RX_SEQ_NUM_MASK 0x1F + +/* R8_UEPn_RX_ST */ +#define USBSS_EP_RX_INT_FLAG 0x80 +#define USBSS_EP_RX_FC_ST 0x40 +#define USBSS_EP_RX_ERDY_REQ 0x20 +#define USBSS_EP_RX_CHAIN_RES 0x10 +#define USBSS_EP_RX_CHAIN_EN_MASK 0x0F + +/* R8_UEPn_RX_CHAIN_CR */ +#define USBSS_EP_RX_CUR_USE 0xC0 +#define USBSS_EP_RX_CUR_CFG 0x30 +#define USBSS_EP_RX_FORCE_RET 0x04 +#define USBSS_EP_RX_RET_SEL 0x03 + +/* R8_UEPn_RX_CHAIN_ST */ +#define USBSS_EP_RX_CHAIN_EN 0x80 +#define USBSS_EP_RX_CHAIN_IF 0x40 +#define USBSS_EP_RX_LPF_FLAG 0x20 +#define USBSS_EP_RX_ISO_PKT_ERR 0x10 +#define USBSS_EP_RX_NUMP_EMPTY 0x08 +#define USBSS_EP_RX_DPH_PP 0x04 +#define USBSS_EP_RX_CHAIN_NO_MASK 0x03 + +/* R32_UH_TX_CTRL */ +#define USBSS_UH_TX_ACT 0x80000000 +#define USBSS_UH_TX_ISO 0x40000000 +#define USBSS_UH_TX_SETUP 0x20000000 +#define USBSS_UH_TX_STATUS 0x10000000 +#define USBSS_UH_TX_LPF 0x00800000 +#define USBSS_UH_TX_RES 0x00600000 + #define USBSS_UH_TX_NRDY 0x00000000 + #define USBSS_UH_TX_ACK 0x00200000 + #define USBSS_UH_TX_STALL 0x00400000 +#define USBSS_UH_TX_SEQ 0x001F0000 +#define USBSS_UH_TX_EP 0x0000F000 +#define USBSS_UH_TX_LEN_MASK 0x000007FF + +/* R32_UH_RX_CTRL */ +#define USBSS_UH_RX_ACT 0x80000000 +#define USBSS_UH_RX_ISO 0x40000000 +#define USBSS_UH_RX_NUMP 0x1F000000 +#define USBSS_UH_RX_RES 0x00600000 + #define USBSS_UH_RX_NRDY 0x00000000 + #define USBSS_UH_RX_ACK 0x00200000 + #define USBSS_UH_RX_STALL 0x00400000 +#define USBSS_UH_RX_SEQ 0x001F0000 +#define USBSS_UH_RX_EP 0x0000F000 +#define USBSS_UH_RX_LEN_MASK 0x000007FF + +/* R32_HOST_STATUS */ +#define USBSS_UH_ITP_PRESAGE 0x000C0000 +#define USBSS_UH_RX_ISO_PKT_ERR 0x00020000 +#define USBSS_UH_RX_EOB_LPF 0x00010000 +#define USBSS_UH_RX_ERDY_DIR 0x00008000 +#define USBSS_UH_RX_ERDY_NUMP 0x00001F00 +#define USBSS_UH_RX_ERDY_EP 0x000000F0 + +/*******************************************************************************/ +/* USBHS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBHS_UD_LPM_EN 0x80 +#define USBHS_UD_DEV_EN 0x20 +#define USBHS_UD_DMA_EN 0x10 +#define USBHS_UD_PHY_SUSPENDM 0x08 +#define USBHS_UD_CLR_ALL 0x04 +#define USBHS_UD_RST_SIE 0x02 +#define USBHS_UD_RST_LINK 0x01 + +/* R8_USB_BASE_MODE */ +#define USBHS_UD_SPEED_FULL 0x00 +#define USBHS_UD_SPEED_HIGH 0x01 +#define USBHS_UD_SPEED_LOW 0x02 +#define USBHS_UD_SPEED_TYPE 0x03 + +/* R8_USB_INT_EN */ +#define USBHS_UDIE_FIFO_OVER 0x80 +#define USBHS_UDIE_LINK_RDY 0x40 +#define USBHS_UDIE_SOF_ACT 0x20 +#define USBHS_UDIE_TRANSFER 0x10 +#define USBHS_UDIE_LPM_ACT 0x08 +#define USBHS_UDIE_BUS_SLEEP 0x04 +#define USBHS_UDIE_SUSPEND 0x02 +#define USBHS_UDIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBHS_UD_DEV_ADDR 0x7F + +/* R8_USB_WAKE_CTRL */ +#define USBHS_UD_REMOTE_WKUP 0x01 + +/* R8_USB_TEST_MODE */ +#define USBHS_UD_TEST_EN 0x80 +#define USBHS_UD_TEST_SE0NAK 0x08 +#define USBHS_UD_TEST_PKT 0x04 +#define USBHS_UD_TEST_K 0x02 +#define USBHS_UD_TEST_J 0x01 + +/* R16_USB_LPM_DATA */ +#define USBHS_UD_LPM_BUSY 0x8000 +#define USBHS_UD_LPM_DATA 0x07FF + +/* R8_USB_INT_FG */ +#define USBHS_UDIF_FIFO_OV 0x80 +#define USBHS_UDIF_LINK_RDY 0x40 +#define USBHS_UDIF_RX_SOF 0x20 +#define USBHS_UDIF_TRANSFER 0x10 +#define USBHS_UDIF_RTX_ACT 0x10 +#define USBHS_UDIF_LPM_ACT 0x08 +#define USBHS_UDIF_BUS_SLEEP 0x04 +#define USBHS_UDIF_SUSPEND 0x02 +#define USBHS_UDIF_BUS_RST 0x01 + +/* R8_USB_INT_ST */ +#define USBHS_UDIS_EP_DIR 0x10 +#define USBHS_UDIS_EP_ID_MASK 0x07 + +/* R8_USB_MIS_ST */ +#define USBHS_UDMS_HS_MOD 0x80 +#define USBHS_UDMS_SUSP_REQ 0x10 +#define USBHS_UDMS_SIE_FREE 0x08 +#define USBHS_UDMS_SLEEP 0x04 +#define USBHS_UDMS_SUSPEND 0x02 +#define USBHS_UDMS_READY 0x01 + +/* R16_USB_FRAME_NO */ +#define USBHS_UD_MFRAME_NO 0xE000 +#define USBHS_UD_FRAME_NO 0x07FF + +/* R16_USB_BUS */ +#define USBHS_USB_DM_ST 0x08 +#define USBHS_USB_DP_ST 0x04 +#define USB_WAKEUP 0x01 + +/* R16_UEP_TX_EN */ +#define USBHS_UEP0_T_EN 0x0001 +#define USBHS_UEP1_T_EN 0x0002 +#define USBHS_UEP2_T_EN 0x0004 +#define USBHS_UEP3_T_EN 0x0008 +#define USBHS_UEP4_T_EN 0x0010 +#define USBHS_UEP5_T_EN 0x0020 +#define USBHS_UEP6_T_EN 0x0040 +#define USBHS_UEP7_T_EN 0x0080 +#define USBHS_UEP8_T_EN 0x0100 +#define USBHS_UEP9_T_EN 0x0200 +#define USBHS_UEP10_T_EN 0x0400 +#define USBHS_UEP11_T_EN 0x0800 +#define USBHS_UEP12_T_EN 0x1000 +#define USBHS_UEP13_T_EN 0x2000 +#define USBHS_UEP14_T_EN 0x4000 +#define USBHS_UEP15_T_EN 0x8000 + +/* R16_UEP_RX_EN */ +#define USBHS_UEP0_R_EN 0x0001 +#define USBHS_UEP1_R_EN 0x0002 +#define USBHS_UEP2_R_EN 0x0004 +#define USBHS_UEP3_R_EN 0x0008 +#define USBHS_UEP4_R_EN 0x0010 +#define USBHS_UEP5_R_EN 0x0020 +#define USBHS_UEP6_R_EN 0x0040 +#define USBHS_UEP7_R_EN 0x0080 +#define USBHS_UEP8_R_EN 0x0100 +#define USBHS_UEP9_R_EN 0x0200 +#define USBHS_UEP10_R_EN 0x0400 +#define USBHS_UEP11_R_EN 0x0800 +#define USBHS_UEP12_R_EN 0x1000 +#define USBHS_UEP13_R_EN 0x2000 +#define USBHS_UEP14_R_EN 0x4000 +#define USBHS_UEP15_R_EN 0x8000 + +/* R16_UEP_T_TOG_AUTO */ +#define USBHS_UEP_T_TOG_AUTO 0xFF + +/* R16_UEP_R_TOG_AUTO */ +#define USBHS_UEP_R_TOG_AUTO 0xFF + +/* R8_UEP_T_BURST */ +#define USBHS_UEP_T_BURST_EN 0xFF + +/* R8_UEP_T_BURST_MODE */ +#define USBHS_UEP_T_BURST_MODE 0xFF + +/* R8_UEP_R_BURST */ +#define USBHS_UEP_R_BURST_EN 0xFF + +/* R8_UEP_R_RES_MODE */ +#define USBHS_UEP_R_RES_MODE 0xFF + +/* R32_UEP_AF_MODE */ +#define USBHS_UEP_T_AF 0xFE + +/* R32_UEP0_DMA */ +#define UEPn_DMA 0xFFFFFF + +/* R32_UEPn_RX_DMA */ +#define UEPn_RX_DMA 0xFFFFFF + +/* R32_UEPn_TX_DMA */ +#define UEPn_TX_DMA 0xFFFFFF + +/* R32_UEPn_MAX_LEN */ +#define USBHS_UEP0_MAX_LEN 0x007F +#define USBHS_UEPn_MAX_LEN 0x07FF + +/* R16_UEPn_RX_LEN */ +#define USBHS_UEP0_RX_LEN 0x007F + +/* R16_UEPn_RX_LEN */ +#define USBHS_UEPn_RX_LEN 0xFFFF + +/* R16_UEPn_R_SIZE */ +#define USBHS_UEPn_R_SIZE 0xFFFF + +/* R16_UEP0_T_LEN */ +#define USBHS_UEP0_T_LEN 0x7F + +/**R16_UEPn_T_LEN**/ +#define USBHS_UEPn_T_LEN 0xFFFF + +/**R8_UEPn_TX_CTRL**/ +#define USBHS_UEP_T_DONE 0x80 +#define USBHS_UEP_T_NAK_ACT 0x40 +#define USBHS_UEP_T_TOG_MASK 0x0C +#define USBHS_UEP_T_TOG_MDATA 0x0C +#define USBHS_UEP_T_TOG_DATA2 0x08 +#define USBHS_UEP_T_TOG_DATA1 0x04 +#define USBHS_UEP_T_TOG_DATA0 0x00 +#define USBHS_UEP_T_RES_MASK 0x03 +#define USBHS_UEP_T_RES_ACK 0x02 +#define USBHS_UEP_T_RES_STALL 0x01 +#define USBHS_UEP_T_RES_NAK 0x00 + +/**R8_UEP0_RX_CTRL**/ + +/**R8_UEPn_RX_CTRL**/ +#define USBHS_UEP_R_DONE 0x80 +#define USBHS_UEP_R_NAK_ACT 0x40 +#define USBHS_UEP_R_NAK_TOG 0x20 +#define USBHS_UEP_R_TOG_MATCH 0x10 +#define USBHS_UEP_R_SETUP_IS 0x08 +#define USBHS_UEP_R_TOG_MASK 0x0C +#define USBHS_UEP_R_TOG_MDATA 0x0C +#define USBHS_UEP_R_TOG_DATA2 0x08 +#define USBHS_UEP_R_TOG_DATA1 0x04 +#define USBHS_UEP_R_TOG_DATA0 0x00 +#define USBHS_UEP_R_RES_MASK 0x03 +#define USBHS_UEP_R_RES_ACK 0x02 +#define USBHS_UEP_R_RES_STALL 0x01 +#define USBHS_UEP_R_RES_NAK 0x00 + +/* R16_UEP_T_ISO */ +#define USBHS_UEP1_T_FIFO_EN 0x0200 +#define USBHS_UEP2_T_FIFO_EN 0x0400 +#define USBHS_UEP3_T_FIFO_EN 0x0800 +#define USBHS_UEP4_T_FIFO_EN 0x1000 +#define USBHS_UEP5_T_FIFO_EN 0x2000 +#define USBHS_UEP6_T_FIFO_EN 0x4000 +#define USBHS_UEP7_T_FIFO_EN 0x8000 +#define USBHS_UEP1_T_ISO_EN 0x0002 +#define USBHS_UEP2_T_ISO_EN 0x0004 +#define USBHS_UEP3_T_ISO_EN 0x0008 +#define USBHS_UEP4_T_ISO_EN 0x0010 +#define USBHS_UEP5_T_ISO_EN 0x0020 +#define USBHS_UEP6_T_ISO_EN 0x0040 +#define USBHS_UEP7_T_ISO_EN 0x0080 + +/* R16_UEP_R_ISO */ +#define USBHS_UEP1_R_FIFO_EN 0x0200 +#define USBHS_UEP2_R_FIFO_EN 0x0400 +#define USBHS_UEP3_R_FIFO_EN 0x0800 +#define USBHS_UEP4_R_FIFO_EN 0x1000 +#define USBHS_UEP5_R_FIFO_EN 0x2000 +#define USBHS_UEP6_R_FIFO_EN 0x4000 +#define USBHS_UEP7_R_FIFO_EN 0x8000 +#define USBHS_UEP1_R_ISO_EN 0x0002 +#define USBHS_UEP2_R_ISO_EN 0x0004 +#define USBHS_UEP3_R_ISO_EN 0x0008 +#define USBHS_UEP4_R_ISO_EN 0x0010 +#define USBHS_UEP5_R_ISO_EN 0x0020 +#define USBHS_UEP6_R_ISO_EN 0x0040 +#define USBHS_UEP7_R_ISO_EN 0x0080 + +/* R32_UEPn_RX_FIFO */ +#define USBHS_UEP_RX_FIFO_E 0xFF00 +#define USBHS_UEP_RX_FIFO_S 0x00FF + +/* R32_UEPn_TX_FIFO */ +#define USBHS_UEP_TX_FIFO_E 0xFF00 +#define USBHS_UEP_TX_FIFO_S 0x00FF + + +/* USB high speed host register */ +/* R8_UH_CFG */ +#define USBHS_UH_LPM_EN 0x80 +#define USBHS_UH_FORCE_FS 0x40 +#define USBHS_UH_SOF_EN 0x20 +#define USBHS_UH_DMA_EN 0x10 +#define USBHS_UH_PHY_SUSPENDM 0x08 +#define USBHS_UH_CLR_ALL 0x04 +#define USBHS_RST_SIE 0x02 +#define USBHS_RST_LINK 0x01 + +/* R8_UH_INT_EN */ +#define USBHS_UHIE_FIFO_OVER 0x80 +#define USBHS_UHIE_TX_HALT 0x40 +#define USBHS_UHIE_SOF_ACT 0x20 +#define USBHS_UHIE_TRANSFER 0x10 +#define USBHS_UHIE_RESUME_ACT 0x08 +#define USBHS_UHIE_WKUP_ACT 0x04 + +/* R8_UH_DEV_AD */ +#define USBHS_UH_DEV_ADDR 0x7F + +/* R32_UH_CONTROL */ +#define USBHS_UH_RX_NO_RES 0x800000 +#define USBHS_UH_TX_NO_RES 0x400000 +#define USBHS_UH_RX_NO_DATA 0x200000 +#define USBHS_UH_TX_NO_DATA 0x100000 +#define USBHS_UH_PRE_PID_EN 0x080000 +#define USBHS_UH_SPLIT_VALID 0x040000 +#define USBHS_UH_LPM_VALID 0x020000 +#define USBHS_UH_HOST_ACTION 0x010000 +#define USBHS_UH_BUF_MODE 0x0400 +#define USBHS_UH_T_TOG_MASK 0x0300 +#define USBHS_UH_T_TOG_MDATA 0x0300 +#define USBHS_UH_T_TOG_DATA2 0x0200 +#define USBHS_UH_T_TOG_DATA1 0x0100 +#define USBHS_UH_T_TOG_DATA0 0x0000 +#define USBHS_UH_T_ENDP_MASK 0xF0 +#define USBHS_UH_T_TOKEN_MASK 0x0F + +/* R8_UH_INT_FLAG */ +#define USBHS_UHIF_FIFO_OVER 0x80 +#define USBHS_UHIF_TX_HALT 0x40 +#define USBHS_UHIF_SOF_ACT 0x20 +#define USBHS_UHIF_TRANSFER 0x10 +#define USBHS_UHIF_RESUME_ACT 0x08 +#define USBHS_UHIF_WKUP_ACT 0x04 + +/* R8_UH_INT_ST */ +#define USBHS_UHIF_PORT_RX_RESUME 0x10 +#define USBHS_UH_R_TOKEN_MASK 0x0F + +/* R8_UH_MIS_ST */ +#define USBHS_UHMS_BUS_SE0 0x80 +#define USBHS_UHMS_BUS_J 0x40 +#define USBHS_UHMS_LINESTATE 0x30 +#define USBHS_UHMS_USB_WAKEUP 0x08 +#define USBHS_UHMS_SOF_ACT 0x04 +#define USBHS_UHMS_SOF_PRE 0x02 +#define USBHS_UHMS_SOF_FREE 0x01 + +/* R32_UH_LPM_DATA */ +#define USBHS_UH_LPM_DATA 0x07FF + +/* R32_UH_SPLIT_DATA */ +#define USBHS_UH_SPLIT_DATA 0x07FFFF + +/* R32_UH_FRAME */ +#define USBHS_UH_SOF_CNT_CLR 0x02000000 +#define USBHS_UH_SOF_CNT_EN 0x01000000 +#define USBHS_UH_MFRAME_NO 0x070000 +#define USBHS_UH_FRAME_NO 0x07FF + +/* R32_UH_TX_LEN */ +#define USBHS_UH_TX_LEN 0x07FF + +/* R32_UH_RX_LEN */ +#define USBHS_UH_RX_LEN 0x07FF + +/* R32_UH_RX_MAX_LEN */ +#define USBHS_UH_RX_MAX_LEN 0x07FF + +/* R32_UH_RX_DMA */ +#define USBHS_R32_UH_RX_DMA 0x01FFFF + +/* R32_UH_TX_DMA */ +#define USBHS_R32_UH_TX_DMA 0x01FFFF + +/* R32_UH_PORT_CTRL */ +#define USBHS_UH_BUS_RST_LONG 0x010000 +#define USBHS_UH_PORT_SLEEP_BESL 0xF000 +#define USBHS_UH_CLR_PORT_SLEEP 0x0100 +#define USBHS_UH_CLR_PORT_CONNECT 0x20 +#define USBHS_UH_CLR_PORT_EN 0x10 +#define USBHS_UH_SET_PORT_SLEEP 0x08 +#define USBHS_UH_CLR_PORT_SUSP 0x04 +#define USBHS_UH_SET_PORT_SUSP 0x02 +#define USBHS_UH_SET_PORT_RESET 0x01 + +/* R8_UH_PORT_CFG */ +#define USBHS_UH_PD_EN 0x80 +#define USBHS_UH_HOST_EN 0x01 + +/* R8_UH_PORT_INT_EN */ +#define USBHS_UHIE_PORT_SLP 0x20 +#define USBHS_UHIE_PORT_RESET 0x10 +#define USBHS_UHIE_PORT_SUSP 0x04 +#define USBHS_UHIE_PORT_EN 0x02 +#define USBHS_UHIE_PORT_CONNECT 0x01 + +/* R8_UH_PORT_TEST_CT */ +#define USBHS_UH_TEST_SE0_NAK 0x10 +#define USBHS_UH_TEST_PACKET 0x08 +#define USBHS_UH_TEST_FORCE_EN 0x04 +#define USBHS_UH_TEST_K 0x02 +#define USBHS_UH_TEST_J 0x01 + +/* R16_UH_PORT_ST */ +#define USBHS_UHIS_PORT_TEST 0x0800 +#define USBHS_UHIS_PORT_SPEED_MASK 0x0600 +#define USBHS_UHIS_PORT_HS 0x0400 +#define USBHS_UHIS_PORT_LS 0x0200 +#define USBHS_UHIS_PORT_FS 0x0000 +#define USBHS_UHIS_PORT_SLP 0x20 +#define USBHS_UHIS_PORT_RST 0x10 +#define USBHS_UHIS_PORT_SUSP 0x04 +#define USBHS_UHIS_PORT_EN 0x02 +#define USBHS_UHIS_PORT_CONNECT 0x01 + +/* R8_UH_PORT_CHG */ +#define USBHS_UHIF_PORT_SLP 0x20 +#define USBHS_UHIF_PORT_RESET 0x10 +#define USBHS_UHIF_PORT_SUSP 0x04 +#define USBHS_UHIF_PORT_EN 0x02 +#define USBHS_UHIF_PORT_CONNECT 0x01 + +/* R32_UH_BC_CTRL */ +#define UDM_VSRC_ACT 0x0400 +#define UDM_BC_VSRC 0x0200 +#define UDP_BC_VSRC 0x0100 +#define BC_AUTO_MODE 0x40 +#define UDM_BC_CMPE 0x20 +#define UDP_BC_CMPE 0x10 +#define UDM_BC_CMPO 0x02 +#define UDP_BC_CMPO 0x01 + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_U_1WIRE_MODE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R32_USB_OTG_CR */ +#define USBFS_CR_SESS_VTH 0x20 +#define USBFS_CR_VBUS_VTH 0x10 +#define USBFS_CR_OTG_EN 0x08 +#define USBFS_CR_IDPU 0x04 +#define USBFS_CR_CHARGE_VBUS 0x02 +#define USBFS_CR_DISCHAR_VBUS 0x01 + +/* R32_USB_OTG_SR */ +#define USBFS_SR_ID_DIG 0x08 +#define USBFS_SR_SESS_END 0x04 +#define USBFS_SR_SESS_VLD 0x02 +#define USBFS_SR_VBUS_VLD 0x01 + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +/* ch32h417_hsadc.h -----------------------------------------------------------*/ + +/* HSADC_First_Conversion_Cycle */ +#define HSADC_First_Conversion_Cycle_8 ((uint32_t)0x00000000) +#define HSADC_First_Conversion_Cycle_9 ((uint32_t)0x00000020) +#define HSADC_First_Conversion_Cycle_10 ((uint32_t)0x00000040) +#define HSADC_First_Conversion_Cycle_11 ((uint32_t)0x00000060) + +/* HSADC_data_size */ +#define HSADC_DataSize_16b ((uint32_t)0x00000000) +#define HSADC_DataSize_8b ((uint32_t)0x00000080) + +/* HSADC_channels */ +#define HSADC_Channel_0 ((uint8_t)0x00) +#define HSADC_Channel_1 ((uint8_t)0x01) +#define HSADC_Channel_2 ((uint8_t)0x02) +#define HSADC_Channel_3 ((uint8_t)0x03) +#define HSADC_Channel_4 ((uint8_t)0x04) +#define HSADC_Channel_5 ((uint8_t)0x05) +#define HSADC_Channel_6 ((uint8_t)0x06) + +/* HSADC_interrupts_definition */ +#define HSADC_IT_EOC ((uint16_t)0x0100) +#define HSADC_IT_DMAEnd ((uint16_t)0x0200) +#define HSADC_IT_BurstEnd ((uint16_t)0x0400) + +/* HSADC_flags_definition */ +#define HSADC_FLAG_EOC ((uint16_t)0x0001) +#define HSADC_FLAG_DMAEnd ((uint16_t)0x0002) +#define HSADC_FLAG_BurstEnd ((uint16_t)0x0004) +#define HSADC_FLAG_RXNE ((uint16_t)0x0008) +#define HSADC_FLAG_DualBufferAddr1 ((uint16_t)0x0010) +#define HSADC_FLAG_FIFO_NE ((uint16_t)0x0100) +#define HSADC_FLAG_FIFO_Full ((uint16_t)0x0200) +#define HSADC_FLAG_FIFO_OV ((uint16_t)0x0400) + +/* ch32h417_hsem.h -----------------------------------------------------------*/ + +/* HSEM_Core_ID */ +#define HSEM_Core_ID_V3F ((uint32_t)0x00000000) +#define HSEM_Core_ID_V5F ((uint32_t)0x00000100) + +/* ch32h417_i3c.h -----------------------------------------------------------*/ + +/* I3C_SDAHoldTime*/ +#define I3C_SDAHoldTime_0_5 ((uint32_t)0x00000000) +#define I3C_SDAHoldTime_1_5 ((uint32_t)0x10000000) + +/* I3C_WaitTime */ +#define I3C_WaitTime_State_0 ((uint32_t)0x00000000) +#define I3C_WaitTime_State_1 ((uint32_t)0x00000100) +#define I3C_WaitTime_State_2 ((uint32_t)0x00000200) +#define I3C_WaitTime_State_3 ((uint32_t)0x00000300) + +/* I3C_IBIPayloadSize */ +#define I3C_IBIPayloadSize_None ((uint32_t)0x00000000) +#define I3C_IBIPayloadSize_1B ((uint32_t)0x00010000) +#define I3C_IBIPayloadSize_2B ((uint32_t)0x00020000) +#define I3C_IBIPayloadSize_3B ((uint32_t)0x00030000) +#define I3C_IBIPayloadSize_4B ((uint32_t)0x00040000) + +/* I3C_DataTurnAroundDuration */ +#define I3C_DataTurnAroundDuration_Mode0 ((uint32_t)0x00000000) +#define I3C_DataTurnAroundDuration_Mode1 ((uint32_t)0x01000000) + +/* I3C_MaxDataSpeed */ +#define I3C_MaxDataSpeed_Format_Mode0 ((uint32_t)0x00000000) +#define I3C_MaxDataSpeed_Format_Mode1 ((uint32_t)0x00000100) +#define I3C_MaxDataSpeed_Format_Mode2 ((uint32_t)0x00000200) +#define I3C_MaxDataSpeed_Format_Mode3 ((uint32_t)0x00000300) + +/* I3C_HandOffActivityState */ +#define I3C_HandOffActivityState_0 ((uint32_t)0x00000000) +#define I3C_HandOffActivityState_1 ((uint32_t)0x00000001) +#define I3C_HandOffActivityState_2 ((uint32_t)0x00000002) +#define I3C_HandOffActivityState_3 ((uint32_t)0x00000003) + +/* I3C_DeviceIndex */ +#define I3C_DeviceIndex_1 ((uint32_t)0x00000001) +#define I3C_DeviceIndex_2 ((uint32_t)0x00000002) +#define I3C_DeviceIndex_3 ((uint32_t)0x00000003) +#define I3C_DeviceIndex_4 ((uint32_t)0x00000004) + +/* I3C_Direction */ +#define I3C_Direction_WR ((uint32_t)0x00000000) +#define I3C_Direction_RD ((uint32_t)0x00010000) + +/* I3C_CONTROLLER MessageType */ +#define I3C_CONTROLLER_MTYPE_RELEASE ((uint32_t)0x00000000) +#define I3C_CONTROLLER_MTYPE_HEADER I3C_CTLR_MTYPE_0 +#define I3C_CONTROLLER_MTYPE_PRIVATE I3C_CTLR_MTYPE_1 +#define I3C_CONTROLLER_MTYPE_DIRECT (I3C_CTLR_MTYPE_1 | I3C_CTLR_MTYPE_0) +#define I3C_CONTROLLER_MTYPE_LEGACY_I2C I3C_CTLR_MTYPE_2 +#define I3C_CONTROLLER_MTYPE_CCC (I3C_CTLR_MTYPE_2 | I3C_CTLR_MTYPE_1) + +/* I3C_EndMode */ +#define I3C_GENERATE_STOP I3C_CTLR_MEND +#define I3C_GENERATE_RESTART ((uint32_t)0x00000000) + +/* I3C_TARGET_MessageType */ +#define I3C_TARGET_MTYPE_HOT_JOIN I3C_CTLR_MTYPE_3 +#define I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CTLR_MTYPE_3 | I3C_CTLR_MTYPE_0) +#define I3C_TARGET_MTYPE_IBI (I3C_CTLR_MTYPE_3 | I3C_CTLR_MTYPE_1) + +/* I3C_PeripheralMode */ +#define PeripheralMode_CONTROLLER ((uint32_t)0x00000000) +#define PeripheralMode_TARGET ((uint32_t)0x00000002) + +/* I3C_RX_FIFO_THRESHOLD */ +#define I3C_RXFIFO_THRESHOLD_1_4 ((uint32_t)0x00000000) +#define I3C_RXFIFO_THRESHOLD_4_4 I3C_CFGR_RXTHRES + +/* I3C_TX_FIFO_THRESHOLD */ +#define I3C_TXFIFO_THRESHOLD_1_4 ((uint32_t)0x00000000) +#define I3C_TXFIFO_THRESHOLD_4_4 I3C_CFGR_TXTHRES + +/* I3C_CONTROL_FIFO_STATE */ +#define I3C_CONTROLFIFO_DISABLE ((uint32_t)0x00000000) +#define I3C_CONTROLFIFO_ENABLE I3C_CFGR_TMODE + +/* I3C_STATUS_FIFO_STATE */ +#define I3C_STATUSFIFO_DISABLE ((uint32_t)0x00000000) +#define I3C_STATUSFIFO_ENABLE I3C_CFGR_SMODE + +/* I3C_flags_definition */ +#define I3C_FLAG_CFEF ((uint32_t)0x00000001) +#define I3C_FLAG_TXFEF ((uint32_t)0x00000002) +#define I3C_FLAG_CFNFF ((uint32_t)0x00000004) +#define I3C_FLAG_SFNEF ((uint32_t)0x00000008) +#define I3C_FLAG_TXFNFF ((uint32_t)0x00000010) +#define I3C_FLAG_RXFNEF ((uint32_t)0x00000020) +#define I3C_FLAG_TXLASTF ((uint32_t)0x00000040) +#define I3C_FLAG_RXLASTF ((uint32_t)0x00000080) +#define I3C_FLAG_FCF ((uint32_t)0x00000200) +#define I3C_FLAG_RXTGTENDF ((uint32_t)0x00000400) +#define I3C_FLAG_ERRF ((uint32_t)0x00000800) +#define I3C_FLAG_IBIF ((uint32_t)0x00008000) +#define I3C_FLAG_IBIENDF ((uint32_t)0x00010000) +#define I3C_FLAG_CRF ((uint32_t)0x00020000) +#define I3C_FLAG_CRUPDF ((uint32_t)0x00040000) +#define I3C_FLAG_HJF ((uint32_t)0x00080000) +#define I3C_FLAG_WKPF ((uint32_t)0x00200000) +#define I3C_FLAG_GETF ((uint32_t)0x00400000) +#define I3C_FLAG_STAF ((uint32_t)0x00800000) +#define I3C_FLAG_DAUPDF ((uint32_t)0x01000000) +#define I3C_FLAG_MWLUPDF ((uint32_t)0x02000000) +#define I3C_FLAG_MRLUPDF ((uint32_t)0x04000000) +#define I3C_FLAG_RSTF ((uint32_t)0x08000000) +#define I3C_FLAG_ASUPDF ((uint32_t)0x10000000) +#define I3C_FLAG_INTUPDF ((uint32_t)0x20000000) +#define I3C_FLAG_DEFF ((uint32_t)0x40000000) +#define I3C_FLAG_GRPF ((uint32_t)0x80000000) + +/* I3C_interrupts_definition */ +#define I3C_IT_CFNFIE ((uint32_t)0x00000004) +#define I3C_IT_SFNEIE ((uint32_t)0x00000008) +#define I3C_IT_TXFNEIE ((uint32_t)0x00000010) +#define I3C_IT_RXFNEIE ((uint32_t)0x00000020) +#define I3C_IT_FCIE ((uint32_t)0x00000200) +#define I3C_IT_RXTGTENDIE ((uint32_t)0x00000400) +#define I3C_IT_ERRIE ((uint32_t)0x00000800) +#define I3C_IT_IBIIE ((uint32_t)0x00008000) +#define I3C_IT_IBIENDIE ((uint32_t)0x00010000) +#define I3C_IT_CRIE ((uint32_t)0x00020000) +#define I3C_IT_HJIE ((uint32_t)0x00080000) +#define I3C_IT_CRUPDIE ((uint32_t)0x00040000) +#define I3C_IT_WKPIE ((uint32_t)0x00200000) +#define I3C_IT_GETIE ((uint32_t)0x00400000) +#define I3C_IT_STAIE ((uint32_t)0x00800000) +#define I3C_IT_DAUPDIE ((uint32_t)0x01000000) +#define I3C_IT_MWLUPDIE ((uint32_t)0x02000000) +#define I3C_IT_MRLUPDIE ((uint32_t)0x04000000) +#define I3C_IT_RSTIE ((uint32_t)0x08000000) +#define I3C_IT_ASUPDIE ((uint32_t)0x10000000) +#define I3C_IT_INTUPDIE ((uint32_t)0x20000000) +#define I3C_IT_DEFIE ((uint32_t)0x40000000) +#define I3C_IT_GRPIE ((uint32_t)0x80000000) + +/* I3C_ERROR */ +#define I3C_ERROR_CE0 ((uint32_t)0x00000000) +#define I3C_ERROR_CE1 ((uint32_t)0x00000001) +#define I3C_ERROR_CE2 ((uint32_t)0x00000002) +#define I3C_ERROR_CE3 ((uint32_t)0x00000003) +#define I3C_ERROR_TE0 ((uint32_t)0x00000008) +#define I3C_ERROR_TE1 ((uint32_t)0x00000009) +#define I3C_ERROR_TE2 ((uint32_t)0x0000000A) +#define I3C_ERROR_TE3 ((uint32_t)0x0000000B) +#define I3C_ERROR_TE4 ((uint32_t)0x0000000C) +#define I3C_ERROR_TE5 ((uint32_t)0x0000000D) +#define I3C_ERROR_TE6 ((uint32_t)0x0000000E) +#define I3C_ERROR_PERR ((uint32_t)0x00000010) +#define I3C_ERROR_STALL ((uint32_t)0x00000020) +#define I3C_ERROR_DOVR ((uint32_t)0x00000040) +#define I3C_ERROR_COVR ((uint32_t)0x00000080) +#define I3C_ERROR_ADDRESS_NACK ((uint32_t)0x00000100) +#define I3C_ERROR_DATA_NACK ((uint32_t)0x00000200) +#define I3C_ERROR_DATA_HAND_OFF ((uint32_t)0x00000400) + +/* ch32h417_lptim.h -----------------------------------------------------------*/ + +/* LPTIM_Clock_Source */ +#define LPTIM_ClockSource_In ((uint32_t)0x00000000) +#define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) + +/* LPTIM_ClockPolarity */ +#define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) +#define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) +#define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) + +/* LPTIM_ClockPrescalerTime */ +#define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) +#define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) +#define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) + +/* LPTIM_TriggerSampleTime */ +#define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) +#define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) +#define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) + +/* LPTIM_ClockPrescaler */ +#define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) +#define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) +#define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) +#define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) +#define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) +#define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) +#define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) +#define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) + +/* LPTIM_TriggerSource */ +#define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) +#define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) +#define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) + +/* LPTIM_ExTriggerPolarity */ +#define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) +#define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) +#define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) +#define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) + +/* LPTIM_OutputPolarity */ +#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) +#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) + +/* LPTIM_UpdateMode */ +#define LPTIM_UpdateMode0 ((uint32_t)0x00000000) +#define LPTIM_UpdateMode1 ((uint32_t)0x00400000) + +/* LPTIM_CountSource */ +#define LPTIM_CountSource_Internal ((uint32_t)0x00000000) +#define LPTIM_CountSource_External ((uint32_t)0x00800000) + +/* LPTIM_InClockSource */ +#define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) +#define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) +#define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) +#define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) + +/* LPTIM_Flag_Definition */ +#define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) +#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) +#define LPTIM_FLAG_UP ((uint32_t)0x00000020) +#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) +#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) +#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) +#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) + +/* LPTIM_Interrupts_Definition */ +#define LPTIM_IT_DOWN ((uint32_t)0x00000040) +#define LPTIM_IT_UP ((uint32_t)0x00000020) +#define LPTIM_IT_ARROK ((uint32_t)0x00000010) +#define LPTIM_IT_CMPOK ((uint32_t)0x00000008) +#define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_IT_ARRM ((uint32_t)0x00000002) +#define LPTIM_IT_CMPM ((uint32_t)0x00000001) + +/* ch32h417_ltdc.h -----------------------------------------------------------*/ + +/* LTDC_HSPolarity */ +#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) +#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL + +/* LTDC_VSPolarity */ +#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) +#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL + +/* LTDC_DEPolarity */ +#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) +#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL + +/* LTDC_PCPolarity */ +#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) +#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL + +/* LTDC_Reload */ +#define LTDC_IMReload LTDC_SRCR_IMR +#define LTDC_VBReload LTDC_SRCR_VBR + + +/* LTDC_Position */ +#define LTDC_POS_CY LTDC_CPSR_CYPOS +#define LTDC_POS_CX LTDC_CPSR_CXPOS + + +/* LTDC_CurrentStatus */ +#define LTDC_CD_VDES LTDC_CDSR_VDES +#define LTDC_CD_HDES LTDC_CDSR_HDES +#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS +#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS + +/* LTDC_Interrupts_definition */ +#define LTDC_IT_LI LTDC_IER_LIE +#define LTDC_IT_FU LTDC_IER_FUIE +#define LTDC_IT_RR LTDC_IER_RRIE + +/* LTDC_Flag_definition */ +#define LTDC_FLAG_LI LTDC_ISR_LIF +#define LTDC_FLAG_FU LTDC_ISR_FUIF +#define LTDC_FLAG_RR LTDC_ISR_RRIF + +/* LTDC_Pixelformat */ +#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) +#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) +#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) +#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) +#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) +#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) +#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) +#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) + +/* LTDC_BlendingFactor1 */ +#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) +#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) + +/* LTDC_BlendingFactor2 */ +#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) +#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) + +/* ch32h417_pioc.h -----------------------------------------------------------*/ + +// Register Bit Attribute / Bit Access Type +// RO: Read Only (internal change) +// RW: Read / Write +// Attribute: master/PIOC + +/* Register name rule: + R32_* for 32 bits register (UINT32,ULONG) + R16_* for 16 bits register (UINT16,USHORT) + R8_* for 8 bits register (UINT8,UCHAR) + RB_* for bit or bit mask of 8 bit register */ + +/* ********************************************************************************************************************* */ + +#define PIOC_SRAM_BASE (0x50040000) // PIOC code RAM base address + +#define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address + +#define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR + +#define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address + +#define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count + +#define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit +#define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag +#define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag +#define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM +#define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2 +#define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1 +#define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0 + +#define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value + + +#define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config + +#define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle +#define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output +#define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1 + +#define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2 + +#define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode +//#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3 +//#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2 +//#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1 +//#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0 +//#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable +//#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable +#define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction +#define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction + +#define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output +#define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input +#define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received +#define RB_PORT_IN1 0x20 // RO/RO, IO1 port input +#define RB_PORT_IN0 0x10 // RO/RO, IO0 port input +#define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input +#define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input +#define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output +#define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output + + +#define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control + +#define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config +#define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect) +#define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD +#define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR +#define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0 +#define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0 +#define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0 +#define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0 +#define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0 + +#define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only + +#define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only + +#define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange + + +#define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3 +#define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0 +#define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1 +#define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2 +#define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3 + +#define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7 +#define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4 +#define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5 +#define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6 +#define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7 + +#define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11 +#define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8 +#define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9 +#define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10 +#define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11 + +#define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15 +#define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12 +#define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13 +#define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14 +#define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15 + +#define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19 +#define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16 +#define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17 +#define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18 +#define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19 + +#define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23 +#define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20 +#define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21 +#define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22 +#define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23 + +#define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27 +#define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24 +#define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25 +#define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26 +#define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27 + +#define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31 +#define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28 +#define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29 +#define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30 +#define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31 + +/* ******************************************************************************************************* */ + +/* PIOC Registers */ +typedef struct +{ + uint32_t RESERVED00; + union { + __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR + struct { + __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address + __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count + __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit + __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value + } ; + } ; + union { + __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config + struct { + __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle + __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2 + __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode + __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output + } ; + } ; + uint32_t RESERVED0C; + uint32_t RESERVED10; + uint32_t RESERVED14; + uint32_t RESERVED18; + union { + __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control + struct { + __IO uint8_t D8_SYS_CFG; // RW/RW, port config + __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only + __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only + __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange + } ; + } ; + union { + __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3 + struct { + __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0 + __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1 + __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2 + __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3 + } ; + __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1 + } ; + union { + __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7 + struct { + __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4 + __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5 + __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6 + __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11 + struct { + __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8 + __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9 + __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10 + __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15 + struct { + __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12 + __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13 + __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14 + __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19 + struct { + __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16 + __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17 + __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18 + __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23 + struct { + __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20 + __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21 + __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22 + __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27 + struct { + __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24 + __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25 + __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26 + __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31 + struct { + __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28 + __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29 + __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30 + __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31 + } ; + } ; +} PIOC_TypeDef; + +#define PIOC ((PIOC_TypeDef *)PIOC_BASE) + +/* ch32h417_qspi.h -----------------------------------------------------------*/ + +/* QSPI_Clock_Mode */ +#define QSPI_CKMode_Mode0 ((uint32_t)0x00000000) +#define QSPI_CKMode_Mode3 ((uint32_t)QSPI_DCR_CKMODE) + +/* QSPI_ChipSelectHighTime */ +#define QSPI_CSHTime_1Cycle ((uint32_t)0x00000000) +#define QSPI_CSHTime_2Cycle ((uint32_t)QSPI_DCR_CSHT_0) +#define QSPI_CSHTime_3Cycle ((uint32_t)QSPI_DCR_CSHT_1) +#define QSPI_CSHTime_4Cycle ((uint32_t)QSPI_DCR_CSHT_0 | QSPI_DCR_CSHT_1) +#define QSPI_CSHTime_5Cycle ((uint32_t)QSPI_DCR_CSHT_2) +#define QSPI_CSHTime_6Cycle ((uint32_t)QSPI_DCR_CSHT_2 | QSPI_DCR_CSHT_0) +#define QSPI_CSHTime_7Cycle ((uint32_t)QSPI_DCR_CSHT_2 | QSPI_DCR_CSHT_1) +#define QSPI_CSHTime_8Cycle ((uint32_t)QSPI_DCR_CSHT) + +/* QSPI_Fash_Select */ +#define QSPI_FSelect_1 ((uint32_t)0x00000000) +#define QSPI_FSelect_2 ((uint32_t)QSPI_CR_FSEL) + +/* QSPI_Dual_Flash */ +#define QSPI_DFlash_Disable ((uint32_t)0x00000000) +#define QSPI_DFlash_Enable ((uint32_t)QSPI_CR_DFM) + +/* QSPI_ComConfig_Functional_Mode */ +#define QSPI_ComConfig_FMode_Indirect_Write ((uint32_t)0x00000000) +#define QSPI_ComConfig_FMode_Indirect_Read ((uint32_t)QSPI_CCR_FMODE_0) +#define QSPI_ComConfig_FMode_Auto_Polling ((uint32_t)QSPI_CCR_FMODE_1) +#define QSPI_ComConfig_FMode_Memory_Mapped ((uint32_t)QSPI_CCR_FMODE) + + +/* QSPI_ComConfig_SendInstructionOnlyOnceMode */ +#define QSPI_ComConfig_SIOOMode_Disable ((uint32_t)0x00000000) +#define QSPI_ComConfig_SIOOMode_Enable ((uint32_t)QSPI_CCR_SIOO) + +/* QSPI_ComConfig_DataMode */ +#define QSPI_ComConfig_DMode_NoData ((uint32_t)0x00000000) +#define QSPI_ComConfig_DMode_1Line ((uint32_t)QSPI_CCR_DMODE_0) +#define QSPI_ComConfig_DMode_2Line ((uint32_t)QSPI_CCR_DMODE_1) +#define QSPI_ComConfig_DMode_4Line ((uint32_t)QSPI_CCR_DMODE) + +/* QSPI_ComConfig_AlternateBytesSize */ +#define QSPI_ComConfig_ABSize_8bit ((uint32_t)0x00000000) +#define QSPI_ComConfig_ABSize_16bit ((uint32_t)QSPI_CCR_ABSIZE_0) +#define QSPI_ComConfig_ABSize_24bit ((uint32_t)QSPI_CCR_ABSIZE_1) +#define QSPI_ComConfig_ABSize_32bit ((uint32_t)QSPI_CCR_ABSIZE) + +/* QSPI_ComConfig_AlternateBytesMode */ +#define QSPI_ComConfig_ABMode_NoAlternateByte ((uint32_t)0x00000000) +#define QSPI_ComConfig_ABMode_1Line ((uint32_t)QSPI_CCR_ABMODE_0) +#define QSPI_ComConfig_ABMode_2Line ((uint32_t)QSPI_CCR_ABMODE_1) +#define QSPI_ComConfig_ABMode_4Line ((uint32_t)QSPI_CCR_ABMODE) + +/* QSPI_ComConfig_AddressSize */ +#define QSPI_ComConfig_ADSize_8bit ((uint32_t)0x00000000) +#define QSPI_ComConfig_ADSize_16bit ((uint32_t)QSPI_CCR_ADSIZE_0) +#define QSPI_ComConfig_ADSize_24bit ((uint32_t)QSPI_CCR_ADSIZE_1) +#define QSPI_ComConfig_ADSize_32bit ((uint32_t)QSPI_CCR_ADSIZE) + +/* QSPI_ComConfig_AddressMode */ +#define QSPI_ComConfig_ADMode_NoAddress ((uint32_t)0x00000000) +#define QSPI_ComConfig_ADMode_1Line ((uint32_t)QSPI_CCR_ADMODE_0) +#define QSPI_ComConfig_ADMode_2Line ((uint32_t)QSPI_CCR_ADMODE_1) +#define QSPI_ComConfig_ADMode_4Line ((uint32_t)QSPI_CCR_ADMODE) + +/* QSPI_ComConfig_InstructionMode */ +#define QSPI_ComConfig_IMode_NoInstruction ((uint32_t)0x00000000) +#define QSPI_ComConfig_IMode_1Line ((uint32_t)QSPI_CCR_IMODE_0) +#define QSPI_ComConfig_IMode_2Line ((uint32_t)QSPI_CCR_IMODE_1) +#define QSPI_ComConfig_IMode_4Line ((uint32_t)QSPI_CCR_IMODE) + + +/* QSPI_Interrupts_definition */ +#define QSPI_IT_TO (uint32_t)(QSPI_CR_TOIE | QSPI_SR_TOF) +#define QSPI_IT_SM (uint32_t)(QSPI_CR_SMIE | QSPI_SR_SMF) +#define QSPI_IT_FT (uint32_t)(QSPI_CR_FTIE | QSPI_SR_FTF) +#define QSPI_IT_TC (uint32_t)(QSPI_CR_TCIE | QSPI_SR_TCF) +#define QSPI_IT_TE (uint32_t)(QSPI_CR_TEIE | QSPI_SR_TEF) + +/* QSPI_Flags_definition */ +#define QSPI_FLAG_TO QSPI_SR_TOF +#define QSPI_FLAG_SM QSPI_SR_SMF +#define QSPI_FLAG_FT QSPI_SR_FTF +#define QSPI_FLAG_TC QSPI_SR_TCF +#define QSPI_FLAG_TE QSPI_SR_TEF +#define QSPI_FLAG_BUSY QSPI_SR_BUSY +#define QSPI_FLAG_IDLE QSPI_SR_IDLEF + +/* QSPI_Polling_Match_Mode */ +#define QSPI_PMM_AND ((uint32_t)0x00000000) +#define QSPI_PMM_OR ((uint32_t)QSPI_CR_PMM) + +/* QSPI_SIOXEN */ +#define QSPI_SIOXEN ((uint32_t)0x00002000) + +/* ch32h417_sai.h -----------------------------------------------------------*/ + +/* SAI_Block_Mode */ +#define SAI_Mode_MasterTx ((uint32_t)0x00000000) +#define SAI_Mode_MasterRx ((uint32_t)0x00000001) +#define SAI_Mode_SlaveTx ((uint32_t)0x00000002) +#define SAI_Mode_SlaveRx ((uint32_t)0x00000003) + +/* SAI_Block_Protocol */ +#define SAI_Free_Protocol ((uint32_t)0x00000000) +#define SAI_SPDIF_Protocol ((uint32_t)SAI_CFGR1_PRTCFG_0) +#define SAI_AC97_Protocol ((uint32_t)SAI_CFGR1_PRTCFG_1) + +/* SAI_Block_Data_Size */ +#define SAI_DataSize_8b ((uint32_t)0x00000040) +#define SAI_DataSize_10b ((uint32_t)0x00000060) +#define SAI_DataSize_16b ((uint32_t)0x00000080) +#define SAI_DataSize_20b ((uint32_t)0x000000A0) +#define SAI_DataSize_24b ((uint32_t)0x000000C0) +#define SAI_DataSize_32b ((uint32_t)0x000000E0) + +/* SAI_Block_MSB_LSB_transmission */ +#define SAI_FirstBit_MSB ((uint32_t)0x00000000) +#define SAI_FirstBit_LSB ((uint32_t)SAI_CFGR1_LSBFIRST) + +/* SAI_Block_Clock_Strobing */ +#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) +#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_CFGR1_CKSTR) + +/* SAI_Block_Synchronization */ +#define SAI_Asynchronous ((uint32_t)0x00000000) +#define SAI_Synchronous ((uint32_t)SAI_CFGR1_SYNCEN_0) + +/* SAI_Block_NoDivider */ +#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) +#define SAI_MasterDivider_Disabled ((uint32_t)SAI_CFGR1_NODIV) + +/* SAI_Block_FS_Definition */ +#define SAI_FS_StartFrame ((uint32_t)0x00000000) +#define I2S_FS_ChannelIdentification ((uint32_t)SAI_FRCR_FSDEF) + +/* SAI_Block_FS_Polarity */ +#define SAI_FS_ActiveLow ((uint32_t)0x00000000) +#define SAI_FS_ActiveHigh ((uint32_t)SAI_FRCR_FSPOL) + +/* SAI_Block_FS_Offset */ +#define SAI_FS_FirstBit ((uint32_t)0x00000000) +#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_FRCR_FSOFF) + +/* SAI_Block_Slot_Size */ +#define SAI_SlotSize_DataSize ((uint32_t)0x00000000) +#define SAI_SlotSize_16b ((uint32_t)0x00000040) +#define SAI_SlotSize_32b ((uint32_t)0x00000080) + +/* SAI_Block_Slot_Active */ +#define SAI_Slot_NotActive ((uint32_t)0x00000000) +#define SAI_SlotActive_0 ((uint32_t)0x00010000) +#define SAI_SlotActive_1 ((uint32_t)0x00020000) +#define SAI_SlotActive_2 ((uint32_t)0x00040000) +#define SAI_SlotActive_3 ((uint32_t)0x00080000) +#define SAI_SlotActive_4 ((uint32_t)0x00100000) +#define SAI_SlotActive_5 ((uint32_t)0x00200000) +#define SAI_SlotActive_6 ((uint32_t)0x00400000) +#define SAI_SlotActive_7 ((uint32_t)0x00800000) +#define SAI_SlotActive_8 ((uint32_t)0x01000000) +#define SAI_SlotActive_9 ((uint32_t)0x02000000) +#define SAI_SlotActive_10 ((uint32_t)0x04000000) +#define SAI_SlotActive_11 ((uint32_t)0x08000000) +#define SAI_SlotActive_12 ((uint32_t)0x10000000) +#define SAI_SlotActive_13 ((uint32_t)0x20000000) +#define SAI_SlotActive_14 ((uint32_t)0x40000000) +#define SAI_SlotActive_15 ((uint32_t)0x80000000) +#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) + +/* SAI_Mono_Streo_Mode */ +#define SAI_MonoMode ((uint32_t)SAI_CFGR1_MONO) +#define SAI_StreoMode ((uint32_t)0x00000000) + +/* SAI_TRIState_Management */ +#define SAI_Output_NotReleased ((uint32_t)0x00000000) +#define SAI_Output_Released ((uint32_t)SAI_CFGR2_TRIS) + +/* SAI_Block_Fifo_Threshold */ +#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) +#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) +#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) +#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) +#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) + +/* SAI_Block_Companding_Mode */ +#define SAI_NoCompanding ((uint32_t)0x00000000) +#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) +#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) +#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) +#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) + +/* SAI_Block_Mute_Value */ +#define SAI_ZeroValue ((uint32_t)0x00000000) +#define SAI_LastSentValue ((uint32_t)SAI_CFGR2_MUTEVAL) + +/* SAI_Block_Interrupts_Definition */ +#define SAI_IT_OVRUDR ((uint32_t)SAI_INTENR_OVRUDRIE) +#define SAI_IT_MUTEDET ((uint32_t)SAI_INTENR_MUTEDETIE) +#define SAI_IT_WCKCFG ((uint32_t)SAI_INTENR_WCKCFGIE) +#define SAI_IT_FREQ ((uint32_t)SAI_INTENR_FREQIE) +#define SAI_IT_CNRDY ((uint32_t)SAI_INTENR_CNRDYIE) +#define SAI_IT_AFSDET ((uint32_t)SAI_INTENR_AFSDETIE) +#define SAI_IT_LFSDET ((uint32_t)SAI_INTENR_LFSDETIE) + +/* SAI_Block_Flags_Definition */ +#define SAI_FLAG_OVRUDR ((uint32_t)SAI_SR_OVRUDR) +#define SAI_FLAG_MUTEDET ((uint32_t)SAI_SR_MUTEDET) +#define SAI_FLAG_WCKCFG ((uint32_t)SAI_SR_WCKCFG) +#define SAI_FLAG_FREQ ((uint32_t)SAI_SR_FREQ) +#define SAI_FLAG_CNRDY ((uint32_t)SAI_SR_CNRDY) +#define SAI_FLAG_AFSDET ((uint32_t)SAI_SR_AFSDET) +#define SAI_FLAG_LFSDET ((uint32_t)SAI_SR_LFSDET) + +/* SAI_Block_Fifo_Status_Level */ +#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) +#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) +#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) +#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) +#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) +#define SAI_FIFOStatus_Full ((uint32_t)0x00050000) + +/* ch32h417_sdmmc.h -----------------------------------------------------------*/ + +/* SDMMC_Mode */ +#define SDMMC_Mode_Host ((uint16_t)0x00000000) +#define SDMMC_Mode_Slave ((uint16_t)SDMMC_SLV_MODE) + +/* SDMMC_PhaseInv */ +#define SDMMC_Phase_No_Inverse ((uint16_t)0x00000000) +#define SDMMC_Phase_Inverse ((uint16_t)SDMMC_PHASEINV) + +/* SDMMC_ClockSpeed */ +#define SDMMC_ClockSpeed_Low ((uint16_t)0x00000000) +#define SDMMC_ClockSpeed_High ((uint16_t)(SDMMC_CLKMode)) + +/* SDMMC_BusWidth */ +#define SDMMC_BusWidth_1 ((uint32_t)0x00000000) +#define SDMMC_BusWidth_4 ((uint32_t)0x00000001) +#define SDMMC_BusWidth_8 ((uint32_t)0x00000002) + +/* SDMMC_ClockEdge */ +#define SDMMC_SampleClock_Rising ((uint8_t)0x00000000) +#define SDMMC_SampleClock_Falling ((uint8_t)SDMMC_NEGSMP) + +/* SDMMC_RespExpect */ +#define SDMMC_Resp_NONE ((uint16_t)0x0000) +#define SDMMC_Resp_136 ((uint16_t)0x00100) +#define SDMMC_Resp_48 ((uint16_t)0x00200) +#define SDMMC_Resp_R1b ((uint16_t)0x00300) + +/* TranMode_Direction */ +#define SDMMC_TranDir_Receive ((uint32_t)0x00000000) +#define SDMMC_TranDir_Send ((uint32_t)SDMMC_DMA_DIR) + +/* DDR_ClockSW_Mode */ +#define SDMMC_DDR_ClockSW_Mode_In ((uint32_t)0x00000000) +#define SDMMC_DDR_ClockSW_Mode_Auto ((uint32_t)0x00080000) +#define SDMMC_DDR_ClockSW_Mode_Force ((uint32_t)0x00100000) + +/* SDMMC_Flags */ +#define SDMMC_FLAG_SLV_BUF_RELEASE ((uint16_t)0x0400) +#define SDMMC_FLAG_SDIOINT ((uint16_t)0x0200) +#define SDMMC_FLAG_FIFO_OV ((uint16_t)0x0100) +#define SDMMC_FLAG_BKGAP ((uint16_t)0x0080) +#define SDMMC_FLAG_TRANDONE ((uint16_t)0x0040) +#define SDMMC_FLAG_TRANERR ((uint16_t)0x0020) +#define SDMMC_FLAG_DATTMO ((uint16_t)0x0010) +#define SDMMC_FLAG_CMDDONE ((uint16_t)0x0008) +#define SDMMC_FLAG_REIDX_ER ((uint16_t)0x0004) +#define SDMMC_FLAG_RECRC_WR ((uint16_t)0x0002) +#define SDMMC_FLAG_RE_TMOUT ((uint16_t)0x0001) + +/* SDMMC_Interrupt_Sources */ +#define SDMMC_IT_SDIOINT ((uint16_t)0x0200) +#define SDMMC_IT_FIFO_OV ((uint16_t)0x0100) +#define SDMMC_IT_BKGAP ((uint16_t)0x0080) +#define SDMMC_IT_TRANDONE ((uint16_t)0x0040) +#define SDMMC_IT_TRANERR ((uint16_t)0x0020) +#define SDMMC_IT_DATTMO ((uint16_t)0x0010) +#define SDMMC_IT_CMDDONE ((uint16_t)0x0008) +#define SDMMC_IT_REIDX_ER ((uint16_t)0x0004) +#define SDMMC_IT_RECRC_WR ((uint16_t)0x0002) +#define SDMMC_IT_RE_TMOUT ((uint16_t)0x0001) + +/* ch32h417_swpmi.h -----------------------------------------------------------*/ + +/* Tx_Buffering_Mode */ +#define SWPMI_TxMode_Buffering_None ((uint32_t)0x0) +#define SWPMI_TxMode_Buffering_Single ((uint32_t)0x2) +#define SWPMI_TxMode_Buffering_Multi ((uint32_t)0xA) + +/* Rx_Buffering_Mode */ +#define SWPMI_RxMode_Buffering_None ((uint32_t)0x0) +#define SWPMI_RxMode_Buffering_Single ((uint32_t)0x1) +#define SWPMI_RxMode_Buffering_Multi ((uint32_t)0x5) + +/* SWPMI interrupts definition */ +#define SWPMI_IT_RXBF ((uint16_t)0x0001) +#define SWPMI_IT_TXBE ((uint16_t)0x0002) +#define SWPMI_IT_RXBER ((uint16_t)0x0004) +#define SWPMI_IT_RXOVR ((uint16_t)0x0008) +#define SWPMI_IT_TXUNR ((uint16_t)0x0010) +#define SWPMI_IT_RXNE ((uint16_t)0x0020) +#define SWPMI_IT_TXE ((uint16_t)0x0040) +#define SWPMI_IT_TC ((uint16_t)0x0080) +#define SWPMI_IT_SR ((uint16_t)0x0100) +#define SWPMI_IT_RDY ((uint16_t)0x0800) + +/* SWPMI flags definition */ +#define SWPMI_FLAG_RXBF ((uint16_t)0x0001) +#define SWPMI_FLAG_TXBE ((uint16_t)0x0002) +#define SWPMI_FLAG_RXBER ((uint16_t)0x0004) +#define SWPMI_FLAG_RXOVR ((uint16_t)0x0008) +#define SWPMI_FLAG_TXUNR ((uint16_t)0x0010) +#define SWPMI_FLAG_RXNE ((uint16_t)0x0020) +#define SWPMI_FLAG_TXE ((uint16_t)0x0040) +#define SWPMI_FLAG_TC ((uint16_t)0x0080) +#define SWPMI_FLAG_SR ((uint16_t)0x0100) +#define SWPMI_FLAG_SUSP ((uint16_t)0x0200) +#define SWPMI_FLAG_DEACT ((uint16_t)0x0400) +#define SWPMI_FLAG_RDY ((uint16_t)0x0800) + +/* ch32h417_usbpd.h -----------------------------------------------------------*/ + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ +#define USBPD_IN_HVT (1<<9) +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_3 +#define PIN_CC2 GPIO_Pin_4 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ +#define UPD_TMR_TX_120M (200-1) /* timer value for USB PD BMC transmittal @Fsys=120MHz */ +#define UPD_TMR_RX_120M (300-1) /* timer value for USB PD BMC receiving @Fsys=120MHz */ +#define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ +#define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + +/* ch32h417_hsem.c -----------------------------------------------------------*/ + +/* HSEM Key */ +#define HSEM_KEY (0x5AA50000) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. +#define DMDATA0 ((volatile uint32_t*)0xe0000340) +#define DMDATA1 ((volatile uint32_t*)0xe0000344) +#define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000348)// Reads as 0x00000000 if debugger is attached. + +// Determination of PLL multiplication factor for non-V003 chips +#if !defined(FUNCONF_SYSTEM_CORE_CLOCK) + #define PLL_MULTIPLICATION ((uint32_t)0) +#elif defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL + #if FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMUL4 + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMUL6 + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMUL7 + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMUL8 + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMUL9 + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMUL10 + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMUL11 + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMUL12 + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMUL13 + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMUL14 + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMUL15 + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMUL16 + #elif FUNCONF_PLL_MULTIPLIER == 17 + #define PLL_MULTIPLICATION RCC_PLLMUL17 + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMUL18 + #elif FUNCONF_PLL_MULTIPLIER == 19 + #define PLL_MULTIPLICATION RCC_PLLMUL19 + #elif FUNCONF_PLL_MULTIPLIER == 20 + #define PLL_MULTIPLICATION RCC_PLLMUL20 + #elif FUNCONF_PLL_MULTIPLIER == 22 + #define PLL_MULTIPLICATION RCC_PLLMUL22 + #elif FUNCONF_PLL_MULTIPLIER == 24 + #define PLL_MULTIPLICATION RCC_PLLMUL24 + #elif FUNCONF_PLL_MULTIPLIER == 26 + #define PLL_MULTIPLICATION RCC_PLLMUL26 + #elif FUNCONF_PLL_MULTIPLIER == 28 + #define PLL_MULTIPLICATION RCC_PLLMUL28 + #elif FUNCONF_PLL_MULTIPLIER == 30 + #define PLL_MULTIPLICATION RCC_PLLMUL30 + #elif FUNCONF_PLL_MULTIPLIER == 32 + #define PLL_MULTIPLICATION RCC_PLLMUL32 + #elif FUNCONF_PLL_MULTIPLIER == 34 + #define PLL_MULTIPLICATION RCC_PLLMUL34 + #elif FUNCONF_PLL_MULTIPLIER == 36 + #define PLL_MULTIPLICATION RCC_PLLMUL36 + #elif FUNCONF_PLL_MULTIPLIER == 38 + #define PLL_MULTIPLICATION RCC_PLLMUL38 + #elif FUNCONF_PLL_MULTIPLIER == 40 + #define PLL_MULTIPLICATION RCC_PLLMUL40 + #elif FUNCONF_PLL_MULTIPLIER == 59 + #define PLL_MULTIPLICATION RCC_PLLMUL59 + #else + #error "Invalid PLL multiplier" + #endif +#endif + + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF_V3F (1<<0) +#define SYSTICK_SR_SWIE (1<<31) +#define SYSTICK_SR_CNTIF_V5F (1<<1) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY3 ((uint32_t)0xBEEF0080) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 + +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 + +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 + +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 + +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 + +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF10 90 +#define PF11 91 +#define PF12 92 +#define PF13 93 +#define PF14 94 +#define PF15 95 + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 1 +#define GPIO_CNF_OUT_OD 5 +#define GPIO_CNF_OUT_PP_AF 9 +#define GPIO_CNF_OUT_OD_AF 13 + +typedef enum +{ GPIO_Mode_AIN = GPIO_CNF_IN_ANALOG, + GPIO_Mode_IN_FLOATING = GPIO_CNF_IN_FLOATING, + GPIO_Mode_IPUPD = GPIO_CNF_IN_PUPD, + GPIO_Mode_Out_OD = GPIO_CNF_OUT_OD, + GPIO_Mode_Out_PP = GPIO_CNF_OUT_PP, + GPIO_Mode_AF_OD = GPIO_CNF_OUT_OD_AF, + GPIO_Mode_AF_PP = GPIO_CNF_OUT_PP_AF +} GPIOMode_TypeDef; + +#define __DTCM __attribute__((section(".dtcm"))) +#define __ITCM __attribute__((section(".itcm"))) + +typedef int (*v5f_main)(void); + +void StartV5F(v5f_main function); + +/* +* This file contains various parts of the official WCH EVT Headers which +* were originally under a restrictive license. +* +* The collection of this file was generated by +* cnlohr, 2023-02-18 and +* AlexanderMandera, 2023-06-23 +* It was significantly reworked into several files cnlohr, 2025-01-29 +* +* While originally under a restrictive copyright, WCH has approved use +* under MIT-licensed use, because of inclusion in Zephyr, as well as other +* open-source licensed projects. +* +* These copies of the headers from WCH are available now under: +* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the “Softwareâ€), to +* deal in the Software without restriction, including without limitation the +* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +* sell copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +* IN THE SOFTWARE. +*/ + +#endif // Header guard diff --git a/inc/ch32l103hw.h b/inc/ch32l103hw.h new file mode 100644 index 0000000..dc4ab82 --- /dev/null +++ b/inc/ch32l103hw.h @@ -0,0 +1,9094 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + LPTIMWakeUp_IRQn = 58, /* LPTIM WakeUp Interrupt */ + USBFS_IRQn = 59, /* USBFS global Interrupt */ + USBFSWakeUp_IRQn = 60, /* USBFS WakeUp Interrupt */ + USART4_IRQn = 61, /* USART4 global Interrupt */ + DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ + LPTIM_IRQn = 63, /* LPTIM global Interrupt */ + OPA_IRQn = 64, /* OPA global Interrupt */ + USBPD_IRQn = 65, /* USBPD global Interrupt */ + + USBPDWakeUp_IRQn = 67, /* USBPD WakeUp Interrupt */ + CMPWakeUp_IRQn = 68, /* CMP WakeUp Interrupt */ + +} IRQn_Type; + +#define BASE_VECTOR "\n\ + .balign 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0 \n\ + .word NMI_Handler /* NMI */ \n\ + .word HardFault_Handler /* Hard Fault */ \n\ + .word 0 \n\ + .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\ + .word 0 \n\ + .word 0 \n\ + .word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\ + .word Break_Point_Handler /* Break Point */ \n\ + .word 0 \n\ + .word 0 \n\ + .word SysTick_Handler /* SysTick */ \n \ + .word 0 \n \ + .word SW_Handler /* SW */ \n \ + .word 0 \n \ + /* External Interrupts */ \n \ + .word WWDG_IRQHandler /* Window Watchdog */ \n \ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n \ + .word TAMPER_IRQHandler /* TAMPER */ \n \ + .word RTC_IRQHandler /* RTC */ \n \ + .word FLASH_IRQHandler /* Flash */ \n \ + .word RCC_IRQHandler /* RCC */ \n \ + .word EXTI0_IRQHandler /* EXTI Line 0 */ \n \ + .word EXTI1_IRQHandler /* EXTI Line 1 */ \n \ + .word EXTI2_IRQHandler /* EXTI Line 2 */ \n \ + .word EXTI3_IRQHandler /* EXTI Line 3 */ \n \ + .word EXTI4_IRQHandler /* EXTI Line 4 */ \n \ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n \ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n \ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n \ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n \ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n \ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n \ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n \ + .word ADC1_2_IRQHandler /* ADC1_2 */ \n \ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ \n \ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ \n \ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \n \ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n \ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ \n \ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n \ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n \ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n \ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n \ + .word TIM2_IRQHandler /* TIM2 */ \n \ + .word TIM3_IRQHandler /* TIM3 */ \n \ + .word TIM4_IRQHandler /* TIM4 */ \n \ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n \ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n \ + .word I2C2_EV_IRQHandler /* I2C2 Event */ \n \ + .word I2C2_ER_IRQHandler /* I2C2 Error */ \n \ + .word SPI1_IRQHandler /* SPI1 */ \n \ + .word SPI2_IRQHandler /* SPI2 */ \n \ + .word USART1_IRQHandler /* USART1 */ \n \ + .word USART2_IRQHandler /* USART2 */ \n \ + .word USART3_IRQHandler /* USART3 */ \n \ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ \n \ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n \ + .word LPTIMWakeUp_IRQHandler /* LPTIM Wake up from suspend */ \n \ + .word USBFS_IRQHandler /* USBFS Break */ \n \ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ \n \ + .word USART4_IRQHandler /* USART4 */ \n \ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel 8 global Interrupt */ \n\ + .word LPTIM_IRQHandler /* LPTIM global Interrupt */ \n \ + .word OPA_IRQHandler /* OPA global Interrupt */ \n \ + .word USBPD_IRQHandler /* USBPD global Interrupt */ \n \ + .word USBPD_WKUP_IRQHandler /* USBPD WakeUp Interrupt */ \n \ + .word CMPWakeUp_IRQHandler /* CMP WakeUp Interrupt */ \n" + +#define EXTRA_VECTOR "" + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR EXTRA_VECTOR "\n.option pop;\n" + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + #define ADC1_2_IRQn ADC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CFG; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + __IO uint32_t TERR_CNT; + __IO uint32_t CANFD_CR; + __IO uint32_t CANFD_BTR; + __IO uint32_t CANFD_TDCT; + __IO uint32_t CANFD_PSR; + __IO uint32_t CANFD_DMA_T[3]; + __IO uint32_t CANFD_DMA_R[2]; + uint32_t RESERVED0[76]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + __IO uint32_t CR; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR_TIM4; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR_TIM4; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR_TIM4; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR_TIM4; + __IO uint32_t CH4CVR; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint32_t DMAADR; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t OPCMKEY; +} OPA_TypeDef; + +/* LPTIM Registers */ +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t CFGR; + __IO uint32_t CR; + __IO uint16_t CMP; + uint16_t RESERVED0; + __IO uint16_t ARR; + uint16_t RESERVED1; + __IO uint16_t CNT; + uint16_t RESERVED2; +} LPTIM_TypeDef; + +/* PD Registers */ +typedef struct +{ + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + __IO uint16_t BMC_TX_SZ; + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + __IO uint16_t BMC_BYTE_CNT; + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + __IO uint16_t DMA; + __IO uint16_t RESERVED; +} USBPD_TypeDef; + +/* USBD Full-Speed Device, Chapter 21. + NOTE: USBD and CAN controller share a dedicated 512-byte SRAM area for data + transmission and reception in the design, so when using USBD and CAN functions + at the same time, this shared area needs to be allocated reasonably to prevent + data conflicts. */ + +typedef struct +{ + __IO uint32_t ADDn_TX; + __IO uint32_t COUNTn_TX; + __IO uint32_t ADDn_RX; + __IO uint32_t COUNTn_RX; +} USBD_BTABLE_TypeDef; + +typedef struct +{ + __IO uint32_t EPR[8]; + __IO uint32_t RESERVED[8]; + __IO uint32_t CNTR; + __IO uint32_t ISTR; + __IO uint32_t FNR; + __IO uint32_t DADDR; + __IO uint32_t BTABLE; +} USBD_TypeDef; + +#define CAN_USBD_SHARED_BASE ((PERIPH_BASE + 0x6000)) +#define USBD_BASE ((PERIPH_BASE + 0x5C00)) + +/* USBD_CNTR */ +#define USBD_CTRM (1<<15) +#define USBD_PMAOVRM (1<<14) +#define USBD_ERRM (1<<13) +#define USBD_WKUPM (1<<12) +#define USBD_SUSPM (1<<11) +#define USBD_RESETM (1<<10) +#define USBD_SOFM (1<<9) +#define USBD_ESOFM (1<<8) +#define USBD_RESUME (1<<4) +#define USBD_FSUP (1<<3) +#define USBD_LPMODE (1<<2) +#define USBD_PDWN (1<<1) +#define USBD_FRES (1<<0) + +/* USBD_ISTR */ +#define USBD_CTR (1<<15) +#define USBD_PMAOVR (1<<14) +#define USBD_ERR (1<<13) +#define USBD_WKUP (1<<12) +#define USBD_SUSP (1<<11) +#define USBD_RESET (1<<10) +#define USBD_SOF (1<<9) +#define USBD_ESOF (1<<8) +#define USBD_DIR (1<<4) +#define USBD_EP_ID (0xf) + +/* USBD_FNR */ +#define USBD_RXDP (1<<15) +#define USBD_RXDM (1<<14) +#define USBD_LCK (1<<13) +#define USBD_LSOF (3<<11) +#define USBD_FN (0x7ff) + +/* USBD_DADDR */ +#define USBD_EF (1<<7) +#define USBD_ADD (0x7f) + +/* USBD_EPRx */ +#define USBD_CTR_RX (1<<15) +#define USBD_DTOG_RX (1<<14) +#define USBD_STAT_RX (3<<12) +#define USBD_SETUP (1<<11) +#define USBD_EPTYPE (3<<9) +#define USBD_EPKIND (1<<8) +#define USBD_CTR_TX (1<<7) +#define USBD_DTOG_TX (1<<6) +#define USBD_STAT_TX (3<<4) +#define USBD_EA (0xf) + +/* USBD_COUNTx_RX */ +#define USBD_BLSIZE (1<<15) +#define USBD_NUM_BLOCK (0x1f<<10) +#define USBD_COUNTx_RX 0x2ff + + +#define USBD ((USBD_TypeDef *) USBD_BASE) + +/* USB-FS-OTG Registers, Chapter 23. */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSD_TypeDef; + +/* R8_USB_CTRL */ +#define USBOTG_UC_HOST_MODE (1<<7) +#define USBOTG_UC_LOW_SPEED (1<<6) +#define USBOTG_UC_DEV_PU_EN (1<<5) +#define USBOTG_UC_SYS_CTRL (1<<4) +#define USBOTG_UC_INT_BUSY (1<<3) +#define USBOTG_UC_RESET_SIE (1<<2) +#define USBOTG_UC_CLR_ALL (1<<1) +#define USBOTG_UC_DMA_EN (1<<0) + +/* R8_USB_INT_EN */ +#define USBOTG_UIE_DEV_NAK (1<<6) +#define USBOTG_UIE_FIFO_OV (1<<4) +#define USBOTG_UIE_HST_SOF (1<<3) +#define USBOTG_UIE_SUSPEND (1<<2) +#define USBOTG_UIE_TRANSFER (1<<1) +#define USBOTG_UIE_DETECT (1<<0) +#define USBOTG_UIE_BUS_RST (1<<0) + +/* R8_USB_DEV_AD */ +#define USBOTG_UDA_GP_BIT (1<<7) +#define USBOTG_USB_ADDR (1<<6) + +/* R8_USB_MIS_ST */ +#define USBOTG_UMS_SOF_PRES (1<<7) +#define USBOTG_UMS_SOF_ACT (1<<6) +#define USBOTG_UMS_SIE_FREE (1<<5) +#define USBOTG_UMS_R_FIFO_RDY (1<<4) +#define USBOTG_UMS_BUS_RESET (1<<3) +#define USBOTG_UMS_SUSPEND (1<<2) +#define USBOTG_UMS_DM_LEVEL (1<<1) +#define USBOTG_UMS_DEV_ATTACH (1<<0) + +/* R8_USB_INT_FG */ +#define USBOTG_U_IS_NAK (1<<7) +#define USBOTG_U_TOG_OK (1<<6) +#define USBOTG_U_SIE_FREE (1<<5) +#define USBOTG_UIF_FIFO_OV (1<<4) +#define USBOTG_UIF_HST_SOF (1<<3) +#define USBOTG_UIF_SUSPEND (1<<2) +#define USBOTG_UIF_TRANSFER (1<<1) +#define USBOTG_UIF_DETECT (1<<0) +#define USBOTG_UIF_BUS_RST (1<<0) + +/* R8_USB_INT_ST */ +#define USBOTG_UIS_IS_NAK (1<<7) +#define USBOTG_UIS_TOG_OK (1<<6) +#define USBOTG_UIS_TOKEN (3<<4) +#define USBOTG_UIS_ENDP 0xf +#define USBOTG_UIS_H_RES 0xf + +/* R32_USB_OTG_CR */ +#define USBOTG_CR_SESS_VTH (1<<5) +#define USBOTG_CR_VBUS_VTH (1<<4) +#define USBOTG_CR_OTG_EN (1<<3) +#define USBOTG_CR_IDPU (1<<2) +#define USBOTG_CR_CHARGE_VBUS (1<<1) +#define USBOTG_CR_DISCHAR_VBUS (1<<0) + +/* R32_USB_OTG_SR */ +#define USBOTG_SR_ID_DIG (1<<3) +#define USBOTG_SR_SESS_END (1<<2) +#define USBOTG_SR_SESS_VLD (1<<1) +#define USBOTG_SR_VBUS_VLD (1<<0) + +/* R8_UEPn_TX_CTRL */ +#define USBOTG_UEP_T_AUTO_TOG (1<<3) +#define USBOTG_UEP_T_TOG (1<<2) +#define USBOTG_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBOTG_UEP_T_RES_ACK (0<<1) +#define USBOTG_UEP_T_RES_NONE (1<<0) +#define USBOTG_UEP_T_RES_NAK (1<<1) +#define USBOTG_UEP_T_RES_STALL (3<<0) + +#define USBOTG_UEP_R_AUTO_TOG (1<<3) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBOTG_UEP_R_TOG (1<<2) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBOTG_UEP_R_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBOTG_UEP_R_RES_ACK (0<<1) +#define USBOTG_UEP_R_RES_NONE (1<<0) +#define USBOTG_UEP_R_RES_NAK (1<<1) +#define USBOTG_UEP_R_RES_STALL (3<<0) + + + +/* R8_UEPn_ RX_CTRL */ +#define USBOTG_UEP_R_AUTO_TOG (1<<3) +#define USBOTG_UEP_R_TOG (1<<2) +#define USBOTG_UEP_R_RES (3<<0) + +/* R8_UEP7_MOD */ +#define USBOTG_UEP7_RX_EN (1<<3) +#define USBOTG_UEP7_TX_EN (1<<2) +#define USBOTG_UEP7_BUF_MOD (1<<0) + +/* R8_UEP5_6_MOD */ +#define USBOTG_UEP6_RX_EN (1<<7) +#define USBOTG_UEP6_TX_EN (1<<6) +#define USBOTG_UEP6_BUF_MOD (1<<4) +#define USBOTG_UEP5_RX_EN (1<<3) +#define USBOTG_UEP5_TX_EN (1<<2) +#define USBOTG_UEP5_BUF_MOD (1<<0) + +/* R8_UEP2_3_MOD */ +#define USBOTG_UEP3_RX_EN (1<<7) +#define USBOTG_UEP3_TX_EN (1<<6) +#define USBOTG_UEP3_BUF_MOD (1<<4) +#define USBOTG_UEP2_RX_EN (1<<3) +#define USBOTG_UEP2_TX_EN (1<<2) +#define USBOTG_UEP2_BUF_MOD (1<<0) + +/* R8_UEP4_1_MOD */ +#define USBOTG_UEP1_RX_EN (1<<7) +#define USBOTG_UEP1_TX_EN (1<<6) +#define USBOTG_UEP1_BUF_MOD (1<<4) +#define USBOTG_UEP4_RX_EN (1<<3) +#define USBOTG_UEP4_TX_EN (1<<2) +#define USBOTG_UEP4_BUF_MOD (1<<0) + +/* R8_UDEV_CTRL */ +#define USBOTG_UD_PD_DIS (1<<7) +#define USBOTG_UD_DP_PIN (1<<5) +#define USBOTG_UD_DM_PIN (1<<4) +#define USBOTG_UD_LOW_SPEED (1<<2) +#define USBOTG_UD_GP_BIT (1<<1) +#define USBOTG_UD_PORT_EN (1<<0) + + +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ +#define UEP_SIZE 64 + +#define DEF_UEP_IN 0x80 +#define DEF_UEP_OUT 0x00 +#define DEF_UEP_BUSY 0x01 +#define DEF_UEP_FREE 0x00 + +#define DEF_UEP0 0 +#define DEF_UEP1 1 +#define DEF_UEP2 2 +#define DEF_UEP3 3 +#define DEF_UEP4 4 +#define DEF_UEP5 5 +#define DEF_UEP6 6 +#define DEF_UEP7 7 +#define UNUM_EP 8 + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSH_TypeDef; + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif // !__ASSEMBLER__ + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define USART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define LPTIM_BASE (APB1PERIPH_BASE + 0x7C00) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ + +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x6000) +#define USBPD_BASE (AHBPERIPH_BASE + 0x7000) + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ + +#define TS_BASE ((uint32_t)0x1FFFF720) +#define OPA_TRIM_BASE ((uint32_t)0x1FFFF724) +#define ADC_TRIM_BASE ((uint32_t)0x1FFFF728) +#define HSI_LP_TRIM_BASE ((uint32_t)0x1FFFF72A) +#define CHIPID_BASE ((uint32_t)0x1FFFF704) +#define USBPD_CFG_BASE ((uint32_t)0x1FFFF730) + + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + + + + + + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define LPTIM ((LPTIM_TypeDef *)LPTIM_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ +#define ADC_RDISCEN ADC_DISCEN + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) +#define ADC_TK1TUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) /* PGA[1:0] bits */ +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP18 ((uint32_t)0x07000000) /* SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMP18_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP18_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP18_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ + +/******************** Bit definition for ADC_CFG register ********************/ +#define ADC_BUFTRIM ((uint32_t)0x0000000F) /* BUFTRIM[3:0] bits */ +#define ADC_BUFTRIM_0 ((uint32_t)0x00000001) +#define ADC_BUFTRIM_1 ((uint32_t)0x00000002) +#define ADC_BUFTRIM_2 ((uint32_t)0x00000004) +#define ADC_BUFTRIM_3 ((uint32_t)0x00000008) + +#define ADC_AWDRST_EN ((uint32_t)0x00000010) +#define ADC_LP ((uint32_t)0x00000020) +#define ADC_FIFO_EN ((uint32_t)0x00000040) +#define ADC_DUTY_EN ((uint32_t)0x00000080) +#define ADC_TKEY_DRV_EN ((uint32_t)0x00000100) + +#define ADC_TKEY_DRV_OUTEN ((uint32_t)0x0007FE00) /* TKEY_DRV_OUTEN[9:0] bits */ +#define ADC_TKEY_DRV_OUTEN_0 ((uint32_t)0x00000200) +#define ADC_TKEY_DRV_OUTEN_1 ((uint32_t)0x00000400) +#define ADC_TKEY_DRV_OUTEN_2 ((uint32_t)0x00000800) +#define ADC_TKEY_DRV_OUTEN_3 ((uint32_t)0x00001000) +#define ADC_TKEY_DRV_OUTEN_4 ((uint32_t)0x00002000) +#define ADC_TKEY_DRV_OUTEN_5 ((uint32_t)0x00004000) +#define ADC_TKEY_DRV_OUTEN_6 ((uint32_t)0x00008000) +#define ADC_TKEY_DRV_OUTEN_7 ((uint32_t)0x00010000) +#define ADC_TKEY_DRV_OUTEN_8 ((uint32_t)0x00020000) +#define ADC_TKEY_DRV_OUTEN_9 ((uint32_t)0x00040000) + +#define ADC_TKEY_SEL ((uint32_t)0x00180000) /* TKEY_SEL[1:0] bits */ +#define ADC_TKEY_SEL_0 ((uint32_t)0x00080000) +#define ADC_TKEY_SEL_1 ((uint32_t)0x00080000) + +#define ADC_TKEY_WAKE_EN ((uint32_t)0x8FE00000) /* TKEY_WAKE_EN[9:0] bits */ +#define ADC_TKEY_WAKE_EN_0 ((uint32_t)0x00200000) +#define ADC_TKEY_WAKE_EN_1 ((uint32_t)0x00400000) +#define ADC_TKEY_WAKE_EN_2 ((uint32_t)0x00800000) +#define ADC_TKEY_WAKE_EN_3 ((uint32_t)0x01000000) +#define ADC_TKEY_WAKE_EN_4 ((uint32_t)0x02000000) +#define ADC_TKEY_WAKE_EN_5 ((uint32_t)0x04000000) +#define ADC_TKEY_WAKE_EN_6 ((uint32_t)0x08000000) +#define ADC_TKEY_WAKE_EN_7 ((uint32_t)0x10000000) +#define ADC_TKEY_WAKE_EN_8 ((uint32_t)0x20000000) +#define ADC_TKEY_WAKE_EN_9 ((uint32_t)0x40000000) + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x00010000) /* CAN controller operating state selection during debugging */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/******************** Bit definition for CAN_TTCTLR register *******************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************** Bit definition for CAN_TTCNT register *******************/ +#define CAN_TTCNT ((uint32_t)0x0000FFFF) + +/******************** Bit definition for CAN_TERR_CNT register *******************/ +#define CAN_TERR_CNT ((uint32_t)0x000001FF) + +/******************** Bit definition for CANFD_CR register *******************/ +#define CANFD_CR_TX_FD ((uint32_t)0x00000001) +#define CANFD_CR_TX_BRS_B ((uint32_t)0x0000000E) +#define CANFD_CR_USER_ESI_B ((uint32_t)0x00000070) +#define CANFD_CR_RES_EXCEPT ((uint32_t)0x00000080) +#define CANFD_CR_CLAS_LONG_TS1 ((uint32_t)0x00000100) +#define CANFD_CR_RESTRICT_MODE ((uint32_t)0x00000200) + +/******************** Bit definition for CANFD_BTR register *******************/ +#define CANFD_BTR_BTR_SJW_FD ((uint32_t)0x0000000F) +#define CANFD_BTR_BTR_TS2_FD ((uint32_t)0x000000F0) +#define CANFD_BTR_BTR_TS1_FD ((uint32_t)0x00001F00) +#define CANFD_BTR_BTR_BRP_FD ((uint32_t)0x001F0000) +#define CANFD_BTR_BTR_TDCE ((uint32_t)0x00800000) + +/******************** Bit definition for CANFD_TDCT register *******************/ +#define CANFD_TDCT_TDCO ((uint32_t)0x0000003F) +#define CANFD_TDCT_TDC_FILTER ((uint32_t)0x00003F00) + +/******************** Bit definition for CANFD_PSR register *******************/ +#define CANFD_PSR_TDCV ((uint32_t)0x00FF0000) + +/******************** Bit definition for CAN_DMA_T0 register *******************/ +#define CANFD_DMA_T0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T1 register *******************/ +#define CANFD_DMA_T1 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T2 register *******************/ +#define CANFD_DMA_T2 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R0 register *******************/ +#define CANFD_DMA_R0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R1 register *******************/ +#define CANFD_DMA_R1 ((uint32_t)0x00007FFF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMIOR_FDF ((uint32_t)0x00000001) +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH0R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_FDF ((uint32_t)0x00000001) +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH1R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) /* Filter Init Mode bit 13 */ +#define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) /* Filter Init Mode bit 14 */ +#define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) /* Filter Init Mode bit 15 */ +#define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) /* Filter Init Mode bit 16 */ +#define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) /* Filter Init Mode bit 17 */ +#define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) /* Filter Init Mode bit 18 */ +#define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) /* Filter Init Mode bit 19 */ +#define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) /* Filter Init Mode bit 20 */ +#define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) /* Filter Init Mode bit 21 */ +#define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) /* Filter Init Mode bit 22 */ +#define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) /* Filter Init Mode bit 23 */ +#define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) /* Filter Init Mode bit 24 */ +#define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) /* Filter Init Mode bit 25 */ +#define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) /* Filter Init Mode bit 26 */ +#define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) /* Filter Init Mode bit 27 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) /* Filter Scale Configuration bit 13 */ +#define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) /* Filter Scale Configuration bit 14 */ +#define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) /* Filter Scale Configuration bit 15 */ +#define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) /* Filter Scale Configuration bit 16 */ +#define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) /* Filter Scale Configuration bit 17 */ +#define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) /* Filter Scale Configuration bit 18 */ +#define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) /* Filter Scale Configuration bit 19 */ +#define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) /* Filter Scale Configuration bit 20 */ +#define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) /* Filter Scale Configuration bit 21 */ +#define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) /* Filter Scale Configuration bit 22 */ +#define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) /* Filter Scale Configuration bit 23 */ +#define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) /* Filter Scale Configuration bit 24 */ +#define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) /* Filter Scale Configuration bit 25 */ +#define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) /* Filter Scale Configuration bit 26 */ +#define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) /* Filter Scale Configuration bit 27 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) /* Filter FIFO Assignment for Filter 13 */ +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) /* Filter FIFO Assignment for Filter 14 */ +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) /* Filter FIFO Assignment for Filter 15 */ +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) /* Filter FIFO Assignment for Filter 16 */ +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) /* Filter FIFO Assignment for Filter 17 */ +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) /* Filter FIFO Assignment for Filter 18 */ +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) /* Filter FIFO Assignment for Filter 19 */ +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) /* Filter FIFO Assignment for Filter 20 */ +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) /* Filter FIFO Assignment for Filter 21 */ +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) /* Filter FIFO Assignment for Filter 22 */ +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) /* Filter FIFO Assignment for Filter 23 */ +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) /* Filter FIFO Assignment for Filter 24 */ +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) /* Filter FIFO Assignment for Filter 25 */ +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) /* Filter FIFO Assignment for Filter 26 */ +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) /* Filter FIFO Assignment for Filter 27 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint32_t)0x00002000) /* Filter 13 Active */ +#define CAN_FWR_FACT14 ((uint32_t)0x00004000) /* Filter 14 Active */ +#define CAN_FWR_FACT15 ((uint32_t)0x00008000) /* Filter 15 Active */ +#define CAN_FWR_FACT16 ((uint32_t)0x00010000) /* Filter 16 Active */ +#define CAN_FWR_FACT17 ((uint32_t)0x00020000) /* Filter 17 Active */ +#define CAN_FWR_FACT18 ((uint32_t)0x00040000) /* Filter 18 Active */ +#define CAN_FWR_FACT19 ((uint32_t)0x00080000) /* Filter 19 Active */ +#define CAN_FWR_FACT20 ((uint32_t)0x00100000) /* Filter 20 Active */ +#define CAN_FWR_FACT21 ((uint32_t)0x00200000) /* Filter 21 Active */ +#define CAN_FWR_FACT22 ((uint32_t)0x00400000) /* Filter 22 Active */ +#define CAN_FWR_FACT23 ((uint32_t)0x00800000) /* Filter 23 Active */ +#define CAN_FWR_FACT24 ((uint32_t)0x01000000) /* Filter 24 Active */ +#define CAN_FWR_FACT25 ((uint32_t)0x02000000) /* Filter 25 Active */ +#define CAN_FWR_FACT26 ((uint32_t)0x04000000) /* Filter 26 Active */ +#define CAN_FWR_FACT27 ((uint32_t)0x08000000) /* Filter 27 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint32_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint32_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint32_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint32_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) +#define FLASH_STATR_TURBO ((uint8_t)0x80) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG (0x0001) /* Programming */ +#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT (0x0040) /* Start */ +#define FLASH_CTLR_LOCK (0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_CFGCANM ((uint32_t)0x00000080) + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* DATA0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* DATA1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_OBR_MODEKEYR register ******************/ +#define FLASH_OBR_MODEKEYR ((uint32_t)0xFFFFFFFF) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_RM ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_RM ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_RM ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_RM ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_RM ((uint32_t)0x00000030) /* USART3_RM[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_RM_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_RM_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_RM ((uint32_t)0x000000C0) /* TIM1_RM[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_RM_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_RM_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_RM ((uint32_t)0x00000300) /* TIM2_RM[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_RM_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_RM_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_RM ((uint32_t)0x00000400) /* TIM3_RM bits (TIM3 remapping) */ + +#define AFIO_PCFR1_TIM4_RM ((uint32_t)0x00001000) /* TIM4_RM bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_RM ((uint32_t)0x00006000) /* CAN_RM[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_RM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_RM_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_PD0PD1_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_PD01_RM AFIO_PCFR1_PD0PD1_RM + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/***************** Bit definition for AFIO_CR register *****************/ +#define AFIO_CR_USBPD_IN_HVT ((uint32_t)0x00000200) +#define AFIO_CR_UPD_BC_VSRC ((uint32_t)0x00010000) +#define AFIO_CR_UDM_BC_VSRC ((uint32_t)0x00020000) +#define AFIO_CR_UPD_BC_CMPE ((uint32_t)0x00040000) +#define AFIO_CR_UDM_BC_CMPE ((uint32_t)0x00080000) +#define AFIO_CR_UPD_BC_CMPO ((uint32_t)0x00100000) +#define AFIO_CR_UDM_BC_CMPO ((uint32_t)0x00200000) + +/***************** Bit definition for AFIO_PCFR2 register *****************/ +#define AFIO_PCFR2_USART4_RM ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART2_RM_H ((uint32_t)0x00040000) + +#define AFIO_PCFR2_USART1_RM_H ((uint32_t)0x00180000) +#define AFIO_PCFR2_USART1_RM_H_0 ((uint32_t)0x00080000) +#define AFIO_PCFR2_USART1_RM_H_1 ((uint32_t)0x00100000) + +#define AFIO_PCFR2_TIM2_RM_H ((uint32_t)0x00200000) +#define AFIO_PCFR2_TIM1_RM_H ((uint32_t)0x00400000) +#define AFIO_PCFR2_I2C_RM_H ((uint32_t)0x00800000) +#define AFIO_PCFR2_SPI1_RM_H ((uint32_t)0x01000000) +#define AFIO_PCFR2_LPTIM_RM ((uint32_t)0x02000000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) /* PVD level 4 */ +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) /* PVD level 5 */ +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) /* PVD level 6 */ +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) /* PVD level 7 */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) + +#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP [1:0]*/ +#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0800) + +#define PWR_CTLR_AUTO_LDO_EC ((uint16_t)0x1000) +#define PWR_CTLR_LDO_EC ((uint16_t)0x2000) +#define PWR_CTLR_R2KSTY ((uint32_t)0x00010000) +#define PWR_CTLR_R18KSTY ((uint32_t)0x00020000) +#define PWR_CTLR_R2KVBAT ((uint32_t)0x00040000) +#define PWR_CTLR_R18KVBAT ((uint32_t)0x00080000) +#define PWR_RAMLV ((uint32_t)0x00100000) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSILP ((uint32_t)0x00000004) +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_HSELP ((uint32_t)0x00100000) +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + +#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ +#define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_ADC_DUTY_CHG ((uint32_t)0x70000000) /* DUTY_CHG[2:0] bits */ +#define RCC_ADC_DUTY_CHG_0 ((uint32_t)0x10000000) +#define RCC_ADC_DUTY_CHG_1 ((uint32_t)0x20000000) +#define RCC_ADC_DUTY_CHG_2 ((uint32_t)0x40000000) + +#define RCC_ADC_PRE_ADJ ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_CFGR2 register *******************/ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 2 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 1 reset */ +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ +#define RCC_LPTIMRST ((uint32_t)0x80000000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint32_t)0x1000) +#define RCC_USBFS ((uint32_t)0x1000) +#define RCC_USBPD ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) /* I2C 2 clock enable */ +#define RCC_CANEN ((uint32_t)0x02000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ +#define RCC_LPTIMEN ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/****************** Bit definition for RCC_AHBRSTR register *****************/ + + + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSRXEN ((uint16_t)0x0001) + + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_BKSEL ((uint16_t)0x1000) +#define TIM_TMR_CAP_OV_EN ((uint16_t)0x4000) +#define TIM_TMR_CAP_LVL_EN ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +#define TIM4_CNT ((uint32_t)0xFFFFFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 (only on parts with RGMII) */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000700) /* ULLDO_TRIM[2:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ +#define EXTEN_ULLDO_TRIM2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00003000) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00001000) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00002000) /* Bit 1 */ + +/******************************************************************************/ +/* DEBUG SUPPORT */ +/******************************************************************************/ +/******************* Bit definition for DBGMCU_DR register *******************/ +#define DBG_DEBUGMCU_SLEEP ((uint32_t)0x00000001) +#define DBG_DEBUGMCU_STOP ((uint32_t)0x00000002) +#define DBG_DEBUGMCU_STBY ((uint32_t)0x00000004) +#define DBG_DEBUGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_DEBUGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_DEBUGMCU_I2C1SMBUS_TOUT ((uint32_t)0x00000400) +#define DBG_DEBUGMCU_I2C2SMBUS_TOUT ((uint32_t)0x00000800) +#define DBG_DEBUGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBG_DEBUGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBG_DEBUGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBG_DEBUGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBG_DEBUGMCU_CAN_STOP ((uint32_t)0x00010000) + +/******************************************************************************/ +/* OPTICAL PARAMETER */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CFGR1 register *******************/ +#define OPA_CFGR1_POLLEN ((uint32_t)0x00000001) +#define OPA_CFGR1_BKINEN ((uint32_t)0x00000004) +#define OPA_CFGR1_RSTEN ((uint32_t)0x00000010) +#define OPA_CFGR1_OPCMLOCK ((uint32_t)0x00000080) +#define OPA_CFGR1_IEOUT ((uint32_t)0x00000100) +#define OPA_CFGR1_IECNT ((uint32_t)0x00000400) +#define OPA_CFGR1_NMIEN ((uint32_t)0x00000800) +#define OPA_CFGR1_IFOUT ((uint32_t)0x00001000) +#define OPA_CFGR1_IFCNT ((uint32_t)0x00004000) + +/******************* Bit definition for OPA_CFGR2 register *******************/ +#define OPA_CFGR2_POLL_VLU ((uint32_t)0x000001FF) +#define OPA_CFGR2_POLL_NUM ((uint32_t)0x00000E00) +#define OPA_CFGR2_POLL_CNT ((uint32_t)0x00007000) + +/******************* Bit definition for OPA_CTLR1 register *******************/ +#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR1_MODE1 ((uint32_t)0x0000000E) +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000070) +#define OPA_CTLR1_FBEN1 ((uint32_t)0x00000080) +#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000F00) +#define OPA_CTLR1_LP1 ((uint32_t)0x00001000) +#define OPA_CTLR1_INTRIMP ((uint32_t)0x00010000) +#define OPA_CTLR1_ITRIMP ((uint32_t)0x003E0000) +#define OPA_CTLR1_INTRIMN ((uint32_t)0x01000000) +#define OPA_CTLR1_ITRIMN ((uint32_t)0x3E000000) + +/******************* Bit definition for OPA_CTLR2 register *******************/ +#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000008) +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000010) +#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000020) +#define OPA_CTLR2_LP1 ((uint32_t)0x00000040) +#define OPA_CTLR2_EN2 ((uint32_t)0x00000100) +#define OPA_CTLR2_MODE2 ((uint32_t)0x00000600) +#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000800) +#define OPA_CTLR2_PSEL2 ((uint32_t)0x00001000) +#define OPA_CTLR2_HYEN2 ((uint32_t)0x00002000) +#define OPA_CTLR2_LP2 ((uint32_t)0x00004000) +#define OPA_CTLR2_EN3 ((uint32_t)0x00010000) +#define OPA_CTLR2_MODE3 ((uint32_t)0x00060000) +#define OPA_CTLR2_NSEL3 ((uint32_t)0x00080000) +#define OPA_CTLR2_PSEL3 ((uint32_t)0x00100000) +#define OPA_CTLR2_HYEN3 ((uint32_t)0x00200000) +#define OPA_CTLR2_LP3 ((uint32_t)0x00400000) + +#define OPA_CTLR2_WKUP_MD ((uint32_t)0x03000000) +#define OPA_CTLR2_WKUP_MD_0 ((uint32_t)0x01000000) +#define OPA_CTLR2_WKUP_MD_1 ((uint32_t)0x02000000) + +/******************* Bit definition for OPCMKEY register *******************/ +#define OPCM_KEY ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* LOW POWER TIM */ +/******************************************************************************/ +/******************* Bit definition for LPTIM_ISR register *******************/ +#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) +#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) +#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) +#define LPTIM_ISR_ARROK ((uint32_t)0000000010) +#define LPTIM_ISR_UP ((uint32_t)0x00000020) +#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) +#define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) + +/******************* Bit definition for LPTIM_ICR register *******************/ +#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) +#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) +#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) +#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) +#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) +#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) +#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_IER register *******************/ +#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) +#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) +#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) +#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) +#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) +#define LPTIM_IER_UPIE ((uint32_t)0x00000020) +#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_CFGR register *******************/ +#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) +#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) +#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) +#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) +#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) +#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) +#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) +#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) +#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) +#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) +#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) +#define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) +#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) +#define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) +#define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) + +/******************* Bit definition for LPTIM_CR register *******************/ +#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) +#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) +#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) +#define LPTIM_CR_OUTEN ((uint32_t)0x00000008) +#define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) + +/******************* Bit definition for LPTIM_CMP register *******************/ +#define LPTIM_CMP ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_ARR register *******************/ +#define LPTIM_ARR ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_COUNT ((uint32_t)0x0000FFFF) + +/******************************************************************************/ +/* TOUCH KEY */ +/******************************************************************************/ +/******************* Bit definition for TKEY_CHARGE register *******************/ +#define TKEY_CHGOFFSET ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_ACT_DCG register *******************/ +#define TKEY_TKACTDCG ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_DR register *******************/ +#define TKEY_DR ((uint32_t)0x0000FFFF) + + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* ch32v00x_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32v00x_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +///* CTLR1 register Mask */ +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/* ch32v20x_bkp.c ------------------------------------------------------------*/ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + + +/* ch32v20x_can.c ------------------------------------------------------------*/ +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + + + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32v00x_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + + +/* DMA2 FLAG mask */ +// Editor's note: Overloaded Definition. +#define DMA2_FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32v00x_flash.c ----------------------------------------------------------*/ + + + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_BER64 ((uint32_t)0x00080000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* EEPROM address */ +#define EEPROM_ADDRESS ((uint32_t)0x8070000) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + + +/* ch32v00x_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +////* I2C registers Masks */ +// Editor's note: Overloaded Definition. +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +//Editor's Note: Overloaded Definition +#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + + +/* ch32v20x_opa.c ------------------------------------------------------------*/ +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + + +/* ch32v00x_pwr.c ------------------------------------------------------------*/ + + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* ch32v00x_rcc.c ------------------------------------------------------------*/ + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + + +/* RCC Flag Mask */ +//Editor's Note: Overloaded Definition +#define RCC_FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +#ifndef __ASSEMBLER__ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; +#endif + + +/* ch32v20x_rtc.c ------------------------------------------------------------*/ + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32v00x_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + + +/* ch32v00x_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_CalInternal ((uint8_t)ADC_Channel_18) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_Sample_mode_definition */ +#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000000) +#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000020) + +/* ch32v20x_bkp.h ------------------------------------------------------------*/ + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + + +/* ch32v20x_can.h ------------------------------------------------------------*/ + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + +/* CAN_flags */ +/* Transmit Flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/* CAN_BS1_Mode */ +#define CAN_BS1_4bit ((uint32_t)0x00000000) +#define CAN_BS1_6bit ((uint32_t)0x00000100) + +/* CANFD_data_length_code */ +#define CANFD_DLC_BYTES_0 ((uint32_t)0x0000) /* 0 bytes data field */ +#define CANFD_DLC_BYTES_1 ((uint32_t)0x0001) /* 1 bytes data field */ +#define CANFD_DLC_BYTES_2 ((uint32_t)0x0002) /* 2 bytes data field */ +#define CANFD_DLC_BYTES_3 ((uint32_t)0x0003) /* 3 bytes data field */ +#define CANFD_DLC_BYTES_4 ((uint32_t)0x0004) /* 4 bytes data field */ +#define CANFD_DLC_BYTES_5 ((uint32_t)0x0005) /* 5 bytes data field */ +#define CANFD_DLC_BYTES_6 ((uint32_t)0x0006) /* 6 bytes data field */ +#define CANFD_DLC_BYTES_7 ((uint32_t)0x0007) /* 7 bytes data field */ +#define CANFD_DLC_BYTES_8 ((uint32_t)0x0008) /* 8 bytes data field */ +#define CANFD_DLC_BYTES_12 ((uint32_t)0x0009) /* 12 bytes data field */ +#define CANFD_DLC_BYTES_16 ((uint32_t)0x000A) /* 16 bytes data field */ +#define CANFD_DLC_BYTES_20 ((uint32_t)0x000B) /* 20 bytes data field */ +#define CANFD_DLC_BYTES_24 ((uint32_t)0x000C) /* 24 bytes data field */ +#define CANFD_DLC_BYTES_32 ((uint32_t)0x000D) /* 32 bytes data field */ +#define CANFD_DLC_BYTES_48 ((uint32_t)0x000E) /* 48 bytes data field */ +#define CANFD_DLC_BYTES_64 ((uint32_t)0x000F) /* 64 bytes data field */ + +/* CANFD_synchronisation_jump_width */ +#define CANFD_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_SJW_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_SJW_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_SJW_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_SJW_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_SJW_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_SJW_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_SJW_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_SJW_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_SJW_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_SJW_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_SJW_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_SJW_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_1 */ +#define CANFD_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ +#define CANFD_BS1_17tq ((uint8_t)0x10) /* 17 time quantum */ +#define CANFD_BS1_18tq ((uint8_t)0x11) /* 18 time quantum */ +#define CANFD_BS1_19tq ((uint8_t)0x12) /* 19 time quantum */ +#define CANFD_BS1_20tq ((uint8_t)0x13) /* 20 time quantum */ +#define CANFD_BS1_21tq ((uint8_t)0x14) /* 21 time quantum */ +#define CANFD_BS1_22tq ((uint8_t)0x15) /* 22 time quantum */ +#define CANFD_BS1_23tq ((uint8_t)0x16) /* 23 time quantum */ +#define CANFD_BS1_24tq ((uint8_t)0x17) /* 24 time quantum */ +#define CANFD_BS1_25tq ((uint8_t)0x18) /* 25 time quantum */ +#define CANFD_BS1_26tq ((uint8_t)0x19) /* 26 time quantum */ +#define CANFD_BS1_27tq ((uint8_t)0x1A) /* 27 time quantum */ +#define CANFD_BS1_28tq ((uint8_t)0x1B) /* 28 time quantum */ +#define CANFD_BS1_29tq ((uint8_t)0x1C) /* 29 time quantum */ +#define CANFD_BS1_30tq ((uint8_t)0x1D) /* 30 time quantum */ +#define CANFD_BS1_31tq ((uint8_t)0x1E) /* 31 time quantum */ +#define CANFD_BS1_32tq ((uint8_t)0x1F) /* 32 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_2 */ +#define CANFD_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS2_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS2_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS2_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS2_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS2_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS2_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS2_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS2_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_Transmit_Mailbox_number_constants */ +#define CAN_Transmit_Mailbox0 ((uint8_t)0x00) +#define CAN_Transmit_Mailbox1 ((uint8_t)0x01) +#define CAN_Transmit_Mailbox2 ((uint8_t)0x02) + + +/* ch32v00x_dac.h ------------------------------------------------------------*/ + +/* DAC_trigger_selection */ +#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ + +/* DAC_wave_generation */ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) + + +/* DAC_lfsrunmask_triangleamplitude */ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ + +/* DAC_output_buffer */ +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) + +/* DAC_Channel_selection */ +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) + +/* DAC_data_alignment */ +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) + +/* DAC_wave_generation */ +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) + +/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ + +/* CFGR0 Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) + +/* ch32v00x_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBPD Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the LPTIM Wakeup event */ +#define EXTI_Line22 ((uint32_t)0x400000) /* External interrupt line 22 Connected to the COMP Wakeup event */ + +/* ch32v00x_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; +#endif + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycle */ + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of sector 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of sector 1 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of sector 2 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of sector 3 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of sector 4 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of sector 5 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of sector 6 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of sector 7 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of sector 8 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of sector 9 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of sector 10 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of sector 11 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of sector 12 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of sector 13 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of sector 14 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of sector 15 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of sector 16 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of sector 17 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of sector 18 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of sector 19 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of sector 20 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of sector 21 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of sector 22 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of sector 23 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of sector 24 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of sector 25 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of sector 26 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of sector 27 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of sector 28 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of sector 29 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of sector 30 */ +#define FLASH_WRProt_Sectors31 ((uint32_t)0x80000000) /* Write protection of sector 31 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_OB_CAN_BusOff_MODE */ +#define OB_CAN_BusOff_MODE1 ((uint16_t)0x0020) /* Bus off recovery mode1 */ +#define OB_CAN_BusOff_MODE2 ((uint16_t)0x0000) /* Bus off recovery mode2 */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WAKE_UP ((uint32_t)0x00000040) /* FLASH Wake up of Operation flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */ + + + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +//bit[31:30] = 11b - PCFR1-bit[15-0] and PCFR2-bit[26:16] +/* bit[29:27] = 000b */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0xC0000001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0xC1000000) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0xC1000001) /* SPI1 Full Alternate Function mapping */ +/* bit[29:27] = 001b */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0xC8800000) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0xC8800002) /* I2C1 Full Alternate Function mapping */ +/* bit[29:27] = 010b */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0xD0000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0xD0080000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART1 ((uint32_t)0xD0080004) /* USART1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART1 ((uint32_t)0xD0100000) /* USART1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0xD0100004) /* USART1 Full Alternate Function mapping */ +/* bit[29:27] = 011b */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0xD8000008) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0xD8040000) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0xD8040008) /* USART2 Full Alternate Function mapping */ +/* bit[29:27] = 100b */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0xE0000040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0xE0000080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0xE00000C0) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM1 ((uint32_t)0xE0400000) /* TIM1 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM1 ((uint32_t)0xE0400040) /* TIM1 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0xE04000C0) /* TIM1 Full Alternate Function mapping */ +/* bit[29:27] = 101b */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0xE8000100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0xE8000200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0xE8000300) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0xE8200000) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0xE8200100) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0xE8200300) /* TIM2 Full Alternate Function mapping */ + +//bit[31:30] = 00b - PCFR1 +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140020) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM3 ((uint32_t)0x00000400) /* TIM3 Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) */ + +//bit[31:30] = 01b - PCFR2 +#define GPIO_Remap_USART4 ((uint32_t)0x40000001) /* USART4 Alternate Function mapping */ +#define GPIO_Remap_LPTIM ((uint32_t)0x40000200) /* LPTIM Alternate Function mapping */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + + +/* ch32v00x_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +/* ch32l103_lptim.h -----------------------------------------------------------*/ + +/* LPTIM_Clock_Source */ +#define LPTIM_ClockSource_In ((uint32_t)0x00000000) +#define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) + +/* LPTIM_ClockPolarity */ +#define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) +#define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) +#define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) + +/* LPTIM_ClockPrescalerTime */ +#define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) +#define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) +#define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) + +/* LPTIM_TriggerSampleTime */ +#define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) +#define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) +#define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) + +/* LPTIM_ClockPrescaler */ +#define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) +#define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) +#define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) +#define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) +#define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) +#define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) +#define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) +#define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) + +/* LPTIM_TriggerSource */ +#define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) +#define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) +#define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) + +/* LPTIM_ExTriggerPolarity */ +#define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) +#define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) +#define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) +#define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) + +/* LPTIM_OutputPolarity */ +#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) +#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) + +/* LPTIM_UpdateMode */ +#define LPTIM_UpdateMode0 ((uint32_t)0x00000000) +#define LPTIM_UpdateMode1 ((uint32_t)0x00400000) + +/* LPTIM_CountSource */ +#define LPTIM_CountSource_Internal ((uint32_t)0x00000000) +#define LPTIM_CountSource_External ((uint32_t)0x00800000) + +/* LPTIM_InClockSource */ +#define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) +#define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) +#define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) +#define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) + +/* LPTIM_Flag_Definition */ +#define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) +#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) +#define LPTIM_FLAG_UP ((uint32_t)0x00000020) +#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) +#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) +#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) +#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) + +/* LPTIM_Interrupts_Definition */ +#define LPTIM_IT_DOWN ((uint32_t)0x00000040) +#define LPTIM_IT_UP ((uint32_t)0x00000020) +#define LPTIM_IT_ARROK ((uint32_t)0x00000010) +#define LPTIM_IT_CMPOK ((uint32_t)0x00000008) +#define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_IT_ARRM ((uint32_t)0x00000002) +#define LPTIM_IT_CMPM ((uint32_t)0x00000001) + + +#define LPYIM_OutputPolarity_High LPTIM_OutputPolarity_High +#define LPYIM_OutputPolarity_Low LPTIM_OutputPolarity_Low +#define LPYIM_UpdateMode0 LPTIM_UpdateMode0 +#define LPYIM_UpdateMode1 LPTIM_UpdateMode1 + +/* ch32v00x_misc.h -----------------------------------------------------------*/ + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + +/* ch32v00x_opa.h ------------------------------------------------------------*/ + +/* Editor's note: I don't know if this is actually useful */ +#ifndef __ASSEMBLER__ + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, /* PA3 */ + OUT_IO_OUT1, /* PB1 */ + OUT_IO_OUT2, /* PA2 */ + OUT_IO_OUT3, /* PA4 */ + OUT_IO_OUT4, /* PB0 */ + OUT_IO_OFF +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, /* PB15 */ + CHP1, /* PB0 */ + CHP2, /* PB14 */ + CHP3, /* PA7 */ + CHP4, /* PA0 */ + CHP5, /* PA6 */ + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, /* PB11 */ + CHN1, /* PA6 */ + CHN2, /* PB10 */ + CHN3, /* PA5 */ + CHN4, /* PA1 */ + CHN5, /* PA7 */ + CHN2_PGA_32xIN, /* PB10 */ + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_PGA_64xIN, + CHN_OFF = 0xF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF = 0, + CHP_OPA1_ON, +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF = 0, /* TIM1 braking signal source form IO input */ + BKIN_OPA1_ON, /* TIM1 braking signal source form OPA output */ +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF = 0, + RST_OPA1_ON, +} OPA_RST_EN_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF = 0, + OUT_IE_OPA1_ON, +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3, + CHP_POLL_NUM_4, + CHP_POLL_NUM_5, + CHP_POLL_NUM_6 +} OPA_PSEL_POLL_NUM_TypeDef; + +/* Offset_voltage_adjustment_value_polarity */ +typedef enum +{ + OPA_Vos_Ads_N = 0, + OPA_Vos_Ads_P +} OPA_Vos_ADS_POLARITY_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO0 = 0, + OUT_IO1, + OUT_IO_TIM2 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP_0 = 0, + CMP_CHP_1, +} CMP_PSEL_TypeDef; + +#define CMP_CHP1 CMP_CHP_0 +#define CMP_CHP2 CMP_CHP_1 + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN0 = 0, + CMP_HYEN1, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* Current channel for OPA polling enumeration */ +typedef enum +{ + O1P0 = 0, + O1P1, + O1P2, + O1P3, + O1P4, + O1P5, +} OPA_POLL_NUM_TypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +/* CMP_WakeUp_IO_mode_definition */ +#define CMP_WakeUp_Rising_Falling ((uint32_t)0x01000000) +#define CMP_WakeUp_Rising ((uint32_t)0x02000000) +#define CMP_WakeUp_Falling ((uint32_t)0x03000000) + +#endif + +/* ch32v00x_pwr.h ------------------------------------------------------------*/ + + + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_7 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + + +/* ch32v00x_rcc.h ------------------------------------------------------------*/ + + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor for other CH32L103 */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) + +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00000000) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00400000) +#define RCC_USBCLKSource_PLLCLK_Div1_5 ((uint32_t)0x00800000) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_HCLK_ADC ((uint32_t)0x80000000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + + + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) + + +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000) + + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_LPTIM ((uint32_t)0x80000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* ADC_clock_H_Level_Duty_Cycle */ +#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) +#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) +#define RCC_ADC_H_Level_Mode2 ((uint32_t)0x20000000) +#define RCC_ADC_H_Level_Mode3 ((uint32_t)0x30000000) +#define RCC_ADC_H_Level_Mode4 ((uint32_t)0x40000000) +#define RCC_ADC_H_Level_Mode5 ((uint32_t)0x50000000) +#define RCC_ADC_H_Level_Mode6 ((uint32_t)0x60000000) +#define RCC_ADC_H_Level_Mode7 ((uint32_t)0x70000000) + +/* ch32v00x_rtc.h ------------------------------------------------------------*/ +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Capture_Mode */ +#define TIM_Capture_Mode0 ((uint16_t)0x0000) +#define TIM_Capture_Mode1 ((uint16_t)0x4000) + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_RX_BUSY ((uint16_t)0x0400) +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + + +/* ch32l103_usb.h ------------------------------------------------------------*/ +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 +#endif + +/* USB Buffer Size */ +#ifndef USBFS_MAX_PACKET_SIZE +#define USBFS_MAX_PACKET_SIZE 64 +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UID_1_WIRE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current SETUP transaction completed +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + +/* ch32l103_usbpd.h -----------------------------------------------------------*/ + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX (3<<0) /* BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CE (7<<5) /* Enable the voltage comparator on port CC */ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ + +#define USBPD_IN_HVT (1<<9) +/********************************************************* +* PD pin PB6/PB7 high threshold input mode: +* 1: High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication +* 0: Normal GPIO threshold input +* *******************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_6 +#define PIN_CC2 GPIO_Pin_7 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ +#define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ +#define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. + #define DMDATA0 ((volatile uint32_t*)0xe0000380) + #define DMDATA1 ((volatile uint32_t*)0xe0000384) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000388)// Reads as 0x00000000 if debugger is attached. + +// Determination of PLL multiplication factor for non-V003 chips + #if !defined(FUNCONF_SYSTEM_CORE_CLOCK) + #define PLL_MULTIPLICATION ((uint32_t)0) + #else + #if defined(CH32V10x) || defined(CH32V20x) || defined(CH32L103) || defined(CH32V30x_D8) + #if FUNCONF_PLL_MULTIPLIER == 2 + #define PLL_MULTIPLICATION RCC_PLLMULL2 + #elif FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3 + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4 + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5 + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6 + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7 + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8 + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9 + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10 + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11 + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12 + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13 + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14 + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15 + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16 + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18 + #else + #error "Invalid PLL multiplier" + #endif + #else + #if FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18_EXTEN + #else + #error "Invalid PLL multiplier" + #endif + #endif + #endif + + + + +// Applies to all processors + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA1 1 +#define PA2 2 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +#define PA0 0 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 + +#define LL_TX_POWER_MINUS_18_DBM 0x01 +#define LL_TX_POWER_MINUS_10_DBM 0x03 +#define LL_TX_POWER_MINUS_5_DBM 0x05 +#define LL_TX_POWER_MINUS_3_DBM 0x07 +#define LL_TX_POWER_0_DBM 0x09 +#define LL_TX_POWER_1_DBM 0x0B +#define LL_TX_POWER_2_DBM 0x0D +#define LL_TX_POWER_3_DBM 0x11 +#define LL_TX_POWER_4_DBM 0x15 +#define LL_TX_POWER_5_DBM 0x1B +#define LL_TX_POWER_6_DBM 0x25 +#define LL_TX_POWER_7_DBM 0x3F + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/ch32v003hw.h b/inc/ch32v003hw.h index deff723..f5dd26e 100644 --- a/inc/ch32v003hw.h +++ b/inc/ch32v003hw.h @@ -3,47 +3,46 @@ #include "ch32fun.h" -#ifndef __ASSEMBLER__ // Things before this can be used in assembly. +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - /* Interrupt Number Definition, according to the selected device */ - typedef enum IRQn - { - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 3 Exception Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - FLASH_IRQn = 18, /* FLASH global Interrupt */ - RCC_IRQn = 19, /* RCC global Interrupt */ - EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ - AWU_IRQn = 21, /* AWU global Interrupt */ - DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 29, /* ADC global Interrupt */ - I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ - USART1_IRQn = 32, /* USART1 global Interrupt */ - SPI1_IRQn = 33, /* SPI1 global Interrupt */ - TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 38, /* TIM2 global Interrupt */ - } IRQn_Type; + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ +} IRQn_Type; #define DEFAULT_INTERRUPT_VECTOR_CONTENTS "\n\ .align 2\n\ @@ -90,663 +89,528 @@ extern "C" .word TIM2_IRQHandler /* TIM2 */ \n\ .option pop;\n" - /* memory mapped structure for SysTick */ - typedef struct - { - __IO uint32_t CTLR; - __IO uint32_t SR; - __IO uint32_t CNT; - uint32_t RESERVED0; - __IO uint32_t CMP; - uint32_t RESERVED1; - } SysTick_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; /* System Count Control Register */ + __IO uint32_t SR; /* System Count Status Register */ + __IO uint32_t CNT; /* System Counter Register */ + uint32_t RESERVED0; + __IO uint32_t CMP; /* System Count Comparison Value Register */ + uint32_t RESERVED1; +} SysTick_Type; + #endif /* __ASSEMBLER__*/ -#define HardFault_IRQn EXC_IRQn +#define HardFault_IRQn EXC_IRQn + /* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT #ifndef __ASSEMBLER__ - /* Analog to Digital Converter */ - typedef struct - { - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; - __IO uint32_t DLYR; - } ADC_TypeDef; +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; /* ADC Status Register */ + __IO uint32_t CTLR1; /* ADC Control Register 1 */ + __IO uint32_t CTLR2; /* ADC Control Register 2 */ + __IO uint32_t SAMPTR1; /* ADC Sample Time Register 1 */ + __IO uint32_t SAMPTR2; /* ADC Sample Time Register 2 */ + __IO uint32_t IOFR1; /* ADC Injected Channel Data Offset Register 1 */ + __IO uint32_t IOFR2; /* ADC Injected Channel Data Offset Register 2 */ + __IO uint32_t IOFR3; /* ADC Injected Channel Data Offset Register 3 */ + __IO uint32_t IOFR4; /* ADC Injected Channel Data Offset Register 4 */ + __IO uint32_t WDHTR; /* ADC Watchdog High Threshold Register */ + __IO uint32_t WDLTR; /* ADC Watchdog Low Threshold Register */ + __IO uint32_t RSQR1; /* ADC Regular Sequence Register 1 */ + __IO uint32_t RSQR2; /* ADC Regular Sequence Register 2 */ + __IO uint32_t RSQR3; /* ADC Regular Sequence Register 3 */ + __IO uint32_t ISQR; /* ADC Injected Sequence Register */ + __IO uint32_t IDATAR1; /* ADC Injected Data Register 1 */ + __IO uint32_t IDATAR2; /* ADC Injected Data Register 2 */ + __IO uint32_t IDATAR3; /* ADC Injected Data Register 3 */ + __IO uint32_t IDATAR4; /* ADC Injected Data Register 4 */ + __IO uint32_t RDATAR; /* ADC Regular Data Register */ + __IO uint32_t DLYR; /* ADC Delayed Data Register */ +} ADC_TypeDef; - /* CRC Calculation Unit */ - typedef struct - { - __IO uint32_t DATAR; - __IO uint8_t IDATAR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CTLR; - } CRC_TypeDef; +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; - /* Debug MCU */ - typedef struct - { - __IO uint32_t CFGR0; - __IO uint32_t CFGR1; - } DBGMCU_TypeDef; +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; /* DMA Configuration Register */ + __IO uint32_t CNTR; /* DMA Number of Data Register */ + __IO uint32_t PADDR; /* DMA Peripheral Address Register */ + __IO uint32_t MADDR; /* DMA Memory Address Register */ +} DMA_Channel_TypeDef; - /* DMA Controller */ - typedef struct - { - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; - } DMA_Channel_TypeDef; +typedef struct +{ + __IO uint32_t INTFR; /* DMA Interrupt Status Register */ + __IO uint32_t INTFCR; /* DMA Interrupt Flag Clear Register */ +} DMA_TypeDef; - typedef struct - { - __IO uint32_t INTFR; - __IO uint32_t INTFCR; - } DMA_TypeDef; +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; /* Interrupt Enable Register */ + __IO uint32_t EVENR; /* Event Capture Register */ + __IO uint32_t RTENR; /* Rising Edge Trigger Enable Register */ + __IO uint32_t FTENR; /* Falling Edge Trigger Enable Register */ + __IO uint32_t SWIEVR; /* Soft Interrupt Event Register */ + __IO uint32_t INTFR; /* Interrupt Flag Register */ +} EXTI_TypeDef; - /* External Interrupt/Event Controller */ - typedef struct - { - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; - } EXTI_TypeDef; +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; /* Control Register */ + __IO uint32_t KEYR; /* FPEC Key Register */ + __IO uint32_t OBKEYR; /* OBKEY Register */ + __IO uint32_t STATR; /* Status Register */ + __IO uint32_t CTLR; /* Configuration Register */ + __IO uint32_t ADDR; /* Address Register */ + __IO uint32_t RESERVED; + __IO uint32_t OBR; /* Select Word Register */ + __IO uint32_t WPR; /* Write Protection Register */ + __IO uint32_t MODEKEYR; /* Extended Key Register */ + __IO uint32_t BOOT_MODEKEYR; /* Unlock BOOT Key Register */ +} FLASH_TypeDef; - /* FLASH Registers */ - typedef struct - { - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; - __IO uint32_t BOOT_MODEKEYR; - } FLASH_TypeDef; +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; +} OB_TypeDef; - /* Option Bytes Registers */ - typedef struct - { - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - } OB_TypeDef; +typedef struct +{ + __IO uint16_t FLACAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UNIID1; + __IO uint32_t UNIID2; + __IO uint32_t UNIID3; +} ESIG_TypeDef; - typedef struct - { - __IO uint16_t CAP; - __IO uint16_t RES1; - __IO uint32_t RES2; - __IO uint32_t UID0; - __IO uint32_t UID1; - __IO uint32_t UID2; - __IO uint32_t RES3; - } ESG_TypeDef; - - typedef struct - { - union +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct { - __I uint32_t CHIPID; - struct - { - __I uint16_t REVID; - __I uint16_t DEVID; - }s; - }u; - } INFO_TypeDef; + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; - /* General Purpose I/O */ - typedef enum - { - GPIO_CFGLR_IN_ANALOG = 0, - GPIO_CFGLR_IN_FLOAT = 4, - GPIO_CFGLR_IN_PUPD = 8, - GPIO_CFGLR_OUT_10Mhz_PP = 1, - GPIO_CFGLR_OUT_2Mhz_PP = 2, - GPIO_CFGLR_OUT_50Mhz_PP = 3, - GPIO_CFGLR_OUT_10Mhz_OD = 5, - GPIO_CFGLR_OUT_2Mhz_OD = 6, - GPIO_CFGLR_OUT_50Mhz_OD = 7, - GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, - GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, - GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, - GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, - GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, - GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, - } GPIO_CFGLR_PIN_MODE_Typedef; +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_30Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_30Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_30Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, + GPIO_CFGLR_OUT_30Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; - typedef union - { - uint32_t __FULL; - struct - { - GPIO_CFGLR_PIN_MODE_Typedef PIN0 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN1 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN2 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN3 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN4 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN5 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN6 : 4; - GPIO_CFGLR_PIN_MODE_Typedef PIN7 : 4; - }s; - } GPIO_CFGLR_t; - typedef union - { - uint32_t __FULL; - const struct - { - uint32_t IDR0 : 1; - uint32_t IDR1 : 1; - uint32_t IDR2 : 1; - uint32_t IDR3 : 1; - uint32_t IDR4 : 1; - uint32_t IDR5 : 1; - uint32_t IDR6 : 1; - uint32_t IDR7 : 1; - uint32_t : 24; - }s; - } GPIO_INDR_t; - typedef union - { - uint32_t __FULL; - struct - { - uint32_t ODR0 : 1; - uint32_t ODR1 : 1; - uint32_t ODR2 : 1; - uint32_t ODR3 : 1; - uint32_t ODR4 : 1; - uint32_t ODR5 : 1; - uint32_t ODR6 : 1; - uint32_t ODR7 : 1; - uint32_t : 24; - }s; - } GPIO_OUTDR_t; - typedef union - { - uint32_t __FULL; - struct - { - uint32_t BS0 : 1; - uint32_t BS1 : 1; - uint32_t BS2 : 1; - uint32_t BS3 : 1; - uint32_t BS4 : 1; - uint32_t BS5 : 1; - uint32_t BS6 : 1; - uint32_t BS7 : 1; - uint32_t : 8; - uint32_t BR0 : 1; - uint32_t BR1 : 1; - uint32_t BR2 : 1; - uint32_t BR3 : 1; - uint32_t BR4 : 1; - uint32_t BR5 : 1; - uint32_t BR6 : 1; - uint32_t BR7 : 1; - uint32_t : 8; - }s; - } GPIO_BSHR_t; - typedef union - { - uint32_t __FULL; - struct - { - uint32_t BR0 : 1; - uint32_t BR1 : 1; - uint32_t BR2 : 1; - uint32_t BR3 : 1; - uint32_t BR4 : 1; - uint32_t BR5 : 1; - uint32_t BR6 : 1; - uint32_t BR7 : 1; - uint32_t : 24; - }s; - } GPIO_BCR_t; - typedef union - { - uint32_t __FULL; - struct - { - uint32_t LCK0 : 1; - uint32_t LCK1 : 1; - uint32_t LCK2 : 1; - uint32_t LCK3 : 1; - uint32_t LCK4 : 1; - uint32_t LCK5 : 1; - uint32_t LCK6 : 1; - uint32_t LCK7 : 1; - uint32_t LCKK : 1; - uint32_t : 23; - }s; - } GPIO_LCKR_t; - typedef struct - { - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __I uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; - } GPIO_TypeDef; +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; /* Port Configuration Register Low */ + __IO uint32_t CFGHR; /* Port Configuration Register High */ + __I uint32_t INDR; /* Port Input Data Register */ + __IO uint32_t OUTDR; /* Port Output Data Register */ + __IO uint32_t BSHR; /* Port Set/Reset Register */ + __IO uint32_t BCR; /* Port Reset Register */ + __IO uint32_t LCKR; /* Port Configuration Lock Register */ +} GPIO_TypeDef; -#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t){.__FULL = gpio->field}) -#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t)__VA_ARGS__).__FULL -#define DYN_GPIO_MOD(gpio, field, reg, val) \ - { \ - GPIO_##field##_t tmp; \ - tmp.__FULL = gpio->field; \ - tmp.reg = val; \ - gpio->field = tmp.__FULL; \ - } +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} - /* Alternate Function I/O */ - typedef struct - { - uint32_t RESERVED0; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR; - } AFIO_TypeDef; +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; /* Remap Register 1 */ + __IO uint32_t EXTICR; /* External Interrupt Configuration Register 1*/ +} AFIO_TypeDef; - /* Inter Integrated Circuit Interface */ - typedef struct - { - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; - } I2C_TypeDef; +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; /* I2C Control Register 1 */ + uint16_t RESERVED0; + __IO uint16_t CTLR2; /* I2C Control Register 2 */ + uint16_t RESERVED1; + __IO uint16_t OADDR1; /* I2C Address Register 1 */ + uint16_t RESERVED2; + __IO uint16_t OADDR2; /* I2C Address Register 1 */ + uint16_t RESERVED3; + __IO uint16_t DATAR; /* I2C Data Register */ + uint16_t RESERVED4; + __IO uint16_t STAR1; /* I2C Status Register 1 */ + uint16_t RESERVED5; + __IO uint16_t STAR2; /* I2C Status Register 2 */ + uint16_t RESERVED6; + __IO uint16_t CKCFGR; /* I2C Clock Register */ + uint16_t RESERVED7; +} I2C_TypeDef; - /* Independent WatchDog */ - typedef struct - { - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; - } IWDG_TypeDef; +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; /* Control Register */ + __IO uint32_t PSCR; /* Prescaler Register */ + __IO uint32_t RLDR; /* Reload Register */ + __IO uint32_t STATR; /* Status Register */ +} IWDG_TypeDef; - /* Power Control */ - typedef struct - { - __IO uint32_t CTLR; - __IO uint32_t CSR; - __IO uint32_t AWUCSR; - __IO uint32_t AWUWR; - __IO uint32_t AWUPSC; - } PWR_TypeDef; +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; /* Power Control Register */ + __IO uint32_t CSR; /* Power Control/Status Register */ + __IO uint32_t AWUCSR; /* Auto-wakeup Control/Status Register */ + __IO uint32_t AWUWR; /* Auto-wakeup Window Comparison Value Register */ + __IO uint32_t AWUPSC; /* Auto-wakeup Crossover Factor Register */ +} PWR_TypeDef; - /* Reset and Clock Control */ - typedef struct - { - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; - __IO uint32_t RESERVED0; - __IO uint32_t RSTSCKR; - } RCC_TypeDef; +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; /* Clock Control Register */ + __IO uint32_t CFGR0; /* Clock Configuration Register 0 */ + __IO uint32_t INTR; /* Clock Interrupt Register */ + __IO uint32_t APB2PRSTR; /* APB2 Peripheral Reset Register */ + __IO uint32_t APB1PRSTR; /* APB1 Peripheral Reset Register */ + __IO uint32_t AHBPCENR; /* AHB Peripheral Clock Enable Register */ + __IO uint32_t APB2PCENR; /* APB2 Peripheral Clock Enable Register */ + __IO uint32_t APB1PCENR; /* APB1 Peripheral Clock Enable Register */ + __IO uint32_t RESERVED0; + __IO uint32_t RSTSCKR; /* Control/Status Register */ +} RCC_TypeDef; - /* Serial Peripheral Interface */ - typedef struct - { - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - uint32_t RESERVED7; - uint32_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; - } SPI_TypeDef; +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; /* SPI Control Register 1 */ + uint16_t RESERVED0; + __IO uint16_t CTLR2; /* SPI Control Register 1 */ + uint16_t RESERVED1; + __IO uint16_t STATR; /* SPI Status Register */ + uint16_t RESERVED2; + __IO uint16_t DATAR; /* SPI Data Register */ + uint16_t RESERVED3; + __IO uint16_t CRCR; /* SPI Polynomial Register */ + uint16_t RESERVED4; + __IO uint16_t RCRCR; /* SPI Receive CRC Register */ + uint16_t RESERVED5; + __IO uint16_t TCRCR; /* SPI Transmit CRC Register */ + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; /* SPI High-speed control register */ + uint16_t RESERVED9; +} SPI_TypeDef; - /* TIM */ - typedef struct - { - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint32_t CH1CVR; - __IO uint32_t CH2CVR; - __IO uint32_t CH3CVR; - __IO uint32_t CH4CVR; - __IO uint16_t BDTR; - uint16_t RESERVED13; - __IO uint16_t DMACFGR; - uint16_t RESERVED14; - __IO uint16_t DMAADR; - uint16_t RESERVED15; - } TIM_TypeDef; +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; /* Control Register 1 */ + uint16_t RESERVED0; + __IO uint16_t CTLR2; /* Control Register 2 */ + uint16_t RESERVED1; + __IO uint16_t SMCFGR; /* Slave Mode Control Register */ + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; /* DMA/Interrupt Enable Register */ + uint16_t RESERVED3; + __IO uint16_t INTFR; /* Interrupt Status Register */ + uint16_t RESERVED4; + __IO uint16_t SWEVGR; /* Event Generation Register */ + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; /* Compare/Capture Control Register 1 */ + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; /* Compare/Capture Control Register 2 */ + uint16_t RESERVED7; + __IO uint16_t CCER; /* Compare/Capture Enable Register */ + uint16_t RESERVED8; + __IO uint16_t CNT; /* Counters */ + uint16_t RESERVED9; + __IO uint16_t PSC; /* Counting Clock Prescaler */ + uint16_t RESERVED10; + __IO uint16_t ATRLR; /* Auto-reload value register */ + uint16_t RESERVED11; + __IO uint16_t RPTCR; /* Recurring Count Value Register */ + uint16_t RESERVED12; + __IO uint32_t CH1CVR; /* Compare/Capture Register 1 */ + __IO uint32_t CH2CVR; /* Compare/Capture Register 2 */ + __IO uint32_t CH3CVR; /* Compare/Capture Register 3 */ + __IO uint32_t CH4CVR; /* Compare/Capture Register 4 */ + __IO uint16_t BDTR; /* Brake and Deadband Registers */ + uint16_t RESERVED13; + __IO uint16_t DMACFGR; /* DMA Control Register */ + uint16_t RESERVED14; + __IO uint16_t DMAADR; /* DMA Address Register For Continuous Mode */ + uint16_t RESERVED15; +} TIM_TypeDef; - /* Universal Synchronous Asynchronous Receiver Transmitter */ - typedef struct - { - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; - } USART_TypeDef; +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint32_t STATR; /* USART Status Register */ + __IO uint32_t DATAR; /* USART Data Register */ + __IO uint32_t BRR; /* USART Baud Rate Register */ + __IO uint32_t CTLR1; /* USART Control Register 1 */ + __IO uint32_t CTLR2; /* USART Control Register 2 */ + __IO uint32_t CTLR3; /* USART Control Register 3 */ + __IO uint32_t GPR; /* USART Protection Time and Prescaler Register */ +} USART_TypeDef; - /* Window WatchDog */ - typedef struct - { - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; - } WWDG_TypeDef; +/* Window WatchDog */ +typedef struct +{ + __IO uint16_t CTLR; /* Control Register */ + uint16_t RESERVED1; + __IO uint16_t CFGR; /* Configuration Register */ + uint16_t RESERVED2; + __IO uint16_t STATR; /* Status Register */ +} WWDG_TypeDef; - /* Enhanced Registers */ - typedef struct - { - __IO uint32_t EXTEN_CTR; - } EXTEN_TypeDef; - - /* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ - typedef struct - { - __IO uint32_t CTR; - } EXTEND_TypeDef; +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; /* Configure Extended Control Registers */ +} EXTEN_TypeDef; #endif /* Peripheral memory map */ #ifdef __ASSEMBLER__ -#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ -#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ #else -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ -#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ #endif -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ -#define ESIG_BASE ((uint32_t)0x1FFFF7E0) -#define INFO_BASE ((uint32_t)0x1FFFF704) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ -#define EXTEN_BASE ((uint32_t)0x40023800) -#define VENDOR_CFG0_BASE ((uint32_t)0x1FFFF7D4) -#define CFG0_PLL_TRIM (VENDOR_CFG0_BASE) +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) -#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) -#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) -// AFIO CTLR Bits -#define PB6_FILT_EN (1 << 27) -#define PB5_FILT_EN (1 << 26) -#define PA4_FILT_EN (1 << 25) -#define PA3_FILT_EN (1 << 24) -#define UDM_BC_CMPO (1 << 19) -#define UDP_BC_CMPO (1 << 17) -#define UDM_BC_VSRC (1 << 17) -#define UDP_BC_VSRC (1 << 16) -#define USBPD_IN_HVT (1 << 9) -#define USBPD_PHY_V33 (1 << 8) -#define USB_IOEN (1 << 7) -#define USB_PHY_V33 (1 << 6) -#define UDP_PUE_00 (0b00 << 2) -#define UDP_PUE_01 (0b01 << 2) -#define UDP_PUE_10 (0b10 << 2) -#define UDP_PUE_11 (0b11 << 2) -#define UDM_PUE_00 (0b00 << 0) -#define UDM_PUE_01 (0b01 << 0) -#define UDM_PUE_10 (0b10 << 0) -#define UDM_PUE_11 (0b11 << 0) -#define UDP_PUE_MASK 0x0000000C -#define UDP_PUE_DISABLE 0x00000000 -#define UDP_PUE_35UA 0x00000004 -#define UDP_PUE_10K 0x00000008 -#define UDP_PUE_1K5 0x0000000C -#define UDM_PUE_MASK 0x00000003 -#define UDM_PUE_DISABLE 0x00000000 -#define UDM_PUE_35UA 0x00000001 -#define UDM_PUE_10K 0x00000002 -#define UDM_PUE_1K5 0x00000003 +#define VENDOR_CFG0_BASE ((uint32_t)0x1FFFF7D4) +#define CFG0_PLL_TRIM (VENDOR_CFG0_BASE) -// USB PD Bits -#define IE_TX_END (1 << 15) -#define IE_RX_RESET (1 << 14) -#define IE_RX_ACT (1 << 13) -#define IE_RX_BYTE (1 << 12) -#define IE_RX_BIT (1 << 11) -#define IE_PD_IO (1 << 10) -#define WAKE_POLAR (1 << 5) -#define PD_RST_EN (1 << 4) -#define PD_DMA_EN (1 << 3) -#define CC_SEL (1 << 2) -#define PD_ALL_CLR (1 << 1) -#define PD_FILT_EN (1 << 0) -#define BMC_CLK_CNT_MASK (0xff) +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) -// R8_CONTROL -#define BMC_BYTE_HI (1 << 7) -#define TX_BIT_BACK (1 << 6) -#define DATA_FLAG (1 << 5) -#define RX_STATE_MASK (0x7 << 2) -#define RX_STATE_0 (1 << 2) -#define RX_STATE_1 (1 << 3) -#define RX_STATE_2 (1 << 4) -#define BMC_START (1 << 1) -#define PD_TX_EN (1 << 0) -#define TX_SEL4_MASK (3 << 6) -#define TX_SEL4_0 (1 << 6) -#define TX_SEL4_1 (1 << 7) -#define TX_SEL3_MASK (3 << 4) -#define TX_SEL3_0 (1 << 4) -#define TX_SEL3_1 (1 << 5) -#define TX_SEL2_MASK (3 << 2) -#define TX_SEL2_0 (1 << 2) -#define TX_SEL2_1 (1 << 3) -#define TX_SEL1 (1 << 0) - -#define BMC_TX_SZ_MASK (0x1ff) - -// R8_STATUS -#define IF_TX_END (1 << 7) -#define IF_RX_RESET (1 << 6) -#define IF_RX_ACT (1 << 5) -#define IF_RX_BYTE (1 << 4) -#define IF_RX_BIT (1 << 3) -#define IFBUF_ERR (1 << 2) -#define BMC_AUX_MASK (3 << 0) -#define BMC_AUX_1 (1 << 1) -#define BMC_AUX_0 (1 << 0) - -// PORT CC1 -#define CC1_CE_MASK (7 << 5) -#define CC1_CE_0 (1 << 5) -#define CC1_CE_1 (2 << 5) -#define CC1_CE_2 (4 << 5) - -#define CC1_LVE (1 << 4) -#define CC1_PU_MASK (3 << 2) -#define CC1_PU_DISABLE (0 << 2) -#define CC1_PU_330uA (1 << 2) -#define CC1_PU_180uA (2 << 2) -#define CC1_PU_80uA (3 << 2) -#define PA_CC1_AI (1 << 0) - -#define CC2_CE_MASK (7 << 5) -#define CC2_CE_0 (1 << 5) -#define CC2_CE_1 (2 << 5) -#define CC2_CE_2 (4 << 5) - -#define CC2_LVE (1 << 4) -#define CC2_PU_MASK (3 << 2) -#define CC2_PU_DISABLE (0 << 2) -#define CC2_PU_330uA (1 << 2) -#define CC2_PU_180uA (2 << 2) -#define CC2_PU_80uA (3 << 2) -#define PA_CC2_AI (1 << 0) /* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define ESIG ((ESG_TypeDef *)ESIG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESIG_TypeDef *)ESIG_BASE) // Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. -//#define INFO ((INFO_TypeDef *)INFO_BASE) -//#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) -//#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + + + /******************************************************************************/ /* Peripheral Registers Bits Definition */ @@ -757,3822 +621,3736 @@ extern "C" /******************************************************************************/ /******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ +#define ADC_AWD ((uint32_t)0x00000001) /* Analog watchdog flag */ +#define ADC_EOC ((uint32_t)0x00000002) /* End of conversion */ +#define ADC_JEOC ((uint32_t)0x00000004) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint32_t)0x00000008) /* Injected channel Start flag */ +#define ADC_STRT ((uint32_t)0x00000010) /* Regular channel Start flag */ /******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ -#define ADC_CALVOLSELECT ((uint32_t)0x06000000) -#define ADC_CALVOLSELECT_0 ((uint32_t)0x02000000) -#define ADC_CALVOLSELECT_1 ((uint32_t)0x04000000) +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_CALVOLSELECT ((uint32_t)0x06000000) +#define ADC_CALVOLSELECT_0 ((uint32_t)0x02000000) +#define ADC_CALVOLSELECT_1 ((uint32_t)0x04000000) /******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ /****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ /****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ /****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ +#define ADC_JOFFSET1 ((uint32_t)0x000002FF) /* Data offset for injected channel 1 */ /****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ +#define ADC_JOFFSET2 ((uint32_t)0x000002FF) /* Data offset for injected channel 2 */ /****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ +#define ADC_JOFFSET3 ((uint32_t)0x000002FF) /* Data offset for injected channel 3 */ /****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ +#define ADC_JOFFSET4 ((uint32_t)0x000002FF) /* Data offset for injected channel 4 */ /******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ +#define ADC_HT ((uint32_t)0x000002FF) /* Analog watchdog high threshold */ /******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ +#define ADC_LT ((uint32_t)0x000002FF) /* Analog watchdog low threshold */ /******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ /******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ /******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ /******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ /******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ +#define ADC_IDATAR1_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ /******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ +#define ADC_IDATAR2_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ /******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ +#define ADC_IDATAR3_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ /******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ +#define ADC_IDATAR4_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ /******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ /******************** Bit definition for ADC_DLYR register ********************/ -#define ADC_DLYR_DLYVLU ((uint32_t)0x1FF) -#define ADC_DLYR_DLYSRC ((uint32_t)0x200) +#define ADC_DLYR_DLYVLU ((uint32_t)0x000001FF) +#define ADC_DLYR_DLYSRC ((uint32_t)0x00000200) /******************************************************************************/ /* DMA Controller */ /******************************************************************************/ /******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + /******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR4 register *******************/ -#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /****************** Bit definition for DMA_CFGR5 register *******************/ -#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ /******************* Bit definition for DMA_CFGR6 register *******************/ -#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR7 register *******************/ -#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ -#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ -#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ -#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ -#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ /****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /******************************************************************************/ /* External Interrupt/Event Controller */ /******************************************************************************/ /******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ /******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ /****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ /****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ /****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ /******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ /******************************************************************************/ /* FLASH and Option Bytes Registers */ /******************************************************************************/ /******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + /****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ /***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ /****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ -#define FLASH_STATR_MODE ((uint16_t)0x4000) -#define FLASH_STATR_LOCK ((uint16_t)0x8000) +#define FLASH_STATR_BSY ((uint32_t)0x00000001) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint32_t)0x00000010) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint32_t)0x00000020) /* End of operation */ +#define FLASH_STATR_MODE ((uint32_t)0x00004000) +#define FLASH_STATR_LOCK ((uint32_t)0x00008000) /******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG (0x0001) /* Programming */ -#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ -#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT (0x0040) /* Start */ -#define FLASH_CTLR_LOCK (0x0080) /* Lock */ -#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FLOCK (0x8000) -#define FLASH_CTLR_PAGE_PG (0x00010000) /* Page Programming 64Byte */ -#define FLASH_CTLR_PAGE_ER (0x00020000) /* Page Erase 64Byte */ -#define FLASH_CTLR_BUF_LOAD (0x00040000) /* Buffer Load */ -#define FLASH_CTLR_BUF_RST (0x00080000) /* Buffer Reset */ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 64Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint32_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint32_t)0x00080000) /* Buffer Reset */ /******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ /****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ +#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /* Read protection */ -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_STANDY_RST ((uint16_t)0x0010) -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ -#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080) -#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) +#define FLASH_OBR_USER ((uint32_t)0x000003FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint32_t)0x00000004) /* WDG_SW */ +#define FLASH_OBR_STANDY_RST ((uint32_t)0x00000010) +#define FLASH_OBR_RST_MODE ((uint32_t)0x00000060) /* RST_MODE */ +#define FLASH_OBR_STATR_MODE ((uint32_t)0x00000080) +#define FLASH_OBR_FIX_11 ((uint32_t)0x00000300) /****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ +#define FLASH_WPR_WRP ((uint32_t)0x0000FFFF) /* Write Protect */ /****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ /****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ /****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ /****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ /****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ /****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ /****************** Bit definition for FLASH_MODEKEYR register ******************/ -#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) -#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) /****************** Bit definition for FLASH__BOOT_MODEKEYR register ******************/ -#define FLASH_BOOT_MODEKEYR_KEY1 ((uint32_t)0x45670123) -#define FLASH_BOOT_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) +#define FLASH_BOOT_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_BOOT_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) /******************************************************************************/ /* General Purpose and Alternate Function I/O */ /******************************************************************************/ /******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ /******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ +#define GPIO_INDR_IDR0 ((uint32_t)0x00000001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint32_t)0x00000002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint32_t)0x00000004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint32_t)0x00000008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint32_t)0x00000010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint32_t)0x00000020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint32_t)0x00000040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint32_t)0x00000080) /* Port input data, bit 7 */ /******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ +#define GPIO_OUTDR_ODR0 ((uint32_t)0x00000001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint32_t)0x00000002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint32_t)0x00000004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint32_t)0x00000008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint32_t)0x00000010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint32_t)0x00000020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint32_t)0x00000040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint32_t)0x00000080) /* Port output data, bit 7 */ /****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ /******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ +#define GPIO_BCR_BR0 ((uint32_t)0x00000001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint32_t)0x00000002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint32_t)0x00000004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint32_t)0x00000008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint32_t)0x00000010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint32_t)0x00000020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint32_t)0x00000040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint32_t)0x00000080) /* Port x Reset bit 7 */ /****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ /****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00200000) /* USART1 remapping higher bit */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00200000) /* USART1 remapping higher bit */ -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PC5, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CH2N/PA2, CH3N/PD1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 ((uint32_t)0x00000040) /* Partial remap (ETR/PC5, CH1/PC6, CH2/PC7, CH3/PC0, CH4/PD3, BKIN/PC1, CH1N/PC3, CH2N/PC4, CH3N/PD1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP2 ((uint32_t)0x00000080) /* Partial remap (ETR/PD4, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CN2N/PA2, CH3N/PD1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PC2, CH1/PC4, CH2/PC7, CH3/PC5, CH4/PD4, BKIN/PC1, CH1N/PC3, CH2N/PD2, CH3N/PC6) */ -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PD4, CH2/PD3, CH3/PC0, CH4/PD4) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PC5, CH2/PC2, CH3/PD4, CH4/PC1) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PC1, CH2/PD3, CH3/PC0, CH4/PD7) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PC1, CH2/PC7, CH3/PD6, CH4/PD5) */ -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 /* legacy compatibility */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP2 ((uint32_t)0x00000080) /* Partial remap (ETR/PD4, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CN2N/PA2, CH3N/PD1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ +#define AFIO_PCFR1_I2C1_HIGH_BIT_REMAP ((uint32_t)0x00400000) +#define AFIO_PCFR1_TIM1_1_RM ((uint32_t)0x00800000) -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define AFIO_PCFR1_SWCFG ((uint32_t)0x07000000) /* SWCFG[2:0] bits (Serial Wire IO Debug configuration) */ +#define AFIO_PCFR1_SWCFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWCFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWCFG_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define AFIO_PCFR1_SWCFG_ENABLE ((uint32_t)0x00000000) /* SWD (SDI) enabled */ +#define AFIO_PCFR1_SWCFG_DISABLE ((uint32_t)0x04000000) /* SWD (SDI) disabled */ -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_PCFR1_USART1_HIGH_BIT_REMAP ((uint32_t)0x00200000) -#define AFIO_PCFR1_I2C1_HIGH_BIT_REMAP ((uint32_t)0x00400000) -#define AFIO_PCFR1_TIM1_1_RM ((uint32_t)0x00800000) - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ /***************** Bit definition for AFIO_EXTICR register *****************/ -#define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ -#define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ -#define AFIO_EXTICR_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ -#define AFIO_EXTICR_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ -#define AFIO_EXTICR_EXTI4 ((uint16_t)0x0300) /* EXTI 4 configuration */ -#define AFIO_EXTICR_EXTI5 ((uint16_t)0x0C00) /* EXTI 5 configuration */ -#define AFIO_EXTICR_EXTI6 ((uint16_t)0x3000) /* EXTI 6 configuration */ -#define AFIO_EXTICR_EXTI7 ((uint16_t)0xC000) /* EXTI 7 configuration */ +#define AFIO_EXTICR_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */ +#define AFIO_EXTICR_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */ +#define AFIO_EXTICR_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */ +#define AFIO_EXTICR_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */ +#define AFIO_EXTICR_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */ -#define AFIO_EXTICR_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ -#define AFIO_EXTICR_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ -#define AFIO_EXTICR_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ -#define AFIO_EXTICR_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ -#define AFIO_EXTICR_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ -#define AFIO_EXTICR_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ -#define AFIO_EXTICR_EXTI4_PC ((uint16_t)0x0200) /* PC[4] pin */ -#define AFIO_EXTICR_EXTI4_PD ((uint16_t)0x0300) /* PD[4] pin */ -#define AFIO_EXTICR_EXTI5_PC ((uint16_t)0x0800) /* PC[5] pin */ -#define AFIO_EXTICR_EXTI5_PD ((uint16_t)0x0C00) /* PD[5] pin */ -#define AFIO_EXTICR_EXTI6_PC ((uint16_t)0x2000) /* PC[6] pin */ -#define AFIO_EXTICR_EXTI6_PD ((uint16_t)0x3000) /* PD[6] pin */ -#define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ -#define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ +#define AFIO_EXTICR_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ +#define AFIO_EXTICR_EXTI0_PD ((uint32_t)0x00000003) /* PD[0] pin */ +#define AFIO_EXTICR_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */ +#define AFIO_EXTICR_EXTI1_PD ((uint32_t)0x0000000C) /* PD[1] pin */ +#define AFIO_EXTICR_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */ +#define AFIO_EXTICR_EXTI2_PD ((uint32_t)0x00000030) /* PD[2] pin */ +#define AFIO_EXTICR_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */ +#define AFIO_EXTICR_EXTI3_PD ((uint32_t)0x000000C0) /* PD[3] pin */ +#define AFIO_EXTICR_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */ +#define AFIO_EXTICR_EXTI4_PD ((uint32_t)0x00000300) /* PD[4] pin */ +#define AFIO_EXTICR_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */ +#define AFIO_EXTICR_EXTI5_PD ((uint32_t)0x00000C00) /* PD[5] pin */ +#define AFIO_EXTICR_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */ +#define AFIO_EXTICR_EXTI6_PD ((uint32_t)0x00003000) /* PD[6] pin */ +#define AFIO_EXTICR_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */ +#define AFIO_EXTICR_EXTI7_PD ((uint32_t)0x0000C000) /* PD[7] pin */ /******************************************************************************/ /* Independent WATCHDOG */ /******************************************************************************/ /******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ /******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ /******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ /******************************************************************************/ /* Inter-integrated Circuit Interface */ /******************************************************************************/ /******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ /******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ /******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ /******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ /******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ /******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ /******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ /******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + /******************************************************************************/ /* Power Control */ /******************************************************************************/ /******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ +#define PWR_CTLR_PDDS ((uint32_t)0x00000002) /* Power Down Deepsleep */ +#define PWR_CTLR_PVDE ((uint32_t)0x00000010) /* Power Voltage Detector Enable */ -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ +#define PWR_CTLR_PLS ((uint32_t)0x000000E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define PWR_PVDLevel_0 ((uint16_t)0x0000) -#define PWR_PVDLevel_1 ((uint16_t)0x0020) -#define PWR_PVDLevel_2 ((uint16_t)0x0040) -#define PWR_PVDLevel_3 ((uint16_t)0x0060) -#define PWR_PVDLevel_4 ((uint16_t)0x0080) -#define PWR_PVDLevel_5 ((uint16_t)0x00A0) -#define PWR_PVDLevel_6 ((uint16_t)0x00C0) -#define PWR_PVDLevel_7 ((uint16_t)0x00E0) - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_7 ((uint32_t)0x000000E0) /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ +#define PWR_CSR_PVDO ((uint32_t)0x00000004) /* PVD Output */ /******************* Bit definition for PWR_AWUCSR register ********************/ -#define PWR_AWUCSR_AWUEN ((uint16_t)0x0002) +#define PWR_AWUCSR_AWUEN ((uint32_t)0x00000002) /******************* Bit definition for PWR_AWUWR register ********************/ -#define PWR_AWUWR ((uint16_t)0x003F) +#define PWR_AWUWR ((uint32_t)0x0000003F) /******************* Bit definition for PWR_AWUWR register ********************/ -#define PWR_AWUPSC ((uint16_t)0x000F) -#define PWR_AWUPSC_0 ((uint16_t)0x0000) -#define PWR_AWUPSC_2 ((uint16_t)0x0002) -#define PWR_AWUPSC_4 ((uint16_t)0x0003) -#define PWR_AWUPSC_8 ((uint16_t)0x0004) -#define PWR_AWUPSC_16 ((uint16_t)0x0005) -#define PWR_AWUPSC_32 ((uint16_t)0x0006) -#define PWR_AWUPSC_64 ((uint16_t)0x0007) -#define PWR_AWUPSC_128 ((uint16_t)0x0008) -#define PWR_AWUPSC_256 ((uint16_t)0x0009) -#define PWR_AWUPSC_512 ((uint16_t)0x000A) -#define PWR_AWUPSC_1024 ((uint16_t)0x000B) -#define PWR_AWUPSC_2048 ((uint16_t)0x000C) -#define PWR_AWUPSC_4096 ((uint16_t)0x000D) -#define PWR_AWUPSC_10240 ((uint16_t)0x000E) -#define PWR_AWUPSC_61440 ((uint16_t)0x000F) +#define PWR_AWUPSC ((uint32_t)0x0000000F) +#define PWR_AWUPSC_0 ((uint32_t)0x00000000) +#define PWR_AWUPSC_OFF0 ((uint32_t)0x00000000) +#define PWR_AWUPSC_OFF1 ((uint32_t)0x00000001) +#define PWR_AWUPSC_2 ((uint32_t)0x00000002) +#define PWR_AWUPSC_4 ((uint32_t)0x00000003) +#define PWR_AWUPSC_8 ((uint32_t)0x00000004) +#define PWR_AWUPSC_16 ((uint32_t)0x00000005) +#define PWR_AWUPSC_32 ((uint32_t)0x00000006) +#define PWR_AWUPSC_64 ((uint32_t)0x00000007) +#define PWR_AWUPSC_128 ((uint32_t)0x00000008) +#define PWR_AWUPSC_256 ((uint32_t)0x00000009) +#define PWR_AWUPSC_512 ((uint32_t)0x0000000A) +#define PWR_AWUPSC_1024 ((uint32_t)0x0000000B) +#define PWR_AWUPSC_2048 ((uint32_t)0x0000000C) +#define PWR_AWUPSC_4096 ((uint32_t)0x0000000D) +#define PWR_AWUPSC_10240 ((uint32_t)0x0000000E) +#define PWR_AWUPSC_61440 ((uint32_t)0x0000000F) /******************************************************************************/ /* Reset and Clock Control */ /******************************************************************************/ /******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + /******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ -#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ -#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ -#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_ADCPRE_2 ((uint32_t)0x00002000) -#define RCC_ADCPRE_3 ((uint32_t)0x00004000) -#define RCC_ADCPRE_4 ((uint32_t)0x00008000) +#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_ADCPRE_2 ((uint32_t)0x00002000) +#define RCC_ADCPRE_3 ((uint32_t)0x00004000) +#define RCC_ADCPRE_4 ((uint32_t)0x00008000) -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* HBCLK divided by 2 */ +/* includes 0x00000800, + 0x00001000, + 0x00001800 */ +#define RCC_ADCPRE_DIV4_1 ((uint32_t)0x00002000) /* HBCLK divided by 4 */ +#define RCC_ADCPRE_DIV8_2 ((uint32_t)0x00002800) /* HBCLK divided by 8 */ +#define RCC_ADCPRE_DIV16_2 ((uint32_t)0x00003000) /* HBCLK divided by 16 */ +#define RCC_ADCPRE_DIV32_2 ((uint32_t)0x00003800) /* HBCLK divided by 32 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* HBCLK divided by 4 */ +/* includes 0x00004800, + 0x00005000, + 0x00005800 */ +#define RCC_ADCPRE_DIV8_1 ((uint32_t)0x00006000) /* HBCLK divided by 8 */ +#define RCC_ADCPRE_DIV16_1 ((uint32_t)0x00006800) /* HBCLK divided by 16 */ +#define RCC_ADCPRE_DIV32_1 ((uint32_t)0x00007000) /* HBCLK divided by 32 */ +#define RCC_ADCPRE_DIV64_1 ((uint32_t)0x00007800) /* HBCLK divided by 64 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* HBCLK divided by 6 */ +/* includes 0x00008800, + 0x00009000, + 0x00009800 */ +#define RCC_ADCPRE_DIV12 ((uint32_t)0x0000A000) /* HBCLK divided by 12 */ +#define RCC_ADCPRE_DIV24 ((uint32_t)0x0000A800) /* HBCLK divided by 24 */ +#define RCC_ADCPRE_DIV48 ((uint32_t)0x0000B000) /* HBCLK divided by 48 */ +#define RCC_ADCPRE_DIV96 ((uint32_t)0x0000B800) /* HBCLK divided by 96 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* HBCLK divided by 8 */ +/* includes 0x0000C800, + 0x0000D000, + 0x0000D800 */ +#define RCC_ADCPRE_DIV16 ((uint32_t)0x0000E000) /* HBCLK divided by 16 */ +#define RCC_ADCPRE_DIV32 ((uint32_t)0x0000E800) /* HBCLK divided by 32 */ +#define RCC_ADCPRE_DIV64 ((uint32_t)0x0000F000) /* HBCLK divided by 64 */ +#define RCC_ADCPRE_DIV128 ((uint32_t)0x0000F800) /* HBCLK divided by 128 */ -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ +#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ - -#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -/******************* Bit definition for RCC_CFGR2 register *******************/ +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ /******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_APB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ -#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ -#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ /***************** Bit definition for RCC_APB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ -#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ -#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ -#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ -#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ -#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ -#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ /****************** Bit definition for RCC_AHBPCENR register ******************/ -#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ -#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ -#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ -#define RCC_USBHD ((uint32_t)0x1000) -#define RCC_USBFS ((uint32_t)0x1000) -#define RCC_USBPD ((uint32_t)0x20000) +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint32_t)0x1000) +#define RCC_USBFS ((uint32_t)0x1000) +#define RCC_USBPD ((uint32_t)0x20000) /****************** Bit definition for RCC_APB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ -#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ /***************** Bit definition for RCC_APB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ -#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ -#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ /******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ /****************** Bit definition for RCC_AHBRSTR register *****************/ + + + /******************************************************************************/ /* Serial Peripheral Interface */ /******************************************************************************/ /******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ /******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ -#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ /******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ /******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ /****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ /****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ /****************** Bit definition for SPI_HSCR register ******************/ -#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /******************************************************************************/ /* TIM */ /******************************************************************************/ /******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ /******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ /******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ /******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ /******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ /******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ +#define TIM_UG ((uint16_t)0x0001) /* Update Generation */ +#define TIM_CC1G ((uint16_t)0x0002) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint16_t)0x0004) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint16_t)0x0008) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint16_t)0x0010) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint16_t)0x0020) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint16_t)0x0040) /* Trigger Generation */ +#define TIM_BG ((uint16_t)0x0080) /* Break Generation */ /****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ /****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ /******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ /******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ /******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ /******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ /******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ /******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_CCR1 ((uint32_t)0x0000FFFF) /* Capture/Compare 1 Value */ +#define TIM_CH1CVR_LEVEL1 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ /******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_CCR2 ((uint32_t)0x0000FFFF) /* Capture/Compare 2 Value */ +#define TIM_CH2CVR_LEVEL2 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ /******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_CCR3 ((uint32_t)0x0000FFFF) /* Capture/Compare 3 Value */ +#define TIM_CH3CVR_LEVEL3 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ /******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_CCR4 ((uint32_t)0x0000FFFF) /* Capture/Compare 4 Value */ +#define TIM_CH4CVR_LEVEL4 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ /******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ /******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ /******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ /******************************************************************************/ /* Universal Synchronous Asynchronous Receiver Transmitter */ /******************************************************************************/ /******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ /******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ /****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ /****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ /****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ /****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ /****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ /******************************************************************************/ /* Window WATCHDOG */ /******************************************************************************/ /******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ /******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ /******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ /******************************************************************************/ /* ENHANCED FUNNCTION */ /******************************************************************************/ /**************************** Enhanced register *****************************/ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ -#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ -#define EXTEN_OPA_EN ((uint32_t)0x00010000) -#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) -#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ + + +#define EXTEN_OPA_EN ((uint32_t)0x00010000) +#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) +#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) + #ifdef __cplusplus } #endif + + #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif + + /* ch32v00x_gpio.c -----------------------------------------------------------*/ /* MASK */ -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + /* ch32v00x_adc.c ------------------------------------------------------------*/ /* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) /* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) /* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) /* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) /* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) /* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) ///* CTLR1 register Mask */ -// Editor's Note: Overloaded Definition -#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) /* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) /* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) /* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) /* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) +#define CTLR2_CAL_Set ((uint32_t)0x00000004) /* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) /* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) /* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) /* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) /* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) /* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) /* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) /* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) /* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) /* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) /* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) /* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) /* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) /* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) /* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) +#define IDATAR_Offset ((uint8_t)0x28) + + + /* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + /* ch32v00x_dma.c ------------------------------------------------------------*/ /* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + /* DMA2 FLAG mask */ // Editor's note: Overloaded Definition. -#define DMA2_FLAG_Mask ((uint32_t)0x10000000) +#define DMA2_FLAG_Mask ((uint32_t)0x10000000) /* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) /* ch32v00x_exti.c -----------------------------------------------------------*/ + /* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) +#define EXTI_LINENONE ((uint32_t)0x00000) /* ch32v00x_flash.c ----------------------------------------------------------*/ /* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) + /* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_BUF_LOAD ((uint32_t)0x00040000) -#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) /* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) /* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) /* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + /* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) /* Flash Program Valid Address */ -#define ValidAddrStart (FLASH_BASE) -#define ValidAddrEnd (FLASH_BASE + 0x4000) +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + /* ch32v00x_i2c.c ------------------------------------------------------------*/ + /* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) /* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) /* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) /* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) /* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) /* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) /* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) /* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) /* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) /* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) ////* I2C registers Masks */ // Editor's note: Overloaded Definition. -#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) /* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) /* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) /* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) /* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) /* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) /* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) /* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) +#define CKCFGR_FS_Set ((uint16_t)0x8000) /* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) /* I2C FLAG mask */ -// Editor's Note: Overloaded Definition -#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) +//Editor's Note: Overloaded Definition +#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) /* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) +#define ITEN_Mask ((uint32_t)0x07000000) /* ch32v00x_iwdg.c -----------------------------------------------------------*/ /* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + /* ch32v00x_pwr.c ------------------------------------------------------------*/ + /* PWR registers bit mask */ /* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) -#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) /* ch32v00x_rcc.c ------------------------------------------------------------*/ /* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) /* RCC registers bit mask */ /* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) /* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + /* RCC Flag Mask */ -// Editor's Note: Overloaded Definition -#define RCC_FLAG_Mask ((uint8_t)0x1F) +//Editor's Note: Overloaded Definition +#define RCC_FLAG_Mask ((uint8_t)0x1F) /* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) /* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) /* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) /* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) #ifndef __ASSEMBLER__ - static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; - static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; +static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; #endif + + /* ch32v00x_spi.c ------------------------------------------------------------*/ /* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + /* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) /* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) /* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) /* SPI registers Masks */ -// Editor's Note: Overloaded Definition -#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + + /* ch32v00x_tim.c ------------------------------------------------------------*/ /* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) /* ch32v00x_usart.c ----------------------------------------------------------*/ /* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -// Editor's Note: Overloaded Definition -#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ /* USART OverSampling-8 Mask */ -#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ -#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ /* USART One Bit Sampling Mask */ -#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ /* ch32v00x_wwdg.c ------------------------------------------------------------*/ /* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) +#define CTLR_WDGA_Set ((uint32_t)0x00000080) /* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + /* ch32v00x_adc.h ------------------------------------------------------------*/ /* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ + +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - /* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) /* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) +#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) -#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) /* ADC_sampling_time */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_9Cycles ((uint8_t)0x01) -#define ADC_SampleTime_15Cycles ((uint8_t)0x02) -#define ADC_SampleTime_30Cycles ((uint8_t)0x03) -#define ADC_SampleTime_43Cycles ((uint8_t)0x04) -#define ADC_SampleTime_57Cycles ((uint8_t)0x05) -#define ADC_SampleTime_73Cycles ((uint8_t)0x06) -#define ADC_SampleTime_241Cycles ((uint8_t)0x07) +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_9Cycles ((uint8_t)0x01) +#define ADC_SampleTime_15Cycles ((uint8_t)0x02) +#define ADC_SampleTime_30Cycles ((uint8_t)0x03) +#define ADC_SampleTime_43Cycles ((uint8_t)0x04) +#define ADC_SampleTime_57Cycles ((uint8_t)0x05) +#define ADC_SampleTime_73Cycles ((uint8_t)0x06) +#define ADC_SampleTime_241Cycles ((uint8_t)0x07) /* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + /* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) /* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) /* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) /* ADC_calibration_voltage_definition */ -#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) -#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) +#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) +#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) /* ADC_external_trigger_sources_delay_channels_definition */ -#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200) +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200) -/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ + + + +/* ch32v003_dbgmcu.h ---------------------------------------------------------*/ /* DBGMCU_CR Register */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) /* ch32v00x_dma.h ------------------------------------------------------------*/ /* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) /* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) /* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) /* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) /* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) /* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) /* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) /* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) /* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) /* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - /* ch32v00x_exti.h -----------------------------------------------------------*/ + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ #ifndef __ASSEMBLER__ - /* EXTI mode enumeration */ - typedef enum - { - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 - } EXTIMode_TypeDef; +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; - /* EXTI Trigger enumeration */ - typedef enum - { - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 - } EXTITrigger_TypeDef; +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; #endif /* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ + +/* ch32v00x_flash.h ----------------------------------------------------------*/ - /* ch32v00x_flash.h ----------------------------------------------------------*/ #ifndef __ASSEMBLER__ - /* FLASH Status */ - typedef enum - { - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT, - FLASH_OP_RANGE_ERROR = 0xFD, - FLASH_ALIGN_ERROR = 0xFE, - FLASH_ADR_RANGE_ERROR = 0xFF, - } FLASH_Status; +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; #endif /* Flash_Latency */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + /* Values to be used with CH32V00x devices (1page = 64Byte) */ -#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ -#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ -#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ -#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ -#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ -#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ -#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ -#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ -#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ -#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ -#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ -#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ -#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ -#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ -#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ -#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ +#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ +#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ +#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ +#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ +#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ +#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ +#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ +#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ +#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ +#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ +#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ +#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ +#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ +#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ +#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ +#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ -#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ /* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ /* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ /* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ /* Option_Bytes_RST_ENandDT */ -#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ -#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ -#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ -#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */ +#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ +#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */ + /* Option_Bytes_Power_ON_Start_Mode */ -#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */ -#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */ +#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */ +#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */ -#define OB_STARTMODE_BOOT ((uint16_t)0x0020) /* Start in BOOT area */ -#define OB_STARTMODE_USER ((uint16_t)0x0000) /* Start in user area */ +#define OB_STARTMODE_BOOT ((uint16_t)0x0020) /* Start in BOOT area */ +#define OB_STARTMODE_USER ((uint16_t)0x0000) /* Start in user area */ /* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ /* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ /* System_Reset_Start_Mode */ -#define Start_Mode_USER ((uint32_t)0x00000000) -#define Start_Mode_BOOT ((uint32_t)0x00004000) +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) - /* ch32v00x_gpio.h ------------------------------------------------------------*/ + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ #ifndef __ASSEMBLER__ - /* Output Maximum frequency selection */ - typedef enum - { - GPIO_Speed_In = 0, - GPIO_Speed_10MHz, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz - } GPIOSpeed_TypeDef; +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz = 3, + GPIO_Speed_30MHz = 3, // Alias 30MHz to 50MHz. +} GPIOSpeed_TypeDef; #endif -#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_ANALOG 0 #define GPIO_CNF_IN_FLOATING 4 -#define GPIO_CNF_IN_PUPD 8 -#define GPIO_CNF_OUT_PP 0 -#define GPIO_CNF_OUT_OD 4 -#define GPIO_CNF_OUT_PP_AF 8 -#define GPIO_CNF_OUT_OD_AF 12 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 - /* Configuration Mode enumeration */ - /* - typedef enum - { - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 - } GPIOMode_TypeDef; - */ +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ #ifndef __ASSEMBLER__ - /* Bit_SET and Bit_RESET enumeration */ - typedef enum - { - Bit_RESET = 0, - Bit_SET - } BitAction; +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; #endif /* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - /* GPIO_Remap_define */ +/* GPIO_Remap_define */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ +#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ -#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ -#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ -#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ /* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) /* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) + /* ch32v00x_i2c.h ------------------------------------------------------------*/ /* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_I2C ((uint16_t)0x0000) /* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ /* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) /* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) /* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) /* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) /* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) /* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) /* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) /* I2C_interrupts_definition */ -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) /* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) /* SR1 register flags */ -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) /****************I2C Master Events (Events grouped in order of communication)********************/ -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ /* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ /* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /*EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave . - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ -/* Master Receive mode */ +/* Master Receive mode */ /* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master Transmitter mode*/ /* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /******************I2C Slave Events (Events grouped in order of communication)******************/ -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ -/* EVT1 */ +/* EVT1 */ /* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ -/* Slave Receiver mode*/ +/* Slave Receiver mode*/ /* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave Transmitter mode -----------------------*/ /* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /*EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + /* ch32v00x_iwdg.h -----------------------------------------------------------*/ /* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) /* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) /* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + /* ch32v00x_misc.h -----------------------------------------------------------*/ /* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) /* ch32v00x_opa.h ------------------------------------------------------------*/ /* Editor's note: I don't know if this is actually useful */ #ifndef __ASSEMBLER__ - /* OPA PSEL enumeration */ - typedef enum - { - CHP0 = 0, - CHP1 - } OPA_PSEL_TypeDef; - /* OPA NSEL enumeration */ - typedef enum - { - CHN0 = 0, - CHN1 - } OPA_NSEL_TypeDef; +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; - /* OPA Init Structure definition */ - typedef struct - { - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ - } OPA_InitTypeDef; +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; - /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ - typedef struct - { - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; - } PFIC_Type; + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ +} OPA_InitTypeDef; + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; /* Interrupt Enable Status Register x */ + __I uint32_t IPR[8]; /* Interrupt Pending Status Register x */ + __IO uint32_t ITHRESDR; /* Interrupt Priority Threshold Configuration Register */ + __IO uint32_t RESERVED; + __IO uint32_t CFGR; /* Interrupt Configuration Register */ + __I uint32_t GISR; /* Interrupt Global Status Register */ + __IO uint8_t VTFIDR[4]; /* VTF ID Configuration Regsite */ + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; /* VTF x Offset register */ + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; /* Interrupt Enable Setting Register x */ + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; /* Interrupt Enable Clear Register x */ + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; /* Interrupt Pending Status Register x */ + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; /* Interrupt Pending Clear Register x */ + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; /* Interrupt Activation Status Register x */ + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; /* Interrupt Priority Configuration Register */ + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; /* System Control Register */ +}PFIC_Type; #endif - /* ch32v00x_pwr.h ------------------------------------------------------------*/ +/* ch32v00x_pwr.h ------------------------------------------------------------*/ - /* PVD_detection_level */ -#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) -#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) -#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) -#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) -#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) +/* PVD_detection_level */ + +#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) +#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) +#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) /* PWR_AWU_Prescaler */ -#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) -#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) -#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) -#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) -#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) -#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) -#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) -#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) -#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) -#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) -#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) -#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) -#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) -#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) -#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) +#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) +#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) +#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) +#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) +#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) +#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) +#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) +#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) +#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) +#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) /* STOP_mode_entry */ -#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) -#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) /* PWR_Flag */ -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + /* ch32v00x_rcc.h ------------------------------------------------------------*/ + /* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + /* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) +#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) + /* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + /* AHB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) -#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) -#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) -#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) -#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) -#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + /* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + /* ADC_clock_source */ -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) -#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) -#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) -#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) -#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) -#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) -#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) -#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) +#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) +#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) +#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) +#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) +#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) +#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) +#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) + + /* AHB_peripheral */ -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) /* APB2_peripheral */ -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) /* APB1_peripheral */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + + /* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK ((uint8_t)0x07) +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + /* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + /* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + + + + + + /* ch32v00x_spi.h ------------------------------------------------------------*/ + /* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) /* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ -#define SPI_Mode_Slave ((uint16_t)0x0000) +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) /* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) /* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) /* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) /* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) /* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) /* SPI_MSB transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + /* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) /* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) /* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) /* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) /* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) /* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + /* ch32v00x_tim.h ------------------------------------------------------------*/ /* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) /* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) /* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) /* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) /* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) /* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) /* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) /* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) /* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) /* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) /* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) /* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) /* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) /* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) /* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) /* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) /* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) /* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) /* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) /* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) /* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ /* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ /* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) /* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) /* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) /* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) /* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) /* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) /* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) /* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) /* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) /* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) /* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) /* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) /* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ /* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) /* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) /* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) /* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) /* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) /* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) /* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) /* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + /* ch32v00x_usart.h ----------------------------------------------------------*/ /* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) /* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) /* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) /* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) /* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) /* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) /* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) /* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) /* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) /* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) -#define USART_IT_ORE USART_IT_ORE_ER +#define USART_IT_ORE USART_IT_ORE_ER /* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) /* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) /* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) /* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) /* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) // While not truly CH32X035, we can re-use some of the USB register defs. /* ch32v30x_usb.h ------------------------------------------------------------*/ + /* ch32v00x_wwdg.h -----------------------------------------------------------*/ + /* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) #ifdef __cplusplus }; #endif + // For debug writing to the debug interface. #ifndef MINICHLINK -#define DMDATA0 ((volatile uint32_t *)0xe00000f4) -#define DMDATA1 ((volatile uint32_t *)0xe00000f8) -#define DMSTATUS_SENTINEL ((volatile uint32_t *)0xe00000fc) // Reads as 0x00000000 if debugger is attached. + #define DMDATA0 ((volatile uint32_t*)0xe00000f4) + #define DMDATA1 ((volatile uint32_t*)0xe00000f8) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe00000fc) // Reads as 0x00000000 if debugger is attached. #endif // Determination of PLL multiplication factor for non-V003 chips + + // xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering. /* Encoder for some of the proprietary 'XW' RISC-V instructions present on the QingKe RV32 processor. Examples: - XW_C_LBU(a3, a1, 27); // c.xw.lbu a3, 27(a1) - XW_C_SB(a0, s0, 13); // c.xw.sb a0, 13(s0) + XW_C_LBU(a3, a1, 27); // c.xw.lbu a3, 27(a1) + XW_C_SB(a0, s0, 13); // c.xw.sb a0, 13(s0) - XW_C_LHU(a5, a5, 38); // c.xw.lhu a5, 38(a5) - XW_C_SH(a2, s1, 14); // c.xw.sh a2, 14(s1) + XW_C_LHU(a5, a5, 38); // c.xw.lhu a5, 38(a5) + XW_C_SH(a2, s1, 14); // c.xw.sh a2, 14(s1) */ // Let us do some compile-time error checking. -#define ASM_ASSERT(COND) \ - .if (!(COND)); \ - .err; \ - .endif +#define ASM_ASSERT(COND) .if (!(COND)); .err; .endif // Integer encodings of the possible compressed registers. #define C_s0 0 @@ -4585,29 +4363,26 @@ Examples: #define C_a5 7 // register to encoding -#define REG2I(X) (C_##X) +#define REG2I(X) (C_ ## X) // XW opcodes #define XW_OP_LBUSP 0b1000000000000000 -#define XW_OP_STSP 0b1000000001000000 +#define XW_OP_STSP 0b1000000001000000 #define XW_OP_LHUSP 0b1000000000100000 -#define XW_OP_SHSP 0b1000000001100000 +#define XW_OP_SHSP 0b1000000001100000 -#define XW_OP_LBU 0b0010000000000000 -#define XW_OP_SB 0b1010000000000000 +#define XW_OP_LBU 0b0010000000000000 +#define XW_OP_SB 0b1010000000000000 -#define XW_OP_LHU 0b0010000000000010 -#define XW_OP_SH 0b1010000000000010 +#define XW_OP_LHU 0b0010000000000010 +#define XW_OP_SH 0b1010000000000010 // The two different XW encodings supported at the moment. -#define XW_ENCODE1(OP, R1, R2, IMM) \ - ASM_ASSERT((IMM) >= 0 && (IMM) < 32); \ - .2byte((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ - (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3))) +#define XW_ENCODE1(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ + (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3))) -#define XW_ENCODE2(OP, R1, R2, IMM) \ - ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ +#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ (((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2)) // Compressed load byte, zero-extend result @@ -4617,30 +4392,33 @@ Examples: #define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM) // Compressed load half, zero-extend result -#define XW_C_LHU(RD, RS, IMM) \ - ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1))) +#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1))) // Compressed store half -#define XW_C_SH(RS1, RS2, IMM) \ - ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1))) +#define XW_C_SH(RS1, RS2, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1))) + + // Applies to all processors + /* some bit definitions for systick regs */ -#define SYSTICK_SR_CNTIF (1 << 0) -#define SYSTICK_CTLR_STE (1 << 0) -#define SYSTICK_CTLR_STIE (1 << 1) -#define SYSTICK_CTLR_STCLK (1 << 2) -#define SYSTICK_CTLR_STRE (1 << 3) -#define SYSTICK_CTLR_SWIE (1 << 31) +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) -#define PFIC ((PFIC_Type *)PFIC_BASE) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) -#define SysTick ((SysTick_Type *)SysTick_BASE) #define PA1 1 #define PA2 2 @@ -4664,8 +4442,8 @@ Examples: /* * This file contains various parts of the official WCH EVT Headers which * were originally under a restrictive license. - * - * The collection of this file was generated by + * + * The collection of this file was generated by * cnlohr, 2023-02-18 and * AlexanderMandera, 2023-06-23 * It was significantly reworked into several files cnlohr, 2025-01-29 @@ -4677,17 +4455,17 @@ Examples: * These copies of the headers from WCH are available now under: * * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the “Softwareâ€), to * deal in the Software without restriction, including without limitation the * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE diff --git a/inc/ch32v10xhw.h b/inc/ch32v10xhw.h new file mode 100644 index 0000000..103a60b --- /dev/null +++ b/inc/ch32v10xhw.h @@ -0,0 +1,6237 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + USBFS_IRQn = 59, /* USBHD global Interrupt */ +} IRQn_Type; + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS "\n\ + .balign 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0 \n\ + j NMI_Handler /* NMI */ \n\ + j HardFault_Handler /* Hard Fault */ \n\ + .word 0 \n\ + .word 0 \n\ + .word 0 \n\ + .word 0 \n\ + .word 0 \n\ + .word 0 \n\ + .word 0 \n\ + .word 0 \n\ + j SysTick_Handler /* SysTick Handler */ \n \ + .word 0 \n \ + j SW_Handler /* SW Handler */ \n \ + .word 0 \n \ + j WWDG_IRQHandler /* Window Watchdog */ \n \ + j PVD_IRQHandler /* PVD through EXTI Line detect */ \n \ + j TAMPER_IRQHandler /* TAMPER */ \n \ + j RTC_IRQHandler /* RTC */ \n \ + j FLASH_IRQHandler /* Flash */ \n \ + j RCC_IRQHandler /* RCC */ \n \ + j EXTI0_IRQHandler /* EXTI Line 0 */ \n \ + j EXTI1_IRQHandler /* EXTI Line 1 */ \n \ + j EXTI2_IRQHandler /* EXTI Line 2 */ \n \ + j EXTI3_IRQHandler /* EXTI Line 3 */ \n \ + j EXTI4_IRQHandler /* EXTI Line 4 */ \n \ + j DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n \ + j DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n \ + j DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n \ + j DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n \ + j DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n \ + j DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n \ + j DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n \ + j ADC1_2_IRQHandler /* ADC1_2 */ \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + j EXTI9_5_IRQHandler /* EXTI Line 9..5 */ \n \ + j TIM1_BRK_IRQHandler /* TIM1 Break */ \n \ + j TIM1_UP_IRQHandler /* TIM1 Update */ \n \ + j TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n \ + j TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n \ + j TIM2_IRQHandler /* TIM2 */ \n \ + j TIM3_IRQHandler /* TIM3 */ \n \ + j TIM4_IRQHandler /* TIM4 */ \n \ + j I2C1_EV_IRQHandler /* I2C1 Event */ \n \ + j I2C1_ER_IRQHandler /* I2C1 Error */ \n \ + j I2C2_EV_IRQHandler /* I2C2 Event */ \n \ + j I2C2_ER_IRQHandler /* I2C2 Error */ \n \ + j SPI1_IRQHandler /* SPI1 */ \n \ + j SPI2_IRQHandler /* SPI2 */ \n \ + j USART1_IRQHandler /* USART1 */ \n \ + j USART2_IRQHandler /* USART2 */ \n \ + j USART3_IRQHandler /* USART3 */ \n \ + j EXTI15_10_IRQHandler /* EXTI Line 15..10 */ \n \ + j RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n \ + j USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ \n \ + j USBFS_IRQHandler /* USBFS */ \n \ + .option pop;\n" + +/* memory mapped structure for SysTick */ + +typedef struct __attribute__((packed)) +{ + __IO uint32_t CTLR; + union + { + struct + { + __IO uint8_t CNT0; + __IO uint8_t CNT1; + __IO uint8_t CNT2; + __IO uint8_t CNT3; + __IO uint8_t CNT4; + __IO uint8_t CNT5; + __IO uint8_t CNT6; + __IO uint8_t CNT7; + __IO uint8_t CMP0; + __IO uint8_t CMP1; + __IO uint8_t CMP2; + __IO uint8_t CMP3; + __IO uint8_t CMP4; + __IO uint8_t CMP5; + __IO uint8_t CMP6; + __IO uint8_t CMP7; + }; + struct + { + __IO uint32_t CNTL; + __IO uint32_t CNTH; + __IO uint32_t CMPL; + __IO uint32_t CMPH; + }; + struct + { + __IO uint64_t CNT; + __IO uint64_t CMP; + }; + }; +} SysTick_Type; + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + #define ADC1_2_IRQn ADC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + uint32_t RESERVED0[86]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +typedef struct +{ + __IO uint16_t CAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UID0; + __IO uint32_t UID1; + __IO uint32_t UID2; + __IO uint32_t RES3; +} ESG_TypeDef; + +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct + { + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; + + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ +typedef struct +{ + __IO uint32_t CTR; +} EXTEND_TypeDef; + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ + +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define DBGMCU_BASE ((uint32_t)0xE000D000) + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) + +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + + + + + + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define TIM12 ((TIM_TypeDef *)TIM12_BASE) +#define TIM13 ((TIM_TypeDef *)TIM13_BASE) +#define TIM14 ((TIM_TypeDef *)TIM14_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESG_TypeDef *)ESIG_BASE) +// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + + + +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +#define FLASH_ACTLR_HLFCYA ((uint8_t)0x08) /* Flash Half Cycle Access Enable */ +#define FLASH_ACTLR_PRFTBE ((uint8_t)0x10) /* Prefetch Buffer Enable */ +#define FLASH_ACTLR_PRFTBS ((uint8_t)0x20) /* Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG (0x0001) /* Programming */ +#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT (0x0040) /* Start */ +#define FLASH_CTLR_LOCK (0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_PAGE_PG (0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER (0x00020000) /* Page Erase 128Byte */ +#define FLASH_CTLR_BUF_LOAD (0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST (0x00080000) /* Buffer Reset */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00200000) /* USART1 remapping higher bit */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 /* legacy compatibility */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP2 ((uint32_t)0x00000080) /* Partial remap (ETR/PD4, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CN2N/PA2, CH3N/PD1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ +#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ +#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ +#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ +#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ +#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ +#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ +#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ + + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_CFGR2 register *******************/ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint32_t)0x1000) +#define RCC_USBFS ((uint32_t)0x1000) +#define RCC_USBPD ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/****************** Bit definition for RCC_AHBRSTR register *****************/ + + + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register *****************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_USBFS_IO_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_USB_5V_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ +#define EXTEN_USBHD_IO_EN EXTEN_USBFS_IO_EN + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + + +#define EXTEN_IDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ +#define EXTEN_WRITE_EN ((uint32_t)0x00004000) /* Bit 14 */ +#define EXTEN_SHORT_WAKE ((uint32_t)0x00008000) /* Bit 15 */ + +#define EXTEN_FLASH_CLK_TRIM ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */ +#define EXTEN_FLASH_CLK_TRIM0 ((uint32_t)0x00010000) /* Bit 0 */ +#define EXTEN_FLASH_CLK_TRIM1 ((uint32_t)0x00020000) /* Bit 1 */ +#define EXTEN_FLASH_CLK_TRIM2 ((uint32_t)0x00040000) /* Bit 2 */ + + + + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* ch32v00x_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32v00x_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +///* CTLR1 register Mask */ +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/* ch32v20x_bkp.c ------------------------------------------------------------*/ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + + + + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32v00x_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) +#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9)) +#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10)) +#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11)) + +/* DMA2 FLAG mask */ +// Editor's note: Overloaded Definition. +#define DMA2_FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32v00x_flash.c ----------------------------------------------------------*/ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) + +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_PGERR ((uint32_t)0x00000004) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x10000) + + +/* ch32v00x_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +////* I2C registers Masks */ +// Editor's note: Overloaded Definition. +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +//Editor's Note: Overloaded Definition +#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + + +/* ch32v00x_pwr.c ------------------------------------------------------------*/ + + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* ch32v00x_rcc.c ------------------------------------------------------------*/ + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + + +/* RCC Flag Mask */ +//Editor's Note: Overloaded Definition +#define RCC_FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +#ifndef __ASSEMBLER__ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; +#endif + + +/* ch32v20x_rtc.c ------------------------------------------------------------*/ + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32v00x_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + + +/* ch32v00x_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_external_trigger_sources_delay_channels_definition */ +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) + +/* ch32v20x_bkp.h ------------------------------------------------------------*/ + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + + + +/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ + +/* CFGR0 Register */ +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000004) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000008) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00000040) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00000080) + +/* CFGR1 Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) + +/* ch32v00x_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ + +#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x00040000) +#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 Connected to the USBFS Wakeup event */ + +/* ch32v00x_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; +#endif + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Half_Cycle_Enable_Disable */ +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ + +/* Prefetch_Buffer_Enable_Disable */ +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ + + +/* Values to be used with CH32V10x Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with CH32V10x Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */ + +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + + + + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ + +/* GPIO_Remap_define */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ + to TIM2 Internal Trigger 1 for calibration \ + (only for Connectivity line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */ +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \ + only for High density Value line devices) */ +#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1 + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + + +/* ch32v00x_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +/* ch32v00x_misc.h -----------------------------------------------------------*/ + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1, +} OPA_PSEL_TypeDef; + + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1, +} OPA_NSEL_TypeDef; + + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ +} OPA_InitTypeDef; + + +/* PVD_detection_level */ +#define PWR_PVDLevel_2V7 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V9 ((uint32_t)0x00000020) +#define PWR_PVDLevel_3V1 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3V3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_3V5 ((uint32_t)0x00000080) +#define PWR_PVDLevel_3V8 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + + +/* ch32v00x_rcc.h ------------------------------------------------------------*/ + + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + + + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) + +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) + +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + + +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + +#define RCC_AHBPeriph_USBHD ((uint32_t)0x00001000) + + +#define RCC_AHBPeriph_USBFS RCC_AHBPeriph_USBHD + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + + +/* ch32v00x_rtc.h ------------------------------------------------------------*/ +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +// While not truly CH32X035, we can re-use some of the USB register defs. +/* ch32v10x_usb.h ------------------------------------------------------------*/ + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef VOID + #define VOID void +#endif +#ifndef CONST + #define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* USB */ +#define R32_USB_CONTROL (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address +#define R8_USB_CTRL (*((PUINT8V)(0x40023400))) // USB base control +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define R8_UDEV_CTRL (*((PUINT8V)(0x40023401))) // USB device physical prot control +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define R8_USB_INT_EN (*((PUINT8V)(0x40023402))) // USB interrupt enable +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define R8_USB_DEV_AD (*((PUINT8V)(0x40023403))) // USB device address +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define R32_USB_STATUS (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status +#define R8_USB_MIS_ST (*((PUINT8V)(0x40023405))) // USB miscellaneous status +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define R8_USB_INT_FG (*((PUINT8V)(0x40023406))) // USB interrupt flag +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define R8_USB_INT_ST (*((PUINT8V)(0x40023407))) // USB interrupt status +#define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R16_USB_RX_LEN (*((PUINT16V)(0x40023408))) // USB receiving length +#define MASK_UIS_RX_LEN 0x3FF // RO, bit mask of current receive length(10 bits for ch32v10x) +#define R32_USB_BUF_MODE (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode +#define R8_UEP4_1_MOD (*((PUINT8V)(0x4002340c))) // endpoint 4/1 mode +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +#define R8_UEP2_3_MOD (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#define R8_UEP5_6_MOD (*((PUINT8V)(0x4002340e))) // endpoint 5/6 mode +#define RB_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define RB_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define RB_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +#define R8_UEP7_MOD (*((PUINT8V)(0x4002340f))) // endpoint 7 mode +#define RB_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +#define R16_UEP0_DMA (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address +#define R16_UEP1_DMA (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address +#define R16_UEP2_DMA (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address +#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address +#define R16_UEP3_DMA (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address + +#define R16_UEP4_DMA (*((PUINT16V)(0x40023420))) // endpoint 4 DMA buffer address +#define R16_UEP5_DMA (*((PUINT16V)(0x40023424))) // endpoint 5 DMA buffer address +#define R16_UEP6_DMA (*((PUINT16V)(0x40023428))) // endpoint 6 DMA buffer address +#define R16_UEP7_DMA (*((PUINT16V)(0x4002342c))) // endpoint 7 DMA buffer address + +#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address +#define R32_USB_EP0_CTRL (*((PUINT32V)(0x40023430))) // endpoint 0 control & transmittal length +#define R8_UEP0_T_LEN (*((PUINT8V)(0x40023430))) // endpoint 0 transmittal length +#define R8_UEP0_CTRL (*((PUINT8V)(0x40023432))) // endpoint 0 control +#define R32_USB_EP1_CTRL (*((PUINT32V)(0x40023434))) // endpoint 1 control & transmittal length +#define R16_UEP1_T_LEN (*((PUINT16V)(0x40023434))) // endpoint 1 transmittal length(16-bits for ch32v10x) +#define R8_UEP1_CTRL (*((PUINT8V)(0x40023436))) // endpoint 1 control +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R32_USB_EP2_CTRL (*((PUINT32V)(0x40023438))) // endpoint 2 control & transmittal length +#define R16_UEP2_T_LEN (*((PUINT16V)(0x40023438))) // endpoint 2 transmittal length(16-bits for ch32v10x) +#define R8_UEP2_CTRL (*((PUINT8V)(0x4002343a))) // endpoint 2 control + +#define R8_UH_EP_PID (*((PUINT8V)(0x40023438))) // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R32_USB_EP3_CTRL (*((PUINT32V)(0x4002343c))) // endpoint 3 control & transmittal length +#define R16_UEP3_T_LEN (*((PUINT16V)(0x4002343c))) // endpoint 3 transmittal length(16-bits for ch32v10x) +#define R8_UEP3_CTRL (*((PUINT8V)(0x4002343e))) // endpoint 3 control +#define R8_UH_TX_LEN (*((PUINT16V)(0x4002343c))) //R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R32_USB_EP4_CTRL (*((PUINT32V)(0x40023440))) // endpoint 4 control & transmittal length +#define R16_UEP4_T_LEN (*((PUINT16V)(0x40023440))) // endpoint 4 transmittal length(16-bits for ch32v10x) +#define R8_UEP4_CTRL (*((PUINT8V)(0x40023442))) // endpoint 4 control + +#define R32_USB_EP5_CTRL (*((PUINT32V)(0x40023444))) // endpoint 5 control & transmittal length +#define R16_UEP5_T_LEN (*((PUINT16V)(0x40023444))) // endpoint 5 transmittal length(16-bits for ch32v10x) +#define R8_UEP5_CTRL (*((PUINT8V)(0x40023446))) // endpoint 5 control + +#define R32_USB_EP6_CTRL (*((PUINT32V)(0x40023448))) // endpoint 6 control & transmittal length +#define R16_UEP6_T_LEN (*((PUINT16V)(0x40023448))) // endpoint 6 transmittal length(16-bits for ch32v10x) +#define R8_UEP6_CTRL (*((PUINT8V)(0x4002344a))) // endpoint 6 control + +#define R32_USB_EP7_CTRL (*((PUINT32V)(0x4002344c))) // endpoint 7 control & transmittal length +#define R16_UEP7_T_LEN (*((PUINT16V)(0x4002344c))) // endpoint 7 transmittal length(16-bits for ch32v10x) +#define R8_UEP7_CTRL (*((PUINT8V)(0x4002344e))) // endpoint 7 control + +/* ch32v10x_usb_host.h -----------------------------------------------------------*/ + +#define ERR_SUCCESS 0x00 +#define ERR_USB_CONNECT 0x15 +#define ERR_USB_DISCON 0x16 +#define ERR_USB_BUF_OVER 0x17 +#define ERR_USB_DISK_ERR 0x1F +#define ERR_USB_TRANSFER 0x20 +#define ERR_USB_UNSUPPORT 0xFB +#define ERR_USB_UNKNOWN 0xFE +#define ERR_AOA_PROTOCOL 0x41 + +#define ROOT_DEV_DISCONNECT 0 +#define ROOT_DEV_CONNECTED 1 +#define ROOT_DEV_FAILED 2 +#define ROOT_DEV_SUCCESS 3 +#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20) +#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30) +#define DEF_AOA_DEVICE 0xF0 +#define DEV_TYPE_UNKNOW 0xFF + +#define HUB_MAX_PORTS 4 +#define WAIT_USB_TOUT_200US 3000 + + +/* ch32v30x_usb.h ------------------------------------------------------------*/ + + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. + #define DMDATA0 ((volatile uint32_t*)0xe0000380) + #define DMDATA1 ((volatile uint32_t*)0xe0000384) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000388)// Reads as 0x00000000 if debugger is attached. + +// Determination of PLL multiplication factor for non-V003 chips + #if !defined(FUNCONF_SYSTEM_CORE_CLOCK) + #define PLL_MULTIPLICATION ((uint32_t)0) + #else + #if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x_D8) + #if FUNCONF_PLL_MULTIPLIER == 2 + #define PLL_MULTIPLICATION RCC_PLLMULL2 + #elif FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3 + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4 + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5 + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6 + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7 + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8 + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9 + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10 + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11 + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12 + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13 + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14 + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15 + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16 + #elif defined(CH32V20x) && FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18 + #else + #error "Invalid PLL multiplier" + #endif + #else + #if FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18_EXTEN + #else + #error "Invalid PLL multiplier" + #endif + #endif + #endif + + + + +// Applies to all processors + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA1 1 +#define PA2 2 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +#define PA0 0 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/ch32v20xhw.h b/inc/ch32v20xhw.h new file mode 100644 index 0000000..df2dacd --- /dev/null +++ b/inc/ch32v20xhw.h @@ -0,0 +1,8450 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + USBHD_IRQn = 59, /* USBHD global Interrupt */ + USBHDWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */ + +#ifdef CH32V20x_D6 + UART4_IRQn = 61, /* UART4 global Interrupt */ + DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ + +#elif defined(CH32V20x_D8) + ETH_IRQn = 61, /* ETH global Interrupt */ + ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ + TIM5_IRQn = 65, /* TIM5 global Interrupt */ + UART4_IRQn = 66, /* UART4 global Interrupt */ + DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ + OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ + OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ + +#elif defined(CH32V20x_D8W) + ETH_IRQn = 61, /* ETH global Interrupt */ + ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ + BB_IRQn = 63, /* BLE BB global Interrupt */ + LLE_IRQn = 64, /* BLE LLE global Interrupt */ + TIM5_IRQn = 65, /* TIM5 global Interrupt */ + UART4_IRQn = 66, /* UART4 global Interrupt */ + DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ + OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ + OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ +#endif +} IRQn_Type; + +#define BASE_VECTOR "\n\ + .balign 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0 \n\ + .word NMI_Handler /* NMI */ \n\ + .word HardFault_Handler /* Hard Fault */ \n\ + .word 0 \n\ + .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\ + .word 0 \n\ + .word 0 \n\ + .word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\ + .word Break_Point_Handler /* Break Point */ \n\ + .word 0 \n\ + .word 0 \n\ + .word SysTick_Handler /* SysTick */ \n \ + .word 0 \n \ + .word SW_Handler /* SW */ \n \ + .word 0 \n \ + /* External Interrupts */ \n \ + .word WWDG_IRQHandler /* Window Watchdog */ \n \ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n \ + .word TAMPER_IRQHandler /* TAMPER */ \n \ + .word RTC_IRQHandler /* RTC */ \n \ + .word FLASH_IRQHandler /* Flash */ \n \ + .word RCC_IRQHandler /* RCC */ \n \ + .word EXTI0_IRQHandler /* EXTI Line 0 */ \n \ + .word EXTI1_IRQHandler /* EXTI Line 1 */ \n \ + .word EXTI2_IRQHandler /* EXTI Line 2 */ \n \ + .word EXTI3_IRQHandler /* EXTI Line 3 */ \n \ + .word EXTI4_IRQHandler /* EXTI Line 4 */ \n \ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n \ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n \ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n \ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n \ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n \ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n \ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n \ + .word ADC1_2_IRQHandler /* ADC1_2 */ \n \ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ \n \ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ \n \ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \n \ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n \ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ \n \ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n \ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n \ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n \ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n \ + .word TIM2_IRQHandler /* TIM2 */ \n \ + .word TIM3_IRQHandler /* TIM3 */ \n \ + .word TIM4_IRQHandler /* TIM4 */ \n \ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n \ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n \ + .word I2C2_EV_IRQHandler /* I2C2 Event */ \n \ + .word I2C2_ER_IRQHandler /* I2C2 Error */ \n \ + .word SPI1_IRQHandler /* SPI1 */ \n \ + .word SPI2_IRQHandler /* SPI2 */ \n \ + .word USART1_IRQHandler /* USART1 */ \n \ + .word USART2_IRQHandler /* USART2 */ \n \ + .word USART3_IRQHandler /* USART3 */ \n \ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ \n \ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n \ + .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ \n \ + .word USBFS_IRQHandler /* USBFS Break */ \n \ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ \n" + +#if defined(CH32V20x_D6) //CH32V20x variants +#define EXTRA_VECTOR "\n\ + .word UART4_IRQHandler /* UART4 */ \n \ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ \n" +#elif defined(CH32V20x_D8) +#define EXTRA_VECTOR "\n\ + .word ETH_IRQHandler /* ETH global */ \n\ + .word ETHWakeUp_IRQHandler /* ETH Wake up */ \n\ + .word 0 \n\ + .word 0 \n\ + .word TIM5_IRQHandler /* TIM5 */ \n\ + .word UART4_IRQHandler /* UART4 */ \n\ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ \n\ + .word OSC32KCal_IRQHandler /* OSC32KCal */ \n\ + .word OSCWakeUp_IRQHandler /* OSC Wake Up */ \n" +#elif defined(CH32V20x_D8W) +#define EXTRA_VECTOR "\n\ + .word ETH_IRQHandler /* ETH global */ \n\ + .word ETHWakeUp_IRQHandler /* ETH Wake up */ \n\ + .word BB_IRQHandler /* BLE BB */ \n\ + .word LLE_IRQHandler /* BLE LLE */ \n\ + .word TIM5_IRQHandler /* TIM5 */ \n\ + .word UART4_IRQHandler /* UART4 */ \n\ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ \n\ + .word OSC32KCal_IRQHandler /* OSC32KCal */ \n\ + .word OSCWakeUp_IRQHandler /* OSC Wake Up */ \n" +#endif //CH32V20x variants + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR EXTRA_VECTOR "\n.option pop;\n" + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + #define ADC1_2_IRQn ADC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t DLYR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + uint32_t RESERVED0[86]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +typedef struct +{ + __IO uint16_t CAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UID0; + __IO uint32_t UID1; + __IO uint32_t UID2; + __IO uint32_t RES3; +} ESG_TypeDef; + +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct + { + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; + + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ +typedef struct +{ + __IO uint32_t CTR; +} EXTEND_TypeDef; + + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + + +/* USBD Full-Speed Device, Chapter 21. + NOTE: USBD and CAN controller share a dedicated 512-byte SRAM area for data + transmission and reception in the design, so when using USBD and CAN functions + at the same time, this shared area needs to be allocated reasonably to prevent + data conflicts. */ + +typedef struct +{ + __IO uint32_t ADDn_TX; + __IO uint32_t COUNTn_TX; + __IO uint32_t ADDn_RX; + __IO uint32_t COUNTn_RX; +} USBD_BTABLE_TypeDef; + +typedef struct +{ + __IO uint32_t EPR[8]; + __IO uint32_t RESERVED[8]; + __IO uint32_t CNTR; + __IO uint32_t ISTR; + __IO uint32_t FNR; + __IO uint32_t DADDR; + __IO uint32_t BTABLE; +} USBD_TypeDef; + +#define CAN_USBD_SHARED_BASE ((PERIPH_BASE + 0x6000)) +#define USBD_BASE ((PERIPH_BASE + 0x5C00)) + +/* USBD_CNTR */ +#define USBD_CTRM (1<<15) +#define USBD_PMAOVRM (1<<14) +#define USBD_ERRM (1<<13) +#define USBD_WKUPM (1<<12) +#define USBD_SUSPM (1<<11) +#define USBD_RESETM (1<<10) +#define USBD_SOFM (1<<9) +#define USBD_ESOFM (1<<8) +#define USBD_RESUME (1<<4) +#define USBD_FSUP (1<<3) +#define USBD_LPMODE (1<<2) +#define USBD_PDWN (1<<1) +#define USBD_FRES (1<<0) + +/* USBD_ISTR */ +#define USBD_CTR (1<<15) +#define USBD_PMAOVR (1<<14) +#define USBD_ERR (1<<13) +#define USBD_WKUP (1<<12) +#define USBD_SUSP (1<<11) +#define USBD_RESET (1<<10) +#define USBD_SOF (1<<9) +#define USBD_ESOF (1<<8) +#define USBD_DIR (1<<4) +#define USBD_EP_ID (0xf) + +/* USBD_FNR */ +#define USBD_RXDP (1<<15) +#define USBD_RXDM (1<<14) +#define USBD_LCK (1<<13) +#define USBD_LSOF (3<<11) +#define USBD_FN (0x7ff) + +/* USBD_DADDR */ +#define USBD_EF (1<<7) +#define USBD_ADD (0x7f) + +/* USBD_EPRx */ +#define USBD_CTR_RX (1<<15) +#define USBD_DTOG_RX (1<<14) +#define USBD_STAT_RX (3<<12) +#define USBD_SETUP (1<<11) +#define USBD_EPTYPE (3<<9) +#define USBD_EPKIND (1<<8) +#define USBD_CTR_TX (1<<7) +#define USBD_DTOG_TX (1<<6) +#define USBD_STAT_TX (3<<4) +#define USBD_EA (0xf) + +/* USBD_COUNTx_RX */ +#define USBD_BLSIZE (1<<15) +#define USBD_NUM_BLOCK (0x1f<<10) +#define USBD_COUNTx_RX 0x2ff + + +#define USBD ((USBD_TypeDef *) USBD_BASE) + +/* USB-FS-OTG Registers, Chapter 23. */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTG_FS_TypeDef; + +/* R8_USB_CTRL */ +#define USBOTG_UC_HOST_MODE (1<<7) +#define USBOTG_UC_LOW_SPEED (1<<6) +#define USBOTG_UC_DEV_PU_EN (1<<5) +#define USBOTG_UC_SYS_CTRL (1<<4) +#define USBOTG_UC_INT_BUSY (1<<3) +#define USBOTG_UC_RESET_SIE (1<<2) +#define USBOTG_UC_CLR_ALL (1<<1) +#define USBOTG_UC_DMA_EN (1<<0) + +/* R8_USB_INT_EN */ +#define USBOTG_UIE_DEV_NAK (1<<6) +#define USBOTG_UIE_FIFO_OV (1<<4) +#define USBOTG_UIE_HST_SOF (1<<3) +#define USBOTG_UIE_SUSPEND (1<<2) +#define USBOTG_UIE_TRANSFER (1<<1) +#define USBOTG_UIE_DETECT (1<<0) +#define USBOTG_UIE_BUS_RST (1<<0) + +/* R8_USB_DEV_AD */ +#define USBOTG_UDA_GP_BIT (1<<7) +#define USBOTG_USB_ADDR (1<<6) + +/* R8_USB_MIS_ST */ +#define USBOTG_UMS_SOF_PRES (1<<7) +#define USBOTG_UMS_SOF_ACT (1<<6) +#define USBOTG_UMS_SIE_FREE (1<<5) +#define USBOTG_UMS_R_FIFO_RDY (1<<4) +#define USBOTG_UMS_BUS_RESET (1<<3) +#define USBOTG_UMS_SUSPEND (1<<2) +#define USBOTG_UMS_DM_LEVEL (1<<1) +#define USBOTG_UMS_DEV_ATTACH (1<<0) + +/* R8_USB_INT_FG */ +#define USBOTG_U_IS_NAK (1<<7) +#define USBOTG_U_TOG_OK (1<<6) +#define USBOTG_U_SIE_FREE (1<<5) +#define USBOTG_UIF_FIFO_OV (1<<4) +#define USBOTG_UIF_HST_SOF (1<<3) +#define USBOTG_UIF_SUSPEND (1<<2) +#define USBOTG_UIF_TRANSFER (1<<1) +#define USBOTG_UIF_DETECT (1<<0) +#define USBOTG_UIF_BUS_RST (1<<0) + +/* R8_USB_INT_ST */ +#define USBOTG_UIS_IS_NAK (1<<7) +#define USBOTG_UIS_TOG_OK (1<<6) +#define USBOTG_UIS_TOKEN (3<<4) +#define USBOTG_UIS_ENDP 0xf +#define USBOTG_UIS_H_RES 0xf + +/* R32_USB_OTG_CR */ +#define USBOTG_CR_SESS_VTH (1<<5) +#define USBOTG_CR_VBUS_VTH (1<<4) +#define USBOTG_CR_OTG_EN (1<<3) +#define USBOTG_CR_IDPU (1<<2) +#define USBOTG_CR_CHARGE_VBUS (1<<1) +#define USBOTG_CR_DISCHAR_VBUS (1<<0) + +/* R32_USB_OTG_SR */ +#define USBOTG_SR_ID_DIG (1<<3) +#define USBOTG_SR_SESS_END (1<<2) +#define USBOTG_SR_SESS_VLD (1<<1) +#define USBOTG_SR_VBUS_VLD (1<<0) + +/* R8_UEPn_TX_CTRL */ +#define USBOTG_UEP_T_AUTO_TOG (1<<3) +#define USBOTG_UEP_T_TOG (1<<2) +#define USBOTG_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBOTG_UEP_T_RES_ACK (0<<1) +#define USBOTG_UEP_T_RES_NONE (1<<0) +#define USBOTG_UEP_T_RES_NAK (1<<1) +#define USBOTG_UEP_T_RES_STALL (3<<0) + +#define USBOTG_UEP_R_AUTO_TOG (1<<3) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBOTG_UEP_R_TOG (1<<2) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBOTG_UEP_R_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBOTG_UEP_R_RES_ACK (0<<1) +#define USBOTG_UEP_R_RES_NONE (1<<0) +#define USBOTG_UEP_R_RES_NAK (1<<1) +#define USBOTG_UEP_R_RES_STALL (3<<0) + + + +/* R8_UEPn_ RX_CTRL */ +#define USBOTG_UEP_R_AUTO_TOG (1<<3) +#define USBOTG_UEP_R_TOG (1<<2) +#define USBOTG_UEP_R_RES (3<<0) + +/* R8_UEP7_MOD */ +#define USBOTG_UEP7_RX_EN (1<<3) +#define USBOTG_UEP7_TX_EN (1<<2) +#define USBOTG_UEP7_BUF_MOD (1<<0) + +/* R8_UEP5_6_MOD */ +#define USBOTG_UEP6_RX_EN (1<<7) +#define USBOTG_UEP6_TX_EN (1<<6) +#define USBOTG_UEP6_BUF_MOD (1<<4) +#define USBOTG_UEP5_RX_EN (1<<3) +#define USBOTG_UEP5_TX_EN (1<<2) +#define USBOTG_UEP5_BUF_MOD (1<<0) + +/* R8_UEP2_3_MOD */ +#define USBOTG_UEP3_RX_EN (1<<7) +#define USBOTG_UEP3_TX_EN (1<<6) +#define USBOTG_UEP3_BUF_MOD (1<<4) +#define USBOTG_UEP2_RX_EN (1<<3) +#define USBOTG_UEP2_TX_EN (1<<2) +#define USBOTG_UEP2_BUF_MOD (1<<0) + +/* R8_UEP4_1_MOD */ +#define USBOTG_UEP1_RX_EN (1<<7) +#define USBOTG_UEP1_TX_EN (1<<6) +#define USBOTG_UEP1_BUF_MOD (1<<4) +#define USBOTG_UEP4_RX_EN (1<<3) +#define USBOTG_UEP4_TX_EN (1<<2) +#define USBOTG_UEP4_BUF_MOD (1<<0) + +/* R8_UDEV_CTRL */ +#define USBOTG_UD_PD_DIS (1<<7) +#define USBOTG_UD_DP_PIN (1<<5) +#define USBOTG_UD_DM_PIN (1<<4) +#define USBOTG_UD_LOW_SPEED (1<<2) +#define USBOTG_UD_GP_BIT (1<<1) +#define USBOTG_UD_PORT_EN (1<<0) + + +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ +#define UEP_SIZE 64 + +#define DEF_UEP_IN 0x80 +#define DEF_UEP_OUT 0x00 +#define DEF_UEP_BUSY 0x01 +#define DEF_UEP_FREE 0x00 + +#define DEF_UEP0 0 +#define DEF_UEP1 1 +#define DEF_UEP2 2 +#define DEF_UEP3 3 +#define DEF_UEP4 4 +#define DEF_UEP5 5 +#define DEF_UEP6 6 +#define DEF_UEP7 7 +#define UNUM_EP 8 + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTG_FS_HOST_TypeDef; + +/* R8_UHOST_CTRL */ +#define USBOTG_UH_PD_DIS (1<<7) +#define USBOTG_UH_DP_PIN (1<<5) +#define USBOTG_UH_DM_PIN (1<<4) +#define USBOTG_UH_LOW_SPEED (1<<2) +#define USBOTG_UH_BUS_RESET (1<<1) +#define USBOTG_UH_PORT_EN (1<<0) + +/* R32_UH_EP_MOD */ +#define USBOTG_UH_EP_TX_EN (1<<6) +#define USBOTG_UH_EP_TBUF_MOD (1<<4) +#define USBOTG_UH_EP_RX_EN (1<<3) +#define USBOTG_UH_EP_RBUF_MOD (1<<0) + +/* R16_UH_SETUP */ +#define USBOTG_UH_PRE_PID_EN (1<<10) +#define USBOTG_UH_SOF_EN (1<<2) + +/* R8_UH_EP_PID */ +#define USBOTG_UH_TOKEN (0xf<<4) +#define USBOTG_UH_ENDP (0xf<<0) + +/* R8_UH_RX_CTRL */ +#define USBOTG_UH_R_AUTO_TOG (1<<3) +#define USBOTG_UH_R_TOG (1<<2) +#define USBOTG_UH_R_RES (1<<0) + +/* R8_UH_TX_CTRL */ +#define USBOTG_UH_T_AUTO_TOG (1<<3) +#define USBOTG_UH_T_TOG (1<<2) +#define USBOTG_UH_T_RES (1<<0) + + + + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/* ETH10M Registers */ +typedef struct +{ + __IO uint8_t reserved1; + __IO uint8_t reserved2; + __IO uint8_t reserved3; + __IO uint8_t EIE; + + __IO uint8_t EIR; + __IO uint8_t ESTAT; + __IO uint8_t ECON2; + __IO uint8_t ECON1; + + __IO uint16_t ETXST; + __IO uint16_t ETXLN; + + __IO uint16_t ERXST; + __IO uint16_t ERXLN; + + __IO uint32_t HTL; + __IO uint32_t HTH; + + __IO uint8_t ERXFCON; + __IO uint8_t MACON1; + __IO uint8_t MACON2; + __IO uint8_t MABBIPG; + + __IO uint16_t EPAUS; + __IO uint16_t MAMXFL; + + __IO uint16_t MIRD; + __IO uint16_t reserved4; + + __IO uint8_t MIERGADR; + __IO uint8_t MISTAT; + __IO uint16_t MIWR; + + __IO uint32_t MAADRL; + + __IO uint16_t MAADRH; + __IO uint16_t reserved5; +} ETH10M_TypeDef; +#endif + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/* OSC Registers */ +typedef struct +{ + __IO uint32_t HSE_CAL_CTRL; + __IO uint32_t Reserve0; + __IO uint16_t Reserve1; + __IO uint16_t LSI32K_TUNE; + __IO uint32_t Reserve2; + __IO uint32_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint8_t Reserve6; + __IO uint8_t LSI32K_CAL_CFG; + __IO uint16_t Reserve7; + __IO uint16_t LSI32K_CAL_STATR; + __IO uint8_t LSI32K_CAL_OV_CNT; + __IO uint8_t LSI32K_CAL_CTRL; +} OSC_TypeDef; + +#endif + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif // !__ASSEMBLER__ + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ + +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define ETH10M_BASE (AHBPERIPH_BASE + 0x8000) + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) + +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define OSC_BASE (AHBPERIPH_BASE + 0x202C) +#endif + + + + + + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) +#define USBOTG_H_FS ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define ETH10M ((ETH10M_TypeDef *)ETH10M_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESG_TypeDef *)ESIG_BASE) +// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define OSC ((OSC_TypeDef *)OSC_BASE) +#endif + + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0xFFFFFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0xFFFFFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0xFFFFFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0xFFFFFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0xFFFFFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG (0x0001) /* Programming */ +#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT (0x0040) /* Start */ +#define FLASH_CTLR_LOCK (0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK (0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG (0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER (0x00020000) /* Page Erase 64Byte */ +#define FLASH_CTLR_PAGE_BER32 (0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PAGE_BER64 (0x00080000) /* Block Erase 64K */ +#define FLASH_CTLR_PG_STRT (0x00200000) /* Page Programming Start */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00200000) /* USART1 remapping higher bit */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 /* legacy compatibility */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP2 ((uint32_t)0x00000080) /* Partial remap (ETR/PD4, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CN2N/PA2, CH3N/PD1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ +#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ +#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ +#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ +#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ +#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ +#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ +#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + + +#define RCC_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits (USB prescaler) */ +#define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ +#define RCC_USBPRE_DIV1 ((uint32_t)0x00000000) /* PLL clock not divided (PLLCLK = 48MHz) */ +#define RCC_USBPRE_DIV2 ((uint32_t)0x00400000) /* PLL clock divided by 2 (PLLCLK = 96MHz) */ +#define RCC_USBPRE_DIV3 ((uint32_t)0x00800000) /* PLL clock divided by 3 (PLLCLK = 144MHz) */ +#define RCC_USBPRE_DIV5 ((uint32_t)0x00C00000) /* PLL clock divided by 5, PLL source is HSE/2 (PLLCLK = 240MHz) */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define RCC_MCO_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_ADCDUTY ((uint32_t)0x80000000) /* ADC clock duty cycle adjustment */ +#define RCC_ADC_DUTY_SEL ((uint32_t)0x40000000) /* ADC clock duty cycle selection */ +#define RCC_ETHPRE ((uint32_t)0x10000000) /* Ethernet clock prescaler */ + +/******************* Bit definition for RCC_CFGR2 register *******************/ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint32_t)0x1000) +#define RCC_USBFS ((uint32_t)0x1000) +#define RCC_USBPD ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/****************** Bit definition for RCC_AHBRSTR register *****************/ + + + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 (only on parts with RGMII) */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ + + + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + +/******************************************************************************/ +/* ETH10M */ +/******************************************************************************/ +/* ETH register */ +#define R8_ETH_EIE (*((volatile uint8_t *)(0x40028000+3))) /* Interrupt Enable Register */ +#define RB_ETH_EIE_INTIE 0x80 /* RW interrupt enable*/ +#define RB_ETH_EIE_RXIE 0x40 /* RW Receive complete interrupt enable */ +#define RB_ETH_EIE_LINKIE 0x10 /* RW Link Change Interrupt Enable */ +#define RB_ETH_EIE_TXIE 0x08 /* RW send complete interrupt enable */ +#define RB_ETH_EIE_R_EN50 0x04 /* RW TX 50�� resistor adjustment. 1: On-chip 50�� connected 0: On-chip 50�� disconnected */ +#define RB_ETH_EIE_TXERIE 0x02 /* RW Transmit Error Interrupt Enable */ +#define RB_ETH_EIE_RXERIE 0x01 /* RW1 receive error flag */ +#define R8_ETH_EIR (*((volatile uint8_t *)(0x40028000+4))) /* Interrupt Flag Register */ +#define RB_ETH_EIR_RXIF 0x40 /* RW1 Receive complete flag */ +#define RB_ETH_EIR_LINKIF 0x10 /* RW1 Link Change Flag */ +#define RB_ETH_EIR_TXIF 0x08 /* RW1 Link Change Flag */ +#define RB_ETH_EIR_TXERIF 0x02 /* RW1 send error flag */ +#define RB_ETH_EIR_RXERIF 0x01 /* RW1 receive error flag */ +#define R8_ETH_ESTAT (*((volatile uint8_t *)(0x40028000+5))) /* status register */ +#define RB_ETH_ESTAT_INT 0x80 /* RW1 interrupt */ +#define RB_ETH_ESTAT_BUFER 0x40 /* RW1 Buffer error */ +#define RB_ETH_ESTAT_RXCRCER 0x20 /* RO receive crc error */ +#define RB_ETH_ESTAT_RXNIBBLE 0x10 /* RO receives nibble error */ +#define RB_ETH_ESTAT_RXMORE 0x08 /* RO receives more than maximum packets */ +#define RB_ETH_ESTAT_RXBUSY 0x04 /* RO receive busy */ +#define RB_ETH_ESTAT_TXABRT 0x02 /* RO send interrupted by mcu */ +#define R8_ETH_ECON2 (*((volatile uint8_t *)(0x40028000+6))) /* ETH PHY Analog Block Control Register */ +#define RB_ETH_ECON2_RX 0x0E /* 011b must be written */ +#define RB_ETH_ECON2_TX 0x01 +#define RB_ETH_ECON2_MUST 0x06 /* 011b must be written */ + +/* Bits [3:1] - Reserved, must write 110b per reference manual */ +#define RB_ETH_ECON2_RX_MASK (0x07 << 1) /* Mask for bits [3:1]: 0x0E */ +#define RB_ETH_ECON2_RX_MUST (0x06 << 1) /* Required value: 110b = 0x0C */ +/* Bit [0] - TX Driver control */ +#define RB_ETH_ECON2_TX_RATED 0x00 /* 0: Rated driver (default) */ +#define RB_ETH_ECON2_TX_ENERGYSAVE 0x01 /* 1: Energy-saving driver */ +#define RB_ETH_ECON2_DEFAULT (RB_ETH_ECON2_RX_MUST | RB_ETH_ECON2_TX_RATED) /* 0x0C */ + +#define R8_ETH_ECON1 (*((volatile uint8_t *)(0x40028000+7))) /* Transceiver Control Register */ +#define RB_ETH_ECON1_TXRST 0x80 /* RW Send module reset */ +#define RB_ETH_ECON1_RXRST 0x40 /* RW Receiver module reset */ +#define RB_ETH_ECON1_TXRTS 0x08 /* RW The transmission starts, and it is automatically cleared after the transmission is completed. */ +#define RB_ETH_ECON1_RXEN 0x04 /* RW Receive is enabled, when cleared, the error flag RXERIF will change to 1 if it is receiving */ + +#define R32_ETH_TX (*((volatile uint32_t *)(0x40028000+8))) /* send control */ +#define R16_ETH_ETXST (*((volatile uint16_t *)(0x40028000+8))) /* RW Send DMA buffer start address */ +#define R16_ETH_ETXLN (*((volatile uint16_t *)(0x40028000+0xA))) /* RW send length */ +#define R32_ETH_RX (*((volatile uint32_t *)(0x40028000+0xC))) /* receive control */ +#define R16_ETH_ERXST (*((volatile uint16_t *)(0x40028000+0xC))) /* RW Receive DMA buffer start address */ +#define R16_ETH_ERXLN (*((volatile uint16_t *)(0x40028000+0xE))) /* RO receive length */ + +#define R32_ETH_HTL (*((volatile uint32_t *)(0x40028000+0x10))) +#define R8_ETH_EHT0 (*((volatile uint8_t *)(0x40028000+0x10))) /* RW Hash Table Byte0 */ +#define R8_ETH_EHT1 (*((volatile uint8_t *)(0x40028000+0x11))) /* RW Hash Table Byte1 */ +#define R8_ETH_EHT2 (*((volatile uint8_t *)(0x40028000+0x12))) /* RW Hash Table Byte2 */ +#define R8_ETH_EHT3 (*((volatile uint8_t *)(0x40028000+0x13))) /* RW Hash Table Byte3 */ +#define R32_ETH_HTH (*((volatile uint32_t *)(0x40028000+0x14))) +#define R8_ETH_EHT4 (*((volatile uint8_t *)(0x40028000+0x14))) /* RW Hash Table Byte4 */ +#define R8_ETH_EHT5 (*((volatile uint8_t *)(0x40028000+0x15))) /* RW Hash Table Byte5 */ +#define R8_ETH_EHT6 (*((volatile uint8_t *)(0x40028000+0x16))) /* RW Hash Table Byte6 */ +#define R8_ETH_EHT7 (*((volatile uint8_t *)(0x40028000+0x17))) /* RW Hash Table Byte7 */ + +#define R32_ETH_MACON (*((volatile uint32_t *)(0x40028000+0x18))) +#define R8_ETH_ERXFCON (*((volatile uint8_t *)(0x40028000+0x18))) /* Received Packet Filtering Control Register */ +/* RW 0=Do not enable this filter condition, 1=When ANDOR=1, +target address mismatch will be filtered, when ANDOR=0, target address match will be accepted */ +#define RB_ETH_ERXFCON_UCEN 0x80 +#define RB_ETH_ERXFCON_CRCEN 0x20 +#define RB_ETH_ERXFCON_EN 0x10 +#define RB_ETH_ERXFCON_MPEN 0x08 +#define RB_ETH_ERXFCON_HTEN 0x04 +#define RB_ETH_ERXFCON_MCEN 0x02 +#define RB_ETH_ERXFCON_BCEN 0x01 +#define R8_ETH_MACON1 (*((volatile uint8_t *)(0x40028000+0x19))) /* Mac flow control registers */ +/* RW When FULDPX=0 is invalid, when FULDPX=1, 11=send 0 timer pause frame, +then stop sending, 10=send pause frame periodically, 01=send pause frame once, then stop sending, 00=stop sending pause frame */ +#define RB_ETH_MACON1_FCEN 0x30 +#define RB_ETH_MACON1_TXPAUS 0x08 /* RW Send pause frame enable*/ +#define RB_ETH_MACON1_RXPAUS 0x04 /* RW Receive pause frame enable */ +#define RB_ETH_MACON1_PASSALL 0x02 /* RW 1=Unfiltered control frames will be written to the buffer, 0=Control frames will be filtered */ +#define RB_ETH_MACON1_MARXEN 0x01 /* RW MAC layer receive enable */ +#define R8_ETH_MACON2 (*((volatile uint8_t *)(0x40028000+0x1A))) /* Mac Layer Packet Control Register */ +#define RB_ETH_MACON2_PADCFG 0xE0 /* RW Short Packet Padding Settings */ +#define RB_ETH_MACON2_TXCRCEN 0x10 /* RW Send to add crc, if you need to add crc in PADCFG, this position is 1 */ +#define RB_ETH_MACON2_PHDREN 0x08 /* RW Special 4 bytes do not participate in crc check */ +#define RB_ETH_MACON2_HFRMEN 0x04 /* RW Allow jumbo frames */ +#define RB_ETH_MACON2_FULDPX 0x01 /* RW full duplex */ +#define R8_ETH_MABBIPG (*((volatile uint8_t *)(0x40028000+0x1B))) /* Minimum Interpacket Interval Register */ +#define RB_ETH_MABBIPG_MABBIPG 0x7F /* RW Minimum number of bytes between packets */ + +#define R32_ETH_TIM (*((volatile uint32_t *)(0x40028000+0x1C))) +#define R16_ETH_EPAUS (*((volatile uint16_t *)(0x40028000+0x1C))) /* RW Flow Control Pause Frame Time Register */ +#define R16_ETH_MAMXFL (*((volatile uint16_t *)(0x40028000+0x1E))) /* RW Maximum Received Packet Length Register */ +#define R16_ETH_MIRD (*((volatile uint16_t *)(0x40028000+0x20))) /* RW MII read data register */ + +#define R32_ETH_MIWR (*((volatile uint32_t *)(0x40028000+0x24))) +#define RB_ETH_MIWR_MIIWR (1 << 8) /* Write operation flag (bit 8) */ +#define RB_ETH_MIWR_DATA_SHIFT 16 /* Data field position (bits [31:16]) */ +#define R8_ETH_MIREGADR (*((volatile uint8_t *)(0x40028000+0x24))) /* MII address register*/ +#define RB_ETH_MIREGADR_MASK 0x1F /* RW PHY register address mask */ +#define R8_ETH_MISTAT (*((volatile uint8_t *)(0x40028000+0x25))) /* MII status register */ +/* RO MISTAT[0]: MII register status (0=Read, 1=Write) - purpose unclear, not typically needed */ +#define RB_ETH_MII_STA 0x01 +//#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII write command */ +#define R16_ETH_MIWR (*((volatile uint16_t *)(0x40028000+0x26))) /* WO MII Write Data Register */ +#define R32_ETH_MAADRL (*((volatile uint32_t *)(0x40028000+0x28))) /* RW MAC 1-4 */ +#define R8_ETH_MAADRL1 (*((volatile uint8_t *)(0x40028000+0x28))) /* RW MAC 1 */ +#define R8_ETH_MAADRL2 (*((volatile uint8_t *)(0x40028000+0x29))) /* RW MAC 2 */ +#define R8_ETH_MAADRL3 (*((volatile uint8_t *)(0x40028000+0x2A))) /* RW MAC 3 */ +#define R8_ETH_MAADRL4 (*((volatile uint8_t *)(0x40028000+0x2B))) /* RW MAC 4 */ +#define R16_ETH_MAADRH (*((volatile uint16_t *)(0x40028000+0x2C))) /* RW MAC 5-6 */ +#define R8_ETH_MAADRL5 (*((volatile uint8_t *)(0x40028000+0x2C))) /* RW MAC 4 */ +#define R8_ETH_MAADRL6 (*((volatile uint8_t *)(0x40028000+0x2D))) /* RW MAC 4 */ + +#define ROM_CFG_USERADR_ID 0x1FFFF7E8 + +//PHY Register Addresses (use with MIERGADR/MIRD for reads, or with R32_ETH_MIWR for writes) +#define PHY_BMCR 0x00 /* Control Register */ +#define PHY_BMSR 0x01 /* Status Register */ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register */ +#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ +#define PHY_PHYSR 0x10 /* Physical Layer Status Register */ +#define PHY_MDIX 0x1e /* Custom MDIX Mode Register */ + +/* PHY Register Access: + * READ: ETH10M->MIERGADR = PHY_BMSR; + * data = ETH10M->MIRD; + * + * WRITE (method 1 - 32-bit register): + * R32_ETH_MIWR = (PHY_BMCR & RB_ETH_MIREGADR_MASK) | RB_ETH_MIWR_MIIWR | (value << RB_ETH_MIWR_DATA_SHIFT); + * + * WRITE (method 2 - separate registers): + * ETH10M->MIERGADR = PHY_BMCR; + * ETH10M->MIWR = value; + */ + +// Basic Control Register (BMCR) @ 0x00 +#define PHY_BMCR_RESET (1 << 15) /* RW/SC, 1 = PHY Reset. Self-clearing bit. */ +#define PHY_BMCR_LOOPBACK (1 << 14) /* RW, 1 = Enable loopback mode */ +#define PHY_BMCR_SPEED_SELECT (1 << 13) /* 0 = 10Mb/s, RO for v20x */ +#define PHY_BMCR_AN_ENABLE (1 << 12) /* RW, 1 = Enable Auto-Negotiation */ +#define PHY_BMCR_AN_RESTART (1 << 9) /* RW/SC, 1 = Restart Auto-Negotiation. Self-clearing bit. */ +#define PHY_BMCR_FULL_DUPLEX (1 << 8) /* RW, 1 = Full-duplex, 0 = Half-duplex */ +#define PHY_BMCR_COLLISION_TEST (1 << 7) /* RW, 1 = Collision test enabled */ +// Basic Status Register (BMSR) @ 0x01 +#define PHY_BMSR_AN_COMPLETE (1 << 5) /* RO, Auto-Negotiation Process Completed */ +#define PHY_BMSR_LINK_STATUS (1 << 2) /* RO, Link is Up */ +// Auto-Negotiation Link Partner Ability Register (ANLPAR) @ 0x05 +#define PHY_ANLPAR_NP (1<<15) /* RO, Next Page ability supported by link partner */ +#define PHY_ANLPAR_ACK (1<<14) /* RO, Link partner acknowledged reception of local node's capability */ +#define PHY_ANLPAR_RF (1<<13) /* RO, Link partner is indicating a remote fault */ +#define PHY_ANLPAR_ASYPAUSE (1<<11) /* RO, Link partner supports Asymmetric PAUSE */ +#define PHY_ANLPAR_PAUSE (1<<10) /* RO, Link partner supports PAUSE */ +#define PHY_ANLPAR_100BASE_T4 (1<<9) /* RO, Link partner supports 100BASE-T4 */ +#define PHY_ANLPAR_100BASE_TXFD (1<<8) /* RO, Link partner supports 100BASE-TX Full-duplex */ +#define PHY_ANLPAR_100BASE_TXHD (1<<7) /* RO, Link partner supports 100BASE-TX Half-duplex */ +#define PHY_ANLPAR_10BASE_TFD (1<<6) /* RO, Link partner supports 10BASE-T Full-duplex */ +#define PHY_ANLPAR_10BASE_THD (1<<5) /* RO, Link partner supports 10BASE-T Half-duplex */ +// Selector Field [4:0] for ANLPAR +#define PHY_ANLPAR_SELECTOR_MASK 0x001F /* RO, Mask for the selector field */ +#define PHY_ANLPAR_SELECTOR_CSMACD 0x0001 /* RO, Indicates IEEE 802.3 (CSMA/CD) */ +// Physical Layer Status Register (PHYSR) +#define PHYSR_LOOPBACK_10M (1<<3) /* RO, 1 = PHY works in 10M self-loop */ +#define PHYSR_FULL_DUPLEX_10M (1<<2) /* RO, 1 = PHY works at 10M full-duplex */ +// Auto-flip (MDIX) Register @ 0x1E +// P/N polarity field [3:2] +#define MDIX_PN_POLARITY_MASK (0x03<<2) /* P/N polarity mask */ +#define MDIX_PN_POLARITY_NORMAL (0x00<<2) /* 00: P/N polarity is normal */ +#define MDIX_PN_POLARITY_REVERSED (0x01<<2) /* 01: P/N polarity is reversed */ +// T/R (MDI/MDIX) mode field [1:0] +#define MDIX_MODE_MASK 0x03 /* MDI/MDIX settings mask */ +#define MDIX_MODE_AUTO 0x00 /* 00: Automatic MDI/MDIX crossover */ +#define MDIX_MODE_MDIX 0x01 /* 01: Forced MDIX (crossover) mode */ +#define MDIX_MODE_MDI 0x02 /* 1x: Forced MDI (straight) mode */ +//ECON2 test mode, to be determined +#define RX_VCM_MODE_0 +#define RX_VCM_MODE_1 +#define RX_VCM_MODE_2 +#define RX_VCM_MODE_3 +//RX reference voltage value setting @RX_REF +#define RX_REF_25mV (0<<2) /* 25mV */ +#define RX_REF_49mV (1<<2) /* 49mV */ +#define RX_REF_74mV (2<<2) /* 74mV */ +#define RX_REF_98mV (3<<2) /* 98mV */ +#define RX_REF_123mV (4<<2) /* 123mV */ +#define RX_REF_148mV (5<<2) /* 148mV */ +#define RX_REF_173mV (6<<2) /* 173mV */ +#define RX_REF_198mV (7<<2) /* 198mV */ +//TX DRIVER Bias Current @TX_AMP +#define TX_AMP_0 (0<<0) /* 43mA / 14.5mA (1.4V/0.7V) */ +#define TX_AMP_1 (1<<0) /* 53.1mA / 18mA (1.8V/0.9V) */ +#define TX_AMP_2 (2<<0) /* 75.6mA / 25.6mA (2.6V/1.3V) */ +#define TX_AMP_3 (3<<0) /* 122mA / 41.45mA (4.1V/2.3V) */ +//FCEN pause frame control @FCEN +#define FCEN_0_TIMER (3<<4) /* Send a 0 timer pause frame, then stop sending */ +#define FCEN_CYCLE (2<<4) /* Periodically send pause frames */ +#define FCEN_ONCE (1<<4) /* Send pause frame once, then stop sending */ +#define FCEN_STOP (0<<4) /* Stop sending pause frames */ +//PADCFG short packet control @PADCFG +#define PADCFG_AUTO_0 (7<<5) /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */ +#define PADCFG_NO_ACT_0 (6<<5) /* No padding for short packets */ +/* The detected VLAN network packet whose field is 8100h is automatically filled +with 00h to 64 bytes, otherwise the short packet is filled with 60 bytes of 0, and then 4 bytes of crc after filling */ +#define PADCFG_DETE_AUTO (5<<5) +#define PADCFG_NO_ACT_1 (4<<5) /* No padding for short packets */ +#define PADCFG_AUTO_1 (3<<5) /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */ +#define PADCFG_NO_ACT_2 (2<<5) /* No padding for short packets */ +#define PADCFG_AUTO_3 (1<<5) /* All short packets are filled with 00h to 60 bytes, and then 4 bytes crc */ +#define PADCFG_NO_ACT_3 (0<<5) /* No padding for short packets */ + +//MII control +#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII write command */ +#define RB_ETH_MIREGADR_MIRDL 0x1f /* RW PHY register address */ + + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* eth_driver.h -----------------------------------------------------------*/ +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +#define ETH_DMARxDesc_FrameLengthShift 16 /* Bit position of frame length field */ + + +/* ch32v00x_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32v00x_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +///* CTLR1 register Mask */ +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/* ch32v20x_bkp.c ------------------------------------------------------------*/ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + + +/* ch32v20x_can.c ------------------------------------------------------------*/ +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + + + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32v00x_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + + +/* DMA2 FLAG mask */ +// Editor's note: Overloaded Definition. +#define DMA2_FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32v00x_flash.c ----------------------------------------------------------*/ + + + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_BER64 ((uint32_t)0x00080000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* EEPROM address */ +#define EEPROM_ADDRESS ((uint32_t)0x8070000) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + + +/* ch32v00x_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +////* I2C registers Masks */ +// Editor's note: Overloaded Definition. +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +//Editor's Note: Overloaded Definition +#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + + +/* ch32v20x_opa.c ------------------------------------------------------------*/ +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + + +/* ch32v00x_pwr.c ------------------------------------------------------------*/ + + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* ch32v00x_rcc.c ------------------------------------------------------------*/ + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + + +/* RCC Flag Mask */ +//Editor's Note: Overloaded Definition +#define RCC_FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +#ifndef __ASSEMBLER__ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; +#endif + + +/* ch32v20x_rtc.c ------------------------------------------------------------*/ + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32v00x_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + + +/* ch32v00x_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + + + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + + + +/* ch32v20x_bkp.h ------------------------------------------------------------*/ + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + + +/* ch32v20x_can.h ------------------------------------------------------------*/ + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + +/* CAN_flags */ +/* Transmit Flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + + +/* ch32v00x_dac.h ------------------------------------------------------------*/ + +/* DAC_trigger_selection */ +#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ + +/* DAC_wave_generation */ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) + + +/* DAC_lfsrunmask_triangleamplitude */ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ + +/* DAC_output_buffer */ +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) + +/* DAC_Channel_selection */ +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) + +/* DAC_data_alignment */ +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) + +/* DAC_wave_generation */ +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) + +/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ + +/* CFGR0 Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) + +/* ch32v00x_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \ + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */ +#endif + + +/* ch32v00x_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +} FLASH_Status; +#endif + + + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */ + + + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ + +/* PCFR1 */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ + to TIM2 Internal Trigger 1 for calibration \ + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +/* PCFR2 */ +#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ +#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ +#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ +#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* Ethernet_Media_Interface */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +/* ch32v00x_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +/* ch32v00x_misc.h -----------------------------------------------------------*/ + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + +/* ch32v00x_opa.h ------------------------------------------------------------*/ + +/* Editor's note: I don't know if this is actually useful */ +#ifndef __ASSEMBLER__ + +/* OPA member enumeration */ +typedef enum +{ + OPA1 = 0, + OPA2, + OPA3, + OPA4 +} OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; + +/* OPA out channel enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1 +} OPA_Mode_TypeDef; + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ +} OPA_InitTypeDef; + +#endif + +/* ch32v00x_pwr.h ------------------------------------------------------------*/ + + + +/* PVD_detection_level */ +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + + +/* ch32v00x_rcc.h ------------------------------------------------------------*/ + + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if defined(CH32V20x) || defined(CH32V30x_D8) || defined(CH32V10x) + +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +#else + +#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + +#endif + +#if defined(CH32V20x) || defined(CH32V30x_D8) || defined(CH32V10x) + +/* PLL_multiplication_factor for other CH32V20x */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) + +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +#else + +#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000) +#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000) +#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000) +#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000) +#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000) +#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000) +#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000) +#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000) +#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000) +#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000) +#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000) +#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000) +#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000) +#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000) +#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000) +#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000) + +#endif // defined(CH32V20x) || defined(CH32V30x_D8) || defined(CH32V10x) + +/* PREDIV1_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) +#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) +#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) +#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) +#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) +#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) +#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) +#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) +#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) +#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) +#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) +#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) +#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) +#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) +#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + +#endif + +/* PREDIV1_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) +#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) +#endif + +/* PREDIV2_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) +#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) +#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) +#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) +#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) +#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) +#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) +#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) +#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) +#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) +#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) +#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) +#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) +#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) +#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) +#endif + +/* PLL2_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100) +#define RCC_PLL2Mul_4 ((uint32_t)0x00000200) +#define RCC_PLL2Mul_5 ((uint32_t)0x00000300) +#define RCC_PLL2Mul_6 ((uint32_t)0x00000400) +#define RCC_PLL2Mul_7 ((uint32_t)0x00000500) +#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) +#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) +#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) +#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) +#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) +#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) +#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) +#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00) +#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) +#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) +#endif + +/* PLL3_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000) +#define RCC_PLL3Mul_4 ((uint32_t)0x00002000) +#define RCC_PLL3Mul_5 ((uint32_t)0x00003000) +#define RCC_PLL3Mul_6 ((uint32_t)0x00004000) +#define RCC_PLL3Mul_7 ((uint32_t)0x00005000) +#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) +#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) +#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) +#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) +#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) +#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) +#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) +#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000) +#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) +#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) +#endif + + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifdef CH32V30x_D8C +#define RCC_IT_PLL2RDY ((uint8_t)0x20) +#define RCC_IT_PLL3RDY ((uint8_t)0x40) +#endif + + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02) + +#ifdef CH32V20x_D8W + #define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03) +#endif + + + + + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + + + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) + + +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + +#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) + +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + +#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + + +#ifdef CH32V20x_D8W +#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040) +#endif + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) + + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifdef CH32V30x_D8C +#define RCC_MCO_PLL2CLK ((uint8_t)0x08) +#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) +#define RCC_MCO_XT1 ((uint8_t)0x0A) +#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) +#endif + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifdef CH32V30x_D8C +#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) +#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) +#endif + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RNG_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) +#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) +#endif + +/* ETH1G_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) +#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) +#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) +#endif + + +/* USBFS_clock_source */ +#define RCC_USBPLL_Div1 ((uint32_t)0x00) +#define RCC_USBPLL_Div2 ((uint32_t)0x01) +#define RCC_USBPLL_Div3 ((uint32_t)0x02) +#define RCC_USBPLL_Div4 ((uint32_t)0x03) +#define RCC_USBPLL_Div5 ((uint32_t)0x04) +#define RCC_USBPLL_Div6 ((uint32_t)0x05) +#define RCC_USBPLL_Div7 ((uint32_t)0x06) +#define RCC_USBPLL_Div8 ((uint32_t)0x07) + +/* ETH_clock_source */ +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define RCC_ETHCLK_Div1 ((uint32_t)0x00) + #define RCC_ETHCLK_Div2 ((uint32_t)0x01) +#endif + + + + + +/* ch32v00x_rtc.h ------------------------------------------------------------*/ +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define RB_OSC32K_HTUNE (0x1FE0) +#define RB_OSC32K_LTUNE (0x1F) + +#define RB_OSC_CAL_HALT (0x80) +#define RB_OSC_CAL_EN (0x02) +#define RB_OSC_CAL_INT_EN (0x01) + +#define RB_OSC_CAL_OV_CNT (0xFF) + +#define RB_OSC_CAL_IF_END (1 << 15) +#define RB_OSC_CAL_CNT_OV (1 << 14) +#define RB_OSC_CAL_CNT (0x3FFF) + +#define RB_CAL_LP_EN (1 << 6) +#define RB_CAL_WKUP_EN (1 << 5) +#define RB_OSC_HALT_MD (1 << 4) +#define RB_OSC_CNT_VLU (0x0F) + + +#ifdef CLK_OSC32K +#if ( CLK_OSC32K == 1 ) +#define CAB_LSIFQ 32000 +#else +#define CAB_LSIFQ 32768 +#endif +#else +#define CAB_LSIFQ 32000 +#endif +#endif // defined(CH32V20x_D8) || defined(CH32V20x_D8W) + + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +// While not truly CH32X035, we can re-use some of the USB register defs. + +/* ch32v30x_usb.h ------------------------------------------------------------*/ + + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. + #define DMDATA0 ((volatile uint32_t*)0xe0000380) + #define DMDATA1 ((volatile uint32_t*)0xe0000384) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000388)// Reads as 0x00000000 if debugger is attached. + +// Determination of PLL multiplication factor for non-V003 chips + #if !defined(FUNCONF_SYSTEM_CORE_CLOCK) + #define PLL_MULTIPLICATION ((uint32_t)0) + #else + #if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x_D8) + #if FUNCONF_PLL_MULTIPLIER == 2 + #define PLL_MULTIPLICATION RCC_PLLMULL2 + #elif FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3 + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4 + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5 + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6 + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7 + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8 + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9 + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10 + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11 + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12 + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13 + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14 + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15 + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16 + #elif defined(CH32V20x) && FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18 + #else + #error "Invalid PLL multiplier" + #endif + #else + #if FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18_EXTEN + #else + #error "Invalid PLL multiplier" + #endif + #endif + #endif + + + + +// Applies to all processors + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA1 1 +#define PA2 2 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +#define PA0 0 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 + +#define LL_TX_POWER_MINUS_18_DBM 0x01 +#define LL_TX_POWER_MINUS_10_DBM 0x03 +#define LL_TX_POWER_MINUS_5_DBM 0x05 +#define LL_TX_POWER_MINUS_3_DBM 0x07 +#define LL_TX_POWER_0_DBM 0x09 +#define LL_TX_POWER_1_DBM 0x0B +#define LL_TX_POWER_2_DBM 0x0D +#define LL_TX_POWER_3_DBM 0x11 +#define LL_TX_POWER_4_DBM 0x15 +#define LL_TX_POWER_5_DBM 0x1B +#define LL_TX_POWER_6_DBM 0x25 +#define LL_TX_POWER_7_DBM 0x3F + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/ch32v30xhw.h b/inc/ch32v30xhw.h new file mode 100644 index 0000000..35c73e0 --- /dev/null +++ b/inc/ch32v30xhw.h @@ -0,0 +1,10625 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + +#ifdef CH32V30x_D8 + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ +#elif defined (CH32V30x_D8C) + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ +#endif + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + FSMC_IRQn = 64, /* FSMC global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 77, /* ETH global Interrupt */ + OTG_FS_IRQn = 83, /* OTGFS global Interrupt NOTE: THIS APPEAR TO BE INCORRECT */ + USBHSWakeup_IRQn = 84, /* USBHS Wakeup Interrupt */ + USBHS_IRQn = 85, /* USBHS global Interrupt */ + DVP_IRQn = 86, /* DVP global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ +} IRQn_Type; + + + +#define BASE_VECTOR "\n\ + .balign 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0 \n\ + .word NMI_Handler /* NMI */ \n\ + .word HardFault_Handler /* Hard Fault */ \n\ + .word 0 \n\ + .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\ + .word 0 \n\ + .word 0 \n\ + .word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\ + .word Break_Point_Handler /* Break Point */ \n\ + .word 0 \n\ + .word 0 \n\ + .word SysTick_Handler /* SysTick */ \n \ + .word 0 \n \ + .word SW_Handler /* SW */ \n \ + .word 0 \n \ + /* External Interrupts */ \n \ + .word WWDG_IRQHandler /* Window Watchdog */ \n \ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n \ + .word TAMPER_IRQHandler /* TAMPER */ \n \ + .word RTC_IRQHandler /* RTC */ \n \ + .word FLASH_IRQHandler /* Flash */ \n \ + .word RCC_IRQHandler /* RCC */ \n \ + .word EXTI0_IRQHandler /* EXTI Line 0 */ \n \ + .word EXTI1_IRQHandler /* EXTI Line 1 */ \n \ + .word EXTI2_IRQHandler /* EXTI Line 2 */ \n \ + .word EXTI3_IRQHandler /* EXTI Line 3 */ \n \ + .word EXTI4_IRQHandler /* EXTI Line 4 */ \n \ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n \ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n \ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n \ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n \ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n \ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n \ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n \ + .word ADC1_2_IRQHandler /* ADC1_2 */ \n \ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ \n \ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ \n \ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \n \ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n \ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ \n \ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n \ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n \ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n \ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n \ + .word TIM2_IRQHandler /* TIM2 */ \n \ + .word TIM3_IRQHandler /* TIM3 */ \n \ + .word TIM4_IRQHandler /* TIM4 */ \n \ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n \ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n \ + .word I2C2_EV_IRQHandler /* I2C2 Event */ \n \ + .word I2C2_ER_IRQHandler /* I2C2 Error */ \n \ + .word SPI1_IRQHandler /* SPI1 */ \n \ + .word SPI2_IRQHandler /* SPI2 */ \n \ + .word USART1_IRQHandler /* USART1 */ \n \ + .word USART2_IRQHandler /* USART2 */ \n \ + .word USART3_IRQHandler /* USART3 */ \n \ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ \n \ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n" +#if defined(CH32V30x_D8C) +#define EXTRA_VECTOR0 ".word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ \n" +#else +#define EXTRA_VECTOR0 ".word 0 \n" +#endif +#define BASE_VECTOR_CONTINUE "\n\ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ \n \ + .word TIM8_UP_IRQHandler /* TIM8 Update */ \n \ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ \n \ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ \n \ + .word RNG_IRQHandler /* RNG */ \n \ + .word 0 \n \ + .word SDIO_IRQHandler /* SDIO */ \n \ + .word TIM5_IRQHandler /* TIM5 */ \n \ + .word SPI3_IRQHandler /* SPI3 */ \n \ + .word UART4_IRQHandler /* UART4 */ \n \ + .word UART5_IRQHandler /* UART5 */ \n \ + .word TIM6_IRQHandler /* TIM6 */ \n \ + .word TIM7_IRQHandler /* TIM7 */ \n \ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ \n \ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ \n \ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ \n \ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ \n \ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ \n" +#if defined(CH32V30x_D8C) +#define EXTRA_VECTOR "\n\ + .word ETH_IRQHandler /* ETH */ \n \ + .word ETHWakeUp_IRQHandler /* ETH WakeUp */ \n \ + .word CAN2_TX_IRQHandler /* CAN2 TX */ \n \ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ \n \ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ \n \ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ \n \ + .word USBFS_IRQHandler /* USBFS */ \n \ + .word USBHSWakeUp_IRQHandler /* USBHS Wakeup */ \n \ + .word USBHS_IRQHandler /* USBHS */ \n \ + .word DVP_IRQHandler /* DVP */ \n" +//defined(CH32V30x_D8C) +#else // defined(CH32V30x_D8) +#define EXTRA_VECTOR "\n\ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n \ + .word USBFS_IRQHandler /* USBFS */ \n \ + .word 0 \n \ + .word 0 \n \ + .word 0 \n" +#endif // End else (Likely defined(CH32V30x_D8)) +#define LAST_VECTOR_BASE "\n\ + .word UART6_IRQHandler /* UART6 */ \n \ + .word UART7_IRQHandler /* UART7 */ \n \ + .word UART8_IRQHandler /* UART8 */ \n \ + .word TIM9_BRK_IRQHandler /* TIM9 Break */ \n \ + .word TIM9_UP_IRQHandler /* TIM9 Update */ \n \ + .word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ \n \ + .word TIM9_CC_IRQHandler /* TIM9 Capture Compare */ \n \ + .word TIM10_BRK_IRQHandler /* TIM10 Break */ \n \ + .word TIM10_UP_IRQHandler /* TIM10 Update */ \n \ + .word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ \n \ + .word TIM10_CC_IRQHandler /* TIM10 Capture Compare */ \n \ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ \n \ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ \n \ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ \n \ + .word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ \n \ + .word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ \n \ + .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ \n" +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR EXTRA_VECTOR0 BASE_VECTOR_CONTINUE EXTRA_VECTOR LAST_VECTOR_BASE "\n.option pop;\n" + + + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + #define ADC1_2_IRQn ADC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + uint32_t RESERVED0[86]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +typedef struct +{ + __IO uint16_t CAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UID0; + __IO uint32_t UID1; + __IO uint32_t UID2; + __IO uint32_t RES3; +} ESG_TypeDef; + +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct + { + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; + +/* FSMC Bank1 Registers */ +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/* FSMC Bank1E Registers */ +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/* FSMC Bank2 Registers */ +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* SDIO Registers */ +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; + __IO uint32_t EXTEN_CTR2; + __IO uint32_t FEATURE_SIGN; +} EXTEN_TypeDef; + +/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ +typedef struct +{ + __IO uint32_t CTR; +} EXTEND_TypeDef; + + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + +/* RNG Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; +} RNG_TypeDef; + +/* DVP Registers */ +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t IER; + __IO uint8_t Reserved0; + __IO uint16_t ROW_NUM; + __IO uint16_t COL_NUM; + __IO uint32_t DMA_BUF0; + __IO uint32_t DMA_BUF1; + __IO uint8_t IFR; + __IO uint8_t STATUS; + __IO uint16_t Reserved1; + __IO uint16_t ROW_CNT; + __IO uint16_t Reserved2; + __IO uint16_t HOFFCNT; + __IO uint16_t VST; + __IO uint16_t CAPCNT; + __IO uint16_t VLINE; + __IO uint32_t DR; +} DVP_TypeDef; + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + + +/* USBD Full-Speed Device, Chapter 21. + NOTE: USBD and CAN controller share a dedicated 512-byte SRAM area for data + transmission and reception in the design, so when using USBD and CAN functions + at the same time, this shared area needs to be allocated reasonably to prevent + data conflicts. */ + +typedef struct +{ + __IO uint32_t ADDn_TX; + __IO uint32_t COUNTn_TX; + __IO uint32_t ADDn_RX; + __IO uint32_t COUNTn_RX; +} USBD_BTABLE_TypeDef; + +typedef struct +{ + __IO uint32_t EPR[8]; + __IO uint32_t RESERVED[8]; + __IO uint32_t CNTR; + __IO uint32_t ISTR; + __IO uint32_t FNR; + __IO uint32_t DADDR; + __IO uint32_t BTABLE; +} USBD_TypeDef; + +#define CAN_USBD_SHARED_BASE ((PERIPH_BASE + 0x6000)) +#define USBD_BASE ((PERIPH_BASE + 0x5C00)) + +/* USBD_CNTR */ +#define USBD_CTRM (1<<15) +#define USBD_PMAOVRM (1<<14) +#define USBD_ERRM (1<<13) +#define USBD_WKUPM (1<<12) +#define USBD_SUSPM (1<<11) +#define USBD_RESETM (1<<10) +#define USBD_SOFM (1<<9) +#define USBD_ESOFM (1<<8) +#define USBD_RESUME (1<<4) +#define USBD_FSUP (1<<3) +#define USBD_LPMODE (1<<2) +#define USBD_PDWN (1<<1) +#define USBD_FRES (1<<0) + +/* USBD_ISTR */ +#define USBD_CTR (1<<15) +#define USBD_PMAOVR (1<<14) +#define USBD_ERR (1<<13) +#define USBD_WKUP (1<<12) +#define USBD_SUSP (1<<11) +#define USBD_RESET (1<<10) +#define USBD_SOF (1<<9) +#define USBD_ESOF (1<<8) +#define USBD_DIR (1<<4) +#define USBD_EP_ID (0xf) + +/* USBD_FNR */ +#define USBD_RXDP (1<<15) +#define USBD_RXDM (1<<14) +#define USBD_LCK (1<<13) +#define USBD_LSOF (3<<11) +#define USBD_FN (0x7ff) + +/* USBD_DADDR */ +#define USBD_EF (1<<7) +#define USBD_ADD (0x7f) + +/* USBD_EPRx */ +#define USBD_CTR_RX (1<<15) +#define USBD_DTOG_RX (1<<14) +#define USBD_STAT_RX (3<<12) +#define USBD_SETUP (1<<11) +#define USBD_EPTYPE (3<<9) +#define USBD_EPKIND (1<<8) +#define USBD_CTR_TX (1<<7) +#define USBD_DTOG_TX (1<<6) +#define USBD_STAT_TX (3<<4) +#define USBD_EA (0xf) + +/* USBD_COUNTx_RX */ +#define USBD_BLSIZE (1<<15) +#define USBD_NUM_BLOCK (0x1f<<10) +#define USBD_COUNTx_RX 0x2ff + + +#define USBD ((USBD_TypeDef *) USBD_BASE) + +/* USB-FS-OTG Registers, Chapter 23. */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTG_FS_TypeDef; + +/* R8_USB_CTRL */ +#define USBOTG_UC_HOST_MODE (1<<7) +#define USBOTG_UC_LOW_SPEED (1<<6) +#define USBOTG_UC_DEV_PU_EN (1<<5) +#define USBOTG_UC_SYS_CTRL (1<<4) +#define USBOTG_UC_INT_BUSY (1<<3) +#define USBOTG_UC_RESET_SIE (1<<2) +#define USBOTG_UC_CLR_ALL (1<<1) +#define USBOTG_UC_DMA_EN (1<<0) + +/* R8_USB_INT_EN */ +#define USBOTG_UIE_DEV_NAK (1<<6) +#define USBOTG_UIE_FIFO_OV (1<<4) +#define USBOTG_UIE_HST_SOF (1<<3) +#define USBOTG_UIE_SUSPEND (1<<2) +#define USBOTG_UIE_TRANSFER (1<<1) +#define USBOTG_UIE_DETECT (1<<0) +#define USBOTG_UIE_BUS_RST (1<<0) + +/* R8_USB_DEV_AD */ +#define USBOTG_UDA_GP_BIT (1<<7) +#define USBOTG_USB_ADDR (1<<6) + +/* R8_USB_MIS_ST */ +#define USBOTG_UMS_SOF_PRES (1<<7) +#define USBOTG_UMS_SOF_ACT (1<<6) +#define USBOTG_UMS_SIE_FREE (1<<5) +#define USBOTG_UMS_R_FIFO_RDY (1<<4) +#define USBOTG_UMS_BUS_RESET (1<<3) +#define USBOTG_UMS_SUSPEND (1<<2) +#define USBOTG_UMS_DM_LEVEL (1<<1) +#define USBOTG_UMS_DEV_ATTACH (1<<0) + +/* R8_USB_INT_FG */ +#define USBOTG_U_IS_NAK (1<<7) +#define USBOTG_U_TOG_OK (1<<6) +#define USBOTG_U_SIE_FREE (1<<5) +#define USBOTG_UIF_FIFO_OV (1<<4) +#define USBOTG_UIF_HST_SOF (1<<3) +#define USBOTG_UIF_SUSPEND (1<<2) +#define USBOTG_UIF_TRANSFER (1<<1) +#define USBOTG_UIF_DETECT (1<<0) +#define USBOTG_UIF_BUS_RST (1<<0) + +/* R8_USB_INT_ST */ +#define USBOTG_UIS_IS_NAK (1<<7) +#define USBOTG_UIS_TOG_OK (1<<6) +#define USBOTG_UIS_TOKEN (3<<4) +#define USBOTG_UIS_ENDP 0xf +#define USBOTG_UIS_H_RES 0xf + +/* R32_USB_OTG_CR */ +#define USBOTG_CR_SESS_VTH (1<<5) +#define USBOTG_CR_VBUS_VTH (1<<4) +#define USBOTG_CR_OTG_EN (1<<3) +#define USBOTG_CR_IDPU (1<<2) +#define USBOTG_CR_CHARGE_VBUS (1<<1) +#define USBOTG_CR_DISCHAR_VBUS (1<<0) + +/* R32_USB_OTG_SR */ +#define USBOTG_SR_ID_DIG (1<<3) +#define USBOTG_SR_SESS_END (1<<2) +#define USBOTG_SR_SESS_VLD (1<<1) +#define USBOTG_SR_VBUS_VLD (1<<0) + +/* R8_UEPn_TX_CTRL */ +#define USBOTG_UEP_T_AUTO_TOG (1<<3) +#define USBOTG_UEP_T_TOG (1<<2) +#define USBOTG_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBOTG_UEP_T_RES_ACK (0<<1) +#define USBOTG_UEP_T_RES_NONE (1<<0) +#define USBOTG_UEP_T_RES_NAK (1<<1) +#define USBOTG_UEP_T_RES_STALL (3<<0) + +#define USBOTG_UEP_R_AUTO_TOG (1<<3) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBOTG_UEP_R_TOG (1<<2) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBOTG_UEP_R_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBOTG_UEP_R_RES_ACK (0<<1) +#define USBOTG_UEP_R_RES_NONE (1<<0) +#define USBOTG_UEP_R_RES_NAK (1<<1) +#define USBOTG_UEP_R_RES_STALL (3<<0) + + + +/* R8_UEPn_ RX_CTRL */ +#define USBOTG_UEP_R_AUTO_TOG (1<<3) +#define USBOTG_UEP_R_TOG (1<<2) +#define USBOTG_UEP_R_RES (3<<0) + +/* R8_UEP7_MOD */ +#define USBOTG_UEP7_RX_EN (1<<3) +#define USBOTG_UEP7_TX_EN (1<<2) +#define USBOTG_UEP7_BUF_MOD (1<<0) + +/* R8_UEP5_6_MOD */ +#define USBOTG_UEP6_RX_EN (1<<7) +#define USBOTG_UEP6_TX_EN (1<<6) +#define USBOTG_UEP6_BUF_MOD (1<<4) +#define USBOTG_UEP5_RX_EN (1<<3) +#define USBOTG_UEP5_TX_EN (1<<2) +#define USBOTG_UEP5_BUF_MOD (1<<0) + +/* R8_UEP2_3_MOD */ +#define USBOTG_UEP3_RX_EN (1<<7) +#define USBOTG_UEP3_TX_EN (1<<6) +#define USBOTG_UEP3_BUF_MOD (1<<4) +#define USBOTG_UEP2_RX_EN (1<<3) +#define USBOTG_UEP2_TX_EN (1<<2) +#define USBOTG_UEP2_BUF_MOD (1<<0) + +/* R8_UEP4_1_MOD */ +#define USBOTG_UEP1_RX_EN (1<<7) +#define USBOTG_UEP1_TX_EN (1<<6) +#define USBOTG_UEP1_BUF_MOD (1<<4) +#define USBOTG_UEP4_RX_EN (1<<3) +#define USBOTG_UEP4_TX_EN (1<<2) +#define USBOTG_UEP4_BUF_MOD (1<<0) + +/* R8_UDEV_CTRL */ +#define USBOTG_UD_PD_DIS (1<<7) +#define USBOTG_UD_DP_PIN (1<<5) +#define USBOTG_UD_DM_PIN (1<<4) +#define USBOTG_UD_LOW_SPEED (1<<2) +#define USBOTG_UD_GP_BIT (1<<1) +#define USBOTG_UD_PORT_EN (1<<0) + + +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ +#define UEP_SIZE 64 + +#define DEF_UEP_IN 0x80 +#define DEF_UEP_OUT 0x00 +#define DEF_UEP_BUSY 0x01 +#define DEF_UEP_FREE 0x00 + +#define DEF_UEP0 0 +#define DEF_UEP1 1 +#define DEF_UEP2 2 +#define DEF_UEP3 3 +#define DEF_UEP4 4 +#define DEF_UEP5 5 +#define DEF_UEP6 6 +#define DEF_UEP7 7 +#define UNUM_EP 8 + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTG_FS_HOST_TypeDef; + +/* R8_UHOST_CTRL */ +#define USBOTG_UH_PD_DIS (1<<7) +#define USBOTG_UH_DP_PIN (1<<5) +#define USBOTG_UH_DM_PIN (1<<4) +#define USBOTG_UH_LOW_SPEED (1<<2) +#define USBOTG_UH_BUS_RESET (1<<1) +#define USBOTG_UH_PORT_EN (1<<0) + +/* R32_UH_EP_MOD */ +#define USBOTG_UH_EP_TX_EN (1<<6) +#define USBOTG_UH_EP_TBUF_MOD (1<<4) +#define USBOTG_UH_EP_RX_EN (1<<3) +#define USBOTG_UH_EP_RBUF_MOD (1<<0) + +/* R16_UH_SETUP */ +#define USBOTG_UH_PRE_PID_EN (1<<10) +#define USBOTG_UH_SOF_EN (1<<2) + +/* R8_UH_EP_PID */ +#define USBOTG_UH_TOKEN (0xf<<4) +#define USBOTG_UH_ENDP (0xf<<0) + +/* R8_UH_RX_CTRL */ +#define USBOTG_UH_R_AUTO_TOG (1<<3) +#define USBOTG_UH_R_TOG (1<<2) +#define USBOTG_UH_R_RES (1<<0) + +/* R8_UH_TX_CTRL */ +#define USBOTG_UH_T_AUTO_TOG (1<<3) +#define USBOTG_UH_T_TOG (1<<2) +#define USBOTG_UH_T_RES (1<<0) + + + +/* Ethernet MAC */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/* ETH10M Registers */ +typedef struct +{ + __IO uint8_t reserved1; + __IO uint8_t reserved2; + __IO uint8_t reserved3; + __IO uint8_t EIE; + + __IO uint8_t EIR; + __IO uint8_t ESTAT; + __IO uint8_t ECON2; + __IO uint8_t ECON1; + + __IO uint16_t ETXST; + __IO uint16_t ETXLN; + + __IO uint16_t ERXST; + __IO uint16_t ERXLN; + + __IO uint32_t HTL; + __IO uint32_t HTH; + + __IO uint8_t ERXFON; + __IO uint8_t MACON1; + __IO uint8_t MACON2; + __IO uint8_t MABBIPG; + + __IO uint16_t EPAUS; + __IO uint16_t MAMXFL; + + __IO uint16_t MIRD; + __IO uint16_t reserved4; + + __IO uint8_t MIERGADR; + __IO uint8_t MISTAT; + __IO uint16_t MIWR; + + __IO uint32_t MAADRL; + + __IO uint16_t MAADRH; + __IO uint16_t reserved5; +} ETH10M_TypeDef; +#endif + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/* OSC Registers */ +typedef struct +{ + __IO uint32_t HSE_CAL_CTRL; + __IO uint32_t Reserve0; + __IO uint16_t Reserve1; + __IO uint16_t LSI32K_TUNE; + __IO uint32_t Reserve2; + __IO uint32_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint8_t Reserve6; + __IO uint8_t LSI32K_CAL_CFG; + __IO uint16_t Reserve7; + __IO uint16_t LSI32K_CAL_STATR; + __IO uint8_t LSI32K_CAL_OV_CNT; + __IO uint8_t LSI32K_CAL_CTRL; +} OSC_TypeDef; + +#endif + + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif // !__ASSEMBLER__ + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + +#ifdef __ASSEMBLER__ +#define FSMC_R_BASE (b 0xA0000000) /* FSMC registers base address */ +#else +#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ +#endif + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define UART6_BASE (APB1PERIPH_BASE + 0x1800) +#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) +#define UART8_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define BKP2_BASE (APB1PERIPH_BASE + 0x6C40) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) +#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) +#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) +#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) +#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) +#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) +#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ + +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define USBFS_BASE ((uint32_t)0x50000000) +#define DVP_BASE ((uint32_t)0x50050000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) + +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + + + + + + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define UART6 ((USART_TypeDef *) UART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) +#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) +#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) +#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) +#define USBOTG_H_FS ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESG_TypeDef *)ESIG_BASE) +// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + + +#define DVP ((DVP_TypeDef *) DVP_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0xFFFFFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0xFFFFFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0xFFFFFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0xFFFFFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0xFFFFFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG (0x0001) /* Programming */ +#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT (0x0040) /* Start */ +#define FLASH_CTLR_LOCK (0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK (0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG (0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER (0x00020000) /* Page Erase 64Byte */ +#define FLASH_CTLR_PAGE_BER32 (0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PAGE_BER64 (0x00080000) /* Block Erase 64K */ +#define FLASH_CTLR_PG_STRT (0x00200000) /* Page Programming Start */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00200000) /* USART1 remapping higher bit */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP1 /* legacy compatibility */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP2 ((uint32_t)0x00000080) /* Partial remap (ETR/PD4, CH1/PD2, CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2, CH1N/PD0, CN2N/PA2, CH3N/PD1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ +#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ +#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ +#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ +#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ +#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ +#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ +#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/* for CH32V307 */ +#define RCC_PLL3RDY ((uint32_t)(1<<29)) +#define RCC_PLL3ON ((uint32_t)(1<<28)) +#define RCC_PLL2RDY ((uint32_t)(1<<27)) +#define RCC_PLL2ON ((uint32_t)(1<<26)) + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + +/* for CH32V307 */ +#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ +#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ +#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ +#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_CFGR2 register *******************/ +#define RCC_PREDIV1_OFFSET (0) +#define RCC_PREDIV1_MASK ((uint32_t)(0xf<CTLRL & RTC_FLAG_RTOFF)); \ + RTC->CTLRL |= RTC_CTLRL_CNF; \ + {a} \ + while (!(RTC->CTLRL & RTC_FLAG_RTOFF)); \ + RTC->CTLRL &= ~RTC_CTLRL_CNF; \ +} while (0) + + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define RB_OSC32K_HTUNE (0x1FE0) +#define RB_OSC32K_LTUNE (0x1F) + +#define RB_OSC_CAL_HALT (0x80) +#define RB_OSC_CAL_EN (0x02) +#define RB_OSC_CAL_INT_EN (0x01) + +#define RB_OSC_CAL_OV_CNT (0xFF) + +#define RB_OSC_CAL_IF_END (1 << 15) +#define RB_OSC_CAL_CNT_OV (1 << 14) +#define RB_OSC_CAL_CNT (0x3FFF) + +#define RB_CAL_LP_EN (1 << 6) +#define RB_CAL_WKUP_EN (1 << 5) +#define RB_OSC_HALT_MD (1 << 4) +#define RB_OSC_CNT_VLU (0x0F) + + +#ifdef CLK_OSC32K +#if ( CLK_OSC32K == 1 ) +#define CAB_LSIFQ 32000 +#else +#define CAB_LSIFQ 32768 +#endif +#else +#define CAB_LSIFQ 32000 +#endif +#endif // defined(CH32V20x_D8) || defined(CH32V20x_D8W) + + +/* ch32v00x_sdio.h -----------------------------------------------------------*/ + +/* SDIO_Clock_Edge */ +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) + +/* SDIO_Clock_Bypass */ +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) + +/* SDIO_Clock_Power_Save */ +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) + +/* SDIO_Bus_Wide */ +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) + +/* SDIO_Hardware_Flow_Control */ +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) + +/* SDIO_Power_State */ +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) + +/* SDIO_Interrupt_sources */ +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Response_Type */ +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) + +/* SDIO_Wait_Interrupt_State */ +#define SDIO_Wait_No ((uint32_t)0x00000000) +#define SDIO_Wait_IT ((uint32_t)0x00000100) +#define SDIO_Wait_Pend ((uint32_t)0x00000200) + +/* SDIO_CPSM_State */ +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) + +/* SDIO_Response_Registers */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +/* SDIO_Data_Block_Size */ +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) + +/* SDIO_Transfer_Direction */ +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) + +/* SDIO_Transfer_Type */ +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) + +/* SDIO_DPSM_State */ +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) + +/* SDIO_Flags */ +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Read_Wait_Mode */ +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +// While not truly CH32X035, we can re-use some of the USB register defs. + +/* ch32v30x_usb.h ------------------------------------------------------------*/ + + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE + #define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 +#endif + +#ifndef MAX_PACKET_SIZE + #define MAX_PACKET_SIZE 64 // maximum packet size +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_DATA2 0x07 +#define USB_PID_MDATA 0x0F +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + + +/******************************************************************************/ +/* USBHS Clock Configuration Related Macro Definition */ +#define USB_CLK_SRC 0x80000000 +#define USBHS_PLL_ALIVE 0x40000000 +#define USBHS_PLL_CKREF_MASK 0x30000000 +#define USBHS_PLL_CKREF_3M 0x00000000 +#define USBHS_PLL_CKREF_4M 0x10000000 +#define USBHS_PLL_CKREF_8M 0x20000000 +#define USBHS_PLL_CKREF_5M 0x30000000 +#define USBHS_PLL_SRC 0x08000000 +#define USBHS_PLL_SRC_PRE_MASK 0x07000000 +#define USBHS_PLL_SRC_PRE_DIV1 0x00000000 +#define USBHS_PLL_SRC_PRE_DIV2 0x01000000 +#define USBHS_PLL_SRC_PRE_DIV3 0x02000000 +#define USBHS_PLL_SRC_PRE_DIV4 0x03000000 +#define USBHS_PLL_SRC_PRE_DIV5 0x04000000 +#define USBHS_PLL_SRC_PRE_DIV6 0x05000000 +#define USBHS_PLL_SRC_PRE_DIV7 0x06000000 +#define USBHS_PLL_SRC_PRE_DIV8 0x07000000 + + +/*******************************************************************************/ +/* USBHS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBHS_UC_HOST_MODE 0x80 +#define USBHS_UC_SPEED_TYPE 0x60 +#define USBHS_UC_SPEED_LOW 0x40 +#define USBHS_UC_SPEED_FULL 0x00 +#define USBHS_UC_SPEED_HIGH 0x20 +#define USBHS_UC_DEV_PU_EN 0x10 +#define USBHS_UC_INT_BUSY 0x08 +#define USBHS_UC_RESET_SIE 0x04 +#define USBHS_UC_CLR_ALL 0x02 +#define USBHS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBHS_UIE_DEV_NAK 0x80 +#define USBHS_UIE_ISO_ACT 0x40 +#define USBHS_UIE_SETUP_ACT 0x20 +#define USBHS_UIE_FIFO_OV 0x10 +#define USBHS_UIE_SOF_ACT 0x08 +#define USBHS_UIE_SUSPEND 0x04 +#define USBHS_UIE_TRANSFER 0x02 +#define USBHS_UIE_DETECT 0x01 +#define USBHS_UIE_BUS_RST 0x01 + +/* R16_USB_DEV_AD */ +#define USBHS_MASK_USB_ADDR 0x7F + +/* R16_USB_FRAME_NO */ +#define USBHS_MICRO_FRAME_NUM 0xE000 +#define USBHS_SOF_FRAME_NUM 0x07FF + +/* R8_USB_SUSPEND */ +#define USBHS_USB_LINESTATE 0x30 +#define USBHS_USB_WAKEUP_ST 0x04 +#define USBHS_USB_SYS_MOD 0x03 + +/* R8_USB_SPEED_TYPE */ +#define USBHS_USB_SPEED_TYPE 0x03 +#define USBHS_USB_SPEED_LOW 0x02 +#define USBHS_USB_SPEED_FULL 0x00 +#define USBHS_USB_SPEED_HIGH 0x01 + +/* R8_USB_MIS_ST */ +#define USBHS_UMS_SOF_PRES 0x80 +#define USBHS_UMS_SOF_ACT 0x40 +#define USBHS_UMS_SIE_FREE 0x20 +#define USBHS_UMS_R_FIFO_RDY 0x10 +#define USBHS_UMS_BUS_RESET 0x08 +#define USBHS_UMS_SUSPEND 0x04 +#define USBHS_UMS_DEV_ATTACH 0x02 +#define USBHS_UMS_SPLIT_CAN 0x01 + +/* R8_USB_INT_FG */ +#define USBHS_UIF_ISO_ACT 0x40 +#define USBHS_UIF_SETUP_ACT 0x20 +#define USBHS_UIF_FIFO_OV 0x10 +#define USBHS_UIF_HST_SOF 0x08 +#define USBHS_UIF_SUSPEND 0x04 +#define USBHS_UIF_TRANSFER 0x02 +#define USBHS_UIF_DETECT 0x01 +#define USBHS_UIF_BUS_RST 0x01 + +/* R8_USB_INT_ST */ +#define USBHS_UIS_IS_NAK 0x80 +#define USBHS_UIS_TOG_OK 0x40 +#define USBHS_UIS_TOKEN_MASK 0x30 +#define USBHS_UIS_TOKEN_OUT 0x00 +#define USBHS_UIS_TOKEN_SOF 0x10 +#define USBHS_UIS_TOKEN_IN 0x20 +#define USBHS_UIS_TOKEN_SETUP 0x30 +#define USBHS_UIS_ENDP_MASK 0x0F +#define USBHS_UIS_H_RES_MASK 0x0F + +/* R16_USB_RX_LEN */ +#define USBHS_USB_RX_LEN 0xFFFF + +/* R32_UEP_CONFIG */ +#define USBHS_UEP15_R_EN 0x80000000 +#define USBHS_UEP14_R_EN 0x40000000 +#define USBHS_UEP13_R_EN 0x20000000 +#define USBHS_UEP12_R_EN 0x10000000 +#define USBHS_UEP11_R_EN 0x08000000 +#define USBHS_UEP10_R_EN 0x04000000 +#define USBHS_UEP9_R_EN 0x02000000 +#define USBHS_UEP8_R_EN 0x01000000 +#define USBHS_UEP7_R_EN 0x00800000 +#define USBHS_UEP6_R_EN 0x00400000 +#define USBHS_UEP5_R_EN 0x00200000 +#define USBHS_UEP4_R_EN 0x00100000 +#define USBHS_UEP3_R_EN 0x00080000 +#define USBHS_UEP2_R_EN 0x00040000 +#define USBHS_UEP1_R_EN 0x00020000 +#define USBHS_UEP0_R_EN 0x00010000 +#define USBHS_UEP15_T_EN 0x00008000 +#define USBHS_UEP14_T_EN 0x00004000 +#define USBHS_UEP13_T_EN 0x00002000 +#define USBHS_UEP12_T_EN 0x00001000 +#define USBHS_UEP11_T_EN 0x00000800 +#define USBHS_UEP10_T_EN 0x00000400 +#define USBHS_UEP9_T_EN 0x00000200 +#define USBHS_UEP8_T_EN 0x00000100 +#define USBHS_UEP7_T_EN 0x00000080 +#define USBHS_UEP6_T_EN 0x00000040 +#define USBHS_UEP5_T_EN 0x00000020 +#define USBHS_UEP4_T_EN 0x00000010 +#define USBHS_UEP3_T_EN 0x00000008 +#define USBHS_UEP2_T_EN 0x00000004 +#define USBHS_UEP1_T_EN 0x00000002 +#define USBHS_UEP0_T_EN 0x00000001 + +/* R32_UEP_TYPE */ +#define USBHS_UEP15_R_TYPE 0x80000000 +#define USBHS_UEP14_R_TYPE 0x40000000 +#define USBHS_UEP13_R_TYPE 0x20000000 +#define USBHS_UEP12_R_TYPE 0x10000000 +#define USBHS_UEP11_R_TYPE 0x08000000 +#define USBHS_UEP10_R_TYPE 0x04000000 +#define USBHS_UEP9_R_TYPE 0x02000000 +#define USBHS_UEP8_R_TYPE 0x01000000 +#define USBHS_UEP7_R_TYPE 0x00800000 +#define USBHS_UEP6_R_TYPE 0x00400000 +#define USBHS_UEP5_R_TYPE 0x00200000 +#define USBHS_UEP4_R_TYPE 0x00100000 +#define USBHS_UEP3_R_TYPE 0x00080000 +#define USBHS_UEP2_R_TYPE 0x00040000 +#define USBHS_UEP1_R_TYPE 0x00020000 +#define USBHS_UEP0_R_TYPE 0x00010000 +#define USBHS_UEP15_T_TYPE 0x00008000 +#define USBHS_UEP14_T_TYPE 0x00004000 +#define USBHS_UEP13_T_TYPE 0x00002000 +#define USBHS_UEP12_T_TYPE 0x00001000 +#define USBHS_UEP11_T_TYPE 0x00000800 +#define USBHS_UEP10_T_TYPE 0x00000400 +#define USBHS_UEP9_T_TYPE 0x00000200 +#define USBHS_UEP8_T_TYPE 0x00000100 +#define USBHS_UEP7_T_TYPE 0x00000080 +#define USBHS_UEP6_T_TYPE 0x00000040 +#define USBHS_UEP5_T_TYPE 0x00000020 +#define USBHS_UEP4_T_TYPE 0x00000010 +#define USBHS_UEP3_T_TYPE 0x00000008 +#define USBHS_UEP2_T_TYPE 0x00000004 +#define USBHS_UEP1_T_TYPE 0x00000002 +#define USBHS_UEP0_T_TYPE 0x00000001 + +/* R32_UEP_BUF_MOD */ +#define USBHS_UEP15_ISO_BUF_MOD 0x80000000 +#define USBHS_UEP14_ISO_BUF_MOD 0x40000000 +#define USBHS_UEP13_ISO_BUF_MOD 0x20000000 +#define USBHS_UEP12_ISO_BUF_MOD 0x10000000 +#define USBHS_UEP11_ISO_BUF_MOD 0x08000000 +#define USBHS_UEP10_ISO_BUF_MOD 0x04000000 +#define USBHS_UEP9_ISO_BUF_MOD 0x02000000 +#define USBHS_UEP8_ISO_BUF_MOD 0x01000000 +#define USBHS_UEP7_ISO_BUF_MOD 0x00800000 +#define USBHS_UEP6_ISO_BUF_MOD 0x00400000 +#define USBHS_UEP5_ISO_BUF_MOD 0x00200000 +#define USBHS_UEP4_ISO_BUF_MOD 0x00100000 +#define USBHS_UEP3_ISO_BUF_MOD 0x00080000 +#define USBHS_UEP2_ISO_BUF_MOD 0x00040000 +#define USBHS_UEP1_ISO_BUF_MOD 0x00020000 +#define USBHS_UEP0_ISO_BUF_MOD 0x00010000 +#define USBHS_UEP15_BUF_MOD 0x00008000 +#define USBHS_UEP14_BUF_MOD 0x00004000 +#define USBHS_UEP13_BUF_MOD 0x00002000 +#define USBHS_UEP12_BUF_MOD 0x00001000 +#define USBHS_UEP11_BUF_MOD 0x00000800 +#define USBHS_UEP10_BUF_MOD 0x00000400 +#define USBHS_UEP9_BUF_MOD 0x00000200 +#define USBHS_UEP8_BUF_MOD 0x00000100 +#define USBHS_UEP7_BUF_MOD 0x00000080 +#define USBHS_UEP6_BUF_MOD 0x00000040 +#define USBHS_UEP5_BUF_MOD 0x00000020 +#define USBHS_UEP4_BUF_MOD 0x00000010 +#define USBHS_UEP3_BUF_MOD 0x00000008 +#define USBHS_UEP2_BUF_MOD 0x00000004 +#define USBHS_UEP1_BUF_MOD 0x00000002 +#define USBHS_UEP0_BUF_MOD 0x00000001 + +/* R32_UEP0_DMA */ +#define USBHS_UEP0_DMA 0x0000FFFF + +/* R32_UEPn_TX_DMA, n=1-15 */ +#define USBHS_UEPn_TX_DMA 0x0000FFFF + +/* R32_UEPn_RX_DMA, n=1-15 */ +#define USBHS_UEPn_RX_DMA 0x0000FFFF + +/* R16_UEPn_MAX_LEN, n=0-15 */ +#define USBHS_UEPn_MAX_LEN 0x07FF + +/* R16_UEPn_T_LEN, n=0-15 */ +#define USBHS_UEPn_T_LEN 0x07FF + +/* R8_UEPn_TX_CTRL, n=0-15 */ +#define USBHS_UEP_T_TOG_AUTO 0x20 +#define USBHS_UEP_T_TOG_MASK 0x18 +#define USBHS_UEP_T_TOG_DATA0 0x00 +#define USBHS_UEP_T_TOG_DATA1 0x08 +#define USBHS_UEP_T_TOG_DATA2 0x10 +#define USBHS_UEP_T_TOG_MDATA 0x18 +#define USBHS_UEP_T_RES_MASK 0x03 +#define USBHS_UEP_T_RES_ACK 0x00 +#define USBHS_UEP_T_RES_NYET 0x01 +#define USBHS_UEP_T_RES_NAK 0x02 +#define USBHS_UEP_T_RES_STALL 0x03 + +/* R8_UEPn_TX_CTRL, n=0-15 */ +#define USBHS_UEP_R_TOG_AUTO 0x20 +#define USBHS_UEP_R_TOG_MASK 0x18 +#define USBHS_UEP_R_TOG_DATA0 0x00 +#define USBHS_UEP_R_TOG_DATA1 0x08 +#define USBHS_UEP_R_TOG_DATA2 0x10 +#define USBHS_UEP_R_TOG_MDATA 0x18 +#define USBHS_UEP_R_RES_MASK 0x03 +#define USBHS_UEP_R_RES_ACK 0x00 +#define USBHS_UEP_R_RES_NYET 0x01 +#define USBHS_UEP_R_RES_NAK 0x02 +#define USBHS_UEP_R_RES_STALL 0x03 + +/* R8_UHOST_CTRL */ +#define USBHS_UH_SOF_EN 0x80 +#define USBHS_UH_SOF_FREE 0x40 +#define USBHS_UH_PHY_SUSPENDM 0x10 +#define USBHS_UH_REMOTE_WKUP 0x08 +#define USBHS_UH_TX_BUS_RESUME 0x04 +#define USBHS_UH_TX_BUS_SUSPEND 0x02 +#define USBHS_UH_TX_BUS_RESET 0x01 + +/* R32_UH_CONFIG */ +#define USBHS_UH_EP_RX_EN 0x00040000 +#define USBHS_UH_EP_TX_EN 0x00000008 + +/* R32_UH_EP_TYPE */ +#define USBHS_UH_EP_RX_TYPE 0x00040000 +#define USBHS_UH_EP_TX_TYPE 0x00000008 + +/* R32_UH_RX_DMA */ +#define USBHS_UH_RX_DMA 0x0000FFFC + +/* R32_UH_TX_DMA */ +#define USBHS_UH_TX_DMA 0x0000FFFF + +/* R16_UH_RX_MAX_LEN */ +#define USBHS_UH_RX_MAX_LEN 0x07FF + +/* R8_UH_EP_PID */ +#define USBHS_UH_TOKEN_MASK 0xF0 +#define USBHS_UH_ENDP_MASK 0x0F + +/* R8_UH_RX_CTRL */ +#define USBHS_UH_R_DATA_NO 0x40 +#define USBHS_UH_R_TOG_AUTO 0x20 +#define USBHS_UH_R_TOG_MASK 0x18 +#define USBHS_UH_R_TOG_DATA0 0x00 +#define USBHS_UH_R_TOG_DATA1 0x08 +#define USBHS_UH_R_TOG_DATA2 0x10 +#define USBHS_UH_R_TOG_MDATA 0x18 +#define USBHS_UH_R_RES_NO 0x04 +#define USBHS_UH_R_RES_MASK 0x03 +#define USBHS_UH_R_RES_ACK 0x00 +#define USBHS_UH_R_RES_NYET 0x01 +#define USBHS_UH_R_RES_NAK 0x02 +#define USBHS_UH_R_RES_STALL 0x03 + +/* R16_UH_TX_LEN */ +#define USBHS_UH_TX_LEN 0x07FF + +/* R8_UH_TX_CTRL */ +#define USBHS_UH_T_DATA_NO 0x40 +#define USBHS_UH_T_AUTO_TOG 0x20 +#define USBHS_UH_T_TOG_MASK 0x18 +#define USBHS_UH_T_TOG_DATA0 0x00 +#define USBHS_UH_T_TOG_DATA1 0x08 +#define USBHS_UH_T_TOG_DATA2 0x10 +#define USBHS_UH_T_TOG_MDATA 0x18 +#define USBHS_UH_T_RES_NO 0x04 +#define USBHS_UH_T_RES_MASK 0x03 +#define USBHS_UH_T_RES_ACK 0x00 +#define USBHS_UH_T_RES_NYET 0x01 +#define USBHS_UH_T_RES_NAK 0x02 +#define USBHS_UH_T_RES_STALL 0x03 + +/* R16_UH_SPLIT_DATA */ +#define USBHS_UH_SPLIT_DATA 0x0FFF + +/* USBHS Registers from ch32v30x_usbhs_device.h */ + +#define USBHSD_UEP_CFG_BASE 0x40023410 +#define USBHSD_UEP_BUF_MOD_BASE 0x40023418 +#define USBHSD_UEP_RXDMA_BASE 0x40023420 +#define USBHSD_UEP_TXDMA_BASE 0x4002345C +#define USBHSD_UEP_TXLEN_BASE 0x400234DC +#define USBHSD_UEP_TXCTL_BASE 0x400234DE +#define USBHSD_UEP_TXCTL_BASE 0x400234DE +#define USBHSD_UEP_TX_EN( N ) ( (uint16_t)( 0x01 << N ) ) +#define USBHSD_UEP_RX_EN( N ) ( (uint16_t)( 0x01 << ( N + 16 ) ) ) +#define USBHSD_UEP_DOUBLE_BUF( N ) ( (uint16_t)( 0x01 << N ) ) +#define DEF_UEP_DMA_LOAD 0 /* Direct the DMA address to the data to be processed */ +#define DEF_UEP_CPY_LOAD 1 /* Use memcpy to move data to a buffer */ +#define USBHSD_UEP_RXDMA( N ) ( *((volatile uint32_t *)( USBHSD_UEP_RXDMA_BASE + ( N - 1 ) * 0x04 ) ) ) +#define USBHSD_UEP_RXBUF( N ) ( (uint8_t *)(*((volatile uint32_t *)( USBHSD_UEP_RXDMA_BASE + ( N - 1 ) * 0x04 ) ) ) + 0x20000000 ) +#define USBHSD_UEP_TXCTRL( N ) ( *((volatile uint8_t *)( USBHSD_UEP_TXCTL_BASE + ( N - 1 ) * 0x04 ) ) ) +#define USBHSD_UEP_RXCTRL( N ) ( *((volatile uint8_t *)( USBHSD_UEP_TXCTL_BASE + ( N - 1 ) * 0x04 + 1 ) ) ) +#define USBHSD_UEP_TXDMA( N ) ( *((volatile uint32_t *)( USBHSD_UEP_TXDMA_BASE + ( N - 1 ) * 0x04 ) ) ) +#define USBHSD_UEP_TXBUF( N ) ( (uint8_t *)(*((volatile uint32_t *)( USBHSD_UEP_TXDMA_BASE + ( N - 1 ) * 0x04 ) ) ) + 0x20000000 ) +#define USBHSD_UEP_TLEN( N ) ( *((volatile uint16_t *)( USBHSD_UEP_TXLEN_BASE + ( N - 1 ) * 0x04 ) ) ) + + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_1WIRE_MODE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R32_USB_OTG_CR */ +#define USBFS_CR_SESS_VTH 0x20 +#define USBFS_CR_VBUS_VTH 0x10 +#define USBFS_CR_OTG_EN 0x08 +#define USBFS_CR_IDPU 0x04 +#define USBFS_CR_CHARGE_VBUS 0x02 +#define USBFS_CR_DISCHAR_VBUS 0x01 + +/* R32_USB_OTG_SR */ +#define USBFS_SR_ID_DIG 0x08 +#define USBFS_SR_SESS_END 0x04 +#define USBFS_SR_SESS_VLD 0x02 +#define USBFS_SR_VBUS_VLD 0x01 + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. + #define DMDATA0 ((volatile uint32_t*)0xe0000380) + #define DMDATA1 ((volatile uint32_t*)0xe0000384) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000388)// Reads as 0x00000000 if debugger is attached. + +// Determination of PLL multiplication factor for non-V003 chips + #if !defined(FUNCONF_SYSTEM_CORE_CLOCK) + #define PLL_MULTIPLICATION ((uint32_t)0) + #else + #if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x_D8) + #if FUNCONF_PLL_MULTIPLIER == 2 + #define PLL_MULTIPLICATION RCC_PLLMULL2 + #elif FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3 + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4 + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5 + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6 + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7 + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8 + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9 + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10 + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11 + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12 + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13 + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14 + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15 + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16 + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18 + #else + #error "Invalid PLL multiplier" + #endif + #else + #if FUNCONF_PLL_MULTIPLIER == 3 + #define PLL_MULTIPLICATION RCC_PLLMULL3_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 4 + #define PLL_MULTIPLICATION RCC_PLLMULL4_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 5 + #define PLL_MULTIPLICATION RCC_PLLMULL5_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 6 + #define PLL_MULTIPLICATION RCC_PLLMULL6_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 7 + #define PLL_MULTIPLICATION RCC_PLLMULL7_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 8 + #define PLL_MULTIPLICATION RCC_PLLMULL8_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 9 + #define PLL_MULTIPLICATION RCC_PLLMULL9_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 10 + #define PLL_MULTIPLICATION RCC_PLLMULL10_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 11 + #define PLL_MULTIPLICATION RCC_PLLMULL11_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 12 + #define PLL_MULTIPLICATION RCC_PLLMULL12_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 13 + #define PLL_MULTIPLICATION RCC_PLLMULL13_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 14 + #define PLL_MULTIPLICATION RCC_PLLMULL14_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 15 + #define PLL_MULTIPLICATION RCC_PLLMULL15_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 16 + #define PLL_MULTIPLICATION RCC_PLLMULL16_EXTEN + #elif FUNCONF_PLL_MULTIPLIER == 18 + #define PLL_MULTIPLICATION RCC_PLLMULL18_EXTEN + #else + #error "Invalid PLL multiplier" + #endif + #endif + #endif + + + + +// Applies to all processors + + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA1 1 +#define PA2 2 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +#define PA0 0 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/ch32x00xhw.h b/inc/ch32x00xhw.h new file mode 100644 index 0000000..a89788c --- /dev/null +++ b/inc/ch32x00xhw.h @@ -0,0 +1,5002 @@ +/* This file supports the CH32V00X and CH32M00X family of chips +*/ + +#ifndef TODO_CH32X00X_H +#define TODO_CH32X00X_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ + +#if defined(CH32V005) || defined(CH32V006) || defined(CH32V007_M007) + USART2_IRQn = 39, /* USART2 global Interrupt */ + OPCM_IRQn = 40, /* OPCM global Interrupt */ +#endif +} IRQn_Type; + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS "\n\ + .align 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0\n\ + .word NMI_Handler /* NMI Handler */ \n\ + .word HardFault_Handler /* Hard Fault Handler */ \n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word SysTick_Handler /* SysTick Handler */ \n\ + .word 0\n\ + .word SW_Handler /* SW Handler */ \n\ + .word 0\n\ + .word WWDG_IRQHandler /* Window Watchdog */ \n\ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n\ + .word FLASH_IRQHandler /* Flash */ \n\ + .word RCC_IRQHandler /* RCC */ \n\ + .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ \n\ + .word AWU_IRQHandler /* AWU */ \n\ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n\ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n\ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n\ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n\ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n\ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n\ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n\ + .word ADC1_IRQHandler /* ADC1 */ \n\ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n\ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n\ + .word USART1_IRQHandler /* USART1 */ \n\ + .word SPI1_IRQHandler /* SPI1 */ \n\ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n\ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n\ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n\ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n\ + .word TIM2_IRQHandler /* TIM2 */ \n\ + .option pop;\n" + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint32_t CNT; + uint32_t RESERVED0; + __IO uint32_t CMP; + uint32_t RESERVED1; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +// Datasheet recommends HSE of 24M +#ifndef HSE_VALUE +#define HSE_VALUE 24000000 +#endif + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CTLR3; + __IO uint32_t WDTR1; + __IO uint32_t WDTR2; +} ADC_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +typedef struct +{ + __IO uint16_t FLACAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UNIID1; + __IO uint32_t UNIID2; + __IO uint32_t UNIID3; +} ESIG_TypeDef; + +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct + { + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; + + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_MASK = 0b1111, + + GPIO_CFGLR_IN_ANALOG = 0b0000, + GPIO_CFGLR_IN_FLOAT = 0b0100, + GPIO_CFGLR_IN_PUPD = 0b1000, + GPIO_CFGLR_RES1 = 0b1100, + GPIO_CFGLR_OUT_PP = 0b0001, + GPIO_CFGLR_OUT_OD = 0b0101, + GPIO_CFGLR_OUT_AF_PP = 0b1001, + GPIO_CFGLR_OUT_AF_OD = 0b1101, + + // For intercompatibility with 003 legacy code. + GPIO_CFGLR_OUT_10Mhz_PP = 0b0001, + GPIO_CFGLR_OUT_2Mhz_PP = 0b0001, + GPIO_CFGLR_OUT_50Mhz_PP = 0b0001, + GPIO_CFGLR_OUT_10Mhz_OD = 0b0101, + GPIO_CFGLR_OUT_2Mhz_OD = 0b0101, + GPIO_CFGLR_OUT_50Mhz_OD = 0b0101, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 0b1001, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 0b1001, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 0b1001, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 0b1101, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 0b1101, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 0b1101, +} GPIO_CFGLR_PIN_MODE_Typedef; + +/* This was correct in the 003, but the 00X have 0b0010 as a reserved bit in this field. The above enum never sets this bit as directed by the RM. But it's included in the following structure as a 4 bit field becaus changing it to two disjoint bit fields would make life too painful. */ + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; + +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + uint32_t RESERVED1; + __IO uint32_t EXTICR; + __IO uint32_t PCFR1; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; + __IO uint32_t AWUCSR; + __IO uint32_t AWUWR; + __IO uint32_t AWUPSC; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + union + { + __IO uint32_t PB2PRSTR; + __IO uint32_t APB2PRSTR; // For 003 compatibility + }; + __IO uint32_t PB1PRSTR; + union + { + __IO uint32_t HBPCENR; + __IO uint32_t AHBPCENR; // For 003 compatibility + }; + union + { + __IO uint32_t PB2PCENR; + __IO uint32_t APB2PCENR; // For 003 compatibility + }; + union + { + __IO uint32_t PB1PCENR; + __IO uint32_t APB1PCENR; // For 003 compatibility + }; + __IO uint32_t RESERVED0; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + + + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* ADTM - Advanced-Control Timer */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint16_t DMAADR; + uint16_t RESERVED15; +} ADTM_TypeDef; + +/* GPTM - General-Purpose Timer */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + uint16_t RESERVED12; + uint16_t RESERVED13; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + __IO uint16_t DTCR; + uint16_t RESERVED14; + __IO uint16_t DMACFGR; + uint16_t RESERVED15; + __IO uint16_t DMAADR; + uint16_t RESERVED16; +} GPTM_TypeDef; + +/* SLTM - Streamlined Timer */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t DMAINTENR; + uint16_t RESERVED2; + __IO uint16_t CNT; + uint16_t RESERVED3; + __IO uint16_t ATRLR; + uint16_t RESERVED4; + __IO uint16_t CH1CVR; + uint16_t RESERVED5; + __IO uint16_t CH2CVR; + uint16_t RESERVED6; + __IO uint16_t CH3CVR; + uint16_t RESERVED7; + __IO uint16_t CH4CVR; + uint16_t RESERVED8; +} SLTM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t DATAR; + __IO uint32_t BRR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t CTLR3; + __IO uint32_t GPR; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint16_t CTLR; + uint16_t RESERVED1; + __IO uint16_t CFGR; + uint16_t RESERVED2; + __IO uint16_t STATR; + uint16_t RESERVED3; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ +typedef struct +{ + __IO uint32_t CTR; +} EXTEND_TypeDef; + + + +/* Operational Amplifier and Comparator */ +typedef struct +{ + __IO uint32_t CFGR1; + __IO uint32_t CTLR1; + __IO uint32_t CFGR2; + __IO uint32_t CTLR2; + __IO uint32_t OPA_KEY; + __IO uint32_t CMP_KEY; + __IO uint32_t POLL_KEY; +} OPA_TypeDef; + + + + +#endif + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x4000) + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) + + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + +/* Peripheral declaration */ +#define TIM2 ((GPTM_TypeDef *)TIM2_BASE) +#define TIM3 ((ALTM_TypeDef *)TIM3_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((ADTM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESIG_TypeDef *)ESIG_BASE) +// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + + + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint32_t)0x00000001) /* Analog watchdog flag */ +#define ADC_EOC ((uint32_t)0x00000002) /* End of conversion */ +#define ADC_JEOC ((uint32_t)0x00000004) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint32_t)0x00000008) /* Injected channel Start flag */ +#define ADC_STRT ((uint32_t)0x00000010) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_TKENABLE ((uint32_t)0x01000000) /* TKEY module enable control */ +#define ADC_TKITUNE ((uint32_t)0x02000000) /* Touchkey current adjustment */ +#define ADC_BUFEN ((uint32_t)0x04000000) /* ADC BUF enable */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_TGREGU ((uint32_t)0x00000010) /* External trigger event of rule channel conversion */ +#define ADC_TGINJE ((uint32_t)0x00000020) /* External trigger event of injection channel conversion */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ +#define ADC_EXTSEL_TRGO_1 ((uint32_t)0x00000000) /* TRGO event of timer 1 */ +#define ADC_EXTSEL_CC1_1 ((uint32_t)0x00000000) /* CC1 event of timer 1 */ +#define ADC_EXTSEL_CC2_1 ((uint32_t)0x00000000) /* CC2 event of timer 1 */ +#define ADC_EXTSEL_TRGO_2 ((uint32_t)0x00000000) /* TRGO event of timer 2 */ +#define ADC_EXTSEL_CC1_2 ((uint32_t)0x00000000) /* CC1 event of timer 2 */ +#define ADC_EXTSEL_CC2_2 ((uint32_t)0x00000000) /* CC2 event of timer 2 */ +#define ADC_EXTSEL_OPA ((uint32_t)0x00000000) /* OPA trigger/(PD3/PC2) */ +#define ADC_EXTSEL_SWSTART ((uint32_t)0x00000000) /* SWSTART software trigger */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint32_t)0x00000FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint32_t)0x00000FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint32_t)0x00000FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint32_t)0x00000FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint32_t)0x000001FF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint32_t)0x000001FF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint32_t)0x0000FFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************* Bit definition for ADC_CTLR3 register ********************/ +#define ADC_ADC_LP ((uint32_t)0x00000001) /* ADC low power mode control bit */ +#define ADC_DUTYEN ((uint32_t)0x00000002) /* ADC clock duty cycle control bit */ +#define ADC_ADC_DRVEN ((uint32_t)0x00000004) /* Touchkey multi-mask enable */ +#define AWD_SCAN ((uint32_t)0x00000008) /* Analog watchdog scan enable */ +#define ADC_AWD0_RST_EN ((uint32_t)0x00000010) /* Analog watchdog 0 output reset enable bit */ +#define ADC_AWD1_RST_EN ((uint32_t)0x00000020) /* Analog watchdog 1 output reset enable bit */ +#define ADC_AWD2_RST_EN ((uint32_t)0x00000040) /* Analog watchdog 2 output reset enable bit */ +#define ADC_AWD0_RES ((uint32_t)0x00000100) /* Analog watchdog 0 compare result */ +#define ADC_AWD1_RES ((uint32_t)0x00000200) /* Analog watchdog 1 compare result */ +#define ADC_AWD2_RES ((uint32_t)0x00000400) /* Analog watchdog 2 compare result */ +#define ADC_DRV_OUTEN ((uint32_t)0x00FF0000) /* DRV_OUTEN[7:0] Touchkey multi-mask each channel enable */ +#define ADC_DRV_OUTEN_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DRV_OUTEN_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DRV_OUTEN_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DRV_OUTEN_3 ((uint32_t)0x00080000) /* Bit 3 */ +#define ADC_DRV_OUTEN_4 ((uint32_t)0x00100000) /* Bit 4 */ +#define ADC_DRV_OUTEN_5 ((uint32_t)0x00200000) /* Bit 5 */ +#define ADC_DRV_OUTEN_6 ((uint32_t)0x00400000) /* Bit 6 */ +#define ADC_DRV_OUTEN_7 ((uint32_t)0x00800000) /* Bit 7 */ + +/******************* Bit definition for ADC_WDTR1 register ********************/ +#define ADC_HTR1 ((uint32_t)0x0FFF0000) /* Analog watchdog high threshold setting */ +#define ADC_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog log threshold setting */ + +/******************* Bit definition for ADC_WDTR2 register ********************/ +#define ADC_HTR2 ((uint32_t)0x0FFF0000) /* Analog watchdog high threshold setting */ +#define ADC_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog log threshold setting */ + + + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint32_t)0x03) /* LATENCY[1:0] bits (Latency) */ +/* unlike all other register bit fields, this one is not defined by bits, but by values! */ +#define FLASH_ACTLR_LATENCY_0 ((uint32_t)0x00) /* Value 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint32_t)0x01) /* Value 1 */ +#define FLASH_ACTLR_LATENCY_2 ((uint32_t)0x02) /* Value 2 */ + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint32_t)0x00000001) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint32_t)0x00000010) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint32_t)0x00000020) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint32_t)0x00000040) /* FLASH wakeup flag */ +#define FLASH_STATR_TURBO ((uint32_t)0x00000080) /* TURBO mode enabled */ +#define FLASH_STATR_BOOT_AVA ((uint32_t)0x00001000) /* Initiaslizes the configuration word status */ +#define FLASH_STATR_BOOT_STATUS ((uint32_t)0x00002000) /* The source of the currently executed program */ +#define FLASH_STATR_BOOT_MODE ((uint32_t)0x00004000) /* Combined with BOOT_AVA, the switch betten user area and BOOT area can be controlled */ +#define FLASH_STATR_BOOT_LOCK ((uint32_t)0x00008000) /* BOOT lock */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OBER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) /* Wakeup interrupt enable */ +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast programming lock */ +#define FLASH_CTLR_PAGE_FTPG ((uint32_t)0x00010000) /* Fast Page Programming 256 byte */ +#define FLASH_CTLR_PAGE_FTER ((uint32_t)0x00020000) /* Fast Page Erase 256Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint32_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint32_t)0x00080000) /* Buffer Reset */ +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Fast block erase 32KB 0x08000000-0x08007FFF */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OBERR ((uint32_t)0x00000001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /* Read protection */ +#define FLASH_OBR_USER ((uint32_t)0x000000FC) /* User Option Bits */ +#define FLASH_OBR_USER_IWDG_SW ((uint32_t)0x00000004) /* WDG_SW */ +#define FLASH_OBR_USER_STANDY_RST ((uint32_t)0x00000010) /* The system is reset and controlled in standby mode */ +#define FLASH_OBR_USER_RST_MODE ((uint32_t)0x00000060) /* Reset Mode bits - Configure byte reset delay time */ +#define FLASH_OBR_USER_STATR_MODE ((uint32_t)0x00000080) /* Power-on startup mode */ +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* DATA0 of user bytes */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* DATA1 of user bytes */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Flash programming mode Key */ + +/****************** Bit definition for FLASH_MODEKEYP register ******************/ +#define FLASH_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* BOOT programming mode Key */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR1_WRPR2 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR2 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR1_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x11111111) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint32_t)0x00000001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint32_t)0x00000002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint32_t)0x00000004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint32_t)0x00000008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint32_t)0x00000010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint32_t)0x00000020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint32_t)0x00000040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint32_t)0x00000080) /* Port input data, bit 7 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint32_t)0x00000001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint32_t)0x00000002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint32_t)0x00000004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint32_t)0x00000008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint32_t)0x00000010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint32_t)0x00000020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint32_t)0x00000040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint32_t)0x00000080) /* Port output data, bit 7 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint32_t)0x00000001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint32_t)0x00000002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint32_t)0x00000004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint32_t)0x00000008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint32_t)0x00000010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint32_t)0x00000020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint32_t)0x00000040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint32_t)0x00000080) /* Port x Reset bit 7 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_RM ((uint32_t)0x00000007) /* SPI1 remapping */ +#define AFIO_PCFR1_SPI1_RM_0 ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_SPI1_RM_1 ((uint32_t)0x00000002) /* SPI1 remapping */ +#define AFIO_PCFR1_SPI1_RM_2 ((uint32_t)0x00000004) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_RM ((uint32_t)0x00000038) /* I2C1 remapping */ +#define AFIO_PCFR1_I2C1_RM_0 ((uint32_t)0x00000008) /* I2C1 remapping */ +#define AFIO_PCFR1_I2C1_RM_1 ((uint32_t)0x00000010) /* I2C1 remapping */ +#define AFIO_PCFR1_I2C1_RM_2 ((uint32_t)0x00000020) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_RM ((uint32_t)0x000003C0) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_RM_0 ((uint32_t)0x00000040) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_RM_1 ((uint32_t)0x00000080) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_RM_2 ((uint32_t)0x00000100) /* USART1 remapping */ +#define AFIO_PCFR1_USART1_RM_3 ((uint32_t)0x00000200) /* USART1 remapping */ +#define AFIO_PCFR1_TIM1_RM ((uint32_t)0x00003C00) /* TIM1_REMAP remapping */ +#define AFIO_PCFR1_TIM1_RM_0 ((uint32_t)0x00000400) /* TIM1_REMAP remapping */ +#define AFIO_PCFR1_TIM1_RM_1 ((uint32_t)0x00000800) /* TIM1_REMAP remapping */ +#define AFIO_PCFR1_TIM1_RM_2 ((uint32_t)0x00001000) /* TIM1_REMAP remapping */ +#define AFIO_PCFR1_TIM1_RM_3 ((uint32_t)0x00002000) /* TIM1_REMAP remapping */ +#define AFIO_PCFR1_TIM2_RM ((uint32_t)0x0001C000) /* TIM2_REMAP remapping */ +#define AFIO_PCFR1_TIM2_RM_0 ((uint32_t)0x00004000) /* TIM2_REMAP remapping */ +#define AFIO_PCFR1_TIM2_RM_1 ((uint32_t)0x00008000) /* TIM2_REMAP remapping */ +#define AFIO_PCFR1_TIM2_RM_2 ((uint32_t)0x00010000) /* TIM2_REMAP remapping */ +#define AFIO_PCFR1_PA12_RM ((uint32_t)0x00020000) /* PA1/2 OSC_IN/OSC_OUT remapping */ +#define AFIO_PCFR1_ADC_ETRGINJ_RM ((uint32_t)0x00040000) /* ADC external triggered injection remapping */ +#define AFIO_PCFR1_ADC_ETRGREG_RM ((uint32_t)0x00080000) /* ADC external triggered rule remapping */ +#define AFIO_PCFR1_USART2_RM ((uint32_t)0x00700000) /* USART2 remapping */ +#define AFIO_PCFR1_USART2_RM_0 ((uint32_t)0x00100000) /* USART2 remapping */ +#define AFIO_PCFR1_USART2_RM_1 ((uint32_t)0x00200000) /* USART2 remapping */ +#define AFIO_PCFR1_USART2_RM_2 ((uint32_t)0x00400000) /* USART2 remapping */ +#define AFIO_PCFR1_SWCFG ((uint32_t)0x07000000) /* SWCFG SDI or GPIO configuration (Please reconsider your design if you find yourself setting this bit) */ +#define AFIO_PCFR1_SWCFG_0 ((uint32_t)0x01000000) /* SWCFG SDI or GPIO configuration Bit 0 (Please reconsider your design if you find yourself setting this bit)*/ +#define AFIO_PCFR1_SWCFG_1 ((uint32_t)0x02000000) /* SWCFG SDI or GPIO configuration Bit 1 (Please reconsider your design if you find yourself setting this bit)*/ +#define AFIO_PCFR1_SWCFG_2 ((uint32_t)0x04000000) /* SWCFG SDI or GPIO configuration Bit 2 (Please reconsider your design if you find yourself setting this bit)*/ + +/***************** Bit definition for AFIO_EXTICR register *****************/ +#define AFIO_EXTICR_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */ +#define AFIO_EXTICR_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */ +#define AFIO_EXTICR_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */ +#define AFIO_EXTICR_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */ +#define AFIO_EXTICR_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ +#define AFIO_EXTICR_EXTI0_PD ((uint32_t)0x00000003) /* PD[0] pin */ +#define AFIO_EXTICR_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR_EXTI1_PB ((uint32_t)0x00000004) /* PB[1] pin */ +#define AFIO_EXTICR_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */ +#define AFIO_EXTICR_EXTI1_PD ((uint32_t)0x0000000C) /* PD[1] pin */ +#define AFIO_EXTICR_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR_EXTI2_PB ((uint32_t)0x00000010) /* PB[2] pin */ +#define AFIO_EXTICR_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */ +#define AFIO_EXTICR_EXTI2_PD ((uint32_t)0x00000030) /* PD[2] pin */ +#define AFIO_EXTICR_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR_EXTI3_PB ((uint32_t)0x00000040) /* PB[3] pin */ +#define AFIO_EXTICR_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */ +#define AFIO_EXTICR_EXTI3_PD ((uint32_t)0x000000C0) /* PD[3] pin */ +#define AFIO_EXTICR_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR_EXTI4_PB ((uint32_t)0x00000100) /* PB[4] pin */ +#define AFIO_EXTICR_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */ +#define AFIO_EXTICR_EXTI4_PD ((uint32_t)0x00000300) /* PD[4] pin */ +#define AFIO_EXTICR_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR_EXTI5_PB ((uint32_t)0x00000400) /* PB[5] pin */ +#define AFIO_EXTICR_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */ +#define AFIO_EXTICR_EXTI5_PD ((uint32_t)0x00000C00) /* PD[5] pin */ +#define AFIO_EXTICR_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR_EXTI6_PB ((uint32_t)0x00001000) /* PB[6] pin */ +#define AFIO_EXTICR_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */ +#define AFIO_EXTICR_EXTI6_PD ((uint32_t)0x00003000) /* PD[6] pin */ +#define AFIO_EXTICR_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR_EXTI7_PB ((uint32_t)0x00004000) /* PB[7] pin */ +#define AFIO_EXTICR_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */ +#define AFIO_EXTICR_EXTI7_PD ((uint32_t)0x0000C000) /* PD[7] pin */ + + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_PDDS ((uint32_t)0x00000002) /* Power Down Deepsleep */ +#define PWR_CTLR_LDOMODE ((uint32_t)0x0000000C) /* LDO mode setting */ +#define PWR_CTLR_PVDE ((uint32_t)0x00000010) /* Power Voltage Detector Enable */ +#define PWR_CTLR_PLS ((uint32_t)0x00000060) /* PLS[1:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define PWR_CTLR_FLASH_LP_REG ((uint32_t)0x00000200) /* FLASH low power mode config */ +#define PWR_CTLR_FLASH_LP ((uint32_t)0x00000C00) /* FLASH low power mode config */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PVD_MAX_THRESHOLD_LVL 3 + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_HSE_LP ((uint32_t)0x00100000) /* External Low Speed clock enable */ +#define RCC_SYSCM_EN ((uint32_t)0x00200000) /* Systemclock monitoring module SCM enable */ +#define RCC_HSE_SI ((uint32_t)0x00C00000) /* HSE current supply regulation value */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits ADC prscaler */ +#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_ADCPRE_2 ((uint32_t)0x00002000) /* Bit 2 */ +#define RCC_ADCPRE_3 ((uint32_t)0x00004000) /* Bit 3 */ +#define RCC_ADCPRE_4 ((uint32_t)0x00008000) /* Bit 4 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* HBCLK divided by 2 */ +/* includes 0x00000800, + 0x00001000, + 0x00001800 */ +#define RCC_ADCPRE_DIV4_1 ((uint32_t)0x00002000) /* HBCLK divided by 4 */ +#define RCC_ADCPRE_DIV8_2 ((uint32_t)0x00002800) /* HBCLK divided by 8 */ +#define RCC_ADCPRE_DIV16_2 ((uint32_t)0x00003000) /* HBCLK divided by 16 */ +#define RCC_ADCPRE_DIV32_2 ((uint32_t)0x00003800) /* HBCLK divided by 32 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* HBCLK divided by 4 */ +/* includes 0x00004800, + 0x00005000, + 0x00005800 */ +#define RCC_ADCPRE_DIV8_1 ((uint32_t)0x00006000) /* HBCLK divided by 8 */ +#define RCC_ADCPRE_DIV16_1 ((uint32_t)0x00006800) /* HBCLK divided by 16 */ +#define RCC_ADCPRE_DIV32_1 ((uint32_t)0x00007000) /* HBCLK divided by 32 */ +#define RCC_ADCPRE_DIV64_1 ((uint32_t)0x00007800) /* HBCLK divided by 64 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* HBCLK divided by 6 */ +/* includes 0x00008800, + 0x00009000, + 0x00009800 */ +#define RCC_ADCPRE_DIV12 ((uint32_t)0x0000A000) /* HBCLK divided by 12 */ +#define RCC_ADCPRE_DIV24 ((uint32_t)0x0000A800) /* HBCLK divided by 24 */ +#define RCC_ADCPRE_DIV48 ((uint32_t)0x0000B000) /* HBCLK divided by 48 */ +#define RCC_ADCPRE_DIV96 ((uint32_t)0x0000B800) /* HBCLK divided by 96 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* HBCLK divided by 8 */ +/* includes 0x0000C800, + 0x0000D000, + 0x0000D800 */ +#define RCC_ADCPRE_DIV16 ((uint32_t)0x0000E000) /* HBCLK divided by 16 */ +#define RCC_ADCPRE_DIV32 ((uint32_t)0x0000E800) /* HBCLK divided by 32 */ +#define RCC_ADCPRE_DIV64 ((uint32_t)0x0000F000) /* HBCLK divided by 64 */ +#define RCC_ADCPRE_DIV128 ((uint32_t)0x0000F800) /* HBCLK divided by 128 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +//For compatibility with the v003 +#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_CFGR0_ADC_CLK_ADJ ((uint32_t)0x10000000) /* ADC clock duty cycle adjustment */ +#define RCC_CFGR0_ADC_CLK_MODE ((uint32_t)0x80000000) /* ADC clock mode */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_SYSCLK_FAILIE ((uint32_t)0x00000200) /* SYSCLK invalid interrupt enable bit */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_PB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART2RST ((uint32_t)0x00002000) /* USART2 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_PB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000004) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface module reset */ + +/****************** Bit definition for RCC_HBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ + +/****************** Bit definition for RCC_PB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADCEN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART2EN ((uint32_t)0x00002000) /* USART2 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_PB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_SYSCLK_FAILIF ((uint32_t)0x00000100) /* System clock failure flag */ +#define RCC_ADCRSTF ((uint32_t)0x00800000) /* ADC reset flag */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_OPCMRSTF ((uint32_t)0x02000000) /* OPA_CMP reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* Externam manual reset pin flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* LSB or MSB first */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Read enable in SPI high-speed mode */ + +/******************************************************************************/ +/* TIM1 */ +/******************************************************************************/ + +/******************* Bit definition for TIM1_CTLR1 register *****************/ +#define TIM1_CTLR1_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM1_CTLR1_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM1_CTLR1_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM1_CTLR1_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM1_CTLR1_DIR ((uint16_t)0x0010) /* Direction */ +#define TIM1_CTLR1_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM1_CTLR1_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM1_CTLR1_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM1_CTLR1_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ +#define TIM1_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM1_CTLR1_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM1_CTLR1_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM1_CTLR1_CAPOV ((uint16_t)0x4000) /* Capture value mode configuration */ +#define TIM1_CTLR1_CAPLVL ((uint16_t)0x8000) /* Capture level indication enable in dual-edge capture */ + +/******************* Bit definition for TIM1_CTLR2 register *****************/ +#define TIM1_CTLR2_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM1_CTLR2_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM1_CTLR2_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ +#define TIM1_CTLR2_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM1_CTLR2_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM1_CTLR2_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM1_CTLR2_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM1_CTLR2_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM1_CTLR2_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM1_CTLR2_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM1_CTLR2_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM1_CTLR2_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM1_CTLR2_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM1_CTLR2_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM1_CTLR2_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM1_SMCFGR register ****************/ +#define TIM1_SMCFGR_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM1_SMCFGR_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM1_SMCFGR_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM1_SMCFGR_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM1_SMCFGR_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM1_SMCFGR_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM1_SMCFGR_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM1_SMCFGR_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM1_SMCFGR_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM1_SMCFGR_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM1_SMCFGR_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM1_SMCFGR_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM1_SMCFGR_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM1_SMCFGR_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM1_SMCFGR_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM1_SMCFGR_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM1_SMCFGR_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM1_SMCFGR_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM1_SMCFGR_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM1_DMAINTENR register *************/ +#define TIM1_DMAINTENR_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM1_DMAINTENR_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM1_DMAINTENR_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM1_DMAINTENR_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM1_DMAINTENR_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM1_DMAINTENR_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM1_DMAINTENR_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM1_DMAINTENR_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM1_DMAINTENR_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM1_DMAINTENR_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM1_DMAINTENR_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM1_DMAINTENR_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM1_DMAINTENR_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM1_DMAINTENR_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM1_DMAINTENR_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************* Bit definition for TIM1_INTFR register *****************/ +#define TIM1_INTFR_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM1_INTFR_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM1_INTFR_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM1_INTFR_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM1_INTFR_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM1_INTFR_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM1_INTFR_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM1_INTFR_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM1_INTFR_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM1_INTFR_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM1_INTFR_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM1_INTFR_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM1_SWEVGR register ****************/ +#define TIM1_SWEVGR_UG ((uint16_t)0x0001) /* Update Generation */ +#define TIM1_SWEVGR_CC1G ((uint16_t)0x0002) /* Capture/Compare 1 Generation */ +#define TIM1_SWEVGR_CC2G ((uint16_t)0x0004) /* Capture/Compare 2 Generation */ +#define TIM1_SWEVGR_CC3G ((uint16_t)0x0008) /* Capture/Compare 3 Generation */ +#define TIM1_SWEVGR_CC4G ((uint16_t)0x0010) /* Capture/Compare 4 Generation */ +#define TIM1_SWEVGR_COMG ((uint16_t)0x0020) /* Capture/Compare Control Update Generation */ +#define TIM1_SWEVGR_TG ((uint16_t)0x0040) /* Trigger Generation */ +#define TIM1_SWEVGR_BG ((uint16_t)0x0080) /* Break Generation */ + +/****************** Bit definition for TIM1_CHCTLR1 register ****************/ +#define TIM1_CHCTLR1_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM1_CHCTLR1_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM1_CHCTLR1_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM1_CHCTLR1_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM1_CHCTLR1_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM1_CHCTLR1_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM1_CHCTLR1_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM1_CHCTLR1_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM1_CHCTLR1_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM1_CHCTLR1_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM1_CHCTLR1_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM1_CHCTLR1_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM1_CHCTLR1_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM1_CHCTLR1_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM1_CHCTLR1_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM1_CHCTLR1_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM1_CHCTLR1_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM1_CHCTLR1_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM1_CHCTLR1_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM1_CHCTLR1_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM1_CHCTLR1_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM1_CHCTLR1_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM1_CHCTLR1_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM1_CHCTLR1_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM1_CHCTLR1_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM1_CHCTLR1_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM1_CHCTLR1_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM1_CHCTLR1_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM1_CHCTLR1_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM1_CHCTLR1_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM1_CHCTLR1_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM1_CHCTLR1_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM1_CHCTLR1_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM1_CHCTLR1_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM1_CHCTLR1_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM1_CHCTLR1_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM1_CHCTLR2 register ****************/ +#define TIM1_CHCTLR2_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM1_CHCTLR2_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM1_CHCTLR2_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM1_CHCTLR2_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM1_CHCTLR2_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM1_CHCTLR2_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM1_CHCTLR2_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM1_CHCTLR2_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM1_CHCTLR2_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM1_CHCTLR2_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM1_CHCTLR2_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM1_CHCTLR2_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM1_CHCTLR2_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM1_CHCTLR2_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM1_CHCTLR2_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM1_CHCTLR2_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM1_CHCTLR2_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM1_CHCTLR2_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM1_CHCTLR2_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM1_CHCTLR2_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM1_CHCTLR2_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM1_CHCTLR2_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM1_CHCTLR2_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM1_CHCTLR2_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM1_CHCTLR2_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM1_CHCTLR2_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM1_CHCTLR2_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM1_CHCTLR2_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM1_CHCTLR2_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM1_CHCTLR2_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM1_CHCTLR2_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM1_CHCTLR2_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM1_CHCTLR2_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM1_CHCTLR2_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM1_CHCTLR2_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM1_CHCTLR2_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM1_CCER register ******************/ +#define TIM1_CCER_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM1_CCER_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM1_CCER_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM1_CCER_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM1_CCER_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM1_CCER_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM1_CCER_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM1_CCER_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM1_CCER_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM1_CCER_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM1_CCER_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM1_CCER_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM1_CCER_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM1_CCER_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM1_CNT register *******************/ +#define TIM1_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM1_PSC register *******************/ +#define TIM1_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM1_ATRLR register *****************/ +#define TIM1_ATRLR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM1_RPTCR register *****************/ +#define TIM1_REP ((uint16_t)0x00FF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM1_CH1CVR register ****************/ +#define TIM1_CH1CVR_CH1CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 1 Value[15:0] */ +#define TIM1_CH1CVR_LEVEL1 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM1_CH2CVR register ****************/ +#define TIM1_CH2CVR_CH2CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 2 Value */ +#define TIM1_CH2CVR_LEVEL2 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM1_CH3CVR register ****************/ +#define TIM1_CH3CVR_CH3CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 3 Value */ +#define TIM1_CH3CVR_LEVEL3 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM1_CH4CVR register ****************/ +#define TIM1_CH4CVR_CH4CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 4 Value */ +#define TIM1_CH4CVR_LEVEL4 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM1_BDTR register ******************/ +#define TIM1_BDTR_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM1_BDTR_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM1_BDTR_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM1_BDTR_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM1_BDTR_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM1_BDTR_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM1_BDTR_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM1_BDTR_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM1_BDTR_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM1_BDTR_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM1_BDTR_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM1_BDTR_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM1_BDTR_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM1_BDTR_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM1_BDTR_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM1_BDTR_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM1_BDTR_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM1_BDTR_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM1_DMACFGR register ***************/ +#define TIM1_DMACFGR_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM1_DMACFGR_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM1_DMACFGR_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM1_DMACFGR_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM1_DMACFGR_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM1_DMACFGR_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM1_DMACFGR_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM1_DMACFGR_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM1_DMACFGR_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM1_DMACFGR_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM1_DMACFGR_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM1_DMACFGR_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM1_DMAADR register ****************/ +#define TIM1_DMAADR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* TIM2 */ +/******************************************************************************/ + +/******************* Bit definition for TIM2_CTLR1 register *****************/ +#define TIM2_CTLR1_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM2_CTLR1_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM2_CTLR1_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM2_CTLR1_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM2_CTLR1_DIR ((uint16_t)0x0010) /* Direction */ +#define TIM2_CTLR1_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM2_CTLR1_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM2_CTLR1_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM2_CTLR1_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ +#define TIM2_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM2_CTLR1_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_CTLR1_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM2_CTLR1_CAPOV ((uint16_t)0x4000) /* Capture value mode configuration */ +#define TIM2_CTLR1_CAPLVL ((uint16_t)0x8000) /* Capture level indication enable in dual-edge capture */ + +/******************* Bit definition for TIM2_CTLR2 register *****************/ +#define TIM2_CTLR2_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ +#define TIM2_CTLR2_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM2_CTLR2_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM2_CTLR2_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM2_CTLR2_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM2_CTLR2_TI1S ((uint16_t)0x0080) /* TI1 Selection */ + +/******************* Bit definition for TIM2_SMCFGR register ****************/ +#define TIM2_SMCFGR_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM2_SMCFGR_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM2_SMCFGR_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM2_SMCFGR_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM2_SMCFGR_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM2_SMCFGR_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM2_SMCFGR_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM2_SMCFGR_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM2_SMCFGR_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM2_SMCFGR_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM2_SMCFGR_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_SMCFGR_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM2_SMCFGR_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM2_SMCFGR_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM2_SMCFGR_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM2_SMCFGR_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM2_SMCFGR_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM2_SMCFGR_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM2_SMCFGR_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM2_DMAINTENR register *************/ +#define TIM2_DMAINTENR_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM2_DMAINTENR_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM2_DMAINTENR_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM2_DMAINTENR_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM2_DMAINTENR_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM2_DMAINTENR_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM2_DMAINTENR_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM2_DMAINTENR_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM2_DMAINTENR_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM2_DMAINTENR_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM2_DMAINTENR_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM2_DMAINTENR_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************* Bit definition for TIM2_INTFR register *****************/ +#define TIM2_INTFR_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM2_INTFR_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM2_INTFR_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM2_INTFR_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM2_INTFR_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM2_INTFR_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM2_INTFR_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM2_INTFR_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM2_INTFR_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM2_INTFR_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM2_SWEVGR register ****************/ +#define TIM2_SWEVGR_UG ((uint16_t)0x0001) /* Update Generation */ +#define TIM2_SWEVGR_CC1G ((uint16_t)0x0002) /* Capture/Compare 1 Generation */ +#define TIM2_SWEVGR_CC2G ((uint16_t)0x0004) /* Capture/Compare 2 Generation */ +#define TIM2_SWEVGR_CC3G ((uint16_t)0x0008) /* Capture/Compare 3 Generation */ +#define TIM2_SWEVGR_CC4G ((uint16_t)0x0010) /* Capture/Compare 4 Generation */ +#define TIM2_SWEVGR_TG ((uint16_t)0x0040) /* Trigger Generation */ + +/****************** Bit definition for TIM2_CHCTLR1 register ****************/ +#define TIM2_CHCTLR1_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM2_CHCTLR1_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM2_CHCTLR1_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM2_CHCTLR1_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM2_CHCTLR1_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM2_CHCTLR1_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM2_CHCTLR1_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM2_CHCTLR1_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM2_CHCTLR1_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM2_CHCTLR1_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM2_CHCTLR1_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM2_CHCTLR1_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_CHCTLR1_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM2_CHCTLR1_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM2_CHCTLR1_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM2_CHCTLR1_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM2_CHCTLR1_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM2_CHCTLR1_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM2_CHCTLR1_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM2_CHCTLR1_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM2_CHCTLR1_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM2_CHCTLR1_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM2_CHCTLR1_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM2_CHCTLR1_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM2_CHCTLR1_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM2_CHCTLR1_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM2_CHCTLR1_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM2_CHCTLR1_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM2_CHCTLR1_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM2_CHCTLR1_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM2_CHCTLR1_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM2_CHCTLR1_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM2_CHCTLR1_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM2_CHCTLR1_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM2_CHCTLR1_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM2_CHCTLR1_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM2_CHCTLR2 register ****************/ +#define TIM2_CHCTLR2_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM2_CHCTLR2_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM2_CHCTLR2_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM2_CHCTLR2_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM2_CHCTLR2_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM2_CHCTLR2_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM2_CHCTLR2_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM2_CHCTLR2_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM2_CHCTLR2_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM2_CHCTLR2_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM2_CHCTLR2_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM2_CHCTLR2_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_CHCTLR2_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM2_CHCTLR2_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM2_CHCTLR2_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM2_CHCTLR2_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM2_CHCTLR2_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM2_CHCTLR2_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM2_CHCTLR2_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM2_CHCTLR2_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM2_CHCTLR2_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM2_CHCTLR2_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM2_CHCTLR2_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM2_CHCTLR2_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM2_CHCTLR2_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM2_CHCTLR2_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM2_CHCTLR2_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM2_CHCTLR2_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM2_CHCTLR2_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM2_CHCTLR2_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM2_CHCTLR2_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM2_CHCTLR2_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM2_CHCTLR2_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM2_CHCTLR2_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM2_CHCTLR2_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM2_CHCTLR2_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM2_CCER register ******************/ +#define TIM2_CCER_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM2_CCER_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM2_CCER_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM2_CCER_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM2_CCER_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM2_CCER_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM2_CCER_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM2_CCER_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM2_CNT register *******************/ +#define TIM2_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM2_PSC register *******************/ +#define TIM2_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM2_ATRLR register *****************/ +#define TIM2_ATRLR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM2_CH1CVR register ****************/ +#define TIM2_CH1CVR_CH1CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 1 Value[15:0] */ +#define TIM2_CH1CVR_LEVEL1 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM2_CH2CVR register ****************/ +#define TIM2_CH2CVR_CH2CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 2 Value */ +#define TIM2_CH2CVR_LEVEL2 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM2_CH3CVR register ****************/ +#define TIM2_CH3CVR_CH3CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 3 Value */ +#define TIM2_CH3CVR_LEVEL3 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM2_CH4CVR register ****************/ +#define TIM2_CH4CVR_CH4CVR ((uint32_t)0x0000FFFF) /* Capture/Compare 4 Value */ +#define TIM2_CH4CVR_LEVEL4 ((uint32_t)0x00010000) /* The level indication bit corresponding to the captured value */ + +/******************* Bit definition for TIM2_DTCR register ******************/ +#define TIM2_DTCR_OC1N_EN ((uint16_t)0x0001) /* Complementary output CH1 EN */ +#define TIM2_DTCR_OC2N_EN ((uint16_t)0x0002) /* Complementary output CH2 EN */ +#define TIM2_DTCR_DT1_P ((uint16_t)0x0004) /* Complementary output CH1 POL */ +#define TIM2_DTCR_DT1N_P ((uint16_t)0x0008) /* Complementary output CH1 compliment POL */ +#define TIM2_DTCR_DT2_P ((uint16_t)0x0010) /* Complementary output CH2 POL */ +#define TIM2_DTCR_DT2N_P ((uint16_t)0x0020) /* Complementary output CH2 compliment POL */ + +#define TIM2_DTCR_DT1 ((uint16_t)0x0F00) /* DT1[3:0] bits (Dead-Time Generator set-up) */ +#define TIM2_DTCR_DT1_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_DTCR_DT1_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM2_DTCR_DT1_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM2_DTCR_DT1_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM2_DTCR_DT2 ((uint16_t)0x0F00) /* DT2[3:0] bits (Dead-Time Generator set-up) */ +#define TIM2_DTCR_DT2_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_DTCR_DT2_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM2_DTCR_DT2_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM2_DTCR_DT2_3 ((uint16_t)0x0800) /* Bit 3 */ + +/******************* Bit definition for TIM2_DMACFGR register ***************/ +#define TIM2_DMACFGR_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM2_DMACFGR_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM2_DMACFGR_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM2_DMACFGR_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM2_DMACFGR_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM2_DMACFGR_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM2_DMACFGR_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM2_DMACFGR_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM2_DMACFGR_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM2_DMACFGR_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM2_DMACFGR_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM2_DMACFGR_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM2_DMAADR register ****************/ +#define TIM2_DMAADR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* TIM3 */ +/******************************************************************************/ + +/******************* Bit definition for TIM3_CTLR register ******************/ +#define TIM3_CTLR_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM3_CTLR_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM3_CTLR_DIR ((uint16_t)0x0010) /* Direction */ +#define TIM3_CTLR_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM3_CTLR_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM3_CTLR_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM3_CTLR_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM3_CTLR_SMS ((uint16_t)0x0700) /* SMS[2:0] bits clock source */ +#define TIM3_CTLR_SMS_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM3_CTLR_SMS_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM3_CTLR_SMS_2 ((uint16_t)0x0400) /* Bit 2 */ + +/******************* Bit definition for TIM3_DMAINTENR register *************/ +#define TIM3_DMAINTENR_OC1PE ((uint16_t)0x0001) /* Compare 1 preload enable */ +#define TIM3_DMAINTENR_OC2PE ((uint16_t)0x0002) /* Compare 2 preload enable */ +#define TIM3_DMAINTENR_OC3PE ((uint16_t)0x0004) /* Compare 3 preload enable */ +#define TIM3_DMAINTENR_OC4PE ((uint16_t)0x0008) /* Compare 4 preload enable */ +#define TIM3_DMAINTENR_CC3DE ((uint16_t)0x0800) /* Compare 3 DMA request enable */ +#define TIM3_DMAINTENR_CC4DE ((uint16_t)0x1000) /* Compare 4 DMA request enable */ + +/******************* Bit definition for TIM3_CNT register *******************/ +#define TIM3_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM3_ATRLR register *****************/ +#define TIM3_ATRLR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM3_CH1CVR register ****************/ +#define TIM3_CH1CVR_CH1CVR ((uint16_t)0xFFFF) /* Compare 1 Value[15:0] */ + +/******************* Bit definition for TIM3_CH2CVR register ****************/ +#define TIM3_CH2CVR_CH2CVR ((uint16_t)0xFFFF) /* Compare 2 Value */ + +/******************* Bit definition for TIM3_CH3CVR register ****************/ +#define TIM3_CH3CVR_CH3CVR ((uint16_t)0xFFFF) /* Compare 3 Value */ + +/******************* Bit definition for TIM3_CH4CVR register ****************/ +#define TIM3_CH4CVR_CH4CVR ((uint16_t)0xFFFF) /* Compare 4 Value */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register ****************/ +#define USART_STATR_PE ((uint32_t)0x00000001) /* Parity Error */ +#define USART_STATR_FE ((uint32_t)0x00000002) /* Framing Error */ +#define USART_STATR_NE ((uint32_t)0x00000004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint32_t)0x00000008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint32_t)0x00000010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint32_t)0x00000020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint32_t)0x00000040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint32_t)0x00000080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint32_t)0x00000100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint32_t)0x00000200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register ****************/ +#define USART_DATAR_DR ((uint32_t)0x000001FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *****************/ +#define USART_CTLR1_SBK ((uint32_t)0x00000001) /* Send Break */ +#define USART_CTLR1_RWU ((uint32_t)0x00000002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint32_t)0x00000004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint32_t)0x00000008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint32_t)0x00000010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint32_t)0x00000020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint32_t)0x00000040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint32_t)0x00000080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint32_t)0x00000100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint32_t)0x00000200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint32_t)0x00000400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint32_t)0x00000800) /* Wakeup method */ +#define USART_CTLR1_M ((uint32_t)0x00001000) /* Word length */ +#define USART_CTLR1_UE ((uint32_t)0x00002000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *****************/ +#define USART_CTLR2_ADD ((uint32_t)0x0000000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint32_t)0x00000020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint32_t)0x00000040) /* LIN Break Detection Interrupt Enable */ + +#define USART_CTLR2_STOP ((uint32_t)0x00003000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint32_t)0x00004000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *****************/ +#define USART_CTLR3_EIE ((uint32_t)0x00000001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint32_t)0x00000002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint32_t)0x00000004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint32_t)0x00000008) /* Half-Duplex Selection */ +#define USART_CTLR3_DMAR ((uint32_t)0x00000040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint32_t)0x00000080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint32_t)0x00000100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint32_t)0x00000200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint32_t)0x00000400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint32_t)0x000000FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint32_t)0x00000010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint32_t)0x00000020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint32_t)0x00000040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint32_t)0x00000080) /* Bit 7 */ + + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ******************/ +#define WWDG_CTLR_T ((uint16_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint16_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint16_t)0x0080) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register ******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint16_t)0x0001) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* Extended Configuration */ +/******************************************************************************/ + +/**************************** EXTEN_CTR *************************************/ +#define EXTEN_LKUPEN ((uint32_t)0x00000040) /* LOCKUP monitoring function enable */ +#define EXTEN_LKUPRST ((uint32_t)0x00000080) /* LOCKUP reset flag */ +#define EXTEN_LDOTRIM ((uint32_t)0x00000400) /* Core voltage modes */ +#define EXTEN_TIM2_DMA_REMAP ((uint32_t)0x00010000) /* DMA alternate of TIM2 */ + +/******************************************************************************/ +/* Operational Amplifier and Comparator */ +/******************************************************************************/ + +/******************** Bit definition for OPA_CFGR1 register ********************/ +#define OPA_CFGR1_POLL_EN ((uint32_t)0x00000001) /* */ +#define OPA_CFGR1_POLL1_NUM ((uint32_t)0x0000000C) /* */ +#define OPA_CFGR1_POLL1_NUM_0 ((uint32_t)0x00000004) /* */ +#define OPA_CFGR1_POLL1_NUM_1 ((uint32_t)0x00000008) /* */ +#define OPA_CFGR1_RST_EN1 ((uint32_t)0x00000010) /* */ +#define OPA_CFGR1_SETUP_CFG ((uint32_t)0x00000060) /* */ +#define OPA_CFGR1_SETUP_CFG_0 ((uint32_t)0x00000020) /* */ +#define OPA_CFGR1_SETUP_CFG_1 ((uint32_t)0x00000040) /* */ +#define OPA_CFGR1_AUTO_ADC_CFG ((uint32_t)0x00000080) /* */ +#define OPA_CFGR1_IE_OUT1 ((uint32_t)0x00000100) /* */ +#define OPA_CFGR1_NMI_EN ((uint32_t)0x00000400) /* */ +#define OPA_CFGR1_IF_OUT_POLL_CH1 ((uint32_t)0x00001000) /* */ +#define OPA_CFGR1_IF_OUT_POLL_CH2 ((uint32_t)0x00002000) /* */ +#define OPA_CFGR1_IF_OUT_POLL_CH3 ((uint32_t)0x00004000) /* */ +#define OPA_CFGR1_POLL_CH1 ((uint32_t)0x00030000) /* */ +#define OPA_CFGR1_POLL_CH1_0 ((uint32_t)0x00010000) /* */ +#define OPA_CFGR1_POLL_CH1_1 ((uint32_t)0x00020000) /* */ +#define OPA_CFGR1_POLL_CH2 ((uint32_t)0x000C0000) /* */ +#define OPA_CFGR1_POLL_CH2_0 ((uint32_t)0x00040000) /* */ +#define OPA_CFGR1_POLL_CH2_1 ((uint32_t)0x00080000) /* */ +#define OPA_CFGR1_POLL_CH3 ((uint32_t)0x00300000) /* */ +#define OPA_CFGR1_POLL_CH3_0 ((uint32_t)0x00100000) /* */ +#define OPA_CFGR1_POLL_CH3_1 ((uint32_t)0x00200000) /* */ +#define OPA_CFGR1_POLL_SWSTRT ((uint32_t)0x01000000) /* */ +#define OPA_CFGR1_POLL_SEL ((uint32_t)0x0E000000) /* */ +#define OPA_CFGR1_POLL_SEL_1 ((uint32_t)0x02000000) /* */ +#define OPA_CFGR1_POLL_SEL_2 ((uint32_t)0x04000000) /* */ +#define OPA_CFGR1_POLL_SEL_3 ((uint32_t)0x08000000) /* */ +#define OPA_CFGR1_POLL_LOCK ((uint32_t)0x80000000) /* */ + +/******************* Bit definition for OPA_CTLR1 register ********************/ +#define OPA_CTLR1_OPA_EN1 ((uint32_t)0x00000001) /* */ +#define OPA_CTLR1_MODE1 ((uint32_t)0x00000006) /* */ +#define OPA_CTLR1_MODE1_0 ((uint32_t)0x00000002) /* */ +#define OPA_CTLR1_MODE1_1 ((uint32_t)0x00000004) /* */ +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000030) /* */ +#define OPA_CTLR1_PSEL1_0 ((uint32_t)0x00000010) /* */ +#define OPA_CTLR1_PSEL1_1 ((uint32_t)0x00000020) /* */ +#define OPA_CTLR1_PSEL1_CHP0 ((uint32_t)0x00000000) /* */ +#define OPA_CTLR1_PSEL1_CHP1 ((uint32_t)0x00000010) /* */ +#define OPA_CTLR1_PSEL1_CHP2 ((uint32_t)0x00000020) /* */ +#define OPA_CTLR1_PSEL1_CHP3 ((uint32_t)0x00000030) /* */ +#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000700) /* */ +#define OPA_CTLR1_NSEL1_0 ((uint32_t)0x00000100) /* */ +#define OPA_CTLR1_NSEL1_1 ((uint32_t)0x00000200) /* */ +#define OPA_CTLR1_NSEL1_2 ((uint32_t)0x00000400) /* */ +#define OPA_CTLR1_NSEL1_CHN0 ((uint32_t)0x00000000) /* */ +#define OPA_CTLR1_NSEL1_CHN1 ((uint32_t)0x00000100) /* */ +#define OPA_CTLR1_NSEL1_PGA4 ((uint32_t)0x00000300) /* */ +#define OPA_CTLR1_NSEL1_PGA8 ((uint32_t)0x00000400) /* */ +#define OPA_CTLR1_NSEL1_PGA16 ((uint32_t)0x00000500) /* */ +#define OPA_CTLR1_NSEL1_PGA32 ((uint32_t)0x00000600) /* */ +#define OPA_CTLR1_FB_EN1 ((uint32_t)0x00000800) /* */ +#define OPA_CTLR1_PGADIF ((uint32_t)0x00001000) /* */ +#define OPA_CTLR1_VBEN ((uint32_t)0x00010000) /* */ +#define OPA_CTLR1_VBSEL ((uint32_t)0x00020000) /* */ +#define OPA_CTLR1_VBCMPSEL ((uint32_t)0x000C0000) /* */ +#define OPA_CTLR1_VBCMPSEL_0 ((uint32_t)0x00040000) /* */ +#define OPA_CTLR1_VBCMPSEL_1 ((uint32_t)0x00080000) /* */ +#define OPA_CTLR1_OPA_HS1 ((uint32_t)0x00100000) /* */ +#define OPA_CTLR1_OPA_LOCK ((uint32_t)0x80000000) /* */ + +/******************** Bit definition for OPA_CFGR2 register ********************/ +#define OPA_CFGR2_POLL_EN1 ((uint32_t)0x00000001) /* */ +#define OPA_CFGR2_POLL1_NUM ((uint32_t)0x0000000C) /* */ +#define OPA_CFGR2_POLL1_NUM_0 ((uint32_t)0x00000004) /* */ +#define OPA_CFGR2_POLL1_NUM_1 ((uint32_t)0x00000008) /* */ +#define OPA_CFGR2_RST_EN1 ((uint32_t)0x00000010) /* */ +#define OPA_CFGR2_RST_EN2 ((uint32_t)0x00000020) /* */ +#define OPA_CFGR2_IE_OUT1 ((uint32_t)0x00000100) /* */ +#define OPA_CFGR2_IE_CNT ((uint32_t)0x00000200) /* */ +#define OPA_CFGR2_IF_OUT_POLL_CH1 ((uint32_t)0x00001000) /* */ +#define OPA_CFGR2_IF_OUT_POLL_CH2 ((uint32_t)0x00002000) /* */ +#define OPA_CFGR2_IF_OUT_POLL_CH3 ((uint32_t)0x00004000) /* */ +#define OPA_CFGR2_IF_CNT ((uint32_t)0x00008000) /* */ +#define OPA_CFGR2_POLL_VLU ((uint32_t)0x01FF0000) /* */ +#define OPA_CFGR2_POLL_CH1 ((uint32_t)0x0C000000) /* */ +#define OPA_CFGR2_POLL_CH1_0 ((uint32_t)0x02000000) /* */ +#define OPA_CFGR2_POLL_CH1_1 ((uint32_t)0x04000000) /* */ +#define OPA_CFGR2_POLL_CH2 ((uint32_t)0x18000000) /* */ +#define OPA_CFGR2_POLL_CH2_0 ((uint32_t)0x08000000) /* */ +#define OPA_CFGR2_POLL_CH2_1 ((uint32_t)0x10000000) /* */ +#define OPA_CFGR2_POLL_CH3 ((uint32_t)0xC0000000) /* */ +#define OPA_CFGR2_POLL_CH3_0 ((uint32_t)0x20000000) /* */ +#define OPA_CFGR2_POLL_CH3_1 ((uint32_t)0x40000000) /* */ + +/******************** Bit definition for OPA_CTRL2 register ********************/ +#define OPA_CTRL2_CMP_EN1 ((uint32_t)0x00000001) /* */ +#define OPA_CTRL2_MODE1 ((uint32_t)0x00000006) /* */ +#define OPA_CTRL2_MODE1_0 ((uint32_t)0x00000002) /* */ +#define OPA_CTRL2_MODE1_1 ((uint32_t)0x00000004) /* */ +#define OPA_CTRL2_NSEL1 ((uint32_t)0x00000018) /* */ +#define OPA_CTRL2_NSEL1_0 ((uint32_t)0x00000008) /* */ +#define OPA_CTRL2_NSEL1_1 ((uint32_t)0x00000010) /* */ +#define OPA_CTRL2_NSEL1_CHN0 ((uint32_t)0x00000000) /* */ +#define OPA_CTRL2_NSEL1_CHN1 ((uint32_t)0x00000008) /* */ +#define OPA_CTRL2_NSEL1_CHN2 ((uint32_t)0x00000010) /* */ +#define OPA_CTRL2_PSEL1 ((uint32_t)0x00000060) /* */ +#define OPA_CTRL2_PSEL1_0 ((uint32_t)0x00000020) /* */ +#define OPA_CTRL2_PSEL1_1 ((uint32_t)0x00000040) /* */ +#define OPA_CTRL2_PSEL1_CHP0 ((uint32_t)0x00000000) /* */ +#define OPA_CTRL2_PSEL1_CHP1 ((uint32_t)0x00000020) /* */ +#define OPA_CTRL2_PSEL1_CHP2 ((uint32_t)0x00000040) /* */ +#define OPA_CTRL2_HYEN1 ((uint32_t)0x00000080) /* */ +#define OPA_CTRL2_RMID1 ((uint32_t)0x00000100) /* */ +#define OPA_CTRL2_CMP_EN2 ((uint32_t)0x00010000) /* */ +#define OPA_CTRL2_FILT_EN ((uint32_t)0x01000000) /* */ +#define OPA_CTRL2_FILT_SEL ((uint32_t)0x02000000) /* */ +#define OPA_CTRL2_BKIN_CFG ((uint32_t)0x0C000000) /* */ +#define OPA_CTRL2_BKIN_CFG_0 ((uint32_t)0x04000000) /* */ +#define OPA_CTRL2_BKIN_CFG_1 ((uint32_t)0x08000000) /* */ +#define OPA_CTRL2_BKIN_CFG_IO ((uint32_t)0x00000000) /* */ +#define OPA_CTRL2_BKIN_CFG_CMP1 ((uint32_t)0x04000000) /* */ +#define OPA_CTRL2_BKIN_CFG_CMP2 ((uint32_t)0x08000000) /* */ +#define OPA_CTRL2_BKIN_CFG_OPA ((uint32_t)0x0C000000) /* */ +#define OPA_CTRL2_CMP_LOCK ((uint32_t)0x80000000) /* */ + +/******************* Bit definition for OPA_KEY register ********************/ +/******************* Bit definition for CMP_KEY register ********************/ +/******************* Bit definition for POLL_KEY register *******************/ +#define OPA_KEY1 ((uint32_t)0x45670123) /* */ +#define OPA_KEY2 ((uint32_t)0xCDEF89AB) /* */ + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* ch32v00x_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32v00x_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +///* CTLR1 register Mask */ +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + + + + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32v00x_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + + +/* DMA2 FLAG mask */ +// Editor's note: Overloaded Definition. +#define DMA2_FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32v00x_flash.c ----------------------------------------------------------*/ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) + + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + + +/* ch32v00x_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +////* I2C registers Masks */ +// Editor's note: Overloaded Definition. +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +//Editor's Note: Overloaded Definition +#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + + +/* ch32v00x_pwr.c ------------------------------------------------------------*/ + + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/* ch32v00x_rcc.c ------------------------------------------------------------*/ + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + + +/* RCC Flag Mask */ +//Editor's Note: Overloaded Definition +#define RCC_FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +#ifndef __ASSEMBLER__ +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; +static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; +#endif + + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32v00x_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + + +/* ch32v00x_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ + +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) +#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) + + +/* ADC_sampling_time */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_9Cycles ((uint8_t)0x01) +#define ADC_SampleTime_15Cycles ((uint8_t)0x02) +#define ADC_SampleTime_30Cycles ((uint8_t)0x03) +#define ADC_SampleTime_43Cycles ((uint8_t)0x04) +#define ADC_SampleTime_57Cycles ((uint8_t)0x05) +#define ADC_SampleTime_73Cycles ((uint8_t)0x06) +#define ADC_SampleTime_241Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_calibration_voltage_definition */ +#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) +#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) + +/* ADC_external_trigger_sources_delay_channels_definition */ +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000) + + + + +/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ + +/* DBGMCU_CR Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) + +/* ch32v00x_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ + +/* ch32v00x_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +} FLASH_Status; +#endif + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + + +/* Values to be used with CH32V00x devices (1page = 64Byte) */ +#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ +#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ +#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ +#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ +#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ +#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ +#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ +#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ +#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ +#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ +#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ +#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ +#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ +#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ +#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ +#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ + + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ +#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ +#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */ + +#define OB_STARTMODE_BOOT ((uint16_t)0x0020) /* Start in BOOT area */ +#define OB_STARTMODE_USER ((uint16_t)0x0000) /* Start in user area */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ +#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) + + +/* ch32v00x_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +/* ch32v00x_misc.h -----------------------------------------------------------*/ + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + +/* ch32v00x_opa.h ------------------------------------------------------------*/ + +/* Editor's note: I don't know if this is actually useful */ +#ifndef __ASSEMBLER__ + + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; + + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ +} OPA_InitTypeDef; + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif + +/* ch32v00x_pwr.h ------------------------------------------------------------*/ + + +/* PVD_detection_level */ + +#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) +#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) +#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) + +/* PWR_AWU_Prescaler */ +#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) +#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) +#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) +#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) +#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) +#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) +#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) +#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) +#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) +#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) + +/* STOP_mode_entry */ +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + + +/* ch32v00x_rcc.h ------------------------------------------------------------*/ + + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) + + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifdef CH32V30x_D8C +#define RCC_IT_PLL2RDY ((uint8_t)0x20) +#define RCC_IT_PLL3RDY ((uint8_t)0x40) +#endif + + + + + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) +#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) +#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) +#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) +#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) +#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) +#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) +#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) + + + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART2 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000004) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + + + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +#ifdef CH32V30x_D8C +#define RCC_MCO_PLL2CLK ((uint8_t)0x08) +#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) +#define RCC_MCO_XT1 ((uint8_t)0x0A) +#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) +#endif + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifdef CH32V30x_D8C +#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) +#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) +#endif + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RNG_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) +#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) +#endif + +/* ETH1G_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) +#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) +#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) +#endif + + + + + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +// While not truly CH32X035, we can re-use some of the USB register defs. + +/* ch32v30x_usb.h ------------------------------------------------------------*/ + + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. +#ifndef MINICHLINK + #define DMDATA0 ((volatile uint32_t*)0xe00000f4) + #define DMDATA1 ((volatile uint32_t*)0xe00000f8) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe00000fc) // Reads as 0x00000000 if debugger is attached. +#endif + +// Determination of PLL multiplication factor for non-V003 chips + + + +// xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering. + +/* +Encoder for some of the proprietary 'XW' RISC-V instructions present on the QingKe RV32 processor. +Examples: + XW_C_LBU(a3, a1, 27); // c.xw.lbu a3, 27(a1) + XW_C_SB(a0, s0, 13); // c.xw.sb a0, 13(s0) + + XW_C_LHU(a5, a5, 38); // c.xw.lhu a5, 38(a5) + XW_C_SH(a2, s1, 14); // c.xw.sh a2, 14(s1) +*/ + +// Let us do some compile-time error checking. +#define ASM_ASSERT(COND) .if (!(COND)); .err; .endif + +// Integer encodings of the possible compressed registers. +#define C_s0 0 +#define C_s1 1 +#define C_a0 2 +#define C_a1 3 +#define C_a2 4 +#define C_a3 5 +#define C_a4 6 +#define C_a5 7 + +// register to encoding +#define REG2I(X) (C_ ## X) + +// XW opcodes +#define XW_OP_LBUSP 0b1000000000000000 +#define XW_OP_STSP 0b1000000001000000 + +#define XW_OP_LHUSP 0b1000000000100000 +#define XW_OP_SHSP 0b1000000001100000 + +#define XW_OP_LBU 0b0010000000000000 +#define XW_OP_SB 0b1010000000000000 + +#define XW_OP_LHU 0b0010000000000010 +#define XW_OP_SH 0b1010000000000010 + +// The two different XW encodings supported at the moment. +#define XW_ENCODE1(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ + (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3))) + +#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ + (((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2)) + +// Compressed load byte, zero-extend result +#define XW_C_LBU(RD, RS, IMM) XW_ENCODE1(XW_OP_LBU, RD, RS, IMM) + +// Compressed store byte +#define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM) + +// Compressed load half, zero-extend result +#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1))) + +// Compressed store half +#define XW_C_SH(RS1, RS2, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1))) + + + +// Applies to all processors + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +// There is not PB7 in V006 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/ch32x03xhw.h b/inc/ch32x03xhw.h new file mode 100644 index 0000000..42e7cd7 --- /dev/null +++ b/inc/ch32x03xhw.h @@ -0,0 +1,6245 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ + USART2_IRQn = 39, /* UART2 Interrupt */ + EXTI15_8_IRQn = 40, /* External Line[8:15] Interrupt */ + EXTI25_16_IRQn = 41, /* External Line[25:16] Interrupt */ + USART3_IRQn = 42, /* UART2 Interrupt */ + USART4_IRQn = 43, /* UART2 Interrupt */ + DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ + USBFS_IRQn = 45, /* USB Full-Speed Interrupt */ + USBFS_WakeUp_IRQn = 46, /* USB Full-Speed Wake-Up Interrupt */ + PIOC_IRQn = 47, /* Programmable IO Controller Interrupt */ + OPA_IRQn = 48, /* Op Amp Interrupt */ + USBPD_IRQn = 49, /* USB Power Delivery Interrupt */ + USBPD_WKUP_IRQn = 50, /* USB Power Delivery Wake-Up Interrupt */ + TIM2_CC_IRQn = 51, /* Timer 2 Compare Global Interrupt */ + TIM2_TRG_IRQn = 52, /* Timer 2 Trigger Global Interrupt */ + TIM2_BRK_IRQn = 53, /* Timer 2 Brk Global Interrupt */ + TIM3_IRQn = 54, /* Timer 3 Global Interrupt */ +} IRQn_Type; + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS "\n\ + .align 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0\n\ + .word NMI_Handler /* NMI Handler */ \n\ + .word HardFault_Handler /* Hard Fault Handler */ \n\ + .word 0\n\ + .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\ + .word 0 \n\ + .word 0 \n\ + .word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\ + .word Break_Point_Handler /* Break Point */ \n\ + .word 0\n\ + .word 0\n\ + .word SysTick_Handler /* SysTick Handler */ \n\ + .word 0\n\ + .word SW_Handler /* SW Handler */ \n\ + .word 0\n\ + /* External Interrupts */ \n\ + .word WWDG_IRQHandler /* Window Watchdog */ \n\ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n\ + .word FLASH_IRQHandler /* Flash */ \n\ + .word RCC_IRQHandler /* RCC */ \n\ + .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ \n\ + .word AWU_IRQHandler /* AWU */ \n\ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n\ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n\ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n\ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n\ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n\ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n\ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n\ + .word ADC1_IRQHandler /* ADC1 */ \n\ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n\ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n\ + .word USART1_IRQHandler /* USART1 */ \n\ + .word SPI1_IRQHandler /* SPI1 */ \n\ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n\ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n\ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n\ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n\ + .word TIM2_IRQHandler /* TIM2 */ \n\ + .word USART2_IRQHandler /* UART2 Interrupt */ \n\ + .word EXTI15_8_IRQHandler /* External Line[8:15] Interrupt */ \n\ + .word EXTI25_16_IRQHandler /* External Line[25:16] Interrupt */ \n\ + .word USART3_IRQHandler /* UART2 Interrupt */ \n\ + .word USART4_IRQHandler /* UART2 Interrupt */ \n\ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel 8 global Interrupt */ \n\ + .word USBFS_IRQHandler /* USB Full-Speed Interrupt */ \n\ + .word USBFS_WakeUp_IRQHandler /* USB Full-Speed Wake-Up Interrupt */ \n\ + .word PIOC_IRQHandler /* Programmable IO Controller Interrupt */ \n\ + .word OPA_IRQHandler /* Op Amp Interrupt */ \n\ + .word USBPD_IRQHandler /* USB Power Delivery Interrupt */ \n\ + .word USBPD_WKUP_IRQHandler /* USB Power Delivery Wake-Up Interrupt */ \n\ + .word TIM2_CC_IRQHandler /* Timer 2 Compare Global Interrupt */ \n\ + .word TIM2_TRG_IRQHandler /* Timer 2 Trigger Global Interrupt */ \n\ + .word TIM2_BRK_IRQHandler /* Timer 2 Brk Global Interrupt */ \n\ + .word TIM3_IRQHandler /* Timer 3 Global Interrupt */ \n\ + .option pop;\n" + + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + union + { + struct + { + __IO uint32_t CNTL; + __IO uint32_t CNTH; + __IO uint32_t CMPL; + __IO uint32_t CMPH; + }; + struct + { + __IO uint64_t CNT; + __IO uint64_t CMP; + }; + }; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + #define ADC1_2_IRQn ADC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CTLR3; + __IO uint32_t WDTR1; + __IO uint32_t WDTR2; + __IO uint32_t WDTR3; +} ADC_TypeDef; + + + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +typedef struct +{ + __IO uint16_t CAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UID0; + __IO uint32_t UID1; + __IO uint32_t UID2; + __IO uint32_t RES3; +} ESG_TypeDef; + +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct + { + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; + + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; + __IO uint32_t CFGXR; + __IO uint32_t BSXR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR1; + __IO uint32_t EXTICR2; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t CTLR; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t RESERVED1; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; +} RCC_TypeDef; + + + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint16_t DMAADR; + uint16_t RESERVED15; + __IO uint16_t SPEC; + uint16_t RESERVED16; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ +typedef struct +{ + __IO uint32_t CTR; +} EXTEND_TypeDef; + + + + +/* Touch Sensor, Mirrors Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t RESERVED0[3]; + __IO uint32_t CHARGE1; + __IO uint32_t CHARGE2; + __IO uint32_t RESERVED1[10]; + __IO uint32_t CHGOFFSET; + __IO uint32_t RESERVED2[3]; + __IO uint32_t DR_ACT_DCG; +} TKEY_TypeDef; + +/* Op amp / comparator */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t OPA_KEY; + __IO uint32_t CMP_KEY; + __IO uint32_t POLL_KEY; +} OPACMP_TypeDef; + +/* USB Full Speed Device Mode */ +typedef struct +{ + __IO uint8_t BASE_CTRL; //XXX (spelling) + __IO uint8_t UDEV_CTRL; // or host ctlr + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; // Also HOST_EP_MOD + __IO uint8_t UEP567_MOD; + __IO uint8_t RESERVED2; + + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; // Also HOST_RX_DMA + __IO uint32_t UEP3_DMA; // Also HOST_TX_DMA + + //__IO uint32_t UEP0_CTRL; + __IO uint16_t UEP0_TX_LEN; + __IO uint16_t UEP0_CTRL_H; + + //__IO uint32_t UEP1_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint16_t UEP1_CTRL_H; // Also HOST_SETUP + + //__IO uint32_t UEP2_CTRL; + __IO uint16_t UEP2_TX_LEN; // Also HOST_PID + __IO uint16_t UEP2_CTRL_H; // Also HOST_RX_CTL + + //__IO uint32_t UEP3_CTRL; + __IO uint16_t UEP3_TX_LEN; // Also HOST_TX_LEN + __IO uint16_t UEP3_CTRL_H; // Also HOST_TX_CTL + + //__IO uint32_t UEP4_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint16_t UEP4_CTRL_H; + + __IO uint32_t RESERVED3[8]; + + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + + __IO uint32_t RESERVED4; + + //__IO uint32_t UEP5_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint16_t UEP5_CTRL_H; + + //__IO uint32_t UEP6_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint16_t UEP6_CTRL_H; + + //__IO uint32_t UEP7_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint16_t UEP7_CTRL_H; + + __IO uint32_t UEPX_MOD; +} USBFS_TypeDef; + + + + + +#define USBFSD_UEP_MOD_BASE 0x4002340C +#define USBFSD_UEP_DMA_BASE 0x40023410 +#define USBFSD_UEP_LEN_BASE 0x40023420 +#define USBFSD_UEP_CTL_BASE 0x40023422 +#define USBFSD_UEP_RX_EN 0x08 +#define USBFSD_UEP_TX_EN 0x04 +#define USBFSD_UEP_BUF_MOD 0x01 +#define USBFSD_UEP_MOD( N ) (*((volatile uint8_t *)( USBFSD_UEP_MOD_BASE + N ))) +#define USBFSD_UEP_TX_CTRL( N ) (*((volatile uint8_t *)( USBFSD_UEP_CTL_BASE + N * 0x04 ))) +#define USBFSD_UEP_RX_CTRL( N ) (*((volatile uint8_t *)( USBFSD_UEP_CTL_BASE + N * 0x04 ))) +#define USBFSD_UEP_DMA( N ) (*((volatile uint32_t *)( USBFSD_UEP_DMA_BASE + N * 0x04 ))) +#define USBFSD_UEP_BUF( N ) ((uint8_t *)(*((volatile uint32_t *)( USBFSD_UEP_DMA_BASE + N * 0x04 ))) + 0x20000000) +#define USBFSD_UEP_TLEN( N ) (*((volatile uint16_t *)( USBFSD_UEP_LEN_BASE + N * 0x04 ))) + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK (0<<1) +#define USBFS_UEP_T_RES_NONE (1<<0) +#define USBFS_UEP_T_RES_NAK (1<<1) +#define USBFS_UEP_T_RES_STALL (3<<0) +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK (0<<3) +#define USBFS_UEP_R_RES_NONE (1<<2) +#define USBFS_UEP_R_RES_NAK (1<<3) +#define USBFS_UEP_R_RES_STALL (3<<2) + + +#define EP1_T_EN (1<<6) +#define EP2_T_EN (1<<2) +#define EP3_T_EN (1<<6) +#define EP4_T_EN (1<<2) +#define EP1_R_EN (1<<7) +#define EP2_R_EN (1<<3) +#define EP3_R_EN (1<<7) +#define EP4_R_EN (1<<3) + + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + + + + +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ +#define UEP_SIZE 64 + +#define DEF_UEP_IN 0x80 +#define DEF_UEP_OUT 0x00 +#define DEF_UEP_BUSY 0x01 +#define DEF_UEP_FREE 0x00 + +#define DEF_UEP0 0 +#define DEF_UEP1 1 +#define DEF_UEP2 2 +#define DEF_UEP3 3 +#define DEF_UEP4 4 +#define DEF_UEP5 5 +#define DEF_UEP6 6 +#define DEF_UEP7 7 +#define UNUM_EP 8 + + + +/* USB Host Mode */ + +typedef struct +{ + __IO uint8_t RESERVED0; + __IO uint8_t HOST_CTRL; + __IO uint8_t RESERVED1; + __IO uint8_t RESERVED2; + __IO uint8_t RESERVED3; + __IO uint8_t RESERVED4; + __IO uint8_t RESERVED5; + __IO uint8_t RESERVED6; + __IO uint16_t RESERVED7; + __IO uint16_t RESERVED8; + __IO uint8_t RESERVED9; + __IO uint8_t HOST_EP_MOD; + __IO uint8_t RESERVED10; + __IO uint8_t RESERVED11; + + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + + __IO uint16_t RESERVED14; + __IO uint16_t RESERVED15; + __IO uint16_t RESERVED16; + + __IO uint16_t HOST_SETUP; + __IO uint16_t HOST_EP_PID; + __IO uint16_t HOST_RX_CTL; + __IO uint16_t HOST_TX_LEN; + __IO uint16_t HOST_TX_CTL; + + __IO uint16_t RESERVED20; + __IO uint16_t RESERVED21; + + __IO uint32_t RESERVED22[8]; + + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + + __IO uint32_t RESERVED26; + + __IO uint16_t RESERVED27; + __IO uint16_t RESERVED28; + + __IO uint16_t RESERVED29; + __IO uint16_t RESERVED30; + + __IO uint16_t RESERVED31; + __IO uint16_t RESERVED32; + + __IO uint32_t RESERVED33; +} USBDH_TypeDef; + + +/* USB Power Delivery */ +typedef struct +{ + __IO uint32_t CONFIG; + __IO uint32_t CONTROL; + __IO uint32_t STATUS; + __IO uint32_t PORT; + __IO uint32_t DMA; +} USBPD_TypeDef; + + +/* USB Power Delivery */ +typedef struct +{ + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + __IO uint16_t BMC_TX_SZ; + + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + __IO uint16_t BMC_BYTE_CNT; + + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + + __IO uint32_t DMA; +} USBPD_DETAILED_TypeDef; + + + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif // !__ASSEMBLER__ + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define USART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ + + +#define OPA_BASE (AHBPERIPH_BASE + 0x6000) +#define USBFS_BASE (AHBPERIPH_BASE + 0x3400) +#define AWU_BASE (AHBPERIPH_BASE + 0x6400) +#define PIOC_BASE (AHBPERIPH_BASE + 0x6C00) +#define USBPD_BASE (AHBPERIPH_BASE + 0x7000) + + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) + +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + + + + + + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TKey ((TKEY_TypeDef *)ADC1_BASE) +#define OPA ((OPACMP_TypeDef *)OPA_BASE) +#define USBFS ((USBFS_TypeDef *)USBFS_BASE) +#define USBPDWORD ((USBPD_TypeDef *)USBPD_BASE) +#define USBPD ((USBPD_DETAILED_TypeDef *)USBPD_BASE) +#define USBDH ((USBDH_TypeDef *)USBFS_BASE) + +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESG_TypeDef *)ESIG_BASE) +// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + + + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_TKENABLE ((uint32_t)0x01000000) /* TKEN mode enable */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + + +/******************** Bit definition for ADC_CTLR3 register ********************/ +#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */ +#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */ +#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */ +#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */ +#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */ +#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */ + +/******************** Bit definition for ADC_WDTR1 register ********************/ +#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */ +#define ADC_WDTR1_HTR1 ((uint32_t)0x0FFF0000) /* Analog watchdog1 high threshold */ + +/******************** Bit definition for ADC_WDTR2 register ********************/ +#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */ +#define ADC_WDTR2_HTR2 ((uint32_t)0x0FFF0000) /* Analog watchdog2 high threshold */ + +/******************** Bit definition for ADC_WDTR3 register ********************/ +#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */ +#define ADC_WDTR3_HTR3 ((uint32_t)0x0FFF0000) /* Analog watchdog3 high threshold */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG8 register *******************/ +#define DMA_CFG8_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG8_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG8_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG8_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG8_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG8_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ +#define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */ +#define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */ +#define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */ +#define EXTI_INTENR_MR26 ((uint32_t)0x04000000) /* Interrupt Mask on line 26 */ +#define EXTI_INTENR_MR27 ((uint32_t)0x08000000) /* Interrupt Mask on line 27 */ +#define EXTI_INTENR_MR28 ((uint32_t)0x10000000) /* Interrupt Mask on line 28 */ +#define EXTI_INTENR_MR29 ((uint32_t)0x20000000) /* Interrupt Mask on line 29 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ +#define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */ +#define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */ +#define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */ +#define EXTI_EVENR_MR26 ((uint32_t)0x04000000) /* Event Mask on line 26 */ +#define EXTI_EVENR_MR27 ((uint32_t)0x08000000) /* Event Mask on line 27 */ +#define EXTI_EVENR_MR28 ((uint32_t)0x10000000) /* Event Mask on line 28 */ +#define EXTI_EVENR_MR29 ((uint32_t)0x20000000) /* Event Mask on line 29 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ +#define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */ +#define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */ +#define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */ +#define EXTI_RTENR_TR26 ((uint32_t)0x04000000) /* Rising trigger event configuration bit of line 26 */ +#define EXTI_RTENR_TR27 ((uint32_t)0x08000000) /* Rising trigger event configuration bit of line 27 */ +#define EXTI_RTENR_TR28 ((uint32_t)0x10000000) /* Rising trigger event configuration bit of line 28 */ +#define EXTI_RTENR_TR29 ((uint32_t)0x20000000) /* Rising trigger event configuration bit of line 29 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ +#define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */ +#define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */ +#define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */ +#define EXTI_FTENR_TR26 ((uint32_t)0x04000000) /* Falling trigger event configuration bit of line 26 */ +#define EXTI_FTENR_TR27 ((uint32_t)0x08000000) /* Falling trigger event configuration bit of line 27 */ +#define EXTI_FTENR_TR28 ((uint32_t)0x10000000) /* Falling trigger event configuration bit of line 28 */ +#define EXTI_FTENR_TR29 ((uint32_t)0x20000000) /* Falling trigger event configuration bit of line 29 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ +#define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */ +#define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */ +#define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */ +#define EXTI_SWIEVR_SWIEVR26 ((uint32_t)0x04000000) /* Software Interrupt on line 26 */ +#define EXTI_SWIEVR_SWIEVR27 ((uint32_t)0x08000000) /* Software Interrupt on line 27 */ +#define EXTI_SWIEVR_SWIEVR28 ((uint32_t)0x10000000) /* Software Interrupt on line 28 */ +#define EXTI_SWIEVR_SWIEVR29 ((uint32_t)0x20000000) /* Software Interrupt on line 29 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ +#define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */ +#define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */ +#define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */ +#define EXTI_INTF_INTF26 ((uint32_t)0x04000000) /* Pending bit for line 26 */ +#define EXTI_INTF_INTF27 ((uint32_t)0x08000000) /* Pending bit for line 27 */ +#define EXTI_INTF_INTF28 ((uint32_t)0x10000000) /* Pending bit for line 28 */ +#define EXTI_INTF_INTF29 ((uint32_t)0x20000000) /* Pending bit for line 29 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */ +#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */ +#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) /* The state of Init Config */ +#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) /* The source of Execute Program */ +#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) /* The switch of user section or boot section*/ +#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /* Lock boot area*/ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG (0x0001) /* Programming */ +#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT (0x0040) /* Start */ +#define FLASH_CTLR_LOCK (0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) /* Wake inter Enable */ +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Fast Program */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Fast Erase */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) /* BUF Load */ +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) /* BUF Reset */ +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +#define FLASH_CTLR_PAGE_PG FLASH_CTLR_FTPG /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER FLASH_CTLR_FTER /* Page Erase 64Byte */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_CFGRSTT FLASH_OBR_RST_MODE /* Config Reset delay time */ + +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* fix 11 */ +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* Data byte0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* Data byte1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */ +#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for BOOT_MODEKEYP register ******************/ +#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */ +#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123) +#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ +#define GPIO_INDR_IDR16 ((uint32_t)0x10000) /* Port input data, bit 16 */ +#define GPIO_INDR_IDR17 ((uint32_t)0x20000) /* Port input data, bit 17 */ +#define GPIO_INDR_IDR18 ((uint32_t)0x40000) /* Port input data, bit 18 */ +#define GPIO_INDR_IDR19 ((uint32_t)0x80000) /* Port input data, bit 19 */ +#define GPIO_INDR_IDR20 ((uint32_t)0x100000) /* Port input data, bit 20 */ +#define GPIO_INDR_IDR21 ((uint32_t)0x200000) /* Port input data, bit 21 */ +#define GPIO_INDR_IDR22 ((uint32_t)0x400000) /* Port input data, bit 22 */ +#define GPIO_INDR_IDR23 ((uint32_t)0x800000) /* Port input data, bit 23 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ +#define GPIO_OUTDR_ODR16 ((uint32_t)0x10000) /* Port output data, bit 16 */ +#define GPIO_OUTDR_ODR17 ((uint32_t)0x20000) /* Port output data, bit 17 */ +#define GPIO_OUTDR_ODR18 ((uint32_t)0x40000) /* Port output data, bit 18 */ +#define GPIO_OUTDR_ODR19 ((uint32_t)0x80000) /* Port output data, bit 19 */ +#define GPIO_OUTDR_ODR20 ((uint32_t)0x100000) /* Port output data, bit 20 */ +#define GPIO_OUTDR_ODR21 ((uint32_t)0x200000) /* Port output data, bit 21 */ +#define GPIO_OUTDR_ODR22 ((uint32_t)0x400000) /* Port output data, bit 22 */ +#define GPIO_OUTDR_ODR23 ((uint32_t)0x800000) /* Port output data, bit 23 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ +#define GPIO_BCR_BR16 ((uint32_t)0x10000) /* Port x Reset bit 16 */ +#define GPIO_BCR_BR17 ((uint32_t)0x20000) /* Port x Reset bit 17 */ +#define GPIO_BCR_BR18 ((uint32_t)0x40000) /* Port x Reset bit 18 */ +#define GPIO_BCR_BR19 ((uint32_t)0x80000) /* Port x Reset bit 19 */ +#define GPIO_BCR_BR20 ((uint32_t)0x100000) /* Port x Reset bit 20 */ +#define GPIO_BCR_BR21 ((uint32_t)0x200000) /* Port x Reset bit 21 */ +#define GPIO_BCR_BR22 ((uint32_t)0x400000) /* Port x Reset bit 22 */ +#define GPIO_BCR_BR23 ((uint32_t)0x800000) /* Port x Reset bit 23 */ + + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCK16 ((uint32_t)0x00010000) /* Port x Lock bit 16 */ +#define GPIO_LCK17 ((uint32_t)0x00020000) /* Port x Lock bit 17 */ +#define GPIO_LCK18 ((uint32_t)0x00040000) /* Port x Lock bit 18 */ +#define GPIO_LCK19 ((uint32_t)0x00080000) /* Port x Lock bit 19 */ +#define GPIO_LCK20 ((uint32_t)0x00100000) /* Port x Lock bit 20 */ +#define GPIO_LCK21 ((uint32_t)0x00200000) /* Port x Lock bit 21 */ +#define GPIO_LCK22 ((uint32_t)0x00400000) /* Port x Lock bit 22 */ +#define GPIO_LCK23 ((uint32_t)0x00800000) /* Port x Lock bit 23 */ + +#define GPIO_LCKK ((uint32_t)0x01000000) /* Lock key */ + +/******************* Bit definition for GPIO_CFGXR register *******************/ +#define GPIO_CFGXR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/****************** Bit definition for GPIO_BSXR register *******************/ +#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000003) /* SPI1_REMAP[1:0] bits (SPI1 remapping) */ +#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x0000001C) /* I2C1_REMAP[4:2] bits (I2C1 remapping) */ +#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000008) /* Bit 1 */ +#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000010) /* Bit 2 */ + +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000060) /* USART1_REMAP[6:5] bits (USART1 remapping) */ +#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000040) /* Bit 1 */ + +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000380) /* USART2_REMAP[9:7] bits (USART2 remapping) */ +#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00000080) /* Bit 0 */ +#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00000100) /* Bit 1 */ +#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00000200) /* Bit 2 */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000C00) /* USART3_REMAP[11:10] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00007000) /* USART4_REMAP[14:12] bits (USART4 remapping) */ +#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00038000) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x001C0000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00600000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00400000) /* Bit 1 */ + +#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00800000) /* PIOC[23] bits (PIOC remapping) */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */ +#define AFIO_EXTICR1_EXTI8 ((uint32_t)0x00030000) /* EXTI 8 configuration */ +#define AFIO_EXTICR1_EXTI9 ((uint32_t)0x000C0000) /* EXTI 9 configuration */ +#define AFIO_EXTICR1_EXTI10 ((uint32_t)0x00300000) /* EXTI 10 configuration */ +#define AFIO_EXTICR1_EXTI11 ((uint32_t)0x00C00000) /* EXTI 11 configuration */ +#define AFIO_EXTICR1_EXTI12 ((uint32_t)0x03000000) /* EXTI 12 configuration */ +#define AFIO_EXTICR1_EXTI13 ((uint32_t)0x0C000000) /* EXTI 13 configuration */ +#define AFIO_EXTICR1_EXTI14 ((uint32_t)0x30000000) /* EXTI 14 configuration */ +#define AFIO_EXTICR1_EXTI15 ((uint32_t)0xC0000000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000004) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000010) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00000040) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00000100) /* PB[4] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00000400) /* PB[5] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x00001000) /* PB[6] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x00004000) /* PB[7] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */ + +#define AFIO_EXTICR1_EXTI8_PA ((uint32_t)0x00000000) /* PA[8] pin */ +#define AFIO_EXTICR1_EXTI8_PB ((uint32_t)0x00010000) /* PB[8] pin */ +#define AFIO_EXTICR1_EXTI8_PC ((uint32_t)0x00020000) /* PC[8] pin */ + +#define AFIO_EXTICR1_EXTI9_PA ((uint32_t)0x00000000) /* PA[9] pin */ +#define AFIO_EXTICR1_EXTI9_PB ((uint32_t)0x00040000) /* PB[9] pin */ +#define AFIO_EXTICR1_EXTI9_PC ((uint32_t)0x00080000) /* PC[9] pin */ + +#define AFIO_EXTICR1_EXTI10_PA ((uint32_t)0x00000000) /* PA[10] pin */ +#define AFIO_EXTICR1_EXTI10_PB ((uint32_t)0x00100000) /* PB[10] pin */ +#define AFIO_EXTICR1_EXTI10_PC ((uint32_t)0x00200000) /* PC[10] pin */ + +#define AFIO_EXTICR1_EXTI11_PA ((uint32_t)0x00000000) /* PA[11] pin */ +#define AFIO_EXTICR1_EXTI11_PB ((uint32_t)0x00400000) /* PB[11] pin */ +#define AFIO_EXTICR1_EXTI11_PC ((uint32_t)0x00800000) /* PC[11] pin */ + +#define AFIO_EXTICR1_EXTI12_PA ((uint32_t)0x00000000) /* PA[12] pin */ +#define AFIO_EXTICR1_EXTI12_PB ((uint32_t)0x01000000) /* PB[12] pin */ +#define AFIO_EXTICR1_EXTI12_PC ((uint32_t)0x02000000) /* PC[12] pin */ + +#define AFIO_EXTICR1_EXTI13_PA ((uint32_t)0x00000000) /* PA[13] pin */ +#define AFIO_EXTICR1_EXTI13_PB ((uint32_t)0x04000000) /* PB[13] pin */ +#define AFIO_EXTICR1_EXTI13_PC ((uint32_t)0x08000000) /* PC[13] pin */ + +#define AFIO_EXTICR1_EXTI14_PA ((uint32_t)0x00000000) /* PA[14] pin */ +#define AFIO_EXTICR1_EXTI14_PB ((uint32_t)0x10000000) /* PB[14] pin */ +#define AFIO_EXTICR1_EXTI14_PC ((uint32_t)0x20000000) /* PC[14] pin */ + +#define AFIO_EXTICR1_EXTI15_PA ((uint32_t)0x00000000) /* PA[15] pin */ +#define AFIO_EXTICR1_EXTI15_PB ((uint32_t)0x40000000) /* PB[15] pin */ +#define AFIO_EXTICR1_EXTI15_PC ((uint32_t)0x80000000) /* PC[15] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI16 ((uint16_t)0x00000003) /* EXTI 16 configuration */ +#define AFIO_EXTICR2_EXTI17 ((uint16_t)0x0000000C) /* EXTI 17 configuration */ +#define AFIO_EXTICR2_EXTI18 ((uint16_t)0x00000030) /* EXTI 18 configuration */ +#define AFIO_EXTICR2_EXTI19 ((uint16_t)0x000000C0) /* EXTI 19 configuration */ +#define AFIO_EXTICR2_EXTI20 ((uint16_t)0x00000300) /* EXTI 20 configuration */ +#define AFIO_EXTICR2_EXTI21 ((uint16_t)0x00000C00) /* EXTI 21 configuration */ +#define AFIO_EXTICR2_EXTI22 ((uint16_t)0x00003000) /* EXTI 22 configuration */ +#define AFIO_EXTICR2_EXTI23 ((uint16_t)0x0000C000) /* EXTI 23 configuration */ + +#define AFIO_EXTICR2_EXTI16_PA ((uint16_t)0x00000000) /* PA[16] pin */ +#define AFIO_EXTICR2_EXTI16_PB ((uint16_t)0x00000001) /* PB[16] pin */ +#define AFIO_EXTICR2_EXTI16_PC ((uint16_t)0x00000002) /* PC[16] pin */ + +#define AFIO_EXTICR2_EXTI17_PA ((uint16_t)0x00000000) /* PA[17] pin */ +#define AFIO_EXTICR2_EXTI17_PB ((uint16_t)0x00000004) /* PB[17] pin */ +#define AFIO_EXTICR2_EXTI17_PC ((uint16_t)0x00000008) /* PC[17] pin */ + +#define AFIO_EXTICR2_EXTI18_PA ((uint16_t)0x00000000) /* PA[18] pin */ +#define AFIO_EXTICR2_EXTI18_PB ((uint16_t)0x00000010) /* PB[18] pin */ +#define AFIO_EXTICR2_EXTI18_PC ((uint16_t)0x00000020) /* PC[18] pin */ + +#define AFIO_EXTICR2_EXTI19_PA ((uint16_t)0x00000000) /* PA[19] pin */ +#define AFIO_EXTICR2_EXTI19_PB ((uint16_t)0x00000040) /* PB[19] pin */ +#define AFIO_EXTICR2_EXTI19_PC ((uint16_t)0x00000080) /* PC[19] pin */ + +#define AFIO_EXTICR2_EXTI20_PA ((uint16_t)0x00000000) /* PA[20] pin */ +#define AFIO_EXTICR2_EXTI20_PB ((uint16_t)0x00000100) /* PB[20] pin */ +#define AFIO_EXTICR2_EXTI20_PC ((uint16_t)0x00000200) /* PC[20] pin */ + +#define AFIO_EXTICR2_EXTI21_PA ((uint16_t)0x00000000) /* PA[21] pin */ +#define AFIO_EXTICR2_EXTI21_PB ((uint16_t)0x00000400) /* PB[21] pin */ +#define AFIO_EXTICR2_EXTI21_PC ((uint16_t)0x00000800) /* PC[21] pin */ + +#define AFIO_EXTICR2_EXTI22_PA ((uint16_t)0x00000000) /* PA[22] pin */ +#define AFIO_EXTICR2_EXTI22_PB ((uint16_t)0x00001000) /* PB[22] pin */ +#define AFIO_EXTICR2_EXTI22_PC ((uint16_t)0x00002000) /* PC[22] pin */ + +#define AFIO_EXTICR2_EXTI23_PA ((uint16_t)0x00000000) /* PA[23] pin */ +#define AFIO_EXTICR2_EXTI23_PB ((uint16_t)0x00004000) /* PB[23] pin */ +#define AFIO_EXTICR2_EXTI23_PC ((uint16_t)0x00008000) /* PC[23] pin */ + +/******************* Bit definition for AFIO_CTLR register ********************/ +#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/ +#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */ +#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */ + +#define UDM_PUE_MASK 0x00000003 +#define UDM_PUE_DISABLE 0x00000000 +#define UDM_PUE_35UA 0x00000001 +#define UDM_PUE_10K 0x00000002 +#define UDM_PUE_1K5 0x00000003 + +#define AFIO_CTLR_UDP_PUE ((uint32_t)0x0000000C) /* PC17/UDP Pin pull-up Mode*/ +#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */ +#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */ + +#define UDP_PUE_MASK 0x0000000C +#define UDP_PUE_DISABLE 0x00000000 +#define UDP_PUE_35UA 0x00000004 +#define UDP_PUE_10K 0x00000008 +#define UDP_PUE_1K5 0x0000000C + +#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */ +#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */ +#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */ +#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */ +#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */ +#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */ +#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */ +#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */ + +#define USB_IOEN AFIO_CTLR_USB_IOEN +#define USB_PHY_V33 AFIO_CTLR_USB_PHY_V33 + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_LP_REG ((uint16_t)0x0200) /* Software configure flash into lower energy mode */ +#define PWR_CTLR_LP ((uint16_t)0x0C00) /* Software configure flash Status */ +#define PWR_CTLR_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_LP_1 ((uint16_t)0x0800) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ +#define PWR_CSR_Flash_ack ((uint16_t)0x0200) /* Flash Status */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ + + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_CFGR2 register *******************/ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint32_t)0x1000) +#define RCC_USBFS ((uint32_t)0x1000) +#define RCC_USBPD ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_OPARSTF ((uint32_t)0x02000000) /* OPA reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/****************** Bit definition for RCC_AHBRSTR register *****************/ +#define RCC_USBFSRST ((uint32_t)0x00001000) /* USBFS reset */ +#define RCC_PIOCRST ((uint32_t)0x00002000) /* PIOC RST */ +#define RCC_USBPDRST ((uint32_t)0x00020000) /* USBPD reset */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ +#define SPI_CTLR2_ODEN ((uint16_t)0x8000) /* SPI OD output Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register *****************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Read Enable under SPI High speed mode */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CMP_BK ((uint16_t)0x1000) /* voltage comparator break enable, TIM1 only */ +#define TIM_CAPOV ((uint16_t)0x4000) /* Cfg mode of capture value */ +#define TIM_CAPLVL ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************* Bit definition for TIM_SPEC register *******************/ +#define TIM_SPEC_PWM_EN_1_2 ((uint16_t)0x0001) /* Channel 1 and Channel 2 alternate */ +#define TIM_SPEC_PWM_EN_3_4 ((uint16_t)0x0002) /* Channel 3 and Channel 4 alternate */ +#define TIM_SPEC_PWM_OC1 ((uint16_t)0x0010) /* Channel 1 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC2 ((uint16_t)0x0020) /* Channel 2 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC3 ((uint16_t)0x0040) /* Channel 3 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC4 ((uint16_t)0x0080) /* Channel 4 invalid level under alternate mode */ +#define TIM_SPEC_TOGGLE ((uint16_t)0x8000) /* valid channel indicator */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + + + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ + + + + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* ch32v00x_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32v00x_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +///* CTLR1 register Mask */ +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_MASK ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_MASK ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_MASK ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + + + + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32v00x_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_MASK ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_MASK ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_MASK ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_MASK ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_MASK ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_MASK ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_MASK ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + + +/* DMA2 FLAG mask */ +// Editor's note: Overloaded Definition. +#define DMA2_FLAG_MASK ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_MASK ((uint32_t)0xFFFF800F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32v00x_flash.c ----------------------------------------------------------*/ + + + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_MASK ((uint32_t)0x00000002) +#define WRP0_MASK ((uint32_t)0x000000FF) +#define WRP1_MASK ((uint32_t)0x0000FF00) +#define WRP2_MASK ((uint32_t)0x00FF0000) +#define WRP3_MASK ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + + +/* ch32v00x_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +////* I2C registers Masks */ +// Editor's note: Overloaded Definition. +#define I2C_CTLR1_CLEAR_MASK ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +//Editor's Note: Overloaded Definition +#define I2c_FLAG_MASK ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_MASK ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + + +/* ch32v00x_pwr.c ------------------------------------------------------------*/ + + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* ch32v00x_rcc.c ------------------------------------------------------------*/ + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_MASK ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_MASK ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_MASK ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_MASK ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_MASK ((uint32_t)0x00020000) +#define CFGR0_SWS_MASK ((uint32_t)0x0000000C) +#define CFGR0_SW_MASK ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_MASK ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_MASK ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_MASK ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_MASK ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_MASK ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_MASK ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_MASK ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_MASK ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + + +/* RCC Flag Mask */ +//Editor's Note: Overloaded Definition +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +#ifndef __ASSEMBLER__ +#endif + + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_MASK ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) + + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_MASK ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32v00x_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_MASK ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_MASK ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_MASK ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_MASK ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_MASK ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_MASK ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_MASK ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_MASK ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_MASK ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_MASK ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_MASK ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFGR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + + +/* ch32v00x_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15) + +/* ADC_sampling_time */ +#define ADC_SampleTime_4Cycles ((uint8_t)0x00) +#define ADC_SampleTime_5Cycles ((uint8_t)0x01) +#define ADC_SampleTime_6Cycles ((uint8_t)0x02) +#define ADC_SampleTime_7Cycles ((uint8_t)0x03) +#define ADC_SampleTime_8Cycles ((uint8_t)0x04) +#define ADC_SampleTime_9Cycles ((uint8_t)0x05) +#define ADC_SampleTime_10Cycles ((uint8_t)0x06) +#define ADC_SampleTime_11Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + + +/* ADC_external_trigger_sources_delay_channels_definition */ +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) + +/* ADC_analog_watchdog_reset_enable_selection */ +#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000) +#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000) +#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000) +#define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000) + +/* ADC_analog_watchdog_reset_flags_definition */ +#define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000) +#define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000) +#define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000) +#define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000) + +/* ADC_clock */ +#define ADC_CLK_Div4 ((uint32_t)0x00000013) +#define ADC_CLK_Div5 ((uint32_t)0x00000014) +#define ADC_CLK_Div6 ((uint32_t)0x00000025) +#define ADC_CLK_Div7 ((uint32_t)0x00000026) +#define ADC_CLK_Div8 ((uint32_t)0x00000037) +#define ADC_CLK_Div9 ((uint32_t)0x00000038) +#define ADC_CLK_Div10 ((uint32_t)0x00000049) +#define ADC_CLK_Div11 ((uint32_t)0x0000004A) +#define ADC_CLK_Div12 ((uint32_t)0x0000005B) +#define ADC_CLK_Div13 ((uint32_t)0x0000005C) +#define ADC_CLK_Div14 ((uint32_t)0x0000006D) +#define ADC_CLK_Div15 ((uint32_t)0x0000006E) +#define ADC_CLK_Div16 ((uint32_t)0x0000007F) + + +/* PWR_AWU_Prescaler */ +#define AWU_Prescaler_1 ((uint32_t)0x00000000) +#define AWU_Prescaler_2 ((uint32_t)0x00000002) +#define AWU_Prescaler_4 ((uint32_t)0x00000003) +#define AWU_Prescaler_8 ((uint32_t)0x00000004) +#define AWU_Prescaler_16 ((uint32_t)0x00000005) +#define AWU_Prescaler_32 ((uint32_t)0x00000006) +#define AWU_Prescaler_64 ((uint32_t)0x00000007) +#define AWU_Prescaler_128 ((uint32_t)0x00000008) +#define AWU_Prescaler_256 ((uint32_t)0x00000009) +#define AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define AWU_Prescaler_61440 ((uint32_t)0x0000000F) + + +/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ +/* CFGR0 Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) + +/* ch32v00x_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */ +#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */ +#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */ +#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */ +#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */ +#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */ +#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */ +#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */ +#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 */ +#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 */ +#define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 */ +#define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 */ +#define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 */ +#define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 */ + +/* ch32v00x_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; +#endif + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Values to be used with devices (1page = 256Byte) */ +#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ +#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ +#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ +#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ +#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ +#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ +#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ +#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ +#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ +#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ +#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ +#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ +#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ +#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ +#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ +#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ +#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ +#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ +#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ +#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ +#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ +#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ +#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ +#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ +#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ +#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ +#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ +#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ +#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ +#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ +#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ + + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + + + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */ +#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */ + + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; +#define GPIO_Speed_30MHz GPIO_Speed_50MHz +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */ +#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */ +#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */ +#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */ +#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */ +#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */ +#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */ +#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */ + +#if defined(GPIO_Pin_23) +#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ +#else +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ +#endif + +/* GPIO_Remap_define */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08020004) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08020008) /* I2C1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0802000C) /* I2C1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08020010) /* I2C1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x08020014) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08070080) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08070100) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08070180) /* USART2 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0x08070200) /* USART2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART3 ((uint32_t)0x001A0400) /* USART3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART3 ((uint32_t)0x001A0800) /* USART3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x001A0C00) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART4 ((uint32_t)0x080C1000) /* USART4 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART4 ((uint32_t)0x080C2000) /* USART4 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART4 ((uint32_t)0x080C3000) /* USART4 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART4 ((uint32_t)0x080C4000) /* USART4 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x080C7000) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x084F0001) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x084F0002) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x084F0003) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x084F0004) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08220004) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08220008) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0822000C) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08220010) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08220014) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x08220018) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00350020) /* TIM3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00350040) /* TIM3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x00350060) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) +#define GPIO_PinSource16 ((uint8_t)0x10) +#define GPIO_PinSource17 ((uint8_t)0x11) +#define GPIO_PinSource18 ((uint8_t)0x12) +#define GPIO_PinSource19 ((uint8_t)0x13) +#define GPIO_PinSource20 ((uint8_t)0x14) +#define GPIO_PinSource21 ((uint8_t)0x15) +#define GPIO_PinSource22 ((uint8_t)0x16) +#define GPIO_PinSource23 ((uint8_t)0x17) + + +/* ch32v00x_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +/* ch32v00x_misc.h -----------------------------------------------------------*/ + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + +/* ch32v00x_opa.h ------------------------------------------------------------*/ + +/* Editor's note: I don't know if this is actually useful */ +#ifndef __ASSEMBLER__ + + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, + OPA2 +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1 +} OPA_Mode_TypeDef; + + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1, + CHP2, + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1, + CHN2_PGA_16xIN, + CHN_PGA_4xIN, + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_OFF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF_OPA2_OFF = 0, + CHP_OPA1_ON_OPA2_OFF, + CHP_OPA1_OFF_OPA2_ON, + CHP_OPA1_ON_OPA2_ON +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF_OPA2_OFF = 0, + BKIN_OPA1_ON_OPA2_OFF, + BKIN_OPA1_OFF_OPA2_ON, + BKIN_OPA1_ON_OPA2_ON +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF_OPA2_OFF = 0, + RST_OPA1_ON_OPA2_OFF, + RST_OPA1_OFF_OPA2_ON, + RST_OPA1_ON_OPA2_ON +} OPA_RST_EN_TypeDef; + +/* OPA_BKIN_SEL_enumeration */ +typedef enum +{ + BKIN_OPA1_TIM1_OPA2_TIM2 = 0, + BKIN_OPA1_TIM2_OPA2_TIM1 +} OPA_BKIN_SEL_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF_OPA2_OFF = 0, + OUT_IE_OPA1_ON_OPA2_OFF, + OUT_IE_OPA1_OFF_OPA2_ON, + OUT_IE_OPA1_ON_OPA2_ON +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3 +} OPA_PSEL_POLL_NUM_TypeDef; + + + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO_TIM2 = 0, + OUT_IO0 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP1 = 0, + CMP_CHP2, +} CMP_PSEL_TypeDef; + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN1 = 0, + CMP_HYEN2, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +#endif + +/* ch32v00x_pwr.h ------------------------------------------------------------*/ + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) + +#define PWR_PVDLevel_2V1 PWR_PVDLevel_0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_1 +#define PWR_PVDLevel_3V0 PWR_PVDLevel_2 +#define PWR_PVDLevel_4V0 PWR_PVDLevel_3 + + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define PWR_FLAG_FLASH ((uint32_t)0x00000020) + + +/* ch32v00x_rcc.h ------------------------------------------------------------*/ + + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + + + + + + + + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_USBHD RCC_AHBPeriph_USBFS +#define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000) +#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + + +/* APB2_peripheral */ +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) + +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) + + + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) + + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_OPARST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + + + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + + + + + + + + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Supersede_Mode_OC1 */ +#define TIM_Supersede_Mode_OC1_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC1_L ((uint16_t)0x0010) + +/* TIM_Supersede_Mode_OC2 */ +#define TIM_Supersede_Mode_OC2_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC2_L ((uint16_t)0x0020) + +/* TIM_Supersede_Mode_OC3 */ +#define TIM_Supersede_Mode_OC3_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC3_L ((uint16_t)0x0040) + +/* TIM_Supersede_Mode_OC4 */ +#define TIM_Supersede_Mode_OC4_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC4_L ((uint16_t)0x0080) + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +// While not truly CH32X035, we can re-use some of the USB register defs. +/* ch32v10x_usb.h ------------------------------------------------------------*/ + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef VOID + #define VOID void +#endif +#ifndef CONST + #define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* USB */ +#define R32_USB_CONTROL (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address +#define R8_USB_CTRL (*((PUINT8V)(0x40023400))) // USB base control +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define R8_UDEV_CTRL (*((PUINT8V)(0x40023401))) // USB device physical prot control +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define R8_USB_INT_EN (*((PUINT8V)(0x40023402))) // USB interrupt enable +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define R8_USB_DEV_AD (*((PUINT8V)(0x40023403))) // USB device address +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define R32_USB_STATUS (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status +#define R8_USB_MIS_ST (*((PUINT8V)(0x40023405))) // USB miscellaneous status +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define R8_USB_INT_FG (*((PUINT8V)(0x40023406))) // USB interrupt flag +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define R8_USB_INT_ST (*((PUINT8V)(0x40023407))) // USB interrupt status +#define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R16_USB_RX_LEN (*((PUINT16V)(0x40023408))) // USB receiving length +#define MASK_UIS_RX_LEN 0x3FF // RO, bit mask of current receive length(10 bits for ch32v10x) +#define R32_USB_BUF_MODE (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode +#define R8_UEP4_1_MOD (*((PUINT8V)(0x4002340c))) // endpoint 4/1 mode +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +#define R8_UEP2_3_MOD (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#define R8_UEP5_6_MOD (*((PUINT8V)(0x4002340e))) // endpoint 5/6 mode +#define RB_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define RB_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define RB_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +#define R8_UEP7_MOD (*((PUINT8V)(0x4002340f))) // endpoint 7 mode +#define RB_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +#define R16_UEP0_DMA (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address +#define R16_UEP1_DMA (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address +#define R16_UEP2_DMA (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address +#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address +#define R16_UEP3_DMA (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address + +#define R16_UEP4_DMA (*((PUINT16V)(0x40023420))) // endpoint 4 DMA buffer address +#define R16_UEP5_DMA (*((PUINT16V)(0x40023424))) // endpoint 5 DMA buffer address +#define R16_UEP6_DMA (*((PUINT16V)(0x40023428))) // endpoint 6 DMA buffer address +#define R16_UEP7_DMA (*((PUINT16V)(0x4002342c))) // endpoint 7 DMA buffer address + +#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address +#define R32_USB_EP0_CTRL (*((PUINT32V)(0x40023430))) // endpoint 0 control & transmittal length +#define R8_UEP0_T_LEN (*((PUINT8V)(0x40023430))) // endpoint 0 transmittal length +#define R8_UEP0_CTRL (*((PUINT8V)(0x40023432))) // endpoint 0 control +#define R32_USB_EP1_CTRL (*((PUINT32V)(0x40023434))) // endpoint 1 control & transmittal length +#define R16_UEP1_T_LEN (*((PUINT16V)(0x40023434))) // endpoint 1 transmittal length(16-bits for ch32v10x) +#define R8_UEP1_CTRL (*((PUINT8V)(0x40023436))) // endpoint 1 control +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R32_USB_EP2_CTRL (*((PUINT32V)(0x40023438))) // endpoint 2 control & transmittal length +#define R16_UEP2_T_LEN (*((PUINT16V)(0x40023438))) // endpoint 2 transmittal length(16-bits for ch32v10x) +#define R8_UEP2_CTRL (*((PUINT8V)(0x4002343a))) // endpoint 2 control + +#define R8_UH_EP_PID (*((PUINT8V)(0x40023438))) // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R32_USB_EP3_CTRL (*((PUINT32V)(0x4002343c))) // endpoint 3 control & transmittal length +#define R16_UEP3_T_LEN (*((PUINT16V)(0x4002343c))) // endpoint 3 transmittal length(16-bits for ch32v10x) +#define R8_UEP3_CTRL (*((PUINT8V)(0x4002343e))) // endpoint 3 control +#define R8_UH_TX_LEN (*((PUINT16V)(0x4002343c))) //R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R32_USB_EP4_CTRL (*((PUINT32V)(0x40023440))) // endpoint 4 control & transmittal length +#define R16_UEP4_T_LEN (*((PUINT16V)(0x40023440))) // endpoint 4 transmittal length(16-bits for ch32v10x) +#define R8_UEP4_CTRL (*((PUINT8V)(0x40023442))) // endpoint 4 control + +#define R32_USB_EP5_CTRL (*((PUINT32V)(0x40023444))) // endpoint 5 control & transmittal length +#define R16_UEP5_T_LEN (*((PUINT16V)(0x40023444))) // endpoint 5 transmittal length(16-bits for ch32v10x) +#define R8_UEP5_CTRL (*((PUINT8V)(0x40023446))) // endpoint 5 control + +#define R32_USB_EP6_CTRL (*((PUINT32V)(0x40023448))) // endpoint 6 control & transmittal length +#define R16_UEP6_T_LEN (*((PUINT16V)(0x40023448))) // endpoint 6 transmittal length(16-bits for ch32v10x) +#define R8_UEP6_CTRL (*((PUINT8V)(0x4002344a))) // endpoint 6 control + +#define R32_USB_EP7_CTRL (*((PUINT32V)(0x4002344c))) // endpoint 7 control & transmittal length +#define R16_UEP7_T_LEN (*((PUINT16V)(0x4002344c))) // endpoint 7 transmittal length(16-bits for ch32v10x) +#define R8_UEP7_CTRL (*((PUINT8V)(0x4002344e))) // endpoint 7 control + +/* ch32v10x_usb_host.h -----------------------------------------------------------*/ + +#define ERR_SUCCESS 0x00 +#define ERR_USB_CONNECT 0x15 +#define ERR_USB_DISCON 0x16 +#define ERR_USB_BUF_OVER 0x17 +#define ERR_USB_DISK_ERR 0x1F +#define ERR_USB_TRANSFER 0x20 +#define ERR_USB_UNSUPPORT 0xFB +#define ERR_USB_UNKNOWN 0xFE +#define ERR_AOA_PROTOCOL 0x41 + +#define ROOT_DEV_DISCONNECT 0 +#define ROOT_DEV_CONNECTED 1 +#define ROOT_DEV_FAILED 2 +#define ROOT_DEV_SUCCESS 3 +#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20) +#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30) +#define DEF_AOA_DEVICE 0xF0 +#define DEV_TYPE_UNKNOW 0xFF + +#define HUB_MAX_PORTS 4 +#define WAIT_USB_TOUT_200US 3000 + + +/* ch32v30x_usb.h ------------------------------------------------------------*/ + + +/* ch32x035_usbpd.h ----------------------------------------------------------*/ + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_EN (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_MASK (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_MASK (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_MASK (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_MASK (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_MASK (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CMP_MASK (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ +#define USBPD_IN_HVT (1<<9) + + +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +#define PIN_CC1 GPIO_Pin_14 +#define PIN_CC2 GPIO_Pin_15 + +/******************************************************************************/ + +#define UPD_TMR_TX (FUNCONF_SYSTEM_CORE_CLOCK / 600000 - 1) +#define UPD_TMR_RX (FUNCONF_SYSTEM_CORE_CLOCK / 400000 - 1) + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. + #define DMDATA0 ((volatile uint32_t*)0xe0000380) + #define DMDATA1 ((volatile uint32_t*)0xe0000384) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000388)// Reads as 0x00000000 if debugger is attached. + +// Determination of PLL multiplication factor for non-V003 chips + + + + +// Applies to all processors + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA1 1 +#define PA2 2 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +#define PA0 0 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/ch5xxhw.h b/inc/ch5xxhw.h new file mode 100644 index 0000000..7137356 --- /dev/null +++ b/inc/ch5xxhw.h @@ -0,0 +1,2645 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef CH5xx +#define CH5xx +#endif +#if defined(CH57x) && (MCU_PACKAGE == 0 || MCU_PACKAGE == 2) +#define CH570_CH572 +#elif defined(CH57x) && (MCU_PACKAGE == 1 || MCU_PACKAGE == 3) +#define CH571_CH573 +#elif defined(CH58x) && (MCU_PACKAGE == 2 || MCU_PACKAGE == 3) +#define CH582_CH583 +#elif defined(CH58x) && (MCU_PACKAGE == 4 || MCU_PACKAGE == 5) +#define CH584_CH585 +#elif defined(CH59x) && (MCU_PACKAGE == 1 || MCU_PACKAGE == 2) +#define CH591_CH592 +#endif + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + TMR0_IRQn = 16, /* TMR0 */ + GPIOA_IRQn = 17, /* GPIOA */ + GPIOB_IRQn = 18, /* GPIOB */ + SPI0_IRQn = 19, /* SPI0 */ + BB_IRQn = 20, /* BLEB */ + LLE_IRQn = 21, /* BLEL */ + USB_IRQn = 22, /* USB */ + USB2_IRQn = 23, /* USB2 */ + TMR1_IRQn = 24, /* TMR1 */ + TMR2_IRQn = 25, /* TMR2 */ + UART0_IRQn = 26, /* UART0 */ + UART1_IRQn = 27, /* UART1 */ + RTC_IRQn = 28, /* RTC */ + ADC_IRQn = 29, /* CMP */ + I2C_IRQn = 30, /* I2C */ + PWMX_IRQn = 31, /* PWMX */ + TMR3_IRQn = 32, /* TMR3 */ + UART2_IRQn = 33, /* UART2 / KEYSCAN */ + UART3_IRQn = 34, /* UART3 / ENCODER */ + WDOG_BAT_IRQn = 35, /* WDOG_BAT */ + NFC_IRQn = 36, /* NFC_IRQn */ + USB2_DEVICE_IRQn = 37, /* USB2_DEVICE_IRQn */ + USB2_HOST_IRQn = 38, /* USB2_HOST_IRQn */ + LED_IRQn = 39, /* LED_IRQn */ +} IRQn_Type; + +#ifdef CH570_CH572 +#define TMR_IRQn TMR1_IRQn +#define SPI_IRQn SPI0_IRQn +#define UART_IRQn UART1_IRQn +#define CMP_IRQn ADC_IRQn +#define KEYSCAN_IRQn UART2_IRQn +#define ENCODER_IRQn UART3_IRQn +#endif + +#ifdef CH571_CH573 +#define WORD_OR_JUMP "j" +#else +#define WORD_OR_JUMP ".word" +#endif + +#define BASE_VECTOR "\n"\ + ".balign 2\n"\ + ".option push;\n"\ + ".option norvc;\n"\ + ISR_HANDLER_INITIAL_JUMP \ + ".word 0\n"\ + WORD_OR_JUMP " NMI_Handler /* NMI Handler */\n"\ + WORD_OR_JUMP " HardFault_Handler /* Hard Fault Handler */\n"\ + ".word 0xF3F9BDA9\n"\ + WORD_OR_JUMP " Ecall_M_Mode_Handler /* 5 */\n"\ + ".word 0\n"\ + ".word 0\n"\ + WORD_OR_JUMP " Ecall_U_Mode_Handler /* 8 */\n"\ + WORD_OR_JUMP " Break_Point_Handler /* 9 */\n"\ + ".word 0\n"\ + ".word 0\n"\ + WORD_OR_JUMP " SysTick_Handler /* SysTick Handler */\n"\ + ".word 0\n"\ + WORD_OR_JUMP " SW_Handler /* SW Handler */\n"\ + ".word 0\n"\ + "/* External Interrupts */\n"\ + WORD_OR_JUMP " TMR0_IRQHandler /* 16: TMR0 */\n"\ + WORD_OR_JUMP " GPIOA_IRQHandler /* GPIOA */\n"\ + WORD_OR_JUMP " GPIOB_IRQHandler /* GPIOB */\n"\ + WORD_OR_JUMP " SPI0_IRQHandler /* SPI0 */\n"\ + WORD_OR_JUMP " BB_IRQHandler /* BLEB */\n"\ + WORD_OR_JUMP " LLE_IRQHandler /* BLEL */\n"\ + WORD_OR_JUMP " USB_IRQHandler /* USB */\n"\ + ".word 0 \n"\ + WORD_OR_JUMP " TMR1_IRQHandler /* TMR1 */\n"\ + WORD_OR_JUMP " TMR2_IRQHandler /* TMR2 */\n"\ + WORD_OR_JUMP " UART0_IRQHandler /* UART0 */\n"\ + WORD_OR_JUMP " UART1_IRQHandler /* UART1 */\n"\ + WORD_OR_JUMP " RTC_IRQHandler /* RTC */\n"\ + WORD_OR_JUMP " ADC_IRQHandler /* ADC */\n"\ + WORD_OR_JUMP " I2C_IRQHandler /* I2C */\n"\ + WORD_OR_JUMP " PWMX_IRQHandler /* PWMX */\n"\ + WORD_OR_JUMP " TMR3_IRQHandler /* TMR3 */\n"\ + WORD_OR_JUMP " UART2_IRQHandler /* UART2 / KEYSCAN */\n"\ + WORD_OR_JUMP " UART3_IRQHandler /* UART3 / ENCODER */\n"\ + WORD_OR_JUMP " WDOG_BAT_IRQHandler /* WDOG_BAT */\n" + +#ifdef CH570_CH572 +#define TMR_IRQHandler TMR1_IRQHandler +#define SPI_IRQHandler SPI0_IRQHandler +#define UART_IRQHandler UART1_IRQHandler +#define CMP_IRQHandler ADC_IRQHandler +#define KEYSCAN_IRQHandler UART2_IRQHandler +#define ENCODER_IRQHandler UART3_IRQHandler +#endif + +#ifndef CH584_CH585 +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR "\n.option pop;\n" +#else +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR "\n"\ + WORD_OR_JUMP " NFC_IRQHandler /* NFC */\n"\ + WORD_OR_JUMP " USB2_DEVICE_IRQHandler /* USB2_DEVICE */\n"\ + WORD_OR_JUMP " USB2_HOST_IRQHandler /* USB2_HOST */\n"\ + WORD_OR_JUMP " LED_IRQHandler /* LED */\n"\ + ".option pop;\n" +#endif + +#define __HIGH_CODE __attribute__((section(".highcode"), used)) +#define __INTERRUPT __attribute__((interrupt)) +#ifdef CH571_CH573 +#define __DMA_SAFE __attribute__((section(".dma_safe"))) // Use with every buffer/array that will be passed to DMA on CH573 +#endif + + +/* memory mapped structure for SysTick */ +typedef struct __attribute__((packed)) +{ +#if (defined(CH570_CH572) || defined(CH584_CH585)) + __IO uint32_t CTLR; + __IO uint32_t SR; + union + { + __IO uint32_t CNT; + __IO uint32_t CNTL; + }; + uint8_t RESERVED[4]; + union + { + __IO uint32_t CMP; + __IO uint32_t CMPL; + }; + uint8_t RESERVED0[4]; +#elif defined(CH571_CH573) + __IO uint32_t CTLR; + __IO uint64_t CNT; + __IO uint64_t CMP; + __IO uint32_t CNTFG; +#else + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +#endif +} SysTick_Type; + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct +{ + __I uint32_t ISR[8]; // 0 + __I uint32_t IPR[8]; // 20H + __IO uint32_t ITHRESDR; // 40H + __IO uint32_t FIBADDRR; // 44H + __O uint32_t CFGR; // 48H + __I uint32_t GISR; // 4CH + __IO uint8_t VTFIDR[4]; // 50H (IDCFGR on ch582) + uint8_t RESERVED0[0x0C]; // 54H + __IO uint32_t VTFADDR[4]; // 60H (FIADDRR on ch582) + uint8_t RESERVED1[0x90]; // 70H + __O uint32_t IENR[8]; // 100H + uint8_t RESERVED2[0x60]; // 120H + __O uint32_t IRER[8]; // 180H + uint8_t RESERVED3[0x60]; // 1A0H + __O uint32_t IPSR[8]; // 200H + uint8_t RESERVED4[0x60]; // 220H + __O uint32_t IPRR[8]; // 280H + uint8_t RESERVED5[0x60]; // 2A0H + __IO uint32_t IACTR[8]; // 300H + uint8_t RESERVED6[0xE0]; // 320H + __IO uint8_t IPRIOR[256]; // 400H + uint8_t RESERVED7[0x810]; // 500H + __IO uint32_t SCTLR; // D10H +} PFIC_Type; +#endif /* __ASSEMBLER__*/ + +#ifdef __ASSEMBLER__ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define CORE_PERIPH_BASE ((uint32_t)(0xE0000000)) +#endif /* __ASSEMBLER__*/ + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + +#define PFIC ((PFIC_Type *) PFIC_BASE) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) SysTick_BASE) +#define SYSTICK_LOAD_RELOAD_MSK (0xFFFFFFFFFFFFFFFF) +#define SYSTICK_CTLR_SWIE (1 << 31) +#define SYSTICK_CTLR_INIT (1 << 5) +#define SYSTICK_CTLR_MODE (1 << 4) +#define SYSTICK_CTLR_STRE (1 << 3) +#define SYSTICK_CTLR_STCLK (1 << 2) +#define SYSTICK_CTLR_STIE (1 << 1) +#define SYSTICK_CTLR_STE (1 << 0) +#define SYSTICK_SR_CNTIF (1 << 0) + +typedef enum +{ +#ifdef CH570_CH572 + CLK_SOURCE_LSI = 0xC0, // WARNING: when using this the debug interface has issues (programming, infobytes, bootloader, everything!) + + CLK_SOURCE_HSE_16MHz = (0x02), + CLK_SOURCE_HSE_8MHz = (0x04), + CLK_SOURCE_HSE_6_4MHz = (0x05), + CLK_SOURCE_HSE_4MHz = (0x08), + CLK_SOURCE_HSE_2MHz = (0x10), + CLK_SOURCE_HSE_1MHz = (0x0), // WARNING: when using this the debug interface has issues (programming, infobytes, bootloader, everything!) + + CLK_SOURCE_PLL_100MHz = (0x40 | 6), + CLK_SOURCE_PLL_75MHz = (0x40 | 8), + CLK_SOURCE_PLL_60MHz = (0x40 | 10), + CLK_SOURCE_PLL_50MHz = (0x40 | 12), + CLK_SOURCE_PLL_40MHz = (0x40 | 15), + CLK_SOURCE_PLL_30MHz = (0x40 | 20), + CLK_SOURCE_PLL_25MHz = (0x40 | 24), + CLK_SOURCE_PLL_24MHz = (0x40 | 25), + CLK_SOURCE_PLL_20MHz = (0x40 | 30), +#elif defined(CH571_CH573) + CLK_SOURCE_LSI = 0x00, + CLK_SOURCE_LSE, + + CLK_SOURCE_HSE_8MHz = 0x24, + CLK_SOURCE_HSE_6_4MHz = 0x25, + CLK_SOURCE_HSE_4MHz = 0x28, + CLK_SOURCE_HSE_2MHz = (0x20 | 16), + CLK_SOURCE_HSE_1MHz = (0x20 | 0), + + CLK_SOURCE_PLL_60MHz = 0x48, + CLK_SOURCE_PLL_48MHz = (0x40 | 10), + CLK_SOURCE_PLL_40MHz = (0x40 | 12), + CLK_SOURCE_PLL_36_9MHz = (0x40 | 13), + CLK_SOURCE_PLL_32MHz = (0x40 | 15), + CLK_SOURCE_PLL_30MHz = (0x40 | 16), + CLK_SOURCE_PLL_24MHz = (0x40 | 20), + CLK_SOURCE_PLL_20MHz = (0x40 | 24), + CLK_SOURCE_PLL_15MHz = (0x40 | 0), +#elif defined(CH582_CH583) + CLK_SOURCE_LSI = 0x00, + CLK_SOURCE_LSE, + + CLK_SOURCE_HSE_16MHz = 0x22, + CLK_SOURCE_HSE_8MHz = 0x24, + CLK_SOURCE_HSE_6_4MHz = 0x25, + CLK_SOURCE_HSE_4MHz = 0x28, + CLK_SOURCE_HSE_2MHz = (0x20 | 16), + CLK_SOURCE_HSE_1MHz = (0x20 | 0), + + CLK_SOURCE_PLL_80MHz = 0x46, + CLK_SOURCE_PLL_60MHz = 0x48, + CLK_SOURCE_PLL_48MHz = (0x40 | 10), + CLK_SOURCE_PLL_40MHz = (0x40 | 12), + CLK_SOURCE_PLL_36_9MHz = (0x40 | 13), + CLK_SOURCE_PLL_32MHz = (0x40 | 15), + CLK_SOURCE_PLL_30MHz = (0x40 | 16), + CLK_SOURCE_PLL_24MHz = (0x40 | 20), + CLK_SOURCE_PLL_20MHz = (0x40 | 24), + CLK_SOURCE_PLL_15MHz = (0x40 | 0), +#elif defined(CH584_CH585) + CLK_SOURCE_32KHz = 0xC0, + + CLK_SOURCE_HSI_16MHz = (0x100 | 0x80), + CLK_SOURCE_HSI_8MHz = 0x02, + CLK_SOURCE_HSI_5_3MHz = 0x03, + CLK_SOURCE_HSI_4MHz = 0x04, + CLK_SOURCE_HSI_2MHz = 0x08, + CLK_SOURCE_HSI_1MHz = 0x10, + + CLK_SOURCE_HSE_32MHz = (0x100 | 0x200 | 0x80), + CLK_SOURCE_HSE_16MHz = (0x200 | 0x02), + CLK_SOURCE_HSE_8MHz = (0x200 | 0x04), + CLK_SOURCE_HSE_6_4MHz = (0x200 | 0x05), + CLK_SOURCE_HSE_4MHz = (0x200 | 0x08), + CLK_SOURCE_HSE_2MHz = (0x200 | 0x10), + + CLK_SOURCE_HSI_PLL_78MHz = (0x100 | 0x40 | 4), // RTC does not work at this speed, so low power sleep also not! + CLK_SOURCE_HSI_PLL_62_4MHz = (0x100 | 0x40 | 5), + CLK_SOURCE_HSI_PLL_52MHz = (0x100 | 0x40 | 6), + CLK_SOURCE_HSI_PLL_39MHz = (0x100 | 0x40 | 8), + CLK_SOURCE_HSI_PLL_26MHz = (0x100 | 0x40 | 12), + CLK_SOURCE_HSI_PLL_24MHz = (0x100 | 0x40 | 13), + CLK_SOURCE_HSI_PLL_19_5MHz = (0x100 | 0x40 | 16), + CLK_SOURCE_HSI_PLL_13MHz = (0x100 | 0x40 | 24), + + CLK_SOURCE_HSE_PLL_78MHz = (0x300 | 0x40 | 4), // RTC does not work at this speed, so low power sleep also not! + CLK_SOURCE_HSE_PLL_62_4MHz = (0x300 | 0x40 | 5), + #define CLK_SOURCE_PLL_60MHz "The ch584/5 does not support an exact 60MHz setting. Please pick an availabe clock source from the SYS_CLKTypeDef struct in ch5xxhw.h" + CLK_SOURCE_HSE_PLL_52MHz = (0x300 | 0x40 | 6), + CLK_SOURCE_HSE_PLL_39MHz = (0x300 | 0x40 | 8), + CLK_SOURCE_HSE_PLL_26MHz = (0x300 | 0x40 | 12), + CLK_SOURCE_HSE_PLL_24MHz = (0x300 | 0x40 | 13), + CLK_SOURCE_HSE_PLL_19_5MHz = (0x300 | 0x40 | 16), + CLK_SOURCE_HSE_PLL_13MHz = (0x300 | 0x40 | 24), +#elif defined(CH591_CH592) + CLK_SOURCE_LSI = 0x00, + CLK_SOURCE_LSE, + + CLK_SOURCE_HSE_16MHz = (0x20 | 2), + CLK_SOURCE_HSE_8MHz = (0x20 | 4), + CLK_SOURCE_HSE_6_4MHz = (0x20 | 5), + CLK_SOURCE_HSE_4MHz = (0x20 | 8), + + CLK_SOURCE_PLL_80MHz = (0x40 | 6), + CLK_SOURCE_PLL_60MHz = (0x40 | 8), + CLK_SOURCE_PLL_48MHz = (0x40 | 10), + CLK_SOURCE_PLL_32MHz = (0x40 | 15), + CLK_SOURCE_PLL_24MHz = (0x40 | 20), +#endif +} SYS_CLKTypeDef; + +// For debug writing to the debug interface, and USB ISP. +#if (defined(CH570_CH572) || defined(CH584_CH585)) +#define DMDATA0 ((vu32*)0xe0000340) +#define DMDATA1 ((vu32*)0xe0000344) +#define DMSTATUS_SENTINEL ((vu32*)0xe0000348) // Reads as 0x00000000 if debugger is attached. +#else +#define DMDATA0 ((vu32*)0xe0000380) +#define DMDATA1 ((vu32*)0xe0000384) +#define DMSTATUS_SENTINEL ((vu32*)0xe0000388) // Reads as 0x00000000 if debugger is attached. +#endif + +#ifdef CH570_CH572 +#define ISPROM_ADDRESS 0x0003c000 +#define ISPROM_IN_RAM_ADDRESS 0x20000000 +#define ISPROM_START_OFFSET 0xc0 +#define ISPROM_SIZE 0x2000 +#define ISPROM_BOOTBUTTON_CHECK_ADDRESS 0x20000100 +#define ISPROM_BSS_ADDRESS 0x20001ba0 +#define ISPROM_BSS_SIZE 0x0474 +#define ISPROM_IN_RAM_GLOBALPOINTER "0x20002398" // string because it goes into asm() +#define ISPROM_IN_RAM_ENTRYPOINT "0x20001196" // string because it goes into asm() +#elif defined(CH571_CH573) +#define ISPROM_ADDRESS 0x00078000 +#define ISPROM_IN_RAM_ADDRESS 0x20003800 // just a placeholder, this is not implemented yet for 571/3 +#define ISPROM_START_OFFSET 0x0 // just a placeholder, this is not implemented yet for 571/3 +#define ISPROM_SIZE 0x2500 +#elif defined(CH582_CH583) +#define ISPROM_ADDRESS 0x00078000 +#define ISPROM_IN_RAM_ADDRESS 0x20003800 +#define ISPROM_START_OFFSET 0xa4 +#define ISPROM_SIZE 0x2500 +#define ISPROM_BOOTBUTTON_CHECK_ADDRESS 0x200038b0 +#define ISPROM_GLOBALPOINTER "0x20006410" // string because it goes into asm() +#define ISPROM_ENTRYPOINT "0x00078064" // string because it goes into asm() +#elif defined(CH584_CH585) +#define ISPROM_ADDRESS 0x00078000 +#define ISPROM_IN_RAM_ADDRESS 0x20000000 +#define ISPROM_START_OFFSET 0x88 +#define ISPROM_SIZE 0x2500 +#define ISPROM_BOOTBUTTON_CHECK_ADDRESS 0x2000010a +#define ISPROM_BSS_ADDRESS 0x200024f0 +#define ISPROM_BSS_SIZE 0x0560 +#define ISPROM_IN_RAM_GLOBALPOINTER "0x20002ce8" // string because it goes into asm() +#define ISPROM_IN_RAM_ENTRYPOINT "0x200018c2" // string because it goes into asm() +#elif defined(CH591_CH592) +#define ISPROM_ADDRESS 0x00078000 +#define ISPROM_IN_RAM_ADDRESS 0x20003800 +#define ISPROM_START_OFFSET 0x94 +#define ISPROM_SIZE 0x2500 +#define ISPROM_BOOTBUTTON_CHECK_ADDRESS 0x20003998 +#define ISPROM_BSS_ADDRESS 0x20005cb8 +#define ISPROM_BSS_SIZE 0x0564 +#define ISPROM_IN_RAM_GLOBALPOINTER "0x200064b0" // string because it goes into asm() +#define ISPROM_IN_RAM_ENTRYPOINT "0x20004e8a" // string because it goes into asm() +#endif + +/* Independent watch-dog register */ +#define R32_IWDG_KR (*((vu32*)0x40001000)) // WO, watch-dog key register +#define R32_IWDG_CFG (*((vu32*)0x40001004)) // RW, watch-dog configuration +#define RB_RLR 0x0FFF // RW, watch-dog counter reload (write protect) +#define RB_PR 0x7000 // PR, prescale (write protect) +#define RB_PVU 0x8000 // RO, register update flag (write protect) +#define RB_COUNT 0xFF0000 // RO, watch-dog down counter +#define RB_STOP_EN 0x20000000 // RW, watch-dog stop enable (write protect) +#define RB_WR_PROTECT 0x40000000 // RO, write protect +#define RB_IWDG_EN 0x80000000 + +/* System: clock configuration register */ +#define R32_CLK_SYS_CFG (*((vu32*)0x40001008)) // RWA, system clock configuration, SAM +#define R16_CLK_SYS_CFG (*((vu16*)0x40001008)) // RWA, system clock configuration, SAM +#define R8_CLK_SYS_CFG (*((vu8*)0x40001008)) // RWA, system clock configuration, SAM +#define RB_CLK_SYS_MOD 0xC0 // RWA, system clock source mode: 00/10=divided from 32MHz, 01=divided from PLL-600MHz,11=directly from LSI +#define RB_CLK_PLL_DIV 0x1F // RWA, output clock divider from PLL or CK32M +#define RB_XROM_SCLK_SEL 0x0100 // RWA, XROM clk 624MHz selected +#define RB_OSC32M_SEL 0x0200 // RWA, PLL source clk external 32MHz selected +#define RB_PLL_GATE_DISS 0x1000 // RWA, PLL clk closed when source clk changed +#define RB_PLL_GATE_TIME 0x2000 // RWA, PLL clk time sel closed when source clk changed +#define RB_TX_32M_PWR_EN 0x40000 // RWA, extern 32MHz HSE power contorl +#define RB_PLL_PWR_EN 0x100000 // RWA, PLL power control +#define R8_HFCK_PWR_CTRL (*((vu8*)0x4000100A)) // RWA, power configuration for system high clock, SAM +#define RB_CLK_RC16M_PON 0x02 // RWA, enable RC16M OSC HSI +#define RB_CLK_XT32M_PON 0x04 // RWA, extern 32MHz HSE power contorl +#define RB_CLK_XT32M_KEEP 0x08 // RWA, RWA, disable auto closing when in halt mode +#define RB_CLK_PLL_PON 0x10 // RWA, PLL power control + + +/* System: sleep control register */ +#define R32_SLEEP_CONTROL (*((vu32*)0x4000100C)) // RWA, sleep control, SAM +#define R8_SLP_CLK_OFF0 (*((vu8*)0x4000100C)) // RWA, sleep clock off control byte 0, SAM +#define RB_SLP_CLK_TMR0 0x01 // RWA, close TMR0 clock +#define RB_SLP_CLK_TMR1 0x02 // RWA, close TMR1 clock +#define RB_SLP_CLK_TMR2 0x04 // RWA, close TMR2 clock +#define RB_SLP_CLK_TMR3 0x08 // RWA, close TMR3 clock +#define RB_SLP_CLK_UART0 0x10 // RWA, close UART0 clock +#define RB_SLP_CLK_UART1 0x20 // RWA, close UART1 clock +#define RB_SLP_CLK_UART2 0x40 // RWA, close UART2 clock +#define RB_SLP_CLK_UART3 0x80 // RWA, close UART3 clock +#ifdef CH570_CH572 +#define RB_SLP_CLK_TMR 0x01 // RWA, set 1 close TMR clock +#define RB_SLP_CLK_CMP 0x02 // RWA, set 1 close CMP clock +#define RB_SLP_CLK_UART 0x10 // RWA, set 1 close UART clock +#define RB_SLP_KEYSCAN_WAKE 0x80 // RWA, enable key_scan waking +#endif +#define R8_SLP_CLK_OFF1 (*((vu8*)0x4000100D)) // RWA, sleep clock off control byte 1, SAM +#define RB_SLP_CLK_SPI0 0x01 // RWA, close SPI0 clock +#define RB_SLP_CLK_SPI1 0x02 // RWA, close SPI1 clock +#define RB_CLK_OFF_AESCCM 0x02 // RWA, set 1 close AES_CCM clock (CH570/2) +#define RB_SLP_CLK_PWMX 0x04 // RWA, close PWMx clock +#define RB_SLP_CLK_I2C 0x08 // RWA, set 1 close I2C clock +#define RB_SLP_CLK_USB 0x10 // RWA, close USB clock +#define RB_SLP_CLK_LCD 0x40 // RWA, close LCD clock (ch592) +#define RB_SLP_CLK_BLE 0x80 // RWA, close BLE clock +#define R8_SLP_WAKE_CTRL (*((vu8*)0x4000100E)) // RWA, wake control, SAM +#define RB_SLP_USB_WAKE 0x01 // RWA, enable USB waking +#define RB_SLP_USB2_WAKE 0x02 // RWA, enable USB2 event waking +//#define RB_SLP_BLE_WAKE 0x04 // RWA, enable BLE waking +#define RB_GPIO_EDGE_WAKE 0x04 // RWA, enable GPIO edge waking,no mater rising or falling (ch584/5) +#define RB_SLP_RTC_WAKE 0x08 // RWA, enable RTC waking +#define RB_SLP_GPIO_WAKE 0x10 // RWA, enable GPIO waking +#define RB_SLP_BAT_WAKE 0x20 // RWA, enable BAT waking +#define RB_WAKE_EV_MODE 0x40 // RWA, event wakeup mode: 0=event keep valid for long time, 1=short pulse event +#ifdef CH571_CH573 +#define RB_WAKE_DELAY 0x80 // RWA, wakeup delay: 0=long time, 1=short time +#else +#define RB_GPIO_WAKE_MODE 0x80 // RWA, GPIO wakeup mode: RB_SLP_GPIO_EDGE_MODE=1,1=all edge , RB_SLP_GPIO_EDGE_MODE=0,1=rise edge;0=high level +#endif +#define R8_SLP_POWER_CTRL (*((vu8*)0x4000100F)) // RWA, peripherals power down control, SAM +//#define RB_SLP_USB_PWR_DN 0x01 // RWA, enable USB power down +//#define RB_SLP_BLE_PWR_DN 0x04 // RWA, enable BLE power down +#define RB_CLK_OFF_UTMI 0x04 // RWA, UTMI clk closed +#define RB_SLP_CLK_RAMX 0x10 // RWA, close main SRAM clock +#define RB_CLK_OFF_RAMR 0x20 // RWA, SRAM(RAM32K) clk closed +#ifdef CH570_CH572 +#define RB_WAKE_DLY_MOD 0x07 // RWA, wakeup wait time selection,FCLK + 48cycle == SCLK +// RB_WAKE_DLY_MOD select wakeup delay +// 000: short time, 3584 cycles+TSUHSE +// 001: short time, 512 cycles+TSUHSE +// 010: short time, 64 cycles+TSUHSE +// 011: short time, 1 cycles+TSUHSE +// 100: long time, 8191 cycles+TSUHSE +// 101: long time, 7168 cycles+TSUHSE +// 110: long time, 6144 cycles+TSUHSE +// 111: long time, 4096 cycles+TSUHSE +#define RB_RAM_RET_LV 0xC0 // RWA, SRAM retention voltage selection: 00=disable, 01=low power mode 1, 10=low power mode 2, 11=low power mode 3, +#else +#define RB_WAKE_DLY_MOD 0x03 // RWA, wakeup delay time selection +// RB_WAKE_DLY_MOD select wakeup delay +// 00: long time, 3590 cycles+TSUHSE +// 01: short time, 520 cycles+TSUHSE +// 10: shorter time, 70 cycles+TSUHSE +// 11: no delay, 8 cycles+TSUHSE +#define RB_SLP_CLK_RAM2K 0x20 // RWA, close retention 2KB SRAM clock +#define RB_RAM_RET_LV 0x40 // RWA, SRAM retention voltage selection: 0=normal, 1=low voltage for low power +#endif +#ifdef CH584_CH585 +#define R32_SAFE_MODE_CTRL (*((vu32*)0x40001010)) // RWA, safe mode control register +#define R8_SAFE_MODE_CTRL (*((vu8*)0x40001010)) // RWA, safe mode control register +#define RB_SAFE_AUTO_EN 0x01 // RWA, disable safe mode auto close +#define RB_XROM_312M_SEL 0x10 // RWA, XROM CLK 312MHz sel +#define R8_SAFE_CLK_CTRL (*((vu8*)0x40001011)) // RWA, main clk off control register +#define RB_CLK_OFF_NFC 0x01 // RWA, disable NFC main clock +#define RB_CLK_OFF_ADC 0x02 // RWA, disable ADC main clock +#define RB_CLK_OFF_LED 0x04 // RWA, disable LED main clock +#define R8_SAFE_DEBUG_CTRL (*((vu8*)0x40001012)) // RWA, DEBUG control register +#define RB_DEBUG_DIS 0x10 // RWA, disable DEBUG +#define R8_SAFE_LRST_CTRL (*((vu8*)0x40001013)) // RWA, long reset control register +#define RB_LONG_RST_EN 0x01 // RWA, long reset enable +#define RB_LONG_TIM_SEL 0x02 // RWA, long reser time 31ms sel +#define RB_IWDG_RST_EN 0x10 // RWA, iwdg rst with power on +#elif defined(CH591_CH592) +#define R32_SLEEP_CTRL2 (*((vu32*)0x40001010)) // RWA, touchkey wake up enable +#define RB_TKEY0_5_WAKE_EN 0x003F // RWA, touchkey wake up enable channel 0-5 +#define RB_TKEY8_13_WAKE_EN 0x3F00 // RWA, touchkey wake up enable channel 8-13 +#endif + +/* System: I/O pin configuration register */ +#define R32_PIN_CONFIG (*((vu32*)0x40001018)) // RW, I/O pin configuration +#define R16_PIN_ALTERNATE (*((vu16*)0x40001018)) // RW, function pin alternate configuration +#ifdef CH570_CH572 +#define RB_PA_DI_DIS 0x0FFF // RW, 1=disable PA input , 0=enable PA input +#define RB_UDP_PU_EN 0x1000 // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +#define RB_PIN_USB_EN 0x2000 // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define RB_PIN_DEBUG_EN 0x4000 // RW, debug interface enable +#else +#define RB_PIN_TMR0 0x01 // RW, TMR0 alternate pin enable: 0=TMR0/PWM0/CAP0 on PA[9], 1=TMR0_/PWM0_/CAP0_ on PB[23] +#define RB_PIN_TMR1 0x02 // RW, TMR1 alternate pin enable: 0=TMR1/PWM1/CAP1 on PA[10], 1=TMR1_/PWM1_/CAP1_ on PB[10] +#define RB_PIN_TMR2 0x04 // RW, TMR2 alternate pin enable: 0=TMR2/PWM2/CAP2 on PA[11], 1=TMR2_/PWM2_/CAP2_ on PB[11] +#define RB_PIN_TMR3 0x08 // RW, TMR3 alternate pin enable: 0=TMR3/PWM3/CAP3 on PA[2], 1=TMR3_/PWM3_/CAP3_ on PB[22] +#define RB_PIN_UART0 0x10 // RW, RXD0/TXD0 alternate pin enable: 0=RXD0/TXD0 on PB[4]/PB[7], 1=RXD0_/TXD0_ on PA[15]/PA[14] +#define RB_PIN_UART1 0x20 // RW, RXD1/TXD1 alternate pin enable: 0=RXD1/TXD1 on PA[8]/PA[9], 1=RXD1_/TXD1_ on PB[12]/PB[13] +#define RB_PIN_UART2 0x40 // RW, RXD2/TXD2 alternate pin enable: 0=RXD2/TXD2 on PA[6]/PA[7], 1=RXD2_/TXD2_ on PB[22]/PB[23] +#define RB_PIN_UART3 0x80 // RW, RXD3/TXD3 alternate pin enable: 0=RXD3/TXD3 on PA[4]/PA[5], 1=RXD3_/TXD3_ on PB[20]/PB[21] +#define RB_PIN_SPI0 0x100 // RW, SCS/SCK0/MOSI/MISO alternate pin enable: 0=SCS/SCK0/MOSI/MISO on PA[12]/PA[13]/PA[14]/PA[15], 1=SCS_/SCK0_/MOSI_/MISO_ on PB[12]/PB[13]/PB[14]/PB[15] +#define RB_PIN_PWMX 0x400 // RW, PWM4/PWM5/PWM7/PWM8/PWM9 alternate pin enable: 0=PWM4/5/7/8/9 on PA[12]/PA[13]/PB[4]/PB[6]/PB[7], 1=PWM4/5/7/8/9 on PA[6]/PA[7]/PB[1]/PB[2]/P[3] +#define RB_PIN_I2C 0x800 // RW, SCL/SDA alternate pin enable: 0=SCL/SDA on PB[13]/PB[12], 1=SCL_/SDA_ on PB[21]/PB[20] +#define RB_PIN_MODEM 0x1000 // RW, DSR/DTR alternate pin enable: 0=DSR/DTR on PB[1]/PB[5], 1=DSR_/DTR_ on PB[14]/PB[15] +#define RB_PIN_INTX 0x2000 // RW, interrupt INT24/INT25 alternate pin enable: 0=INT24/INT25 on PB[8]/PB[9], 1=INT24_/INT25_ on PB[22]/PB[23] +#define RB_PIN_U0_INV 0x4000 // RW, RXD0/RXD0_/TXD0/TXD0_ invert input/output enable: 0=normal input/output, 1=RXD invert input, TXD invert output +#define RB_RF_ANT_SW_EN 0x8000 // RW, RF antenna switch control output enable: 0=disable output, 1=output on PB[16]/PB[17]/PB[18]/PB[19]/PB[20]/PB[21] +#endif +#ifdef CH570_CH572 +#define R16_PIN_ALTERNATE_H (*((vu16*)0x4000101A)) // RW, function pin alternate configuration high word +#define RB_UART_RXD 0x0007 // RW, RXD alternate pin enable +#define RB_UART_TXD 0x0038 // RW, TXD alternate pin enable +#define RB_TMR_PIN 0x00C0 // RW, TIMER alternate pin enable +#define RB_SPI_CS 0x0100 // RW, SPI CS alternate pin enable +#define RB_I2C_PIN 0x0600 // RW, I2C alternate pin enable +#define RB_SPI_CLK 0x0800 // RW, SPI CLK alternate pin enable +#define RB_25M_EN 0x1000 // RW, CLK25M OUPUT enable +#elif defined(CH584_CH585) +#define R16_PIN_CONFIG (*((vu16*)0x4000101A)) // RW, functional pin enable and digital input disable +#define RB_PB16_8_SEL 0x10 // RW, interupt pin select,0=PB8, 1=PB16 +#define RB_PIN_USB2_EN 0x20 // RW, USB high speed comunication pin select, 0=PB12/13 not use, 1=PB12/13 used +#define RB_UDP_PU_EN 0x40 // RW, enable USB ud+ pin pulled upresistance , 0=control by RB_UC_DEV_PU_EN, 1=force pulled up +#define RB_PIN_USB_EN 0x80 // RW, enable USB fast speed pin, 0=PB10/PB11 not used, 1=PB10/PB11 used +#define RB_PBHx_IN_DIS 0xFF00 // RW, disable PB16-PB23 digital input +#else +#define R16_PIN_ANALOG_IE (*((vu16*)0x4000101A)) // RW, analog pin enable and digital input disable +#define RB_PIN_ADC8_9_IE 0x01 // RW, ADC/TouchKey channel 9/8 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC6_7_IE 0x02 // RW, ADC/TouchKey channel 7/6 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC10_IE 0x04 // RW, ADC/TouchKey channel 10 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC11_IE 0x08 // RW, ADC/TouchKey channel 11 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_USB2_DP_PU 0x10 // RW, USB2 UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +#define RB_PIN_USB2_IE 0x20 // RW, USB2 analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define RB_PIN_USB_DP_PU 0x40 // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +#define RB_PIN_USB_IE 0x80 // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +//#define RB_PIN_ADC8_9_IE 0x0100 // RW, ADC/TouchKey channel 9/8 digital input disable: 0=digital input enable, 1=digital input disable (ch571/3) +#define RB_PIN_ADC0_IE 0x0200 // RW, ADC/TouchKey channel 0 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC1_IE 0x0400 // RW, ADC/TouchKey channel 1 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC12_IE 0x0800 // RW, ADC/TouchKey channel 12 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC13_IE 0x1000 // RW, ADC/TouchKey channel 13 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_XT32K_IE 0x2000 // RW, external 32KHz oscillator digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC2_3_IE 0x4000 // RW, ADC/TouchKey channel 2/3 digital input disable: 0=digital input enable, 1=digital input disable +#define RB_PIN_ADC4_5_IE 0x8000 // RW, ADC/TouchKey channel 4/5 digital input disable: 0=digital input enable, 1=digital input disable +#endif +#ifdef CH584_CH585 +#define R32_PIN_IN_DIS (*((vu32*)0x4000101C)) // RW, I/O pin configuration +#define RB_PAx_IN_DIS 0x0000FFFF //disable PA0-15 port digital input +#define RB_PBLx_IN_DIS 0xFFFF0000 //disable PB0-15 port digital input +#elif defined(CH591_CH592) +#define R32_PIN_CONFIG2 (*((vu32*)0x4000101C)) // RW, I/O pin configuration +#define RB_PIN_PA4_15_DIS 0xFFF0 // RW, PA4-PA15 digital input disable +#define RB_PIN_PB0_DIS 0x10000 // RW, PB0 digital input disable +#define RB_PIN_PB4_DIS 0x100000 // RW, PB4 digital input disable +#define RB_PIN_PB6_7_DIS 0xC00000 // RW, PB6-PB7 digital input disable +#define RB_PIN_PB22_23_DIS 0x3000000 // RW, PB22-PB23 digital input disable +#define RB_PIN_PB10_15_DIS 0xFC000000 // RW, PB10-PB15 digital input disable +#elif defined(CH570_CH572) +#define R8_LONG_RST_CFG (*((vu8*)0x4000101C)) // RWA, long reset config, SAM +#define RB_LONG_RST_EN 0x01 // RW, long reset enable +#define RB_LONG_TIM_SEL 0x06 // RW, long reset time value selecet 11=32.768ms,10=25.000ms,01=20.000msm,00=15.000ms +#define R8_SLP_CLK_OFF2 (*((vu8*)0x4000101D)) // RWA, sleep clock off control byte 2, SAM +#define RB_CLK_OFF_XROM 0x01 // RW, 1=XROM 64M or 600M clk off +#define RB_CLK_OFF_DEBUG 0x02 // RW, 1=2wire debug clk off +#define RB_CLK_OFF_HCLK 0x10 // RW, 1=XROM hclk off +#define R16_SLP_WAKE_CFG (*((vu16*)0x4000101E)) // RWA, sleep clock aux register, SAM +#define RB_OSCCLK_RDY_KEEP 0x0001 // RWA, 1=force OSC READY when halt sleep , 0= OSC not READY when halt sleep +#define RB_PRECLK_CNT_EN 0x0010 // RWA, 1=need to wait until reach to wait time to release flck when wake up +#define RB_PRECLK_CNT_SEL 0x0060 // RWA, preclk count value sel,11=2048,101024,01= 512,00=256(actual time value = cnt * Fsys) +#define RB_ACAUTO_ENABLE 0x0100 // RWA, 1=enable safe register acess auto off,1=disable safe register acess auto off +#endif + +/* System: power management register */ +#define R32_POWER_MANAG (*((vu32*)0x40001020)) // RWA, power management register, SAM +#define R16_POWER_PLAN (*((vu16*)0x40001020)) // RWA, power plan before sleep instruction, SAM +#define RB_PWR_XROM 0x01 // RWA, power for flash ROM +#define RB_PWR_RAM2K 0x02 // RWA, power for retention 2KB SRAM +#define RB_PWR_CORE 0x04 // RWA, power retention for core and base peripherals +#define RB_PWR_EXTEND 0x08 // RWA, power retention for USB and BLE +#define RB_PWR_RAM16K 0x10 // RWA, power for main SRAM ch571/3 +#define RB_PWR_RAM24K 0x10 // RWA, power for main SRAM ch591/2 +#define RB_PWR_RAM30K 0x10 // RWA, power for main SRAM ch582/3 +#define RB_PWR_RAMX 0x10 // RWA, power for main SRAM, all CH5xx +#define RB_PWR_SYS_EN 0x80 // RWA, power for system +#define RB_PWR_LDO_EN 0x0100 // RWA, LDO enable +#define RB_PWR_LDO5V_EN 0x0100 // RWA, internal LDO5v enable,1=power by V5,0=power by VDD33 (ch570/2) +#define RB_PWR_DCDC_EN 0x0200 // RWA, DC/DC converter enable: 0=DC/DC disable and bypass, 1=DC/DC enable +#define RB_PWR_DCDC_PRE 0x0400 // RWA, DC/DC converter pre-enable +#define RB_XT_PRE_CFG 0x1800 // RWA, extern 32MHz HSE early wake up time configuration +#define RB_PWR_MUST_0 0x2000 // RWA, must write 0 +#define RB_XT_PRE_EN 0x4000 // RWA, extern 32MHz HSE early wake up enable, must be used with LSI/LSE +#define RB_PWR_PLAN_EN 0x8000 // RWA/WZ, power plan enable, auto clear after sleep executed +#define RB_PWR_MUST_0010 0x1000 // RWA, must write 0010 +#define R16_AUX_POWER_ADJ (*((vu16*)0x40001022)) // RWA, aux power adjust control, SAM +#define RB_ULPLDO_ADJ 0x0007 // RWA, Ultra-Low-Power LDO voltage adjust +#define RB_DCDC_CHARGE 0x0080 // RWA, DC/DC aux charge enable +#define RB_CFG_IVREF 0x0F00 // RWA, I/V reference config data +#define RB_IPU_TKEY_SEL 0xC000 // RWA, TouchKey wakeup + +/* System: battery detector register */ +#define R32_BATTERY_CTRL (*((vu32*)0x40001024)) // RWA, battery voltage detector, SAM +#define R8_BAT_DET_CTRL (*((vu8*)0x40001024)) // RWA, battery voltage detector control, SAM +#define RB_BAT_DET_EN 0x01 // RWA, battery voltage detector enable if RB_BAT_MON_EN=0 +#define RB_BAT_LOW_VTHX 0x01 // RWA, select monitor threshold voltage if RB_BAT_MON_EN=1 +#define RB_BAT_MON_EN 0x02 // RWA, battery voltage monitor enable under sleep mode +#define RB_BAT_LOWER_IE 0x04 // RWA, interrupt enable for battery lower voltage +#define RB_BAT_LOW_IE 0x08 // RWA, interrupt enable for battery low voltage +// request NMI interrupt if both RB_BAT_LOWER_IE and RB_BAT_LOW_IE enabled +#define R8_BAT_DET_CFG (*((vu8*)0x40001025)) // RWA, battery voltage detector configuration, SAM +#define RB_BAT_LOW_VTH 0x03 // RWA, select detector/monitor threshold voltage of battery voltage low +#define R8_BAT_STATUS (*((vu8*)0x40001026)) // RO, battery status +#define RB_BAT_STAT_LOWER 0x01 // RO, battery lower voltage status for detector, high action +#define RB_BAT_STAT_LOW 0x02 // RO, battery low voltage status for detector/monitor, high action + +/* System: 32KHz oscillator control register */ +#define R32_OSC32K_CTRL (*((vu32*)0x4000102C)) // RWA, 32KHz oscillator control, SAM +#define R16_INT32K_TUNE (*((vu16*)0x4000102C)) // RWA, internal 32KHz oscillator tune control, SAM +#ifdef CH571_CH573 +#define RB_INT32K_TUNE 0x0FFF // RWA, internal 32KHz oscillator frequency tune +#else +#define RB_INT32K_TUNE 0x1FFF // RWA, internal 32KHz oscillator frequency tune +#endif +#define R8_XT32K_TUNE (*((vu8*)0x4000102E)) // RWA, external 32KHz oscillator tune control, SAM +#define RB_XT32K_I_TUNE 0x03 // RWA, external 32KHz oscillator current tune: 00=75% current, 01=standard current, 10=150% current, 11=200% current for startup +#define RB_XT32K_C_LOAD 0xF0 // RWA, external 32KHz oscillator load capacitor tune: Cap = RB_XT32K_C_LOAD + 12pF +#define R8_CK32K_CONFIG (*((vu8*)0x4000102F)) // RWA, 32KHz oscillator configure +#define RB_CLK_XT32K_PON 0x01 // RWA, external 32KHz oscillator power on +#define RB_CLK_INT32K_PON 0x02 // RWA, internal 32KHz oscillator power on +#define RB_CLK_OSC32K_XT 0x04 // RWA, 32KHz oscillator source selection: 0=RC, 1=XT +#define RB_CLK_OSC32K_FILT 0x08 // RWA, internal 32KHz oscillator low noise mode disable: 0=enable, 1=disable +#define RB_32K_CLK_PIN 0x80 // RO, 32KHz oscillator clock pin status + +/* System: real-time clock register */ +#define R32_RTC_CTRL (*((vu32*)0x40001030)) // RWA, RTC control, SAM +#define R8_RTC_FLAG_CTRL (*((vu8*)0x40001030)) // RW, RTC flag and clear control +#define RB_RTC_TMR_CLR 0x10 // RW, set 1 to clear RTC timer action flag, auto clear +#define RB_RTC_TRIG_CLR 0x20 // RW, set 1 to clear RTC trigger action flag, auto clear +#define RB_RTC_TMR_FLAG 0x40 // RO, RTC timer action flag +#define RB_RTC_TRIG_FLAG 0x80 // RO, RTC trigger action flag +#define R8_RTC_MODE_CTRL (*((vu8*)0x40001031)) // RWA, RTC mode control, SAM +#define RB_RTC_TMR_MODE 0x07 // RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S +#define RB_RTC_IGNORE_B0 0x08 // RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0 +#define RB_RTC_TMR_EN 0x10 // RWA, RTC timer mode enable +#define RB_RTC_TRIG_EN 0x20 // RWA, RTC trigger mode enable +#define RB_RTC_LOAD_LO 0x40 // RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded +#define RB_RTC_LOAD_HI 0x80 // RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded +#define R32_RTC_TRIG (*((vu32*)0x40001034)) // RWA, RTC trigger value, SAM +#define R32_RTC_CNT_32K (*((vu32*)0x40001038)) // RO, RTC count based 32KHz +#define R16_RTC_CNT_32K (*((vu16*)0x40001038)) // RO, RTC count based 32KHz +#define R16_RTC_CNT_2S (*((vu16*)0x4000103A)) // RO, RTC count based 2 second +#define R32_RTC_CNT_DAY (*((vu32*)0x4000103C)) // RO, RTC count based one day, only low 14 bit + +#define RTC_MAX_COUNT 0xA8C00000 +#define RTC_FREQ 32000 // LSI +// #define RTC_FREQ 32768 // LSE +#define CLK_PER_US (1.0 / ((1.0 / RTC_FREQ) * 1000 * 1000)) +#define CLK_PER_MS (CLK_PER_US * 1000) +#define US_TO_RTC(us) ((uint32_t)((us) * CLK_PER_US + 0.5)) +#define MS_TO_RTC(ms) ((uint32_t)((ms) * CLK_PER_MS + 0.5)) +#define RTC_WAIT_TICKS(t) uint32_t rtcset = R32_RTC_CNT_32K +(t); while(R32_RTC_CNT_32K <= rtcset) +#define SLEEP_RTC_MIN_TIME US_TO_RTC(1000) +#define SLEEP_RTC_MAX_TIME (RTC_MAX_COUNT - 1000 * 1000 * 30) +#define WAKE_UP_RTC_MAX_TIME US_TO_RTC(1600) + +// The datasheet of ch570/2 refer to some registers differently. +// They should be defined in case the user is referring to the datasheet. +#define R16_RTC_CNT_LSI R16_RTC_CNT_32K +#define R16_RTC_CNT_DIV1 R16_RTC_CNT_2S +#define R8_LSI_CONFIG R8_CK32K_CONFIG +#define RB_CLK_LSI_PON RB_CLK_XT32K_PON + +/* System: safe accessing register */ +#define R32_SAFE_ACCESS (*((vu32*)0x40001040)) // RW, safe accessing +#define R8_SAFE_ACCESS_SIG (*((vu8*)0x40001040)) // WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode +#define RB_SAFE_ACC_MODE 0x03 // RO, current safe accessing mode: 11=safe/unlocked (SAM), other=locked (00..01..10..11) +#if (defined(CH571_CH573) || defined(CH584_CH585)) +#define RB_SAFE_ACC_ACT 0x08 // RO, indicate safe accessing on +#define RB_SAFE_ACC_TIMER 0x70 // RO, safe accessing mode closed +#else +#define RB_SAFE_ACC_ACT 0x04 // RO, indicate safe accessing on +#define RB_SAFE_ACC_TIMER 0xF8 // RO, safe accessing mode closed +#endif +#define SAFE_ACCESS_SIG1 0x57 // WO: safe accessing sign value step 1 +#define SAFE_ACCESS_SIG2 0xA8 // WO: safe accessing sign value step 2 +#define SAFE_ACCESS_SIG0 0x00 // WO: safe accessing sign value for disable +#define SYS_SAFE_ACCESS(a) do { R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG1; \ + R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG2; \ + asm volatile ("nop\nnop"); \ + {a} \ + R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG0; \ + asm volatile ("nop\nnop"); } while(0) + +#define R8_CHIP_ID (*((vu8*)0x40001041)) // RF, chip ID register +#define R8_SAFE_ACCESS_ID (*((vu8*)0x40001042)) // RF, safe accessing ID register +#define R8_WDOG_COUNT (*((vu8*)0x40001043)) // RW, watch-dog count, count by clock frequency Fsys/131072 + +/* System: global configuration register */ +#define R32_GLOBAL_CONFIG (*((vu32*)0x40001044)) // RW, global configuration +#define R8_RESET_STATUS (*((vu8*)0x40001044)) // RO, reset status +#define RB_RESET_FLAG 0x07 // RO: recent reset flag +#define RST_FLAG_SW 0x00 +#define RST_FLAG_RPOR 0x01 +#define RST_FLAG_WTR 0x02 +#define RST_FLAG_MR 0x03 +//#define RST_FLAG_GPWSM 0x04 // RO, power on reset flag during sleep/shutdown: 0=no power on reset during sleep/shutdown, 1=power on reset occurred during sleep/shutdown +#define RST_FLAG_GPWSM 0x05 +// RB_RESET_FLAG: recent reset flag +// 000 - SR, software reset, by RB_SOFTWARE_RESET=1 @RB_WDOG_RST_EN=0 +// 001 - RPOR, real power on reset +// 010 - WTR, watch-dog timer-out reset +// 011 - MR, external manual reset by RST pin input low +// 101 - GRWSM, global reset by waking under shutdown mode +// 1?? - LRW, power on reset occurred during sleep +#define R8_GLOB_ROM_CFG R8_RESET_STATUS // RWA, flash ROM configuration, SAM +#define RB_ROM_CODE_OFS 0x10 // RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x040000 +#define RB_ROM_CTRL_EN 0x20 // RWA, enable flash ROM control interface enable: 0=disable access, 1=enable access control register +#define RB_ROM_DATA_WE 0x40 // RWA, enable flash ROM data & code area being erase/write: 0=all writing protect, 1=enable data area program and erase +#ifdef CH570_CH572 +#define RB_ROM_CODE_WE 0xC0 // RWA, enable flash ROM code area being erase/write: 0=code writing protect, 1=enable code area program and erase +#else +#define RB_ROM_CODE_WE 0x80 // RWA, enable flash ROM code area being erase/write: 0=code writing protect, 1=enable code area program and erase +#endif +#define R8_GLOB_CFG_INFO (*((vu8*)0x40001045)) // RO, global configuration information and status +#define RB_CFG_ROM_READ 0x01 // RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer +#define RB_CFG_RESET_EN 0x04 // RO, manual reset input enable status +#define RB_CFG_BOOT_EN 0x08 // RO, boot-loader enable status +#define RB_CFG_DEBUG_EN 0x10 // RO, debug enable status +#define RB_BOOT_LOADER 0x20 // RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status +#define R8_RST_WDOG_CTRL (*((vu8*)0x40001046)) // RWA, reset and watch-dog control, SAM +#define RB_SOFTWARE_RESET 0x01 // WA/WZ, global software reset, high action, auto clear +#define RB_WDOG_RST_EN 0x02 // RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow +#define RB_WDOG_INT_EN 0x04 // RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable +#define RB_WDOG_INT_FLAG 0x10 // RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event) +#define R8_GLOB_RESET_KEEP (*((vu8*)0x40001047)) // RW, value keeper during global reset + +/*System: Miscellaneous Control register */ +#define R32_MISC_CTRL (*((vu32*)0x40001048)) // RWA, miscellaneous control register +#define R8_PLL_CONFIG (*((vu8*)0x4000104B)) // RWA, PLL configuration control, SAM +#ifdef CH584_CH585 +#define RB_PLL_CFG_DAT 0x3F // RWA, PLL configuration control, SAM +#else +#define RB_PLL_CFG_DAT 0x7F // RWA, PLL configuration control, SAM +#endif +#define RB_FLASH_IO_MOD 0x80 // RWA, flash ROM interface mode, SAM + +/* System: 32MHz oscillator control register */ +#define R32_OSC32M_CTRL (*((vu32*)0x4000104C)) // RWA, 32MHz oscillator control, SAM +#define R8_XT32M_TUNE (*((vu8*)0x4000104E)) // RWA, external 32MHz oscillator tune control, SAM +#define RB_XT32M_I_BIAS 0x03 // RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current +#ifdef CH584_CH585 +#define RB_XT32M_C_LOAD 0xF0 // RWA, external 32MHz oscillator load capacitor tune: if bit7 = 0,Cap = RB_XT32M_C_LOAD * 2 + 10pF,else if bit7 = 1,Cap = RB_XT32M_C_LOAD * 2 + 2pF, +#else +#define RB_XT32M_C_LOAD 0x70 // RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF +#endif + +/* System: oscillator frequency calibration register */ +#define R32_OSC_CALIB (*((vu32*)0x40001050)) // RWA, oscillator frequency calibration, SAM +#define R16_OSC_CAL_CNT (*((vu16*)0x40001050)) // RO, system clock count value for 32KHz 5 cycles +#define RB_OSC_CAL_CNT 0x3FFF // RO, system clock count value for LSI multi-cycles +#define RB_OSC_CAL_OV_CLR 0x4000 // RW1, indicate R8_OSC_CAL_OV_CNT not zero, set 1 to clear R8_OSC_CAL_OV_CNT +#define RB_OSC_CAL_IF 0x8000 // RW1, interrupt flag for oscillator capture end, set 1 to clear +#define R8_OSC_CAL_OV_CNT (*((vu8*)0x40001052)) // RO, oscillator frequency calibration overflow times +#define R8_OSC_CAL_CTRL (*((vu8*)0x40001053)) // RWA, oscillator frequency calibration control, SAM +#define RB_OSC_CNT_TOTAL 0x07 // RWA, total cycles mode for oscillator capture +// RB_OSC_CNT_TOTAL: select total cycles for oscillator capture +// 000: 1 +// 001: 2 +// 010: 4 +// 011: 32 +// 100: 64 +// 101: 128 +// 110: 1024 +// 111: 2047 +#define RB_OSC_CNT_HALT 0x08 // RO, calibration counter halt status: 0=counting, 1=halt for reading count value +#define RB_OSC_CAL_IE 0x10 // RWA, interrupt enable for oscillator capture end +#define RB_OSC_CNT_EN 0x20 // RWA, calibration counter enable +#define RB_OSC_CNT_END 0x40 // RWA, select oscillator capture end mode: 0=normal, 1=append 2 cycles +#define RB_CNT_CLR 0x80 // RWA, reset RB_OSC_CAL_CNT + +/* System: ADC and Touch-key register */ +#ifdef CH570_CH572 +/*system: CMP*/ +#define R32_CMP_CTRL (*((vu32*)0x40001054)) // RW, configuration for comparator, +#define R8_CMP_CTRL_0 (*((vu8*)0x40001054)) // RW, configuration for comparator0, +#define RB_CMP_EN 0x01 // RW, enable comparators +#define RB_CMP_CAP 0x02 // RW, connect COMP_output to be TIM_cap1_input +#define RB_CMP_SW 0x0C // RW, [0]comparator -channel input sel:1=PA7,0=PA3 ; [1]comparator +channel input sel: 1=COMP_VERF,0=PA2 +#define RB_CMP_NREF_LEVEL 0xF0 // RW, comparator negative end point Vref sel:1111=800mv,0000=50mv +#define R8_CMP_CTRL_1 (*((vu8*)0x40001055)) // RW, configuration for comparator1, +#define RB_CMP_IE 0x01 // RW, comparator interupt enable +#define RB_CMP_OUT_SEL 0x0C // RW, comparator output sel:11=rise edge,10=fall edge,01=low,00=high +#define R8_CMP_CTRL_2 (*((vu8*)0x40001056)) // RW, configuration for comparator2, +#define RB_CMP_IF 0x01 // RW1Z, comparator interupt flag +#define R8_CMP_CTRL_3 (*((vu8*)0x40001057)) // RW, configuration for comparator3, +#define RB_CMP_REAL_SIG 0x01 // RO, comparator current real siginal +#define RB_APR_OUT_CMP 0x02 // RO, comparator current output siginal +#define R32_SAFE_ACCESS_SIG2 (*((vu32*)0x40001058)) // RO, safe accessing sign register2, +#define RB_SAFE_AC_DIS 0x00100000 // RO, safe register auto disable flag,1=disable safe access auto off; 0=enable safe access auto off +#define RB_RD_PROTECT 0x00200000 // RO, flash read protecet flag,1=enable read project; 0=disable read project +#define RB_MANU_CFG_LOCK 0x00400000 // RO, vendor configuration word lock flag,1=locked; 0= not locked +#define RB_FLASH_HALTED 0x00800000 // RO, 2wire flash prohibited operation flag,1=prohibit operation; 0=allow operation +#define RB_FUN_MODE 0x07000000 // RO, function enable +/* KEYSCAN register */ +#define R16_KEY_SCAN_CTRL (*((vu16*)0x40001064)) // KEY SCAN control register +#define RB_SCAN_START_EN 0x0001 // RW, start key scan enable,1=enable 0=disable +#define RB_SCAN_CNT_END 0x000E // RW, set the times of the same key_scan value +#define RB_SCAN_CLK_DIV 0x00F0 // RW, divider value of scanning clock +#define RB_PIN_SCAN_EN 0x1F00 // RW, select which pin could be scaned, 1=enable 0=disable +#define RB_SCAN_1END_WAKE_EN 0x2000 // RW, wake up chip after 1 round of key scanning, 1=enable 0=disable +#define RB_CLR_WAKEUP_EN 0x4000 // RW, claer wake_up siginal after chip wakeing up, 1=enable 0=disable +#define R8_KEY_SCAN_INT_EN (*((vu8*)0x40001066)) // KEY SCAN interupt enable register +#define RB_KEY_PRESSED_IE 0x01 // RW, detect key pressed interupt enable +#define RB_SCAN_1END_IE 0x02 // RW, key scan 1 round end interupt enable +#define R8_KEY_SCAN_INT_FLAG (*((vu8*)0x40001067)) // KEY SCAN interupt flag register +#define RB_KEY_PRESSED_IF 0x01 // RW1, detect key pressed flag enable +#define RB_SCAN_1END_IF 0x02 // RW1, key scan 1 round end flag enable +#define R32_KEY_SCAN_NUMB (*((vu32*)0x40001068)) // SCAN_KEY number address now register +#define RB_KEY_SCAN_CNT 0x700000 // current SCAN_KEY times +#define RB_KEY_SCAN_NUMB 0x0FFFFF // SCAN_KEY number address now +#else +#define R32_ADC_CTRL (*((vu32*)0x40001058)) // RW, ADC control +#define R8_ADC_CHANNEL (*((vu8*)0x40001058)) // RW, ADC input channel selection +#ifdef CH584_CH585 +#define RB_ADC_CH_INX 0x1F // RW, ADC input channel index, 00~0D=A0~13, 0E=VBAT, 0F=TS, 10=NFC energy check channel +#else +#define RB_ADC_CH_INX 0x0F // RW, ADC input channel index +#endif +#define R8_ADC_CFG (*((vu8*)0x40001059)) // RW, ADC configure +#define RB_ADC_POWER_ON 0x01 // RW, ADC power control: 0=power down, 1=power on +#define RB_ADC_BUF_EN 0x02 // RW, ADC input buffer enable +#define RB_ADC_DIFF_EN 0x04 // RW, ADC input channel mode: 0=single-end, 1=differnetial +#define RB_ADC_OFS_TEST 0x08 // RW, enable ADC offset test mode: 0=normal mode, 1=short AIN7 to test offset +#define RB_ADC_PGA_GAIN 0x30 // RW, set ADC input PGA gain: 00=-12dB, 01=-6dB, 10=0dB, 11=6dB +#define RB_ADC_CLK_DIV 0xC0 // RW, select ADC clock frequency: 00=3.2MHz, 01=8MHz, 10=5.33MHz, 11=4MHz +#define R8_ADC_CONVERT (*((vu8*)0x4000105A)) // RW, ADC convert control +#define RB_ADC_START 0x01 // RW, ADC convert start control: 0=stop ADC convert, 1=start an ADC convert, auto clear +#define RB_ADC_PGA_GAIN2 0x02 // RW, ADC gain direction, must be 0 when using TS +#define RB_ADC_EOC_X 0x80 // RO, end of ADC conversion flag +#define R8_TEM_SENSOR (*((vu8*)0x4000105B)) // RW, temperature sensor control +#define RB_TEM_SEN_PWR_ON 0x80 // RW, temperature sensor power control: 0=power down, 1=power on +#define R32_ADC_DATA (*((vu32*)0x4000105C)) // RO, ADC data and status +#define R16_ADC_DATA (*((vu16*)0x4000105C)) // RO, ADC data +#define RB_ADC_DATA 0x0FFF // RO, ADC conversion data +#define R8_ADC_INT_FLAG (*((vu8*)0x4000105E)) // RO, ADC interrupt flag register +#define RB_ADC_IF_EOC 0x80 // RO, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, auto ADC or write R8_ADC_CONVERT or write R8_TKEY_CONVERT to clear flag +#define R32_TKEY_CTRL (*((vu32*)0x40001054)) // RW, Touchkey control +#define R8_TKEY_COUNT (*((vu8*)0x40001054)) // RW, Touchkey charge and discharge count +#define RB_TKEY_CHARG_CNT 0x1F // RW, Touchkey charge count +#define RB_TKEY_DISCH_CNT 0xE0 // RW, Touchkey discharge count +#define R8_TKEY_CONVERT (*((vu8*)0x40001056)) // RW, Touchkey convert control +#define RB_TKEY_START 0x01 // RW, Touchkey convert start control: 0=stop Touchkey convert, 1=start a Touchkey convert, auto clear +#define R8_TKEY_CFG (*((vu8*)0x40001057)) // RW, Touchkey configure +#define RB_TKEY_PWR_ON 0x01 // RW, Touchkey power on: 0=power down, 1=power on +#define RB_TKEY_CURRENT 0x02 // RW, Touchkey charge current selection: 0=35uA, 1=70uA +#define RB_TKEY_DRV_EN 0x04 // RW, Touchkey drive shield enable +#define RB_TKEY_PGA_ADJ 0x08 // RW, ADC input PGA speed selection: 0=slow, 1=fast +#define RB_TKEY_AUTO_EN 0x20 // RW, Touchkey auto-trigger enable +#ifdef CH584_CH585 // this is sus +#define RB_TKEY_RAND_EN 0x10 // RW, Touchkey random trigger enable +#define RB_TKEY_DMA_EN 0x40 // RW, Touchkey DMA enable +#else +#define RB_TKEY_DMA_EN 0x10 // RW, Touchkey DMA enable +#define RB_TKEY_RAND_EN 0x40 // RW, Touchkey random trigger enable +#endif +#define R32_ADC_DMA_CTRL (*((vu32*)0x40001060)) // RW, ADC DMA control +#define R8_ADC_CTRL_DMA (*((vu8*)0x40001061)) // RW, ADC DMA control +#define RB_ADC_DMA_ENABLE 0x01 // RW, ADC DMA enable +#define RB_ADC_DMA_LOOP 0x04 // RW, ADC DMA address loop enable +#define RB_ADC_IE_DMA_END 0x08 // RW, enable interrupt for ADC DMA completion +#define RB_ADC_IE_EOC 0x10 // RW, enable interrupt for end of ADC conversion +#define RB_ADC_CONT_EN 0x40 // RW, enable contineous conversion ADC +#define RB_ADC_AUTO_EN 0x80 // RW, enable auto continuing ADC for DMA +#define R8_ADC_DMA_IF (*((vu8*)0x40001062)) // RW1, ADC interrupt flag +#define RB_ADC_IF_DMA_END 0x08 // RW1, interrupt flag for ADC DMA completion +#define RB_ADC_IF_END_ADC 0x10 // RW1, interrupt flag for end of ADC conversion, DMA for auto ADC or write R8_ADC_CONVERT to clear flag +#define R8_ADC_AUTO_CYCLE (*((vu8*)0x40001063)) // RW, auto ADC cycle value, unit is 16 Fsys +#define R32_ADC_DMA_NOW (*((vu32*)0x40001064)) // RW, ADC DMA current address +#define R16_ADC_DMA_NOW (*((vu16*)0x40001064)) // RW, ADC DMA current address +#define R32_ADC_DMA_BEG (*((vu32*)0x40001068)) // RW, ADC DMA begin address +#define R16_ADC_DMA_BEG (*((vu16*)0x40001068)) // RW, ADC DMA begin address +#define R32_ADC_DMA_END (*((vu32*)0x4000106C)) // RW, ADC DMA end address +#define R16_ADC_DMA_END (*((vu16*)0x4000106C)) // RW, ADC DMA end address +#ifdef CH584_CH585 +#define R32_ADC_SCAN_CFG1 (*((vu32*)0x40001070)) // RW, ADC channel scan config +#define RB_ADC_SCAN_CH1 0x000F // RW, channel1 analog input channel select +#define RB_ADC_SCAN_CH2 0x00F0 // RW, channel2 analog input channel select +#define RB_ADC_SCAN_CH3 0x0F00 // RW, channel3 analog input channel select +#define RB_ADC_SCAN_CH4 0xF000 // RW, channel4 analog input channel select +#define RB_ADC_SCAN_CH5 0x000F0000 // RW, channel5 analog input channel select +#define RB_ADC_SCAN_CH6 0x00F00000 // RW, channel6 analog input channel select +#define RB_ADC_SCAN_CH7 0x0F000000 // RW, channel7 analog input channel select +#define RB_ADC_SCAN_CH8 0xF0000000 // RW, channel8 analog input channel select +#define R32_ADC_SCAN_CFG2 (*((vu32*)0x40001074)) // RW, ADC channel scan config +#define RB_ADC_SCAN_CH9 0x000F // RW, channel9 analog input channel select +#define RB_ADC_SCAN_CH10 0x00F0 // RW, channel10 analog input channel select +#define RB_ADC_SCAN_CH11 0x0F00 // RW, channel11 analog input channel select +#define RB_ADC_SCAN_CH12 0xF000 // RW, channel12 analog input channel select +#define RB_ADC_SCAN_CH13 0x000F0000 // RW, channel13 analog input channel select +#define RB_ADC_SCAN_NUM 0x0F000000 // RW, ADC scan number +#define RB_ADC_SCAN_SEL 0x10000000 // RW, ADC scan select, 0=TKEY, 1=ADC +#define RB_ADC_IE_SCAN_END 0x20000000 // RW, enable ADC scan end interupt +#define RB_ADC_SCAN_MASK_DIS 0x40000000 // RW, disble ADC channel when sample end +#define RB_ADC_IF_SCAN_END 0x80000000 // RW, clear when RB_ADC_IF_SCAN_END = 1 +#define R32_TKEY_SEL (*((vu32*)0x4000107C)) // RW, Touchkey sel +#define RB_TKEY_DRV_OUTEN 0xFFFC0000 // RW, Touchkey multi_drive shields each channel,high enable +#endif // CH584_CH585 +#endif + +/* System: GPIO interrupt control register */ +#define R32_GPIO_INT_EN (*((vu32*)0x40001090)) // RW, GPIO interrupt enable +#define R16_PA_INT_EN (*((vu16*)0x40001090)) // RW, GPIO PA interrupt enable +#define R16_PB_INT_EN (*((vu16*)0x40001092)) // RW, GPIO PB interrupt enable +#define R32_GPIO_INT_MODE (*((vu32*)0x40001094)) // RW, GPIO interrupt mode: 0=level action, 1=edge action +#define R16_PA_INT_MODE (*((vu16*)0x40001094)) // RW, GPIO PA interrupt mode: 0=level action, 1=edge action +#define R16_PB_INT_MODE (*((vu16*)0x40001096)) // RW, GPIO PB interrupt mode: 0=level action, 1=edge action +#define R32_GPIO_INT_IF (*((vu32*)0x4000109C)) // RW1, GPIO interrupt flag +#define R16_PA_INT_IF (*((vu16*)0x4000109C)) // RW1, GPIO PA interrupt flag +#define R16_PB_INT_IF (*((vu16*)0x4000109E)) // RW1, GPIO PB interrupt flag + +/* GPIO PA register */ +#define R32_PA_DIR (*((vu32*)0x400010A0)) // RW, GPIO PA I/O direction: 0=in, 1=out +#define R32_PA_PIN (*((vu32*)0x400010A4)) // RO, GPIO PA input +#define R32_PA_OUT (*((vu32*)0x400010A8)) // RW, GPIO PA output +#define R32_PA_CLR (*((vu32*)0x400010AC)) // WZ, GPIO PA clear output: 0=keep, 1=clear +#define R32_PA_PU (*((vu32*)0x400010B0)) // RW, GPIO PA pullup resistance enable +#define R32_PA_PD_DRV (*((vu32*)0x400010B4)) // RW, PA pulldown for input or PA driving capability for output +#define R32_PA_SET (*((vu32*)0x400010B8)) // RW, PA set high for output ,1=set output high,0=IDLE + +#ifndef CH570_CH572 +/* GPIO PB register */ +#define R32_PB_DIR (*((vu32*)0x400010C0)) // RW, GPIO PB I/O direction: 0=in, 1=out +#define R32_PB_PIN (*((vu32*)0x400010C4)) // RO, GPIO PB input +#define R32_PB_OUT (*((vu32*)0x400010C8)) // RW, GPIO PB output +#define R32_PB_CLR (*((vu32*)0x400010CC)) // WZ, GPIO PB clear output: 0=keep, 1=clear +#define R32_PB_PU (*((vu32*)0x400010D0)) // RW, GPIO PB pullup resistance enable +#define R32_PB_PD_DRV (*((vu32*)0x400010D4)) // RW, PB pulldown for input or PB driving capability for output +#define R32_PB_SET (*((vu32*)0x400010D8)) // RW, PB set high for output ,1=set output high,0=IDLE +#endif + +#define PA0 (0x00000001) /*!< Pin 0 selected */ +#define PA1 (0x00000002) /*!< Pin 1 selected */ +#define PA2 (0x00000004) /*!< Pin 2 selected */ +#define PA3 (0x00000008) /*!< Pin 3 selected */ +#define PA4 (0x00000010) /*!< Pin 4 selected */ +#define PA5 (0x00000020) /*!< Pin 5 selected */ +#define PA6 (0x00000040) /*!< Pin 6 selected */ +#define PA7 (0x00000080) /*!< Pin 7 selected */ +#define PA8 (0x00000100) /*!< Pin 8 selected */ +#define PA9 (0x00000200) /*!< Pin 9 selected */ +#define PA10 (0x00000400) /*!< Pin 10 selected */ +#define PA11 (0x00000800) /*!< Pin 11 selected */ +#define PA12 (0x00001000) /*!< Pin 12 selected */ +#define PA13 (0x00002000) /*!< Pin 13 selected */ +#define PA14 (0x00004000) /*!< Pin 14 selected */ +#define PA15 (0x00008000) /*!< Pin 15 selected */ + +#ifndef CH570_CH572 +#define PB (0x80000000) /* Bit mask to indicate bank B */ +#define PB0 (0x80000001) /*!< Pin 0 selected */ +#define PB1 (0x80000002) /*!< Pin 1 selected */ +#define PB2 (0x80000004) /*!< Pin 2 selected */ +#define PB3 (0x80000008) /*!< Pin 3 selected */ +#define PB4 (0x80000010) /*!< Pin 4 selected */ +#define PB5 (0x80000020) /*!< Pin 5 selected */ +#define PB6 (0x80000040) /*!< Pin 6 selected */ +#define PB7 (0x80000080) /*!< Pin 7 selected */ +#define PB8 (0x80000100) /*!< Pin 8 selected */ +#define PB9 (0x80000200) /*!< Pin 9 selected */ +#define PB10 (0x80000400) /*!< Pin 10 selected */ +#define PB11 (0x80000800) /*!< Pin 11 selected */ +#define PB12 (0x80001000) /*!< Pin 12 selected */ +#define PB13 (0x80002000) /*!< Pin 13 selected */ +#define PB14 (0x80004000) /*!< Pin 14 selected */ +#define PB15 (0x80008000) /*!< Pin 15 selected */ +#define PB16 (0x80010000) /*!< Pin 16 selected */ +#define PB17 (0x80020000) /*!< Pin 17 selected */ +#define PB18 (0x80040000) /*!< Pin 18 selected */ +#define PB19 (0x80080000) /*!< Pin 19 selected */ +#define PB20 (0x80100000) /*!< Pin 20 selected */ +#define PB21 (0x80200000) /*!< Pin 21 selected */ +#define PB22 (0x80400000) /*!< Pin 22 selected */ +#define PB23 (0x80800000) /*!< Pin 23 selected */ +#endif +#define P_All (0xFFFFFFFF) /*!< All pins selected */ + +typedef enum +{ + GPIO_ModeIN_Floating, + GPIO_ModeIN_PU, + GPIO_ModeIN_PD, + GPIO_ModeOut_PP_5mA, + GPIO_ModeOut_PP_20mA, +} GPIOModeTypeDef; + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_FLOAT = GPIO_ModeIN_Floating, + GPIO_CFGLR_IN_PUPD = GPIO_ModeIN_PU, // is most common + GPIO_CFGLR_IN_PU = GPIO_ModeIN_PU, + GPIO_CFGLR_IN_PD = GPIO_ModeIN_PD, // to suppress the -Wswitch warning + GPIO_CFGLR_OUT_10Mhz_PP = GPIO_ModeOut_PP_20mA, + GPIO_CFGLR_OUT_2Mhz_PP = GPIO_ModeOut_PP_5mA, + GPIO_CFGLR_OUT_50Mhz_PP = GPIO_ModeOut_PP_20mA, +} GPIO_CFGLR_PIN_MODE_Typedef; + +/* System: Flash ROM control register */ +#define R32_FLASH_DATA (*((vu32*)0x40001800)) // RO/WO, flash ROM data + +// bit 24..26 flash wait states +// bit 12 = flash very slow. +#define R32_FLASH_CONTROL (*((vu32*)0x40001804)) // RW, flash ROM control, byte1 and byte3 need RWA + +#define R8_FLASH_DATA (*((vu8*)0x40001804)) // RO/WO, flash ROM data buffer +#define R8_FLASH_SCK (*((vu8*)0x40001805)) // RW, flash ROM sck time config +#define R8_FLASH_CTRL (*((vu8*)0x40001806)) // RW, flash ROM access control +#define R8_FLASH_CFG (*((vu8*)0x40001807)) // RWA, flash ROM access config, SAM + +#ifdef CH570_CH572 +/* Timer1 register */ +#define R32_TMR_CONTROL (*((vu32*)0x40002400)) // RW, TMR control +#define R8_TMR_CTRL_MOD (*((vu8*)0x40002400)) // RW, TMR mode control +#define R8_TMR_CTRL_DMA (*((vu8*)0x40002401)) // RW, TMR DMA control +#define R8_TMR_INTER_EN (*((vu8*)0x40002402)) // RW, TMR interrupt enable +// #define R32_TMR_STATUS (*((vu32*)0x40002404)) // RW, TMR status +#define R8_TMR_INT_FLAG (*((vu8*)0x40002406)) // RW1, TMR interrupt flag +#define R8_TMR_FIFO_COUNT (*((vu8*)0x40002407)) // RO, TMR FIFO count status +#define R32_TMR_COUNT (*((vu32*)0x40002408)) // RO, TMR current count +#define R16_TMR_COUNT (*((vu16*)0x40002408)) // RO, TMR current count +#define R8_TMR_COUNT (*((vu8*)0x40002408)) // RO, TMR current count +#define R32_TMR_CNT_END (*((vu32*)0x4000240C)) // RW, TMR end count value, only low 26 bit +#define R32_TMR_FIFO (*((vu32*)0x40002410)) // RO/WO, TMR FIFO register, only low 26 bit +#define R16_TMR_FIFO (*((vu16*)0x40002410)) // RO/WO, TMR FIFO register +#define R8_TMR_FIFO (*((vu8*)0x40002410)) // RO/WO, TMR FIFO register +#define R32_TMR_DMA_NOW (*((vu32*)0x40002414)) // RW, TMR DMA current address +#define R16_TMR_DMA_NOW (*((vu16*)0x40002414)) // RW, TMR DMA current address +#define R32_TMR_DMA_BEG (*((vu32*)0x40002418)) // RW, TMR DMA begin address +#define R16_TMR_DMA_BEG (*((vu16*)0x40002418)) // RW, TMR DMA begin address +#define R32_TMR_DMA_END (*((vu32*)0x4000241C)) // RW, TMR DMA end address +#define R16_TMR_DMA_END (*((vu16*)0x4000241C)) // RW, TMR DMA end address +/* ENCODER register */ +#define R32_ENC_REG_CTRL (*((vu32*)0x40002420)) +#define R8_ENC_REG_CTRL (*((vu8*)0x40002420)) // RW, ENCODER control register +// #define RB_WAKEUP_CLR_EN 0x10 // RW, clear wake_up siginal after chip wake up enable +#define RB_ENC_DIR 0x20 // RO, encoder director,0=forward,1=backward +#define RB_RD_CLR_EN 0x08 // RW, clear encoder count value after R32_ENC_REG_CCNT be read +#define RB_SMS_MODE 0x06 // RW, SMS mode value,10=T1EDGE,01=T2EDGE,11=T12EDGE +#define RB_START_ENC_EN 0x01 // RW, start encode enable +#define R8_ENC_INTER_EN (*((vu8*)0x40002421)) // RW, ENCODER interupt enable register +#define RB_IE_DIR_DEC 0x02 // RW, encode decrease interupt enable +#define RB_IE_DIR_INC 0x01 // RW, encode increase interupt enable +#define R8_ENC_INT_FLAG (*((vu8*)0x40002422)) // RW, ENCODER interupt flag register +#define RB_IF_DIR_DEC 0x02 // RWA, encode decrease interupt flag +#define RB_IF_DIR_INC 0x01 // RWA, encode increase interupt flag +#define R32_ENC_REG_CEND (*((vu32*)0x40002424)) +#define R32_ENC_REG_CCNT (*((vu32*)0x40002428)) +#define BA_TMR ((vu8*)0x40002400) // point TMR base address +#else + +/* Timer0 register */ +#define R32_TMR0_CONTROL (*((vu32*)0x40002000)) // RW, TMR0 control +#define R8_TMR0_CTRL_MOD (*((vu8*)0x40002000)) // RW, TMR0 mode control +#define R8_TMR0_CTRL_DMA (*((vu8*)0x40002001)) // RW, TMR0 DMA control +#define R8_TMR0_INTER_EN (*((vu8*)0x40002002)) // RW, TMR0 interrupt enable +#define R32_TMR0_STATUS (*((vu32*)0x40002004)) // RW, TMR0 status +#define R8_TMR0_INT_FLAG (*((vu8*)0x40002006)) // RW1, TMR0 interrupt flag +#define R8_TMR0_FIFO_COUNT (*((vu8*)0x40002007)) // RO, TMR0 FIFO count status +#define R32_TMR0_COUNT (*((vu32*)0x40002008)) // RO, TMR0 current count +#define R16_TMR0_COUNT (*((vu16*)0x40002008)) // RO, TMR0 current count +#define R8_TMR0_COUNT (*((vu8*)0x40002008)) // RO, TMR0 current count +#define R32_TMR0_CNT_END (*((vu32*)0x4000200C)) // RW, TMR0 end count value, only low 26 bit +#define R32_TMR0_FIFO (*((vu32*)0x40002010)) // RO/WO, TMR0 FIFO register, only low 26 bit +#define R16_TMR0_FIFO (*((vu16*)0x40002010)) // RO/WO, TMR0 FIFO register +#define R8_TMR0_FIFO (*((vu8*)0x40002010)) // RO/WO, TMR0 FIFO register +#define R32_TMR0_DMA_NOW (*((vu32*)0x40002014)) // RW, TMR0 DMA current address +#define R32_TMR0_DMA_BEG (*((vu32*)0x40002018)) // RW, TMR0 DMA begin address +#define R32_TMR0_DMA_END (*((vu32*)0x4000201C)) // RW, TMR0 DMA end address + +/* Timer1 register */ +#define R32_TMR1_CONTROL (*((vu32*)0x40002400)) // RW, TMR1 control +#define R8_TMR1_CTRL_MOD (*((vu8*)0x40002400)) // RW, TMR1 mode control +#define R8_TMR1_CTRL_DMA (*((vu8*)0x40002401)) // RW, TMR1 DMA control +#define R8_TMR1_INTER_EN (*((vu8*)0x40002402)) // RW, TMR1 interrupt enable +#define R32_TMR1_STATUS (*((vu32*)0x40002404)) // RW, TMR1 status +#define R8_TMR1_INT_FLAG (*((vu8*)0x40002406)) // RW1, TMR1 interrupt flag +#define R8_TMR1_FIFO_COUNT (*((vu8*)0x40002407)) // RO, TMR1 FIFO count status +#define R32_TMR1_COUNT (*((vu32*)0x40002408)) // RO, TMR1 current count +#define R16_TMR1_COUNT (*((vu16*)0x40002408)) // RO, TMR1 current count +#define R8_TMR1_COUNT (*((vu8*)0x40002408)) // RO, TMR1 current count +#define R32_TMR1_CNT_END (*((vu32*)0x4000240C)) // RW, TMR1 end count value, only low 26 bit +#define R32_TMR1_FIFO (*((vu32*)0x40002410)) // RO/WO, TMR1 FIFO register, only low 26 bit +#define R16_TMR1_FIFO (*((vu16*)0x40002410)) // RO/WO, TMR1 FIFO register +#define R8_TMR1_FIFO (*((vu8*)0x40002410)) // RO/WO, TMR1 FIFO register +#define R32_TMR1_DMA_NOW (*((vu32*)0x40002414)) // RW, TMR1 DMA current address +#define R16_TMR1_DMA_NOW (*((vu16*)0x40002414)) // RW, TMR1 DMA current address +#define R32_TMR1_DMA_BEG (*((vu32*)0x40002418)) // RW, TMR1 DMA begin address +#define R16_TMR1_DMA_BEG (*((vu16*)0x40002418)) // RW, TMR1 DMA begin address +#define R32_TMR1_DMA_END (*((vu32*)0x4000241C)) // RW, TMR1 DMA end address +#define R16_TMR1_DMA_END (*((vu16*)0x4000241C)) // RW, TMR1 DMA end address + +/* Timer2 register */ +#define R32_TMR2_CONTROL (*((vu32*)0x40002800)) // RW, TMR2 control +#define R8_TMR2_CTRL_MOD (*((vu8*)0x40002800)) // RW, TMR2 mode control +#define R8_TMR2_CTRL_DMA (*((vu8*)0x40002801)) // RW, TMR2 DMA control +#define R8_TMR2_INTER_EN (*((vu8*)0x40002802)) // RW, TMR2 interrupt enable +#define R32_TMR2_STATUS (*((vu32*)0x40002804)) // RW, TMR2 status +#define R8_TMR2_INT_FLAG (*((vu8*)0x40002806)) // RW1, TMR2 interrupt flag +#define R8_TMR2_FIFO_COUNT (*((vu8*)0x40002807)) // RO, TMR2 FIFO count status +#define R32_TMR2_COUNT (*((vu32*)0x40002808)) // RO, TMR2 current count +#define R16_TMR2_COUNT (*((vu16*)0x40002808)) // RO, TMR2 current count +#define R8_TMR2_COUNT (*((vu8*)0x40002808)) // RO, TMR2 current count +#define R32_TMR2_CNT_END (*((vu32*)0x4000280C)) // RW, TMR2 end count value, only low 26 bit +#define R32_TMR2_FIFO (*((vu32*)0x40002810)) // RO/WO, TMR2 FIFO register, only low 26 bit +#define R16_TMR2_FIFO (*((vu16*)0x40002810)) // RO/WO, TMR2 FIFO register +#define R8_TMR2_FIFO (*((vu8*)0x40002810)) // RO/WO, TMR2 FIFO register +#define R32_TMR2_DMA_NOW (*((vu32*)0x40002814)) // RW, TMR2 DMA current address +#define R16_TMR2_DMA_NOW (*((vu16*)0x40002814)) // RW, TMR2 DMA current address +#define R32_TMR2_DMA_BEG (*((vu32*)0x40002818)) // RW, TMR2 DMA begin address +#define R16_TMR2_DMA_BEG (*((vu16*)0x40002818)) // RW, TMR2 DMA begin address +#define R32_TMR2_DMA_END (*((vu32*)0x4000281C)) // RW, TMR2 DMA end address +#define R16_TMR2_DMA_END (*((vu16*)0x4000281C)) // RW, TMR2 DMA end address + +/* Timer3 register */ +#define R32_TMR3_CONTROL (*((vu32*)0x40002C00)) // RW, TMR3 control +#define R8_TMR3_CTRL_MOD (*((vu8*)0x40002C00)) // RW, TMR3 mode control +#define R8_TMR3_CTRL_DMA (*((vu8*)0x40002C01)) // RW, TMR3 DMA control +#define R8_TMR3_INTER_EN (*((vu8*)0x40002C02)) // RW, TMR3 interrupt enable +#define R32_TMR3_STATUS (*((vu32*)0x40002C04)) // RW, TMR3 status +#define R8_TMR3_INT_FLAG (*((vu8*)0x40002C06)) // RW1, TMR3 interrupt flag +#define R8_TMR3_FIFO_COUNT (*((vu8*)0x40002C07)) // RO, TMR3 FIFO count status +#define R32_TMR3_COUNT (*((vu32*)0x40002C08)) // RO, TMR3 current count +#define R16_TMR3_COUNT (*((vu16*)0x40002C08)) // RO, TMR3 current count +#define R8_TMR3_COUNT (*((vu8*)0x40002C08)) // RO, TMR3 current count +#define R32_TMR3_CNT_END (*((vu32*)0x40002C0C)) // RW, TMR3 end count value, only low 26 bit +#define R32_TMR3_FIFO (*((vu32*)0x40002C10)) // RO/WO, TMR3 FIFO register, only low 26 bit +#define R16_TMR3_FIFO (*((vu16*)0x40002C10)) // RO/WO, TMR3 FIFO register +#define R8_TMR3_FIFO (*((vu8*)0x40002C10)) // RO/WO, TMR3 FIFO register +#define R32_TMR3_DMA_NOW (*((vu32*)0x40002C14)) // RW, TMR3 DMA current address +#define R32_TMR3_DMA_BEG (*((vu32*)0x40002C18)) // RW, TMR3 DMA begin address +#define R32_TMR3_DMA_END (*((vu32*)0x40002C1C)) // RW, TMR3 DMA end address + +/* Timer register address offset and bit define */ +#define BA_TMR0 ((vu8*)0x40002000) // point TMR0 base address +#define BA_TMR1 ((vu8*)0x40002400) // point TMR1 base address +#define BA_TMR2 ((vu8*)0x40002800) // point TMR2 base address +#define BA_TMR3 ((vu8*)0x40002C00) // point TMR3 base address +#endif + +#define TMR_FIFO_SIZE 8 // timer FIFO size (depth) +#define TMR_CTRL_MOD 0 +#define RB_TMR_MODE_IN 0x01 // RW, timer in mode: 0=timer/PWM, 1=capture/count +#define RB_TMR_ALL_CLEAR 0x02 // RW, force clear timer FIFO and count +#define RB_TMR_COUNT_EN 0x04 // RW, timer count enable +#define RB_TMR_OUT_EN 0x08 // RW, timer output enable +#define RB_TMR_OUT_POLAR 0x10 // RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action +#define RB_TMR_CAP_COUNT 0x10 // RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count +#define RB_TMR_PWM_REPEAT 0xC0 // RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 +#define RB_TMR_CAP_EDGE 0xC0 // RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise +#define TMR_CTRL_DMA 1 +#define RB_TMR_DMA_ENABLE 0x01 // RW, timer1/2 DMA enable +#define RB_TMR_DMA_LOOP 0x04 // RW, timer1/2 DMA address loop enable +#define TMR_INTER_EN 2 +#define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer capture count timeout or PWM cycle end +#define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer capture input action or PWM trigger +#define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo <=3) +#define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer1/2 DMA completion +#define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow +#define TMR_INT_FLAG 6 +#define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer capture count timeout or PWM cycle end +#define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer capture input action or PWM trigger +#define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo <=3) +#define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer1/2 DMA completion +#define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow +#define TMR_FIFO_COUNT 7 +#define TMR_COUNT 0x08 +#define TMR_CNT_END 0x0C +#define TMR_FIFO 0x10 +#define TMR_DMA_NOW 0x14 +#define TMR_DMA_BEG 0x18 +#define TMR_DMA_END 0x1C + +/* UART0 register */ +#define R32_UART0_CTRL (*((vu32*)0x40003000)) // RW, UART0 control +#define R8_UART0_MCR (*((vu8*)0x40003000)) // RW, UART0 modem control +#define R8_UART0_IER (*((vu8*)0x40003001)) // RW, UART0 interrupt enable +#define R8_UART0_FCR (*((vu8*)0x40003002)) // RW, UART0 FIFO control +#define R8_UART0_LCR (*((vu8*)0x40003003)) // RW, UART0 line control +#define R32_UART0_STAT (*((vu32*)0x40003004)) // RO, UART0 status +#define R8_UART0_IIR (*((vu8*)0x40003004)) // RO, UART0 interrupt identification +#define R8_UART0_LSR (*((vu8*)0x40003005)) // RO, UART0 line status +#define R8_UART0_MSR (*((vu8*)0x40003006)) // RO, UART0 modem status +#define R32_UART0_FIFO (*((vu32*)0x40003008)) // RW, UART0 data or FIFO port +#define R8_UART0_RBR (*((vu8*)0x40003008)) // RO, UART0 receiver buffer, receiving byte +#define R8_UART0_THR (*((vu8*)0x40003008)) // WO, UART0 transmitter holding, transmittal byte +#define R8_UART0_RFC (*((vu8*)0x4000300A)) // RO, UART0 receiver FIFO count +#define R8_UART0_TFC (*((vu8*)0x4000300B)) // RO, UART0 transmitter FIFO count +#define R32_UART0_SETUP (*((vu32*)0x4000300C)) // RW, UART0 setup +#define R16_UART0_DL (*((vu16*)0x4000300C)) // RW, UART0 divisor latch +#define R8_UART0_DLL (*((vu8*)0x4000300C)) // RW, UART0 divisor latch LSB byte +#define R8_UART0_DLM (*((vu8*)0x4000300D)) // RW, UART0 divisor latch MSB byte +#define R8_UART0_DIV (*((vu8*)0x4000300E)) // RW, UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART0_ADR (*((vu8*)0x4000300F)) // RW, UART0 slave address: 0xFF=disable, other=enable + +/* UART1 register */ +#define R32_UART1_CTRL (*((vu32*)0x40003400)) // RW, UART1 control +#define R8_UART1_MCR (*((vu8*)0x40003400)) // RW, UART1 modem control +#define R8_UART1_IER (*((vu8*)0x40003401)) // RW, UART1 interrupt enable +#define R8_UART1_FCR (*((vu8*)0x40003402)) // RW, UART1 FIFO control +#define R8_UART1_LCR (*((vu8*)0x40003403)) // RW, UART1 line control +#define R32_UART1_STAT (*((vu32*)0x40003404)) // RO, UART1 status +#define R8_UART1_IIR (*((vu8*)0x40003404)) // RO, UART1 interrupt identification +#define R8_UART1_LSR (*((vu8*)0x40003405)) // RO, UART1 line status +#define R32_UART1_FIFO (*((vu32*)0x40003408)) // RW, UART1 data or FIFO port +#define R8_UART1_RBR (*((vu8*)0x40003408)) // RO, UART1 receiver buffer, receiving byte +#define R8_UART1_THR (*((vu8*)0x40003408)) // WO, UART1 transmitter holding, transmittal byte +#define R8_UART1_RFC (*((vu8*)0x4000340A)) // RO, UART1 receiver FIFO count +#define R8_UART1_TFC (*((vu8*)0x4000340B)) // RO, UART1 transmitter FIFO count +#define R32_UART1_SETUP (*((vu32*)0x4000340C)) // RW, UART1 setup +#define R16_UART1_DL (*((vu16*)0x4000340C)) // RW, UART1 divisor latch +#define R8_UART1_DLL (*((vu8*)0x4000340C)) // RW, UART1 divisor latch LSB byte +#define R8_UART1_DLM (*((vu8*)0x4000340D)) // RW, UART1 divisor latch MSB byte +#define R8_UART1_DIV (*((vu8*)0x4000340E)) // RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART2 register */ +#define R32_UART2_CTRL (*((vu32*)0x40003800)) // RW, UART2 control +#define R8_UART2_MCR (*((vu8*)0x40003800)) // RW, UART2 modem control +#define R8_UART2_IER (*((vu8*)0x40003801)) // RW, UART2 interrupt enable +#define R8_UART2_FCR (*((vu8*)0x40003802)) // RW, UART2 FIFO control +#define R8_UART2_LCR (*((vu8*)0x40003803)) // RW, UART2 line control +#define R32_UART2_STAT (*((vu32*)0x40003804)) // RO, UART2 status +#define R8_UART2_IIR (*((vu8*)0x40003804)) // RO, UART2 interrupt identification +#define R8_UART2_LSR (*((vu8*)0x40003805)) // RO, UART2 line status +#define R32_UART2_FIFO (*((vu32*)0x40003808)) // RW, UART2 data or FIFO port +#define R8_UART2_RBR (*((vu8*)0x40003808)) // RO, UART2 receiver buffer, receiving byte +#define R8_UART2_THR (*((vu8*)0x40003808)) // WO, UART2 transmitter holding, transmittal byte +#define R8_UART2_RFC (*((vu8*)0x4000380A)) // RO, UART2 receiver FIFO count +#define R8_UART2_TFC (*((vu8*)0x4000380B)) // RO, UART2 transmitter FIFO count +#define R32_UART2_SETUP (*((vu32*)0x4000380C)) // RW, UART2 setup +#define R16_UART2_DL (*((vu16*)0x4000380C)) // RW, UART2 divisor latch +#define R8_UART2_DLL (*((vu8*)0x4000380C)) // RW, UART2 divisor latch LSB byte +#define R8_UART2_DLM (*((vu8*)0x4000380D)) // RW, UART2 divisor latch MSB byte +#define R8_UART2_DIV (*((vu8*)0x4000380E)) // RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART3 register */ +#define R32_UART3_CTRL (*((vu32*)0x40003C00)) // RW, UART3 control +#define R8_UART3_MCR (*((vu8*)0x40003C00)) // RW, UART3 modem control +#define R8_UART3_IER (*((vu8*)0x40003C01)) // RW, UART3 interrupt enable +#define R8_UART3_FCR (*((vu8*)0x40003C02)) // RW, UART3 FIFO control +#define R8_UART3_LCR (*((vu8*)0x40003C03)) // RW, UART3 line control +#define R32_UART3_STAT (*((vu32*)0x40003C04)) // RO, UART3 status +#define R8_UART3_IIR (*((vu8*)0x40003C04)) // RO, UART3 interrupt identification +#define R8_UART3_LSR (*((vu8*)0x40003C05)) // RO, UART3 line status +#define R32_UART3_FIFO (*((vu32*)0x40003C08)) // RW, UART3 data or FIFO port +#define R8_UART3_RBR (*((vu8*)0x40003C08)) // RO, UART3 receiver buffer, receiving byte +#define R8_UART3_THR (*((vu8*)0x40003C08)) // WO, UART3 transmitter holding, transmittal byte +#define R8_UART3_RFC (*((vu8*)0x40003C0A)) // RO, UART3 receiver FIFO count +#define R8_UART3_TFC (*((vu8*)0x40003C0B)) // RO, UART3 transmitter FIFO count +#define R32_UART3_SETUP (*((vu32*)0x40003C0C)) // RW, UART3 setup +#define R16_UART3_DL (*((vu16*)0x40003C0C)) // RW, UART3 divisor latch +#define R8_UART3_DLL (*((vu8*)0x40003C0C)) // RW, UART3 divisor latch LSB byte +#define R8_UART3_DLM (*((vu8*)0x40003C0D)) // RW, UART3 divisor latch MSB byte +#define R8_UART3_DIV (*((vu8*)0x40003C0E)) // RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART register address offset and bit define */ +#define UART_FIFO_SIZE 8 // UART FIFO size (depth) +#define UART_RECV_RDY_SZ 7 // the max FIFO trigger level for UART receiver data available +#define BA_UART0 ((vu8*)0x40003000) // point UART0 base address +#define BA_UART ((vu8*)0x40003400) // point UART1 base address +#define BA_UART1 ((vu8*)0x40003400) // point UART1 base address +#define BA_UART2 ((vu8*)0x40003800) // point UART2 base address +#define BA_UART3 ((vu8*)0x40003C00) // point UART3 base address +#define UART_MCR 0 +#define RB_MCR_DTR 0x01 // RW, UART0 control DTR +#define RB_MCR_RTS 0x02 // RW, UART0 control RTS +#define RB_MCR_OUT1 0x04 // RW, UART0 control OUT1 +#define RB_MCR_OUT2 0x08 // RW, UART control OUT2 +#define RB_MCR_INT_OE 0x08 // RW, UART interrupt output enable +#define RB_MCR_LOOP 0x10 // RW, UART0 enable local loop back +#define RB_MCR_AU_FLOW_EN 0x20 // RW, UART0 enable autoflow control +#define RB_MCR_TNOW 0x40 // RW, UART0 enable TNOW output on DTR pin +#define RB_MCR_HALF 0x80 // RW, UART0 enable half-duplex +#define UART_IER 1 +#define RB_IER_RECV_RDY 0x01 // RW, UART interrupt enable for receiver data ready +#define RB_IER_THR_EMPTY 0x02 // RW, UART interrupt enable for THR empty +#define RB_IER_LINE_STAT 0x04 // RW, UART interrupt enable for receiver line status +#define RB_IER_MODEM_CHG 0x08 // RW, UART0 interrupt enable for modem status change +#define RB_IER_DTR_EN 0x10 // RW, UART0 DTR/TNOW output pin enable +#define RB_IER_RTS_EN 0x20 // RW, UART0 RTS output pin enable +#define RB_IER_TXD_EN 0x40 // RW, UART TXD pin enable +#define RB_IER_RESET 0x80 // WZ, UART software reset control, high action, auto clear +#define UART_FCR 2 +#define RB_FCR_FIFO_EN 0x01 // RW, UART FIFO enable +#define RB_FCR_RX_FIFO_CLR 0x02 // WZ, clear UART receiver FIFO, high action, auto clear +#define RB_FCR_TX_FIFO_CLR 0x04 // WZ, clear UART transmitter FIFO, high action, auto clear +#define RB_FCR_FIFO_TRIG 0xC0 // RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes +#define UART_LCR 3 +#define RB_LCR_WORD_SZ 0x03 // RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit +#define RB_LCR_STOP_BIT 0x04 // RW, UART stop bit length: 0-1bit, 1-2bit +#define RB_LCR_PAR_EN 0x08 // RW, UART parity enable +#define RB_LCR_PAR_MOD 0x30 // RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space +#define RB_LCR_BREAK_EN 0x40 // RW, UART break control enable +#define RB_LCR_DLAB 0x80 // RW, UART reserved bit +#define RB_LCR_GP_BIT 0x80 // RW, UART general purpose bit +#define UART_IIR 4 +#define RB_IIR_NO_INT 0x01 // RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt +#define RB_IIR_INT_MASK 0x0F // RO, UART interrupt flag bit mask +#define RB_IIR_FIFO_ID 0xC0 // RO, UART FIFO enabled flag +#define UART_LSR 5 +#define RB_LSR_DATA_RDY 0x01 // RO, UART receiver fifo data ready status +#define RB_LSR_OVER_ERR 0x02 // RZ, UART receiver overrun error +#define RB_LSR_PAR_ERR 0x04 // RZ, UART receiver parity error +#define RB_LSR_FRAME_ERR 0x08 // RZ, UART receiver frame error +#define RB_LSR_BREAK_ERR 0x10 // RZ, UART receiver break error +#define RB_LSR_TX_FIFO_EMP 0x20 // RO, UART transmitter fifo empty status +#define RB_LSR_TX_ALL_EMP 0x40 // RO, UART transmitter all empty status +#define RB_LSR_ERR_RX_FIFO 0x80 // RO, indicate error in UART receiver fifo +#define UART_MSR 6 +#define RB_MSR_CTS_CHG 0x01 // RZ, UART0 CTS changed status, high action +#define RB_MSR_DSR_CHG 0x02 // RZ, UART0 DSR changed status, high action +//#define RB_MSR_RI_CHG 0x04 // RZ, UART0 RI changed status, high action +//#define RB_MSR_DCD_CHG 0x08 // RZ, UART0 DCD changed status, high action +#define RB_MSR_CTS 0x10 // RO, UART0 CTS action status +#define RB_MSR_DSR 0x20 // RO, UART0 DSR action status +//#define RB_MSR_RI 0x40 // RO, UART0 RI action status +//#define RB_MSR_DCD 0x80 // RO, UART0 DCD action status +#define UART_RBR 8 +#define UART_THR 8 +#define UART_RFC 0x0A +#define UART_TFC 0x0B +#define UART_DLL 0x0C +#define UART_DLM 0x0D +#define UART_DIV 0x0E +#define UART_ADR 0x0F + +/* UART interrupt identification values for IIR bits 3:0 */ +#define UART_II_SLV_ADDR 0x0E // RO, UART0 slave address match +#define UART_II_LINE_STAT 0x06 // RO, UART interrupt by receiver line status +#define UART_II_RECV_RDY 0x04 // RO, UART interrupt by receiver data available +#define UART_II_RECV_TOUT 0x0C // RO, UART interrupt by receiver fifo timeout +#define UART_II_THR_EMPTY 0x02 // RO, UART interrupt by THR empty +#define UART_II_MODEM_CHG 0x00 // RO, UART0 interrupt by modem status change +#define UART_II_NO_INTER 0x01 // RO, no UART interrupt is pending + +/* SPI0 register */ +#define R32_SPI0_CONTROL (*((vu32*)0x40004000)) // RW, SPI0 control +#define R8_SPI0_CTRL_MOD (*((vu8*)0x40004000)) // RW, SPI0 mode control +#define R8_SPI0_CTRL_CFG (*((vu8*)0x40004001)) // RW, SPI0 configuration control +#define R8_SPI0_INTER_EN (*((vu8*)0x40004002)) // RW, SPI0 interrupt enable +#define R8_SPI0_CLOCK_DIV (*((vu8*)0x40004003)) // RW, SPI0 master clock divisor +#define R8_SPI0_SLAVE_PRE (*((vu8*)0x40004003)) // RW, SPI0 slave preset value +#define R32_SPI0_STATUS (*((vu32*)0x40004004)) // RW, SPI0 status +#define R8_SPI0_BUFFER (*((vu8*)0x40004004)) // RO, SPI0 data buffer +#define R8_SPI0_RUN_FLAG (*((vu8*)0x40004005)) // RO, SPI0 work flag +#define R8_SPI0_INT_FLAG (*((vu8*)0x40004006)) // RW1, SPI0 interrupt flag +#define R8_SPI0_FIFO_COUNT (*((vu8*)0x40004007)) // RO, SPI0 FIFO count status +#define R32_SPI0_TOTAL_CNT (*((vu32*)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit +#define R16_SPI0_TOTAL_CNT (*((vu16*)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit +#define R32_SPI0_FIFO (*((vu32*)0x40004010)) // RW, SPI0 FIFO register +#define R8_SPI0_FIFO (*((vu8*)0x40004010)) // RO/WO, SPI0 FIFO register +#define R8_SPI0_FIFO_COUNT1 (*((vu8*)0x40004013)) // RO, SPI0 FIFO count status +#define R32_SPI0_DMA_NOW (*((vu32*)0x40004014)) // RW, SPI0 DMA current address +#define R16_SPI0_DMA_NOW (*((vu16*)0x40004014)) // RW, SPI0 DMA current address +#define R32_SPI0_DMA_BEG (*((vu32*)0x40004018)) // RW, SPI0 DMA begin address +#define R16_SPI0_DMA_BEG (*((vu16*)0x40004018)) // RW, SPI0 DMA begin address +#define R32_SPI0_DMA_END (*((vu32*)0x4000401C)) // RW, SPI0 DMA end address +#define R16_SPI0_DMA_END (*((vu16*)0x4000401C)) // RW, SPI0 DMA end address + +/* SPI1 register */ +#define R32_SPI1_CONTROL (*((vu32*)0x40004400)) // RW, SPI1 control +#define R8_SPI1_CTRL_MOD (*((vu8*)0x40004400)) // RW, SPI1 mode control +#define R8_SPI1_CTRL_CFG (*((vu8*)0x40004401)) // RW, SPI1 configuration control +#define R8_SPI1_INTER_EN (*((vu8*)0x40004402)) // RW, SPI1 interrupt enable +#define R8_SPI1_CLOCK_DIV (*((vu8*)0x40004403)) // RW, SPI1 master clock divisor +#define R32_SPI1_STATUS (*((vu32*)0x40004404)) // RW, SPI1 status +#define R8_SPI1_BUFFER (*((vu8*)0x40004404)) // RO, SPI1 data buffer +#define R8_SPI1_RUN_FLAG (*((vu8*)0x40004405)) // RO, SPI1 work flag +#define R8_SPI1_INT_FLAG (*((vu8*)0x40004406)) // RW1, SPI1 interrupt flag +#define R8_SPI1_FIFO_COUNT (*((vu8*)0x40004407)) // RO, SPI1 FIFO count status +#define R32_SPI1_TOTAL_CNT (*((vu32*)0x4000440C)) // RW, SPI1 total byte count, only low 12 bit +#define R16_SPI1_TOTAL_CNT (*((vu16*)0x4000440C)) // RW, SPI1 total byte count, only low 12 bit +#define R32_SPI1_FIFO (*((vu32*)0x40004410)) // RW, SPI1 FIFO register +#define R8_SPI1_FIFO (*((vu8*)0x40004410)) // RO/WO, SPI1 FIFO register +#define R8_SPI1_FIFO_COUNT1 (*((vu8*)0x40004413)) // RO, SPI1 FIFO count status + +/* SPI register address offset and bit define */ +#define SPI_FIFO_SIZE 8 // SPI FIFO size (depth) +#define BA_SPI0 ((vu8*)0x40004000) // point SPI0 base address +#define BA_SPI1 ((vu8*)0x40004400) // point SPI1 base address +#define SPI_CTRL_MOD 0 +#define RB_SPI_MODE_SLAVE 0x01 // RW, SPI0 slave mode: 0=master/host, 1=slave/device +#define RB_SPI_ALL_CLEAR 0x02 // RW, force clear SPI FIFO and count +#define RB_SPI_2WIRE_MOD 0x04 // RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX) +#define RB_SPI_MST_SCK_MOD 0x08 // RW, SPI master clock mode: 0=mode 0, 1=mode 3 +#define RB_SPI_SLV_CMD_MOD 0x08 // RW, SPI0 slave command mode: 0=byte stream, 1=first byte command +#define RB_SPI_FIFO_DIR 0x10 // RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode) +#define RB_SPI_SCK_OE 0x20 // RW, SPI SCK output enable +#define RB_SPI_MOSI_OE 0x40 // RW, SPI MOSI output enable +#define RB_SPI1_SDO_OE 0x40 // RW, SPI1 SDO output enable +#define RB_SPI_MISO_OE 0x80 // RW, SPI MISO output enable +#define RB_SPI1_SDI_OE 0x80 // RW, SPI1 SDI output enable, SPI1 enable 2 wire mode: 0=3wire(SCK1,SDO,SDI), 1=2wire(SCK1,SDI=SDX) +#define SPI_CTRL_CFG 1 +#define RB_SPI_DMA_ENABLE 0x01 // RW, SPI DMA enable +#define RB_MST_CLK_SEL 0x02 // RW, hclk polarity reversal,1= polarity reversal,0=IDLE +#define RB_SPI_DMA_LOOP 0x04 // RW, SPI DMA address loop enable +#define RB_SPI_AUTO_IF 0x10 // RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag +#define RB_SPI_BIT_ORDER 0x20 // RW, SPI bit data order: 0=MSB first, 1=LSB first +#define RB_SPI_MST_DLY_EN 0x40 // RW, SPI master input delay enable +#define SPI_INTER_EN 2 +#define RB_SPI_IE_CNT_END 0x01 // RW, enable interrupt for SPI total byte count end +#define RB_SPI_IE_BYTE_END 0x02 // RW, enable interrupt for SPI byte exchanged +#define RB_SPI_IE_FIFO_HF 0x04 // RW, enable interrupt for SPI FIFO half +#define RB_SPI_IE_DMA_END 0x08 // RW, enable interrupt for SPI DMA completion +#define RB_SPI_IE_FIFO_OV 0x10 // RW, enable interrupt for SPI FIFO overflow +#define RB_SPI_IE_FST_BYTE 0x80 // RW, enable interrupt for SPI slave mode first byte received +#define SPI_CLOCK_DIV 3 +#define SPI_SLAVE_PRESET 3 +#define SPI_BUFFER 4 +#define SPI_RUN_FLAG 5 +#define RB_SPI_SLV_CMD_ACT 0x10 // RO, SPI slave first byte / command flag +#define RB_SPI_FIFO_READY 0x20 // RO, SPI FIFO ready status +#define RB_SPI_SLV_CS_LOAD 0x40 // RO, SPI slave chip-select loading status +#define RB_SPI_SLV_SELECT 0x80 // RO, SPI slave selection status +#define SPI_INT_FLAG 6 +#define RB_SPI_IF_CNT_END 0x01 // RW1, interrupt flag for SPI total byte count end +#define RB_SPI_IF_BYTE_END 0x02 // RW1, interrupt flag for SPI byte exchanged +#define RB_SPI_IF_FIFO_HF 0x04 // RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : <4bytes) +#define RB_SPI_IF_DMA_END 0x08 // RW1, interrupt flag for SPI DMA completion +#define RB_SPI_IF_FIFO_OV 0x10 // RW1, interrupt flag for SPI FIFO overflow +#define RB_SPI_FREE 0x40 // RO, current SPI free status +#define RB_SPI_IF_FST_BYTE 0x80 // RW1, interrupt flag for SPI slave mode first byte received +#define SPI_FIFO_COUNT 7 +#define SPI_INTER_CFG1 8 +#define RB_SPI_INT_TYPE 0x001F // RW, interupt trig mode select,1=edge,0=level +#define RB_SPI_IE_FIFO_EMPTY 0x0100 // RW, fifo empty interupt enable +#define RB_SPI_IE_FIFO_FULL 0x0200 // RW, fifo full interupt enable +#define RB_SPI_IF_FIFO_EMPTY 0x010000 // RW, fifo empty interupt flag +#define RB_SPI_IF_FIFO_FULL 0x020000 // RW, fifo full interupt flag +#define SPI_TOTAL_CNT 0x0C +#define SPI_FIFO 0x10 +#define SPI_DMA_NOW 0x14 +#define SPI_DMA_BEG 0x18 +#define SPI_DMA_END 0x1C + +/* I2C register */ +#define R16_I2C_CTRL1 (*((vu16*)0x40004800)) // RW, I2C control 1 +#define R16_I2C_CTRL2 (*((vu16*)0x40004804)) // RW, I2C control 2 +#define R16_I2C_OADDR1 (*((vu16*)0x40004808)) // RW, I2C own address register 1 +#define R16_I2C_OADDR2 (*((vu16*)0x4000480C)) // RW, I2C own address register 2 +#define R16_I2C_DATAR (*((vu16*)0x40004810)) // RW, I2C data register +#define R16_I2C_STAR1 (*((vu16*)0x40004814)) // R0, I2C stauts register 1 +#define R16_I2C_STAR2 (*((vu16*)0x40004818)) // R0, I2C status register 2 +// #define R8_I2C_PEC (*((vu8*) 0x40004819)) // R0, I2C Packet error checking register +#define R16_I2C_CKCFGR (*((vu16*)0x4000481C)) // RW, I2C clock control register +#define R16_I2C_RTR (*((vu16*)0x40004820)) // RW, I2C trise register + +/* I2C register address offset and bit define */ +#define BA_I2C ((vu8*)0x40004800) // point I2C base address +#define I2C_CTRL1 0 +#define RB_I2C_PE 0x0001 // RW, Peripheral enable +#define RB_I2C_SMBUS 0x0002 // RW, SMBUS mode: 0=I2C mode, 1=SMBUS mode +#define RB_I2C_SMBTYPE 0x0008 // RW, SMBus type: 0=Device, 1=Host +#define RB_I2C_EBARP 0x0010 // RW, ARP enable +#define RB_I2C_ENPEC 0x0020 // RW, PEC ebable +#define RB_I2C_ENGC 0x0040 // RW, General call enable +#define RB_I2C_NOSTRETCH 0x0080 // RW, Clock stretching disable (Slave mode) +#define RB_I2C_START 0x0100 // RW, Start generation: master mode: 0=no start, 1=repeated start; slave mode: 0=no start, 1=start at bus free +#define RB_I2C_STOP 0x0200 // RW, Stop generation: master mode: 0=no stop, 1=stop after the current byte transfer or after the current Start condition is sent; slave mode: 0=no stop, 1=Release the SCL and SDA lines after the current byte transfer +#define RB_I2C_ACK 0x0400 // RW, Acknowledge enable +#define RB_I2C_POS 0x0800 // RW, Acknowledge/PEC Position (for data reception) +#define RB_I2C_PEC 0x1000 // RW, Packet error checking: 0=No PEC transfer, 1=PEC transfer (in Tx or Rx mode) +#define RB_I2C_ALERT 0x2000 // RW, SMBus alert: 0=Releases SMBA pin high, 1=Drives SMBA pin low. +#define RB_I2C_SWRST 0x8000 // RW, Software reset +#define I2C_CTRL2 4 +#define RB_I2C_FREQ 0x003F // RW, Peripheral clock frequency, The minimum allowed frequency is 2 MHz,the maximum frequency is 36 MHz +#define RB_I2C_ITERREN 0x0100 // RW, Error interrupt enable +#define RB_I2C_ITEVTEN 0x0200 // RW, Event interrupt enable +#define RB_I2C_ITBUFEN 0x0400 // RW, Buffer interrupt enable +#define I2C_OADDR1 8 +#define RB_I2C_ADD0 0x0001 // RW, bit0 of address in 10-bit addressing mode +#define RB_I2C_ADD7_1 0x00FE // RW, bit[7:1] of address +#define RB_I2C_ADD9_8 0x0300 // RW, bit[9:8] of address in 10-bit addressing mode +#define RB_I2C_MUST1 0x4000 // RW, Should always be kept at 1 +#define RB_I2C_ADDMODE 0x8000 // RW, Addressing mode (slave mode): 0=7-bit slave address, 1=10-bit slave address +#define I2C_OADDR2 12 +#define RB_I2C_ENDUAL 0x0001 // RW, Dual addressing mode enable +#define RB_I2C_ADD2 0x00FE // RW, bit[7:1] of address2 +#define I2C_DATAR 16 +#define I2C_STAR1 20 +#define RB_I2C_SB 0x0001 // RW0, Start bit flag (Master mode) +#define RB_I2C_ADDR 0x0002 // RW0, Address sent (master mode)/matched (slave mode) flag +#define RB_I2C_BTF 0x0004 // RO, Byte transfer finished flag +#define RB_I2C_ADD10 0x0008 // RO, 10-bit header sent flag (Master mode) +#define RB_I2C_STOPF 0x0010 // RO, Stop detection flag (slave mode) +#define RB_I2C_RxNE 0x0040 // RO, Data register not empty flag (receivers) +#define RB_I2C_TxE 0x0080 // RO, Data register empty flag (transmitters) +#define RB_I2C_BERR 0x0100 // RW0, Bus error flag +#define RB_I2C_ARLO 0x0200 // RW0, Arbitration lost flag (master mode) +#define RB_I2C_AF 0x0400 // RW0, Acknowledge failure flag +#define RB_I2C_OVR 0x0800 // RW0, Overrun/Underrun flag +#define RB_I2C_PECERR 0x1000 // RW0, PEC Error flag in reception +#define RB_I2C_TIMEOUT 0x4000 // RW0, Timeout or Tlow error flag +#define RB_I2C_SMBALERT 0x8000 // RW0, SMBus alert flag +#define I2C_STAR2 24 +#define RB_I2C_MSL 0x0001 // RO, Mode statu: 0=Slave mode, 1=Master mode +#define RB_I2C_BUSY 0x0002 // RO, Bus busy flag +#define RB_I2C_TRA 0x0004 // RO, Trans flag: 0=data bytes received, 1=data bytes transmitted +#define RB_I2C_GENCALL 0x0010 // RO, General call address (Slave mode) received flag +#define RB_I2C_SMBDEFAULT 0x0020 // RO, SMBus device default address (Slave mode) received flag +#define RB_I2C_SMBHOST 0x0040 // RO, SMBus host header (Slave mode) received flag +#define RB_I2C_DUALF 0x0080 // RO, Dual flag (Slave mode): 0=Received address matched with OAR1, 1=Received address matched with OAR2 +#define RB_I2C_PECX 0xFF00 // RO, Packet error checking register +#define I2C_CKCFGR 28 +#define RB_I2C_CCR 0x0FFF // RW, Controls the SCL clock in Fm/Sm mode (Master mode) +#define RB_I2C_DUTY 0x4000 // RW, Fm mode duty cycle: 0=L/H=2, 1=L/H=16/9 +#define RB_I2C_F_S 0x8000 // RW, I2C master mode selection: 0=standard mode, 1=fast mode +#define I2C_RTR 32 +#define RB_I2C_TRISE 0x003F // RW, Maximum rise time in Fm/Sm mode (Master mode) + +#ifdef CH57x +/* PWM1/2/3/4/5/register */ +#define R32_PWM_CONTROL (*((vu32*)0x40005000)) // RW, PWM control +#define R8_PWM_OUT_EN (*((vu8*)0x40005000)) // RW, PWM output enable control +#define R8_PWM_POLAR (*((vu8*)0x40005001)) // RW, PWM output polarity control +#define R8_PWM_CONFIG (*((vu8*)0x40005002)) // RW, PWM configuration +#define R8_PWM_DMA_CTRL (*((vu8*)0x40005003)) // RW, PWM DMA control +#define R32_PWM1_3_DATA (*((vu32*)0x40005004)) // RW, PWM1-3 data holding +#define R16_PWM1_DATA (*((vu16*)0x40005004)) // RW, PWM1 data (16 bit) holding +#define R16_PWM2_DATA (*((vu16*)0x40005006)) // RW, PWM2 data (16 bit) holding +#define R8_PWM1_DATA (*((vu8*)0x40005004)) // RW, PWM1 data (8 bit) holding +#define R8_PWM2_DATA (*((vu8*)0x40005005)) // RW, PWM2 data (8 bit) holding +#define R8_PWM3_DATA (*((vu8*)0x40005006)) // RW, PWM3 data (8 bit) holding +#define R16_PWM3_DATA (*((vu16*)0x40005008)) // RW, PWM3 data (16 bit) holding +#define R32_PWM4_5_DATA (*((vu32*)0x40005010)) // RW, PWM4-5 data register +#define R16_PWM4_DATA (*((vu16*)0x40005010)) // RW, PWM4 data (16 bit) holding +#define R16_PWM5_DATA (*((vu16*)0x40005012)) // RW, PWM5 data (16 bit) holding +#define R8_PWM4_DATA (*((vu8*)0x40005010)) // RW, PWM4 data (8 bit) holding +#define R8_PWM5_DATA (*((vu8*)0x40005011)) // RW, PWM5 data (8 bit) holding +#define R8_PWM_INT_EN (*((vu8*)0x4000500C)) // RW, PWM interrupt enable +#define RB_PWM_IE_CYC 0x01 // RW, enable interrupt for PWM1\2\3 cycle end +#define RB_PWM_CYC_PRE 0x02 // RW, select PWM cycle interrupt point: 0=after count 0xFE (0x7E for 7 bits mode...), 1=after count 0xF0 (0x70 for 7 bits mode...) +#define RB_PWM1_IE_CYC 0x04 // RW, enable interrupt for PWM4\5 cycle end +#define RB_PWM_IE_FIFO 0x10 // RW, enable interrupt for fifo count < 4 +#define RB_PWM_IE_DMA 0x20 // RW, enable interrupt for DMA transmision end +#define RB_PWM_IE_OVER 0x40 // RW, enable interrupt for fifo overflow +#define R8_PWM_INT_FLAG (*((vu8*)0x4000500D)) // RW1, PWM interrupt flag +#ifdef CH571_CH573 +#define RB_PWM_IF_CYC 0x80 // RW1, interrupt flag for PWM1\2\3 cycle end +#else +#define RB_PWM_IF_CYC 0x01 // RW1, interrupt flag for PWM1\2\3 cycle end +#endif +#define RB_PWM1_IF_CYC 0x02 // RW1, interrupt flag for PWM4\5 cycle end +#define RB_PWM_IF_FIFO 0x04 // RW1, interrupt flag for fifo count < 4 +#define RB_PWM_IF_DMA 0x08 // RW1, interrupt flag for DMA transmision end +#define RB_PWM_IF_OVER 0x10 // RW1, interrupt flag for fifo overflow +#define R16_PWM_CYC_VALUE (*((vu16*)0x40005014)) // RW, PWM1\2\3 cycle value for 16bit +#define R16_PWM_CYC1_VALUE (*((vu16*)0x40005016)) // RW, PWM4\5 cycle value for 16bit +#define R16_PWM_CLOCK_DIV (*((vu16*)0x40005018)) // RW, PWM clock division +#define R32_PWM_DMA_NOW (*((vu32*)0x4000501C)) // RW, PWM DMA addr for now +#define R32_PWM_DMA_BEG (*((vu32*)0x40005020)) // RW, PWM DMA addr of begining +#define R32_PWM_DMA_END (*((vu32*)0x40005024)) // RW, PWM DMA addr of end + +/* PWM1/2/3/4/5 register address offset and bit define */ +#define BA_PWMX ((vu8*)0x40005000) // point PWM1/2/3/4/5 base address +#define PWM_OUT_EN 0 +#define RB_PWM5_OUT_EN 0x10 // RW, PWM5 output enable +#define RB_PWM4_OUT_EN 0x08 // RW, PWM4 output enable +#define RB_PWM3_OUT_EN 0x04 // RW, PWM3 output enable +#define RB_PWM2_OUT_EN 0x02 // RW, PWM2 output enable +#define RB_PWM1_OUT_EN 0x01 // RW, PWM1 output enable +#define PWM_POLAR 1 +#define RB_PWM5_POLAR 0x10 // RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM4_POLAR 0x08 // RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM3_POLAR 0x04 // RW, PWM3 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM2_POLAR 0x02 // RW, PWM2 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM1_POLAR 0x01 // RW, PWM1 output polarity: 0=default low and high action, 1=default high and low action +#define PWM_CONFIG 2 +#define RB_PWM_SYNC_EN 0x80 // RW, enable sync +#define RB_PWM_SYNC_START 0x40 // RW, enable sync start when RB_PWM_SYN_EN=1 +#define RB_PWM4_5_CH 0x10 // RO, 1=PWM4 channel output 0=PWM5 channel output +#define RB_PWM4_5_STAG_EN 0x08 // RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output +#ifdef CH571_CH573 +#define RB_PWM_CYC_MOD 0x0C // RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=16 bits data +#else +#define RB_PWM_CYC_MOD 0x06 // RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=16 bits data +#endif +#define RB_PWM_CYCLE_SEL 0x01 // RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks +#define PWM_DMA_CTRL 3 +#define RB_DMA_SEL 0x04 // RW, RB_PWM_SYN_EN=0: 1=DMA choose 1/2/3 channel output , 0=DMA choose 4/5 channel output ,RB_PWM_SYN_EN=1: 1=DMA choose 1/2/3/4/5 channel output +#define RB_DMA_ADDR_LOOP 0x02 // RW, DMA mode:1=DMA loop,0=DMA no loop +#define RB_DMA_ENABLE 0x01 // RW, DMA enable(only 16bit data) + +#define PWM1_DATA_HOLD 4 +#define PWM2_DATA_HOLD 5 +#define PWM3_DATA_HOLD 6 +#define PWM4_DATA_HOLD 7 +#define PWM5_DATA_HOLD 8 +#else // PWM for CH58x and ch59x +/* PWM4/5/6/7/8/9/10/11 register */ +#define R32_PWM_CONTROL (*((vu32*)0x40005000)) // RW, PWM control +#define R8_PWM_OUT_EN (*((vu8*)0x40005000)) // RW, PWM output enable control +#define R8_PWM_POLAR (*((vu8*)0x40005001)) // RW, PWM output polarity control +#define R8_PWM_CONFIG (*((vu8*)0x40005002)) // RW, PWM configuration +#define R8_PWM_CLOCK_DIV (*((vu8*)0x40005003)) // RW, PWM clock divisor +#define R32_PWM4_7_DATA (*((vu32*)0x40005004)) // RW, PWM4-7 data holding +#define R8_PWM4_DATA (*((vu8*)0x40005004)) // RW, PWM4 data holding +#define R16_PWM4_DATA (*((vu16*)0x40005004)) // RW, PWM4 16bit data holding +#define R8_PWM5_DATA (*((vu8*)0x40005005)) // RW, PWM5 data holding +#define R16_PWM5_DATA (*((vu16*)0x40005006)) // RW, PWM5 16bit data holding +#define R8_PWM6_DATA (*((vu8*)0x40005006)) // RW, PWM6 data holding +#define R8_PWM7_DATA (*((vu8*)0x40005007)) // RW, PWM7 data holding +#define R32_PWM8_11_DATA (*((vu32*)0x40005008)) // RW, PWM8-11 data holding +#define R8_PWM8_DATA (*((vu8*)0x40005008)) // RW, PWM8 data holding +#define R8_PWM9_DATA (*((vu8*)0x40005009)) // RW, PWM9 data holding +#define R8_PWM10_DATA (*((vu8*)0x4000500A)) // RW, PWM10 data holding +#define R8_PWM11_DATA (*((vu8*)0x4000500B)) // RW, PWM11 data holding +#define R8_PWM_INT_CTRL (*((vu8*)0x4000500C)) // RW, PWM interrupt control +#define RB_PWM_IE_CYC 0x01 // RW, enable interrupt for PWM cycle end +#define RB_PWM_CYC_PRE 0x02 // RW, select PWM cycle interrupt point: 0=after count 0xFE (0x7E for 7 bits mode...), 1=after count 0xF0 (0x70 for 7 bits mode...) +#define RB_PWM_IF_CYC 0x80 // RW1, interrupt flag for PWM cycle end +#define R32_PWM_REG_DATA8 (*((vu32*)0x40005010)) // RW, PWM8-9 data register +#define R16_PWM8_DATA (*((vu16*)0x40005010)) // RW, PWM8 16bit data holding +#define R16_PWM8_REG_DATA (*((vu16*)0x40005010)) // RW, PWM8 16bit data holding +#define R16_PWM9_DATA (*((vu16*)0x40005012)) // RW, PWM9 16bit data holding +#define R16_PWM9_REG_DATA (*((vu16*)0x40005012)) // RW, PWM9 16bit data holding +#define R32_PWM_REG_CYCLE (*((vu32*)0x40005014)) // RW, PWM cycle value + +/* PWM4/5/6/7/8/9/10/11 register address offset and bit define */ +#define BA_PWMX ((vu8*)0x40005000) // point PWM4/5/6/7/8/9/10/11 base address +#define PWM_OUT_EN 0 +#define RB_PWM4_OUT_EN 0x01 // RW, PWM4 output enable +#define RB_PWM5_OUT_EN 0x02 // RW, PWM5 output enable +#define RB_PWM6_OUT_EN 0x04 // RW, PWM6 output enable +#define RB_PWM7_OUT_EN 0x08 // RW, PWM7 output enable +#define RB_PWM8_OUT_EN 0x10 // RW, PWM8 output enable +#define RB_PWM9_OUT_EN 0x20 // RW, PWM9 output enable +#define RB_PWM10_OUT_EN 0x40 // RW, PWM10 output enable +#define RB_PWM11_OUT_EN 0x80 // RW, PWM11 output enable +#define PWM_POLAR 1 +#define RB_PWM4_POLAR 0x01 // RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM5_POLAR 0x02 // RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM6_POLAR 0x04 // RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM7_POLAR 0x08 // RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM8_POLAR 0x10 // RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM9_POLAR 0x20 // RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM10_POLAR 0x40 // RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM11_POLAR 0x80 // RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action +#define PWM_CONFIG 2 +#define RB_PWM_CYCLE_SEL 0x01 // RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks +#define RB_PWM_STAG_ST 0x02 // RO, PWM stagger cycle status +#define RB_PWM_CYC_MOD 0x0C // RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=16 bits data +#define RB_PWM4_5_STAG_EN 0x10 // RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output +#define RB_PWM6_7_STAG_EN 0x20 // RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output +#define RB_PWM8_9_STAG_EN 0x40 // RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output +#define RB_PWM10_11_STAG_EN 0x80 // RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output +#define PWM_CLOCK_DIV 3 +#define PWM4_DATA_HOLD 4 +#define PWM5_DATA_HOLD 5 +#define PWM6_DATA_HOLD 6 +#define PWM7_DATA_HOLD 7 +#define PWM8_DATA_HOLD 8 +#define PWM9_DATA_HOLD 9 +#define PWM10_DATA_HOLD 10 +#define PWM11_DATA_HOLD 11 +#endif + +#ifdef CH584_CH585 +/* LCD register */ +#define R8_LCD_CMD (*((vu8*)(0x40006000))) +#define RB_LCD_SYS_EN 0x01 // RW, LCD digital system enable +#define RB_LCD_ON 0x02 // RW, LCD analog system enable +#define RB_LCD_BIAS 0x04 // RW, LCD bias select: 0=1/2 bias, 1=1/3 bias +#define RB_LCD_DUTY 0x18 // RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty +#define RB_LCD_SCAN_CLK 0x60 // RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz +#define RB_LCD_VLCD_SEL 0x80 // RW, LCD drive voltage select 0=VIO33*100%(3.3V),1=VIO33*76%(2.5V) + +#define R32_LCD_RAM0 (*((vu32*)(0x40006004))) // RW, LCD driver data0, address 0-3 +#define R32_LCD_RAM1 (*((vu32*)(0x40006008))) // RW, LCD driver data1, address 4-7 +#define R32_LCD_RAM2 (*((vu32*)(0x4000600C))) // RW, LCD driver data2, address 8-11 +#define R32_LCD_RAM3 (*((vu32*)(0x40006010))) // RW, LCD driver data3, address 12-15 +#define R32_LCD_SEG_EN (*((vu32*)(0x40006014))) // RW, LCD SEG27~SEG0 enable +#define RB_LCD_SEG0_7_EN 0x000000FF // RW, SEG0-SEG7 enable +#define RB_LCD_SEG8_15_EN 0x0000FF00 // RW, SEG8-SEG15 enable +#define RB_LCD_SEG16_23_EN 0x00FF0000 // RW, SEG16-SEG23 enable +#define RB_LCD_SEG24_27_EN 0x0F000000 // RW, SEG24-SEG27 enable +#elif defined(CH591_CH592) +/* LCD register */ +#define R32_LCD_CMD (*((vu32*)(0x40006000))) +#define RB_LCD_SYS_EN 0x01 // RW, LCD digital system enable +#define RB_LCD_ON 0x02 // RW, LCD analog system enable +#define RB_LCD_BIAS 0x04 // RW, LCD bias select: 0=1/2 bias, 1=1/3 bias +#define RB_LCD_DUTY 0x18 // RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty +#define RB_LCD_SCAN_CLK 0x60 // RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz +#define RB_LCD_VLCD_SEL 0x80 // RW, LCD drive voltage：0=VIO33*100%(3.3V),1=VIO33*76%(2.5V) +#define RB_LCD_SEG0_7_EN 0xFF00 // RW, SEG0-SEG7 enable +#define RB_LCD_SEG8_15_EN 0xFF0000 // RW, SEG8-SEG15 enable +#define RB_LCD_SEG16_19_EN 0xF000000 // RW, SEG16-SEG19 enable + +#define R32_LCD_RAM0 (*((vu32*)(0x40006004))) // RW, LCD driver data0, address 0-3 +#define R32_LCD_RAM1 (*((vu32*)(0x40006008))) // RW, LCD driver data1, address 4-7 +#define R32_LCD_RAM2 (*((vu32*)(0x4000600C))) // RW, LCD driver data2, address 8-12 +#endif + +#ifdef CH584_CH585 +/* LED register */ +#define R8_LED_CTRL_MOD (*((vu8*)0x4000F000)) // RW, LED mode config register +#define RB_LED_BIT_ORDER 0x01 // RW, LED serial bit director select 0=hign first, 1=low first +#define RB_LED_ALL_CLEAR 0x02 // RW, force LED FIFO/count/interupt flag clear +#define RB_LED_OUT_POLAR 0x04 // RW, LED data output inverted +#define RB_LED_OUT_EN 0x08 // RW, enable LED output +#define RB_LED_DMA_EN 0x10 // RW, enable LED DMA and DMA interupt +#define RB_LED_IE_FIFO 0x20 // RW, enable LED fifo count <=2 interupt +#define RB_LED_CHAN_MOD 0xC0 // RW, LED channel mode select, 00=LED0, 01=LED0/1, 10=LED0~3, 11=LED0~7 +#define R8_LED_CLOCK_DIV (*((vu8*)0x4000F001)) // RW, LED serial clk div register +#define RB_LED_CLOCK_DIV 0xFF // RW, paramater of LED output clk divider +#define R8_LED_CTRL_MOD1 (*((vu8*)0x4000F002)) // RW, LED mode config1 register +#define RB_LED_DMA_LOOP 0x01 // RW, enable LED DMA data loop +#define RB_IE_SEND_END 0x02 // RW, enable DMA data transfer interupt +#define R16_LED_STATUS (*((vu16*)0x4000F004)) // RW, LED status register +#define RB_LED_FIFO_COUNT 0x0F // RO, LED fifo current count +#define RB_LED_CLOCK 0x20 // RO, LED clock current status +#define RB_LED_IF_FIFO 0x40 // RW1, FIFO count <=2 flag, clear RB_LED_IF_FIFO +#define RB_LED_LOAD_FAIL 0x80 // R0, result of LED data loading +#define RB_LED_IF_DMA_END 0x0100 // RW1, LED DMA complete flag, clear RB_LED_IF_DMA_END +#define RB_LED_IF_DMA_INT 0x0200 // RW1, LED DMA transfer complete flag, clear RB_LED_IF_DMA_INT +#define R32_LED_FIFO (*((vu32*)0x4000F008)) // RW, LED data fifo register +#define RB_LED_FIFO 0xFFFFFFFF // WO, LED fifo data input +#define R16_LED_DMA_LEN (*((vu16*)0x4000F010)) // RW, LED DMA send length +#define RB_LED_DMA_LEN 0x0FFF // WO, LED DMA send length +#define R16_LED_DMA_CNT (*((vu16*)0x4000F014)) // RW, LED DMA remain count +#define RB_LED_DMA_CNT 0x0FFF // RO, LED DMA main buffer remain data cnt +#define R32_LED_DMA_BEG (*((vu32*)0x4000F018)) // RW, LED DMA begin address +#define RB_LED_DMA_BEG 0x01FFFC // RW, LED DMA start adress +#define R32_LED_DMA_CUR (*((vu32*)0x4000F01C)) // RW, LED DMA current address +#define RB_LED_DMA_CUR 0x01FFFC // RW, LED DMA now address +#endif + +// USB: +8000H - 83FFH */ +#define USB_BASE_ADDR (0x40008000) +#define BA_USB ((vu8*)0x40008000) // point USB base address + +/* USB */ +#define R32_USB_CONTROL (*((vu32*)0x40008000)) // USB control & interrupt enable & device address +#define R8_USB_CTRL (*((vu8*)0x40008000)) // USB base control +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need RB_PIN_USB_DP_PU=1 or need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define R8_UDEV_CTRL (*((vu8*)0x40008001)) // USB device physical prot control +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define R8_USB_INT_EN (*((vu8*)0x40008002)) // USB interrupt enable +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_MOD_1_WIRE 0x20 // enable single wire mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define R8_USB_DEV_AD (*((vu8*)0x40008003)) // USB device address +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define R32_USB_STATUS (*((vu32*)0x40008004)) // USB miscellaneous status & interrupt flag & interrupt status +#define R8_USB_MIS_ST (*((vu8*)0x40008005)) // USB miscellaneous status +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define R8_USB_INT_FG (*((vu8*)0x40008006)) // USB interrupt flag +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define R8_USB_INT_ST (*((vu8*)0x40008007)) // USB interrupt status +#define RB_UIS_SETUP_ACT 0x80 // RO, indicate SETUP token & 8 bytes setup request received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode, keep last status during SETUP token, clear RB_UIF_TRANSFER ( RB_UIF_TRANSFER from 1 to 0 ) to set free +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: free +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R8_USB_RX_LEN (*((vu8*)0x40008008)) // USB receiving length +#define R32_USB_BUF_MODE (*((vu32*)0x4000800C)) // USB endpoint buffer mode +#define R8_UEP4_1_MOD (*((vu8*)0x4000800C)) // endpoint 4/1 mode +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +#define R8_UEP2_3_MOD (*((vu8*)0x4000800D)) // endpoint 2/3 mode +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define R8_UEP567_MOD (*((vu8*)0x4000800E)) // endpoint 5/6/7 mode +#define RB_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) +// bUEPn_RX_EN & bUEPn_TX_EN: USB endpoint 5/6/7 buffer mode, buffer start address is UEPn_DMA +// 0 0: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (OUT endpoint) +// 0 1: 64 bytes buffer for transmittal (IN endpoint) +// 1 1: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes + +#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#ifdef CH584_CH585 +#define R32_UEP0_DMA (*((vu32*)0x40008010)) // endpoint 0 DMA buffer address +#define R32_UEP1_DMA (*((vu32*)0x40008014)) // endpoint 1 DMA buffer address +#define R32_UEP2_DMA (*((vu32*)0x40008018)) // endpoint 2 DMA buffer address +#define R32_UH_RX_DMA R32_UEP2_DMA // host rx endpoint buffer address +#define R32_UEP3_DMA (*((vu32*)0x4000801C)) // endpoint 3 DMA buffer address +#define R32_UH_TX_DMA R32_UEP3_DMA // host tx endpoint buffer address +#define R32_UEP5_DMA (*((vu32*)0x40008054)) // endpoint 5 DMA buffer address +#define R32_UEP6_DMA (*((vu32*)0x40008058)) // endpoint 6 DMA buffer address +#define R32_UEP7_DMA (*((vu32*)0x4000805C)) // endpoint 7 DMA buffer address +#else +#define R16_UEP0_DMA (*((vu16*)0x40008010)) // endpoint 0 DMA buffer address +#define R16_UEP1_DMA (*((vu16*)0x40008014)) // endpoint 1 DMA buffer address +#define R16_UEP2_DMA (*((vu16*)0x40008018)) // endpoint 2 DMA buffer address +#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer address +#define R16_UEP3_DMA (*((vu16*)0x4000801C)) // endpoint 3 DMA buffer address +#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer address +#define R16_UEP5_DMA (*((vu16*)0x40008054)) // endpoint 5 DMA buffer address +#define R16_UEP6_DMA (*((vu16*)0x40008058)) // endpoint 6 DMA buffer address +#define R16_UEP7_DMA (*((vu16*)0x4000805C)) // endpoint 7 DMA buffer address +#endif +#define R32_USB_EP0_CTRL (*((vu32*)0x40008020)) // endpoint 0 control & transmittal length +#define R8_UEP0_T_LEN (*((vu8*)0x40008020)) // endpoint 0 transmittal length +#define R8_UEP0_CTRL (*((vu8*)0x40008022)) // endpoint 0 control +#define R32_USB_EP1_CTRL (*((vu32*)0x40008024)) // endpoint 1 control & transmittal length +#define R8_UEP1_T_LEN (*((vu8*)0x40008024)) // endpoint 1 transmittal length +#define R8_UEP1_CTRL (*((vu8*)0x40008026)) // endpoint 1 control +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R32_USB_EP2_CTRL (*((vu32*)0x40008028)) // endpoint 2 control & transmittal length +#define R8_UEP2_T_LEN (*((vu8*)0x40008028)) // endpoint 2 transmittal length +#define R8_UEP2_CTRL (*((vu8*)0x4000802A)) // endpoint 2 control + +#define R8_UH_EP_PID R8_UEP2_T_LEN // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R32_USB_EP3_CTRL (*((vu32*)0x4000802c)) // endpoint 3 control & transmittal length +#define R8_UEP3_T_LEN (*((vu8*)0x4000802c)) // endpoint 3 transmittal length +#define R8_UEP3_CTRL (*((vu8*)0x4000802e)) // endpoint 3 control +#define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R32_USB_EP4_CTRL (*((vu32*)0x40008030)) // endpoint 4 control & transmittal length +#define R8_UEP4_T_LEN (*((vu8*)0x40008030)) // endpoint 4 transmittal length +#define R8_UEP4_CTRL (*((vu8*)0x40008032)) // endpoint 4 control + +#define R32_USB_EP5_CTRL (*((vu32*)0x40008064)) // endpoint 5 control & transmittal length +#define R8_UEP5_T_LEN (*((vu8*)0x40008064)) // endpoint 5 transmittal length +#define R8_UEP5_CTRL (*((vu8*)0x40008066)) // endpoint 5 control + +#define R32_USB_EP6_CTRL (*((vu32*)0x40008068)) // endpoint 6 control & transmittal length +#define R8_UEP6_T_LEN (*((vu8*)0x40008068)) // endpoint 6 transmittal length +#define R8_UEP6_CTRL (*((vu8*)0x4000806A)) // endpoint 6 control + +#define R32_USB_EP7_CTRL (*((vu32*)0x4000806C)) // endpoint 7 control & transmittal length +#define R8_UEP7_T_LEN (*((vu8*)0x4000806C)) // endpoint 7 transmittal length +#define R8_UEP7_CTRL (*((vu8*)0x4000806E)) // endpoint 7 control + +#ifdef CH582_CH583 +/* USB2 */ +#define R32_USB2_CONTROL (*((vu32*)0x40008400)) // USB2 control & interrupt enable & device address +#define R8_USB2_CTRL (*((vu8*)0x40008400)) // USB2 base control +#define R8_U2DEV_CTRL (*((vu8*)0x40008401)) // USB2 device physical prot control +#define R8_U2HOST_CTRL R8_U2DEV_CTRL // USB2 host physical prot control +#define R8_USB2_INT_EN (*((vu8*)0x40008402)) // USB2 interrupt enable +#define R8_USB2_DEV_AD (*((vu8*)0x40008403)) // USB2 device address +#define R32_USB2_STATUS (*((vu32*)0x40008404)) // USB2 miscellaneous status & interrupt flag & interrupt status +#define R8_USB2_MIS_ST (*((vu8*)0x40008405)) // USB2 miscellaneous status +#define R8_USB2_INT_FG (*((vu8*)0x40008406)) // USB2 interrupt flag +#define R8_USB2_INT_ST (*((vu8*)0x40008407)) // USB2 interrupt status +#define R8_USB2_RX_LEN (*((vu8*)0x40008408)) // USB2 receiving length +#define R32_USB2_BUF_MODE (*((vu32*)0x4000840C)) // USB2 endpoint buffer mode +#define R8_U2EP4_1_MOD (*((vu8*)0x4000840C)) // USB2 endpoint 4/1 mode +#define R8_U2EP2_3_MOD (*((vu8*)0x4000840D)) // USB2 endpoint 2/3 mode +#define R8_U2EP567_MOD (*((vu8*)0x4000840E)) // USB2 endpoint 5/6/7 mode +#define R8_U2H_EP_MOD R8_U2EP2_3_MOD // USB2 host endpoint mode +#define R16_U2EP0_DMA (*((vu16*)0x40008410)) // USB2 endpoint 0 DMA buffer address +#define R16_U2EP1_DMA (*((vu16*)0x40008414)) // USB2 endpoint 1 DMA buffer address +#define R16_U2EP2_DMA (*((vu16*)0x40008418)) // USB2 endpoint 2 DMA buffer address +#define R16_U2H_RX_DMA R16_U2EP2_DMA // USB2 host rx endpoint buffer address +#define R16_U2EP3_DMA (*((vu16*)0x4000841C)) // USB2 endpoint 3 DMA buffer address +#define R16_U2H_TX_DMA R16_U2EP3_DMA // USB2 host tx endpoint buffer address +#define R16_U2EP5_DMA (*((vu16*)0x40008454)) // USB2 endpoint 5 DMA buffer address +#define R16_U2EP6_DMA (*((vu16*)0x40008458)) // USB2 endpoint 6 DMA buffer address +#define R16_U2EP7_DMA (*((vu16*)0x4000845C)) // USB2 endpoint 7 DMA buffer address +#define R32_USB2_EP0_CTRL (*((vu32*)0x40008420)) // USB2 endpoint 0 control & transmittal length +#define R8_U2EP0_T_LEN (*((vu8*)0x40008420)) // USB2 endpoint 0 transmittal length +#define R8_U2EP0_CTRL (*((vu8*)0x40008422)) // USB2 endpoint 0 control +#define R32_USB2_EP1_CTRL (*((vu32*)0x40008424)) // USB2 endpoint 1 control & transmittal length +#define R8_U2EP1_T_LEN (*((vu8*)0x40008424)) // USB2 endpoint 1 transmittal length +#define R8_U2EP1_CTRL (*((vu8*)0x40008426)) // USB2 endpoint 1 control +#define R8_U2H_SETUP R8_U2EP1_CTRL // USB2 host aux setup +#define R32_USB2_EP2_CTRL (*((vu32*)0x40008428)) // USB2 endpoint 2 control & transmittal length +#define R8_U2EP2_T_LEN (*((vu8*)0x40008428)) // USB2 endpoint 2 transmittal length +#define R8_U2EP2_CTRL (*((vu8*)0x4000842A)) // USB2 endpoint 2 control +#define R8_U2H_EP_PID R8_U2EP2_T_LEN // USB2 host endpoint and PID +#define R8_U2H_RX_CTRL R8_U2EP2_CTRL // USB2 host receiver endpoint control +#define R32_USB2_EP3_CTRL (*((vu32*)0x4000842c)) // USB2 endpoint 3 control & transmittal length +#define R8_U2EP3_T_LEN (*((vu8*)0x4000842c)) // USB2 endpoint 3 transmittal length +#define R8_U2EP3_CTRL (*((vu8*)0x4000842e)) // USB2 endpoint 3 control +#define R8_U2H_TX_LEN R8_U2EP3_T_LEN // USB2 host transmittal endpoint transmittal length +#define R8_U2H_TX_CTRL R8_U2EP3_CTRL // USB2 host transmittal endpoint control +#define R32_USB2_EP4_CTRL (*((vu32*)0x40008430)) // USB2 endpoint 4 control & transmittal length +#define R8_U2EP4_T_LEN (*((vu8*)0x40008430)) // USB2 endpoint 4 transmittal length +#define R8_U2EP4_CTRL (*((vu8*)0x40008432)) // USB2 endpoint 4 control +#define R32_USB2_EP5_CTRL (*((vu32*)0x40008464)) // USB2 endpoint 5 control & transmittal length +#define R8_U2EP5_T_LEN (*((vu8*)0x40008464)) // USB2 endpoint 5 transmittal length +#define R8_U2EP5_CTRL (*((vu8*)0x40008466)) // USB2 endpoint 5 control +#define R32_USB2_EP6_CTRL (*((vu32*)0x40008468)) // USB2 endpoint 6 control & transmittal length +#define R8_U2EP6_T_LEN (*((vu8*)0x40008468)) // USB2 endpoint 6 transmittal length +#define R8_U2EP6_CTRL (*((vu8*)0x4000846A)) // USB2 endpoint 6 control +#define R32_USB2_EP7_CTRL (*((vu32*)0x4000846C)) // USB2 endpoint 7 control & transmittal length +#define R8_U2EP7_T_LEN (*((vu8*)0x4000846C)) // USB2 endpoint 7 transmittal length +#define R8_U2EP7_CTRL (*((vu8*)0x4000846E)) // USB2 endpoint 7 control +#elif defined(CH584_CH585) +/* USB high speed device register */ +#define R8_USB2_CTRL (*((vu8*)0x40009000)) // RW, USB_high_speed control register +#define USBHS_UD_LPM_EN 0x80 // RW, enable LPM +#define USBHS_UD_DEV_EN 0x20 // RW, enable USB equipment +#define USBHS_UD_DMA_EN 0x10 // RW, enable DMA transmit +#define USBHS_UD_PHY_SUSPENDM 0x08 // RW, suspeng USB PHY +#define USBHS_UD_CLR_ALL 0x04 // RW, clear all interupt flag +#define USBHS_UD_RST_SIE 0x02 // RW, reset USB protocol processor,including end point register +#define USBHS_UD_RST_LINK 0x01 // RW, enable LNK layer reset +#define R8_USB2_BASE_MODE (*((vu8*)0x40009001)) // RW, USB_high_speed mode control register +#define USBHS_UD_SPEED_FULL 0x00 +#define USBHS_UD_SPEED_HIGH 0x01 +#define USBHS_UD_SPEED_LOW 0x02 +#define USBHS_UD_SPEED_TYPE 0x03 // RW, speed mode excpeted by the equipment,00:full speed, 01:high speed, 10:low speed +#define R8_USB2_INT_EN (*((vu8*)0x40009002)) // RW, USB_high_speed intreurpt enable register +#define USBHS_UDIE_FIFO_OVER 0x80 // RW, enable fifo overflow interupt +#define USBHS_UDIE_LINK_RDY 0x40 // RW, enable USB conect interupt +#define USBHS_UDIE_SOF_ACT 0x20 // RW, enable SOF package received interupt +#define USBHS_UDIE_TRANSFER 0x10 // RW, enable USB transmit end interupt +#define USBHS_UDIE_LPM_ACT 0x08 // RW, enable lpm transmit end interupt +#define USBHS_UDIE_BUS_SLEEP 0x04 // RW, enable usb bus sleep interupt +#define USBHS_UDIE_SUSPEND 0x02 // RW, enable usb bus suspend interupt +#define USBHS_UDIE_BUS_RST 0x01 // RW, enable usb bus reset interupt +#define R8_USB2_DEV_AD (*((vu8*)0x40009003)) // RW, USB_high_speed device adress register +#define USBHS_UD_DEV_ADDR 0x7F // RW, adress of usb equipment +#define R8_USB2_WAKE_CTRL (*((vu8*)0x40009004)) // RW, USB_high_speed wake up remotely register +#define USBHS_UD_UD_REMOTE_WKUP 0x01 // RW1, wake up remotely and auto reset hardware +#define R8_USB2_TEST_MODE (*((vu8*)0x40009005)) // RW, USB_high_speed test mode register +#define USBHS_UD_TEST_EN 0x80 // RW, enable test mode +#define USBHS_UD_TEST_SE0NAK 0x08 // RW, output SE0 when in test mode +#define USBHS_UD_TEST_PKT 0x04 // RW, output one package(including DATA0,data and length of end pont4) when in test mode,not work on virtual equipment +#define USBHS_UD_TEST_K 0x02 // RW, output K when in test mode +#define USBHS_UD_TEST_J 0x01 // RW, output J when in test mode +#define R16_USB2_LPM_DATA (*((vu16*)0x40009006)) // RW, USB_high_speed power control register +#define USBHS_UD_LPM_BUSY 0x8000 // RW, power control busy +#define USBHS_UD_LPM_DATA 0x07FF // RO, power control data +#define R8_USB2_INT_FG (*((vu8*)0x40009008)) // RW, USB_high_speed interupt flag register +#define USBHS_UDIF_FIFO_OV 0x80 // RW1, clear fifo overflow interupt flag +#define USBHS_UDIF_LINK_RDY 0x40 // RW1, clear USB conect interupt flag +#define USBHS_UDIF_RX_SOF 0x20 // RW1, clear SOF package received interupt flag +#define USBHS_UDIF_TRANSFER 0x10 // RO, USB transmit end interupt flag,cleared by USBHS_UDMS_HS_MOD +#define USBHS_UDIF_LPM_ACT 0x08 // RW1, clear lpm transmit end interupt flag +#define USBHS_UDIF_BUS_SLEEP 0x04 // RW1, clear usb bus sleep interupt flag +#define USBHS_UDIF_SUSPEND 0x02 // RW1, clear usb bus suspend interupt flag +#define USBHS_UDIF_BUS_RST 0x01 // RW1, clear usb bus reset interupt flag +#define R8_USB2_INT_ST (*((vu8*)0x40009009)) // RW, USB_high_speed interupt status register +#define USBHS_UDIS_EP_DIR 0x10 // RO, end point tranfer diector of data +#define USBHS_UDIS_EP_ID_MASK 0x07 // RO, number of end point which data transmission occured +#define R8_USB2_MIS_ST (*((vu8*)0x4000900A)) // RW, USB_high_speed miscellaneous register +#define USBHS_UDMS_HS_MOD 0x80 // RO, host with high speed +#define USBHS_UDMS_SUSP_REQ 0x10 // RO, requirment of suspending USB +#define USBHS_UDMS_SIE_FREE 0x08 // RO, USB free state +#define USBHS_UDMS_SLEEP 0x04 // RO, USB sleep state +#define USBHS_UDMS_SUSPEND 0x02 // RO, USB in suspend state +#define USBHS_UDMS_READY 0x01 // RO, USB in connected state +#define R16_USB2_FRAME_NO (*((vu16*)0x4000900C)) // RW, USB_high_speed frame number register +#define USBHS_UD_MFRAME_NO 0xE000 +#define USBHS_UD_FRAME_NO 0x07FF +#define R16_USB2_BUS (*((vu16*)0x4000900E)) // RW, USB_high_speed bus status register +#define USBHS_USB_DM_ST 0x08 +#define USBHS_USB_DP_ST 0x04 +#define USB_WAKEUP 0x01 +#define R16_U2EP_TX_EN (*((vu16*)0x40009010)) // RW, USB_high_speed end point transmit enable register +/* Bit definition for R16_U2EP_TX_EN & R16_U2EP_RX_EN register */ +#define RB_EP0_EN 0x0001 +#define RB_EP1_EN 0x0002 +#define RB_EP2_EN 0x0004 +#define RB_EP3_EN 0x0008 +#define RB_EP4_EN 0x0010 +#define RB_EP5_EN 0x0020 +#define RB_EP6_EN 0x0040 +#define RB_EP7_EN 0x0080 +#define RB_EP8_EN 0x0100 +#define RB_EP9_EN 0x0200 +#define RB_EP10_EN 0x0400 +#define RB_EP11_EN 0x0800 +#define RB_EP12_EN 0x1000 +#define RB_EP13_EN 0x2000 +#define RB_EP14_EN 0x4000 +#define RB_EP15_EN 0x8000 + +#define R16_U2EP_RX_EN (*((vu16*)0x40009012)) // RW, USB_high_speed end point receive enableregister +#define USBHS_UEP_RX_EN_MASK 0xFFFF +#define R16_U2EP_T_TOG_AUTO (*((vu16*)0x40009014)) // RW, USB_high_speed end point transmit auto toggle enable register +#define USBHS_UEP_T_TOG_AUTO_MASK 0xFF +#define R16_U2EP_R_TOG_AUTO (*((vu16*)0x40009016)) // RW, USB_high_speed end point receive auto toggle enable register +#define USBHS_UEP_R_TOG_AUTO_MASK 0xFF +#define R8_U2EP_T_BURST (*((vu8*)0x40009018)) // RW, USB_high_speed end point transmit burst register +#define USBHS_UEP_T_BURST_EN_MASK 0xFF +#define R8_U2EP_T_BURST_MODE (*((vu8*)0x40009019)) // RW, USB_high_speed end point transmit burst mode register +#define USBHS_UEP_T_BURST_MODE_MASK 0xFF +#define R8_U2EP_R_BURST (*((vu8*)0x4000901A)) // RW, USB_high_speed end point receive burst register +#define USBHS_UEP_R_BURST_EN_MASK 0xFF +#define R8_U2EP_R_RES_MODE (*((vu8*)0x4000901B)) // RW, USB_high_speed end point transmit reply mode register +#define USBHS_UEP_R_RES_MODE_MASK 0xFF +#define R32_U2EP_AF_MODE (*((vu32*)0x4000901C)) // RW, USB_high_speed end point multiplexing register +#define USBHS_UEP_T_AF_MASK 0xFE +#define R32_U2EP0_DMA (*((vu32*)0x40009020)) // RW, USB_high_speed end point0 begin adress of DMA buffer register +#define UEPn_DMA_MASK 0x01FFFF +#define R32_U2EP1_RX_DMA (*((vu32*)0x40009024)) // RW, USB_high_speed end point1 begin adress of DMA receive buffer register +#define R32_U2EP2_RX_DMA (*((vu32*)0x40009028)) // RW, USB_high_speed end point2 begin adress of DMA receive buffer register +#define R32_U2EP3_RX_DMA (*((vu32*)0x4000902C)) // RW, USB_high_speed end point3 begin adress of DMA receive buffer register +#define R32_U2EP4_RX_DMA (*((vu32*)0x40009030)) // RW, USB_high_speed end point4 begin adress of DMA receive buffer register +#define R32_U2EP5_RX_DMA (*((vu32*)0x40009034)) // RW, USB_high_speed end point5 begin adress of DMA receive buffer register +#define R32_U2EP6_RX_DMA (*((vu32*)0x40009038)) // RW, USB_high_speed end point6 begin adress of DMA receive buffer register +#define R32_U2EP7_RX_DMA (*((vu32*)0x4000903C)) // RW, USB_high_speed end point7 begin adress of DMA receive buffer register +#define UEPn_RX_DMA_MASK 0x01FFFF +#define R32_U2EP1_TX_DMA (*((vu32*)0x40009040)) // RW, USB_high_speed end point1 begin adress of DMA transmit buffer register +#define R32_U2EP2_TX_DMA (*((vu32*)0x40009044)) // RW, USB_high_speed end point2 begin adress of DMA transmit buffer register +#define R32_U2EP3_TX_DMA (*((vu32*)0x40009048)) // RW, USB_high_speed end point3 begin adress of DMA transmit buffer register +#define R32_U2EP4_TX_DMA (*((vu32*)0x4000904C)) // RW, USB_high_speed end point4 begin adress of DMA transmit buffer register +#define R32_U2EP5_TX_DMA (*((vu32*)0x40009050)) // RW, USB_high_speed end point5 begin adress of DMA transmit buffer register +#define R32_U2EP6_TX_DMA (*((vu32*)0x40009054)) // RW, USB_high_speed end point6 begin adress of DMA transmit buffer register +#define R32_U2EP7_TX_DMA (*((vu32*)0x40009058)) // RW, USB_high_speed end point7 begin adress of DMA transmit buffer register +#define UEPn_TX_DMA_MASK 0x01FFFF +#define R32_U2EP0_MAX_LEN (*((vu32*)0x4000905C)) // RW, USB_high_speed end point0 max length package register +#define R32_U2EP1_MAX_LEN (*((vu32*)0x40009060)) // RW, USB_high_speed end point1 max length package register +#define R32_U2EP2_MAX_LEN (*((vu32*)0x40009064)) // RW, USB_high_speed end point2 max length package register +#define R32_U2EP3_MAX_LEN (*((vu32*)0x40009068)) // RW, USB_high_speed end point3 max length package register +#define R32_U2EP4_MAX_LEN (*((vu32*)0x4000906C)) // RW, USB_high_speed end point4 max length package register +#define R32_U2EP5_MAX_LEN (*((vu32*)0x40009070)) // RW, USB_high_speed end point5 max length package register +#define R32_U2EP6_MAX_LEN (*((vu32*)0x40009074)) // RW, USB_high_speed end point6 max length package register +#define R32_U2EP7_MAX_LEN (*((vu32*)0x40009078)) // RW, USB_high_speed end point7 max length package register +#define UEPn_MAX_LEN_MASK 0x007F +#define R16_U2EP0_RX_LEN (*((vu16*)0x4000907C)) // RW, USB_high_speed end point0 length of receive register +#define UEP0_RX_LEN_MASK 0x007F +#define R16_U2EP1_RX_LEN (*((vu16*)0x40009080)) // RW, USB_high_speed end point1 single received length register +#define R16_U2EP1_R_SIZE (*((vu16*)0x40009082)) // RW, USB_high_speed end point1 total received length register +#define R16_U2EP2_RX_LEN (*((vu16*)0x40009084)) // RW, USB_high_speed end point2 single received length register +#define R16_U2EP2_R_SIZE (*((vu16*)0x40009086)) // RW, USB_high_speed end point2 total received length register +#define R16_U2EP3_RX_LEN (*((vu16*)0x40009088)) // RW, USB_high_speed end point3 single received length register +#define R16_U2EP3_R_SIZE (*((vu16*)0x4000908A)) // RW, USB_high_speed end point3 total received length register +#define R16_U2EP4_RX_LEN (*((vu16*)0x4000908C)) // RW, USB_high_speed end point4 single received length register +#define R16_U2EP4_R_SIZE (*((vu16*)0x4000908E)) // RW, USB_high_speed end point4 total received length register +#define R16_U2EP5_RX_LEN (*((vu16*)0x40009090)) // RW, USB_high_speed end point5 single received length register +#define R16_U2EP5_R_SIZE (*((vu16*)0x40009092)) // RW, USB_high_speed end point5 total received length register +#define R16_U2EP6_RX_LEN (*((vu16*)0x40009094)) // RW, USB_high_speed end point6 single received length register +#define R16_U2EP6_R_SIZE (*((vu16*)0x40009096)) // RW, USB_high_speed end point6 total received length register +#define R16_U2EP7_RX_LEN (*((vu16*)0x40009098)) // RW, USB_high_speed end point7 single received length register +#define R16_U2EP7_R_SIZE (*((vu16*)0x4000909A)) // RW, USB_high_speed end point7 total received length register +#define UEPn_RX_LEN_MASK 0xFFFF +#define UEPn_R_SIZE_MASK 0xFFFF +#define R16_U2EP0_T_LEN (*((vu16*)0x4000909C)) // RW, USB_high_speed end point0 length of transmission register +#define UEP0_T_LEN_MASK 0x7F +#define R8_U2EP0_TX_CTRL (*((vu8*)0x4000909E)) // RW, USB_high_speed end point0 transmit control register +#define R8_U2EP0_RX_CTRL (*((vu8*)0x4000909F)) // RW, USB_high_speed end point0 receive control register +#define R16_U2EP1_T_LEN (*((vu16*)0x400090A0)) // RW, USB_high_speed end point1 length of transmission register +#define R8_U2EP1_TX_CTRL (*((vu8*)0x400090A2)) // RW, USB_high_speed end point1 transmit control register +#define R8_U2EP1_RX_CTRL (*((vu8*)0x400090A3)) // RW, USB_high_speed end point1 receive control register +#define R16_U2EP2_T_LEN (*((vu16*)0x400090A4)) // RW, USB_high_speed end point2 length of transmission register +#define R8_U2EP2_TX_CTRL (*((vu8*)0x400090A6)) // RW, USB_high_speed end point2 transmit control register +#define R8_U2EP2_RX_CTRL (*((vu8*)0x400090A7)) // RW, USB_high_speed end point2 receive control register +#define R16_U2EP3_T_LEN (*((vu16*)0x400090A8)) // RW, USB_high_speed end point3 length of transmission register +#define R8_U2EP3_TX_CTRL (*((vu8*)0x400090AA)) // RW, USB_high_speed end point3 transmit control register +#define R8_U2EP3_RX_CTRL (*((vu8*)0x400090AB)) // RW, USB_high_speed end point3 receive control register +#define R16_U2EP4_T_LEN (*((vu16*)0x400090AC)) // RW, USB_high_speed end point4 length of transmission register +#define R8_U2EP4_TX_CTRL (*((vu8*)0x400090AE)) // RW, USB_high_speed end point4 transmit control register +#define R8_U2EP4_RX_CTRL (*((vu8*)0x400090AF)) // RW, USB_high_speed end point4 receive control register +#define R16_U2EP5_T_LEN (*((vu16*)0x400090B0)) // RW, USB_high_speed end point5 length of transmission register +#define R8_U2EP5_TX_CTRL (*((vu8*)0x400090B2)) // RW, USB_high_speed end point5 transmit control register +#define R8_U2EP5_RX_CTRL (*((vu8*)0x400090B3)) // RW, USB_high_speed end point5 receive control register +#define R16_U2EP6_T_LEN (*((vu16*)0x400090B4)) // RW, USB_high_speed end point6 length of transmission register +#define R8_U2EP6_TX_CTRL (*((vu8*)0x400090B6)) // RW, USB_high_speed end point6 transmit control register +#define R8_U2EP6_RX_CTRL (*((vu8*)0x400090B7)) // RW, USB_high_speed end point6 receive control register +#define R16_U2EP7_T_LEN (*((vu16*)0x400090B8)) // RW, USB_high_speed end point7 length of transmission register +#define R8_U2EP7_TX_CTRL (*((vu8*)0x400090BA)) // RW, USB_high_speed end point7 transmit control register +#define R8_U2EP7_RX_CTRL (*((vu8*)0x400090BB)) // RW, USB_high_speed end point7 receive control register +/**R16_UEPn_T_LEN**/ +#define UEPn_T_LEN 0xFFFF +/**R8_UEPn_TX_CTRL**/ +#define USBHS_UEP_T_DONE 0x80 +#define USBHS_UEP_T_NAK_ACT 0x40 +#define USBHS_UEP_T_TOG_MASK 0x0C +#define USBHS_UEP_T_TOG_MDATA 0x0C +#define USBHS_UEP_T_TOG_DATA2 0x08 +#define USBHS_UEP_T_TOG_DATA1 0x04 +#define USBHS_UEP_T_TOG_DATA0 0x00 +#define USBHS_UEP_T_RES_MASK 0x03 +#define USBHS_UEP_T_RES_ACK 0x02 +#define USBHS_UEP_T_RES_STALL 0x01 +#define USBHS_UEP_T_RES_NAK 0x00 + +/**R8_UEPn_RX_CTRL**/ +#define USBHS_UEP_R_DONE 0x80 +#define USBHS_UEP_R_NAK_ACT 0x40 +#define USBHS_UEP_R_NAK_TOG 0x20 +#define USBHS_UEP_R_TOG_MATCH 0x10 +#define USBHS_UEP_R_SETUP_IS 0x08 +#define USBHS_UEP_R_TOG_MASK 0x04 +//#define USBHS_UEP_R_TOG_MDATA 0x0C +//#define USBHS_UEP_R_TOG_DATA2 0x08 +#define USBHS_UEP_R_TOG_DATA1 0x04 +#define USBHS_UEP_R_TOG_DATA0 0x00 +#define USBHS_UEP_R_RES_MASK 0x03 +#define USBHS_UEP_R_RES_ACK 0x02 +#define USBHS_UEP_R_RES_STALL 0x01 +#define USBHS_UEP_R_RES_NAK 0x00 + +#define R16_U2EP_T_ISO (*((vu16*)0x400090BC)) // RW, USB_high_speed end point transmit sync mode register +#define USBHS_UEP1_T_ISO_EN 0x02 +#define USBHS_UEP2_T_ISO_EN 0x04 +#define USBHS_UEP3_T_ISO_EN 0x08 +#define USBHS_UEP4_T_ISO_EN 0x10 +#define USBHS_UEP5_T_ISO_EN 0x20 +#define USBHS_UEP6_T_ISO_EN 0x40 +#define USBHS_UEP7_T_ISO_EN 0x80 +#define R16_U2EP_R_ISO (*((vu16*)0x400090BE)) // RW, USB_high_speed end point receive sync mode register +#define USBHS_UEP1_R_ISO_EN 0x02 +#define USBHS_UEP2_R_ISO_EN 0x04 +#define USBHS_UEP3_R_ISO_EN 0x08 +#define USBHS_UEP4_R_ISO_EN 0x10 +#define USBHS_UEP5_R_ISO_EN 0x20 +#define USBHS_UEP6_R_ISO_EN 0x40 +#define USBHS_UEP7_R_ISO_EN 0x80 + +/* USB high speed host register */ +#define R8_U2H_CFG (*((vu8*)0x40009100)) // RW, USB_high_speed register +#define USBHS_UH_LPM_EN 0x80 +#define USBHS_UH_FORCE_FS 0x40 +#define USBHS_UH_SOF_EN 0x20 +#define USBHS_UH_DMA_EN 0x10 +#define USBHS_UH_PHY_SUSPENDM 0x08 +#define USBHS_UH_CLR_ALL 0x04 +#define USBHS_RST_SIE 0x02 +#define USBHS_RST_LINK 0x01 +#define R8_U2H_INT_EN (*((vu8*)0x40009102)) // RW, USB_high_speed register +#define USBHS_UHIE_FIFO_OVER 0x80 +#define USBHS_UHIE_TX_HALT 0x40 +#define USBHS_UHIE_SOF_ACT 0x20 +#define USBHS_UHIE_TRANSFER 0x10 +#define USBHS_UHIE_RESUME_ACT 0x08 +#define USBHS_UHIE_WKUP_ACT 0x04 +#define R8_U2H_DEV_AD (*((vu8*)0x40009103)) // RW, USB_high_speed register +#define USBHS_UH_DEV_ADDR 0xFF +#define R32_U2H_CONTROL (*((vu32*)0x40009104)) // RW, USB_high_speed register +#define USBHS_UH_RX_NO_RES 0x800000 +#define USBHS_UH_TX_NO_RES 0x400000 +#define USBHS_UH_RX_NO_DATA 0x200000 +#define USBHS_UH_TX_NO_DATA 0x100000 +#define USBHS_UH_PRE_PID_EN 0x080000 +#define USBHS_UH_SPLIT_VALID 0x040000 +#define USBHS_UH_LPM_VALID 0x020000 +#define USBHS_UH_HOST_ACTION 0x010000 +#define USBHS_UH_BUF_MODE 0x0400 +#define USBHS_UH_T_TOG_MASK 0x0300 +#define USBHS_UH_T_TOG_MDATA 0x0300 +#define USBHS_UH_T_TOG_DATA2 0x0200 +#define USBHS_UH_T_TOG_DATA1 0x0100 +#define USBHS_UH_T_TOG_DATA0 0x0000 +#define USBHS_UH_T_ENDP_MASK 0xF0 +#define USBHS_UH_T_TOKEN_MASK 0x0F + +#define R8_U2H_INT_FLAG (*((vu8*)0x40009108)) // RW, USB_high_speed register +#define USBHS_UHIF_FIFO_OVER 0x80 +#define USBHS_UHIF_TX_HALT 0x40 +#define USBHS_UHIF_SOF_ACT 0x20 +#define USBHS_UHIF_TRANSFER 0x10 +#define USBHS_UHIF_RESUME_ACT 0x08 +#define USBHS_UHIF_WKUP_ACT 0x04 +#define R8_U2H_INT_ST (*((vu8*)0x40009109)) // RW, USB_high_speed register +#define USBHS_UHIF_PORT_RX_RESUME 0x10 +#define USBHS_UH_R_TOKEN_MASK 0x0F +#define R8_U2H_MIS_ST (*((vu8*)0x4000910A)) // RW, USB_high_speed register +#define USBHS_UHMS_BUS_SE0 0x80 +#define USBHS_UHMS_BUS_J 0x40 +#define USBHS_UHMS_LINESTATE 0x30 +#define USBHS_UHMS_USB_WAKEUP 0x08 +#define USBHS_UHMS_SOF_ACT 0x04 +#define USBHS_UHMS_SOF_PRE 0x02 +#define USBHS_UHMS_SOF_FREE 0x01 +#define R32_U2H_LPM_DATA (*((vu32*)0x4000910C)) // RW, USB_high_speed register +#define USBHS_UH_LPM_DATA 0x07FF +#define R32_U2H_SPLIT_DATA (*((vu32*)0x40009110)) // RW, USB_high_speed register +#define USBHS_UH_SPLIT_DATA 0x07FFFF +#define R32_U2H_FRAME (*((vu32*)0x40009114)) // RW, USB_high_speed register +#define USBHS_UH_SOF_CNT_CLR 0x02000000 +#define USBHS_UH_SOF_CNT_EN 0x01000000 +#define USBHS_UH_MFRAME_NO 0x070000 +#define USBHS_UH_FRAME_NO 0x07FF +#define R32_U2H_TX_LEN (*((vu32*)0x40009118)) // RW, USB_high_speed register +#define USBHS_UH_TX_LEN 0x07FF +#define R32_U2H_RX_LEN (*((vu32*)0x4000911C)) // RW, USB_high_speed register +#define USBHS_UH_RX_LEN 0x07FF +#define R32_U2H_RX_MAX_LEN (*((vu32*)0x40009120)) // RW, USB_high_speed register +#define USBHS_UH_RX_MAX_LEN 0x07FF +#define R32_U2H_RX_DMA (*((vu32*)0x40009124)) // RW, USB_high_speed register +#define USBHS_R32_UH_RX_DMA 0x01FFFF +#define R32_U2H_TX_DMA (*((vu32*)0x40009128)) // RW, USB_high_speed register +#define USBHS_R32_UH_TX_DMA 0x01FFFF +#define R32_U2H_PORT_CTRL (*((vu32*)0x4000912C)) // RW, USB_high_speed register +#define USBHS_UH_BUS_RST_LONG 0x010000 +#define USBHS_UH_PORT_SLEEP_BESL 0xF000 +#define USBHS_UH_CLR_PORT_SLEEP 0x0100 +#define USBHS_UH_CLR_PORT_CONNECT 0x20 +#define USBHS_UH_CLR_PORT_EN 0x10 +#define USBHS_UH_SET_PORT_SLEEP 0x08 +#define USBHS_UH_CLR_PORT_SUSP 0x04 +#define USBHS_UH_SET_PORT_SUSP 0x02 +#define USBHS_UH_SET_PORT_RESET 0x01 +#define R8_U2H_PORT_CFG (*((vu8*)0x40009130)) // RW, USB_high_speed register +#define USBHS_UH_PD_EN 0x80 +#define USBHS_UH_HOST_EN 0x01 +#define R8_U2H_PORT_INT_EN (*((vu8*)0x40009132)) // RW, USB_high_speed register +#define USBHS_UHIE_PORT_SLP 0x20 +#define USBHS_UHIE_PORT_RESET 0x10 +#define USBHS_UHIE_PORT_SUSP 0x04 +#define USBHS_UHIE_PORT_EN 0x02 +#define USBHS_UHIE_PORT_CONNECT 0x01 +#define R8_U2H_PORT_TEST_CT (*((vu8*)0x40009133)) // RW, USB_high_speed register +#define USBHS_UH_TEST_FORCE_EN 0x04 +#define USBHS_UH_TEST_K 0x02 +#define USBHS_UH_TEST_J 0x01 +#define R16_U2H_PORT_ST (*((vu16*)0x40009134)) // RW, USB_high_speed register +#define USBHS_UHIS_PORT_TEST 0x0800 +#define USBHS_UHIS_PORT_SPEED_MASK 0x0600 +#define USBHS_UHIS_PORT_HS 0x0400 +#define USBHS_UHIS_PORT_LS 0x0200 +#define USBHS_UHIS_PORT_FS 0x0000 +#define USBHS_UHIS_PORT_SLP 0x20 +#define USBHS_UHIS_PORT_RST 0x10 +#define USBHS_UHIS_PORT_SUSP 0x04 +#define USBHS_UHIS_PORT_EN 0x02 +#define USBHS_UHIS_PORT_CONNECT 0x01 +#define R8_U2H_PORT_CHG (*((vu8*)0x40009136)) +#define USBHS_UHIF_PORT_SLP 0x20 +#define USBHS_UHIF_PORT_RESET 0x10 +#define USBHS_UHIF_PORT_SUSP 0x04 +#define USBHS_UHIF_PORT_EN 0x02 +#define USBHS_UHIF_PORT_CONNECT 0x01 +#define R32_U2H_BC_CTRL (*((vu32*)0x4000913C)) +#define UDM_VSRC_ACT 0x0400 +#define UDM_BC_VSRC 0x0200 +#define UDP_BC_VSRC 0x0100 +#define BC_AUTO_MODE 0x40 +#define UDM_BC_CMPE 0x20 +#define UDP_BC_CMPE 0x10 +#define UDM_BC_CMPO 0x02 +#define UDP_BC_CMPO 0x01 +#define R8_USBHS_PLL_CTRL (*((vu8*)0x40009200)) +#define USBHS_PLL_EN 0x04 +#define USBHS_PLL_LOWPOW 0x02 +#define USBHS_PLL_CKSEL 0x01 +#endif + +#define LL_TX_POWER_MINUS_25_DBM 0x01 +#define LL_TX_POWER_MINUS_20_DBM 0x02 +#define LL_TX_POWER_MINUS_15_DBM 0x03 +#define LL_TX_POWER_MINUS_10_DBM 0x05 +#define LL_TX_POWER_MINUS_8_DBM 0x07 +#define LL_TX_POWER_MINUS_5_DBM 0x0A +#define LL_TX_POWER_MINUS_3_DBM 0x0C +#define LL_TX_POWER_MINUS_1_DBM 0x10 +#define LL_TX_POWER_0_DBM 0x12 +#define LL_TX_POWER_1_DBM 0x15 +#define LL_TX_POWER_2_DBM 0x18 +#define LL_TX_POWER_3_DBM 0x1B +#define LL_TX_POWER_4_DBM 0x1F +#define LL_TX_POWER_5_DBM 0x25 +#define LL_TX_POWER_6_DBM 0x2D +#define LL_TX_POWER_7_DBM 0x3B + + +RV_STATIC_INLINE void LSIEnable() +{ + SYS_SAFE_ACCESS + ( +#ifdef CH570_CH572 + R8_LSI_CONFIG |= RB_CLK_LSI_PON; //turn on LSI +#else + R8_CK32K_CONFIG &= ~(RB_CLK_OSC32K_XT | RB_CLK_XT32K_PON); // turn off LSE + R8_CK32K_CONFIG |= RB_CLK_INT32K_PON; // turn on LSI +#endif + ); +} +RV_STATIC_INLINE void DCDCEnable() +{ +#ifndef CH570_CH572 // CH570/2 has no DCDC. + SYS_SAFE_ACCESS + ( + R16_AUX_POWER_ADJ |= RB_DCDC_CHARGE; + R16_POWER_PLAN |= RB_PWR_DCDC_PRE; + ); + + RTC_WAIT_TICKS(2); + + SYS_SAFE_ACCESS + ( + R16_POWER_PLAN |= RB_PWR_DCDC_EN; + ); +#endif +} + +RV_STATIC_INLINE void SleepInit() +{ + SYS_SAFE_ACCESS + ( + R8_RTC_MODE_CTRL |= RB_RTC_TRIG_EN; //enable RTC trigger + R8_SLP_WAKE_CTRL |= RB_SLP_RTC_WAKE; // enable wakeup control + ); + //enable RTC interrupt + NVIC->IENR[((uint32_t)(RTC_IRQn) >> 5)] = (1 << ((uint32_t)(RTC_IRQn) & 0x1F)); +} + +//clear RTC counters. +//probabily not needed for most cases, waking up from +//power off resets the RTC anyway. +RV_STATIC_INLINE void RTCInit() +{ + SYS_SAFE_ACCESS + ( + R32_RTC_TRIG = 0; + R32_RTC_CTRL |= RB_RTC_LOAD_HI; + R32_RTC_CTRL |= RB_RTC_LOAD_LO; + R8_RTC_MODE_CTRL |= RB_RTC_TRIG_EN; //enable RTC trigger + ); + +} + +//Set RTC to generate an interrupt after cyc ticks. +RV_STATIC_INLINE void RTCTrigger(uint32_t cyc) +{ + //get the rtc current time + uint32_t alarm = (uint32_t) R16_RTC_CNT_LSI | ( (uint32_t) R16_RTC_CNT_DIV1 << 16 ); + + alarm += cyc; + + if( alarm > RTC_MAX_COUNT ) + { + alarm -= RTC_MAX_COUNT; + } + + SYS_SAFE_ACCESS + ( + R32_RTC_TRIG = alarm; + ); +} + +// enter idle state +RV_STATIC_INLINE void LowPowerIdle(uint32_t cyc) +{ + RTCTrigger(cyc); + + NVIC->SCTLR &= ~(1 << 2); // don't deep sleep + NVIC->SCTLR &= ~(1 << 3); // wfi + asm volatile ("wfi\nnop\nnop" ); +} + +// This macro defines which power pin +// to use. If not defined correctly, sleep current +// will be higher than expected. +#ifndef FUNCONF_POWERED_BY_V5PIN +#define FUNCONF_POWERED_BY_V5PIN 0 +#endif + +RV_STATIC_INLINE void LowPowerSleep(uint32_t cyc, uint16_t power_plan) +{ +#if defined(CH570_CH572) && (FUNCONF_POWERED_BY_V5PIN == 1) + power_plan |= RB_PWR_LDO5V_EN; +#endif + + RTCTrigger(cyc); + +#ifdef CH570_CH572 +#if ( CLK_SOURCE_CH5XX == CLK_SOURCE_PLL_75MHz ) || ( CLK_SOURCE_CH5XX == CLK_SOURCE_PLL_100MHz ) + //if system clock is higher than 60Mhz, it need to be reduced before sleep. + SYS_SAFE_ACCESS + ( + R8_CLK_SYS_CFG = CLK_SOURCE_PLL_60MHz; + ); +#endif +#else + SYS_SAFE_ACCESS + ( + R8_BAT_DET_CTRL = 0; + R8_XT32K_TUNE = (R16_RTC_CNT_32K > 0x3fff) ? (R8_XT32K_TUNE & 0xfc) | 0x01 : R8_XT32K_TUNE; + R8_XT32M_TUNE = (R8_XT32M_TUNE & 0xfc) | 0x03; + ); +#endif + + NVIC->SCTLR |= (1 << 2); //deep sleep + SYS_SAFE_ACCESS + ( + R8_SLP_POWER_CTRL |= RB_RAM_RET_LV; + R16_POWER_PLAN = RB_PWR_PLAN_EN | RB_PWR_CORE | power_plan; + R8_PLL_CONFIG |= (1 << 5); + ); + + NVIC->SCTLR &= ~(1 << 3); // wfi + asm volatile ("wfi\nnop\nnop" ); + +#ifdef CH570_CH572 +#if ( CLK_SOURCE_CH5XX == CLK_SOURCE_PLL_75MHz ) || ( CLK_SOURCE_CH5XX == CLK_SOURCE_PLL_100MHz ) + //machine delay for a while. + uint16_t i = 400; + do { + asm volatile("nop"); + } while(i--); + + //get system clock back to normal + SYS_SAFE_ACCESS + ( + R8_CLK_SYS_CFG = CLK_SOURCE_CH5XX; + ); +#endif +#else + SYS_SAFE_ACCESS + ( + R16_POWER_PLAN &= ~RB_XT_PRE_EN; + R8_PLL_CONFIG &= ~(1 << 5); + R8_XT32M_TUNE = (R8_XT32M_TUNE & 0xfc) | 0x01; + ); +#endif +} + +RV_STATIC_INLINE void LowPower(uint32_t time, uint16_t power_plan) +{ + if( time > 500){ + LowPowerSleep( time, power_plan ); + } else { + LowPowerIdle( time ); + } + +} + +RV_STATIC_INLINE void jump_isprom() +{ + memcpy((void*)ISPROM_IN_RAM_ADDRESS, (void*)(ISPROM_ADDRESS + ISPROM_START_OFFSET), ISPROM_SIZE); // copy bootloader to ram +#ifdef CH570_CH572 + *(int32_t*)(ISPROM_BOOTBUTTON_CHECK_ADDRESS + 0xc) = 0x00014505; // nop \n li a0,1, patch PA1 detection +#elif defined(CH582_CH583) + *(int16_t*)(ISPROM_BOOTBUTTON_CHECK_ADDRESS + 0xe) = 0x4505; // li a0, 1, patch PB22 detection to always return true +#elif (defined(CH584_CH585) || defined(CH591_CH592)) + *(int16_t*)(ISPROM_BOOTBUTTON_CHECK_ADDRESS + 0xa) = 0x4505; // li a0,1, patch PB11 (option byte is not read correctly) detection +#endif + +#if (defined(CH570_CH572) || defined(CH584_CH585) || defined(CH591_CH592)) + memset((void*)ISPROM_BSS_ADDRESS, 0, ISPROM_BSS_SIZE); // clear .bss + + asm( "la gp, " ISPROM_IN_RAM_GLOBALPOINTER "\n" + ".option arch, +zicsr\n" + "li t0, " ISPROM_IN_RAM_ENTRYPOINT "\n" + "csrw mepc, t0\n" // __set_MEPC is not available here + "mret\n"); +#elif defined(CH582_CH583) + asm( "la gp, " ISPROM_GLOBALPOINTER "\n" + "j " ISPROM_ENTRYPOINT "\n"); +#endif +} + +#define HardFault_IRQn EXC_IRQn + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifdef __cplusplus +} +#endif + +#endif // Header guard diff --git a/inc/ch641hw.h b/inc/ch641hw.h new file mode 100644 index 0000000..add26db --- /dev/null +++ b/inc/ch641hw.h @@ -0,0 +1,5187 @@ +#ifndef TODO_HARDWARE_H +#define TODO_HARDWARE_H + +#include "ch32fun.h" + +#ifndef __ASSEMBLER__ // Things before this can be used in assembly. + +#ifdef __cplusplus +extern "C" { +#endif + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + EXTI15_8_IRQn = 33, /* External Line[15:8] Interrupts Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ + USBPD_IRQn = 39, /* USBPD global Interrupt */ + USBPDWakeUp_IRQn = 40, /* USBPD WakeUp global Interrupt */ +} IRQn_Type; + +#define DEFAULT_INTERRUPT_VECTOR_CONTENTS "\n\ + .align 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .word 0\n\ + .word NMI_Handler /* NMI Handler */ \n\ + .word HardFault_Handler /* Hard Fault Handler */ \n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word 0\n\ + .word SysTick_Handler /* SysTick Handler */ \n\ + .word 0\n\ + .word SW_Handler /* SW Handler */ \n\ + .word 0\n\ + .word WWDG_IRQHandler /* Window Watchdog */ \n\ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n\ + .word FLASH_IRQHandler /* Flash */ \n\ + .word RCC_IRQHandler /* RCC */ \n\ + .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ \n\ + .word AWU_IRQHandler /* AWU */ \n\ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n\ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n\ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n\ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n\ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n\ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n\ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n\ + .word ADC1_IRQHandler /* ADC1 */ \n\ + .word I2C1_EV_IRQHandler /* I2C1 Event */ \n\ + .word I2C1_ER_IRQHandler /* I2C1 Error */ \n\ + .word USART1_IRQHandler /* USART1 */ \n\ + .word EXTI15_8_IRQHandler /* External Line[8:15] Interrupt */ \n\ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n\ + .word TIM1_UP_IRQHandler /* TIM1 Update */ \n\ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n\ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n\ + .word TIM2_IRQHandler /* TIM2 */ \n\ + .word USBPD_IRQHandler /* USB Power Delivery Interrupt */ \n\ + .word USBPD_WKUP_IRQHandler /* USB Power Delivery Wake-Up Interrupt */ \n\ + .option pop;\n" + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint32_t CNT; + uint32_t RESERVED0; + __IO uint32_t CMP; + uint32_t RESERVED1; +} SysTick_Type; + + +#endif /* __ASSEMBLER__*/ + +#define HardFault_IRQn EXC_IRQn + + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +#ifndef __ASSEMBLER__ +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t DLYR; +} ADC_TypeDef; + + + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; +} OB_TypeDef; + +typedef struct +{ + __IO uint16_t CAP; + __IO uint16_t RES1; + __IO uint32_t RES2; + __IO uint32_t UID0; + __IO uint32_t UID1; + __IO uint32_t UID2; + __IO uint32_t RES3; +} ESG_TypeDef; + +typedef struct +{ + union + { + __I uint32_t CHIPID; + struct + { + __I uint16_t REVID; + __I uint16_t DEVID; + }; + }; +} INFO_TypeDef; + + +/* General Purpose I/O */ +typedef enum +{ + GPIO_CFGLR_IN_ANALOG = 0, + GPIO_CFGLR_IN_FLOAT = 4, + GPIO_CFGLR_IN_PUPD = 8, + GPIO_CFGLR_OUT_10Mhz_PP = 1, + GPIO_CFGLR_OUT_2Mhz_PP = 2, + GPIO_CFGLR_OUT_50Mhz_PP = 3, + GPIO_CFGLR_OUT_10Mhz_OD = 5, + GPIO_CFGLR_OUT_2Mhz_OD = 6, + GPIO_CFGLR_OUT_50Mhz_OD = 7, + GPIO_CFGLR_OUT_10Mhz_AF_PP = 9, + GPIO_CFGLR_OUT_2Mhz_AF_PP = 10, + GPIO_CFGLR_OUT_50Mhz_AF_PP = 11, + GPIO_CFGLR_OUT_10Mhz_AF_OD = 13, + GPIO_CFGLR_OUT_2Mhz_AF_OD = 14, + GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, +} GPIO_CFGLR_PIN_MODE_Typedef; + +typedef union { + uint32_t __FULL; + struct { + GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; + GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; + }; +} GPIO_CFGLR_t; +typedef union { + uint32_t __FULL; + const struct { + uint32_t IDR0 :1; + uint32_t IDR1 :1; + uint32_t IDR2 :1; + uint32_t IDR3 :1; + uint32_t IDR4 :1; + uint32_t IDR5 :1; + uint32_t IDR6 :1; + uint32_t IDR7 :1; + uint32_t :24; + }; +} GPIO_INDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t ODR0 :1; + uint32_t ODR1 :1; + uint32_t ODR2 :1; + uint32_t ODR3 :1; + uint32_t ODR4 :1; + uint32_t ODR5 :1; + uint32_t ODR6 :1; + uint32_t ODR7 :1; + uint32_t :24; + }; +} GPIO_OUTDR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BS0 :1; + uint32_t BS1 :1; + uint32_t BS2 :1; + uint32_t BS3 :1; + uint32_t BS4 :1; + uint32_t BS5 :1; + uint32_t BS6 :1; + uint32_t BS7 :1; + uint32_t :8; + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :8; + }; +} GPIO_BSHR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t BR0 :1; + uint32_t BR1 :1; + uint32_t BR2 :1; + uint32_t BR3 :1; + uint32_t BR4 :1; + uint32_t BR5 :1; + uint32_t BR6 :1; + uint32_t BR7 :1; + uint32_t :24; + }; +} GPIO_BCR_t; +typedef union { + uint32_t __FULL; + struct { + uint32_t LCK0 :1; + uint32_t LCK1 :1; + uint32_t LCK2 :1; + uint32_t LCK3 :1; + uint32_t LCK4 :1; + uint32_t LCK5 :1; + uint32_t LCK6 :1; + uint32_t LCK7 :1; + uint32_t LCKK :1; + uint32_t :23; + }; +} GPIO_LCKR_t; +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __I uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) +#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL +#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; + __IO uint32_t AWUCSR; + __IO uint32_t AWUWR; + __IO uint32_t AWUPSC; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t RESERVED0; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + + + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint16_t DMAADR; + uint16_t RESERVED15; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t CTLR0; + __IO uint32_t RESERVED; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; +} EXTEN_TypeDef; + +/* The reference manual for the ch32v2xx/v3xx reference this as "CTR" field in the "EXTEND" register so adding an alias here. */ +typedef struct +{ + __IO uint32_t CTR; +} EXTEND_TypeDef; + + + +/* USB Power Delivery */ +typedef struct +{ + __IO uint32_t CONFIG; + __IO uint32_t CONTROL; + __IO uint32_t STATUS; + __IO uint32_t PORT; + __IO uint32_t DMA; +} USBPD_TypeDef; + + +/* USB Power Delivery */ +typedef struct +{ + __IO uint16_t CONFIG; + __IO uint16_t BCM_CLK_CNT; + + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + __IO uint16_t BMC_TX_SZ; + + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + __IO uint16_t BMC_BYTE_CNT; + + __IO uint8_t PORT_CC1; + __IO uint8_t RESERVED0; + __IO uint8_t PORT_CC2; + __IO uint8_t PORT_CC3; + + __IO uint32_t USBPD_DMA; +} USBPD_DETAILED_TypeDef; + + + +#endif + +/* Peripheral memory map */ +#ifdef __ASSEMBLER__ +#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ +#else +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ +#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ +#endif + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ + + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define ESIG_BASE ((uint32_t)0x1FFFF7E0) +#define INFO_BASE ((uint32_t)0x1FFFF704) + +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define USBPD_BASE (AHBPERIPH_BASE + 0x4000) + +#define VENDOR_CFG0_BASE ((uint32_t)0x1FFFF7D4) +#define CFG0_PLL_TRIM (VENDOR_CFG0_BASE) +#define CFG0_PD_C (VENDOR_CFG0_BASE + 0x02) + +#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) +#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) + + + + + + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ESIG ((ESG_TypeDef *)ESIG_BASE) +// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. +#define INFO ((INFO_TypeDef *)INFO_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN + + + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_CALVOLSELECT ((uint32_t)0x06000000) +#define ADC_CALVOLSELECT_0 ((uint32_t)0x02000000) +#define ADC_CALVOLSELECT_1 ((uint32_t)0x04000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +#define ADC_TRIG_SEL0 ((uint32_t)0x01000000) +#define ADC_TRIG_SEL1 ((uint32_t)0x02000000) +#define ADC_TRIG_SEL2 ((uint32_t)0x04000000) +#define ADC_TRIG_SEL3 ((uint32_t)0x08000000) +#define ADC_TRIG_SEL4 ((uint32_t)0x10000000) +#define ADC_REGU_SWOFF ((uint32_t)0x20000000) +#define ADC_INJE_SWOFF ((uint32_t)0x40000000) + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************** Bit definition for ADC_DLYR register ********************/ +#define ADC_DLYR_DLYVLU ((uint32_t)0x1FF) +#define ADC_DLYR_DLYSRC ((uint32_t)0x200) + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction (Setting = Memory -> Peripheral) */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR4 register *******************/ +#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFGR5 register *******************/ +#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFGR6 register *******************/ +#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR7 register *******************/ +#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_MODE ((uint16_t)0x4000) +#define FLASH_STATR_LOCK ((uint16_t)0x8000) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG (0x0001) /* Programming */ +#define FLASH_CTLR_PER (0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER (0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG (0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER (0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT (0x0040) /* Start */ +#define FLASH_CTLR_LOCK (0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE (0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE (0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE (0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FLOCK (0x8000) +#define FLASH_CTLR_PAGE_PG (0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER (0x00020000) /* Page Erase 64Byte */ +#define FLASH_CTLR_BUF_LOAD (0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST (0x00080000) /* Buffer Reset */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_STANDY_RST ((uint16_t)0x0010) +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080) +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH__BOOT_MODEKEYR register ******************/ +#define FLASH_BOOT_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_BOOT_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000003) /* I2C1_REMAP[1:0] bits */ +#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000001) +#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000002) + +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x0000001C) /* USART1_REMAP[2:0] bits */ +#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000004) +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000008) +#define AFIO_PCFR1_USART1_REMAP_2 ((uint32_t)0x00000010) + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00000040) + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SW_CFG ((uint32_t)0x07000000) /* SW_CFG[2:0] bits (SDI configuration) */ +#define AFIO_PCFR1_SW_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SW_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SW_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0001) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x0002) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0004) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x0008) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0010) +#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0020) +#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x0040) +#define AFIO_EXTICR1_EXTI7 ((uint16_t)0x0080) +#define AFIO_EXTICR1_EXTI8 ((uint16_t)0x0100) +#define AFIO_EXTICR1_EXTI9 ((uint16_t)0x0200) +#define AFIO_EXTICR1_EXTI10 ((uint16_t)0x0400) +#define AFIO_EXTICR1_EXTI11 ((uint16_t)0x0800) +#define AFIO_EXTICR1_EXTI12 ((uint16_t)0x1000) +#define AFIO_EXTICR1_EXTI13 ((uint16_t)0x2000) +#define AFIO_EXTICR1_EXTI14 ((uint16_t)0x4000) +#define AFIO_EXTICR1_EXTI15 ((uint16_t)0x8000) + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0002) /* PB[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0004) /* PB[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x0008) /* PB[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint16_t)0x0010) /* PB[4] pin */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint16_t)0x0020) /* PB[5] pin */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint16_t)0x0040) /* PB[6] pin */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint16_t)0x0080) /* PB[7] pin */ + +#define AFIO_EXTICR1_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR1_EXTI8_PB ((uint16_t)0x0100) /* PB[8] pin */ + +#define AFIO_EXTICR1_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR1_EXTI9_PB ((uint16_t)0x0200) /* PB[9] pin */ + +#define AFIO_EXTICR1_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR1_EXTI10_PB ((uint16_t)0x0400) /* PB[10] pin */ + +#define AFIO_EXTICR1_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR1_EXTI11_PB ((uint16_t)0x0800) /* PB[11] pin */ + +#define AFIO_EXTICR1_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR1_EXTI12_PB ((uint16_t)0x1000) /* PB[12] pin */ + +#define AFIO_EXTICR1_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR1_EXTI13_PB ((uint16_t)0x2000) /* PB[13] pin */ + +#define AFIO_EXTICR1_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR1_EXTI14_PB ((uint16_t)0x4000) /* PB[14] pin */ + +#define AFIO_EXTICR1_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR1_EXTI15_PB ((uint16_t)0x8000) /* PB[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_PVDLevel_0 ((uint16_t)0x0000) +#define PWR_PVDLevel_1 ((uint16_t)0x0020) +#define PWR_PVDLevel_2 ((uint16_t)0x0040) +#define PWR_PVDLevel_3 ((uint16_t)0x0060) +#define PWR_PVDLevel_4 ((uint16_t)0x0080) +#define PWR_PVDLevel_5 ((uint16_t)0x00A0) +#define PWR_PVDLevel_6 ((uint16_t)0x00C0) +#define PWR_PVDLevel_7 ((uint16_t)0x00E0) + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************* Bit definition for PWR_AWUCSR register ********************/ +#define PWR_AWUCLR ((uint16_t)0x0001) +#define PWR_AWUCSR_AWUEN ((uint16_t)0x0002) + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUWR ((uint16_t)0x003F) + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUPSC ((uint16_t)0x000F) +#define PWR_AWUPSC_0 ((uint16_t)0x0000) +#define PWR_AWUPSC_2 ((uint16_t)0x0002) +#define PWR_AWUPSC_4 ((uint16_t)0x0003) +#define PWR_AWUPSC_8 ((uint16_t)0x0004) +#define PWR_AWUPSC_16 ((uint16_t)0x0005) +#define PWR_AWUPSC_32 ((uint16_t)0x0006) +#define PWR_AWUPSC_64 ((uint16_t)0x0007) +#define PWR_AWUPSC_128 ((uint16_t)0x0008) +#define PWR_AWUPSC_256 ((uint16_t)0x0009) +#define PWR_AWUPSC_512 ((uint16_t)0x000A) +#define PWR_AWUPSC_1024 ((uint16_t)0x000B) +#define PWR_AWUPSC_2048 ((uint16_t)0x000C) +#define PWR_AWUPSC_4096 ((uint16_t)0x000D) +#define PWR_AWUPSC_10240 ((uint16_t)0x000E) +#define PWR_AWUPSC_61440 ((uint16_t)0x000F) + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_ADCPRE ((uint32_t)0x0001F800) /* ADCPRE[5:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_ADCPRE_2 ((uint32_t)0x00002000) +#define RCC_ADCPRE_3 ((uint32_t)0x00004000) +#define RCC_ADCPRE_4 ((uint32_t)0x00008000) +#define RCC_ADCPRE_5 ((uint32_t)0x00010000) + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ +#define RCC_ADCPRE_DIV12 ((uint32_t)0x00010000) +#define RCC_ADCPRE_DIV16 ((uint32_t)0x00014000) +#define RCC_ADCPRE_DIV24 ((uint32_t)0x00018000) +#define RCC_ADCPRE_DIV32 ((uint32_t)0x00016000) +#define RCC_ADCPRE_DIV48 ((uint32_t)0x0001A000) +#define RCC_ADCPRE_DIV64 ((uint32_t)0x00016100) +#define RCC_ADCPRE_DIV96 ((uint32_t)0x0001A100) +#define RCC_ADCPRE_DIV128 ((uint32_t)0x00017000) +#define RCC_ADCPRE_DIV192 ((uint32_t)0x0001B000) +#define RCC_ADCPRE_DIV256 ((uint32_t)0x00017100) +#define RCC_ADCPRE_DIV384 ((uint32_t)0x0001B100) +#define RCC_ADCPRE_DIV768 ((uint32_t)0x0001F100) + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ + + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_CFGR2 register *******************/ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint32_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint32_t)0x0040) /* CRC clock enable */ +#define RCC_USBPDEN ((uint32_t)0x0080) +#define RCC_USBHD ((uint32_t)0x1000) +#define RCC_USBFS ((uint32_t)0x1000) +#define RCC_USBPD ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_USBPDRSTF ((uint32_t)0x02000000) +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/****************** Bit definition for RCC_AHBRSTR register *****************/ + + + + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CO1NE ((uint16_t)0x0400) /* Only for TIM2 */ +#define TIM_CO2NE ((uint16_t)0x0800) /* Only for TIM2 */ + +#define TIM_CAPOV ((uint16_t)0x4000) +#define TIM_CAPLVL ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +#define TIM_DT1 ((uint16_t)0x0F00) /* Only for TIM2 */ +#define TIM_DT2 ((uint16_t)0xF000) /* Only for TIM2 */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +#define TIM_CO1P ((uint16_t)0x0040)/* Only for TIM2 */ +#define TIM_CO2P ((uint16_t)0x0080)/* Only for TIM2 */ +#define TIM_CO1NP ((uint16_t)0x0100)/* Only for TIM2 */ +#define TIM_CO2NP ((uint16_t)0x0200)/* Only for TIM2 */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/********************* Bit definition for EXTEN_CTLR0 register *****************************/ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + + + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ + + +#define EXTEN_OPA_EN ((uint32_t)0x00010000) +#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) +#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) + + +/********************* Bit definition for EXTEN_CTLR1 register *****************************/ +#define EXTEN_UDP_BUFOE ((uint32_t)0x00000001) + +#define EXTEN_UDP_PCS ((uint32_t)0x00000006) /* UDP_PCS[1:0] bits */ +#define EXTEN_UDP_PCS_0 ((uint32_t)0x00000002) +#define EXTEN_UDP_PCS_1 ((uint32_t)0x00000004) + +#define EXTEN_UDP_PUE ((uint32_t)0x00000008) +#define EXTEN_UDP_PDE ((uint32_t)0x00000010) +#define EXTEN_UDP_DAC ((uint32_t)0x000007E0) +#define EXTEN_UDP_AE ((uint32_t)0x00000800) +#define EXTEN_UDP_AI ((uint32_t)0x00001000) +#define EXTEN_UDM_BUFOE ((uint32_t)0x00010000) + +#define EXTEN_UDM_PCS ((uint32_t)0x00060000) /* UDM_PCS[1:0] bits */ +#define EXTEN_UDM_PCS_0 ((uint32_t)0x00020000) +#define EXTEN_UDM_PCS_1 ((uint32_t)0x00040000) + +#define EXTEN_UDM_PUE ((uint32_t)0x00080000) +#define EXTEN_UDM_PDE ((uint32_t)0x00100000) +#define EXTEN_UDM_DAC ((uint32_t)0x07E00000) +#define EXTEN_UDM_AE ((uint32_t)0x08000000) +#define EXTEN_UDM_AI ((uint32_t)0x10000000) + +/********************* Bit definition for EXTEN_CTLR2 register *****************************/ +#define EXTEN_QII_AE ((uint32_t)0x00000001) +#define EXTEN_QII_PS ((uint32_t)0x00000002) +#define EXTEN_QII_AV ((uint32_t)0x00000004) +#define EXTEN_QII_HYP ((uint32_t)0x00000008) +#define EXTEN_QII_FILT ((uint32_t)0x00000020) + +#define EXTEN_ISP_AE ((uint32_t)0x00000100) +#define EXTEN_ISP_PS ((uint32_t)0x00000200) +#define EXTEN_ISP_BE ((uint32_t)0x00000400) +#define EXTEN_ISP_NS ((uint32_t)0x00001000) + +#define EXTEN_CC1_REF ((uint32_t)0x00010000) +#define EXTEN_CC2_REF ((uint32_t)0x00020000) +#define EXTEN_CC3_REF ((uint32_t)0x00040000) +#define EXTEN_CC_HVT ((uint32_t)0x00080000) +#define EXTEN_IREF_INC ((uint32_t)0x00100000) + + +#ifdef __cplusplus +} +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* ch32v00x_gpio.c -----------------------------------------------------------*/ +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + + +/* ch32v00x_adc.c ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +///* CTLR1 register Mask */ +//Editor's Note: Overloaded Definition +#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + + + + +/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/* ch32v00x_dma.c ------------------------------------------------------------*/ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + + +/* DMA2 FLAG mask */ +// Editor's note: Overloaded Definition. +#define DMA2_FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/* ch32v00x_exti.c -----------------------------------------------------------*/ + + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/* ch32v00x_flash.c ----------------------------------------------------------*/ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) + + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + + +/* ch32v00x_i2c.c ------------------------------------------------------------*/ + + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +////* I2C registers Masks */ +// Editor's note: Overloaded Definition. +#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +//Editor's Note: Overloaded Definition +#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* ch32v00x_iwdg.c -----------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + + +/* ch32v00x_pwr.c ------------------------------------------------------------*/ + + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/* ch32v00x_rcc.c ------------------------------------------------------------*/ + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + + +/* RCC Flag Mask */ +//Editor's Note: Overloaded Definition +#define RCC_FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +#ifndef __ASSEMBLER__ +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; +static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; +#endif + + + +/* ch32v00x_spi.c ------------------------------------------------------------*/ + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +//Editor's Note: Overloaded Definition +#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + + + +/* ch32v00x_tim.c ------------------------------------------------------------*/ + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/* ch32v00x_usart.c ----------------------------------------------------------*/ + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +//Editor's Note: Overloaded Definition +#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/* ch32v00x_wwdg.c ------------------------------------------------------------*/ + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + + +/* ch32v00x_adc.h ------------------------------------------------------------*/ + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ + +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_PA4_PA15 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) + +#define ADC_Channel_VHV ((uint8_t)ADC_Channel_15) + + +/* ADC_sampling_time */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_9Cycles ((uint8_t)0x01) +#define ADC_SampleTime_15Cycles ((uint8_t)0x02) +#define ADC_SampleTime_30Cycles ((uint8_t)0x03) +#define ADC_SampleTime_43Cycles ((uint8_t)0x04) +#define ADC_SampleTime_57Cycles ((uint8_t)0x05) +#define ADC_SampleTime_73Cycles ((uint8_t)0x06) +#define ADC_SampleTime_241Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC1 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T1_CC2 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_PA4_PA15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_calibration_voltage_definition */ +#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) +#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) + +/* ADC_external_trigger_sources_delay_channels_definition */ +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200) + + + + +/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ + +/* DBGMCU_CR Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) + +/* ch32v00x_dma.h ------------------------------------------------------------*/ + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + + + + +/* ch32v00x_exti.h -----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#endif + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ + +#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 Connected to the PWR Auto Wake-up event*/ +#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 Connected to the PVD Wake-up event */ + +/* ch32v00x_flash.h ----------------------------------------------------------*/ + + +#ifndef __ASSEMBLER__ +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; +#endif + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + + +/* Values to be used with CH32V00x devices (1page = 64Byte) */ +#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ +#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ +#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ +#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ +#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ +#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ +#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ +#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ +#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ +#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ +#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ +#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ +#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ +#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ +#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ +#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ + + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */ +#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */ + + +/* Option_Bytes_Power_ON_Start_Mode */ +#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */ +#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */ + +#define OB_STARTMODE_BOOT ((uint16_t)0x0020) /* Start in BOOT area */ +#define OB_STARTMODE_USER ((uint16_t)0x0000) /* Start in user area */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/* ch32v00x_gpio.h ------------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_In = 0, + GPIO_Speed_10MHz, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +#endif + +#define GPIO_CNF_IN_ANALOG 0 +#define GPIO_CNF_IN_FLOATING 4 +#define GPIO_CNF_IN_PUPD 8 +#define GPIO_CNF_OUT_PP 0 +#define GPIO_CNF_OUT_OD 4 +#define GPIO_CNF_OUT_PP_AF 8 +#define GPIO_CNF_OUT_OD_AF 12 + +/* Configuration Mode enumeration */ +/* +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; +*/ + +#ifndef __ASSEMBLER__ + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#endif + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ + +#if defined(GPIO_Pin_23) +#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ +#else +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ +#endif + +/* GPIO_Remap_define */ + +#define GPIO_PartialRemap_I2C1 ((uint32_t)0x00100001) /* I2C1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x00100002) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80300004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80300008) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART1 ((uint32_t)0x8030000C) /* USART1 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x80300010) /* USART1 Full Alternate Function mapping */ +#define GPIO_Remap_TIM1 ((uint32_t)0x00000040) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ +#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* ch32v00x_i2c.h ------------------------------------------------------------*/ + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +/* ch32v00x_iwdg.h -----------------------------------------------------------*/ + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +/* ch32v00x_misc.h -----------------------------------------------------------*/ + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + +/* ch32v00x_opa.h ------------------------------------------------------------*/ + +/* Editor's note: I don't know if this is actually useful */ +#ifndef __ASSEMBLER__ + + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; + + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ +} OPA_InitTypeDef; + + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#endif + +/* ch32v00x_pwr.h ------------------------------------------------------------*/ + + +/* PVD_detection_level */ + +#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) +#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) +#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) + +/* PWR_AWU_Prescaler */ +#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) +#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) +#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) +#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) +#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) +#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) +#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) +#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) +#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) +#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) + +/* STOP_mode_entry */ +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + + +/* ch32v00x_rcc.h ------------------------------------------------------------*/ + + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) + + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_PCLK2_Div12 ((uint32_t)0x00010000) +#define RCC_PCLK2_Div16 ((uint32_t)0x00014000) +#define RCC_PCLK2_Div24 ((uint32_t)0x00018000) +#define RCC_PCLK2_Div32 ((uint32_t)0x00016000) +#define RCC_PCLK2_Div48 ((uint32_t)0x0001A000) +#define RCC_PCLK2_Div64 ((uint32_t)0x00016100) +#define RCC_PCLK2_Div96 ((uint32_t)0x0001A100) +#define RCC_PCLK2_Div128 ((uint32_t)0x00017000) +#define RCC_PCLK2_Div192 ((uint32_t)0x0001B000) +#define RCC_PCLK2_Div256 ((uint32_t)0x00017100) +#define RCC_PCLK2_Div384 ((uint32_t)0x0001B100) +#define RCC_PCLK2_Div768 ((uint32_t)0x0001F100) + + + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USBPD ((uint32_t)0x00000080) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + + + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_USBPDRSTF ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + + + + + + + +/* ch32v00x_spi.h ------------------------------------------------------------*/ + + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) /* Sets MSTR, as well as SSI, which is required for Master Mode */ +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) + + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +/* ch32v00x_tim.h ------------------------------------------------------------*/ + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +/* ch32v00x_usart.h ----------------------------------------------------------*/ + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +// While not truly CH32X035, we can re-use some of the USB register defs. + +/* ch32v30x_usb.h ------------------------------------------------------------*/ + + +/* ch641_usbpd.h ------------------------------------------------------------*/ +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_ALL_SEL (3<<2) /* Select PD communication port ALL*/ +#define CC_SEL_Mask (3<<2) /* Clear PD communication port */ +#define CC_SEL_1 (0<<2) /* Select PD communication port1 */ +#define CC_SEL_2 (1<<2) /* Select PD communication port2 */ +#define CC_SEL_3 (2<<2) /* Select PD communication port3 */ +#define PD_DMA_EN (1<<4) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<5) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<6) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +/* USBPD->PORT_CC3 */ +#define CC_CMPO (1<<0) /* CC port comparator analog input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CVS_Mask (3<<5) /* clear CC_CVS*/ +#define CC_CVS_55 (0<<5) /* 00-0.55V */ +#define CC_CVS_22 (1<<5) /* 01-0.22V */ +#define CC_CVS_66 (2<<5) /* 10-0.66V */ +#define CC_CVS_123 (3<<5) /* 11-1.23V */ +#define CC_CE (1<<7) /* Enable the voltage comparator on port CC */ + +/********************************************************* + * PD pin PB0/PB1/PB9 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_HVT (1<<19) + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define PIN_CC1 GPIO_Pin_0 +#define PIN_CC2 GPIO_Pin_1 +#define PIN_CC3 GPIO_Pin_9 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ + +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + +/* ch32v00x_wwdg.h -----------------------------------------------------------*/ + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +#ifdef __cplusplus +}; +#endif + + +// For debug writing to the debug interface. +#ifndef MINICHLINK + #define DMDATA0 ((volatile uint32_t*)0xe00000f4) + #define DMDATA1 ((volatile uint32_t*)0xe00000f8) + #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe00000fc) // Reads as 0x00000000 if debugger is attached. +#endif + +// Determination of PLL multiplication factor for non-V003 chips + + + +// xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering. + +/* +Encoder for some of the proprietary 'XW' RISC-V instructions present on the QingKe RV32 processor. +Examples: + XW_C_LBU(a3, a1, 27); // c.xw.lbu a3, 27(a1) + XW_C_SB(a0, s0, 13); // c.xw.sb a0, 13(s0) + + XW_C_LHU(a5, a5, 38); // c.xw.lhu a5, 38(a5) + XW_C_SH(a2, s1, 14); // c.xw.sh a2, 14(s1) +*/ + +// Let us do some compile-time error checking. +#define ASM_ASSERT(COND) .if (!(COND)); .err; .endif + +// Integer encodings of the possible compressed registers. +#define C_s0 0 +#define C_s1 1 +#define C_a0 2 +#define C_a1 3 +#define C_a2 4 +#define C_a3 5 +#define C_a4 6 +#define C_a5 7 + +// register to encoding +#define REG2I(X) (C_ ## X) + +// XW opcodes +#define XW_OP_LBUSP 0b1000000000000000 +#define XW_OP_STSP 0b1000000001000000 + +#define XW_OP_LHUSP 0b1000000000100000 +#define XW_OP_SHSP 0b1000000001100000 + +#define XW_OP_LBU 0b0010000000000000 +#define XW_OP_SB 0b1010000000000000 + +#define XW_OP_LHU 0b0010000000000010 +#define XW_OP_SH 0b1010000000000010 + +// The two different XW encodings supported at the moment. +#define XW_ENCODE1(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ + (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3))) + +#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ + (((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2)) + +// Compressed load byte, zero-extend result +#define XW_C_LBU(RD, RS, IMM) XW_ENCODE1(XW_OP_LBU, RD, RS, IMM) + +// Compressed store byte +#define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM) + +// Compressed load half, zero-extend result +#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1))) + +// Compressed store half +#define XW_C_SH(RS1, RS2, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1))) + + + +// Applies to all processors + + +/* some bit definitions for systick regs */ +#define SYSTICK_SR_CNTIF (1<<0) +#define SYSTICK_CTLR_STE (1<<0) +#define SYSTICK_CTLR_STIE (1<<1) +#define SYSTICK_CTLR_STCLK (1<<2) +#define SYSTICK_CTLR_STRE (1<<3) +#define SYSTICK_CTLR_SWIE (1<<31) + +#define PFIC ((PFIC_Type *) PFIC_BASE ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + + +#define SysTick ((SysTick_Type *) SysTick_BASE) + + +#define PA1 1 +#define PA2 2 +#define PC0 32 +#define PC1 33 +#define PC2 34 +#define PC3 35 +#define PC4 36 +#define PC5 37 +#define PC6 38 +#define PC7 39 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 + +/* + * This file contains various parts of the official WCH EVT Headers which + * were originally under a restrictive license. + * + * The collection of this file was generated by + * cnlohr, 2023-02-18 and + * AlexanderMandera, 2023-06-23 + * It was significantly reworked into several files cnlohr, 2025-01-29 + * + * While originally under a restrictive copyright, WCH has approved use + * under MIT-licensed use, because of inclusion in Zephyr, as well as other + * open-source licensed projects. + * + * These copies of the headers from WCH are available now under: + * + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the “Softwareâ€), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#endif // Header guard diff --git a/inc/extralibs/ch32v003_GPIO_branchless.h b/inc/extralibs/ch32v003_GPIO_branchless.h index 5504f0d..f809f0a 100644 --- a/inc/extralibs/ch32v003_GPIO_branchless.h +++ b/inc/extralibs/ch32v003_GPIO_branchless.h @@ -1,22 +1,26 @@ // 2023-06-26 recallmenot -// ######## necessities +//######## necessities // include guards #ifndef CH32V003_GPIO_BR_H #define CH32V003_GPIO_BR_H // includes +#include //uintN_t support #include "../ch32fun/ch32fun.h" -#include //uintN_t support + + /*######## library description This is a speedy and light GPIO library due to - static inlining of most functions - compile-time abstraction - branchless where it counts + static inlining of most functions + compile-time abstraction + branchless where it counts */ + + /*######## library usage and configuration first, enable the desired port. @@ -94,81 +98,78 @@ Writing `TIMx->SWEVGR |= TIM_UG` will immediately update the shadow register and */ -// ######## ports, pins and states: use these for the functions below! -#define GPIOv_from_PORT_PIN(GPIO_port_n, pin) -enum GPIO_port_n -{ - GPIO_port_A = 0b00, - GPIO_port_C = 0b10, - GPIO_port_D = 0b11, +//######## ports, pins and states: use these for the functions below! + +#define GPIOv_from_PORT_PIN( GPIO_port_n, pin ) + +enum GPIO_port_n { + GPIO_port_A = 0b00, + GPIO_port_C = 0b10, + GPIO_port_D = 0b11, }; -enum GPIO_pinModes -{ - GPIO_pinMode_I_floating, - GPIO_pinMode_I_pullUp, - GPIO_pinMode_I_pullDown, - GPIO_pinMode_I_analog, - GPIO_pinMode_O_pushPull, - GPIO_pinMode_O_openDrain, - GPIO_pinMode_O_pushPullMux, - GPIO_pinMode_O_openDrainMux, +enum GPIO_pinModes { + GPIO_pinMode_I_floating, + GPIO_pinMode_I_pullUp, + GPIO_pinMode_I_pullDown, + GPIO_pinMode_I_analog, + GPIO_pinMode_O_pushPull, + GPIO_pinMode_O_openDrain, + GPIO_pinMode_O_pushPullMux, + GPIO_pinMode_O_openDrainMux, }; -enum lowhigh -{ - low, - high, +enum lowhigh { + low, + high, }; // analog inputs -enum GPIO_analog_inputs -{ - GPIO_Ain0_A2, - GPIO_Ain1_A1, - GPIO_Ain2_C4, - GPIO_Ain3_D2, - GPIO_Ain4_D3, - GPIO_Ain5_D5, - GPIO_Ain6_D6, - GPIO_Ain7_D4, - GPIO_AinVref, - GPIO_AinVcal, +enum GPIO_analog_inputs { + GPIO_Ain0_A2, + GPIO_Ain1_A1, + GPIO_Ain2_C4, + GPIO_Ain3_D2, + GPIO_Ain4_D3, + GPIO_Ain5_D5, + GPIO_Ain6_D6, + GPIO_Ain7_D4, + GPIO_AinVref, + GPIO_AinVcal, }; // how many cycles the ADC shall sample the input for (speed vs precision) -enum GPIO_ADC_sampletimes -{ - GPIO_ADC_sampletime_3cy, - GPIO_ADC_sampletime_9cy, - GPIO_ADC_sampletime_15cy, - GPIO_ADC_sampletime_30cy, - GPIO_ADC_sampletime_43cy, - GPIO_ADC_sampletime_57cy, - GPIO_ADC_sampletime_73cy, - GPIO_ADC_sampletime_241cy_default, +enum GPIO_ADC_sampletimes { + GPIO_ADC_sampletime_3cy, + GPIO_ADC_sampletime_9cy, + GPIO_ADC_sampletime_15cy, + GPIO_ADC_sampletime_30cy, + GPIO_ADC_sampletime_43cy, + GPIO_ADC_sampletime_57cy, + GPIO_ADC_sampletime_73cy, + GPIO_ADC_sampletime_241cy_default, }; -enum GPIO_tim1_output_sets -{ - GPIO_tim1_output_set_0__D2_A1_C3_C4__D0_A2_D1, - GPIO_tim1_output_set_1__C6_C7_C0_D3__C3_C4_D1, - GPIO_tim1_output_set_2__D2_A1_C3_C4__D0_A2_D1, - GPIO_tim1_output_set_3__C4_C7_C5_D4__C3_D2_C6, +enum GPIO_tim1_output_sets { + GPIO_tim1_output_set_0__D2_A1_C3_C4__D0_A2_D1, + GPIO_tim1_output_set_1__C6_C7_C0_D3__C3_C4_D1, + GPIO_tim1_output_set_2__D2_A1_C3_C4__D0_A2_D1, + GPIO_tim1_output_set_3__C4_C7_C5_D4__C3_D2_C6, }; -enum GPIO_tim2_output_sets -{ - GPIO_tim2_output_set_0__D4_D3_C0_D7, - GPIO_tim2_output_set_1__C5_C2_D2_C1, - GPIO_tim2_output_set_2__C1_D3_C0_D7, - GPIO_tim2_output_set_3__C1_C7_D6_D5, +enum GPIO_tim2_output_sets { + GPIO_tim2_output_set_0__D4_D3_C0_D7, + GPIO_tim2_output_set_1__C5_C2_D2_C1, + GPIO_tim2_output_set_2__C1_D3_C0_D7, + GPIO_tim2_output_set_3__C1_C7_D6_D5, }; -// ######## interface function overview: use these! -// most functions have been reduced to function-like macros, actual definitions downstairs + + +//######## interface function overview: use these! +// most functions have been reduced to function-like macros, actual definitions downstairs // setup #define GPIO_port_enable(GPIO_port_n) @@ -201,66 +202,72 @@ static inline void GPIO_tim2_init(); #define GPIO_tim1_analogWrite(channel, value) #define GPIO_tim2_analogWrite(channel, value) -// ######## internal function declarations -// ######## internal variables -// ######## preprocessor macros +//######## internal function declarations -#define CONCAT(a, b) a##b + + +//######## internal variables + + + +//######## preprocessor macros + +#define CONCAT(a, b) a ## b #define CONCAT_INDIRECT(a, b) CONCAT(a, b) #undef GPIOv_from_PORT_PIN -#define GPIOv_from_PORT_PIN(GPIO_port_n, pin) ((GPIO_port_n << 4) | (pin)) -#define GPIOv_to_PORT(GPIOv) (GPIOv >> 4) -#define GPIOv_to_PIN(GPIOv) (GPIOv & 0b1111) -#define GPIOv_to_GPIObase(GPIOv) ((GPIO_TypeDef *)(uintptr_t)((GPIOA_BASE + (0x400 * (GPIOv >> 4))))) +#define GPIOv_from_PORT_PIN( GPIO_port_n, pin ) ((GPIO_port_n << 4 ) | (pin)) +#define GPIOv_to_PORT( GPIOv ) (GPIOv >> 4 ) +#define GPIOv_to_PIN( GPIOv ) (GPIOv & 0b1111) +#define GPIOv_to_GPIObase( GPIOv ) ((GPIO_TypeDef*)(uintptr_t)((GPIOA_BASE + (0x400 * (GPIOv >> 4))))) -#define GPIOx_to_port_n2(GPIOx) GPIOx_to_port_n_##GPIOx -#define GPIOx_to_port_n(GPIOx) GPIOx_to_port_n2(GPIOx) -#define GPIOx_to_port_n_GPIO_port_A 0b00 -#define GPIOx_to_port_n_GPIO_port_C 0b10 -#define GPIOx_to_port_n_GPIO_port_D 0b11 +#define GPIOx_to_port_n2(GPIOx) GPIOx_to_port_n_##GPIOx +#define GPIOx_to_port_n(GPIOx) GPIOx_to_port_n2(GPIOx) +#define GPIOx_to_port_n_GPIO_port_A 0b00 +#define GPIOx_to_port_n_GPIO_port_C 0b10 +#define GPIOx_to_port_n_GPIO_port_D 0b11 -#define GPIO_port_n_to_GPIOx2(GPIO_port_n) GPIO_port_n_to_GPIOx_##GPIO_port_n -#define GPIO_port_n_to_GPIOx(GPIO_port_n) GPIO_port_n_to_GPIOx2(GPIO_port_n) -#define GPIO_port_n_to_GPIOx_GPIO_port_A GPIOA -#define GPIO_port_n_to_GPIOx_GPIO_port_C GPIOC -#define GPIO_port_n_to_GPIOx_GPIO_port_D GPIOD +#define GPIO_port_n_to_GPIOx2(GPIO_port_n) GPIO_port_n_to_GPIOx_##GPIO_port_n +#define GPIO_port_n_to_GPIOx(GPIO_port_n) GPIO_port_n_to_GPIOx2(GPIO_port_n) +#define GPIO_port_n_to_GPIOx_GPIO_port_A GPIOA +#define GPIO_port_n_to_GPIOx_GPIO_port_C GPIOC +#define GPIO_port_n_to_GPIOx_GPIO_port_D GPIOD -#define GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph_##GPIO_port_n -#define GPIO_port_n_to_RCC_APB2Periph(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) -#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_A RCC_APB2Periph_GPIOA -#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_C RCC_APB2Periph_GPIOC -#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_D RCC_APB2Periph_GPIOD +#define GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph_##GPIO_port_n +#define GPIO_port_n_to_RCC_APB2Periph(GPIO_port_n) GPIO_port_n_to_RCC_APB2Periph2(GPIO_port_n) +#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_A RCC_APB2Periph_GPIOA +#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_C RCC_APB2Periph_GPIOC +#define GPIO_port_n_to_RCC_APB2Periph_GPIO_port_D RCC_APB2Periph_GPIOD -#define GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG_##GPIO_pinMode(GPIO_Speed) -#define GPIO_pinMode_to_CFG(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_floating(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_FLOATING) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullUp(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullDown(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_analog(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_ANALOG) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPull(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrain(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_OD) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPullMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP_AF) -#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrainMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_IN_ANALOG) +#define GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG_##GPIO_pinMode(GPIO_Speed) +#define GPIO_pinMode_to_CFG(GPIO_pinMode, GPIO_Speed) GPIO_pinMode_to_CFG2(GPIO_pinMode, GPIO_Speed) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_floating(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_FLOATING) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullUp(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_pullDown(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_PUPD) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_I_analog(GPIO_Speed) (GPIO_Speed_In | GPIO_CNF_IN_ANALOG) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPull(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrain(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_OD) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_pushPullMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_OUT_PP_AF) +#define GPIO_pinMode_to_CFG_GPIO_pinMode_O_openDrainMux(GPIO_Speed) (GPIO_Speed | GPIO_CNF_IN_ANALOG) -#define GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD_##GPIO_pinMode(GPIOv) -#define GPIO_pinMode_set_PUPD(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) +#define GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD_##GPIO_pinMode(GPIOv) +#define GPIO_pinMode_set_PUPD(GPIO_pinMode, GPIOv) GPIO_pinMode_set_PUPD2(GPIO_pinMode, GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_floating(GPIOv) -#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) -#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (GPIOv_to_PIN(GPIOv) + 16)) +#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) +#define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (GPIOv_to_PIN(GPIOv) + 16)) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_I_analog(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_pushPull(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_openDrain(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_pushPullMux(GPIOv) #define GPIO_pinMode_set_PUPD_GPIO_pinMode_O_openDrainMux(GPIOv) -#define GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD_##GPIO_pinMode(GPIO_port_n) -#define GPIO_port_pinMode_set_PUPD(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) +#define GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD_##GPIO_pinMode(GPIO_port_n) +#define GPIO_port_pinMode_set_PUPD(GPIO_pinMode, GPIO_port_n) GPIO_port_pinMode_set_PUPD2(GPIO_pinMode, GPIO_port_n) #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_floating(GPIO_port_n) -#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b11111111 -#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b00000000 +#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullUp(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b11111111 +#define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_pullDown(GPIO_port_n) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = 0b00000000 #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_I_analog(GPIO_port_n) #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_O_pushPull(GPIO_port_n) #define GPIO_port_pinMode_set_PUPD_GPIO_pinMode_O_openDrain(GPIO_port_n) @@ -280,74 +287,91 @@ static inline void GPIO_tim2_init(); #endif #if !defined(GPIO_timer_prescaler) -#define GPIO_timer_prescaler TIM_CKD_DIV2 // APB_CLOCK / 1024 / 2 = 23.4kHz +#define GPIO_timer_prescaler TIM_CKD_DIV2 // APB_CLOCK / 1024 / 2 = 23.4kHz #endif -// ######## define requirements / maintenance defines +//######## define requirements / maintenance defines + + + +//######## small function definitions, static inline -// ######## small function definitions, static inline #undef GPIO_port_enable #define GPIO_port_enable(GPIO_port_n) RCC->APB2PCENR |= GPIO_port_n_to_RCC_APB2Periph(GPIO_port_n); -#define GPIO_port_pinMode(GPIO_port_n, pinMode, GPIO_Speed) ({ \ - GPIO_port_n_to_GPIOx(GPIO_port_n)->CFGLR = (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 0)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 1)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 2)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 3)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 4)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 5)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 6)) | \ - (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 7)); \ - GPIO_port_pinMode_set_PUPD(pinMode, GPIO_port_n); \ +#define GPIO_port_pinMode(GPIO_port_n, pinMode, GPIO_Speed) ({ \ + GPIO_port_n_to_GPIOx(GPIO_port_n)->CFGLR = (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 0)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 1)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 2)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 3)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 4)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 5)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 6)) | \ + (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * 7)); \ + GPIO_port_pinMode_set_PUPD(pinMode, GPIO_port_n); \ }) #undef GPIO_port_digitalWrite -#define GPIO_port_digitalWrite(GPIO_port_n, byte) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = byte +#define GPIO_port_digitalWrite(GPIO_port_n, byte) GPIO_port_n_to_GPIOx(GPIO_port_n)->OUTDR = byte #undef GPIO_port_digitalRead -#define GPIO_port_digitalRead(GPIO_port_n) (GPIO_port_n_to_GPIOx(GPIO_port_n)->INDR & 0b11111111) +#define GPIO_port_digitalRead(GPIO_port_n) (GPIO_port_n_to_GPIOx(GPIO_port_n)->INDR & 0b11111111) #undef GPIO_pinMode -#define GPIO_pinMode(GPIOv, pinMode, GPIO_Speed) ({ \ - GPIOv_to_GPIObase(GPIOv)->CFGLR &= ~(0b1111 << (4 * GPIOv_to_PIN(GPIOv))); \ - GPIOv_to_GPIObase(GPIOv)->CFGLR |= (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * GPIOv_to_PIN(GPIOv))); \ - GPIO_pinMode_set_PUPD(pinMode, GPIOv); \ +#define GPIO_pinMode(GPIOv, pinMode, GPIO_Speed) ({ \ + GPIOv_to_GPIObase(GPIOv)->CFGLR &= ~(0b1111 << (4 * GPIOv_to_PIN(GPIOv))); \ + GPIOv_to_GPIObase(GPIOv)->CFGLR |= (GPIO_pinMode_to_CFG(pinMode, GPIO_Speed) << (4 * GPIOv_to_PIN(GPIOv))); \ + GPIO_pinMode_set_PUPD(pinMode, GPIOv); \ }) #undef GPIO_digitalWrite_hi -#define GPIO_digitalWrite_hi(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) +#define GPIO_digitalWrite_hi(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << GPIOv_to_PIN(GPIOv)) #undef GPIO_digitalWrite_lo -#define GPIO_digitalWrite_lo(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (16 + GPIOv_to_PIN(GPIOv))) +#define GPIO_digitalWrite_lo(GPIOv) GPIOv_to_GPIObase(GPIOv)->BSHR = (1 << (16 + GPIOv_to_PIN(GPIOv))) #undef GPIO_digitalWrite -#define GPIO_digitalWrite(GPIOv, lowhigh) GPIO_digitalWrite_##lowhigh(GPIOv) -#define GPIO_digitalWrite_low(GPIOv) GPIO_digitalWrite_lo(GPIOv) -#define GPIO_digitalWrite_0(GPIOv) GPIO_digitalWrite_lo(GPIOv) -#define GPIO_digitalWrite_high(GPIOv) GPIO_digitalWrite_hi(GPIOv) -#define GPIO_digitalWrite_1(GPIOv) GPIO_digitalWrite_hi(GPIOv) +#define GPIO_digitalWrite(GPIOv, lowhigh) GPIO_digitalWrite_##lowhigh(GPIOv) +#define GPIO_digitalWrite_low(GPIOv) GPIO_digitalWrite_lo(GPIOv) +#define GPIO_digitalWrite_0(GPIOv) GPIO_digitalWrite_lo(GPIOv) +#define GPIO_digitalWrite_high(GPIOv) GPIO_digitalWrite_hi(GPIOv) +#define GPIO_digitalWrite_1(GPIOv) GPIO_digitalWrite_hi(GPIOv) #undef GPIO_digitalWrite_branching -#define GPIO_digitalWrite_branching(GPIOv, lowhigh) (lowhigh ? GPIO_digitalWrite_hi(GPIOv) : GPIO_digitalWrite_lo(GPIOv)) +#define GPIO_digitalWrite_branching(GPIOv, lowhigh) (lowhigh ? (GPIO_digitalWrite_hi(GPIOv)) : (GPIO_digitalWrite_lo(GPIOv))) #undef GPIO_digitalRead -#define GPIO_digitalRead(GPIOv) ((GPIOv_to_GPIObase(GPIOv)->INDR >> GPIOv_to_PIN(GPIOv)) & 0b1) +#define GPIO_digitalRead(GPIOv) ((GPIOv_to_GPIObase(GPIOv)->INDR >> GPIOv_to_PIN(GPIOv)) & 0b1) #undef GPIO_ADC_set_sampletime // 0:7 => 3/9/15/30/43/57/73/241 cycles -#define GPIO_ADC_set_sampletime(GPIO_analog_input, GPIO_ADC_sampletime) ({ \ - ADC1->SAMPTR2 &= ~(0b111) << (3 * GPIO_analog_input); \ - ADC1->SAMPTR2 |= GPIO_ADC_sampletime << (3 * GPIO_analog_input); \ +#define GPIO_ADC_set_sampletime(GPIO_analog_input, GPIO_ADC_sampletime) ({ \ + ADC1->SAMPTR2 &= ~(0b111) << (3 * GPIO_analog_input); \ + ADC1->SAMPTR2 |= GPIO_ADC_sampletime << (3 * GPIO_analog_input); \ }) #undef GPIO_ADC_set_sampletimes_all -#define GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime) ({ \ - ADC1->SAMPTR2 &= 0; \ - ADC1->SAMPTR2 |= \ - GPIO_ADC_sampletime << (0 * 3) | GPIO_ADC_sampletime << (1 * 3) | GPIO_ADC_sampletime << (2 * 3) | GPIO_ADC_sampletime << (3 * 3) | GPIO_ADC_sampletime << (4 * 3) | GPIO_ADC_sampletime << (5 * 3) | GPIO_ADC_sampletime << (6 * 3) | GPIO_ADC_sampletime << (7 * 3) | GPIO_ADC_sampletime << (8 * 3) | GPIO_ADC_sampletime << (9 * 3); \ - ADC1->SAMPTR1 &= 0; \ - ADC1->SAMPTR1 |= \ - GPIO_ADC_sampletime << (0 * 3) | GPIO_ADC_sampletime << (1 * 3) | GPIO_ADC_sampletime << (2 * 3) | GPIO_ADC_sampletime << (3 * 3) | GPIO_ADC_sampletime << (4 * 3) | GPIO_ADC_sampletime << (5 * 3); \ +#define GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime) ({ \ + ADC1->SAMPTR2 &= 0; \ + ADC1->SAMPTR2 |= \ + GPIO_ADC_sampletime << (0 * 3) \ + | GPIO_ADC_sampletime << (1 * 3) \ + | GPIO_ADC_sampletime << (2 * 3) \ + | GPIO_ADC_sampletime << (3 * 3) \ + | GPIO_ADC_sampletime << (4 * 3) \ + | GPIO_ADC_sampletime << (5 * 3) \ + | GPIO_ADC_sampletime << (6 * 3) \ + | GPIO_ADC_sampletime << (7 * 3) \ + | GPIO_ADC_sampletime << (8 * 3) \ + | GPIO_ADC_sampletime << (9 * 3); \ + ADC1->SAMPTR1 &= 0; \ + ADC1->SAMPTR1 |= \ + GPIO_ADC_sampletime << (0 * 3) \ + | GPIO_ADC_sampletime << (1 * 3) \ + | GPIO_ADC_sampletime << (2 * 3) \ + | GPIO_ADC_sampletime << (3 * 3) \ + | GPIO_ADC_sampletime << (4 * 3) \ + | GPIO_ADC_sampletime << (5 * 3); \ }) #undef GPIO_ADC_set_power @@ -357,137 +381,133 @@ static inline void GPIO_tim2_init(); #define GPIO_ADC_set_power_0 ADC1->CTLR2 &= ~(ADC_ADON) #undef GPIO_ADC_calibrate -#define GPIO_ADC_calibrate() ({ \ - ADC1->CTLR2 |= ADC_RSTCAL; \ - while (ADC1->CTLR2 & ADC_RSTCAL) \ - ; \ - ADC1->CTLR2 |= ADC_CAL; \ - while (ADC1->CTLR2 & ADC_CAL) \ - ; \ +#define GPIO_ADC_calibrate() ({ \ + ADC1->CTLR2 |= ADC_RSTCAL; \ + while(ADC1->CTLR2 & ADC_RSTCAL); \ + ADC1->CTLR2 |= ADC_CAL; \ + while(ADC1->CTLR2 & ADC_CAL); \ }) // large but will likely only ever be called once -static inline void GPIO_ADCinit() -{ - // select ADC clock source - // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide by 2 - RCC->CFGR0 &= ~(0x1F << 11); +static inline void GPIO_ADCinit() { + // select ADC clock source + // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide by 2 + RCC->CFGR0 &= ~(0x1F<<11); - // enable clock to the ADC - RCC->APB2PCENR |= RCC_APB2Periph_ADC1; + // enable clock to the ADC + RCC->APB2PCENR |= RCC_APB2Periph_ADC1; - // Reset the ADC to init all regs - RCC->APB2PRSTR |= RCC_APB2Periph_ADC1; - RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1; + // Reset the ADC to init all regs + RCC->APB2PRSTR |= RCC_APB2Periph_ADC1; + RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1; - // set sampling time for all inputs to 241 cycles - GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime); + // set sampling time for all inputs to 241 cycles + GPIO_ADC_set_sampletimes_all(GPIO_ADC_sampletime); - // set trigger to software - ADC1->CTLR2 |= ADC_EXTSEL; + // set trigger to software + ADC1->CTLR2 |= ADC_EXTSEL; - // pre-clear conversion queue - ADC1->RSQR1 = 0; - ADC1->RSQR2 = 0; - ADC1->RSQR3 = 0; + // pre-clear conversion queue + ADC1->RSQR1 = 0; + ADC1->RSQR2 = 0; + ADC1->RSQR3 = 0; - // power the ADC - GPIO_ADC_set_power(1); - GPIO_ADC_calibrate(); + // power the ADC + GPIO_ADC_set_power(1); + GPIO_ADC_calibrate(); } -static inline uint16_t GPIO_analogRead(enum GPIO_analog_inputs input) -{ - // set mux to selected input - ADC1->RSQR3 = input; - // allow everything to precharge - Delay_Us(GPIO_ADC_MUX_DELAY); - // start sw conversion (auto clears) - ADC1->CTLR2 |= ADC_SWSTART; - // wait for conversion complete - while (!(ADC1->STATR & ADC_EOC)) {} - // get result - return ADC1->RDATAR; +static inline uint16_t GPIO_analogRead(enum GPIO_analog_inputs input) { + // set mux to selected input + ADC1->RSQR3 = input; + // allow everything to precharge + Delay_Us(GPIO_ADC_MUX_DELAY); + // start sw conversion (auto clears) + ADC1->CTLR2 |= ADC_SWSTART; + // wait for conversion complete + while(!(ADC1->STATR & ADC_EOC)) {} + // get result + return ADC1->RDATAR; } + + #undef GPIO_tim1_map -#define GPIO_tim1_map(GPIO_tim1_output_set) ({ \ - RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ - AFIO->PCFR1 |= ((GPIO_tim1_output_set & 0b11) << 6); \ +#define GPIO_tim1_map(GPIO_tim1_output_set) ({ \ + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ + AFIO->PCFR1 |= ((GPIO_tim1_output_set & 0b11) << 6); \ }) #undef GPIO_tim2_map -#define GPIO_tim2_map(GPIO_tim2_output_set) ({ \ - RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ - AFIO->PCFR1 |= ((GPIO_tim2_output_set & 0b11) << 8); \ +#define GPIO_tim2_map(GPIO_tim2_output_set) ({ \ + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; \ + AFIO->PCFR1 |= ((GPIO_tim2_output_set & 0b11) << 8); \ }) -static inline void GPIO_tim1_init() -{ - // enable TIM1 - RCC->APB2PCENR |= RCC_APB2Periph_TIM1; - // reset TIM1 to init all regs - RCC->APB2PRSTR |= RCC_APB2Periph_TIM1; - RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1; - // SMCFGR: default clk input is CK_INT - // set clock prescaler divider - TIM1->PSC = GPIO_timer_prescaler; - // set PWM total cycle width - TIM1->ATRLR = GPIO_timer_resolution; - // CTLR1: default is up, events generated, edge align - // enable auto-reload of preload - TIM1->CTLR1 |= TIM_ARPE; - // initialize counter - TIM1->SWEVGR |= TIM_UG; - // disengage brake - TIM1->BDTR |= TIM_MOE; - // Enable TIM1 - TIM1->CTLR1 |= TIM_CEN; +static inline void GPIO_tim1_init() { + // enable TIM1 + RCC->APB2PCENR |= RCC_APB2Periph_TIM1; + // reset TIM1 to init all regs + RCC->APB2PRSTR |= RCC_APB2Periph_TIM1; + RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1; + // SMCFGR: default clk input is CK_INT + // set clock prescaler divider + TIM1->PSC = GPIO_timer_prescaler; + // set PWM total cycle width + TIM1->ATRLR = GPIO_timer_resolution; + // CTLR1: default is up, events generated, edge align + // enable auto-reload of preload + TIM1->CTLR1 |= TIM_ARPE; + // initialize counter + TIM1->SWEVGR |= TIM_UG; + // disengage brake + TIM1->BDTR |= TIM_MOE; + // Enable TIM1 + TIM1->CTLR1 |= TIM_CEN; } -static inline void GPIO_tim2_init() -{ - // enable TIM2 - RCC->APB1PCENR |= RCC_APB1Periph_TIM2; - // reset TIM2 to init all regs - RCC->APB1PRSTR |= RCC_APB1Periph_TIM2; - RCC->APB1PRSTR &= ~RCC_APB1Periph_TIM2; - // SMCFGR: default clk input is CK_INT - // set clock prescaler divider - TIM2->PSC = GPIO_timer_prescaler; - // set PWM total cycle width - TIM2->ATRLR = GPIO_timer_resolution; - // CTLR1: default is up, events generated, edge align - // enable auto-reload of preload - TIM2->CTLR1 |= TIM_ARPE; - // initialize counter - TIM2->SWEVGR |= TIM_UG; - // Enable TIM2 - TIM2->CTLR1 |= TIM_CEN; +static inline void GPIO_tim2_init() { + // enable TIM2 + RCC->APB1PCENR |= RCC_APB1Periph_TIM2; + // reset TIM2 to init all regs + RCC->APB1PRSTR |= RCC_APB1Periph_TIM2; + RCC->APB1PRSTR &= ~RCC_APB1Periph_TIM2; + // SMCFGR: default clk input is CK_INT + // set clock prescaler divider + TIM2->PSC = GPIO_timer_prescaler; + // set PWM total cycle width + TIM2->ATRLR = GPIO_timer_resolution; + // CTLR1: default is up, events generated, edge align + // enable auto-reload of preload + TIM2->CTLR1 |= TIM_ARPE; + // initialize counter + TIM2->SWEVGR |= TIM_UG; + // Enable TIM2 + TIM2->CTLR1 |= TIM_CEN; } -#define GPIO_timer_channel_set2(timer, channel) GPIO_timer_channel_set_##channel(timer) -#define GPIO_timer_channel_set(timer, channel) GPIO_timer_channel_set2(timer, channel) -#define GPIO_timer_channel_set_1(timer) timer->CHCTLR1 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) -#define GPIO_timer_channel_set_2(timer) timer->CHCTLR1 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) -#define GPIO_timer_channel_set_3(timer) timer->CHCTLR2 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) -#define GPIO_timer_channel_set_4(timer) timer->CHCTLR2 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) +#define GPIO_timer_channel_set2(timer, channel) GPIO_timer_channel_set_##channel(timer) +#define GPIO_timer_channel_set(timer, channel) GPIO_timer_channel_set2(timer, channel) +#define GPIO_timer_channel_set_1(timer) timer->CHCTLR1 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) +#define GPIO_timer_channel_set_2(timer) timer->CHCTLR1 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) +#define GPIO_timer_channel_set_3(timer) timer->CHCTLR2 |= (TIM_OCMode_PWM1 | TIM_OCPreload_Enable) +#define GPIO_timer_channel_set_4(timer) timer->CHCTLR2 |= ((TIM_OCMode_PWM1 | TIM_OCPreload_Enable) << 8) #undef GPIO_tim1_enableCH -#define GPIO_tim1_enableCH(channel) ({ \ - GPIO_timer_channel_set(TIM1, channel); \ - TIM1->CCER |= (TIM_OutputState_Enable) << (4 * (channel - 1)); \ +#define GPIO_tim1_enableCH(channel) ({ \ + GPIO_timer_channel_set(TIM1, channel); \ + TIM1->CCER |= (TIM_OutputState_Enable) << (4 * (channel - 1)); \ }) #undef GPIO_tim2_enableCH -#define GPIO_tim2_enableCH(channel) ({ \ - GPIO_timer_channel_set(TIM2, channel); \ - TIM2->CCER |= (TIM_OutputState_Enable) << (4 * (channel - 1)); \ +#define GPIO_tim2_enableCH(channel) ({ \ + GPIO_timer_channel_set(TIM2, channel); \ + TIM2->CCER |= (TIM_OutputState_Enable ) << (4 * (channel - 1)); \ }) -#define GPIO_timer_CVR(channel) CONCAT_INDIRECT(CH, CONCAT_INDIRECT(channel, CVR)) +#define GPIO_timer_CVR(channel) CONCAT_INDIRECT(CH, CONCAT_INDIRECT(channel, CVR)) #undef GPIO_tim1_analogWrite -#define GPIO_tim1_analogWrite(channel, value) TIM1->GPIO_timer_CVR(channel) = value; +#define GPIO_tim1_analogWrite(channel, value) TIM1->GPIO_timer_CVR(channel) = value; #undef GPIO_tim2_analogWrite -#define GPIO_tim2_analogWrite(channel, value) TIM2->GPIO_timer_CVR(channel) = value; +#define GPIO_tim2_analogWrite(channel, value) TIM2->GPIO_timer_CVR(channel) = value; #endif // CH32V003_GPIO_BR_H diff --git a/inc/extralibs/ch32v003_SPI.h b/inc/extralibs/ch32v003_SPI.h index cbca66b..d2b98a3 100644 --- a/inc/extralibs/ch32v003_SPI.h +++ b/inc/extralibs/ch32v003_SPI.h @@ -1,15 +1,15 @@ -// ######## necessities +//######## necessities // include guards #ifndef CH32V003_SPI_H #define CH32V003_SPI_H // includes +#include //uintN_t support #include "ch32fun.h" -#include //uintN_t support #ifndef APB_CLOCK -#define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK + #define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK #endif /*######## library usage and configuration @@ -20,7 +20,7 @@ SYSTEM_CORE_CLOCK and APB_CLOCK should be defined already as APB_CLOCK is used b #ifndef APB_CLOCK - #define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK + #define APB_CLOCK FUNCONF_SYSTEM_CORE_CLOCK #endif to enable using the functions of this library: @@ -47,8 +47,10 @@ then pick the desired setting of each group: #define CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL // toggle manually! */ -// ######## function overview (declarations): use these! -// initialize and configure the SPI peripheral + + +//######## function overview (declarations): use these! +// initialize and configure the SPI peripheral static inline void SPI_init(); // establish / end a connection to the SPI device @@ -65,14 +67,14 @@ static inline void SPI_NSS_software_high(); // read / write the SPI device // these commands are raw, you'll have to consider all other steps in SPI_transfer! -static inline uint8_t SPI_read_8(); +static inline uint8_t SPI_read_8(); static inline uint16_t SPI_read_16(); -static inline void SPI_write_8(uint8_t data); -static inline void SPI_write_16(uint16_t data); +static inline void SPI_write_8(uint8_t data); +static inline void SPI_write_16(uint16_t data); // send a command and get a response from the SPI device // you'll use this for most devices -static inline uint8_t SPI_transfer_8(uint8_t data); +static inline uint8_t SPI_transfer_8(uint8_t data); static inline uint16_t SPI_transfer_16(uint16_t data); // SPI peripheral power enable / disable (default off, init() automatically enables) @@ -85,25 +87,31 @@ static inline void SPI_poweron(); static inline void kill_interrrupts(); static inline void restore_interrupts(); -// ######## internal function declarations -static inline void SPI_wait_TX_complete(); -static inline uint8_t SPI_is_RX_empty(); -static inline void SPI_wait_RX_available(); -// ######## internal variables + +//######## internal function declarations +static inline void SPI_wait_TX_complete(); +static inline uint8_t SPI_is_RX_empty(); +static inline void SPI_wait_RX_available(); + + + +//######## internal variables static uint16_t EXT1_INTENR_backup; -// ######## preprocessor macros -// min and max helper macros -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + + +//######## preprocessor macros +// min and max helper macros +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) // stringify for displaying what #defines evaluated to at preprocessor stage #define VALUE_TO_STRING(x) #x #define VALUE(x) VALUE_TO_STRING(x) -#define VAR_NAME_VALUE(var) #var "=" VALUE(var) +#define VAR_NAME_VALUE(var) #var "=" VALUE(var) -// compile-time log2 +//compile-time log2 #define LOG2(x) ((x) == 0 ? -1 : __builtin_ctz(x)) // compile-time clock prescaler calculation: log2(APB_CLOCK/SPEED_BUS) @@ -112,249 +120,233 @@ static uint16_t EXT1_INTENR_backup; // ensure that CLOCK_PRESCALER_VALUE is within the range of 0..7 _Static_assert(SPI_CLK_PRESCALER >= 0 && SPI_CLK_PRESCALER <= 7, "SPI_CLK_PRESCALER is out of range (0..7). Please set a different SPI bus speed. prescaler = log2(f_CPU/f_SPI)"); -// #pragma message(VAR_NAME_VALUE(SPI_CLK_PRESCALER)) +#pragma message(VAR_NAME_VALUE(SPI_CLK_PRESCALER)) -// ######## preprocessor #define requirements + + +//######## preprocessor #define requirements #if !defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) && !defined(CH32V003_SPI_DIRECTION_1LINE_TX) -#warning "none of the CH32V003_SPI_DIRECTION_ options were defined!" + #warning "none of the CH32V003_SPI_DIRECTION_ options were defined!" #endif #if defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) && defined(CH32V003_SPI_DIRECTION_1LINE_TX) -#warning "both CH32V003_SPI_DIRECTION_ options were defined!" + #warning "both CH32V003_SPI_DIRECTION_ options were defined!" #endif #if ((defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) > 1 -#warning "more than one of the CH32V003_SPI_CLK_MODE_ options were defined!" + (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) > 1 + #warning "more than one of the CH32V003_SPI_CLK_MODE_ options were defined!" #endif #if ((defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ - (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) == 0 -#warning "none of the CH32V003_SPI_CLK_MODE_ options were defined!" + (defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) ? 1 : 0) + \ + (defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) ? 1 : 0)) == 0 + #warning "none of the CH32V003_SPI_CLK_MODE_ options were defined!" #endif #if ((defined(CH32V003_SPI_NSS_HARDWARE_PC0) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) > 1 -#warning "more than one of the CH32V003_SPI_NSS_ options were defined!" + (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) > 1 + #warning "more than one of the CH32V003_SPI_NSS_ options were defined!" #endif #if ((defined(CH32V003_SPI_NSS_HARDWARE_PC0) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ - (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) == 0 -#warning "none of the CH32V003_SPI_NSS_ options were defined!" + (defined(CH32V003_SPI_NSS_HARDWARE_PC1) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC3) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_PC4) ? 1 : 0) + \ + (defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) ? 1 : 0)) == 0 + #warning "none of the CH32V003_SPI_NSS_ options were defined!" #endif -// ######## small function definitions, static inline -static inline void SPI_init() -{ - SPI_poweron(); - // reset control register - SPI1->CTLR1 = 0; - // set prescaler - SPI1->CTLR1 |= SPI_CTLR1_BR & (SPI_CLK_PRESCALER << 3); +//######## small function definitions, static inline +static inline void SPI_init() { + SPI_poweron(); + + // reset control register + SPI1->CTLR1 = 0; -// set clock polarity and phase -#if defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) - SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_1Edge); -#elif defined(CH32V003_SPI_CLK_MODE_POL0_PHA1) - SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_2Edge); -#elif defined(CH32V003_SPI_CLK_MODE_POL1_PHA0) - SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_1Edge); -#elif defined(CH32V003_SPI_CLK_MODE_POL1_PHA1) - SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_2Edge); -#endif + // set prescaler + SPI1->CTLR1 |= SPI_CTLR1_BR & (SPI_CLK_PRESCALER<<3); -// configure NSS pin, master mode -#if defined(CH32V003_SPI_NSS_HARDWARE_PC0) - // _NSS (negative slave select) on PC0, 10MHz Output, alt func, push-pull1 - SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode - GPIOC->CFGLR &= ~(0xf << (4 * 0)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 0); - AFIO->PCFR1 |= GPIO_Remap_SPI1; // remap NSS (C1) to _NSS (C0) - SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high -#elif defined(CH32V003_SPI_NSS_HARDWARE_PC1) - // NSS (negative slave select) on PC1, 10MHz Output, alt func, push-pull1 - SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode - GPIOC->CFGLR &= ~(0xf << (4 * 1)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 1); - SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high -#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC3) - SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode - GPIOC->CFGLR &= ~(0xf << (4 * 3)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 3); -#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode - GPIOC->CFGLR &= ~(0xf << (4 * 4)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 4); -#elif defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) - SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode -#endif + // set clock polarity and phase + #if defined(CH32V003_SPI_CLK_MODE_POL0_PHA0) + SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_1Edge); + #elif defined (CH32V003_SPI_CLK_MODE_POL0_PHA1) + SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_2Edge); + #elif defined (CH32V003_SPI_CLK_MODE_POL1_PHA0) + SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_1Edge); + #elif defined (CH32V003_SPI_CLK_MODE_POL1_PHA1) + SPI1->CTLR1 |= (SPI_CPOL_High | SPI_CPHA_2Edge); + #endif + + // configure NSS pin, master mode + #if defined(CH32V003_SPI_NSS_HARDWARE_PC0) + // _NSS (negative slave select) on PC0, 10MHz Output, alt func, push-pull1 + SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode + GPIOC->CFGLR &= ~(0xf<<(4*0)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*0); + AFIO->PCFR1 |= GPIO_Remap_SPI1; // remap NSS (C1) to _NSS (C0) + SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high + #elif defined(CH32V003_SPI_NSS_HARDWARE_PC1) + // NSS (negative slave select) on PC1, 10MHz Output, alt func, push-pull1 + SPI1->CTLR1 |= SPI_NSS_Hard; // NSS hardware control mode + GPIOC->CFGLR &= ~(0xf<<(4*1)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*1); + SPI1->CTLR2 |= SPI_CTLR2_SSOE; // pull _NSS high + #elif defined(CH32V003_SPI_NSS_SOFTWARE_PC3) + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode + GPIOC->CFGLR &= ~(0xf<<(4*3)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*3); + #elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode + GPIOC->CFGLR &= ~(0xf<<(4*4)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*4); + #elif defined(CH32V003_SPI_NSS_SOFTWARE_ANY_MANUAL) + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode + #endif - // SCK on PC5, 10MHz Output, alt func, push-pull - GPIOC->CFGLR &= ~(0xf << (4 * 5)); - GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5); + // SCK on PC5, 10MHz Output, alt func, push-pull + GPIOC->CFGLR &= ~(0xf<<(4*5)); + GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF)<<(4*5); - // CH32V003 is master - SPI1->CTLR1 |= SPI_Mode_Master; + // CH32V003 is master + SPI1->CTLR1 |= SPI_Mode_Master; + + // set data direction and configure data pins + #if defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) + SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex; -// set data direction and configure data pins -#if defined(CH32V003_SPI_DIRECTION_2LINE_TXRX) - SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex; + // MOSI on PC6, 10MHz Output, alt func, push-pull + GPIOC->CFGLR &= ~(0xf<<(4*6)); + GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF)<<(4*6); + + // MISO on PC7, 10MHz input, floating + GPIOC->CFGLR &= ~(0xf<<(4*7)); + GPIOC->CFGLR |= GPIO_CNF_IN_FLOATING<<(4*7); + #elif defined(CH32V003_SPI_DIRECTION_1LINE_TX) + SPI1->CTLR1 |= SPI_Direction_1Line_Tx; - // MOSI on PC6, 10MHz Output, alt func, push-pull - GPIOC->CFGLR &= ~(0xf << (4 * 6)); - GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 6); - - // MISO on PC7, 10MHz input, floating - GPIOC->CFGLR &= ~(0xf << (4 * 7)); - GPIOC->CFGLR |= GPIO_CNF_IN_FLOATING << (4 * 7); -#elif defined(CH32V003_SPI_DIRECTION_1LINE_TX) - SPI1->CTLR1 |= SPI_Direction_1Line_Tx; - - // MOSI on PC6, 10MHz Output, alt func, push-pull - GPIOC->CFGLR &= ~(0xf << (4 * 6)); - GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 6); -#endif + // MOSI on PC6, 10MHz Output, alt func, push-pull + GPIOC->CFGLR &= ~(0xf<<(4*6)); + GPIOC->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF)<<(4*6); + #endif } -static inline void SPI_begin_8() -{ - SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // DFF 16bit data-length enable, writable only when SPE is 0 - SPI1->CTLR1 |= SPI_CTLR1_SPE; +static inline void SPI_begin_8() { + SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // DFF 16bit data-length enable, writable only when SPE is 0 + SPI1->CTLR1 |= SPI_CTLR1_SPE; } -static inline void SPI_begin_16() -{ - SPI1->CTLR1 |= SPI_CTLR1_DFF; // DFF 16bit data-length enable, writable only when SPE is 0 - SPI1->CTLR1 |= SPI_CTLR1_SPE; +static inline void SPI_begin_16() { + SPI1->CTLR1 |= SPI_CTLR1_DFF; // DFF 16bit data-length enable, writable only when SPE is 0 + SPI1->CTLR1 |= SPI_CTLR1_SPE; } -static inline void SPI_end() -{ - SPI1->CTLR1 &= ~(SPI_CTLR1_SPE); +static inline void SPI_end() { + SPI1->CTLR1 &= ~(SPI_CTLR1_SPE); } #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) -static inline void SPI_NSS_software_high() -{ - GPIOC->BSHR = (1 << 3); +static inline void SPI_NSS_software_high() { + GPIOC->BSHR = (1<<3); } -static inline void SPI_NSS_software_low() -{ - GPIOC->BSHR = (1 << (16 + 3)); +static inline void SPI_NSS_software_low() { + GPIOC->BSHR = (1<<(16+3)); } -#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) -static inline void SPI_NSS_software_high() -{ - GPIOC->BSHR = (1 << 4); +#elif defined(CH32V003_SPI_NSS_SOFTWARE_PC4) +static inline void SPI_NSS_software_high() { + GPIOC->BSHR = (1<<4); } -static inline void SPI_NSS_software_low() -{ - GPIOC->BSHR = (1 << (16 + 4)); +static inline void SPI_NSS_software_low() { + GPIOC->BSHR = (1<<(16+4)); } #endif -static inline uint8_t SPI_read_8() -{ - return SPI1->DATAR; +static inline uint8_t SPI_read_8() { + return SPI1->DATAR; } -static inline uint16_t SPI_read_16() -{ - return SPI1->DATAR; +static inline uint16_t SPI_read_16() { + return SPI1->DATAR; } -static inline void SPI_write_8(uint8_t data) -{ - SPI1->DATAR = data; +static inline void SPI_write_8(uint8_t data) { + SPI1->DATAR = data; } -static inline void SPI_write_16(uint16_t data) -{ - SPI1->DATAR = data; +static inline void SPI_write_16(uint16_t data) { + SPI1->DATAR = data; } -static inline uint8_t SPI_transfer_8(uint8_t data) -{ -#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_high(); -#endif - SPI_write_8(data); - SPI_wait_TX_complete(); - asm volatile("nop"); - SPI_wait_RX_available(); -#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_low(); -#endif - return SPI_read_8(); +static inline uint8_t SPI_transfer_8(uint8_t data) { + #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_high(); + #endif + SPI_write_8(data); + SPI_wait_TX_complete(); + asm volatile("nop"); + SPI_wait_RX_available(); + #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_low(); + #endif + return SPI_read_8(); } -static inline uint16_t SPI_transfer_16(uint16_t data) -{ -#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_high(); -#endif - SPI_write_16(data); - SPI_wait_TX_complete(); - asm volatile("nop"); - SPI_wait_RX_available(); -#if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) - SPI_NSS_software_low(); -#endif - return SPI_read_16(); +static inline uint16_t SPI_transfer_16(uint16_t data) { + #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_high(); + #endif + SPI_write_16(data); + SPI_wait_TX_complete(); + asm volatile("nop"); + SPI_wait_RX_available(); + #if defined(CH32V003_SPI_NSS_SOFTWARE_PC3) || defined(CH32V003_SPI_NSS_SOFTWARE_PC4) + SPI_NSS_software_low(); + #endif + return SPI_read_16(); } -static inline void SPI_poweroff() -{ - SPI_end(); - RCC->APB2PCENR &= ~RCC_APB2Periph_SPI1; +static inline void SPI_poweroff() { + SPI_end(); + RCC->APB2PCENR &= ~RCC_APB2Periph_SPI1; } -static inline void SPI_poweron() -{ - RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; +static inline void SPI_poweron() { + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; } -static inline void kill_interrrupts() -{ - EXT1_INTENR_backup = EXTI->INTENR; - // zero the interrupt enable register to disable all interrupts - EXTI->INTENR = 0; +static inline void kill_interrrupts() { + EXT1_INTENR_backup = EXTI->INTENR; + // zero the interrupt enable register to disable all interrupts + EXTI->INTENR = 0; } -static inline void restore_interrupts() -{ - EXTI->INTENR = EXT1_INTENR_backup; +static inline void restore_interrupts() { + EXTI->INTENR = EXT1_INTENR_backup; } -// ######## small internal function definitions, static inline -static inline void SPI_wait_TX_complete() -{ - while (!(SPI1->STATR & SPI_STATR_TXE)) {} + + +//######## small internal function definitions, static inline +static inline void SPI_wait_TX_complete() { + while(!(SPI1->STATR & SPI_STATR_TXE)) {} } -static inline uint8_t SPI_is_RX_empty() -{ - return SPI1->STATR & SPI_STATR_RXNE; +static inline uint8_t SPI_is_RX_empty() { + return SPI1->STATR & SPI_STATR_RXNE; } -static inline void SPI_wait_RX_available() -{ - while (!(SPI1->STATR & SPI_STATR_RXNE)) {} +static inline void SPI_wait_RX_available() { + while(!(SPI1->STATR & SPI_STATR_RXNE)) {} } -static inline void SPI_wait_not_busy() -{ - while ((SPI1->STATR & SPI_STATR_BSY) != 0) {} +static inline void SPI_wait_not_busy() { + while((SPI1->STATR & SPI_STATR_BSY) != 0) {} } -static inline void SPI_wait_transmit_finished() -{ - SPI_wait_TX_complete(); - SPI_wait_not_busy(); +static inline void SPI_wait_transmit_finished() { + SPI_wait_TX_complete(); + SPI_wait_not_busy(); } -// ######## implementation block -// #define CH32V003_SPI_IMPLEMENTATION //enable so LSP can give you text colors while working on the implementation block, disable for normal use of the library + +//######## implementation block +//#define CH32V003_SPI_IMPLEMENTATION //enable so LSP can give you text colors while working on the implementation block, disable for normal use of the library #if defined(CH32V003_SPI_IMPLEMENTATION) -// no functions here because I think all of the functions are small enough to static inline +//no functions here because I think all of the functions are small enough to static inline #endif // CH32V003_SPI_IMPLEMENTATION #endif // CH32V003_SPI_H diff --git a/inc/extralibs/ch32v003_touch.h b/inc/extralibs/ch32v003_touch.h index 44f42e2..825f7e8 100644 --- a/inc/extralibs/ch32v003_touch.h +++ b/inc/extralibs/ch32v003_touch.h @@ -3,42 +3,44 @@ /** ADC-based Capactive Touch Control. - see cap_touch_adc.c for an example. + see cap_touch_adc.c for an example. - // Enable GPIOD, C and ADC - RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC | RCC_APB2Periph_ADC1; - InitTouchADC(); + // Enable GPIOD, C and ADC + RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC | RCC_APB2Periph_ADC1; + InitTouchADC(); - // Then do this any time you want to read some touches. - sum[0] += ReadTouchPin( GPIOA, 2, 0, iterations ); - sum[1] += ReadTouchPin( GPIOA, 1, 1, iterations ); - sum[2] += ReadTouchPin( GPIOC, 4, 2, iterations ); - sum[3] += ReadTouchPin( GPIOD, 2, 3, iterations ); - sum[4] += ReadTouchPin( GPIOD, 3, 4, iterations ); - sum[5] += ReadTouchPin( GPIOD, 5, 5, iterations ); - sum[6] += ReadTouchPin( GPIOD, 6, 6, iterations ); - sum[7] += ReadTouchPin( GPIOD, 4, 7, iterations ); + // Then do this any time you want to read some touches. + sum[0] += ReadTouchPin( GPIOA, 2, 0, iterations ); + sum[1] += ReadTouchPin( GPIOA, 1, 1, iterations ); + sum[2] += ReadTouchPin( GPIOC, 4, 2, iterations ); + sum[3] += ReadTouchPin( GPIOD, 2, 3, iterations ); + sum[4] += ReadTouchPin( GPIOD, 3, 4, iterations ); + sum[5] += ReadTouchPin( GPIOD, 5, 5, iterations ); + sum[6] += ReadTouchPin( GPIOD, 6, 6, iterations ); + sum[7] += ReadTouchPin( GPIOD, 4, 7, iterations ); */ -#define TOUCH_ADC_SAMPLE_TIME 2 // Tricky: Don't change this without a lot of experimentation. + + +#define TOUCH_ADC_SAMPLE_TIME 2 // Tricky: Don't change this without a lot of experimentation. // Can either be 0 or 1. // If 0: Measurement low and rises high. So more pressed is smaller number. // If 1: Higher number = harder press. Good to pair with TOUCH_FLAT. // If you are doing more prox, use mode 0, otherwise, use mode 1. -#define TOUCH_SLOPE 1 +#define TOUCH_SLOPE 1 // If you set this to 1, it will glitch the line, so it will only read // anything reasonable if the capacitance can overcome that initial spike. // Typically, it seems if you use this you probbly don't need to do // any pre-use calibration. -#define TOUCH_FLAT 0 +#define TOUCH_FLAT 0 // Macro used for force-alingining ADC timing #define FORCEALIGNADC \ - asm volatile( \ - "\n\ + asm volatile( \ + "\n\ .balign 4\n\ andi a2, %[cyccnt], 3\n\ c.slli a2, 1\n\ @@ -48,172 +50,169 @@ jalr a2, 1\n\ .long 0x00010001\n\ .long 0x00010001\n\ - " ::[cyccnt] "r"(SysTick->CNT) : "a1", "a2"); + "\ + :: [cyccnt]"r"(SysTick->CNT) : "a1", "a2"\ + ); -static void InitTouchADC(); -void InitTouchADC() + +static void InitTouchADC( ); +void InitTouchADC( ) { - // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide sys clock by 2 - RCC->CFGR0 &= ~(0x1F << 11); + // ADCCLK = 24 MHz => RCC_ADCPRE = 0: divide sys clock by 2 + RCC->CFGR0 &= ~(0x1F<<11); - // Set up single conversion on chl 2 - ADC1->RSQR1 = 0; - ADC1->RSQR2 = 0; + // Set up single conversion on chl 2 + ADC1->RSQR1 = 0; + ADC1->RSQR2 = 0; - // turn on ADC and set rule group to sw trig - ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL; - - // Reset calibration - ADC1->CTLR2 |= ADC_RSTCAL; - while (ADC1->CTLR2 & ADC_RSTCAL) - ; - - // Calibrate - ADC1->CTLR2 |= ADC_CAL; - while (ADC1->CTLR2 & ADC_CAL) - ; + // turn on ADC and set rule group to sw trig + ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL; + + // Reset calibration + ADC1->CTLR2 |= ADC_RSTCAL; + while(ADC1->CTLR2 & ADC_RSTCAL); + + // Calibrate + ADC1->CTLR2 |= ADC_CAL; + while(ADC1->CTLR2 & ADC_CAL); } // Run from RAM to get even more stable timing. // This function call takes about 8.1uS to execute. -static uint32_t ReadTouchPin(GPIO_TypeDef *io, int portpin, int adcno, int iterations) __attribute__((noinline, section(".srodata"))); -uint32_t ReadTouchPin(GPIO_TypeDef *io, int portpin, int adcno, int iterations) +static uint32_t ReadTouchPin( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) __attribute__((noinline, section(".srodata"))); +uint32_t ReadTouchPin( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) { - uint32_t ret = 0; + uint32_t ret = 0; - __disable_irq(); - FORCEALIGNADC - ADC1->RSQR3 = adcno; - ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME << (3 * adcno); - __enable_irq(); + __disable_irq(); + FORCEALIGNADC + ADC1->RSQR3 = adcno; + ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME<<(3*adcno); + __enable_irq(); - uint32_t CFGBASE = io->CFGLR & (~(0xf << (4 * portpin))); - uint32_t CFGFLOAT = ((GPIO_CFGLR_IN_PUPD) << (4 * portpin)) | CFGBASE; - uint32_t CFGDRIVE = (GPIO_CFGLR_OUT_2Mhz_PP) << (4 * portpin) | CFGBASE; + uint32_t CFGBASE = io->CFGLR & (~(0xf<<(4*portpin))); + uint32_t CFGFLOAT = ((GPIO_CFGLR_IN_PUPD)<<(4*portpin)) | CFGBASE; + uint32_t CFGDRIVE = (GPIO_CFGLR_OUT_2Mhz_PP)<<(4*portpin) | CFGBASE; + + // If we run multiple times with slightly different wait times, we can + // reduce the impact of the ADC's DNL. - // If we run multiple times with slightly different wait times, we can - // reduce the impact of the ADC's DNL. #if TOUCH_FLAT == 1 -#define RELEASEIO \ - io->BSHR = 1 << (portpin + 16 * TOUCH_SLOPE); \ - io->CFGLR = CFGFLOAT; +#define RELEASEIO io->BSHR = 1<<(portpin+16*TOUCH_SLOPE); io->CFGLR = CFGFLOAT; #else -#define RELEASEIO \ - io->CFGLR = CFGFLOAT; \ - io->BSHR = 1 << (portpin + 16 * TOUCH_SLOPE); +#define RELEASEIO io->CFGLR = CFGFLOAT; io->BSHR = 1<<(portpin+16*TOUCH_SLOPE); #endif -#define INNER_LOOP(n) \ - { \ - /* Only lock IRQ for a very narrow window. */ \ - __disable_irq(); \ - FORCEALIGNADC \ - \ - /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ - this We are catching it onthe slope much more effectively. */ \ - ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ - \ - ADD_N_NOPS(n) \ - \ - RELEASEIO \ - \ - /* Sampling actually starts here, somewhere, so we can let other \ - interrupts run */ \ - __enable_irq(); \ - while (!(ADC1->STATR & ADC_EOC)) \ - ; \ - io->CFGLR = CFGDRIVE; \ - io->BSHR = 1 << (portpin + (16 * (1 - TOUCH_SLOPE))); \ - ret += ADC1->RDATAR; \ - } +#define INNER_LOOP( n ) \ + { \ + /* Only lock IRQ for a very narrow window. */ \ + __disable_irq(); \ + FORCEALIGNADC \ + \ + /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ + this We are catching it onthe slope much more effectively. */ \ + ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ + \ + ADD_N_NOPS( n ) \ + \ + RELEASEIO \ + \ + /* Sampling actually starts here, somewhere, so we can let other \ + interrupts run */ \ + __enable_irq(); \ + while(!(ADC1->STATR & ADC_EOC)); \ + io->CFGLR = CFGDRIVE; \ + io->BSHR = 1<<(portpin+(16*(1-TOUCH_SLOPE))); \ + ret += ADC1->RDATAR; \ + } - int i; - for (i = 0; i < iterations; i++) - { - // Wait a variable amount of time based on loop iteration, in order - // to get a variety of RC points and minimize DNL. + int i; + for( i = 0; i < iterations; i++ ) + { + // Wait a variable amount of time based on loop iteration, in order + // to get a variety of RC points and minimize DNL. - INNER_LOOP(0); - INNER_LOOP(2); - INNER_LOOP(4); - } + INNER_LOOP( 0 ); + INNER_LOOP( 2 ); + INNER_LOOP( 4 ); + } - return ret; + return ret; } // Run from RAM to get even more stable timing. // This function call takes about 8.1uS to execute. -static uint32_t ReadTouchPinSafe(GPIO_TypeDef *io, int portpin, int adcno, int iterations) __attribute__((noinline, section(".srodata"))); -uint32_t ReadTouchPinSafe(GPIO_TypeDef *io, int portpin, int adcno, int iterations) +static uint32_t ReadTouchPinSafe( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) __attribute__((noinline, section(".srodata"))); +uint32_t ReadTouchPinSafe( GPIO_TypeDef * io, int portpin, int adcno, int iterations ) { - uint32_t ret = 0; + uint32_t ret = 0; - ADC1->RSQR3 = adcno; - ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME << (3 * adcno); + ADC1->RSQR3 = adcno; + ADC1->SAMPTR2 = TOUCH_ADC_SAMPLE_TIME<<(3*adcno); - // If we run multiple times with slightly different wait times, we can - // reduce the impact of the ADC's DNL. + // If we run multiple times with slightly different wait times, we can + // reduce the impact of the ADC's DNL. -#define INNER_LOOP_SAFE(n) \ - { \ - /* Only lock IRQ for a very narrow window. */ \ - __disable_irq(); \ - \ - FORCEALIGNADC \ - \ - /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ - this We are catching it onthe slope much more effectively. */ \ - ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ - \ - ADD_N_NOPS(n) \ - \ - io->CFGLR = ((GPIO_CFGLR_IN_PUPD) << (4 * portpin)) | (io->CFGLR & (~(0xf << (4 * portpin)))); \ - io->BSHR = 1 << (portpin + 16 * TOUCH_SLOPE); \ - \ - /* Sampling actually starts here, somewhere, so we can let other \ - interrupts run */ \ - __enable_irq(); \ - while (!(ADC1->STATR & ADC_EOC)) \ - ; \ - __disable_irq(); \ - io->CFGLR = (GPIO_CFGLR_OUT_2Mhz_PP) << (4 * portpin) | (io->CFGLR & (~(0xf << (4 * portpin)))); \ - __enable_irq(); \ - io->BSHR = 1 << (portpin + (16 * (1 - TOUCH_SLOPE))); \ - ret += ADC1->RDATAR; \ - } +#define INNER_LOOP_SAFE( n ) \ + { \ + /* Only lock IRQ for a very narrow window. */ \ + __disable_irq(); \ + \ + FORCEALIGNADC \ + \ + /* Tricky - we start the ADC BEFORE we transition the pin. By doing \ + this We are catching it onthe slope much more effectively. */ \ + ADC1->CTLR2 = ADC_SWSTART | ADC_ADON | ADC_EXTSEL; \ + \ + ADD_N_NOPS( n ) \ + \ + io->CFGLR = ((GPIO_CFGLR_IN_PUPD)<<(4*portpin)) | (io->CFGLR & (~(0xf<<(4*portpin)))); \ + io->BSHR = 1<<(portpin+16*TOUCH_SLOPE); \ + \ + /* Sampling actually starts here, somewhere, so we can let other \ + interrupts run */ \ + __enable_irq(); \ + while(!(ADC1->STATR & ADC_EOC)); \ + __disable_irq(); \ + io->CFGLR = (GPIO_CFGLR_OUT_2Mhz_PP)<<(4*portpin) | (io->CFGLR & (~(0xf<<(4*portpin)))); \ + __enable_irq(); \ + io->BSHR = 1<<(portpin+(16*(1-TOUCH_SLOPE))); \ + ret += ADC1->RDATAR; \ + } - int i; - for (i = 0; i < iterations; i++) - { - // Wait a variable amount of time based on loop iteration, in order - // to get a variety of RC points and minimize DNL. + int i; + for( i = 0; i < iterations; i++ ) + { + // Wait a variable amount of time based on loop iteration, in order + // to get a variety of RC points and minimize DNL. - INNER_LOOP_SAFE(0); - INNER_LOOP_SAFE(2); - INNER_LOOP_SAFE(4); - } + INNER_LOOP_SAFE( 0 ); + INNER_LOOP_SAFE( 2 ); + INNER_LOOP_SAFE( 4 ); + } - return ret; + return ret; } + #endif /* * MIT License - * + * * Copyright (c) 2023 Valve Corporation - * + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -222,3 +221,4 @@ uint32_t ReadTouchPinSafe(GPIO_TypeDef *io, int portpin, int adcno, int i * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ + diff --git a/inc/extralibs/ch32v208_eth.h b/inc/extralibs/ch32v208_eth.h new file mode 100644 index 0000000..dc8994b --- /dev/null +++ b/inc/extralibs/ch32v208_eth.h @@ -0,0 +1,944 @@ +/* + * Single-File-Header for the CH32V208 (and CH579?) built-in 10BASE-T MAC/PHY. + * + * This peripheral uses POINTER-BASED DMA, not descriptor-based DMA: + * + * Hardware: + * - ERXST register: Points to buffer for next RX packet + * - ETXST register: Points to buffer for current TX packet + * - Hardware DMAs directly to/from these addresses + * - Software must manually update pointers after each packet + * + * Software (this driver): + * - Creates descriptor ring for bookkeeping + * - Descriptors are NEVER accessed by hardware + * - OWN bit is pure software: 1=empty, 0=filled + * - Provides ring-buffer API on top of simple pointers + * + * USAGE + * + * Include once with implementation: + * + * #define CH32V208_ETH_IMPLEMENTATION + * #include "ch32v208_eth.h" + * + * Init: + * + * eth_config_t config = { + * .mac_addr = my_mac, // NULL = use chip default + * .rx_callback = eth_rx_cb, // NULL if using manual polling + * .link_callback = link_cb, // optional + * .activity_callback = led_cb, // optional + * .broadcast_filter = true, + * }; + * eth_init(&config); + * + * Main loop: + * + * while (1) { + * eth_poll_link(); // call every 50-100ms + * eth_process_rx(); // IF using callback mode + * } + * + * RECEIVING PACKETS + * + * Callback mode: + * + * void eth_rx_cb(const uint8_t *packet, uint16_t length) { + * // process packet (called from eth_process_rx) + * } + * + * Manual polling (zero-copy, for sfhip, lwIP etc): + * + * uint16_t length; + * const uint8_t *packet; + * while ((packet = eth_get_rx_packet(&length)) != NULL) { + * // process packet directly from DMA buffer + * eth_release_rx_packet(); // must call when done + * } + * + * SENDING PACKETS + * + * Simple (with memcpy): + * + * uint8_t packet[64]; + * // ... fill packet ... + * int ret = eth_send_packet(packet, 64); + * // ret: 0=success, -1=queue full + * + * Zero-copy mode (build directly in DMA buffer): + * + * uint16_t max_len; + * uint8_t *buf = eth_get_tx_buffer(&max_len); + * if (buf) { + * // build packet directly in DMA buffer + * eth_send_packet_zerocopy(actual_length); + * } + * + * CONFIGURATION + * + * Define before including header to customize: + * + * ETH_RX_BUF_COUNT RX descriptor ring size (default: 4) + * ETH_TX_BUF_COUNT TX queue depth (default: 2) + * ETH_MAX_PACKET_SIZE MAC MTU (default: 1536) + * ETH_RX_BUF_SIZE RX buffer size (default: ETH_MAX_PACKET_SIZE) + * ETH_TX_BUF_SIZE TX buffer size (default: ETH_MAX_PACKET_SIZE) + * ETH_ENABLE_STATS Enable eth_get_stats() and eth_reset_stats() + */ + +#ifndef _CH32V208_ETH_H +#define _CH32V208_ETH_H + +#include +#include + +#ifndef ETH_RX_BUF_COUNT +#define ETH_RX_BUF_COUNT 4 +#endif + +#ifndef ETH_TX_BUF_COUNT +#define ETH_TX_BUF_COUNT 2 +#endif + +#ifndef ETH_MAX_PACKET_SIZE +#define ETH_MAX_PACKET_SIZE 1536 +#endif + +#ifndef ETH_RX_BUF_SIZE +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +#ifndef ETH_TX_BUF_SIZE +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +#define ETH_MAC_ADDR_LEN 6 + +// Define ETH_ENABLE_STATS before including this header to enable stats collection +// #define ETH_ENABLE_STATS + +// Callback types +typedef void ( *eth_rx_callback_t )( const uint8_t *packet, uint16_t length ); +typedef void ( *eth_link_callback_t )( bool link_up ); +typedef void ( *eth_activity_callback_t )( void ); + +// Ethernet configuration +typedef struct +{ + uint8_t *mac_addr; // MAC address (can be NULL to use chip default) + eth_rx_callback_t rx_callback; // Called when packet received + eth_link_callback_t link_callback; // Called when link status changes + eth_activity_callback_t activity_callback; // Called on TX/RX activity, can be used for LED + bool promiscuous_mode; // Enable promiscuous mode + bool broadcast_filter; // Accept broadcast packets + bool multicast_filter; // Accept multicast packets +} eth_config_t; + +#ifdef ETH_ENABLE_STATS +// Ethernet statistics +typedef struct +{ + uint32_t rx_packets; + uint32_t tx_packets; + uint32_t rx_errors; + uint32_t tx_errors; + uint32_t rx_dropped; + uint32_t tx_dropped; +} eth_stats_t; +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * Init the Ethernet peripheral + * @param config Ptr to config struct + * @return 0 on success, negative on error + */ + int eth_init( const eth_config_t *config ); + + /** + * Send an Ethernet packet + * @param packet Ptr to packet data (incl. Ethernet header) + * @param length Length of pkt in bytes + * @return 0: success, -1: queue full + */ + int eth_send_packet( const uint8_t *packet, uint16_t length ); + + /** + * Get pointer to next available TX buffer for zero-copy transmission + * @param length max length available in buffer + * @return pointer to TX buffer, or NULL if queue full + * @note After writing packet data, call eth_send_packet_zerocopy() with actual length + */ + uint8_t *eth_get_tx_buffer( uint16_t *max_length ); + + /** + * Commit a zero-copy TX buffer for transmission + * @param length packet length written to buffer from eth_get_tx_buffer() + * @return 0 on success + */ + int eth_send_packet_zerocopy( uint16_t length ); + + /** + * Process received packets (call from main loop) + * This will invoke the rx_callback for each received pkt + */ + void eth_process_rx( void ); + + /** + * Get pointer to next received packet (alternative to eth_process_rx with callback) + * @param length Pointer to store packet length + * @return Pointer to packet data, or NULL if no packet ready + * @note Caller MUST call eth_release_rx_packet() when done with the packet + * @note Packet data is valid only until eth_release_rx_packet() is called + */ + const uint8_t *eth_get_rx_packet( uint16_t *length ); + + /** + * Release currently held RX packet back to DMA + * @note Must be called after eth_get_rx_packet() to free the descriptor + */ + void eth_release_rx_packet( void ); + + /** + * Poll link status and handle auto-negotiation + * this is based on WCHNET_LinkProcess + * https://github.com/openwch/ch32v20x/blob/main/EVT/EXAM/ETH/NetLib/eth_driver.c#L131 + * TODO: cable polarity reversal is untested + * + * call this periodically from main loop (i.e. every 50-100ms) + */ + void eth_poll_link( void ); + + /** + * Get current MAC + * @param mac_addr Buffer to store MAC address (6 bytes) + */ + void eth_get_mac_address( uint8_t *mac_addr ); + + /** + * Check if link is up + * @return true if link is up + */ + bool eth_is_link_up( void ); + +#ifdef ETH_ENABLE_STATS + /** + * Get stats + * @param stats Pointer to statistics structure to fill + */ + void eth_get_stats( eth_stats_t *stats ); + + /** + * Reset stat counters + */ + void eth_reset_stats( void ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _CH32V208_ETH_H + + +#ifdef CH32V208_ETH_IMPLEMENTATION + +#include "ch32fun.h" +#include + +// DMA descriptor +typedef struct +{ + volatile uint32_t Status; + volatile uint32_t Buffer1Addr; +} ETH_DMADESCTypeDef; + +// TX queue management +typedef struct +{ + volatile uint32_t head; + volatile uint32_t tail; + volatile bool is_full; // this is only really needed if ETH_TX_BUF_COUNT == 1 +} tx_queue_t; + +// driver state +typedef struct +{ + uint32_t rx_head_idx; + uint32_t rx_tail_idx; + tx_queue_t tx_q; + uint8_t mac_addr[ETH_MAC_ADDR_LEN]; + eth_rx_callback_t rx_callback; + eth_link_callback_t link_callback; + eth_activity_callback_t activity_callback; + volatile bool link_irq_flag; +#ifdef ETH_ENABLE_STATS + eth_stats_t stats; +#endif + // autoneg & polarity state + uint8_t phy_mdix_mode; // current MDI/MDIX setting + uint8_t crc_error_count; // CRC errors since link up + bool polarity_detect_active; + uint8_t negotiation_poll_count; + enum + { + LINK_STATE_DOWN, + LINK_STATE_NEGOTIATING, + LINK_STATE_UP + } link_state; +} eth_driver_state_t; + +__attribute__( ( aligned( 4 ) ) ) static ETH_DMADESCTypeDef g_dma_rx_descs[ETH_RX_BUF_COUNT]; +__attribute__( ( aligned( 4 ) ) ) static ETH_DMADESCTypeDef g_dma_tx_descs[ETH_TX_BUF_COUNT]; +__attribute__( ( aligned( 4 ) ) ) static uint8_t g_mac_rx_bufs[ETH_RX_BUF_COUNT * ETH_RX_BUF_SIZE]; +__attribute__( ( aligned( 4 ) ) ) static uint8_t g_mac_tx_bufs[ETH_TX_BUF_COUNT * ETH_TX_BUF_SIZE]; + +static eth_driver_state_t g_eth_state = { 0 }; + +static void phy_write_reg( uint8_t reg_add, uint16_t reg_val ) +{ + R32_ETH_MIWR = ( reg_add & RB_ETH_MIREGADR_MASK ) | RB_ETH_MIWR_MIIWR | ( reg_val << RB_ETH_MIWR_DATA_SHIFT ); +} + +static uint16_t phy_read_reg( uint8_t reg_add ) +{ + ETH10M->MIERGADR = reg_add; + return ETH10M->MIRD; +} + +static inline void tx_queue_init( tx_queue_t *q ) +{ + q->head = 0; + q->tail = 0; + q->is_full = false; +} + +static inline bool tx_queue_is_empty( const tx_queue_t *q ) +{ + return !q->is_full && ( q->head == q->tail ); +} + +static inline bool tx_queue_is_full( const tx_queue_t *q ) +{ + return q->is_full; +} + +static inline void tx_queue_produce( tx_queue_t *q ) +{ + q->head = ( q->head + 1 ) % ETH_TX_BUF_COUNT; + if ( q->head == q->tail ) + { + q->is_full = true; // head caught up to tail = full + } +} + +static inline void tx_queue_consume( tx_queue_t *q ) +{ + q->tail = ( q->tail + 1 ) % ETH_TX_BUF_COUNT; + q->is_full = false; // after consuming, definitely not full +} + +static void eth_get_chip_mac_addr( uint8_t *mac ) +{ + const uint8_t *macaddr_src = (const uint8_t *)( ROM_CFG_USERADR_ID + 5 ); + for ( int i = 0; i < 6; i++ ) + { + mac[i] = *( macaddr_src-- ); + } +} + +static void tx_start_if_possible( void ) +{ + if ( ETH10M->ECON1 & RB_ETH_ECON1_TXRTS ) + { + return; + } + + if ( tx_queue_is_empty( &g_eth_state.tx_q ) ) + { + return; + } + + uint32_t idx = g_eth_state.tx_q.tail; + ETH_DMADESCTypeDef *desc = &g_dma_tx_descs[idx]; + uint16_t len = desc->Status; + + ETH10M->ETXLN = len; // set tx packet len + ETH10M->ETXST = desc->Buffer1Addr; // set tx buf start address (DMA source) + ETH10M->ECON1 |= RB_ETH_ECON1_TXRTS; // set tx req flag to start DMA transmission +} + +/** + * Start PHY auto-negotiation with specific MDI/MDIX mode + */ +static void phy_start_autoneg( uint8_t mdix_mode ) +{ + // reset and restart auto-negotiation + phy_write_reg( PHY_BMCR, PHY_BMCR_RESET ); + Delay_Us( 100 ); + // configure MDI/MDIX mode + phy_write_reg( PHY_MDIX, ( mdix_mode & MDIX_MODE_MASK ) | MDIX_PN_POLARITY_NORMAL ); + // enable auto-negotiation + phy_write_reg( PHY_BMCR, PHY_BMCR_AN_ENABLE | PHY_BMCR_AN_RESTART ); + + g_eth_state.phy_mdix_mode = mdix_mode; +} + +/** + * Try next MDI/MDIX mode in sequence: AUTO -> MDIX -> MDI -> AUTO + */ +static void phy_try_next_mdix_mode( void ) +{ + uint8_t next_mode; + + switch ( g_eth_state.phy_mdix_mode & MDIX_MODE_MASK ) + { + case MDIX_MODE_AUTO: + next_mode = MDIX_MODE_MDIX; // try forced MDIX + break; + case MDIX_MODE_MDIX: + next_mode = MDIX_MODE_MDI; // try forced MDI + break; + default: + next_mode = MDIX_MODE_AUTO; // back to auto + break; + } + + phy_start_autoneg( next_mode ); +} + +/** + * Handle cable polarity issue (P/N reversal) + */ +static void phy_fix_polarity( void ) +{ + uint16_t mdix_reg = phy_read_reg( PHY_MDIX ); + + // toggle P/N polarity between NORMAL and REVERSED + mdix_reg ^= MDIX_PN_POLARITY_REVERSED; + + phy_write_reg( PHY_MDIX, mdix_reg ); + g_eth_state.crc_error_count = 0; +} + +static void eth_link_up_handler( void ) +{ + // read auto-negotiation registers + uint16_t anar = phy_read_reg( PHY_ANAR ); // what we advertised + uint16_t anlpar = phy_read_reg( PHY_ANLPAR ); // what partner advertised + uint16_t common = anar & anlpar; + + // check if both sides support full-duplex + bool is_full_duplex = ( common & PHY_ANLPAR_10BASE_TFD ) != 0; + // configure MAC to match negotiated duplex mode + if ( is_full_duplex ) + { + ETH10M->MACON2 |= RB_ETH_MACON2_FULDPX; + } + else + { + ETH10M->MACON2 &= ~RB_ETH_MACON2_FULDPX; + } + // enable CRC error packet reception for polarity detection + ETH10M->ERXFCON |= RB_ETH_ERXFCON_CRCEN; + + g_eth_state.link_state = LINK_STATE_UP; + g_eth_state.crc_error_count = 0; + g_eth_state.polarity_detect_active = true; + g_eth_state.negotiation_poll_count = 0; + + if ( g_eth_state.link_callback ) + { + g_eth_state.link_callback( true ); + } +} + +/** + * Configure MAC for link down + */ +static void eth_link_down_handler( void ) +{ + // Disable polarity detection + g_eth_state.polarity_detect_active = false; + ETH10M->ERXFCON &= ~RB_ETH_ERXFCON_CRCEN; + + g_eth_state.link_state = LINK_STATE_DOWN; + + if ( g_eth_state.link_callback ) + { + g_eth_state.link_callback( false ); + } +} + +int eth_init( const eth_config_t *config ) +{ + if ( !config ) + { + return -1; + } + + memset( &g_eth_state, 0, sizeof( g_eth_state ) ); + + g_eth_state.rx_callback = config->rx_callback; + g_eth_state.link_callback = config->link_callback; + g_eth_state.activity_callback = config->activity_callback; + + if ( config->mac_addr ) + { + memcpy( g_eth_state.mac_addr, config->mac_addr, ETH_MAC_ADDR_LEN ); + } + else + { + eth_get_chip_mac_addr( g_eth_state.mac_addr ); + } + + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; + RCC->CFGR0 |= RCC_ETHPRE; // Ethernet clock prescaler + EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN; // Extended Control Register, 10M Ethernet enable and clock enable + + // Transmit/Receive module reset + ETH10M->ECON1 = RB_ETH_ECON1_TXRST | RB_ETH_ECON1_RXRST; + ETH10M->ECON1 = 0; + + uint32_t rx_filter; + + if ( config->promiscuous_mode ) + { + // Promiscuous: disable filtering (ERXFCON=0 *probably* receives everything) + rx_filter = 0; + } + else + { + // Normal mode: enable filtering and ALWAYS receive unicast to our MAC + rx_filter = RB_ETH_ERXFCON_EN | RB_ETH_ERXFCON_UCEN; + + // broadcast packet reception + if ( config->broadcast_filter ) + { + rx_filter |= RB_ETH_ERXFCON_BCEN; + } + // multicast packet reception + if ( config->multicast_filter ) + { + rx_filter |= RB_ETH_ERXFCON_MCEN; + } + } + + ETH10M->ERXFCON = rx_filter; + // MAC layer receive enable + ETH10M->MACON1 = RB_ETH_MACON1_MARXEN; + + // Pad short packets with 0x00 to 60 bytes, then append 4-byte CRC + // Hardware pads CRC + ETH10M->MACON2 = PADCFG_AUTO_3 | RB_ETH_MACON2_TXCRCEN; + // Set maximum frame length (MTU) + ETH10M->MAMXFL = ETH_MAX_PACKET_SIZE; + + // MAC is reversed + R8_ETH_MAADRL1 = g_eth_state.mac_addr[5]; + R8_ETH_MAADRL2 = g_eth_state.mac_addr[4]; + R8_ETH_MAADRL3 = g_eth_state.mac_addr[3]; + R8_ETH_MAADRL4 = g_eth_state.mac_addr[2]; + R8_ETH_MAADRL5 = g_eth_state.mac_addr[1]; + R8_ETH_MAADRL6 = g_eth_state.mac_addr[0]; + + // PHY Analog Parameter Setting, default value and "Rated driver" + ETH10M->ECON2 = RB_ETH_ECON2_DEFAULT; + + tx_queue_init( &g_eth_state.tx_q ); + for ( int i = 0; i < ETH_TX_BUF_COUNT; i++ ) + { + g_dma_tx_descs[i].Status = 0; + g_dma_tx_descs[i].Buffer1Addr = (uint32_t)&g_mac_tx_bufs[i * ETH_TX_BUF_SIZE]; + } + + // init RX descriptor ring (DMA reads from these) + g_eth_state.rx_head_idx = 0; + g_eth_state.rx_tail_idx = 0; + for ( int i = 0; i < ETH_RX_BUF_COUNT; i++ ) + { + g_dma_rx_descs[i].Status = ETH_DMARxDesc_OWN; // DMA owns all initially + g_dma_rx_descs[i].Buffer1Addr = (uint32_t)&g_mac_rx_bufs[i * ETH_RX_BUF_SIZE]; + } + + // start RX + ETH10M->ERXST = g_dma_rx_descs[0].Buffer1Addr; + ETH10M->ECON1 = RB_ETH_ECON1_RXEN; + + g_eth_state.link_state = LINK_STATE_DOWN; + g_eth_state.negotiation_poll_count = 0; + g_eth_state.polarity_detect_active = false; + g_eth_state.crc_error_count = 0; + + // start auto-negotiation with AUTO MDI/MDIX + phy_start_autoneg( MDIX_MODE_AUTO ); + Delay_Ms( 100 ); // Give PHY time to initialize + + // clear all pending interrupt flags + ETH10M->EIR = 0xFF; + ETH10M->ESTAT |= RB_ETH_ESTAT_INT | RB_ETH_ESTAT_BUFER; + + ETH10M->EIE = RB_ETH_EIE_INTIE | // Ethernet interrupt enable (master enable) + RB_ETH_EIE_RXIE | // RX complete interrupt + RB_ETH_EIE_TXIE | // TX complete interrupt + RB_ETH_EIE_LINKIE | // Link status change interrupt + RB_ETH_EIE_TXERIE | // TX error interrupt (collision, underrun, etc.) + RB_ETH_EIE_RXERIE | // RX error interrupt (CRC error, overrun, etc.) + RB_ETH_EIE_R_EN50; // Built-in 50ohm impedance matching resistor enable + + NVIC_EnableIRQ( ETH_IRQn ); + + return 0; +} + +int eth_send_packet( const uint8_t *packet, uint16_t length ) +{ + if ( tx_queue_is_full( &g_eth_state.tx_q ) ) + { +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.tx_dropped++; +#endif + return -1; + } + + // reserve our slot in the queue + uint32_t idx = g_eth_state.tx_q.head; + tx_queue_produce( &g_eth_state.tx_q ); + + uint8_t *tx_buf = (uint8_t *)g_dma_tx_descs[idx].Buffer1Addr; + memcpy( tx_buf, packet, length ); + g_dma_tx_descs[idx].Status = length; + + tx_start_if_possible(); + return 0; +} + +uint8_t *eth_get_tx_buffer( uint16_t *max_length ) +{ + if ( tx_queue_is_full( &g_eth_state.tx_q ) ) + { + return NULL; + } + + if ( max_length ) + { + *max_length = ETH_TX_BUF_SIZE; + } + + uint32_t idx = g_eth_state.tx_q.head; + return (uint8_t *)g_dma_tx_descs[idx].Buffer1Addr; +} + + +int eth_send_packet_zerocopy( uint16_t length ) +{ + uint32_t idx = g_eth_state.tx_q.head; + g_dma_tx_descs[idx].Status = length; + + tx_queue_produce( &g_eth_state.tx_q ); + tx_start_if_possible(); + + return 0; +} + +const uint8_t *eth_get_rx_packet( uint16_t *length ) +{ + if ( !length ) + { + return NULL; + } + + uint32_t tail_idx = g_eth_state.rx_tail_idx; + + if ( g_dma_rx_descs[tail_idx].Status & ETH_DMARxDesc_OWN ) + { + return NULL; // no packet ready + } + + // extract packet length from descriptor status field + *length = ( g_dma_rx_descs[tail_idx].Status & ETH_DMARxDesc_FL ) >> ETH_DMARxDesc_FrameLengthShift; + + // return pointer to packet buffer + return (const uint8_t *)g_dma_rx_descs[tail_idx].Buffer1Addr; +} + +void eth_release_rx_packet( void ) +{ +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.rx_packets++; +#endif + uint32_t tail_idx = g_eth_state.rx_tail_idx; + + // give descriptor back to DMA + g_dma_rx_descs[tail_idx].Status = ETH_DMARxDesc_OWN; + + // advance to next descriptor in ring + g_eth_state.rx_tail_idx = ( tail_idx + 1 ) % ETH_RX_BUF_COUNT; +} + + +void eth_process_rx( void ) +{ + uint16_t length; + const uint8_t *packet; + + // process all packets that DMA has released + while ( ( packet = eth_get_rx_packet( &length ) ) != NULL ) + { + // deliver to user callback if registered + if ( g_eth_state.rx_callback ) + { + g_eth_state.rx_callback( packet, length ); + } + + eth_release_rx_packet(); + } +} + +void eth_poll_link( void ) +{ + if ( g_eth_state.link_irq_flag ) + { + g_eth_state.link_irq_flag = false; + g_eth_state.negotiation_poll_count = 0; + } + + uint16_t bmsr = phy_read_reg( PHY_BMSR ); + uint16_t anlpar = phy_read_reg( PHY_ANLPAR ); + + bool phy_link = ( bmsr & PHY_BMSR_LINK_STATUS ) != 0; + bool an_complete = ( bmsr & PHY_BMSR_AN_COMPLETE ) != 0; + + switch ( g_eth_state.link_state ) + { + + case LINK_STATE_DOWN: + if ( phy_link && an_complete && ( anlpar != 0 ) ) + { + // valid link with successful negotiation + eth_link_up_handler(); + } + else if ( phy_link && an_complete && ( anlpar == 0 ) ) + { + // false auto-negotiation completion (ANLPAR=0) + // reset PHY and try different mode + g_eth_state.link_state = LINK_STATE_NEGOTIATING; + g_eth_state.negotiation_poll_count = 0; + phy_write_reg( PHY_BMCR, PHY_BMCR_RESET ); + Delay_Us( 100 ); + phy_try_next_mdix_mode(); + } + break; + + case LINK_STATE_NEGOTIATING: + if ( phy_link && an_complete && ( anlpar != 0 ) ) + { + // negotiation succeeded + eth_link_up_handler(); + } + else if ( phy_link && an_complete && ( anlpar == 0 ) ) + { + // still no valid partner response after negotiation + g_eth_state.negotiation_poll_count++; + + if ( g_eth_state.negotiation_poll_count >= 10 ) + { + // try next MDI/MDIX mode after 10 polls + g_eth_state.negotiation_poll_count = 0; + phy_write_reg( PHY_BMCR, PHY_BMCR_RESET ); + Delay_Us( 100 ); + phy_try_next_mdix_mode(); + } + } + else if ( !phy_link ) + { + // link went down during negotiation + g_eth_state.link_state = LINK_STATE_DOWN; + g_eth_state.negotiation_poll_count = 0; + } + break; + + case LINK_STATE_UP: + if ( !phy_link ) + { + // link went down + eth_link_down_handler(); + phy_start_autoneg( MDIX_MODE_AUTO ); + } + else if ( g_eth_state.polarity_detect_active ) + { + // monitor for polarity issues + if ( g_eth_state.crc_error_count >= 3 ) + { + phy_fix_polarity(); + g_eth_state.polarity_detect_active = false; + ETH10M->ERXFCON &= ~RB_ETH_ERXFCON_CRCEN; + } + } + break; + } +} + +void eth_get_mac_address( uint8_t *mac_addr ) +{ + if ( mac_addr ) + { + memcpy( mac_addr, g_eth_state.mac_addr, ETH_MAC_ADDR_LEN ); + } +} + +bool eth_is_link_up( void ) +{ + return g_eth_state.link_state == LINK_STATE_UP; +} + +#ifdef ETH_ENABLE_STATS +void eth_get_stats( eth_stats_t *stats ) +{ + if ( stats ) + { + *stats = g_eth_state.stats; + } +} + +void eth_reset_stats( void ) +{ + memset( &g_eth_state.stats, 0, sizeof( eth_stats_t ) ); +} +#endif + +void ETH_IRQHandler( void ) __attribute__( ( interrupt ) ) __attribute__( ( used ) ); +void ETH_IRQHandler( void ) +{ + uint32_t flags = ETH10M->EIR; + + uint32_t head_idx = g_eth_state.rx_head_idx; + + if ( flags & RB_ETH_EIR_RXIF ) + { + ETH10M->EIR = RB_ETH_EIR_RXIF; // clear interrupt flag + + // check if DMA still owns the current head descriptor + if ( g_dma_rx_descs[head_idx].Status & ETH_DMARxDesc_OWN ) + { + uint16_t rx_len = ETH10M->ERXLN; + + if ( rx_len == 0 || rx_len > ETH_RX_BUF_SIZE ) + { +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.rx_errors++; +#endif + return; + } + + // check for RX errors + uint8_t estat = ETH10M->ESTAT; + const uint8_t error_mask = + RB_ETH_ESTAT_BUFER | RB_ETH_ESTAT_RXCRCER | RB_ETH_ESTAT_RXNIBBLE | RB_ETH_ESTAT_RXMORE; + + if ( estat & error_mask ) + { + // track CRC errors specifically for polarity detection + if ( ( estat & RB_ETH_ESTAT_RXCRCER ) && g_eth_state.polarity_detect_active ) + { + g_eth_state.crc_error_count++; + } + +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.rx_errors++; +#endif + return; // discard + } + + // check if next descriptor is available + uint32_t next_idx = ( head_idx + 1 ) % ETH_RX_BUF_COUNT; + + if ( !( g_dma_rx_descs[next_idx].Status & ETH_DMARxDesc_OWN ) ) + { + // ring full +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.rx_dropped++; +#endif + } + else + { + // packet is ready and we have space + // mark current descriptor as ready for CPU processing + g_dma_rx_descs[head_idx].Status &= ~ETH_DMARxDesc_OWN; + + // add frame metadata + g_dma_rx_descs[head_idx].Status |= ( ETH_DMARxDesc_FS | ETH_DMARxDesc_LS | // Single segment frame + ( ETH10M->ERXLN << ETH_DMARxDesc_FrameLengthShift ) ); + + // advance head to next descriptor for DMA + g_eth_state.rx_head_idx = next_idx; + + // tell MAC where to write next packet + ETH10M->ERXST = g_dma_rx_descs[next_idx].Buffer1Addr; + + // signal activity + if ( g_eth_state.activity_callback ) + { + g_eth_state.activity_callback(); + } + } + } + } + + if ( flags & RB_ETH_EIR_TXIF ) + { + ETH10M->EIR = RB_ETH_EIR_TXIF; + + if ( !tx_queue_is_empty( &g_eth_state.tx_q ) ) + { +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.tx_packets++; +#endif + tx_queue_consume( &g_eth_state.tx_q ); + } + + tx_start_if_possible(); + + // signal activity + if ( g_eth_state.activity_callback ) + { + g_eth_state.activity_callback(); + } + } + + if ( flags & RB_ETH_EIR_TXERIF ) + { + ETH10M->EIR = RB_ETH_EIR_TXERIF; +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.tx_errors++; +#endif + + if ( !tx_queue_is_empty( &g_eth_state.tx_q ) ) + { + tx_queue_consume( &g_eth_state.tx_q ); + } + tx_start_if_possible(); + } + + if ( flags & RB_ETH_EIR_RXERIF ) + { + ETH10M->EIR = RB_ETH_EIR_RXERIF; + ETH10M->ECON1 |= RB_ETH_ECON1_RXEN; +#ifdef ETH_ENABLE_STATS + g_eth_state.stats.rx_errors++; +#endif + } + + if ( flags & RB_ETH_EIR_LINKIF ) + { + g_eth_state.link_irq_flag = true; + ETH10M->EIR = RB_ETH_EIR_LINKIF; + } +} + +#endif // CH32V208_ETH_IMPLEMENTATION diff --git a/inc/extralibs/ch32v307gigabit.h b/inc/extralibs/ch32v307gigabit.h index 4af9137..60ca030 100644 --- a/inc/extralibs/ch32v307gigabit.h +++ b/inc/extralibs/ch32v307gigabit.h @@ -2,7 +2,7 @@ #define _CH32V307GIGABIT_H /* This file is written against the RTL8211E - */ +*/ // #define CH32V307GIGABIT_MCO25 1 // #define CH32V307GIGABIT_PHYADDRESS 0 @@ -34,515 +34,515 @@ // ETH DMA structure definition (From ch32v30x_eth.c typedef struct { - uint32_t volatile Status; /* Status */ - uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ - uint32_t Buffer1Addr; /* Buffer1 address pointer */ - uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ + uint32_t volatile Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ } ETH_DMADESCTypeDef; // You must provide: -void ch32v307ethHandleReconfig(int link, int speed, int duplex); +void ch32v307ethHandleReconfig( int link, int speed, int duplex ); // Return non-zero to suppress OWN return (for if you are still holding onto the buffer) -int ch32v307ethInitHandlePacket(uint8_t *data, int frame_length, ETH_DMADESCTypeDef *dmadesc); +int ch32v307ethInitHandlePacket( uint8_t * data, int frame_length, ETH_DMADESCTypeDef * dmadesc ); -void ch32v307ethInitHandleTXC(void); +void ch32v307ethInitHandleTXC( void ); // This library provides: -static void ch32v307ethGetMacInUC(uint8_t *mac); -static int ch32v307ethInit(void); -static int ch32v307ethTransmitStatic(uint8_t *buffer, uint32_t length, int enable_txc); // Does not copy. -static int ch32v307ethTickPhy(void); +static void ch32v307ethGetMacInUC( uint8_t * mac ); +static int ch32v307ethInit( void ); +static int ch32v307ethTransmitStatic(uint8_t * buffer, uint32_t length, int enable_txc); // Does not copy. +static int ch32v307ethTickPhy( void ); // Data pursuent to ethernet. -uint8_t ch32v307eth_mac[6] = {0}; -uint16_t ch32v307eth_phyid = 0; // 0xc916 = RTL8211FS / 0xc915 = RTL8211E-VB -ETH_DMADESCTypeDef ch32v307eth_DMARxDscrTab[CH32V307GIGABIT_RXBUFNB] __attribute__((aligned(4))); // MAC receive descriptor, 4-byte aligned -ETH_DMADESCTypeDef ch32v307eth_DMATxDscrTab[CH32V307GIGABIT_TXBUFNB] __attribute__((aligned(4))); // MAC send descriptor, 4-byte aligned -uint8_t ch32v307eth_MACRxBuf[CH32V307GIGABIT_RXBUFNB * CH32V307GIGABIT_BUFFSIZE] __attribute__((aligned(4))); // MAC receive buffer, 4-byte aligned -ETH_DMADESCTypeDef *pDMARxGet; -ETH_DMADESCTypeDef *pDMATxSet; +uint8_t ch32v307eth_mac[6] = { 0 }; +uint16_t ch32v307eth_phyid = 0; // 0xc916 = RTL8211FS / 0xc915 = RTL8211E-VB +ETH_DMADESCTypeDef ch32v307eth_DMARxDscrTab[CH32V307GIGABIT_RXBUFNB] __attribute__((aligned(4))); // MAC receive descriptor, 4-byte aligned +ETH_DMADESCTypeDef ch32v307eth_DMATxDscrTab[CH32V307GIGABIT_TXBUFNB] __attribute__((aligned(4))); // MAC send descriptor, 4-byte aligned +uint8_t ch32v307eth_MACRxBuf[CH32V307GIGABIT_RXBUFNB*CH32V307GIGABIT_BUFFSIZE] __attribute__((aligned(4))); // MAC receive buffer, 4-byte aligned +ETH_DMADESCTypeDef * pDMARxGet; +ETH_DMADESCTypeDef * pDMATxSet; + // Internal functions -static int ch32v307ethPHYRegWrite(uint32_t reg, uint32_t val); -static int ch32v307ethPHYRegAsyncRead(int reg, int *value); -static int ch32v307ethPHYRegRead(uint32_t reg); +static int ch32v307ethPHYRegWrite( uint32_t reg, uint32_t val ); +static int ch32v307ethPHYRegAsyncRead( int reg, int * value ); +static int ch32v307ethPHYRegRead( uint32_t reg ); -static int ch32v307ethPHYRegAsyncRead(int reg, int *value) +static int ch32v307ethPHYRegAsyncRead( int reg, int * value ) { - static uint8_t reg_request_count = 0; + static uint8_t reg_request_count = 0; - uint32_t miiar = ETH->MACMIIAR; - if (miiar & ETH_MACMIIAR_MB) - { - return -1; - } - if (((miiar & ETH_MACMIIAR_MR) >> 6) != reg || reg_request_count < 2) - { - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | - ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA - (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | - (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; - reg_request_count++; - return -1; - } - reg_request_count = 0; - *value = ETH->MACMIIDR; - ETH->MACMIIAR |= ETH_MACMIIAR_MR; // Poison register. - return 0; + uint32_t miiar = ETH->MACMIIAR; + if( miiar & ETH_MACMIIAR_MB ) + { + return -1; + } + if( ( ( miiar & ETH_MACMIIAR_MR ) >> 6 ) != reg || reg_request_count < 2 ) + { + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | + ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA + (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | + (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; + reg_request_count++; + return -1; + } + reg_request_count = 0; + *value = ETH->MACMIIDR; + ETH->MACMIIAR |= ETH_MACMIIAR_MR; // Poison register. + return 0; } static int ch32v307ethTickPhy(void) { - int speed, linked, duplex; - const int reg = (ch32v307eth_phyid == 0xc916) ? 0x1a : 0x11; // PHYSR (different on each part) - int miidr; - if (ch32v307ethPHYRegAsyncRead(reg, &miidr)) return -1; + int speed, linked, duplex; + const int reg = (ch32v307eth_phyid == 0xc916) ? 0x1a : 0x11; // PHYSR (different on each part) + int miidr; + if( ch32v307ethPHYRegAsyncRead( reg, &miidr ) ) return -1; - printf("REG: %02x / %04x / %04x\n", reg, miidr, ch32v307eth_phyid); + printf( "REG: %02x / %04x / %04x\n", reg, miidr, ch32v307eth_phyid ); - if (reg == 0x1a) - { - speed = ((miidr >> 4) & 3); - linked = ((miidr >> 2) & 1); - duplex = ((miidr >> 3) & 1); - } - else - { - speed = ((miidr >> 14) & 3); - linked = ((miidr >> 10) & 1); - duplex = ((miidr >> 13) & 1); - } + if( reg == 0x1a ) + { + speed = ((miidr>>4)&3); + linked = ((miidr>>2)&1); + duplex = ((miidr>>3)&1); + } + else + { + speed = ((miidr>>14)&3); + linked = ((miidr>>10)&1); + duplex = ((miidr>>13)&1); + } - printf("LINK INFO: %d %d %d\n", speed, linked, duplex); - if (linked) - { - uint32_t oldmaccr = ETH->MACCR; - uint32_t newmaccr = (oldmaccr & ~((1 << 11) | (3 << 14))) | (speed << 14) | (duplex << 11); - if (newmaccr != oldmaccr) - { - ETH->MACCR = newmaccr; - ch32v307ethHandleReconfig(linked, speed, duplex); - return 1; - } - } - return 0; + printf( "LINK INFO: %d %d %d\n", speed, linked, duplex ); + if( linked ) + { + uint32_t oldmaccr = ETH->MACCR; + uint32_t newmaccr = (oldmaccr & ~( ( 1<<11 ) | (3<<14) ) ) | (speed<<14) | ( duplex<<11); + if( newmaccr != oldmaccr ) + { + ETH->MACCR = newmaccr; + ch32v307ethHandleReconfig( linked, speed, duplex ); + return 1; + } + } + return 0; } + // Based on ETH_WritePHYRegister -static int ch32v307ethPHYRegWrite(uint32_t reg, uint32_t val) +static int ch32v307ethPHYRegWrite( uint32_t reg, uint32_t val ) { - ETH->MACMIIDR = val; - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | - (((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11)) | // ETH_MACMIIAR_PA - (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | - ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; + ETH->MACMIIDR = val; + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | + (((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11)) | // ETH_MACMIIAR_PA + (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | + ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; - uint32_t timeout = 0x100000; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) && --timeout) - ; + uint32_t timeout = 0x100000; + while( ( ETH->MACMIIAR & ETH_MACMIIAR_MB ) && --timeout ); - // If timeout = 0, is an error. - return timeout ? 0 : -1; + // If timeout = 0, is an error. + return timeout ? 0 : -1; } -static int ch32v307ethPHYRegRead(uint32_t reg) +static int ch32v307ethPHYRegRead( uint32_t reg ) { - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | - ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA - (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | - (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42 /* = 0, per 27.1.8.1.4 */ | + ((uint32_t)CH32V307GIGABIT_PHYADDRESS << 11) | // ETH_MACMIIAR_PA + (((uint32_t)reg << 6) & ETH_MACMIIAR_MR) | + (0 /*!ETH_MACMIIAR_MW*/) | ETH_MACMIIAR_MB; - uint32_t timeout = 0x100000; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) && --timeout) - ; + uint32_t timeout = 0x100000; + while( ( ETH->MACMIIAR & ETH_MACMIIAR_MB ) && --timeout ); - // If timeout = 0, is an error. - return timeout ? ETH->MACMIIDR : -1; + // If timeout = 0, is an error. + return timeout ? ETH->MACMIIDR : -1; } -static void ch32v307ethGetMacInUC(uint8_t *mac) + +static void ch32v307ethGetMacInUC( uint8_t * mac ) { - // Mac is backwards. - const uint8_t *macaddr = (const uint8_t *)(ROM_CFG_USERADR_ID + 5); - for (int i = 0; i < 6; i++) - { - mac[i] = *(macaddr--); - } + // Mac is backwards. + const uint8_t *macaddr = (const uint8_t *)(ROM_CFG_USERADR_ID+5); + for( int i = 0; i < 6; i++ ) + { + mac[i] = *(macaddr--); + } } -static int ch32v307ethInit(void) +static int ch32v307ethInit( void ) { - int i; + int i; #ifdef CH32V307GIGABIT_PHY_RSTB - funPinMode(CH32V307GIGABIT_PHY_RSTB, GPIO_CFGLR_OUT_50Mhz_PP); // PHY_RSTB (For reset) - funDigitalWrite(CH32V307GIGABIT_PHY_RSTB, FUN_LOW); + funPinMode( CH32V307GIGABIT_PHY_RSTB, GPIO_CFGLR_OUT_50Mhz_PP ); //PHY_RSTB (For reset) + funDigitalWrite( CH32V307GIGABIT_PHY_RSTB, FUN_LOW ); #endif - // Configure strapping. - funPinMode(PA1, GPIO_CFGLR_IN_PUPD); // GMII_RXD3 - funPinMode(PA0, GPIO_CFGLR_IN_PUPD); // GMII_RXD2 - funPinMode(PC3, GPIO_CFGLR_IN_PUPD); // GMII_RXD1 - funPinMode(PC2, GPIO_CFGLR_IN_PUPD); // GMII_RXD0 - funDigitalWrite(PA1, FUN_HIGH); - funDigitalWrite(PA0, FUN_HIGH); - funDigitalWrite(PC3, FUN_HIGH); // No TX Delay - funDigitalWrite(PC2, FUN_HIGH); + // Configure strapping. + funPinMode( PA1, GPIO_CFGLR_IN_PUPD ); // GMII_RXD3 + funPinMode( PA0, GPIO_CFGLR_IN_PUPD ); // GMII_RXD2 + funPinMode( PC3, GPIO_CFGLR_IN_PUPD ); // GMII_RXD1 + funPinMode( PC2, GPIO_CFGLR_IN_PUPD ); // GMII_RXD0 + funDigitalWrite( PA1, FUN_HIGH ); + funDigitalWrite( PA0, FUN_HIGH ); + funDigitalWrite( PC3, FUN_HIGH ); // No TX Delay + funDigitalWrite( PC2, FUN_HIGH ); - // Pull-up MDIO - funPinMode(PD9, GPIO_CFGLR_OUT_50Mhz_PP); // Pull-up control (DO NOT CHECK IN, ADD RESISTOR) - funDigitalWrite(PD9, FUN_HIGH); + // Pull-up MDIO + funPinMode( PD9, GPIO_CFGLR_OUT_50Mhz_PP ); //Pull-up control (DO NOT CHECK IN, ADD RESISTOR) + funDigitalWrite( PD9, FUN_HIGH ); - // Will be required later. - RCC->APB2PCENR |= RCC_APB2Periph_AFIO; + // Will be required later. + RCC->APB2PCENR |= RCC_APB2Periph_AFIO; - // https://cnlohr.github.io/microclockoptimizer/?chipSelect=ch32vx05_7%2Cd8c&HSI=1,8&HSE=0,8&PREDIV2=1,1&PLL2CLK=1,7&PLL2VCO=0,72&PLL3CLK=1,1&PLL3VCO=0,100&PREDIV1SRC=1,0&PREDIV1=1,2&PLLSRC=1,0&PLL=0,4&PLLVCO=1,144&SYSCLK=1,2& - // Clock Tree: - // 8MHz Input - // PREDIV2 = 2 (1 in register) = 4MHz - // PLL2 = 9 (7 in register) = 36MHz / PLL2VCO = 72MHz - // PLL3CLK = 12.5 (1 in register) = 50MHz = 100MHz VCO - // PREDIV1SRC = HSE (1 in register) = 8MHz - // PREDIV1 = 2 (1 in register). - // PLLSRC = PREDIV1 (0 in register) = 4MHz - // PLL = 18 (0 in register) = 72MHz - // PLLVCO = 144MHz - // SYSCLK = PLLVCO = 144MHz - // Use EXT_125M (ETH1G_SRC) + // https://cnlohr.github.io/microclockoptimizer/?chipSelect=ch32vx05_7%2Cd8c&HSI=1,8&HSE=0,8&PREDIV2=1,1&PLL2CLK=1,7&PLL2VCO=0,72&PLL3CLK=1,1&PLL3VCO=0,100&PREDIV1SRC=1,0&PREDIV1=1,2&PLLSRC=1,0&PLL=0,4&PLLVCO=1,144&SYSCLK=1,2& + // Clock Tree: + // 8MHz Input + // PREDIV2 = 2 (1 in register) = 4MHz + // PLL2 = 9 (7 in register) = 36MHz / PLL2VCO = 72MHz + // PLL3CLK = 12.5 (1 in register) = 50MHz = 100MHz VCO + // PREDIV1SRC = HSE (1 in register) = 8MHz + // PREDIV1 = 2 (1 in register). + // PLLSRC = PREDIV1 (0 in register) = 4MHz + // PLL = 18 (0 in register) = 72MHz + // PLLVCO = 144MHz + // SYSCLK = PLLVCO = 144MHz + // Use EXT_125M (ETH1G_SRC) - // Switch processor back to HSI so we don't eat dirt. - RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI; + // Switch processor back to HSI so we don't eat dirt. + RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI; - // Setup clock tree. - RCC->CFGR2 |= - (1 << RCC_PREDIV2_OFFSET) | // PREDIV = /2; Prediv Freq = 4MHz - (1 << RCC_PLL3MUL_OFFSET) | // PLL3 = x12.5 (PLL3 = 50MHz) - (2 << RCC_ETH1GSRC_OFFSET) | // External source for RGMII - (7 << RCC_PLL2MUL_OFFSET) | // PLL2 = x9 (PLL2 = 36MHz) - (1 << RCC_PREDIV1_OFFSET) | // PREDIV1 = /2; Prediv freq = 50MHz - 0; + // Setup clock tree. + RCC->CFGR2 |= + (1<CTLR |= RCC_PLL3ON | RCC_PLL2ON; - int timeout; + // Power on PLLs + RCC->CTLR |= RCC_PLL3ON | RCC_PLL2ON; + int timeout; - for (timeout = 10000; timeout > 0; timeout--) - if (RCC->CTLR & RCC_PLL3RDY) break; - if (timeout == 0) return -5; - for (timeout = 10000; timeout > 0; timeout--) - if (RCC->CTLR & RCC_PLL2RDY) break; - if (timeout == 0) return -6; + for( timeout = 10000; timeout > 0; timeout--) if (RCC->CTLR & RCC_PLL3RDY) break; + if( timeout == 0 ) return -5; + for( timeout = 10000; timeout > 0; timeout--) if (RCC->CTLR & RCC_PLL2RDY) break; + if( timeout == 0 ) return -6; - // PLL = x18 (0 in register) - RCC->CFGR0 = (RCC->CFGR0 & ~(0xf << 18)) | 0; - RCC->CTLR |= RCC_PLLON; + // PLL = x18 (0 in register) + RCC->CFGR0 = ( RCC->CFGR0 & ~(0xf<<18)) | 0; + RCC->CTLR |= RCC_PLLON; - for (timeout = 10000; timeout > 0; timeout--) - if (RCC->CTLR & RCC_PLLRDY) break; - if (timeout == 0) return -7; + for( timeout = 10000; timeout > 0; timeout--) if (RCC->CTLR & RCC_PLLRDY) break; + if( timeout == 0 ) return -7; - // Switch to PLL. + // Switch to PLL. #ifdef CH32V307GIGABIT_MCO25 - RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL | (9 << 24); // And output clock on PA8 + RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL | (9<<24); // And output clock on PA8 #else - RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL; + RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL; #endif - // For clock in. - funPinMode(PB1, GPIO_CFGLR_IN_FLOAT); // GMII_CLK125 + // For clock in. + funPinMode( PB1, GPIO_CFGLR_IN_FLOAT ); //GMII_CLK125 - RCC->CFGR2 |= RCC_ETH1G_125M_EN; // Enable 125MHz clock. + RCC->CFGR2 |= RCC_ETH1G_125M_EN; // Enable 125MHz clock. - // Power on and reset. - RCC->AHBPCENR |= RCC_ETHMACEN | RCC_ETHMACTXEN | RCC_ETHMACRXEN; - RCC->AHBRSTR |= RCC_ETHMACRST; - RCC->AHBRSTR &= ~RCC_ETHMACRST; + // Power on and reset. + RCC->AHBPCENR |= RCC_ETHMACEN | RCC_ETHMACTXEN | RCC_ETHMACRXEN; + RCC->AHBRSTR |= RCC_ETHMACRST; + RCC->AHBRSTR &=~RCC_ETHMACRST; - ETH->DMABMR |= ETH_DMABMR_SR; + ETH->DMABMR |= ETH_DMABMR_SR; - // Wait for reset to complete. - for (timeout = 10000; timeout > 0 && (ETH->DMABMR & ETH_DMABMR_SR); timeout--) - { - Delay_Us(10); - } + // Wait for reset to complete. + for( timeout = 10000; timeout > 0 && (ETH->DMABMR & ETH_DMABMR_SR); timeout-- ) + { + Delay_Us(10); + } - // Use RGMII - EXTEN->EXTEN_CTR |= EXTEN_ETH_RGMII_SEL; // EXTEN_ETH_RGMII_SEL; + // Use RGMII + EXTEN->EXTEN_CTR |= EXTEN_ETH_RGMII_SEL; //EXTEN_ETH_RGMII_SEL; - funPinMode(PB13, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_MDIO - funPinMode(PB12, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_MDC + funPinMode( PB13, GPIO_CFGLR_OUT_50Mhz_AF_PP ); //GMII_MDIO + funPinMode( PB12, GPIO_CFGLR_OUT_50Mhz_AF_PP ); //GMII_MDC - // For clock output to Ethernet module. - funPinMode(PA8, GPIO_CFGLR_OUT_50Mhz_AF_PP); // PHY_CKTAL + // For clock output to Ethernet module. + funPinMode( PA8, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // PHY_CKTAL - // Release PHY from reset. + // Release PHY from reset. #ifdef CH32V307GIGABIT_PHY_RSTB - funDigitalWrite(CH32V307GIGABIT_PHY_RSTB, FUN_HIGH); + funDigitalWrite( CH32V307GIGABIT_PHY_RSTB, FUN_HIGH ); #endif - Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 23ms (But only on the RTL8211FS) None is needed on the RTL8211E + Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 23ms (But only on the RTL8211FS) None is needed on the RTL8211E - funPinMode(PB0, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD3 - funPinMode(PC5, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD2 - funPinMode(PC4, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD1 - funPinMode(PA7, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXD0 - funPinMode(PA3, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXCTL - funPinMode(PA2, GPIO_CFGLR_OUT_50Mhz_AF_PP); // GMII_TXC - funPinMode(PA1, GPIO_CFGLR_IN_PUPD); // GMII_RXD3 - funPinMode(PA0, GPIO_CFGLR_IN_PUPD); // GMII_RXD2 - funPinMode(PC3, GPIO_CFGLR_IN_PUPD); // GMII_RXD1 - funPinMode(PC2, GPIO_CFGLR_IN_PUPD); // GMII_RXD0 - funPinMode(PC1, GPIO_CFGLR_IN_PUPD); // GMII_RXCTL - funPinMode(PC0, GPIO_CFGLR_IN_FLOAT); // GMII_RXC + funPinMode( PB0, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD3 + funPinMode( PC5, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD2 + funPinMode( PC4, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD1 + funPinMode( PA7, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXD0 + funPinMode( PA3, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXCTL + funPinMode( PA2, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // GMII_TXC + funPinMode( PA1, GPIO_CFGLR_IN_PUPD ); // GMII_RXD3 + funPinMode( PA0, GPIO_CFGLR_IN_PUPD ); // GMII_RXD2 + funPinMode( PC3, GPIO_CFGLR_IN_PUPD ); // GMII_RXD1 + funPinMode( PC2, GPIO_CFGLR_IN_PUPD ); // GMII_RXD0 + funPinMode( PC1, GPIO_CFGLR_IN_PUPD ); // GMII_RXCTL + funPinMode( PC0, GPIO_CFGLR_IN_FLOAT ); // GMII_RXC - funDigitalWrite(PA1, FUN_HIGH); // SELGRV = 3.3V - funDigitalWrite(PA0, FUN_HIGH); // TXDelay = 1 - funDigitalWrite(PC3, FUN_HIGH); // AN[0] = 1 - funDigitalWrite(PC2, FUN_HIGH); // AN[1] = 1 - funDigitalWrite(PC1, FUN_LOW); // PHYAD[0] + funDigitalWrite( PA1, FUN_HIGH ); // SELGRV = 3.3V + funDigitalWrite( PA0, FUN_HIGH ); // TXDelay = 1 + funDigitalWrite( PC3, FUN_HIGH ); // AN[0] = 1 + funDigitalWrite( PC2, FUN_HIGH ); // AN[1] = 1 + funDigitalWrite( PC1, FUN_LOW ); // PHYAD[0] - // Configure MDC/MDIO - // Conflicting notes - some say /42, others don't. - ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42; + // Configure MDC/MDIO + // Conflicting notes - some say /42, others don't. + ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42; - // Update MACCR - ETH->MACCR = - (CH32V307GIGABIT_CFG_CLOCK_DELAY << 29) | // No clock delay - (0 << 23) | // Max RX = 2kB (Revisit if looking into jumbo frames) - (0 << 22) | // Max TX = 2kB (Revisit if looking into jumbo frames) - (0 << 21) | // Rated Drive (instead of energy savings mode) (10M PHY only) - (1 << 20) | // Bizarre re-use of termination resistor terminology? (10M PHY Only) - (0 << 17) | // IFG = 0, 96-bit guard time. - (0 << 14) | // FES = 2 = GBE, 1=100MBit/s (UNSET TO START) - (0 << 12) | // Self Loop = 0 - (0 << 11) | // Full-Duplex Mode (UNSET TO START) - (1 << 10) | // IPCO = 1, Check TCP, UDP, ICMP header checksums. - (1 << 7) | // APCS (automatically strip frames) - (1 << 3) | // TE (Transmit enable!) - (1 << 2) | // RE (Receive Enable) - (CH32V307GIGABIT_CFG_CLOCK_PHASE << 1) | // TCF = 0 (Potentailly change if clocking is wrong) - 0; + // Update MACCR + ETH->MACCR = + ( CH32V307GIGABIT_CFG_CLOCK_DELAY << 29 ) | // No clock delay + ( 0 << 23 ) | // Max RX = 2kB (Revisit if looking into jumbo frames) + ( 0 << 22 ) | // Max TX = 2kB (Revisit if looking into jumbo frames) + ( 0 << 21 ) | // Rated Drive (instead of energy savings mode) (10M PHY only) + ( 1 << 20 ) | // Bizarre re-use of termination resistor terminology? (10M PHY Only) + ( 0 << 17 ) | // IFG = 0, 96-bit guard time. + ( 0 << 14 ) | // FES = 2 = GBE, 1=100MBit/s (UNSET TO START) + ( 0 << 12 ) | // Self Loop = 0 + ( 0 << 11 ) | // Full-Duplex Mode (UNSET TO START) + ( 1 << 10 ) | // IPCO = 1, Check TCP, UDP, ICMP header checksums. + ( 1 << 7 ) | // APCS (automatically strip frames) + ( 1 << 3 ) | // TE (Transmit enable!) + ( 1 << 2 ) | // RE (Receive Enable) + ( CH32V307GIGABIT_CFG_CLOCK_PHASE << 1 ) | // TCF = 0 (Potentailly change if clocking is wrong) + 0; - Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 19ms. + Delay_Ms(25); // Waiting for PHY to exit sleep. This is inconsistent at 19ms. - // Reset the physical layer - ch32v307ethPHYRegWrite(PHY_BCR, - PHY_Reset | - 1 << 12 | // Auto negotiate - 1 << 8 | // Duplex - 1 << 6 | // Speed Bit. - 0); + // Reset the physical layer + ch32v307ethPHYRegWrite( PHY_BCR, + PHY_Reset | + 1<<12 | // Auto negotiate + 1<<8 | // Duplex + 1<<6 | // Speed Bit. + 0 ); - // De-assert reset. - ch32v307ethPHYRegWrite(PHY_BCR, - 1 << 12 | // Auto negotiate - 1 << 8 | // Duplex - 1 << 6 | // Speed Bit. - 0); + // De-assert reset. + ch32v307ethPHYRegWrite( PHY_BCR, + 1<<12 | // Auto negotiate + 1<<8 | // Duplex + 1<<6 | // Speed Bit. + 0 ); - ch32v307ethPHYRegRead(0x03); - ch32v307eth_phyid = ch32v307ethPHYRegRead(0x03); // Read twice to be safe. - if (ch32v307eth_phyid == 0xc916) - ch32v307ethPHYRegWrite(0x1F, 0x0a43); // RTL8211FS needs page select. + ch32v307ethPHYRegRead( 0x03 ); + ch32v307eth_phyid = ch32v307ethPHYRegRead( 0x03 ); // Read twice to be safe. + if( ch32v307eth_phyid == 0xc916 ) + ch32v307ethPHYRegWrite( 0x1F, 0x0a43 ); // RTL8211FS needs page select. - ch32v307ethGetMacInUC(ch32v307eth_mac); + ch32v307ethGetMacInUC( ch32v307eth_mac ); - ETH->MACA0HR = (uint32_t)((ch32v307eth_mac[5] << 8) | ch32v307eth_mac[4]); - ETH->MACA0LR = (uint32_t)(ch32v307eth_mac[0] | (ch32v307eth_mac[1] << 8) | (ch32v307eth_mac[2] << 16) | (ch32v307eth_mac[3] << 24)); + ETH->MACA0HR = (uint32_t)((ch32v307eth_mac[5]<<8) | ch32v307eth_mac[4]); + ETH->MACA0LR = (uint32_t)(ch32v307eth_mac[0] | (ch32v307eth_mac[1]<<8) | (ch32v307eth_mac[2]<<16) | (ch32v307eth_mac[3]<<24)); - ETH->MACFFR = (uint32_t)(ETH_ReceiveAll_Disable | - ETH_SourceAddrFilter_Disable | - ETH_PassControlFrames_BlockAll | - ETH_BroadcastFramesReception_Enable | - ETH_DestinationAddrFilter_Normal | - ETH_PromiscuousMode_Disable | - ETH_MulticastFramesFilter_Perfect | - ETH_UnicastFramesFilter_Perfect); + ETH->MACFFR = (uint32_t)(ETH_ReceiveAll_Disable | + ETH_SourceAddrFilter_Disable | + ETH_PassControlFrames_BlockAll | + ETH_BroadcastFramesReception_Enable | + ETH_DestinationAddrFilter_Normal | + ETH_PromiscuousMode_Disable | + ETH_MulticastFramesFilter_Perfect | + ETH_UnicastFramesFilter_Perfect); - ETH->MACHTHR = (uint32_t)0; - ETH->MACHTLR = (uint32_t)0; - ETH->MACVLANTR = (uint32_t)(ETH_VLANTagComparison_16Bit); + ETH->MACHTHR = (uint32_t)0; + ETH->MACHTLR = (uint32_t)0; + ETH->MACVLANTR = (uint32_t)(ETH_VLANTagComparison_16Bit); - ETH->MACFCR = 0; // No pause frames. + ETH->MACFCR = 0; // No pause frames. - // Configure RX/TX chains. - ETH_DMADESCTypeDef *tdesc; - for (i = 0; i < CH32V307GIGABIT_TXBUFNB; i++) - { - tdesc = ch32v307eth_DMATxDscrTab + i; - tdesc->ControlBufferSize = 0; - tdesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC | ETH_DMATxDesc_FS; - tdesc->Buffer1Addr = (uint32_t)0; // Populate with data. - tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_TXBUFNB - 1) ? ((uint32_t)(ch32v307eth_DMATxDscrTab + i + 1)) : (uint32_t)ch32v307eth_DMATxDscrTab; - } - ETH->DMATDLAR = (uint32_t)ch32v307eth_DMATxDscrTab; - for (i = 0; i < CH32V307GIGABIT_RXBUFNB; i++) - { - tdesc = ch32v307eth_DMARxDscrTab + i; - tdesc->Status = ETH_DMARxDesc_OWN; - tdesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)CH32V307GIGABIT_BUFFSIZE; - tdesc->Buffer1Addr = (uint32_t)(&ch32v307eth_MACRxBuf[i * CH32V307GIGABIT_BUFFSIZE]); - tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_RXBUFNB - 1) ? (uint32_t)(ch32v307eth_DMARxDscrTab + i + 1) : (uint32_t)(ch32v307eth_DMARxDscrTab); - } - ETH->DMARDLAR = (uint32_t)ch32v307eth_DMARxDscrTab; + // Configure RX/TX chains. + ETH_DMADESCTypeDef *tdesc; + for(i = 0; i < CH32V307GIGABIT_TXBUFNB; i++) + { + tdesc = ch32v307eth_DMATxDscrTab + i; + tdesc->ControlBufferSize = 0; + tdesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC | ETH_DMATxDesc_FS; + tdesc->Buffer1Addr = (uint32_t)0; // Populate with data. + tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_TXBUFNB - 1) ? ((uint32_t)(ch32v307eth_DMATxDscrTab + i + 1)) : (uint32_t)ch32v307eth_DMATxDscrTab; + } + ETH->DMATDLAR = (uint32_t)ch32v307eth_DMATxDscrTab; + for(i = 0; i < CH32V307GIGABIT_RXBUFNB; i++) + { + tdesc = ch32v307eth_DMARxDscrTab + i; + tdesc->Status = ETH_DMARxDesc_OWN; + tdesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)CH32V307GIGABIT_BUFFSIZE; + tdesc->Buffer1Addr = (uint32_t)(&ch32v307eth_MACRxBuf[i * CH32V307GIGABIT_BUFFSIZE]); + tdesc->Buffer2NextDescAddr = (i < CH32V307GIGABIT_RXBUFNB - 1) ? (uint32_t)(ch32v307eth_DMARxDscrTab + i + 1) : (uint32_t)(ch32v307eth_DMARxDscrTab); + } + ETH->DMARDLAR = (uint32_t)ch32v307eth_DMARxDscrTab; - pDMARxGet = ch32v307eth_DMARxDscrTab; - pDMATxSet = ch32v307eth_DMATxDscrTab; + pDMARxGet = ch32v307eth_DMARxDscrTab; + pDMATxSet = ch32v307eth_DMATxDscrTab; - // Receive a good frame half interrupt mask. - // Receive CRC error frame half interrupt mask. - // For the future: Why do we want this? - ETH->MMCTIMR = ETH_MMCTIMR_TGFM; - ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM; + // Receive a good frame half interrupt mask. + // Receive CRC error frame half interrupt mask. + // For the future: Why do we want this? + ETH->MMCTIMR = ETH_MMCTIMR_TGFM; + ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM; - ETH->DMAIER = ETH_DMA_IT_NIS | // Normal interrupt enable. - ETH_DMA_IT_R | // Receive - ETH_DMA_IT_T | // Transmit - ETH_DMA_IT_AIS | // Abnormal interrupt - ETH_DMA_IT_RBU; // Receive buffer unavailable interrupt enable + ETH->DMAIER = ETH_DMA_IT_NIS | // Normal interrupt enable. + ETH_DMA_IT_R | // Receive + ETH_DMA_IT_T | // Transmit + ETH_DMA_IT_AIS | // Abnormal interrupt + ETH_DMA_IT_RBU; // Receive buffer unavailable interrupt enable - NVIC_EnableIRQ(ETH_IRQn); + NVIC_EnableIRQ( ETH_IRQn ); - // Actually enable receiving process. - ETH->DMAOMR = ETH_DMAOMR_SR | ETH_DMAOMR_ST | ETH_DMAOMR_TSF | ETH_DMAOMR_FEF; + // Actually enable receiving process. + ETH->DMAOMR = ETH_DMAOMR_SR | ETH_DMAOMR_ST | ETH_DMAOMR_TSF | ETH_DMAOMR_FEF; - return 0; + return 0; } -void ETH_IRQHandler(void) __attribute__((interrupt)); -void ETH_IRQHandler(void) +void ETH_IRQHandler( void ) __attribute__((interrupt)); +void ETH_IRQHandler( void ) { uint32_t int_sta; - do - { - int_sta = ETH->DMASR; - if ((int_sta & (ETH_DMA_IT_AIS | ETH_DMA_IT_NIS)) == 0) - { - break; - } + do + { + int_sta = ETH->DMASR; + if ( ( int_sta & ( ETH_DMA_IT_AIS | ETH_DMA_IT_NIS ) ) == 0 ) + { + break; + } - // Off nominal situations. - if (int_sta & ETH_DMA_IT_AIS) - { - // Receive buffer unavailable interrupt enable. - if (int_sta & ETH_DMA_IT_RBU) - { - ETH->DMASR = ETH_DMA_IT_RBU; - if ((INFO->CHIPID & 0xf0) == 0x10) - { - ((ETH_DMADESCTypeDef *)(((ETH_DMADESCTypeDef *)(ETH->DMACHRDR))->Buffer2NextDescAddr))->Status = ETH_DMARxDesc_OWN; - ETH->DMARPDR = 0; - } - } - ETH->DMASR = ETH_DMA_IT_AIS; - } + // Off nominal situations. + if (int_sta & ETH_DMA_IT_AIS) + { + // Receive buffer unavailable interrupt enable. + if (int_sta & ETH_DMA_IT_RBU) + { + ETH->DMASR = ETH_DMA_IT_RBU; + if((INFO->CHIPID & 0xf0) == 0x10) + { + ((ETH_DMADESCTypeDef *)(((ETH_DMADESCTypeDef *)(ETH->DMACHRDR))->Buffer2NextDescAddr))->Status = ETH_DMARxDesc_OWN; + ETH->DMARPDR = 0; + } + } + ETH->DMASR = ETH_DMA_IT_AIS; + } - // Nominal interrupts. - if (int_sta & ETH_DMA_IT_NIS) - { - if (int_sta & ETH_DMA_IT_R) - { - // Received a packet, normally. - // Status is in Table 27-17 Definitions of RDes0 - do - { - // XXX TODO: Is this a good place to acknowledge? REVISIT: Should this go lower? - // XXX TODO: Restructure this to allow for - ETH->DMASR = ETH_DMA_IT_R; + // Nominal interrupts. + if( int_sta & ETH_DMA_IT_NIS ) + { + if( int_sta & ETH_DMA_IT_R ) + { + // Received a packet, normally. + // Status is in Table 27-17 Definitions of RDes0 + do + { + // XXX TODO: Is this a good place to acknowledge? REVISIT: Should this go lower? + // XXX TODO: Restructure this to allow for + ETH->DMASR = ETH_DMA_IT_R; - uint32_t status = pDMARxGet->Status; - if (status & ETH_DMARxDesc_OWN) break; + uint32_t status = pDMARxGet->Status; + if( status & ETH_DMARxDesc_OWN ) break; - // We only have a valid packet in a specific situation. - // So, we take the status, then mask off the bits we care about - // And see if they're equal to the ones that need to be set/unset. - const uint32_t mask = - ETH_DMARxDesc_OWN | - ETH_DMARxDesc_LS | - ETH_DMARxDesc_ES | - ETH_DMARxDesc_FS; - const uint32_t eq = - 0 | - ETH_DMARxDesc_LS | - 0 | - ETH_DMARxDesc_FS; + // We only have a valid packet in a specific situation. + // So, we take the status, then mask off the bits we care about + // And see if they're equal to the ones that need to be set/unset. + const uint32_t mask = + ETH_DMARxDesc_OWN | + ETH_DMARxDesc_LS | + ETH_DMARxDesc_ES | + ETH_DMARxDesc_FS; + const uint32_t eq = + 0 | + ETH_DMARxDesc_LS | + 0 | + ETH_DMARxDesc_FS; - int suppress_own = 0; + int suppress_own = 0; - if ((status & mask) == eq) - { - int32_t frame_length = ((status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - if (frame_length > 0) - { - uint8_t *data = (uint8_t *)pDMARxGet->Buffer1Addr; - suppress_own = ch32v307ethInitHandlePacket(data, frame_length, pDMARxGet); - } - } - // Otherwise, Invalid Packet + if( ( status & mask ) == eq ) + { + int32_t frame_length = ((status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + if( frame_length > 0 ) + { + uint8_t * data = (uint8_t*)pDMARxGet->Buffer1Addr; + suppress_own = ch32v307ethInitHandlePacket( data, frame_length, pDMARxGet ); + } + } + // Otherwise, Invalid Packet - // Relinquish control back to underlying hardware. - if (!suppress_own) - pDMARxGet->Status = ETH_DMARxDesc_OWN; + // Relinquish control back to underlying hardware. + if( !suppress_own ) + pDMARxGet->Status = ETH_DMARxDesc_OWN; - // Tricky logic for figuring out the next packet. Originally - // discussed in ch32v30x_eth.c in ETH_DropRxPkt - if ((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - pDMARxGet = (ETH_DMADESCTypeDef *)(pDMARxGet->Buffer2NextDescAddr); - else - { - if ((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - pDMARxGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); - else - pDMARxGet = (ETH_DMADESCTypeDef *)((uint32_t)pDMARxGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } while (1); - } - if (int_sta & ETH_DMA_IT_T) - { - ch32v307ethInitHandleTXC(); - ETH->DMASR = ETH_DMA_IT_T; - } - ETH->DMASR = ETH_DMA_IT_NIS; - } - } while (1); + // Tricky logic for figuring out the next packet. Originally + // discussed in ch32v30x_eth.c in ETH_DropRxPkt + if((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + pDMARxGet = (ETH_DMADESCTypeDef *)(pDMARxGet->Buffer2NextDescAddr); + else + { + if((pDMARxGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + pDMARxGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + else + pDMARxGet = (ETH_DMADESCTypeDef *)((uint32_t)pDMARxGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } while( 1 ); + } + if( int_sta & ETH_DMA_IT_T ) + { + ch32v307ethInitHandleTXC(); + ETH->DMASR = ETH_DMA_IT_T; + } + ETH->DMASR = ETH_DMA_IT_NIS; + } + } while( 1 ); } -static int ch32v307ethTransmitStatic(uint8_t *buffer, uint32_t length, int enable_txc) +static int ch32v307ethTransmitStatic(uint8_t * buffer, uint32_t length, int enable_txc) { - // The official SDK waits until ETH_DMATxDesc_TTSS is set. - // This also provides a transmit timestamp, which could be - // used for PTP. - // But we don't want to do that. - // We just want to go. If anyone cares, they can check later. + // The official SDK waits until ETH_DMATxDesc_TTSS is set. + // This also provides a transmit timestamp, which could be + // used for PTP. + // But we don't want to do that. + // We just want to go. If anyone cares, they can check later. - if (pDMATxSet->Status & ETH_DMATxDesc_OWN) - { - ETH->DMATPDR = 0; - return -1; - } + if( pDMATxSet->Status & ETH_DMATxDesc_OWN ) + { + ETH->DMATPDR = 0; + return -1; + } pDMATxSet->ControlBufferSize = (length & ETH_DMATxDesc_TBS1); - pDMATxSet->Buffer1Addr = (uint32_t)buffer; + pDMATxSet->Buffer1Addr = (uint32_t)buffer; - // Status is in Table 27-12 "Definitions of TDes0 bits" - enable_txc = enable_txc ? ETH_DMATxDesc_IC : 0; - pDMATxSet->Status = - ETH_DMATxDesc_LS | // Last Segment (This is all you need to have to transmit) - ETH_DMATxDesc_FS | // First Segment (Beginning of transmission) - enable_txc | // Interrupt when complete - ETH_DMATxDesc_TCH | // Next Descriptor Address Valid - ETH_DMATxDesc_CIC_TCPUDPICMP_Full | // Do all header checksums. - ETH_DMATxDesc_OWN; // Own back to hardware + // Status is in Table 27-12 "Definitions of TDes0 bits" + enable_txc = enable_txc ? ETH_DMATxDesc_IC : 0; + pDMATxSet->Status = + ETH_DMATxDesc_LS | // Last Segment (This is all you need to have to transmit) + ETH_DMATxDesc_FS | // First Segment (Beginning of transmission) + enable_txc | // Interrupt when complete + ETH_DMATxDesc_TCH | // Next Descriptor Address Valid + ETH_DMATxDesc_CIC_TCPUDPICMP_Full | // Do all header checksums. + ETH_DMATxDesc_OWN; // Own back to hardware - pDMATxSet = (ETH_DMADESCTypeDef *)pDMATxSet->Buffer2NextDescAddr; + pDMATxSet = (ETH_DMADESCTypeDef*)pDMATxSet->Buffer2NextDescAddr; - ETH->DMASR = ETH_DMASR_TBUS; // This resets the transmit process (or "starts" it) - ETH->DMATPDR = 0; + ETH->DMASR = ETH_DMASR_TBUS; // This resets the transmit process (or "starts" it) + ETH->DMATPDR = 0; - return 0; + return 0; } + #endif + diff --git a/inc/extralibs/font_8x8.h b/inc/extralibs/font_8x8.h index 4cf7511..815d5b2 100644 --- a/inc/extralibs/font_8x8.h +++ b/inc/extralibs/font_8x8.h @@ -6,2564 +6,2564 @@ const static unsigned char fontdata[] = { - /* 0 0x00 '^@' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 1 0x01 '^A' */ - 0x7e, /* 01111110 */ - 0x81, /* 10000001 */ - 0xa5, /* 10100101 */ - 0x81, /* 10000001 */ - 0xbd, /* 10111101 */ - 0x99, /* 10011001 */ - 0x81, /* 10000001 */ - 0x7e, /* 01111110 */ - - /* 2 0x02 '^B' */ - 0x7e, /* 01111110 */ - 0xff, /* 11111111 */ - 0xdb, /* 11011011 */ - 0xff, /* 11111111 */ - 0xc3, /* 11000011 */ - 0xe7, /* 11100111 */ - 0xff, /* 11111111 */ - 0x7e, /* 01111110 */ - - /* 3 0x03 '^C' */ - 0x6c, /* 01101100 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0x7c, /* 01111100 */ - 0x38, /* 00111000 */ - 0x10, /* 00010000 */ - 0x00, /* 00000000 */ - - /* 4 0x04 '^D' */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x7c, /* 01111100 */ - 0xfe, /* 11111110 */ - 0x7c, /* 01111100 */ - 0x38, /* 00111000 */ - 0x10, /* 00010000 */ - 0x00, /* 00000000 */ - - /* 5 0x05 '^E' */ - 0x38, /* 00111000 */ - 0x7c, /* 01111100 */ - 0x38, /* 00111000 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0xd6, /* 11010110 */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - - /* 6 0x06 '^F' */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x7c, /* 01111100 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0x7c, /* 01111100 */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - - /* 7 0x07 '^G' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 8 0x08 '^H' */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xe7, /* 11100111 */ - 0xc3, /* 11000011 */ - 0xc3, /* 11000011 */ - 0xe7, /* 11100111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - - /* 9 0x09 '^I' */ - 0x00, /* 00000000 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x42, /* 01000010 */ - 0x42, /* 01000010 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 10 0x0a '^J' */ - 0xff, /* 11111111 */ - 0xc3, /* 11000011 */ - 0x99, /* 10011001 */ - 0xbd, /* 10111101 */ - 0xbd, /* 10111101 */ - 0x99, /* 10011001 */ - 0xc3, /* 11000011 */ - 0xff, /* 11111111 */ - - /* 11 0x0b '^K' */ - 0x0f, /* 00001111 */ - 0x07, /* 00000111 */ - 0x0f, /* 00001111 */ - 0x7d, /* 01111101 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x78, /* 01111000 */ - - /* 12 0x0c '^L' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - - /* 13 0x0d '^M' */ - 0x3f, /* 00111111 */ - 0x33, /* 00110011 */ - 0x3f, /* 00111111 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x70, /* 01110000 */ - 0xf0, /* 11110000 */ - 0xe0, /* 11100000 */ - - /* 14 0x0e '^N' */ - 0x7f, /* 01111111 */ - 0x63, /* 01100011 */ - 0x7f, /* 01111111 */ - 0x63, /* 01100011 */ - 0x63, /* 01100011 */ - 0x67, /* 01100111 */ - 0xe6, /* 11100110 */ - 0xc0, /* 11000000 */ - - /* 15 0x0f '^O' */ - 0x18, /* 00011000 */ - 0xdb, /* 11011011 */ - 0x3c, /* 00111100 */ - 0xe7, /* 11100111 */ - 0xe7, /* 11100111 */ - 0x3c, /* 00111100 */ - 0xdb, /* 11011011 */ - 0x18, /* 00011000 */ - - /* 16 0x10 '^P' */ - 0x80, /* 10000000 */ - 0xe0, /* 11100000 */ - 0xf8, /* 11111000 */ - 0xfe, /* 11111110 */ - 0xf8, /* 11111000 */ - 0xe0, /* 11100000 */ - 0x80, /* 10000000 */ - 0x00, /* 00000000 */ - - /* 17 0x11 '^Q' */ - 0x02, /* 00000010 */ - 0x0e, /* 00001110 */ - 0x3e, /* 00111110 */ - 0xfe, /* 11111110 */ - 0x3e, /* 00111110 */ - 0x0e, /* 00001110 */ - 0x02, /* 00000010 */ - 0x00, /* 00000000 */ - - /* 18 0x12 '^R' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - - /* 19 0x13 '^S' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - - /* 20 0x14 '^T' */ - 0x7f, /* 01111111 */ - 0xdb, /* 11011011 */ - 0xdb, /* 11011011 */ - 0x7b, /* 01111011 */ - 0x1b, /* 00011011 */ - 0x1b, /* 00011011 */ - 0x1b, /* 00011011 */ - 0x00, /* 00000000 */ - - /* 21 0x15 '^U' */ - 0x3e, /* 00111110 */ - 0x61, /* 01100001 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x86, /* 10000110 */ - 0x7c, /* 01111100 */ - - /* 22 0x16 '^V' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x7e, /* 01111110 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 23 0x17 '^W' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - - /* 24 0x18 '^X' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 25 0x19 '^Y' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 26 0x1a '^Z' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0xfe, /* 11111110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 27 0x1b '^[' */ - 0x00, /* 00000000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0xfe, /* 11111110 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 28 0x1c '^\' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 29 0x1d '^]' */ - 0x00, /* 00000000 */ - 0x24, /* 00100100 */ - 0x66, /* 01100110 */ - 0xff, /* 11111111 */ - 0x66, /* 01100110 */ - 0x24, /* 00100100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 30 0x1e '^^' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 31 0x1f '^_' */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0x7e, /* 01111110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 32 0x20 ' ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 33 0x21 '!' */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 34 0x22 '"' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x24, /* 00100100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 35 0x23 '#' */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 36 0x24 '$' */ - 0x18, /* 00011000 */ - 0x3e, /* 00111110 */ - 0x60, /* 01100000 */ - 0x3c, /* 00111100 */ - 0x06, /* 00000110 */ - 0x7c, /* 01111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 37 0x25 '%' */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xcc, /* 11001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x66, /* 01100110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 38 0x26 '&' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 39 0x27 ''' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 40 0x28 '(' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x00, /* 00000000 */ - - /* 41 0x29 ')' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - - /* 42 0x2a '*' */ - 0x00, /* 00000000 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0xff, /* 11111111 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 43 0x2b '+' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 44 0x2c ',' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - - /* 45 0x2d '-' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 46 0x2e '.' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 47 0x2f '/' */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0xc0, /* 11000000 */ - 0x80, /* 10000000 */ - 0x00, /* 00000000 */ - - /* 48 0x30 '0' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xd6, /* 11010110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 49 0x31 '1' */ - 0x18, /* 00011000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 50 0x32 '2' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0x06, /* 00000110 */ - 0x1c, /* 00011100 */ - 0x30, /* 00110000 */ - 0x66, /* 01100110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 51 0x33 '3' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0x06, /* 00000110 */ - 0x3c, /* 00111100 */ - 0x06, /* 00000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 52 0x34 '4' */ - 0x1c, /* 00011100 */ - 0x3c, /* 00111100 */ - 0x6c, /* 01101100 */ - 0xcc, /* 11001100 */ - 0xfe, /* 11111110 */ - 0x0c, /* 00001100 */ - 0x1e, /* 00011110 */ - 0x00, /* 00000000 */ - - /* 53 0x35 '5' */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xfc, /* 11111100 */ - 0x06, /* 00000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 54 0x36 '6' */ - 0x38, /* 00111000 */ - 0x60, /* 01100000 */ - 0xc0, /* 11000000 */ - 0xfc, /* 11111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 55 0x37 '7' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - - /* 56 0x38 '8' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 57 0x39 '9' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7e, /* 01111110 */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x78, /* 01111000 */ - 0x00, /* 00000000 */ - - /* 58 0x3a ':' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 59 0x3b ';' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - - /* 60 0x3c '<' */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x06, /* 00000110 */ - 0x00, /* 00000000 */ - - /* 61 0x3d '=' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 62 0x3e '>' */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0x00, /* 00000000 */ - - /* 63 0x3f '?' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 64 0x40 '@' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xde, /* 11011110 */ - 0xde, /* 11011110 */ - 0xde, /* 11011110 */ - 0xc0, /* 11000000 */ - 0x78, /* 01111000 */ - 0x00, /* 00000000 */ - - /* 65 0x41 'A' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 66 0x42 'B' */ - 0xfc, /* 11111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0xfc, /* 11111100 */ - 0x00, /* 00000000 */ - - /* 67 0x43 'C' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 68 0x44 'D' */ - 0xf8, /* 11111000 */ - 0x6c, /* 01101100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x6c, /* 01101100 */ - 0xf8, /* 11111000 */ - 0x00, /* 00000000 */ - - /* 69 0x45 'E' */ - 0xfe, /* 11111110 */ - 0x62, /* 01100010 */ - 0x68, /* 01101000 */ - 0x78, /* 01111000 */ - 0x68, /* 01101000 */ - 0x62, /* 01100010 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 70 0x46 'F' */ - 0xfe, /* 11111110 */ - 0x62, /* 01100010 */ - 0x68, /* 01101000 */ - 0x78, /* 01111000 */ - 0x68, /* 01101000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 71 0x47 'G' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xce, /* 11001110 */ - 0x66, /* 01100110 */ - 0x3a, /* 00111010 */ - 0x00, /* 00000000 */ - - /* 72 0x48 'H' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 73 0x49 'I' */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 74 0x4a 'J' */ - 0x1e, /* 00011110 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x78, /* 01111000 */ - 0x00, /* 00000000 */ - - /* 75 0x4b 'K' */ - 0xe6, /* 11100110 */ - 0x66, /* 01100110 */ - 0x6c, /* 01101100 */ - 0x78, /* 01111000 */ - 0x6c, /* 01101100 */ - 0x66, /* 01100110 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 76 0x4c 'L' */ - 0xf0, /* 11110000 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0x62, /* 01100010 */ - 0x66, /* 01100110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 77 0x4d 'M' */ - 0xc6, /* 11000110 */ - 0xee, /* 11101110 */ - 0xfe, /* 11111110 */ - 0xfe, /* 11111110 */ - 0xd6, /* 11010110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 78 0x4e 'N' */ - 0xc6, /* 11000110 */ - 0xe6, /* 11100110 */ - 0xf6, /* 11110110 */ - 0xde, /* 11011110 */ - 0xce, /* 11001110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 79 0x4f 'O' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 80 0x50 'P' */ - 0xfc, /* 11111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 81 0x51 'Q' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xce, /* 11001110 */ - 0x7c, /* 01111100 */ - 0x0e, /* 00001110 */ - - /* 82 0x52 'R' */ - 0xfc, /* 11111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x6c, /* 01101100 */ - 0x66, /* 01100110 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 83 0x53 'S' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 84 0x54 'T' */ - 0x7e, /* 01111110 */ - 0x7e, /* 01111110 */ - 0x5a, /* 01011010 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 85 0x55 'U' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 86 0x56 'V' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 87 0x57 'W' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 88 0x58 'X' */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 89 0x59 'Y' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 90 0x5a 'Z' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x8c, /* 10001100 */ - 0x18, /* 00011000 */ - 0x32, /* 00110010 */ - 0x66, /* 01100110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 91 0x5b '[' */ - 0x3c, /* 00111100 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 92 0x5c '\' */ - 0xc0, /* 11000000 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x06, /* 00000110 */ - 0x02, /* 00000010 */ - 0x00, /* 00000000 */ - - /* 93 0x5d ']' */ - 0x3c, /* 00111100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 94 0x5e '^' */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 95 0x5f '_' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - - /* 96 0x60 '`' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 97 0x61 'a' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 98 0x62 'b' */ - 0xe0, /* 11100000 */ - 0x60, /* 01100000 */ - 0x7c, /* 01111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - - /* 99 0x63 'c' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc0, /* 11000000 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 100 0x64 'd' */ - 0x1c, /* 00011100 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 101 0x65 'e' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 102 0x66 'f' */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x60, /* 01100000 */ - 0xf8, /* 11111000 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 103 0x67 'g' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x7c, /* 01111100 */ - 0x0c, /* 00001100 */ - 0xf8, /* 11111000 */ - - /* 104 0x68 'h' */ - 0xe0, /* 11100000 */ - 0x60, /* 01100000 */ - 0x6c, /* 01101100 */ - 0x76, /* 01110110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 105 0x69 'i' */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 106 0x6a 'j' */ - 0x06, /* 00000110 */ - 0x00, /* 00000000 */ - 0x06, /* 00000110 */ - 0x06, /* 00000110 */ - 0x06, /* 00000110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - - /* 107 0x6b 'k' */ - 0xe0, /* 11100000 */ - 0x60, /* 01100000 */ - 0x66, /* 01100110 */ - 0x6c, /* 01101100 */ - 0x78, /* 01111000 */ - 0x6c, /* 01101100 */ - 0xe6, /* 11100110 */ - 0x00, /* 00000000 */ - - /* 108 0x6c 'l' */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 109 0x6d 'm' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xec, /* 11101100 */ - 0xfe, /* 11111110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0x00, /* 00000000 */ - - /* 110 0x6e 'n' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - - /* 111 0x6f 'o' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 112 0x70 'p' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - - /* 113 0x71 'q' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x7c, /* 01111100 */ - 0x0c, /* 00001100 */ - 0x1e, /* 00011110 */ - - /* 114 0x72 'r' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x76, /* 01110110 */ - 0x60, /* 01100000 */ - 0x60, /* 01100000 */ - 0xf0, /* 11110000 */ - 0x00, /* 00000000 */ - - /* 115 0x73 's' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x06, /* 00000110 */ - 0xfc, /* 11111100 */ - 0x00, /* 00000000 */ - - /* 116 0x74 't' */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0xfc, /* 11111100 */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x36, /* 00110110 */ - 0x1c, /* 00011100 */ - 0x00, /* 00000000 */ - - /* 117 0x75 'u' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 118 0x76 'v' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 119 0x77 'w' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xd6, /* 11010110 */ - 0xd6, /* 11010110 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 120 0x78 'x' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 121 0x79 'y' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7e, /* 01111110 */ - 0x06, /* 00000110 */ - 0xfc, /* 11111100 */ - - /* 122 0x7a 'z' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x4c, /* 01001100 */ - 0x18, /* 00011000 */ - 0x32, /* 00110010 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 123 0x7b '{' */ - 0x0e, /* 00001110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x70, /* 01110000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x0e, /* 00001110 */ - 0x00, /* 00000000 */ - - /* 124 0x7c '|' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 125 0x7d '}' */ - 0x70, /* 01110000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x0e, /* 00001110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x70, /* 01110000 */ - 0x00, /* 00000000 */ - - /* 126 0x7e '~' */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 127 0x7f '' */ - 0x00, /* 00000000 */ - 0x10, /* 00010000 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 128 0x80 '€' */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x0c, /* 00001100 */ - 0x78, /* 01111000 */ - - /* 129 0x81 '' */ - 0xcc, /* 11001100 */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 130 0x82 '‚' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 131 0x83 'ƒ' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 132 0x84 '„' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 133 0x85 '…' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 134 0x86 '†' */ - 0x30, /* 00110000 */ - 0x30, /* 00110000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 135 0x87 '‡' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x7e, /* 01111110 */ - 0x0c, /* 00001100 */ - 0x38, /* 00111000 */ - - /* 136 0x88 'ˆ' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 137 0x89 '‰' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 138 0x8a 'Š' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 139 0x8b '‹' */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 140 0x8c 'Œ' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 141 0x8d '' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 142 0x8e 'Ž' */ - 0xc6, /* 11000110 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 143 0x8f '' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 144 0x90 '' */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0xf8, /* 11111000 */ - 0xc0, /* 11000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 145 0x91 '‘' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0xd8, /* 11011000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 146 0x92 '’' */ - 0x3e, /* 00111110 */ - 0x6c, /* 01101100 */ - 0xcc, /* 11001100 */ - 0xfe, /* 11111110 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xce, /* 11001110 */ - 0x00, /* 00000000 */ - - /* 147 0x93 '“' */ - 0x7c, /* 01111100 */ - 0x82, /* 10000010 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 148 0x94 '”' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 149 0x95 '•' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 150 0x96 '–' */ - 0x78, /* 01111000 */ - 0x84, /* 10000100 */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 151 0x97 '—' */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 152 0x98 '˜' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7e, /* 01111110 */ - 0x06, /* 00000110 */ - 0xfc, /* 11111100 */ - - /* 153 0x99 '™' */ - 0xc6, /* 11000110 */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 154 0x9a 'š' */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 155 0x9b '›' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 156 0x9c 'œ' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x64, /* 01100100 */ - 0xf0, /* 11110000 */ - 0x60, /* 01100000 */ - 0x66, /* 01100110 */ - 0xfc, /* 11111100 */ - 0x00, /* 00000000 */ - - /* 157 0x9d '' */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 158 0x9e 'ž' */ - 0xf8, /* 11111000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xfa, /* 11111010 */ - 0xc6, /* 11000110 */ - 0xcf, /* 11001111 */ - 0xc6, /* 11000110 */ - 0xc7, /* 11000111 */ - - /* 159 0x9f 'Ÿ' */ - 0x0e, /* 00001110 */ - 0x1b, /* 00011011 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0xd8, /* 11011000 */ - 0x70, /* 01110000 */ - 0x00, /* 00000000 */ - - /* 160 0xa0 ' ' */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x7c, /* 01111100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 161 0xa1 '¡' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x38, /* 00111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 162 0xa2 '¢' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - - /* 163 0xa3 '£' */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 164 0xa4 '¤' */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0xdc, /* 11011100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x00, /* 00000000 */ - - /* 165 0xa5 '¥' */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0xe6, /* 11100110 */ - 0xf6, /* 11110110 */ - 0xde, /* 11011110 */ - 0xce, /* 11001110 */ - 0x00, /* 00000000 */ - - /* 166 0xa6 '¦' */ - 0x3c, /* 00111100 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x3e, /* 00111110 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 167 0xa7 '§' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 168 0xa8 '¨' */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x63, /* 01100011 */ - 0x3e, /* 00111110 */ - 0x00, /* 00000000 */ - - /* 169 0xa9 '©' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 170 0xaa 'ª' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x06, /* 00000110 */ - 0x06, /* 00000110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 171 0xab '«' */ - 0x63, /* 01100011 */ - 0xe6, /* 11100110 */ - 0x6c, /* 01101100 */ - 0x7e, /* 01111110 */ - 0x33, /* 00110011 */ - 0x66, /* 01100110 */ - 0xcc, /* 11001100 */ - 0x0f, /* 00001111 */ - - /* 172 0xac '¬' */ - 0x63, /* 01100011 */ - 0xe6, /* 11100110 */ - 0x6c, /* 01101100 */ - 0x7a, /* 01111010 */ - 0x36, /* 00110110 */ - 0x6a, /* 01101010 */ - 0xdf, /* 11011111 */ - 0x06, /* 00000110 */ - - /* 173 0xad '­' */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 174 0xae '®' */ - 0x00, /* 00000000 */ - 0x33, /* 00110011 */ - 0x66, /* 01100110 */ - 0xcc, /* 11001100 */ - 0x66, /* 01100110 */ - 0x33, /* 00110011 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 175 0xaf '¯' */ - 0x00, /* 00000000 */ - 0xcc, /* 11001100 */ - 0x66, /* 01100110 */ - 0x33, /* 00110011 */ - 0x66, /* 01100110 */ - 0xcc, /* 11001100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 176 0xb0 '°' */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - 0x22, /* 00100010 */ - 0x88, /* 10001000 */ - - /* 177 0xb1 '±' */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - 0x55, /* 01010101 */ - 0xaa, /* 10101010 */ - - /* 178 0xb2 '²' */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - 0x77, /* 01110111 */ - 0xdd, /* 11011101 */ - - /* 179 0xb3 '³' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 180 0xb4 '´' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 181 0xb5 'µ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 182 0xb6 '¶' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf6, /* 11110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 183 0xb7 '·' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 184 0xb8 '¸' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 185 0xb9 '¹' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf6, /* 11110110 */ - 0x06, /* 00000110 */ - 0xf6, /* 11110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 186 0xba 'º' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 187 0xbb '»' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x06, /* 00000110 */ - 0xf6, /* 11110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 188 0xbc '¼' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf6, /* 11110110 */ - 0x06, /* 00000110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 189 0xbd '½' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 190 0xbe '¾' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 191 0xbf '¿' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xf8, /* 11111000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 192 0xc0 'À' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 193 0xc1 'Á' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 194 0xc2 'Â' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 195 0xc3 'Ã' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 196 0xc4 'Ä' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 197 0xc5 'Å' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 198 0xc6 'Æ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 199 0xc7 'Ç' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x37, /* 00110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 200 0xc8 'È' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x37, /* 00110111 */ - 0x30, /* 00110000 */ - 0x3f, /* 00111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 201 0xc9 'É' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x3f, /* 00111111 */ - 0x30, /* 00110000 */ - 0x37, /* 00110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 202 0xca 'Ê' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf7, /* 11110111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 203 0xcb 'Ë' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xf7, /* 11110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 204 0xcc 'Ì' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x37, /* 00110111 */ - 0x30, /* 00110000 */ - 0x37, /* 00110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 205 0xcd 'Í' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 206 0xce 'Î' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xf7, /* 11110111 */ - 0x00, /* 00000000 */ - 0xf7, /* 11110111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 207 0xcf 'Ï' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 208 0xd0 'Ð' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 209 0xd1 'Ñ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 210 0xd2 'Ò' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 211 0xd3 'Ó' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x3f, /* 00111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 212 0xd4 'Ô' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 213 0xd5 'Õ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 214 0xd6 'Ö' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x3f, /* 00111111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 215 0xd7 '×' */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0xff, /* 11111111 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - - /* 216 0xd8 'Ø' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0xff, /* 11111111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 217 0xd9 'Ù' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xf8, /* 11111000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 218 0xda 'Ú' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x1f, /* 00011111 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 219 0xdb 'Û' */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - - /* 220 0xdc 'Ü' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - - /* 221 0xdd 'Ý' */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - 0xf0, /* 11110000 */ - - /* 222 0xde 'Þ' */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - 0x0f, /* 00001111 */ - - /* 223 0xdf 'ß' */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0xff, /* 11111111 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 224 0xe0 'à' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0xc8, /* 11001000 */ - 0xdc, /* 11011100 */ - 0x76, /* 01110110 */ - 0x00, /* 00000000 */ - - /* 225 0xe1 'á' */ - 0x78, /* 01111000 */ - 0xcc, /* 11001100 */ - 0xcc, /* 11001100 */ - 0xd8, /* 11011000 */ - 0xcc, /* 11001100 */ - 0xc6, /* 11000110 */ - 0xcc, /* 11001100 */ - 0x00, /* 00000000 */ - - /* 226 0xe2 'â' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0xc0, /* 11000000 */ - 0x00, /* 00000000 */ - - /* 227 0xe3 'ã' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x00, /* 00000000 */ - - /* 228 0xe4 'ä' */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - - /* 229 0xe5 'å' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xd8, /* 11011000 */ - 0xd8, /* 11011000 */ - 0xd8, /* 11011000 */ - 0x70, /* 01110000 */ - 0x00, /* 00000000 */ - - /* 230 0xe6 'æ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x7c, /* 01111100 */ - 0xc0, /* 11000000 */ - - /* 231 0xe7 'ç' */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - - /* 232 0xe8 'è' */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x3c, /* 00111100 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - - /* 233 0xe9 'é' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xfe, /* 11111110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - - /* 234 0xea 'ê' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0xee, /* 11101110 */ - 0x00, /* 00000000 */ - - /* 235 0xeb 'ë' */ - 0x0e, /* 00001110 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x3e, /* 00111110 */ - 0x66, /* 01100110 */ - 0x66, /* 01100110 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - - /* 236 0xec 'ì' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0xdb, /* 11011011 */ - 0xdb, /* 11011011 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 237 0xed 'í' */ - 0x06, /* 00000110 */ - 0x0c, /* 00001100 */ - 0x7e, /* 01111110 */ - 0xdb, /* 11011011 */ - 0xdb, /* 11011011 */ - 0x7e, /* 01111110 */ - 0x60, /* 01100000 */ - 0xc0, /* 11000000 */ - - /* 238 0xee 'î' */ - 0x1e, /* 00011110 */ - 0x30, /* 00110000 */ - 0x60, /* 01100000 */ - 0x7e, /* 01111110 */ - 0x60, /* 01100000 */ - 0x30, /* 00110000 */ - 0x1e, /* 00011110 */ - 0x00, /* 00000000 */ - - /* 239 0xef 'ï' */ - 0x00, /* 00000000 */ - 0x7c, /* 01111100 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0xc6, /* 11000110 */ - 0x00, /* 00000000 */ - - /* 240 0xf0 'ð' */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0xfe, /* 11111110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 241 0xf1 'ñ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x7e, /* 01111110 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 242 0xf2 'ò' */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 243 0xf3 'ó' */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x18, /* 00011000 */ - 0x0c, /* 00001100 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - - /* 244 0xf4 'ô' */ - 0x0e, /* 00001110 */ - 0x1b, /* 00011011 */ - 0x1b, /* 00011011 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - - /* 245 0xf5 'õ' */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0xd8, /* 11011000 */ - 0xd8, /* 11011000 */ - 0x70, /* 01110000 */ - - /* 246 0xf6 'ö' */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x7e, /* 01111110 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 247 0xf7 '÷' */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0x76, /* 01110110 */ - 0xdc, /* 11011100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 248 0xf8 'ø' */ - 0x38, /* 00111000 */ - 0x6c, /* 01101100 */ - 0x6c, /* 01101100 */ - 0x38, /* 00111000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 249 0xf9 'ù' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 250 0xfa 'ú' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x18, /* 00011000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 251 0xfb 'û' */ - 0x0f, /* 00001111 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0x0c, /* 00001100 */ - 0xec, /* 11101100 */ - 0x6c, /* 01101100 */ - 0x3c, /* 00111100 */ - 0x1c, /* 00011100 */ - - /* 252 0xfc 'ü' */ - 0x6c, /* 01101100 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x36, /* 00110110 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 253 0xfd 'ý' */ - 0x78, /* 01111000 */ - 0x0c, /* 00001100 */ - 0x18, /* 00011000 */ - 0x30, /* 00110000 */ - 0x7c, /* 01111100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 254 0xfe 'þ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x3c, /* 00111100 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - - /* 255 0xff 'ÿ' */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ - 0x00, /* 00000000 */ + /* 0 0x00 '^@' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 1 0x01 '^A' */ + 0x7e, /* 01111110 */ + 0x81, /* 10000001 */ + 0xa5, /* 10100101 */ + 0x81, /* 10000001 */ + 0xbd, /* 10111101 */ + 0x99, /* 10011001 */ + 0x81, /* 10000001 */ + 0x7e, /* 01111110 */ + + /* 2 0x02 '^B' */ + 0x7e, /* 01111110 */ + 0xff, /* 11111111 */ + 0xdb, /* 11011011 */ + 0xff, /* 11111111 */ + 0xc3, /* 11000011 */ + 0xe7, /* 11100111 */ + 0xff, /* 11111111 */ + 0x7e, /* 01111110 */ + + /* 3 0x03 '^C' */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + + /* 4 0x04 '^D' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + + /* 5 0x05 '^E' */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + + /* 6 0x06 '^F' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + + /* 7 0x07 '^G' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 8 0x08 '^H' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xe7, /* 11100111 */ + 0xc3, /* 11000011 */ + 0xc3, /* 11000011 */ + 0xe7, /* 11100111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 9 0x09 '^I' */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x42, /* 01000010 */ + 0x42, /* 01000010 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 10 0x0a '^J' */ + 0xff, /* 11111111 */ + 0xc3, /* 11000011 */ + 0x99, /* 10011001 */ + 0xbd, /* 10111101 */ + 0xbd, /* 10111101 */ + 0x99, /* 10011001 */ + 0xc3, /* 11000011 */ + 0xff, /* 11111111 */ + + /* 11 0x0b '^K' */ + 0x0f, /* 00001111 */ + 0x07, /* 00000111 */ + 0x0f, /* 00001111 */ + 0x7d, /* 01111101 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + + /* 12 0x0c '^L' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + + /* 13 0x0d '^M' */ + 0x3f, /* 00111111 */ + 0x33, /* 00110011 */ + 0x3f, /* 00111111 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x70, /* 01110000 */ + 0xf0, /* 11110000 */ + 0xe0, /* 11100000 */ + + /* 14 0x0e '^N' */ + 0x7f, /* 01111111 */ + 0x63, /* 01100011 */ + 0x7f, /* 01111111 */ + 0x63, /* 01100011 */ + 0x63, /* 01100011 */ + 0x67, /* 01100111 */ + 0xe6, /* 11100110 */ + 0xc0, /* 11000000 */ + + /* 15 0x0f '^O' */ + 0x18, /* 00011000 */ + 0xdb, /* 11011011 */ + 0x3c, /* 00111100 */ + 0xe7, /* 11100111 */ + 0xe7, /* 11100111 */ + 0x3c, /* 00111100 */ + 0xdb, /* 11011011 */ + 0x18, /* 00011000 */ + + /* 16 0x10 '^P' */ + 0x80, /* 10000000 */ + 0xe0, /* 11100000 */ + 0xf8, /* 11111000 */ + 0xfe, /* 11111110 */ + 0xf8, /* 11111000 */ + 0xe0, /* 11100000 */ + 0x80, /* 10000000 */ + 0x00, /* 00000000 */ + + /* 17 0x11 '^Q' */ + 0x02, /* 00000010 */ + 0x0e, /* 00001110 */ + 0x3e, /* 00111110 */ + 0xfe, /* 11111110 */ + 0x3e, /* 00111110 */ + 0x0e, /* 00001110 */ + 0x02, /* 00000010 */ + 0x00, /* 00000000 */ + + /* 18 0x12 '^R' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + + /* 19 0x13 '^S' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + + /* 20 0x14 '^T' */ + 0x7f, /* 01111111 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7b, /* 01111011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x00, /* 00000000 */ + + /* 21 0x15 '^U' */ + 0x3e, /* 00111110 */ + 0x61, /* 01100001 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x86, /* 10000110 */ + 0x7c, /* 01111100 */ + + /* 22 0x16 '^V' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 23 0x17 '^W' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + + /* 24 0x18 '^X' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 25 0x19 '^Y' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 26 0x1a '^Z' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0xfe, /* 11111110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 27 0x1b '^[' */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xfe, /* 11111110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 28 0x1c '^\' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 29 0x1d '^]' */ + 0x00, /* 00000000 */ + 0x24, /* 00100100 */ + 0x66, /* 01100110 */ + 0xff, /* 11111111 */ + 0x66, /* 01100110 */ + 0x24, /* 00100100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 30 0x1e '^^' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 31 0x1f '^_' */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 32 0x20 ' ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 33 0x21 '!' */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 34 0x22 '"' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x24, /* 00100100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 35 0x23 '#' */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 36 0x24 '$' */ + 0x18, /* 00011000 */ + 0x3e, /* 00111110 */ + 0x60, /* 01100000 */ + 0x3c, /* 00111100 */ + 0x06, /* 00000110 */ + 0x7c, /* 01111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 37 0x25 '%' */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xcc, /* 11001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x66, /* 01100110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 38 0x26 '&' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 39 0x27 ''' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 40 0x28 '(' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + + /* 41 0x29 ')' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + + /* 42 0x2a '*' */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0xff, /* 11111111 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 43 0x2b '+' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 44 0x2c ',' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + + /* 45 0x2d '-' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 46 0x2e '.' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 47 0x2f '/' */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0x80, /* 10000000 */ + 0x00, /* 00000000 */ + + /* 48 0x30 '0' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 49 0x31 '1' */ + 0x18, /* 00011000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 50 0x32 '2' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x1c, /* 00011100 */ + 0x30, /* 00110000 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 51 0x33 '3' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x3c, /* 00111100 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 52 0x34 '4' */ + 0x1c, /* 00011100 */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xfe, /* 11111110 */ + 0x0c, /* 00001100 */ + 0x1e, /* 00011110 */ + 0x00, /* 00000000 */ + + /* 53 0x35 '5' */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfc, /* 11111100 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 54 0x36 '6' */ + 0x38, /* 00111000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0xfc, /* 11111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 55 0x37 '7' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + + /* 56 0x38 '8' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 57 0x39 '9' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 58 0x3a ':' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 59 0x3b ';' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + + /* 60 0x3c '<' */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + + /* 61 0x3d '=' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 62 0x3e '>' */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + + /* 63 0x3f '?' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 64 0x40 '@' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xde, /* 11011110 */ + 0xde, /* 11011110 */ + 0xde, /* 11011110 */ + 0xc0, /* 11000000 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 65 0x41 'A' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 66 0x42 'B' */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + + /* 67 0x43 'C' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 68 0x44 'D' */ + 0xf8, /* 11111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + + /* 69 0x45 'E' */ + 0xfe, /* 11111110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x62, /* 01100010 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 70 0x46 'F' */ + 0xfe, /* 11111110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 71 0x47 'G' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xce, /* 11001110 */ + 0x66, /* 01100110 */ + 0x3a, /* 00111010 */ + 0x00, /* 00000000 */ + + /* 72 0x48 'H' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 73 0x49 'I' */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 74 0x4a 'J' */ + 0x1e, /* 00011110 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 75 0x4b 'K' */ + 0xe6, /* 11100110 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 76 0x4c 'L' */ + 0xf0, /* 11110000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 77 0x4d 'M' */ + 0xc6, /* 11000110 */ + 0xee, /* 11101110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 78 0x4e 'N' */ + 0xc6, /* 11000110 */ + 0xe6, /* 11100110 */ + 0xf6, /* 11110110 */ + 0xde, /* 11011110 */ + 0xce, /* 11001110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 79 0x4f 'O' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 80 0x50 'P' */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 81 0x51 'Q' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xce, /* 11001110 */ + 0x7c, /* 01111100 */ + 0x0e, /* 00001110 */ + + /* 82 0x52 'R' */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 83 0x53 'S' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 84 0x54 'T' */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x5a, /* 01011010 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 85 0x55 'U' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 86 0x56 'V' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 87 0x57 'W' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 88 0x58 'X' */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 89 0x59 'Y' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 90 0x5a 'Z' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x8c, /* 10001100 */ + 0x18, /* 00011000 */ + 0x32, /* 00110010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 91 0x5b '[' */ + 0x3c, /* 00111100 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 92 0x5c '\' */ + 0xc0, /* 11000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x02, /* 00000010 */ + 0x00, /* 00000000 */ + + /* 93 0x5d ']' */ + 0x3c, /* 00111100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 94 0x5e '^' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 95 0x5f '_' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + + /* 96 0x60 '`' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 97 0x61 'a' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 98 0x62 'b' */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x7c, /* 01111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + + /* 99 0x63 'c' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 100 0x64 'd' */ + 0x1c, /* 00011100 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 101 0x65 'e' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 102 0x66 'f' */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x60, /* 01100000 */ + 0xf8, /* 11111000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 103 0x67 'g' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0xf8, /* 11111000 */ + + /* 104 0x68 'h' */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x6c, /* 01101100 */ + 0x76, /* 01110110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 105 0x69 'i' */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 106 0x6a 'j' */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + + /* 107 0x6b 'k' */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + + /* 108 0x6c 'l' */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 109 0x6d 'm' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xec, /* 11101100 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0x00, /* 00000000 */ + + /* 110 0x6e 'n' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + + /* 111 0x6f 'o' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 112 0x70 'p' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + + /* 113 0x71 'q' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0x1e, /* 00011110 */ + + /* 114 0x72 'r' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x76, /* 01110110 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 115 0x73 's' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x06, /* 00000110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + + /* 116 0x74 't' */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0xfc, /* 11111100 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x36, /* 00110110 */ + 0x1c, /* 00011100 */ + 0x00, /* 00000000 */ + + /* 117 0x75 'u' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 118 0x76 'v' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 119 0x77 'w' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 120 0x78 'x' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 121 0x79 'y' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0xfc, /* 11111100 */ + + /* 122 0x7a 'z' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x4c, /* 01001100 */ + 0x18, /* 00011000 */ + 0x32, /* 00110010 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 123 0x7b '{' */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x0e, /* 00001110 */ + 0x00, /* 00000000 */ + + /* 124 0x7c '|' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 125 0x7d '}' */ + 0x70, /* 01110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + + /* 126 0x7e '~' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 127 0x7f '' */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 128 0x80 '€' */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0x78, /* 01111000 */ + + /* 129 0x81 '' */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 130 0x82 '‚' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 131 0x83 'ƒ' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 132 0x84 '„' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 133 0x85 '…' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 134 0x86 '†' */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 135 0x87 '‡' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x7e, /* 01111110 */ + 0x0c, /* 00001100 */ + 0x38, /* 00111000 */ + + /* 136 0x88 'ˆ' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 137 0x89 '‰' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 138 0x8a 'Š' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 139 0x8b '‹' */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 140 0x8c 'Œ' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 141 0x8d '' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 142 0x8e 'Ž' */ + 0xc6, /* 11000110 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 143 0x8f '' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 144 0x90 '' */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xf8, /* 11111000 */ + 0xc0, /* 11000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 145 0x91 '‘' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0xd8, /* 11011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 146 0x92 '’' */ + 0x3e, /* 00111110 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xfe, /* 11111110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xce, /* 11001110 */ + 0x00, /* 00000000 */ + + /* 147 0x93 '“' */ + 0x7c, /* 01111100 */ + 0x82, /* 10000010 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 148 0x94 '”' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 149 0x95 '•' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 150 0x96 '–' */ + 0x78, /* 01111000 */ + 0x84, /* 10000100 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 151 0x97 '—' */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 152 0x98 '˜' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0xfc, /* 11111100 */ + + /* 153 0x99 '™' */ + 0xc6, /* 11000110 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 154 0x9a 'š' */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 155 0x9b '›' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 156 0x9c 'œ' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x64, /* 01100100 */ + 0xf0, /* 11110000 */ + 0x60, /* 01100000 */ + 0x66, /* 01100110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + + /* 157 0x9d '' */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 158 0x9e 'ž' */ + 0xf8, /* 11111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xfa, /* 11111010 */ + 0xc6, /* 11000110 */ + 0xcf, /* 11001111 */ + 0xc6, /* 11000110 */ + 0xc7, /* 11000111 */ + + /* 159 0x9f 'Ÿ' */ + 0x0e, /* 00001110 */ + 0x1b, /* 00011011 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + + /* 160 0xa0 ' ' */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 161 0xa1 '¡' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 162 0xa2 '¢' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + + /* 163 0xa3 '£' */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 164 0xa4 '¤' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + + /* 165 0xa5 '¥' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0xe6, /* 11100110 */ + 0xf6, /* 11110110 */ + 0xde, /* 11011110 */ + 0xce, /* 11001110 */ + 0x00, /* 00000000 */ + + /* 166 0xa6 '¦' */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x3e, /* 00111110 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 167 0xa7 '§' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 168 0xa8 '¨' */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x63, /* 01100011 */ + 0x3e, /* 00111110 */ + 0x00, /* 00000000 */ + + /* 169 0xa9 '©' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 170 0xaa 'ª' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 171 0xab '«' */ + 0x63, /* 01100011 */ + 0xe6, /* 11100110 */ + 0x6c, /* 01101100 */ + 0x7e, /* 01111110 */ + 0x33, /* 00110011 */ + 0x66, /* 01100110 */ + 0xcc, /* 11001100 */ + 0x0f, /* 00001111 */ + + /* 172 0xac '¬' */ + 0x63, /* 01100011 */ + 0xe6, /* 11100110 */ + 0x6c, /* 01101100 */ + 0x7a, /* 01111010 */ + 0x36, /* 00110110 */ + 0x6a, /* 01101010 */ + 0xdf, /* 11011111 */ + 0x06, /* 00000110 */ + + /* 173 0xad '­' */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 174 0xae '®' */ + 0x00, /* 00000000 */ + 0x33, /* 00110011 */ + 0x66, /* 01100110 */ + 0xcc, /* 11001100 */ + 0x66, /* 01100110 */ + 0x33, /* 00110011 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 175 0xaf '¯' */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0x66, /* 01100110 */ + 0x33, /* 00110011 */ + 0x66, /* 01100110 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 176 0xb0 '°' */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + 0x22, /* 00100010 */ + 0x88, /* 10001000 */ + + /* 177 0xb1 '±' */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + + /* 178 0xb2 '²' */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + + /* 179 0xb3 '³' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 180 0xb4 '´' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 181 0xb5 'µ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 182 0xb6 '¶' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 183 0xb7 '·' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 184 0xb8 '¸' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 185 0xb9 '¹' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x06, /* 00000110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 186 0xba 'º' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 187 0xbb '»' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x06, /* 00000110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 188 0xbc '¼' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x06, /* 00000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 189 0xbd '½' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 190 0xbe '¾' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 191 0xbf '¿' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 192 0xc0 'À' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 193 0xc1 'Á' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 194 0xc2 'Â' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 195 0xc3 'Ã' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 196 0xc4 'Ä' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 197 0xc5 'Å' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 198 0xc6 'Æ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 199 0xc7 'Ç' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 200 0xc8 'È' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x30, /* 00110000 */ + 0x3f, /* 00111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 201 0xc9 'É' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x30, /* 00110000 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 202 0xca 'Ê' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf7, /* 11110111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 203 0xcb 'Ë' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xf7, /* 11110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 204 0xcc 'Ì' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x30, /* 00110000 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 205 0xcd 'Í' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 206 0xce 'Î' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf7, /* 11110111 */ + 0x00, /* 00000000 */ + 0xf7, /* 11110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 207 0xcf 'Ï' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 208 0xd0 'Ð' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 209 0xd1 'Ñ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 210 0xd2 'Ò' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 211 0xd3 'Ó' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x3f, /* 00111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 212 0xd4 'Ô' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 213 0xd5 'Õ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 214 0xd6 'Ö' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 215 0xd7 '×' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xff, /* 11111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 216 0xd8 'Ø' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 217 0xd9 'Ù' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 218 0xda 'Ú' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 219 0xdb 'Û' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 220 0xdc 'Ü' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 221 0xdd 'Ý' */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + + /* 222 0xde 'Þ' */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + + /* 223 0xdf 'ß' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 224 0xe0 'à' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0xc8, /* 11001000 */ + 0xdc, /* 11011100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + + /* 225 0xe1 'á' */ + 0x78, /* 01111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xd8, /* 11011000 */ + 0xcc, /* 11001100 */ + 0xc6, /* 11000110 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + + /* 226 0xe2 'â' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + + /* 227 0xe3 'ã' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + + /* 228 0xe4 'ä' */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + + /* 229 0xe5 'å' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + + /* 230 0xe6 'æ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0xc0, /* 11000000 */ + + /* 231 0xe7 'ç' */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + + /* 232 0xe8 'è' */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + + /* 233 0xe9 'é' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + + /* 234 0xea 'ê' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xee, /* 11101110 */ + 0x00, /* 00000000 */ + + /* 235 0xeb 'ë' */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x3e, /* 00111110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 236 0xec 'ì' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 237 0xed 'í' */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x7e, /* 01111110 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7e, /* 01111110 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + + /* 238 0xee 'î' */ + 0x1e, /* 00011110 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x7e, /* 01111110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x1e, /* 00011110 */ + 0x00, /* 00000000 */ + + /* 239 0xef 'ï' */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + + /* 240 0xf0 'ð' */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 241 0xf1 'ñ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 242 0xf2 'ò' */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 243 0xf3 'ó' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + + /* 244 0xf4 'ô' */ + 0x0e, /* 00001110 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 245 0xf5 'õ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + + /* 246 0xf6 'ö' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 247 0xf7 '÷' */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 248 0xf8 'ø' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 249 0xf9 'ù' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 250 0xfa 'ú' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 251 0xfb 'û' */ + 0x0f, /* 00001111 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0xec, /* 11101100 */ + 0x6c, /* 01101100 */ + 0x3c, /* 00111100 */ + 0x1c, /* 00011100 */ + + /* 252 0xfc 'ü' */ + 0x6c, /* 01101100 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 253 0xfd 'ý' */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 254 0xfe 'þ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 255 0xff 'ÿ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ }; diff --git a/inc/extralibs/fsusb.c b/inc/extralibs/fsusb.c new file mode 100644 index 0000000..4134cae --- /dev/null +++ b/inc/extralibs/fsusb.c @@ -0,0 +1,1036 @@ +#include "fsusb.h" +#include "ch32fun.h" +#include + +#ifdef __DMA_SAFE +// CH573 needs all buffers that will touch DMA be allocated at specific memory location +// Since we have EP buffers inside the context struct we put it all there. +// If you want to use your own external buffers, be sure to use this macro before their definitions. +__DMA_SAFE +#endif +struct _USBState USBFSCTX; +volatile uint8_t usb_debug = 0; + +#if !defined CH5xx && FUSB_USE_DMA7_COPYs +static inline void copyBuffer( uint8_t * dest, const uint8_t * src, int len ) +{ + while( DMA1_Channel7->CNTR ); + DMA1_Channel7->CFGR = 0; + DMA1_Channel7->MADDR = (uintptr_t)src; + DMA1_Channel7->PADDR = (uintptr_t)dest; + DMA1_Channel7->CNTR = (len+3)/4; + DMA1_Channel7->CFGR = + DMA_M2M_Enable | + DMA_DIR_PeripheralDST | + DMA_Priority_Low | + DMA_MemoryDataSize_Word | + DMA_PeripheralDataSize_Word | + DMA_MemoryInc_Enable | + DMA_PeripheralInc_Enable | + DMA_Mode_Normal | DMA_CFGR1_EN; +#if !( FUSB_CURSED_TURBO_DMA == 1 ) + // Somehow, it seems to work (unsafely) without this. + // Really, though, it's probably fine. + while( DMA1_Channel7->CNTR ); +#endif +} + +static inline void copyBufferComplete() { while( DMA1_Channel7->CNTR ); } +#else +#define copyBuffer memcpy +#define copyBufferComplete() ((void)0) +#endif + +#if defined (CH5xx) +#define USBFS_IRQHandler USB_IRQHandler +#endif + +#if FUSB_USE_HPE +// There is an issue with some registers apparently getting lost with HPE, just do it the slow way. +void USBFS_IRQHandler() __attribute__((section(".text.vector_handler"))) __attribute((interrupt)); +// void USBHD_IRQHandler() __attribute__((section(".text.vector_handler"))) __attribute((naked)); +#else +#if defined(FUSB_FROM_RAM) && (FUSB_FROM_RAM) +void USBFS_IRQHandler() __USBFS_FUN_ATTRIBUTE __attribute((interrupt)); +#else +void USBFS_IRQHandler() __attribute__((section(".text.vector_handler"))) __attribute((interrupt)); +#endif +#endif + +void USBFS_InternalFinishSetup(); + +void USBFS_IRQHandler() +{ +#if FUSB_IO_PROFILE + funDigitalWrite( DEBUG_PIN, 1 ); +#endif + + // Combined FG + ST flag. + uint16_t intfgst = *(uint16_t*)(&USBFS->INT_FG); + int len = 0; + struct _USBState * ctx = &USBFSCTX; + uint8_t * ctrl0buff = CTRL0BUFF; + + // TODO: Check if needs to be do-while to re-check. + if( intfgst & CRB_UIF_TRANSFER ) + { + + int token = ( intfgst & CMASK_UIS_TOKEN) >> 12; + int ep = ( intfgst & CMASK_UIS_ENDP ) >> 8; + if( usb_debug ) printf("[USB] TRANSFER, token = %02x, ep = %d, bmRequestType = %02x, bRequest = %02x\n", token, ep, pUSBFS_SetupReqPak->bmRequestType, pUSBFS_SetupReqPak->bRequest); + switch ( token ) + { + case CUIS_TOKEN_IN: + if( ep ) + { + if( ep < FUSB_CONFIG_EPS ) + { +#if FUSB_USER_HANDLERS + len = HandleInRequest( ctx, ep, ctx->ENDPOINTS[ ep ], 0 ); +#endif + UEP_CTRL_TX(ep) ^= USBFS_UEP_T_TOG; + if( len ) + { + if( len < 0 ) len = 0; + UEP_CTRL_LEN( ep ) = len; + UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_ACK; + } + else + { + UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_NAK; + } + ctx->USBFS_Endp_Busy[ ep ] = 0; + } + } + else + { + /* end-point 0 data in interrupt */ + if( ctx->USBFS_SetupReqLen == 0 ) + { +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(0) = USBFS_UEP_R_RES_ACK | USBFS_UEP_R_TOG; + // R8_UEP0_CTRL = (R8_UEP0_CTRL & ~MASK_UEP_R_RES ) | UEP_R_RES_ACK; +#else + UEP_CTRL_RX(0) = USBFS_UEP_R_RES_ACK | USBFS_UEP_R_TOG; +#endif + } + + ctx->USBFS_errata_dont_send_endpoint_in_window = 0; + + if( ctx->pCtrlPayloadPtr ) + { + // Shortcut mechanism, for descriptors or if the user wants it. + len = ctx->USBFS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBFS_SetupReqLen; + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); // FYI -> Would need to do this if using DMA + ctx->USBFS_SetupReqLen -= len; + if( ctx->USBFS_SetupReqLen > 0 ) + ctx->pCtrlPayloadPtr += len; + else + ctx->pCtrlPayloadPtr = 0; + + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) ^= USBFS_UEP_T_TOG; + } + else if ( ( ctx->USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) + { + len = ctx->USBFS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBFS_SetupReqLen; +#if FUSB_HID_USER_REPORTS + if( len && USBFSCTX.USBFS_SetupReqCode == HID_GET_REPORT ) + { + len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) ^= USBFS_UEP_T_TOG; + ctx->USBFS_SetupReqLen -= len; + ctx->pCtrlPayloadPtr += len; + } +#endif +#if FUSB_USER_HANDLERS + if( len && USBFSCTX.USBFS_SetupReqCode != HID_GET_REPORT ) + { + len = HandleInRequest( ctx, 0, ctrl0buff, len ); + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) ^= USBFS_UEP_T_TOG; + ctx->USBFS_SetupReqLen -= len; + ctx->pCtrlPayloadPtr += len; + } +#endif + } + else + { + switch( USBFSCTX.USBFS_SetupReqCode ) + { + case USB_GET_DESCRIPTOR: + break; + + case USB_SET_ADDRESS: + USBFS->DEV_ADDR = ( USBFS->DEV_ADDR & USBFS_UDA_GP_BIT ) | ctx->USBFS_DevAddr; + break; + + default: + break; + } + } + } + break; + + /* data-out stage processing */ + case CUIS_TOKEN_OUT: + len = USBFS->RX_LEN; + switch( ep ) + { + /* end-point 0 data out interrupt */ + case DEF_UEP0: + if( intfgst & CRB_UIS_TOG_OK ) + { +#if FUSB_HID_USER_REPORTS + if( ctx->USBFS_SetupReqCode == HID_SET_REPORT ) + { + uint8_t * cptr = ctx->pCtrlPayloadPtr; + if( !cptr ) + { + HandleHidUserReportDataOut( ctx, ctrl0buff, len ); + } + else + { + int remain = ctx->USBFS_SetupReqLen - len; + if( remain < 0 ) + { + len += remain; + remain = 0; + } + copyBuffer( cptr, ctrl0buff, len ); + ctx->USBFS_SetupReqLen = remain; + if( remain > 0 ) + ctx->pCtrlPayloadPtr = cptr + len; + else + ctx->pCtrlPayloadPtr = 0; + } + } +#endif +#if FUSB_USER_HANDLERS + if ( ctx->USBFS_SetupReqCode != HID_SET_REPORT ) + { + HandleDataOut( ctx, ep, ctrl0buff, len ); + } +#endif + if( ctx->USBFS_SetupReqLen == 0 ) + { +#if FUSB_HID_USER_REPORTS + copyBufferComplete(); + if( ctx->USBFS_SetupReqCode == HID_SET_REPORT ) + HandleHidUserReportOutComplete( ctx ); +#endif + // Only set this flag for OUT requests (e.g. SET_LINE_CODING). + // For IN requests (e.g. GET_DESCRIPTOR), don't set it. + if ( ( ctx->USBFS_SetupReqType & USB_REQ_TYP_IN ) == 0 ) + { + ctx->USBFS_errata_dont_send_endpoint_in_window = 1; + } + UEP_CTRL_LEN(0) = 0; + UEP_CTRL_TX(0) = USBFS_UEP_T_TOG | CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_T_RES_ACK; + } + else + { +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(0) ^= USBFS_UEP_R_TOG; +#else + UEP_CTRL_RX(0) ^= USBFS_UEP_R_TOG; +#endif + } + } + break; + + default: +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(ep) ^= USBFS_UEP_R_TOG; +#else + UEP_CTRL_RX(ep) ^= USBFS_UEP_R_TOG; +#endif +#if FUSB_USER_HANDLERS + HandleDataOut( ctx, ep, ctx->ENDPOINTS[ep], len ); +#endif + break; + } + break; + + /* Setup stage processing */ + case CUIS_TOKEN_SETUP: +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) +#if !defined (CH32V10x) + if (!(USBFS->INT_ST & 0x80)) goto replycomplete; +#endif + UEP_CTRL_TX(0) = USBFS_UEP_T_RES_NAK | USBFS_UEP_T_TOG | USBFS_UEP_R_RES_NAK | USBFS_UEP_R_TOG | CHECK_USBFS_UEP_AUTO_TOG; +#else + UEP_CTRL_TX(0) = USBFS_UEP_T_RES_NAK | CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_T_TOG; + UEP_CTRL_RX(0) = USBFS_UEP_R_RES_NAK | CHECK_USBFS_UEP_R_AUTO_TOG | USBFS_UEP_R_TOG; +#endif + + /* Store All Setup Values */ + int USBFS_SetupReqType = USBFSCTX.USBFS_SetupReqType = pUSBFS_SetupReqPak->bmRequestType; + int USBFS_SetupReqCode = USBFSCTX.USBFS_SetupReqCode = pUSBFS_SetupReqPak->bRequest; + int USBFS_SetupReqLen = USBFSCTX.USBFS_SetupReqLen = pUSBFS_SetupReqPak->wLength; + int USBFS_SetupReqIndex = pUSBFS_SetupReqPak->wIndex; + int USBFS_IndexValue = USBFSCTX.USBFS_IndexValue = ( pUSBFS_SetupReqPak->wIndex << 16 ) | pUSBFS_SetupReqPak->wValue; + if( usb_debug ) printf( "[USB] SETUP: %02x %02x %02d %02x %04x\n", USBFS_SetupReqType, USBFS_SetupReqCode, USBFS_SetupReqLen, USBFS_SetupReqIndex, USBFS_IndexValue ); + len = 0; + + if( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) + { +#if FUSB_HID_INTERFACES > 0 || FUSB_USER_HANDLERS + if( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) == USB_REQ_TYP_CLASS ) + { + /* Class Request */ + switch( USBFS_SetupReqCode ) + { +#if FUSB_HID_INTERFACES > 0 + case HID_SET_REPORT: +#if FUSB_HID_USER_REPORTS + len = HandleHidUserSetReportSetup( ctx, pUSBFS_SetupReqPak ); + if( len < 0 ) goto sendstall; + ctx->USBFS_SetupReqLen = len; + UEP_CTRL_LEN(0) = 0; + // Previously would have been a CTRL_RX = ACK && TOG, but not here on the 203. +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(0) = USBFS_UEP_R_RES_ACK | USBFS_UEP_R_TOG | CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_T_TOG; + // R8_UEP0_CTRL = (R8_UEP0_CTRL & ~MASK_UEP_R_RES) | UEP_R_RES_ACK ; +#else + UEP_CTRL_RX(0) = CHECK_USBFS_UEP_R_AUTO_TOG | USBFS_UEP_R_RES_ACK | USBFS_UEP_R_TOG; + UEP_CTRL_TX(0) = CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_T_TOG; +#endif + goto replycomplete; + + case HID_GET_REPORT: + len = HandleHidUserGetReportSetup( ctx, pUSBFS_SetupReqPak ); + if( len < 0 ) goto sendstall; + ctx->USBFS_SetupReqLen = len; + len = len >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : len; + if( !ctx->pCtrlPayloadPtr ) + { + len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); + } + else + { + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + ctx->pCtrlPayloadPtr += len; + } + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) = CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_T_RES_ACK | USBFS_UEP_T_TOG; + ctx->USBFS_SetupReqLen -= len; + goto replycomplete; +#endif + break; + + case HID_SET_IDLE: + if( USBFS_SetupReqIndex < FUSB_HID_INTERFACES ) + USBFSCTX.USBFS_HidIdle[ USBFS_SetupReqIndex ] = (uint8_t)( USBFS_IndexValue >> 8 ); + break; + case HID_SET_PROTOCOL: + if ( USBFS_SetupReqIndex < FUSB_HID_INTERFACES ) + USBFSCTX.USBFS_HidProtocol[USBFS_SetupReqIndex] = (uint8_t)USBFS_IndexValue; + break; + + case HID_GET_IDLE: + if( USBFS_SetupReqIndex < FUSB_HID_INTERFACES ) + { + ctrl0buff[0] = USBFSCTX.USBFS_HidIdle[ USBFS_SetupReqIndex ]; + len = 1; + } + break; + + case HID_GET_PROTOCOL: + if( USBFS_SetupReqIndex < FUSB_HID_INTERFACES ) + { + ctrl0buff[0] = USBFSCTX.USBFS_HidProtocol[ USBFS_SetupReqIndex ]; + len = 1; + } + break; +#endif + default: +#if FUSB_USER_HANDLERS + len = HandleSetupCustom( ctx, USBFS_SetupReqCode ); + + if( len ) + { + if( len < 0 ) { + len = 0; + ctx->USBFS_SetupReqLen = 0; + } + else + { + ctx->USBFS_SetupReqLen = len; + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + // printf("%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", ctrl0buff[0], ctrl0buff[1], ctrl0buff[2], ctrl0buff[3], ctrl0buff[4], ctrl0buff[5], ctrl0buff[6]); + ctx->pCtrlPayloadPtr += len; + } + + if( ctx->USBFS_SetupReqType & DEF_UEP_IN || ctx->USBFS_SetupReqLen == 0) + { + len = len >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : len; + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK; + ctx->USBFS_SetupReqLen -= len; + } +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + else UEP_CTRL_TX(0)= USBFS_UEP_R_TOG|USBFS_UEP_R_RES_ACK; +#else + else UEP_CTRL_RX(0)= USBFS_UEP_R_TOG|USBFS_UEP_R_RES_ACK; +#endif + // UEP_CTRL_LEN(0) = len; + // UEP_CTRL_TX(0) = CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_T_RES_ACK | USBFS_UEP_T_TOG; + // ctx->USBFS_SetupReqLen -= len; + // goto epzero_rxtx; + goto replycomplete; + } + else +#endif + { + goto sendstall; + } + break; + } + } +#else + ; +#endif + } + else + { + /* usb standard request processing */ + switch( USBFS_SetupReqCode ) + { + /* get device/configuration/string/report/... descriptors */ + case USB_GET_DESCRIPTOR: + { + const struct descriptor_list_struct * e = descriptor_list; + const struct descriptor_list_struct * e_end = e + DESCRIPTOR_LIST_ENTRIES; + for( ; e != e_end; e++ ) + { + if( e->lIndexValue == (uint32_t)USBFS_IndexValue ) + { + ctx->pCtrlPayloadPtr = (uint8_t*)e->addr; + len = e->length; + break; + } + } + if( e == e_end ) + goto sendstall; + if( len > USBFS_SetupReqLen ) + len = USBFS_SetupReqLen; + ctx->USBFS_SetupReqLen = len; + + break; + } + + /* Set usb address */ + case USB_SET_ADDRESS: + ctx->USBFS_DevAddr = (uint8_t)( ctx->USBFS_IndexValue & 0xFF ); + // NOTE: Do not actually set addres here! If we do, we won't get the PID_IN associated with this SETUP. + break; + + /* Get usb configuration now set */ + case USB_GET_CONFIGURATION: + ctrl0buff[0] = ctx->USBFS_DevConfig; + if( ctx->USBFS_SetupReqLen > 1 ) + ctx->USBFS_SetupReqLen = 1; + break; + + /* Set usb configuration to use */ + case USB_SET_CONFIGURATION: + ctx->USBFS_DevConfig = (uint8_t)( ctx->USBFS_IndexValue & 0xFF ); + ctx->USBFS_DevEnumStatus = 0x01; + break; + + /* Clear or disable one usb feature */ + case USB_CLEAR_FEATURE: +#if FUSB_SUPPORTS_SLEEP + if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { + /* clear one device feature */ + if( (uint8_t)( USBFS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) + { + /* clear usb sleep status, device not prepare to sleep */ + ctx->USBFS_DevSleepStatus &= ~0x01; + } + else + { + goto sendstall; + } + } + else +#endif + if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + if( (uint8_t)( USBFS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) + { + /* Clear End-point Feature */ + if( ep < FUSB_CONFIG_EPS ) + { + // UEP_CTRL_TX(ep) = USBFS_UEP_T_RES_STALL | CHECK_USBFS_UEP_T_AUTO_TOG; + if( USBFS_SetupReqIndex & DEF_UEP_IN && ctx->endpoint_mode[ep] == -1 ) UEP_CTRL_TX(ep) = USBFS_UEP_T_RES_NAK; +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + else if( USBFS_SetupReqIndex & DEF_UEP_OUT && ctx->endpoint_mode[ep] == 1 ) UEP_CTRL_TX(ep) = USBFS_UEP_R_RES_ACK; +#else + else if( USBFS_SetupReqIndex & DEF_UEP_OUT && ctx->endpoint_mode[ep] == 1 ) UEP_CTRL_RX(ep) = USBFS_UEP_R_RES_ACK; +#endif + else goto sendstall; + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + break; + + /* set or enable one usb feature */ + case USB_SET_FEATURE: + if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { +#if FUSB_SUPPORTS_SLEEP + /* Set Device Feature */ + if( (uint8_t)( USBFS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) + { + /* Set Wake-up flag, device prepare to sleep */ + USBFS_DevSleepStatus |= 0x01; + } + else +#endif + { + goto sendstall; + } + } + else if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + /* Set Endpoint Feature */ + if( (uint8_t)( USBFS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) + { + if( ep < FUSB_CONFIG_EPS ) + { + if( (USBFS_SetupReqIndex & DEF_UEP_IN) && ctx->endpoint_mode[ep] == -1 )UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL; +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + else if( (USBFS_SetupReqIndex & DEF_UEP_OUT) && ctx->endpoint_mode[ep] == 1 )UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_STALL; +#else + else if( (USBFS_SetupReqIndex & DEF_UEP_OUT) && ctx->endpoint_mode[ep] == 1 )UEP_CTRL_RX(ep) = ( UEP_CTRL_RX(ep) & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_STALL; +#endif + else goto sendstall; + } + } + else + goto sendstall; + } + else + goto sendstall; + break; + + /* This request allows the host to select another setting for the specified interface */ + case USB_GET_INTERFACE: + ctrl0buff[0] = 0x00; + if( USBFS_SetupReqLen > 1 ) USBFS_SetupReqLen = 1; + break; + + case USB_SET_INTERFACE: + break; + + /* host get status of specified device/interface/end-points */ + case USB_GET_STATUS: + ctrl0buff[0] = 0x00; + ctrl0buff[1] = 0x00; + if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { +#if FUSB_SUPPORTS_SLEEP + ctrl0buff[0] = (ctx->USBFS_DevSleepStatus & 0x01)<<1; +#else + ctrl0buff[0] = 0x00; +#endif + } + else if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + if( ep < FUSB_CONFIG_EPS ) + { + if( USBFS_SetupReqIndex & DEF_UEP_IN && ctx->endpoint_mode[ep] == -1 ) ctrl0buff[0] = ( UEP_CTRL_TX(ep) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL; +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + else if( USBFS_SetupReqIndex & DEF_UEP_OUT && ctx->endpoint_mode[ep] == 1 ) ctrl0buff[0] = ( UEP_CTRL_TX(ep) & USBFS_UEP_R_RES_MASK ) == USBFS_UEP_R_RES_STALL; +#else + else if( USBFS_SetupReqIndex & DEF_UEP_OUT && ctx->endpoint_mode[ep] == 1 ) ctrl0buff[0] = ( UEP_CTRL_TX(ep) & USBFS_UEP_R_RES_MASK ) == USBFS_UEP_R_RES_STALL; +#endif + else goto sendstall; + } + + else + goto sendstall; + } + else + goto sendstall; + if( USBFS_SetupReqLen > 2 ) + USBFS_SetupReqLen = 2; + break; + + default: + goto sendstall; + break; + } + } + // epzero_rxtx: + { + /* end-point 0 data Tx/Rx */ + if( USBFS_SetupReqType & DEF_UEP_IN ) + { + len = ( USBFS_SetupReqLen > DEF_USBD_UEP0_SIZE )? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen; + USBFS_SetupReqLen -= len; + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) = USBFS_UEP_T_RES_ACK; + // R8_UEP0_CTRL = (R8_UEP0_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; + } + else + { + if( USBFS_SetupReqLen == 0 ) + { + UEP_CTRL_LEN(0) = 0; + UEP_CTRL_TX(0) = USBFS_UEP_T_RES_ACK | USBFS_UEP_T_TOG; + // R8_UEP0_CTRL = (R8_UEP0_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; + } + else + { +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(0) = CHECK_USBFS_UEP_T_AUTO_TOG | USBFS_UEP_R_RES_ACK | USBFS_UEP_R_TOG; + // R8_UEP0_CTRL = (R8_UEP0_CTRL & ~MASK_UEP_R_RES) | UEP_R_RES_ACK ; +#else + UEP_CTRL_RX(0) = CHECK_USBFS_UEP_R_AUTO_TOG | USBFS_UEP_R_RES_ACK | USBFS_UEP_R_TOG; +#endif + } + } + } + break; + + // This might look a little weird, for error handling but it saves a nontrivial amount of storage, and simplifies + // control flow to hard-abort here. + sendstall: + // if one request not support, return stall. Stall means permanent error. +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(0) = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL | USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL; +#else + UEP_CTRL_TX(0) = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL; + UEP_CTRL_RX(0) = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL; +#endif + replycomplete: + break; + + /* Sof pack processing */ + //case CUIS_TOKEN_SOF: + // break; + + default : + break; + } + // printf("clear transfer int flag\n"); + USBFS->INT_FG = CRB_UIF_TRANSFER; + } + else if( intfgst & CRB_UIF_BUS_RST ) + { + if( usb_debug ) printf("[USB] RESET\n"); + /* usb reset interrupt processing */ + ctx->USBFS_DevConfig = 0; + ctx->USBFS_DevAddr = 0; + ctx->USBFS_DevSleepStatus = 0; + ctx->USBFS_DevEnumStatus = 0; + + USBFS->DEV_ADDR = 0; + USBFS_InternalFinishSetup(); + USBFS->INT_FG = CRB_UIF_BUS_RST; + } + else if( intfgst & CRB_UIF_SUSPEND ) + { + if( usb_debug ) printf("[USB] SUSPEND\n"); + USBFS->INT_FG = USBFS_UMS_SUSPEND; + Delay_Us(10); + /* usb suspend interrupt processing */ + if( USBFS->MIS_ST & USBFS_UMS_SUSPEND ) + { + ctx->USBFS_DevSleepStatus |= 0x02; + if( ctx->USBFS_DevSleepStatus == 0x03 ) + { + /* Handling usb sleep here */ + //TODO: MCU_Sleep_Wakeup_Operate( ); + } + } + else + { + ctx->USBFS_DevSleepStatus &= ~0x02; + } + + } + else + { + /* other interrupts */ + USBFS->INT_FG = intfgst & 0xff; + if( usb_debug) printf("[USB] intfgst = %04x\n",intfgst); + } + +#if FUSB_IO_PROFILE + funDigitalWrite( DEBUG_PIN, 0 ); +#endif + +#if FUSB_USE_HPE + // asm volatile( "mret" ); +#endif +} + +void USBFS_InternalFinishSetup() +{ + +#if FUSB_EP1_MODE + USBFSCTX.endpoint_mode[1] = FUSB_EP1_MODE; +#if FUSB_EP1_MODE > 0 + USBFS->UEP4_1_MOD = USBFS_UEP1_TX_EN; +#else + USBFS->UEP4_1_MOD = USBFS_UEP1_RX_EN; +#endif +#endif +#if FUSB_EP4_MODE + USBFSCTX.endpoint_mode[4] = FUSB_EP4_MODE; +#if FUSB_EP4_MODE > 0 + USBFS->UEP4_1_MOD |= USBFS_UEP4_TX_EN; +#else + USBFS->UEP4_1_MOD |= USBFS_UEP4_RX_EN; +#endif +#endif + +#if FUSB_EP2_MODE + USBFSCTX.endpoint_mode[2] = FUSB_EP2_MODE; +#if FUSB_EP2_MODE > 0 + USBFS->UEP2_3_MOD = USBFS_UEP2_TX_EN; +#else + USBFS->UEP2_3_MOD = USBFS_UEP2_RX_EN; +#endif +#endif +#if FUSB_EP3_MODE + USBFSCTX.endpoint_mode[3] = FUSB_EP3_MODE; +#if FUSB_EP3_MODE > 0 + USBFS->UEP2_3_MOD |= USBFS_UEP3_TX_EN; +#else + USBFS->UEP2_3_MOD |= USBFS_UEP3_RX_EN; +#endif +#endif + +#if FUSB_EP5_MODE + USBFSCTX.endpoint_mode[5] = FUSB_EP5_MODE; +#if FUSB_EP5_MODE > 0 +#if defined (CH5xx) || defined (CH32X03x) + USBFS->UEP567_MOD = USBFS_UEP5_TX_EN; +#else + USBFS->UEP5_6_MOD = USBFS_UEP5_TX_EN; +#endif +#else +#if defined (CH5xx) || defined (CH32X03x) + USBFS->UEP567_MOD = USBFS_UEP5_RX_EN; +#else + USBFS->UEP5_6_MOD = USBFS_UEP5_RX_EN; +#endif +#endif +#endif +#if FUSB_EP6_MODE + USBFSCTX.endpoint_mode[6] = FUSB_EP6_MODE; +#if FUSB_EP6_MODE > 0 +#if defined (CH5xx) || defined (CH32X03x) + USBFS->UEP567_MOD = USBFS_UEP6_TX_EN; +#else + USBFS->UEP5_6_MOD |= USBFS_UEP6_TX_EN; +#endif +#else +#if defined (CH5xx) || defined (CH32X03x) + USBFS->UEP567_MOD |= USBFS_UEP6_RX_EN; +#else + USBFS->UEP5_6_MOD |= USBFS_UEP6_RX_EN; +#endif +#endif +#endif + +#if FUSB_EP7_MODE + USBFSCTX.endpoint_mode[7] = FUSB_EP7_MODE; +#if FUSB_EP7_MODE > 0 +#if defined (CH5xx) || defined (CH32X03x) + USBFS->UEP567_MOD |= USBFS_UEP7_TX_EN; +#else + USBFS->UEP7_MOD = USBFS_UEP1_TX_EN; +#endif +#else +#if defined (CH5xx) || defined (CH32X03x) + USBFS->UEP567_MOD |= USBFS_UEP7_RX_EN; +#else + USBFS->UEP7_MOD = USBFS_UEP1_RX_EN; +#endif +#endif +#endif + +#if !defined (FUSB_CONFIG_EPS) || !FUSB_CONFIG_EPS +#error You must have at least EP0! +#endif + + for( int i = 0; i < FUSB_CONFIG_EPS; i++ ) + { + UEP_DMA(i) = (uintptr_t)USBFSCTX.ENDPOINTS[i]; + } + +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(0) = USBFS_UEP_T_RES_NAK | USBFS_UEP_R_RES_ACK | CHECK_USBFS_UEP_T_AUTO_TOG; +#else + UEP_CTRL_TX(0) = USBFS_UEP_T_RES_NAK | CHECK_USBFS_UEP_T_AUTO_TOG; + UEP_CTRL_RX(0) = USBFS_UEP_R_RES_ACK | CHECK_USBFS_UEP_R_AUTO_TOG; +#endif + + for( int i = 1; i < FUSB_CONFIG_EPS; i++ ) + { + if( USBFSCTX.endpoint_mode[i] > 0 ) + { + UEP_CTRL_TX(i) = USBFS_UEP_T_RES_NAK; + } + else if( USBFSCTX.endpoint_mode[i] < 0 ) + { +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + UEP_CTRL_TX(i) = USBFS_UEP_R_RES_ACK; +#else + UEP_CTRL_RX(i) = USBFS_UEP_R_RES_ACK; +#endif + } + USBFSCTX.USBFS_Endp_Busy[i] = 0; + } +} + +int USBFSSetup() +{ +#if defined (CH32V10x) +#if (FUNCONF_SYSTEM_CORE_CLOCK != 72000000) && (FUNCONF_SYSTEM_CORE_CLOCK != 48000000) +#error CH32V103 needs 72MHz or 48MHz main clock for USB to work +#endif +#if FUNCONF_SYSTEM_CORE_CLOCK == 48000000 + RCC->CFGR0 |= RCC_USBPRE; // Disable 1.5 divider for USB clock +#endif +#if defined (FUSB_VDD_5V) && FUSB_VDD_5V + EXTEN->EXTEN_CTR |= EXTEN_USB_5V_SEL; +#endif + EXTEN->EXTEN_CTR |= EXTEN_USBFS_IO_EN; +#endif + +#if defined (CH32V20x) || defined (CH32V30x) || defined(CH32L103) +#ifdef CH32V30x_D8C + RCC->CFGR2 = RCC_USBHSSRC | RCC_USBHSPLL | 1<< RCC_USBHSCLK_OFFSET | RCC_USBHSPLLSRC | 1 << RCC_USBHSDIV_OFFSET; + RCC->AHBPCENR |= RCC_USBHSEN; +#else + // USBPRE[1:0] = 10: Divided by 3 (when PLLCLK=144MHz); + // Must be done before enabling clock to USBFS tree. +#if FUNCONF_SYSTEM_CORE_CLOCK == 144000000 + RCC->CFGR0 = (RCC->CFGR0 & ~(3<<22)) | (2<<22); +#elif FUNCONF_SYSTEM_CORE_CLOCK == 96000000 + RCC->CFGR0 = (RCC->CFGR0 & ~(3<<22)) | (1<<22); +#elif FUNCONF_SYSTEM_CORE_CLOCK == 48000000 + RCC->CFGR0 = (RCC->CFGR0 & ~(3<<22)); +#elif FUNCONF_SYSTEM_CORE_CLOCK == 240000000 +#error CH32V20x/30x is unstable at 240MHz +#else +#error CH32V20x/30x need 144/96/48MHz main clock for USB to work +#endif +#endif +#endif + +#if defined (CH32X03x) + RCC->APB2PCENR |= RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC; +// #ifdef FUSB_VDD_5V + // AFIO->CTLR = (AFIO->CTLR & ~(UDP_PUE_MASK | UDM_PUE_MASK | USB_PHY_V33)) | UDP_PUE_10K | USB_IOEN; +// #else + AFIO->CTLR = (AFIO->CTLR & ~(UDP_PUE_MASK | UDM_PUE_MASK )) | USB_PHY_V33 | UDP_PUE_1K5 | USB_IOEN; +// #endif + // Enable PC16/17 Alternate Function (USB) + // According to EVT, GPIO16 = GPIO_Mode_IN_FLOATING, GPIO17 = GPIO_Mode_IPU + GPIOC->CFGXR = ( GPIOC->CFGXR & ~( (0xf<<(4*0)) | (0xf<<(4*1)) ) ) | + (((GPIO_CFGLR_IN_FLOAT)<<(4*0)) | (((GPIO_CFGLR_IN_PUPD)<<(4*1)))); // MSBs are CNF, LSBs are MODE + GPIOC->BSXR = 1<<1; // PC17 on. +#endif + +#if defined (CH5xx) +#if defined (CH570_CH572) + R16_PIN_ALTERNATE |= RB_PIN_USB_EN | RB_UDP_PU_EN; +#elif defined (CH584_CH585) + R16_PIN_CONFIG |= RB_PIN_USB_EN | RB_UDP_PU_EN; +#else + R16_PIN_ANALOG_IE |= RB_PIN_USB_IE | RB_PIN_USB_DP_PU; +#endif + +#else + +#if defined (CH32V10x) || defined (CH32V30x) || defined(CH32L103) + RCC->APB2PCENR |= RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA; +#endif + +#if defined (CH32V20x) + RCC->APB2PCENR |= RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB; +#endif + + RCC->AHBPCENR |= RCC_USBFS | RCC_AHBPeriph_DMA1; + +#endif + + // Force module to reset. + USBFS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL; + USBFS->BASE_CTRL = 0x00; + Delay_Us(10); + + // Enter device mode. + USBFS->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_TRANSFER | USBFS_UIE_BUS_RST; + USBFS->DEV_ADDR = 0x00; + USBFS->BASE_CTRL = USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN | USBFS_UC_DEV_PU_EN; + USBFS->INT_FG = 0xff; + USBFS_InternalFinishSetup(); + USBFS->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN; + + NVIC_EnableIRQ( USB_IRQn ); + +#if defined (CH32V30x) + USBFS->OTG_CR = 0; //Note says only valid on 305, 307. +#endif + +// #ifndef CH32X03x +// // Actually go on-bus. +// USBFS->BASE_CTRL |= USBFS_UC_DEV_PU_EN; +// #endif + +#if FUSB_IO_PROFILE + funPinMode( DEBUG_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); +#endif + + // Go on-bus. + return 0; +} + +#ifdef CH5xx +void USBFSReset() +{ + NVIC_DisableIRQ( USB_IRQn ); +#if defined (CH570_CH572) + R16_PIN_ALTERNATE &= ~(RB_PIN_USB_EN | RB_UDP_PU_EN); +#elif defined (CH584_CH585) + R16_PIN_CONFIG &= ~(RB_PIN_USB_EN | RB_UDP_PU_EN); +#else + R16_PIN_ANALOG_IE &= ~(RB_PIN_USB_IE | RB_PIN_USB_DP_PU); +#endif + USBFS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL; + USBFS->BASE_CTRL = 0x00; + Delay_Us(10); +} +#endif + +static inline uint8_t * USBFS_GetEPBufferIfAvailable( int endp ) +{ + if( USBFSCTX.USBFS_Endp_Busy[ endp ] ) return 0; + return USBFSCTX.ENDPOINTS[ endp ]; +} + +static inline int USBFS_SendEndpoint( int endp, int len ) +{ + if( USBFSCTX.USBFS_errata_dont_send_endpoint_in_window || USBFSCTX.USBFS_Endp_Busy[ endp ] ) return -1; + // This prevents sending while ep0 is receiving + if( USBFSCTX.USBFS_SetupReqLen > 0 ) return -2; +#if defined (CH5xx) || defined (CH32X03x) + // Check RB_UIS_SETUP_ACT + if( (USBFS->INT_ST & 0x80) ) return -3; +#endif + NVIC_DisableIRQ( USB_IRQn ); + UEP_CTRL_LEN( endp ) = len; + UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_ACK; + USBFSCTX.USBFS_Endp_Busy[ endp ] = 1; + NVIC_EnableIRQ( USB_IRQn ); + return 0; +} + +int USBFS_SendEndpointNEW( int endp, uint8_t* data, int len, int copy) +{ + if( USBFSCTX.USBFS_errata_dont_send_endpoint_in_window || USBFSCTX.USBFS_Endp_Busy[ endp ] ) return -1; + // This prevents sending while ep0 is receiving + if( USBFSCTX.USBFS_SetupReqLen > 0 ) return USBFSCTX.USBFS_SetupReqLen; +#if defined (CH5xx) || defined (CH32X03x) + // Check RB_UIS_SETUP_ACT + if( (USBFS->INT_ST & 0x80) ) return -3; +#endif + if ( len ) + { + if( copy ) + { + UEP_DMA( endp ) = (uintptr_t)USBFSCTX.ENDPOINTS[endp]; + copyBuffer( USBFSCTX.ENDPOINTS[endp], data, len ); + copyBufferComplete(); + } + else UEP_DMA( endp ) = (uintptr_t)data; + } + // NVIC_DisableIRQ( USB_IRQn ); + UEP_CTRL_LEN( endp ) = len; + UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_ACK; + USBFSCTX.USBFS_Endp_Busy[ endp ] = 1; + // NVIC_EnableIRQ( USB_IRQn ); + return 0; +} + +static inline int USBFS_SendACK( int endp, int tx ) +{ + if( tx ) UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_ACK; +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + else UEP_CTRL_TX(endp) = ( UEP_CTRL_TX(endp) & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_ACK; +#else + else UEP_CTRL_RX(endp) = ( UEP_CTRL_RX(endp) & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_ACK; +#endif + return 0; +} + +static inline int USBFS_SendNAK( int endp, int tx ) +{ + if( tx ) UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_NAK; +#if defined (CH5xx) || defined (CH32X03x) || defined (CH32V10x) + else UEP_CTRL_TX(endp) = ( UEP_CTRL_TX(endp) & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_NAK; +#else + else UEP_CTRL_RX(endp) = ( UEP_CTRL_RX(endp) & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_NAK; +#endif + return 0; +} + +#if defined( FUNCONF_USE_USBPRINTF ) && FUNCONF_USE_USBPRINTF +int HandleInRequest( struct _USBState *ctx, int endp, uint8_t *data, int len ) +{ + return 0; +} + +void HandleDataOut( struct _USBState *ctx, int endp, uint8_t *data, int len ) +{ + if ( endp == 0 ) + { + ctx->USBFS_SetupReqLen = 0; // To ACK + } +} + +int HandleSetupCustom( struct _USBState *ctx, int setup_code ) +{ + int ret = -1; + if ( ctx->USBFS_SetupReqType & USB_REQ_TYP_CLASS ) + { + switch ( setup_code ) + { + case CDC_SET_LINE_CODING: + case CDC_SET_LINE_CTLSTE: + case CDC_SEND_BREAK: ret = ( ctx->USBFS_SetupReqLen ) ? ctx->USBFS_SetupReqLen : -1; break; + case CDC_GET_LINE_CODING: ret = ctx->USBFS_SetupReqLen; break; + default: ret = 0; break; + } + } + else + { + ret = 0; // Go to STALL + } + return ret; +} +#endif // FUNCONF_USE_USBPRINTF + diff --git a/inc/extralibs/fsusb.h b/inc/extralibs/fsusb.h new file mode 100644 index 0000000..616c67f --- /dev/null +++ b/inc/extralibs/fsusb.h @@ -0,0 +1,419 @@ +#ifndef _FSUSB_H +#define _FSUSB_H + +#include +#include "ch32fun.h" +#include "usb_defines.h" +#include "usb_config.h" + +#if defined(FUSB_FROM_RAM) && (FUSB_FROM_RAM) +#if defined(CH5xx) +#define __USBFS_FUN_ATTRIBUTE __attribute__((section(".srodata"), used)) +#else +#define __USBFS_FUN_ATTRIBUTE +#endif +#else +#define __USBFS_FUN_ATTRIBUTE +#endif + +#if defined(CH5xx) || defined(CH32X03x) || defined(CH32V10x) +#if !defined (CH32X03x) && !defined(CH32V10x) +#define USBFS_BASE USB_BASE_ADDR +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t USB_STATUS; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) + __IO uint8_t INT_ST; + __IO uint8_t RX_LEN; + __IO uint8_t Reserved0; + __IO uint16_t Reserved1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP567_MOD; + __IO uint8_t Reserved2; + __IO uint16_t UEP0_DMA; + __IO uint16_t Reserved3; + __IO uint16_t UEP1_DMA; + __IO uint16_t Reserved4; + __IO uint16_t UEP2_DMA; + __IO uint16_t Reserved5; + __IO uint16_t UEP3_DMA; + __IO uint16_t Reserved6; + __IO uint8_t UEP0_TX_LEN; + __IO uint8_t Reserved7; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t Reserved8; + __IO uint8_t UEP1_TX_LEN; + __IO uint8_t Reserved9; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t Reserved10; + __IO uint8_t UEP2_TX_LEN; + __IO uint8_t Reserved11; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t Reserved12; + __IO uint8_t UEP3_TX_LEN; + __IO uint8_t Reserved13; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t Reserved14; + __IO uint8_t UEP4_TX_LEN; + __IO uint8_t Reserved15; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t Reserved16; + __IO uint32_t Reserved17; + __IO uint32_t Reserved18; + __IO uint32_t Reserved19; + __IO uint32_t Reserved20; + __IO uint32_t Reserved21; + __IO uint32_t Reserved22; + __IO uint32_t Reserved23; + __IO uint32_t Reserved24; + __IO uint16_t UEP5_DMA; + __IO uint16_t UEP6_DMA; + __IO uint16_t UEP7_DMA; + __IO uint32_t Reserved25; + __IO uint8_t UEP5_TX_LEN; + __IO uint8_t Reserved26; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t Reserved27; + __IO uint8_t UEP6_TX_LEN; + __IO uint8_t Reserved28; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t Reserved29; + __IO uint8_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t Reserved30; + __IO uint32_t EPX_MODE; +} USBFS_TypeDef; + +#define UEP_CTRL_LEN(n) (((uint8_t*)&USBFS->UEP0_TX_LEN)[n*4]) +#define UEP_CTRL_TX(n) (((uint8_t*)&USBFS->UEP0_TX_CTRL)[n*4]) +#define UEP_CTRL_RX(n) (((uint8_t*)&USBFS->UEP0_TX_CTRL)[n*4]) +#define UEP_DMA(n) (((uint16_t*)&USBFS->UEP0_DMA)[n*2]) +#endif + +#if defined(CH32V10x) +#define USBFS_BASE 0x40023400 +#define USB_IRQn USBFS_IRQn +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t USB_STATUS; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) + __IO uint8_t INT_ST; + __IO uint8_t RX_LEN; + __IO uint8_t Reserved0; + __IO uint16_t Reserved1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint16_t UEP0_DMA; + __IO uint16_t Reserved3; + __IO uint16_t UEP1_DMA; + __IO uint16_t Reserved4; + __IO uint16_t UEP2_DMA; + __IO uint16_t Reserved5; + __IO uint16_t UEP3_DMA; + __IO uint16_t Reserved6; + __IO uint16_t UEP4_DMA; + __IO uint16_t Reserved7; + __IO uint16_t UEP5_DMA; + __IO uint16_t Reserved8; + __IO uint16_t UEP6_DMA; + __IO uint16_t Reserved9; + __IO uint16_t UEP7_DMA; + __IO uint16_t Reserved10; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t Reserved11; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t Reserved12; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t Reserved13; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t Reserved14; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t Reserved15; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t Reserved16; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t Reserved17; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t Reserved18; +} USBFS_TypeDef; + +#define UEP_CTRL_LEN(n) (((volatile uint16_t*)&USBFS->UEP0_TX_LEN)[n*2]) +#define UEP_CTRL_TX(n) (((volatile uint8_t*)&USBFS->UEP0_TX_CTRL)[n*4]) +#define UEP_CTRL_RX(n) (((volatile uint8_t*)&USBFS->UEP0_TX_CTRL)[n*4]) +#define UEP_DMA(n) (((volatile uint16_t*)&USBFS->UEP0_DMA)[n*2]) +#endif + +#if !defined (CH32X03x) +#define DEBUG_PIN PA8 + +#define DEF_USBD_UEP0_SIZE 64 /* usb hs/fs device end-point 0 size */ +#define UEP_SIZE 64 + +#define DEF_UEP_IN 0x80 +#define DEF_UEP_OUT 0x00 +#define DEF_UEP_BUSY 0x01 +#define DEF_UEP_FREE 0x00 + +#define DEF_UEP0 0 +#define DEF_UEP1 1 +#define DEF_UEP2 2 +#define DEF_UEP3 3 +#define DEF_UEP4 4 +#define DEF_UEP5 5 +#define DEF_UEP6 6 +#define DEF_UEP7 7 +#define UNUM_EP 8 + +#define USBFS_UEP_T_RES_MASK MASK_UEP_T_RES +#define USBFS_UEP_T_RES_ACK UEP_T_RES_ACK +#define USBFS_UEP_T_RES_NAK UEP_T_RES_NAK +#define USBFS_UEP_T_TOG RB_UEP_T_TOG +#define USBFS_UEP_T_RES_STALL UEP_T_RES_STALL + +#define USBFS_UEP_R_RES_MASK MASK_UEP_R_RES +#define USBFS_UEP_R_RES_ACK UEP_R_RES_ACK +#define USBFS_UEP_R_RES_NAK UEP_R_RES_NAK +#define USBFS_UEP_R_TOG RB_UEP_R_TOG +#define USBFS_UEP_R_RES_STALL UEP_R_RES_STALL + +#define USBFS_UDA_GP_BIT RB_UDA_GP_BIT +#define USBFS_UMS_SUSPEND RB_UMS_SUSPEND + +#define USBFS_UC_RESET_SIE RB_UC_RESET_SIE +#define USBFS_UC_CLR_ALL RB_UC_CLR_ALL +#define USBFS_UIE_SUSPEND RB_UIE_SUSPEND +#define USBFS_UIE_TRANSFER RB_UIE_TRANSFER +#define USBFS_UIE_BUS_RST RB_UIE_BUS_RST +#define USBFS_UC_INT_BUSY RB_UC_INT_BUSY +#define USBFS_UC_DMA_EN RB_UC_DMA_EN +#define USBFS_UC_DEV_PU_EN RB_UC_DEV_PU_EN + +#endif + +#define USBFS_UD_PORT_EN RB_UD_PORT_EN +#define USBFS_UD_PD_DIS RB_UD_PD_DIS + +#define USBFS_UEP1_RX_EN RB_UEP1_RX_EN +#define USBFS_UEP2_RX_EN RB_UEP2_RX_EN +#define USBFS_UEP3_RX_EN RB_UEP3_RX_EN +#define USBFS_UEP4_RX_EN RB_UEP4_RX_EN + +#define USBFS_UEP1_TX_EN RB_UEP1_TX_EN +#define USBFS_UEP2_TX_EN RB_UEP2_TX_EN +#define USBFS_UEP3_TX_EN RB_UEP3_TX_EN +#define USBFS_UEP4_TX_EN RB_UEP4_TX_EN + +#define CHECK_USBFS_UEP_AUTO_TOG RB_UEP_AUTO_TOG +#define CHECK_USBFS_UEP_T_AUTO_TOG RB_UEP_AUTO_TOG +// #define CHECK_USBFS_UEP_R_AUTO_TOG USBOTG_UEP_R_AUTO_TOG + +#define USBFS ((USBFS_TypeDef *)USBFS_BASE) + +#ifdef CH32X03x +#define UEP_CTRL_LEN(n) (((volatile uint16_t*)&USBFS->UEP0_TX_LEN)[n*2]) +#define UEP_CTRL_TX(n) (((volatile uint16_t*)&USBFS->UEP0_CTRL_H)[n*2]) +#define UEP_CTRL_RX(n) (((volatile uint16_t*)&USBFS->UEP0_CTRL_H)[n*2]) +#define UEP_DMA(n) (((volatile uint32_t*)&USBFS->UEP0_DMA)[n]) +#define DEBUG_PIN PB12 +#define USB_IRQn USBFS_IRQn +#endif + +#else + +#define DEBUG_PIN PB0 + +#define USBFS ((USBOTG_FS_TypeDef *)USBFS_BASE) + +#define UEP_CTRL_LEN(n) (((volatile uint16_t*)&USBFS->UEP0_TX_LEN)[n*2]) +#define UEP_CTRL_TX(n) (((volatile uint8_t*)&USBFS->UEP0_TX_CTRL)[n*4]) +#define UEP_CTRL_RX(n) (((volatile uint8_t*)&USBFS->UEP0_RX_CTRL)[n*4]) +#define UEP_DMA(n) (((volatile uint32_t*)&USBFS->UEP0_DMA)[n]) + +#define CHECK_USBFS_UEP_T_AUTO_TOG USBOTG_UEP_T_AUTO_TOG +#define CHECK_USBFS_UEP_R_AUTO_TOG USBOTG_UEP_R_AUTO_TOG + +#define USBFS_UEP_T_RES_MASK USBOTG_UEP_T_RES_MASK +#define USBFS_UEP_T_RES_ACK USBOTG_UEP_T_RES_ACK +#define USBFS_UEP_T_RES_NAK USBOTG_UEP_T_RES_NAK +#define USBFS_UEP_T_TOG USBOTG_UEP_T_TOG +#define USBFS_UEP_T_RES_STALL USBOTG_UEP_T_RES_STALL + +#define USBFS_UEP_R_RES_MASK USBOTG_UEP_R_RES_MASK +#define USBFS_UEP_R_RES_ACK USBOTG_UEP_R_RES_ACK +#define USBFS_UEP_R_RES_NAK USBOTG_UEP_R_RES_NAK +#define USBFS_UEP_R_TOG USBOTG_UEP_R_TOG +#define USBFS_UEP_R_RES_STALL USBOTG_UEP_R_RES_STALL + +// #define USBFS_UDA_GP_BIT USBOTG_UDA_GP_BIT +#define USBFS_UMS_SUSPEND USBOTG_UMS_SUSPEND +#define USBFS_UEP1_RX_EN USBOTG_UEP1_RX_EN +#define USBFS_UEP2_RX_EN USBOTG_UEP2_RX_EN +#define USBFS_UEP3_RX_EN USBOTG_UEP3_RX_EN +#define USBFS_UEP4_RX_EN USBOTG_UEP4_RX_EN + +#define USBFS_UEP1_TX_EN USBOTG_UEP1_TX_EN +#define USBFS_UEP2_TX_EN USBOTG_UEP2_TX_EN +#define USBFS_UEP3_TX_EN USBOTG_UEP3_TX_EN +#define USBFS_UEP4_TX_EN USBOTG_UEP4_TX_EN + +#define USBFS_UC_RESET_SIE USBOTG_UC_RESET_SIE +#define USBFS_UC_CLR_ALL USBOTG_UC_CLR_ALL +#define USBFS_UIE_SUSPEND USBOTG_UIE_SUSPEND +#define USBFS_UIE_TRANSFER USBOTG_UIE_TRANSFER +#define USBFS_UIE_BUS_RST USBOTG_UIE_BUS_RST +#define USBFS_UC_INT_BUSY USBOTG_UC_INT_BUSY +#define USBFS_UC_DMA_EN USBOTG_UC_DMA_EN +#define USBFS_UC_DEV_PU_EN USBOTG_UC_DEV_PU_EN +#define USBFS_UD_PD_DIS USBOTG_UD_PD_DIS +#define USBFS_UD_PORT_EN USBOTG_UD_PORT_EN + +#ifdef CH32V30x_D8C +#define USB_IRQn OTG_FS_IRQn +#else +#define USB_IRQn USBHD_IRQn +#endif + +#endif + +// Mask for the combined USBFS->INT_FG + USBFS->INT_ST +#define CRB_UIS_IS_NAK (1<<7) +#define CRB_U_TOG_OK (1<<6) +#define CRB_U_SIE_FREE (1<<5) +#define CRB_UIF_FIFO_OV (1<<4) +#define CRB_UIF_HST_SOF (1<<3) +#define CRB_UIF_SUSPEND (1<<2) +#define CRB_UIF_TRANSFER (1<<1) +#define CRB_UIF_BUS_RST (1<<0) + +#if defined(CH5xx) || defined(CH32X03x) || defined(CH32V10x) +#define CRB_UIF_SETUP_ACT (1<<15) +#endif +#define CRB_UIS_TOG_OK (1<<14) +#define CMASK_UIS_TOKEN (3<<12) +#define CMASK_UIS_ENDP (0xf<<8) + +#define CUIS_TOKEN_OUT 0x0 +#define CUIS_TOKEN_SOF 0x1 +#define CUIS_TOKEN_IN 0x2 +#define CUIS_TOKEN_SETUP 0x3 + +#define USBFS_PACKET_SIZE 64 + +extern uint32_t USBDEBUG0, USBDEBUG1, USBDEBUG2; + +struct _USBState; + +// Provided functions: +int USBFSSetup(); +uint8_t USBFS_Endp_DataUp(uint8_t endp, const uint8_t *pbuf, uint16_t len, uint8_t mod); +static inline uint8_t * USBFS_GetEPBufferIfAvailable( int endp ); +static inline int USBFS_SendEndpoint( int endp, int len ); +static inline int USBFS_SendACK( int endp, int tx ); +static inline int USBFS_SendNAK( int endp, int tx ); + +#if FUSB_USE_DMA7_COPY +static inline void copyBuffer( uint8_t * dest, const uint8_t * src, int len ); +static inline void copyBufferComplete(); +#endif + +// Implement the following: +#if FUSB_HID_USER_REPORTS +__USBFS_FUN_ATTRIBUTE int HandleHidUserGetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); +__USBFS_FUN_ATTRIBUTE int HandleHidUserSetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); +void HandleHidUserReportDataOut( struct _USBState * ctx, uint8_t * data, int len ); +int HandleHidUserReportDataIn( struct _USBState * ctx, uint8_t * data, int len ); +void HandleHidUserReportOutComplete( struct _USBState * ctx ); +#endif +#if FUSB_USER_HANDLERS +__USBFS_FUN_ATTRIBUTE int HandleInRequest( struct _USBState * ctx, int endp, uint8_t * data, int len ); +__USBFS_FUN_ATTRIBUTE void HandleDataOut( struct _USBState * ctx, int endp, uint8_t * data, int len ); +__USBFS_FUN_ATTRIBUTE int HandleSetupCustom( struct _USBState * ctx, int setup_code); +#endif + +typedef enum +{ + USBFS_EP_OFF = 0, + USBFS_EP_RX = -1, + USBFS_EP_TX = 1, +} USBFS_EP_mode; + +#ifndef FUSB_EP1_MODE +#define FUSB_EP1_MODE 0 +#endif +#ifndef FUSB_EP2_MODE +#define FUSB_EP2_MODE 0 +#endif +#ifndef FUSB_EP3_MODE +#define FUSB_EP3_MODE 0 +#endif +#ifndef FUSB_EP4_MODE +#define FUSB_EP4_MODE 0 +#endif +#ifndef FUSB_EP5_MODE +#define FUSB_EP5_MODE 0 +#endif +#ifndef FUSB_EP6_MODE +#define FUSB_EP6_MODE 0 +#endif +#ifndef FUSB_EP7_MODE +#define FUSB_EP7_MODE 0 +#endif + + +struct _USBState +{ + // Setup Request + uint8_t USBFS_SetupReqCode; + uint8_t USBFS_SetupReqType; + uint16_t USBFS_SetupReqLen; // Used for tracking place along send. + uint32_t USBFS_IndexValue; + + // USB Device Status + uint8_t USBFS_DevConfig; + uint8_t USBFS_DevAddr; + uint8_t USBFS_DevSleepStatus; + uint8_t USBFS_DevEnumStatus; + + uint8_t* pCtrlPayloadPtr; + + uint8_t ENDPOINTS[FUSB_CONFIG_EPS][64]; + USBFS_EP_mode endpoint_mode[FUSB_CONFIG_EPS+1]; // IN -1, OUT 1, OFF 0 + + #define CTRL0BUFF (USBFSCTX.ENDPOINTS[0]) + #define pUSBFS_SetupReqPak ((tusb_control_request_t*)CTRL0BUFF) + +#if FUSB_HID_INTERFACES > 0 + uint8_t USBFS_HidIdle[FUSB_HID_INTERFACES]; + uint8_t USBFS_HidProtocol[FUSB_HID_INTERFACES]; +#endif + volatile uint8_t USBFS_Endp_Busy[FUSB_CONFIG_EPS]; + volatile uint8_t USBFS_errata_dont_send_endpoint_in_window; +}; + +extern struct _USBState USBFSCTX; + +#include "fsusb.c" + +#endif + diff --git a/inc/extralibs/hsusb.c b/inc/extralibs/hsusb.c new file mode 100644 index 0000000..2087284 --- /dev/null +++ b/inc/extralibs/hsusb.c @@ -0,0 +1,1022 @@ +#include "hsusb.h" +#include "ch32fun.h" +#include +#include + +struct _USBState USBHSCTX; +volatile uint8_t usb_debug = 0; + +#ifdef CH584_CH585 +static inline void mcpy_raw( void *dst, void *start, void *end ) +{ + __asm__ volatile ( ".insn r 0x0f, 0x7, 0, x0, %3, %0, %1" + : "+r"(start), "+r"(dst) + : "r"(0), "r"(end) + : "memory" ); +} + +void * fast_memcpy( void *dst, void *src, uint32_t size ) +{ + uint32_t * end = src + size; + mcpy_raw( dst, src, (void *)end ); + + return dst; +} +#define copyBuffer fast_memcpy +// #define copyBuffer memcpy +#else +#define copyBuffer memcpy +#endif + +#if (FUSB_OUT_FLOW_CONTROL > 0) && (FUSB_USER_HANDLERS < 1) +#error FUSB_OUT_FLOW_CONTROL requires FUSB_USER_HANDLERS +#endif + +#if (USBHS_IMPL==2) +#define USBHS_IRQHandler USB2_DEVICE_IRQHandler +#define USBHS_IRQn USB2_DEVICE_IRQn +#endif + +#if FUSB_USE_HPE // Will it ever work? +// There is an issue with some registers apparently getting lost with HPE, just do it the slow way. +#if defined(CH584_CH585) +void USBHS_IRQHandler() __attribute__((section(".highcode"))) __attribute((interrupt)); +#else +void USBHS_IRQHandler() __attribute__((section(".text.vector_handler"))) __attribute((interrupt)); +#endif +// void USBHD_IRQHandler() __attribute__((section(".text.vector_handler"))) __attribute((naked)); +#else +#if defined(CH584_CH585) +void USBHS_IRQHandler() __attribute__((section(".highcode"))) __attribute((interrupt)); +#else +void USBHS_IRQHandler() __attribute__((section(".text.vector_handler"))) __attribute((interrupt)); +#endif +#endif + +void USBHS_InternalFinishSetup(); + +void USBHS_IRQHandler() +{ +#if FUSB_IO_PROFILE + funDigitalWrite( DEBUG_PIN, 1 ); +#endif + +#if (FUSB_SOF_HSITRIM) + uint64_t systick_local = SysTick->CNT; +#endif + + // Combined FG + ST flag. + uint16_t intfgst = *(uint16_t*)(&USBHS->INT_FG); + int len = 0; + struct _USBState * ctx = &USBHSCTX; + uint8_t * ctrl0buff = ctx->CTRL0BUFF; + // int ep = ( intfgst & CMASK_UIS_ENDP ) >> 8; + + // First check if this it setup +#if (USBHS_IMPL==1) + if( intfgst & CRB_UIF_SETUP_ACT ) +#else + if( (intfgst & CRB_UIF_TRANSFER) && !(intfgst & (1<<12)) && !(( intfgst & CMASK_UIS_ENDP ) >> 8) && (USBHS->UEP0_RX_CTRL & USBHS_UEP_R_SETUP_IS) ) +#endif + { + /* Setup stage processing */ + UEP_CTRL_TX(0) = USBHS_UEP_T_RES_NAK | USBHS_UEP_T_TOG_DATA1; + UEP_CTRL_RX(0) = USBHS_UEP_R_RES_NAK | USBHS_UEP_R_TOG_DATA1; + + /* Store All Setup Values */ + int USBHS_SetupReqType = USBHSCTX.USBHS_SetupReqType = pUSBHS_SetupReqPak->bmRequestType; + int USBHS_SetupReqCode = USBHSCTX.USBHS_SetupReqCode = pUSBHS_SetupReqPak->bRequest; + int USBHS_SetupReqLen = USBHSCTX.USBHS_SetupReqLen = pUSBHS_SetupReqPak->wLength; + int USBHS_SetupReqIndex = pUSBHS_SetupReqPak->wIndex; + int USBHS_IndexValue = USBHSCTX.USBHS_IndexValue = ( pUSBHS_SetupReqPak->wIndex << 16 ) | pUSBHS_SetupReqPak->wValue; + if( usb_debug ) printf( "[USB] SETUP: %02x %02x %d %04x %08x\n", USBHS_SetupReqType, USBHS_SetupReqCode, USBHS_SetupReqLen, USBHS_SetupReqIndex, USBHS_IndexValue ); + + if( ( USBHS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) + { +#if FUSB_HID_INTERFACES > 0 || FUSB_USER_HANDLERS + if( ( USBHS_SetupReqType & USB_REQ_TYP_MASK ) == USB_REQ_TYP_CLASS ) + { + /* Class Request */ + switch( USBHS_SetupReqCode ) + { +#if FUSB_HID_INTERFACES > 0 + case HID_SET_REPORT: +#if FUSB_HID_USER_REPORTS + len = HandleHidUserSetReportSetup( ctx, pUSBHS_SetupReqPak ); + if( len < 0 ) + { + goto sendstall; + } + ctx->USBHS_SetupReqLen = len; + UEP_CTRL_LEN(0) = 0; + // Previously would have been a CTRL_RX = ACK && TOG, but not here on the 203. + UEP_CTRL_RX(0) = USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_DATA1; + UEP_CTRL_TX(0) = USBHS_UEP_T_TOG_DATA1; + goto replycomplete; + + case HID_GET_REPORT: + len = HandleHidUserGetReportSetup( ctx, pUSBHS_SetupReqPak ); + if( len < 0 ) + { + goto sendstall; + } + ctx->USBHS_SetupReqLen = len; + len = len >= USBHS_DEF_UEP0_SIZE ? USBHS_DEF_UEP0_SIZE : len; + if( !ctx->pCtrlPayloadPtr ) + { + len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); + } + else + { + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + ctx->pCtrlPayloadPtr += len; + } + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) = USBHS_UEP_T_RES_ACK | USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_SetupReqLen -= len; + goto replycomplete; +#endif + break; + + case HID_SET_IDLE: + if( USBHS_SetupReqIndex < FUSB_HID_INTERFACES ) + USBHSCTX.USBHS_HidIdle[ USBHS_SetupReqIndex ] = (uint8_t)( USBHS_IndexValue >> 8 ); + break; + case HID_SET_PROTOCOL: + if ( USBHS_SetupReqIndex < FUSB_HID_INTERFACES ) + USBHSCTX.USBHS_HidProtocol[USBHS_SetupReqIndex] = (uint8_t)USBHS_IndexValue; + break; + + case HID_GET_IDLE: + if( USBHS_SetupReqIndex < FUSB_HID_INTERFACES ) + { + ctrl0buff[0] = USBHSCTX.USBHS_HidIdle[ USBHS_SetupReqIndex ]; + len = 1; + } + break; + + case HID_GET_PROTOCOL: + if( USBHS_SetupReqIndex < FUSB_HID_INTERFACES ) + { + ctrl0buff[0] = USBHSCTX.USBHS_HidProtocol[ USBHS_SetupReqIndex ]; + len = 1; + } + break; +#endif + default: +#if FUSB_USER_HANDLERS + len = HandleSetupCustom( ctx, USBHS_SetupReqCode ); + + if( len ) + { + if( len < 0 ) { + len = 0; + ctx->USBHS_SetupReqLen = 0; + } + else + { + ctx->USBHS_SetupReqLen = len; + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + // printf("%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", ctrl0buff[0], ctrl0buff[1], ctrl0buff[2], ctrl0buff[3], ctrl0buff[4], ctrl0buff[5], ctrl0buff[6]); + ctx->pCtrlPayloadPtr += len; + } + + if( ctx->USBHS_SetupReqType & USBHS_DEF_UEP_IN || ctx->USBHS_SetupReqLen == 0) + { + len = len >= USBHS_DEF_UEP0_SIZE ? USBHS_DEF_UEP0_SIZE : len; + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + ctx->USBHS_SetupReqLen -= len; + } + else UEP_CTRL_RX(0)= USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + // UEP_CTRL_LEN(0) = len; + // UEP_CTRL_TX(0) = CHECK_USBHS_UEP_T_AUTO_TOG | USBHS_UEP_T_RES_ACK | USBHS_UEP_T_TOG; + // ctx->USBHS_SetupReqLen -= len; + // goto epzero_rxtx; + goto replycomplete; + } + else +#endif + { + goto sendstall; + } + break; + } + } +#else + ; +#endif + } + else + { + /* usb standard request processing */ + switch( USBHS_SetupReqCode ) + { + /* get device/configuration/string/report/... descriptors */ + case USB_GET_DESCRIPTOR: + { + const struct descriptor_list_struct * e = descriptor_list; + const struct descriptor_list_struct * e_end = e + DESCRIPTOR_LIST_ENTRIES; + for( ; e != e_end; e++ ) + { + if( e->lIndexValue == USBHS_IndexValue ) + { + ctx->pCtrlPayloadPtr = (uint8_t*)e->addr; + len = e->length; + break; + } + } + if( e == e_end ) // If descriptor list is empty + { + goto sendstall; + } + + /* Copy Descriptors to Endp0 DMA buffer */ + if( ctx->USBHS_SetupReqLen > len ) ctx->USBHS_SetupReqLen = len; + len = ( USBHS_SetupReqLen >= USBHS_DEF_UEP0_SIZE ) ? USBHS_DEF_UEP0_SIZE : USBHS_SetupReqLen; + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + ctx->pCtrlPayloadPtr += len; + } + break; + + /* Set usb address */ + case USB_SET_ADDRESS: + ctx->USBHS_DevAddr = (uint8_t)( ctx->USBHS_IndexValue & 0xFF ); + // NOTE: Do not actually set addres here! If we do, we won't get the PID_IN associated with this SETUP. + break; + + /* Get usb configuration now set */ + case USB_GET_CONFIGURATION: + ctrl0buff[0] = ctx->USBHS_DevConfig; + if( ctx->USBHS_SetupReqLen > 1 ) + ctx->USBHS_SetupReqLen = 1; + break; + + /* Set usb configuration to use */ + case USB_SET_CONFIGURATION: + ctx->USBHS_DevConfig = (uint8_t)( ctx->USBHS_IndexValue & 0xFF ); + ctx->USBHS_DevEnumStatus = 0x01; + break; + + /* Clear or disable one usb feature */ + case USB_CLEAR_FEATURE: +#if FUSB_SUPPORTS_SLEEP + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { + /* clear one device feature */ + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) + { + /* clear usb sleep status, device not prepare to sleep */ + ctx->USBHS_DevSleepStatus &= ~0x01; + } + else + { + goto sendstall; + } + } + else +#endif + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) + { + /* Clear End-point Feature */ + int ep = USBHS_SetupReqIndex & 0xf; + if( ep < FUSB_CONFIG_EPS ) + { + // UEP_CTRL_TX(ep) = USBHS_UEP_T_RES_STALL; + if( USBHS_SetupReqIndex & USBHS_DEF_UEP_IN && ctx->endpoint_mode[ep] == -1 ) UEP_CTRL_TX(ep) = USBHS_UEP_T_RES_NAK; + else if( USBHS_SetupReqIndex & USBHS_DEF_UEP_OUT && ctx->endpoint_mode[ep] == 1 ) UEP_CTRL_RX(ep) = USBHS_UEP_R_RES_ACK; + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + break; + + /* set or enable one usb feature */ + case USB_SET_FEATURE: + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { +#if FUSB_SUPPORTS_SLEEP + /* Set Device Feature */ + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) + { + /* Set Wake-up flag, device prepare to sleep */ + USBHS_DevSleepStatus |= 0x01; + } + else +#endif + { + goto sendstall; + } + } + else if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + /* Set Endpoint Feature */ + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) + { + int ep = USBHS_SetupReqIndex & 0xf; + if( ep < FUSB_CONFIG_EPS ) + { + if( (USBHS_SetupReqIndex & USBHS_DEF_UEP_IN) && ctx->endpoint_mode[ep] == -1 ) UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_STALL; + else if( (USBHS_SetupReqIndex & USBHS_DEF_UEP_OUT) && ctx->endpoint_mode[ep] == 1 ) UEP_CTRL_RX(ep) = ( UEP_CTRL_RX(ep) & ~USBHS_UEP_R_RES_MASK ) | USBHS_UEP_R_RES_STALL; + else + { + goto sendstall; + } + } + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + break; + + /* This request allows the host to select another setting for the specified interface */ + case USB_GET_INTERFACE: + ctrl0buff[0] = 0x00; + if( USBHS_SetupReqLen > 1 ) USBHS_SetupReqLen = 1; + break; + + case USB_SET_INTERFACE: + break; + + /* host get status of specified device/interface/end-points */ + case USB_GET_STATUS: + ctrl0buff[0] = 0x00; + ctrl0buff[1] = 0x00; + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { +#if FUSB_SUPPORTS_SLEEP + ctrl0buff[0] = (ctx->USBHS_DevSleepStatus & 0x01)<<1; +#else + ctrl0buff[0] = 0x00; +#endif + } + else if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + int ep = USBHS_SetupReqIndex & 0xf; + if( ep < FUSB_CONFIG_EPS ) + { + if( USBHS_SetupReqIndex & USBHS_DEF_UEP_IN && ctx->endpoint_mode[ep] == -1 ) ctrl0buff[0] = ( UEP_CTRL_TX(ep) & USBHS_UEP_T_RES_MASK ) == USBHS_UEP_T_RES_STALL; + else if( USBHS_SetupReqIndex & USBHS_DEF_UEP_OUT && ctx->endpoint_mode[ep] == 1 ) ctrl0buff[0] = ( UEP_CTRL_RX(ep) & USBHS_UEP_R_RES_MASK ) == USBHS_UEP_R_RES_STALL; + else goto sendstall; + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + if( USBHS_SetupReqLen > 2 ) + USBHS_SetupReqLen = 2; + break; + + default: + goto sendstall; + break; + } + } + // epzero_rxtx: + { + /* end-point 0 data Tx/Rx */ + if( USBHS_SetupReqType & USBHS_DEF_UEP_IN ) + { + len = ( ctx->USBHS_SetupReqLen > USBHS_DEF_UEP0_SIZE )? USBHS_DEF_UEP0_SIZE : ctx->USBHS_SetupReqLen; + ctx->USBHS_SetupReqLen -= len; + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) = USBHS_UEP_T_RES_ACK | USBHS_UEP_T_TOG_DATA1; + } + else + { + if( ctx->USBHS_SetupReqLen == 0 ) + { + UEP_CTRL_LEN(0) = 0; + UEP_CTRL_TX(0) = USBHS_UEP_T_RES_ACK | USBHS_UEP_T_TOG_DATA1; + } + else + { + UEP_CTRL_RX(0) = USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_DATA1; + } + } + } + + goto replycomplete; + +sendstall: + { + // if one request not support, return stall. Stall means permanent error. + UEP_CTRL_TX(0) = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_STALL; + UEP_CTRL_RX(0) = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_STALL; + } + +replycomplete: + USBHS->INT_FG = intfgst; + USBHS_DONE_RX(0); + + } + else if( intfgst & CRB_UIF_TRANSFER ) + { + int token = ( intfgst & CMASK_UIS_TOKEN ) >> 12; + int ep = ( intfgst & CMASK_UIS_ENDP ) >> 8; + + if( usb_debug ) printf( "[USB] TRANSFER, token = %02x, ep = %d, bmRequestType = %02x, bRequest = %02x\n", token, ep, pUSBHS_SetupReqPak->bmRequestType, pUSBHS_SetupReqPak->bRequest ); + switch ( token ) + { + case CUIS_TOKEN_IN: + if( ep ) + { + if( ep < FUSB_CONFIG_EPS ) + { +#if FUSB_USER_HANDLERS + len = HandleInRequest( ctx, ep, ctx->ENDPOINTS[ ep-1 ], 0 ); +#endif + UEP_CTRL_TX(ep) ^= USBHS_UEP_T_TOG_DATA1; + if( len ) + { + if( len < 0 ) len = 0; + UEP_CTRL_LEN(ep) = len; + UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_ACK; + } + else + { + UEP_CTRL_TX(ep) = ( UEP_CTRL_TX(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_NAK; + } + ctx->USBHS_Endp_Busy[ep] = 0; + } + } + else // EP0 + { + /* end-point 0 data in interrupt */ + if( ctx->USBHS_SetupReqLen == 0 ) + { + UEP_CTRL_RX(0) = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + } + + ctx->USBHS_errata_dont_send_endpoint_in_window = 0; + + if( ctx->pCtrlPayloadPtr ) + { + // Shortcut mechanism, for descriptors or if the user wants it. + len = ctx->USBHS_SetupReqLen >= USBHS_DEF_UEP0_SIZE ? USBHS_DEF_UEP0_SIZE : ctx->USBHS_SetupReqLen; + copyBuffer( ctrl0buff, ctx->pCtrlPayloadPtr, len ); // FYI -> Would need to do this if using DMA + ctx->USBHS_SetupReqLen -= len; + if( ctx->USBHS_SetupReqLen > 0 ) + ctx->pCtrlPayloadPtr += len; + else + ctx->pCtrlPayloadPtr = 0; + + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) ^= USBHS_UEP_T_TOG_DATA1; +#if (USBHS_IMPL==2) + UEP_CTRL_TX(0) = ( UEP_CTRL_TX(0) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_ACK; // clear +#endif + } + else if ( ( ctx->USBHS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) + { + len = ctx->USBHS_SetupReqLen >= USBHS_DEF_UEP0_SIZE ? USBHS_DEF_UEP0_SIZE : ctx->USBHS_SetupReqLen; +#if FUSB_HID_USER_REPORTS + if( len && USBHSCTX.USBHS_SetupReqCode == HID_GET_REPORT ) + { + len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) ^= USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_SetupReqLen -= len; + ctx->pCtrlPayloadPtr += len; + } +#endif +#if FUSB_USER_HANDLERS + if( len && USBHSCTX.USBHS_SetupReqCode != HID_GET_REPORT ) + { + len = HandleInRequest( ctx, 0, ctrl0buff, len ); + UEP_CTRL_LEN(0) = len; + UEP_CTRL_TX(0) ^= USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_SetupReqLen -= len; + ctx->pCtrlPayloadPtr += len; + } +#endif + } + else + { + switch( USBHSCTX.USBHS_SetupReqCode ) + { + case USB_GET_DESCRIPTOR: + break; + + case USB_SET_ADDRESS: + USBHS->DEV_AD = ctx->USBHS_DevAddr; + break; + + default: + break; + } + } + } + USBHS_DONE_TX(ep); + break; + + /* data-out stage processing */ + case CUIS_TOKEN_OUT: +#if (USBHS_IMPL == 1) + len = USBHS->RX_LEN; +#else + if( ep ) len = UEP_RX_LEN(ep); + else len = USBHS->UEP0_RX_LEN; +#endif + switch( ep ) + { + /* end-point 0 data out interrupt */ + case USBHS_DEF_UEP0: +#if (USBHS_IMPL==1) + if( intfgst & CRB_UIS_TOG_OK ) +#else + if( USBHS->UEP0_RX_CTRL & (1<<4) ) // RB_UEP_R_TOG_MATCH +#endif + { +#if FUSB_HID_USER_REPORTS + if( ctx->USBHS_SetupReqCode == HID_SET_REPORT ) + { + uint8_t * cptr = ctx->pCtrlPayloadPtr; + if( !cptr ) + { + HandleHidUserReportDataOut( ctx, ctrl0buff, len ); + } + else + { + int remain = ctx->USBHS_SetupReqLen - len; + if( remain < 0 ) + { + len += remain; + remain = 0; + } + copyBuffer( cptr, ctrl0buff, len ); + ctx->USBHS_SetupReqLen = remain; + if( remain > 0 ) + ctx->pCtrlPayloadPtr = cptr + len; + else + ctx->pCtrlPayloadPtr = 0; + } + } +#endif +#if FUSB_USER_HANDLERS + if ( ctx->USBHS_SetupReqCode != HID_SET_REPORT ) + { + HandleDataOut( ctx, ep, ctrl0buff, len ); + } +#endif + if( ctx->USBHS_SetupReqLen == 0 ) + { +#if FUSB_HID_USER_REPORTS + if( ctx->USBHS_SetupReqCode == HID_SET_REPORT ) + HandleHidUserReportOutComplete( ctx ); +#endif + // Only set this flag for OUT requests (e.g. SET_LINE_CODING). + // For IN requests (e.g. GET_DESCRIPTOR), don't set it. + if ( ( ctx->USBHS_SetupReqType & USB_REQ_TYP_IN ) == 0 ) + { + ctx->USBHS_errata_dont_send_endpoint_in_window = 1; + } + UEP_CTRL_LEN(0) = 0; + UEP_CTRL_TX(0) = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + } + else + { + UEP_CTRL_RX(0) ^= USBHS_UEP_R_TOG_DATA1; +#if (USBHS_IMPL==2) + UEP_CTRL_RX(0) = ( UEP_CTRL_RX(0) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_ACK; // clear +#endif + } + } + USBHS_DONE_RX(0); + break; + + default: +#if (USBHS_IMPL==1) + if( intfgst & CRB_UIS_TOG_OK ) +#else + if( UEP_CTRL_RX(ep) & (1<<4) ) // RB_UEP_R_TOG_MATCH +#endif + { + uint_fast8_t rx_ctrl = UEP_CTRL_RX(ep) & ~USBHS_UEP_R_RES_MASK; + rx_ctrl ^= USBHS_UEP_R_TOG_DATA1; +#if FUSB_OUT_FLOW_CONTROL > 0 + rx_ctrl |= USBHS_UEP_R_RES_NAK; // ACK later when receiver is ready +#else + rx_ctrl |= USBHS_UEP_R_RES_ACK; +#endif + UEP_CTRL_RX(ep) = rx_ctrl; +#if FUSB_USER_HANDLERS + HandleDataOut( ctx, ep, ctx->ENDPOINTS[ep-1], len ); +#endif + } + USBHS_DONE_RX(ep); + break; + } + break; + +#if (USBHS_IMPL==1) + case CUIS_TOKEN_SOF: + { +#if (FUSB_SOF_HSITRIM) + int32_t diff = (int64_t)(systick_local - ctx->USBHS_sof_timestamp); + uint32_t trim = (RCC->CTLR & RCC_HSITRIM) >> 3; + if( diff > TICKS_PER_HSITRIM && (trim > 0)) { + uint32_t regtemp; + regtemp = RCC->CTLR & ~RCC_HSITRIM; + RCC->CTLR = regtemp | (--trim)<<3; + } + else if( diff < 0 && diff < (TICKS_PER_HSITRIM*-1) && (trim < 31)) + { + uint32_t regtemp; + regtemp = RCC->CTLR & ~RCC_HSITRIM; + RCC->CTLR = regtemp | (++trim)<<3;; + } + ctx->USBHS_sof_timestamp = systick_local + Ticks_from_Us(125); +#endif + USBHS->INT_FG = CRB_UIF_HST_SOF; + } + break; +#endif + + default : + break; + } + USBHS->INT_FG = CRB_UIF_TRANSFER; + } + else if( intfgst & CRB_UIF_BUS_RST ) + { + if( usb_debug ) printf( "[USB] RESET\n" ); + /* usb reset interrupt processing */ + ctx->USBHS_DevConfig = 0; + ctx->USBHS_DevAddr = 0; + ctx->USBHS_DevSleepStatus = 0; + ctx->USBHS_DevEnumStatus = 0; + + USBHS->DEV_AD = 0; + USBHS_InternalFinishSetup(); + USBHS->INT_FG = CRB_UIF_BUS_RST; + } + else if( intfgst & CRB_UIF_SUSPEND ) + { + if( usb_debug ) printf( "[USB] SUSPEND\n" ); + USBHS->INT_FG = CRB_UIF_SUSPEND; + Delay_Us(10); + /* usb suspend interrupt processing */ + if( USBHS->MIS_ST & USBHS_UMS_SUSPEND ) + { + ctx->USBHS_DevSleepStatus |= 0x02; + if( ctx->USBHS_DevSleepStatus == 0x03 ) + { + /* Handling usb sleep here */ + //TODO: MCU_Sleep_Wakeup_Operate( ); + } + } + else + { + ctx->USBHS_DevSleepStatus &= ~0x02; + } + } + else + { + /* other interrupts */ + USBHS->INT_FG = intfgst & 0xff; + } + + +#if FUSB_IO_PROFILE + funDigitalWrite( DEBUG_PIN, 0 ); +#endif + +#if FUSB_USE_HPE + // asm volatile( "mret" ); +#endif +} + +void USBHS_InternalFinishSetup() +{ + +#if FUSB_EP1_MODE + USBHSCTX.endpoint_mode[1] = FUSB_EP1_MODE; +#ifndef FUSB_EP1_SIZE + USBHS->UEP1_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP1_MAX_LEN = FUSB_EP1_SIZE; +#endif +#if FUSB_EP1_MODE > 0 + UEP_TX_EN(1); + UEP_DMA_TX(1) = (uintptr_t)USBHSCTX.ENDPOINTS[0]; +#else + UEP_RX_EN(1); + UEP_DMA_RX(1) = (uintptr_t)USBHSCTX.ENDPOINTS[0]; +#endif +#endif + +#if FUSB_EP2_MODE + USBHSCTX.endpoint_mode[2] = FUSB_EP2_MODE; +#ifndef FUSB_EP2_SIZE + USBHS->UEP2_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP2_MAX_LEN = FUSB_EP2_SIZE; +#endif +#if FUSB_EP2_MODE > 0 + UEP_TX_EN(2); + UEP_DMA_TX(2) = (uintptr_t)USBHSCTX.ENDPOINTS[1]; +#else + UEP_RX_EN(2); + UEP_DMA_RX(2) = (uintptr_t)USBHSCTX.ENDPOINTS[1]; +#endif +#endif + +#if FUSB_EP3_MODE + USBHSCTX.endpoint_mode[3] = FUSB_EP3_MODE; +#ifndef FUSB_EP3_SIZE + USBHS->UEP3_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP3_MAX_LEN = FUSB_EP3_SIZE; +#endif +#if FUSB_EP3_MODE > 0 + UEP_TX_EN(3); + UEP_DMA_TX(3) = (uintptr_t)USBHSCTX.ENDPOINTS[2]; +#else + UEP_RX_EN(3); + UEP_DMA_RX(3) = (uintptr_t)USBHSCTX.ENDPOINTS[2]; +#endif +#endif + +#if FUSB_EP4_MODE + USBHSCTX.endpoint_mode[4] = FUSB_EP4_MODE; +#ifndef FUSB_EP4_SIZE + USBHS->UEP4_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP4_MAX_LEN = FUSB_EP4_SIZE; +#endif +#if FUSB_EP4_MODE > 0 + UEP_TX_EN(4); + UEP_DMA_TX(4) = (uintptr_t)USBHSCTX.ENDPOINTS[3]; +#else + UEP_RX_EN(4); + UEP_DMA_RX(4) = (uintptr_t)USBHSCTX.ENDPOINTS[3]; +#endif +#endif + +#if FUSB_EP5_MODE + USBHSCTX.endpoint_mode[5] = FUSB_EP5_MODE; +#ifndef FUSB_EP5_SIZE + USBHS->UEP5_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP5_MAX_LEN = FUSB_EP5_SIZE; +#endif +#if FUSB_EP5_MODE > 0 + UEP_TX_EN(5); + UEP_DMA_TX(5) = (uintptr_t)USBHSCTX.ENDPOINTS[4]; +#else + UEP_RX_EN(5); + UEP_DMA_RX(5) = (uintptr_t)USBHSCTX.ENDPOINTS[4]; +#endif +#endif + +#if FUSB_EP6_MODE + USBHSCTX.endpoint_mode[6] = FUSB_EP6_MODE; +#ifndef FUSB_EP6_SIZE + USBHS->UEP6_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP6_MAX_LEN = FUSB_EP6_SIZE; +#endif +#if FUSB_EP6_MODE > 0 + UEP_TX_EN(6); + UEP_DMA_TX(6) = (uintptr_t)USBHSCTX.ENDPOINTS[5]; +#else + UEP_RX_EN(6); + UEP_DMA_RX(6) = (uintptr_t)USBHSCTX.ENDPOINTS[5]; +#endif +#endif + +#if FUSB_EP7_MODE + USBHSCTX.endpoint_mode[7] = FUSB_EP7_MODE; +#ifndef FUSB_EP7_SIZE + USBHS->UEP7_MAX_LEN = FUSB_EP_SIZE; +#else + USBHS->UEP7_MAX_LEN = FUSB_EP7_SIZE; +#endif +#if FUSB_EP7_MODE > 0 + UEP_TX_EN(7); + UEP_DMA_TX(7) = (uintptr_t)USBHSCTX.ENDPOINTS[6]; +#else + UEP_RX_EN(7); + UEP_DMA_RX(7) = (uintptr_t)USBHSCTX.ENDPOINTS[6]; +#endif +#endif + +#if !defined (FUSB_CONFIG_EPS) || !FUSB_CONFIG_EPS +#error You must have at least EP0! +#endif + + USBHS->UEP0_DMA = (uintptr_t)USBHSCTX.CTRL0BUFF; + USBHS->UEP0_MAX_LEN = USBHS_DEF_UEP0_SIZE; + USBHS->UEP0_T_LEN = 0; + UEP_TX_EN(0); + UEP_RX_EN(0); + UEP_CTRL_TX(0) = USBHS_UEP_T_RES_NAK; + UEP_CTRL_RX(0) = USBHS_UEP_R_RES_ACK; + + for( int i = 1; i < FUSB_CONFIG_EPS; i++ ) + { + if( USBHSCTX.endpoint_mode[i] > 0 ) + { + UEP_CTRL_TX(i) = USBHS_UEP_T_RES_NAK; + } + else if( USBHSCTX.endpoint_mode[i] < 0 ) + { + UEP_CTRL_RX(i) = USBHS_UEP_R_RES_ACK; + } + USBHSCTX.USBHS_Endp_Busy[i] = 0; + } +} + +#if FUSB_OUT_FLOW_CONTROL > 0 +void USBHS_RxReady(int endp) +{ + // Just ACK previous transfer for the RX to get ready + UEP_CTRL_RX(endp) &= ~USBHS_UEP_R_RES_MASK; +} +#endif + +int USBHSSetup() +{ +#if defined (CH584_CH585) + R8_USBHS_PLL_CTRL = USBHS_PLL_EN; + R16_PIN_CONFIG |= RB_PIN_USB2_EN; +#elif defined (CH32V30x) +#if (FUNCONF_SYSTEM_CORE_CLOCK != 144000000) && (FUNCONF_SYSTEM_CORE_CLOCK != 96000000) && (FUNCONF_SYSTEM_CORE_CLOCK != 48000000) +#error "CH32V30x need 144/96/48MHz main clock for USB to work" +#endif + RCC->CFGR2 &= ~((7 << 24) | (1 << 27) | (3 << 28) | (1<<31)); +#if (FUNCONF_USE_HSE) + RCC->CFGR2 = RCC_USBHSSRC | RCC_USBHSPLL | 1<< RCC_USBHSCLK_OFFSET | 1 << RCC_USBHSDIV_OFFSET; +#else +#warning "Using HSI" + RCC->CFGR2 = RCC_USBHSSRC | RCC_USBHSPLL | RCC_USBHSPLLSRC | 1<< RCC_USBHSCLK_OFFSET | 1 << RCC_USBHSDIV_OFFSET; +#endif + RCC->AHBPCENR |= RCC_USBHSEN | RCC_AHBPeriph_DMA1; +#else +#error "Need to add USB clock setup for this chip" +#endif + +#if (USBHS_IMPL==1) + // Force module to reset. + USBHS->BASE_CTRL = USBHS_UC_CLR_ALL | USBHS_UC_RESET_SIE; + Delay_Us(10); + USBHS->BASE_CTRL = 0; + USBHS->HOST_CTRL = USBHS_UH_PHY_SUSPENDM; + // Initialize USB device config + USBHS->HOST_CTRL = USBHS_UH_PHY_SUSPENDM; + USBHS->BASE_CTRL = USBHS_UC_DMA_EN | USBHS_UC_INT_BUSY | (FUSB_SPEED<<5); + USBHS->INT_EN = USBHS_UIE_SETUP_ACT | USBHS_UIE_TRANSFER | USBHS_UIE_DETECT | USBHS_UIE_SUSPEND; +#if (FUSB_SOF_HSITRIM) + USBHS->INT_EN |= USBHS_UIE_SOF_ACT; +#endif + USBHS_InternalFinishSetup(); + USBHS->BASE_CTRL |= USBHS_UC_DEV_PU_EN; +#else + // Force module to reset. + USBHS->BASE_CTRL = USBHS_UD_RST_LINK | USBHS_UD_PHY_SUSPENDM; + Delay_Us(10); + USBHS->BASE_CTRL = 0; + // Initialize USB device config + USBHS->INT_EN = USBHS_UDIE_BUS_RST | USBHS_UDIE_SUSPEND | USBHS_UDIE_BUS_SLEEP | USBHS_UDIE_LPM_ACT | USBHS_UDIE_TRANSFER | USBHS_UDIE_LINK_RDY; + USBHS_InternalFinishSetup(); + USBHS->BASE_MODE = FUSB_SPEED; + USBHS->BASE_CTRL = USBHS_UD_DEV_EN | USBHS_UD_DMA_EN | USBHS_UD_LPM_EN | USBHS_UD_PHY_SUSPENDM; +#endif + + NVIC_EnableIRQ( USBHS_IRQn ); + +#if FUSB_IO_PROFILE + funPinMode( DEBUG_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); +#endif + + // Go on-bus. + return 0; +} + +static inline uint8_t * USBHS_GetEPBufferIfAvailable( int endp ) +{ + if( USBHSCTX.USBHS_Endp_Busy[endp] ) return 0; + return USBHSCTX.ENDPOINTS[endp-1]; +} + +static inline int USBHS_SendEndpoint( int endp, int len ) +{ + if( USBHSCTX.USBHS_errata_dont_send_endpoint_in_window || USBHSCTX.USBHS_Endp_Busy[endp] ) return -1; + // This prevents sending while ep0 is receiving + if( USBHSCTX.USBHS_SetupReqLen > 0 ) return -2; + // Check if in SETUP request + // if( USBHS->UEP0_RX_CTRL & USBHS_UEP_R_SETUP_IS ) return -3; + NVIC_DisableIRQ( USBHS_IRQn ); + UEP_CTRL_LEN( endp ) = len; + UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_ACK; + USBHSCTX.USBHS_Endp_Busy[endp] = 1; + NVIC_EnableIRQ( USBHS_IRQn ); + return 0; +} + +static inline int USBHS_SendEndpointNEW( int endp, const uint8_t* data, int len, int copy) +{ + if( USBHSCTX.USBHS_errata_dont_send_endpoint_in_window || USBHSCTX.USBHS_Endp_Busy[endp] ) return -1; + // This prevents sending while ep0 is receiving + if( USBHSCTX.USBHS_SetupReqLen > 0 ) return USBHSCTX.USBHS_SetupReqLen; + + if ( len ) + { + if( copy ) + { + uint8_t* dest = (endp?USBHSCTX.ENDPOINTS[endp-1]:USBHSCTX.CTRL0BUFF); + copyBuffer( dest, data, len ); + } + else + { + if( !endp ) USBHS->UEP0_DMA = (uintptr_t)data; + else UEP_DMA_TX( endp ) = (uintptr_t)data; + } + } + // NVIC_DisableIRQ( USBHS_IRQn ); + UEP_CTRL_LEN( endp ) = len; + UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_ACK; + USBHSCTX.USBHS_Endp_Busy[endp] = 1; + // NVIC_EnableIRQ( USBHS_IRQn ); + return 0; +} + +static inline int USBHS_SendACK( int endp, int tx ) +{ + if( tx ) UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_ACK; + else UEP_CTRL_RX(endp) = ( UEP_CTRL_RX(endp) & ~USBHS_UEP_R_RES_MASK ) | USBHS_UEP_R_RES_ACK; + return 0; +} + +static inline int USBHS_SendNAK( int endp, int tx ) +{ + if( tx ) UEP_CTRL_TX( endp ) = ( UEP_CTRL_TX( endp ) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_NAK; + else UEP_CTRL_RX(endp) = ( UEP_CTRL_RX(endp) & ~USBHS_UEP_R_RES_MASK ) | USBHS_UEP_R_RES_NAK; + return 0; +} + +#if defined( FUNCONF_USE_USBPRINTF ) && FUNCONF_USE_USBPRINTF +WEAK int HandleInRequest( struct _USBState *ctx, int endp, uint8_t *data, int len ) +{ + return 0; +} + +WEAK void HandleDataOut( struct _USBState *ctx, int endp, uint8_t *data, int len ) +{ + if ( endp == 0 ) + { + ctx->USBHS_SetupReqLen = 0; // To ACK + } +} + +WEAK int HandleSetupCustom( struct _USBState *ctx, int setup_code ) +{ + int ret = -1; + if ( ctx->USBHS_SetupReqType & USB_REQ_TYP_CLASS ) + { + switch ( setup_code ) + { + case CDC_SET_LINE_CODING: + case CDC_SET_LINE_CTLSTE: + case CDC_SEND_BREAK: ret = ( ctx->USBHS_SetupReqLen ) ? ctx->USBHS_SetupReqLen : -1; break; + case CDC_GET_LINE_CODING: ret = ctx->USBHS_SetupReqLen; break; + default: ret = 0; break; + } + } + else + { + ret = 0; // Go to STALL + } + return ret; +} +#endif // FUNCONF_USE_USBPRINTF + diff --git a/inc/extralibs/hsusb.h b/inc/extralibs/hsusb.h new file mode 100644 index 0000000..6c533be --- /dev/null +++ b/inc/extralibs/hsusb.h @@ -0,0 +1,475 @@ +#ifndef _HSUSB_H +#define _HSUSB_H + +#include +#include "ch32fun.h" +#include "usb_defines.h" +#include "usb_config.h" + +#if !defined(CH584_CH585) && !defined(CH32V205) && !defined(CH32H4xx) && !defined(CH32V30x) && !defined(CH565_CH569) +#error "This lib doesn't work on this MCU" +#endif + +#if defined(CH32V30x) || defined(CH565_CH569) +#define USBHS_IMPL 1 +// #elif defined(CH584_CH585) || defined(CH32V205) || defined(CH32H4xx) +#else +#define USBHS_IMPL 2 +#endif + +#ifndef __HIGH_CODE +#define __HIGH_CODE +#endif + +#ifndef USBHS_BASE +#if defined(CH32V30x) || defined(CH32V205) +#define USBHS_BASE (0x40023400) +#elif defined(CH32H4xx) +#define USBHS_BASE (0x40030000) +#else +#define USBHS_BASE (0x40009000) +#endif +#endif + +#if (USBHS_IMPL==1) +#if (FUNCONF_USE_HSI) && !defined(FUSB_SOF_HSITRIM) +#define FUSB_SOF_HSITRIM 1 +#endif +#define TICKS_PER_HSITRIM (FUNCONF_PLL_MULTIPLIER * 20000 * 125) / 1000000 // SOF is sent every 125uS, each HSITRIM changes HSI by 20kHz +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t UEP_CONFIG; + __IO uint32_t UEP_TYPE; + __IO uint32_t UEP_BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_T_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_T_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_T_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_T_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_T_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_T_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_T_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_T_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_T_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_T_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_T_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_T_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_T_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_T_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_T_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_T_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHS_TypeDef; + +#define USBHS_CHECK_NAK_RX (USBHS->INT_ST & 0x80) + +#define CRB_U_IS_NAK (1<<7) +#define CTOG_MATCH_SYNC (1<<6) +#define CRB_UIF_SETUP_ACT (1<<5) // CRB_U_SIE_FREE on USBFS +#define CRB_UIF_FIFO_OV (1<<4) +#define CRB_UIF_HST_SOF (1<<3) +#define CRB_UIF_SUSPEND (1<<2) +#define CRB_UIF_TRANSFER (1<<1) +#define CRB_UIF_BUS_RST (1<<0) +#define CSETUP_ACT (1<<15) +#define CRB_UIS_TOG_OK (1<<14) +#define CMASK_UIS_TOKEN (3<<12) +#define CMASK_UIS_ENDP (0xf<<8) + +#define CUIS_TOKEN_OUT 0x0 +#define CUIS_TOKEN_SOF 0x1 +#define CUIS_TOKEN_IN 0x2 +#define CUIS_TOKEN_SETUP 0x3 + +#define UEP_TX_EN(n) USBHS->UEP_CONFIG |= ((uint32_t)(1<UEP_CONFIG |= ((uint32_t)(1<<(n+16))) + +#define USBHS_DONE_TX(n) +#define USBHS_DONE_RX(n) + +#elif (USBHS_IMPL==2) +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t BASE_MODE; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint8_t WAKE_CTRL; + __IO uint8_t TEST_MODE; + __IO uint16_t LPM_DATA; + __IO uint8_t INT_FG; // "Combined" register in some situations. (ST_FG) + __IO uint8_t INT_ST; + __IO uint8_t MIS_ST; + __IO uint16_t FRAME_NO; + __IO uint16_t BUS; + __IO uint16_t UEP_TX_EN; + __IO uint16_t UEP_RX_EN; + __IO uint16_t UEP_T_TOG_AUTO; + __IO uint16_t UEP_R_TOG_AUTO; + __IO uint8_t UEP_T_BURST; + __IO uint8_t UEP_T_BURST_MODE; + __IO uint8_t UEP_R_BURST; + __IO uint8_t UEP_R_RES_MODE; + __IO uint32_t UEP_AF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP0_MAX_LEN; + __IO uint32_t UEP1_MAX_LEN; + __IO uint32_t UEP2_MAX_LEN; + __IO uint32_t UEP3_MAX_LEN; + __IO uint32_t UEP4_MAX_LEN; + __IO uint32_t UEP5_MAX_LEN; + __IO uint32_t UEP6_MAX_LEN; + __IO uint32_t UEP7_MAX_LEN; + __IO uint16_t UEP0_RX_LEN; + __IO uint16_t reserved; + __IO uint16_t UEP1_RX_LEN; + __IO uint16_t UEP1_R_SIZE; + __IO uint16_t UEP2_RX_LEN; + __IO uint16_t UEP2_R_SIZE; + __IO uint16_t UEP3_RX_LEN; + __IO uint16_t UEP3_R_SIZE; + __IO uint16_t UEP4_RX_LEN; + __IO uint16_t UEP4_R_SIZE; + __IO uint16_t UEP5_RX_LEN; + __IO uint16_t UEP5_R_SIZE; + __IO uint16_t UEP6_RX_LEN; + __IO uint16_t UEP6_R_SIZE; + __IO uint16_t UEP7_RX_LEN; + __IO uint16_t UEP7_R_SIZE; + __IO uint16_t UEP0_T_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_T_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_T_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_T_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_T_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_T_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_T_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_T_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP_T_ISO; + __IO uint16_t UEP_R_ISO; +} USBHS_TypeDef; + +#define USBHS_CHECK_NAK_RX (USBHS->UEP0_RX_CTRL & (1<<6)) + +#define UEP_RX_LEN(n) (((volatile uint16_t*)&USBHS->UEP1_RX_LEN)[(n-1)*2]) +#define UEP_TX_EN(n) USBHS->UEP_TX_EN |= ((uint16_t)(1<UEP_RX_EN |= ((uint16_t)(1<INT_FG + USBHS->INT_ST +#define CRB_UIF_FIFO_OV (1<<7) +#define CRB_UIF_LINK_RDY (1<<6) +#define CRB_UIF_RX_SOF (1<<5) +#define CRB_UIF_TRANSFER (1<<4) +#define CRB_UIF_LPM_ACT (1<<3) +#define CRB_UIF_BUS_SLEEP (1<<2) +#define CRB_UIF_SUSPEND (1<<1) +#define CRB_UIF_BUS_RST (1<<0) + +#define CMASK_UIS_TOKEN (1<<12) +#define CMASK_UIS_ENDP (7<<8) + +#define CUIS_TOKEN_OUT 0x0 +#define CUIS_TOKEN_IN 0x1 + +#define USBHS_DONE_TX(n) UEP_CTRL_TX(n) &= ~(USBHS_UEP_T_DONE) +#define USBHS_DONE_RX(n) UEP_CTRL_RX(n) &= ~(USBHS_UEP_R_DONE) + +#endif + +#define USBHS_SPEED_TYPE_MASK ((uint8_t)(0x03)) + +#define USBHS_DEF_UEP_IN 0x80 +#define USBHS_DEF_UEP_OUT 0x00 +#define USBHS_DEF_UEP_BUSY 0x01 +#define USBHS_DEF_UEP_FREE 0x00 + +#define USBHS_NUM_EP 8 +#define USBHS_DEF_UEP0 0 +#define USBHS_DEF_UEP1 1 +#define USBHS_DEF_UEP2 2 +#define USBHS_DEF_UEP3 3 +#define USBHS_DEF_UEP4 4 +#define USBHS_DEF_UEP5 5 +#define USBHS_DEF_UEP6 6 +#define USBHS_DEF_UEP7 7 +#define USBHS_DEF_UEP8 8 +#define USBHS_DEF_UEP9 9 +#define USBHS_DEF_UEP10 10 +#define USBHS_DEF_UEP11 11 +#define USBHS_DEF_UEP12 12 +#define USBHS_DEF_UEP13 13 +#define USBHS_DEF_UEP14 14 +#define USBHS_DEF_UEP15 15 + +#define USBHS_DEF_UEP0_SIZE 64 + +#ifndef FUSB_EP_SIZE +#define USBHS_UEP_SIZE 64 +#else +#define USBHS_UEP_SIZE FUSB_EP_SIZE +#endif + +#define UEP_CTRL_LEN(n) (((volatile uint16_t*)&USBHS->UEP0_T_LEN)[n*2]) +#define UEP_CTRL_TX(n) (((volatile uint8_t*)&USBHS->UEP0_TX_CTRL)[n*4]) +#define UEP_CTRL_RX(n) (((volatile uint8_t*)&USBHS->UEP0_RX_CTRL)[n*4]) +#define UEP_DMA_RX(n) (((volatile uint32_t*)&USBHS->UEP0_DMA)[n]) +#define UEP_DMA_TX(n) (((volatile uint32_t*)&USBHS->UEP1_TX_DMA)[n-1]) + +#define USBHS ((USBHS_TypeDef *)USBHS_BASE) + +extern uint32_t USBDEBUG0, USBDEBUG1, USBDEBUG2; + +struct _USBState; + +// Provided functions: +int USBHSSetup(); +static inline int USBHS_SendEndpointNEW( int endp, const uint8_t* data, int len, int copy); +static inline uint8_t * USBHS_GetEPBufferIfAvailable( int endp ); +static inline int USBHS_SendEndpoint( int endp, int len ); +static inline int USBHS_SendACK( int endp, int tx ); +static inline int USBHS_SendNAK( int endp, int tx ); + +// Implement the following: +#if FUSB_HID_USER_REPORTS +__HIGH_CODE int HandleHidUserGetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); +__HIGH_CODE int HandleHidUserSetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); +void HandleHidUserReportDataOut( struct _USBState * ctx, uint8_t * data, int len ); +int HandleHidUserReportDataIn( struct _USBState * ctx, uint8_t * data, int len ); +void HandleHidUserReportOutComplete( struct _USBState * ctx ); +#endif + +#if FUSB_USER_HANDLERS +__HIGH_CODE int HandleInRequest( struct _USBState * ctx, int endp, uint8_t * data, int len ); +__HIGH_CODE void HandleDataOut( struct _USBState * ctx, int endp, uint8_t * data, int len ); +__HIGH_CODE int HandleSetupCustom( struct _USBState * ctx, int setup_code); +#endif + +#if FUSB_OUT_FLOW_CONTROL > 0 +void USBHS_RxReady(int endp); +#endif + +typedef enum +{ + USB_SPEED_FULL = 0, + USB_SPEED_HIGH = 1, + USB_SPEED_LOW = 2, +} USB_SPEED_t; + +typedef enum +{ + USBHS_EP_OFF = 0, + USBHS_EP_RX = -1, + USBHS_EP_TX = 1, +} USBHS_EP_mode; + +#ifndef FUSB_EP1_MODE +#define FUSB_EP1_MODE 0 +#endif +#ifndef FUSB_EP2_MODE +#define FUSB_EP2_MODE 0 +#endif +#ifndef FUSB_EP3_MODE +#define FUSB_EP3_MODE 0 +#endif +#ifndef FUSB_EP4_MODE +#define FUSB_EP4_MODE 0 +#endif +#ifndef FUSB_EP5_MODE +#define FUSB_EP5_MODE 0 +#endif +#ifndef FUSB_EP6_MODE +#define FUSB_EP6_MODE 0 +#endif +#ifndef FUSB_EP7_MODE +#define FUSB_EP7_MODE 0 +#endif + +struct _USBState +{ + __attribute__ ((aligned(4))) uint8_t CTRL0BUFF[64]; + __attribute__ ((aligned(4))) uint8_t ENDPOINTS[FUSB_CONFIG_EPS-1][FUSB_EP_SIZE]; + // Setup Request + uint8_t USBHS_SetupReqCode; + uint8_t USBHS_SetupReqType; + uint16_t USBHS_SetupReqLen; // Used for tracking place along send. + uint32_t USBHS_IndexValue; + + // USB Device Status + uint8_t USBHS_DevConfig; + uint8_t USBHS_DevAddr; + uint8_t USBHS_DevSleepStatus; + uint8_t USBHS_DevEnumStatus; + + uint8_t* pCtrlPayloadPtr; + + + USBHS_EP_mode endpoint_mode[FUSB_CONFIG_EPS+1]; // IN -1, OUT 1, OFF 0 + + #define pUSBHS_SetupReqPak ((tusb_control_request_t*)USBHSCTX.CTRL0BUFF) + +#if FUSB_HID_INTERFACES > 0 + uint8_t USBHS_HidIdle[FUSB_HID_INTERFACES]; + uint8_t USBHS_HidProtocol[FUSB_HID_INTERFACES]; +#endif + volatile uint8_t USBHS_Endp_Busy[FUSB_CONFIG_EPS]; + volatile uint8_t USBHS_errata_dont_send_endpoint_in_window; + volatile uint64_t USBHS_sof_timestamp; +}; + +extern struct _USBState USBHSCTX; + +#include "hsusb.c" + +#endif + diff --git a/inc/extralibs/hsusb_v30x.c b/inc/extralibs/hsusb_v30x.c index 73aabfb..055375b 100644 --- a/inc/extralibs/hsusb_v30x.c +++ b/inc/extralibs/hsusb_v30x.c @@ -2,29 +2,29 @@ #include "ch32fun.h" #include -#define UEP_CTRL_H(n) (((uint16_t *)&USBHSD->UEP0_TX_CTRL)[n * 2]) +#define UEP_CTRL_H(n) (((uint16_t*)&USBHSD->UEP0_TX_CTRL)[n*2]) struct _USBState HSUSBCTX; // based on https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/USB/USBHS/DEVICE/CompositeKM // Mask for the combined USBHSD->INT_FG + USBHSD->INT_ST -#define CRB_U_IS_NAK (1 << 7) -#define CTOG_MATCH_SYNC (1 << 6) -#define CRB_UIF_SETUP_ACT (1 << 5) // CRB_U_SIE_FREE on USBFS -#define CRB_UIF_FIFO_OV (1 << 4) -#define CRB_UIF_HST_SOF (1 << 3) -#define CRB_UIF_SUSPEND (1 << 2) -#define CRB_UIF_TRANSFER (1 << 1) -#define CRB_UIF_BUS_RST (1 << 0) -#define CSETUP_ACT (1 << 15) -#define CRB_UIS_TOG_OK (1 << 14) -#define CMASK_UIS_TOKEN (3 << 12) -#define CMASK_UIS_ENDP (0xf << 8) +#define CRB_U_IS_NAK (1<<7) +#define CTOG_MATCH_SYNC (1<<6) +#define CRB_UIF_SETUP_ACT (1<<5) // CRB_U_SIE_FREE on USBFS +#define CRB_UIF_FIFO_OV (1<<4) +#define CRB_UIF_HST_SOF (1<<3) +#define CRB_UIF_SUSPEND (1<<2) +#define CRB_UIF_TRANSFER (1<<1) +#define CRB_UIF_BUS_RST (1<<0) +#define CSETUP_ACT (1<<15) +#define CRB_UIS_TOG_OK (1<<14) +#define CMASK_UIS_TOKEN (3<<12) +#define CMASK_UIS_ENDP (0xf<<8) -#define CUIS_TOKEN_OUT 0x0 -#define CUIS_TOKEN_SOF 0x1 -#define CUIS_TOKEN_IN 0x2 +#define CUIS_TOKEN_OUT 0x0 +#define CUIS_TOKEN_SOF 0x1 +#define CUIS_TOKEN_IN 0x2 #define CUIS_TOKEN_SETUP 0x3 #if 0 @@ -44,7 +44,7 @@ static inline void DMA7FastCopy( uint8_t * dest, const uint8_t * src, int len ) DMA_MemoryInc_Enable | DMA_PeripheralInc_Enable | DMA_Mode_Normal | DMA_CFGR1_EN; -#if !(FUSB_CURSED_TURBO_DMA == 1) +#if !( FUSB_CURSED_TURBO_DMA == 1 ) // Somehow, it seems to work (unsafely) without this. // Really, though, it's probably fine. while( DMA1_Channel7->CNTR ); @@ -57,595 +57,607 @@ static inline void DMA7FastCopyComplete() { while( DMA1_Channel7->CNTR ); } void USBHS_InternalFinishSetup(); -// void USBHSWakeUp_IRQHandler(void) __attribute((interrupt)); -// void USBHSWakeUp_IRQHandler(void) +//void USBHSWakeUp_IRQHandler(void) __attribute((interrupt)); +//void USBHSWakeUp_IRQHandler(void) //{ // printf( "USBHSWakeUp MSTATUS:%08x MTVAL:%08x MCAUSE:%08x MEPC:%08x\n", (int)__get_MSTATUS(), (int)__get_MTVAL(), (int)__get_MCAUSE(), (int)__get_MEPC() ); -// } +//} extern uint8_t scratchpad[]; -void USBHS_IRQHandler(void) __attribute((interrupt)); -void USBHS_IRQHandler(void) +void USBHS_IRQHandler(void) __attribute((interrupt)); +void USBHS_IRQHandler(void) { - // Based on https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/USB/USBHS/DEVICE/CompositeKM/User/ch32v30x_usbhs_device.c - // Combined FG + ST flag - uint16_t intfgst = *(uint16_t *)(&USBHSD->INT_FG); - int len = 0; - struct _USBState *ctx = &HSUSBCTX; - uint8_t *ctrl0buff = CTRL0BUFF; + // Based on https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/USB/USBHS/DEVICE/CompositeKM/User/ch32v30x_usbhs_device.c + // Combined FG + ST flag + uint16_t intfgst = *(uint16_t*)(&USBHSD->INT_FG); + int len = 0; + struct _USBState * ctx = &HSUSBCTX; + uint8_t * ctrl0buff = CTRL0BUFF; - if (intfgst & (CRB_UIF_SETUP_ACT)) - { - // On the Chapter 22 USB, SETUP Requests are handled here instead of in UIF_TRANSFER, with TOKEN_SETUP. - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + if( intfgst & ( CRB_UIF_SETUP_ACT ) ) + { + // On the Chapter 22 USB, SETUP Requests are handled here instead of in UIF_TRANSFER, with TOKEN_SETUP. + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - /* Store All Setup Values */ - int USBHS_SetupReqType = HSUSBCTX.USBHS_SetupReqType = pUSBHS_SetupReqPak->bmRequestType; - int USBHS_SetupReqCode = HSUSBCTX.USBHS_SetupReqCode = pUSBHS_SetupReqPak->bRequest; - int USBHS_SetupReqLen = HSUSBCTX.USBHS_SetupReqLen = pUSBHS_SetupReqPak->wLength; - int USBHS_SetupReqIndex = pUSBHS_SetupReqPak->wIndex; - int USBHS_IndexValue = HSUSBCTX.USBHS_IndexValue = (pUSBHS_SetupReqPak->wIndex << 16) | pUSBHS_SetupReqPak->wValue; - len = 0; + /* Store All Setup Values */ + int USBHS_SetupReqType = HSUSBCTX.USBHS_SetupReqType = pUSBHS_SetupReqPak->bmRequestType; + int USBHS_SetupReqCode = HSUSBCTX.USBHS_SetupReqCode = pUSBHS_SetupReqPak->bRequest; + int USBHS_SetupReqLen = HSUSBCTX.USBHS_SetupReqLen = pUSBHS_SetupReqPak->wLength; + int USBHS_SetupReqIndex = pUSBHS_SetupReqPak->wIndex; + int USBHS_IndexValue = HSUSBCTX.USBHS_IndexValue = ( pUSBHS_SetupReqPak->wIndex << 16 ) | pUSBHS_SetupReqPak->wValue; + len = 0; - // printf( "Setup: %d %d %d %d %d\n", USBHS_SetupReqType, USBHS_SetupReqCode, USBHS_SetupReqLen, - // USBHS_SetupReqIndex, USBHS_IndexValue ); + //printf( "Setup: %d %d %d %d %d\n", USBHS_SetupReqType, USBHS_SetupReqCode, USBHS_SetupReqLen, + // USBHS_SetupReqIndex, USBHS_IndexValue ); - if ((USBHS_SetupReqType & USB_REQ_TYP_MASK) != USB_REQ_TYP_STANDARD) - { -#if HUSB_HID_INTERFACES > 0 - if ((USBHS_SetupReqType & USB_REQ_TYP_MASK) == USB_REQ_TYP_CLASS) - { - /* Class Request */ - // printf( "REQ: %d [%02x %02x %04x %04x]\n", USBHS_SetupReqCode, pUSBHS_SetupReqPak->bmRequestType, pUSBHS_SetupReqPak->bRequest, pUSBHS_SetupReqPak->wValue, pUSBHS_SetupReqPak->wLength ); - switch (USBHS_SetupReqCode) - { - case HID_SET_REPORT: + if( ( USBHS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) + { +#if HUSB_HID_INTERFACES > 0 + if( ( USBHS_SetupReqType & USB_REQ_TYP_MASK ) == USB_REQ_TYP_CLASS ) + { + /* Class Request */ + //printf( "REQ: %d [%02x %02x %04x %04x]\n", USBHS_SetupReqCode, pUSBHS_SetupReqPak->bmRequestType, pUSBHS_SetupReqPak->bRequest, pUSBHS_SetupReqPak->wValue, pUSBHS_SetupReqPak->wLength ); + switch( USBHS_SetupReqCode ) + { + case HID_SET_REPORT: #if HUSB_HID_USER_REPORTS - len = HandleHidUserSetReportSetup(ctx, pUSBHS_SetupReqPak); - if (len < 0) goto sendstall; - ctx->USBHS_SetupReqLen = len; - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1; - goto replycomplete; - case HID_GET_REPORT: - len = HandleHidUserGetReportSetup(ctx, pUSBHS_SetupReqPak); - if (len < 0) goto sendstall; - ctx->USBHS_SetupReqLen = len; - len = len >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : len; - if (!ctx->pCtrlPayloadPtr) - { - len = HandleHidUserReportDataIn(ctx, ctrl0buff, len); - } - else - { - // DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); - memcpy(ctrl0buff, ctx->pCtrlPayloadPtr, len); - ctx->pCtrlPayloadPtr += len; - } - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - ctx->USBHS_SetupReqLen -= len; - goto replycomplete; + len = HandleHidUserSetReportSetup( ctx, pUSBHS_SetupReqPak ); + if( len < 0 ) goto sendstall; + ctx->USBHS_SetupReqLen = len; + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1; + goto replycomplete; + case HID_GET_REPORT: + len = HandleHidUserGetReportSetup( ctx, pUSBHS_SetupReqPak ); + if( len < 0 ) goto sendstall; + ctx->USBHS_SetupReqLen = len; + len = len >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : len; + if( !ctx->pCtrlPayloadPtr ) + { + len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); + } + else + { + //DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + memcpy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + ctx->pCtrlPayloadPtr += len; + } + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + ctx->USBHS_SetupReqLen -= len; + goto replycomplete; #endif - break; + break; - case HID_SET_IDLE: - if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) - HSUSBCTX.USBHS_HidIdle[USBHS_SetupReqIndex] = (uint8_t)(USBHS_IndexValue >> 8); - break; - case HID_SET_PROTOCOL: - if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) - HSUSBCTX.USBHS_HidProtocol[USBHS_SetupReqIndex] = (uint8_t)USBHS_IndexValue; - break; - case HID_GET_IDLE: - if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) - { - ctrl0buff[0] = HSUSBCTX.USBHS_HidIdle[USBHS_SetupReqIndex]; - len = 1; - } - break; + case HID_SET_IDLE: + if( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) + HSUSBCTX.USBHS_HidIdle[ USBHS_SetupReqIndex ] = (uint8_t)( USBHS_IndexValue >> 8 ); + break; + case HID_SET_PROTOCOL: + if ( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) + HSUSBCTX.USBHS_HidProtocol[USBHS_SetupReqIndex] = (uint8_t)USBHS_IndexValue; + break; - case HID_GET_PROTOCOL: - if (USBHS_SetupReqIndex < HUSB_HID_INTERFACES) - { - ctrl0buff[0] = HSUSBCTX.USBHS_HidProtocol[USBHS_SetupReqIndex]; - len = 1; - } - break; + case HID_GET_IDLE: + if( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) + { + ctrl0buff[0] = HSUSBCTX.USBHS_HidIdle[ USBHS_SetupReqIndex ]; + len = 1; + } + break; - default: - goto sendstall; - break; - } - } + case HID_GET_PROTOCOL: + if( USBHS_SetupReqIndex < HUSB_HID_INTERFACES ) + { + ctrl0buff[0] = HSUSBCTX.USBHS_HidProtocol[ USBHS_SetupReqIndex ]; + len = 1; + } + break; + + default: + goto sendstall; + break; + } + } #else - ; + ; #endif - } - else - { - /* usb standard request processing */ - switch (USBHS_SetupReqCode) - { - /* get device/configuration/string/report/... descriptors */ - case USB_GET_DESCRIPTOR: - { - const struct descriptor_list_struct *e = descriptor_list; - const struct descriptor_list_struct *e_end = e + DESCRIPTOR_LIST_ENTRIES; - for (; e != e_end; e++) - { - if (e->lIndexValue == USBHS_IndexValue) - { - ctx->pCtrlPayloadPtr = (uint8_t *)e->addr; - len = e->length; - break; - } - } - if (e == e_end) - { - goto sendstall; - } + } + else + { + /* usb standard request processing */ + switch( USBHS_SetupReqCode ) + { + /* get device/configuration/string/report/... descriptors */ + case USB_GET_DESCRIPTOR: + { + const struct descriptor_list_struct * e = descriptor_list; + const struct descriptor_list_struct * e_end = e + DESCRIPTOR_LIST_ENTRIES; + for( ; e != e_end; e++ ) + { + if( e->lIndexValue == USBHS_IndexValue ) + { + ctx->pCtrlPayloadPtr = (uint8_t*)e->addr; + len = e->length; + break; + } + } + if( e == e_end ) + { + goto sendstall; + } - /* Copy Descriptors to Endp0 DMA buffer */ - int totalLen = USBHS_SetupReqLen; - if (totalLen > len) - { - totalLen = len; - } - len = (totalLen >= DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : totalLen; - // DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); //memcpy( CTRL0BUFF, ctx->pCtrlPayloadPtr, len ); - memcpy(ctrl0buff, ctx->pCtrlPayloadPtr, len); - ctx->USBHS_SetupReqLen = totalLen - len; - ctx->pCtrlPayloadPtr += len; - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - goto replycomplete; - } - /* Set usb address */ - case USB_SET_ADDRESS: - ctx->USBHS_DevAddr = (uint16_t)(ctx->USBHS_IndexValue & 0xFF); - break; + /* Copy Descriptors to Endp0 DMA buffer */ + int totalLen = USBHS_SetupReqLen; + if( totalLen > len ) + { + totalLen = len; + } + len = ( totalLen >= DEF_USBD_UEP0_SIZE ) ? DEF_USBD_UEP0_SIZE : totalLen; + //DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); //memcpy( CTRL0BUFF, ctx->pCtrlPayloadPtr, len ); + memcpy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + ctx->USBHS_SetupReqLen = totalLen - len; + ctx->pCtrlPayloadPtr += len; + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + goto replycomplete; + } - /* Get usb configuration now set */ - case USB_GET_CONFIGURATION: - ctrl0buff[0] = ctx->USBHS_DevConfig; - if (ctx->USBHS_SetupReqLen > 1) - ctx->USBHS_SetupReqLen = 1; - break; + /* Set usb address */ + case USB_SET_ADDRESS: + ctx->USBHS_DevAddr = (uint16_t)( ctx->USBHS_IndexValue & 0xFF ); + break; - /* Set usb configuration to use */ - case USB_SET_CONFIGURATION: - ctx->USBHS_DevConfig = (uint8_t)(ctx->USBHS_IndexValue & 0xFF); - ctx->USBHS_DevEnumStatus = 0x01; - break; + /* Get usb configuration now set */ + case USB_GET_CONFIGURATION: + ctrl0buff[0] = ctx->USBHS_DevConfig; + if( ctx->USBHS_SetupReqLen > 1 ) + ctx->USBHS_SetupReqLen = 1; + break; - /* Clear or disable one usb feature */ - case USB_CLEAR_FEATURE: + /* Set usb configuration to use */ + case USB_SET_CONFIGURATION: + ctx->USBHS_DevConfig = (uint8_t)( ctx->USBHS_IndexValue & 0xFF ); + ctx->USBHS_DevEnumStatus = 0x01; + break; + + /* Clear or disable one usb feature */ + case USB_CLEAR_FEATURE: #if HUSB_SUPPORTS_SLEEP - if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_DEVICE) - { - /* clear one device feature */ - if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_REMOTE_WAKEUP) - { - /* clear usb sleep status, device not prepare to sleep */ - ctx->USBHS_DevSleepStatus &= ~0x01; - } - else - { - goto sendstall; - } - } - else + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { + /* clear one device feature */ + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) + { + /* clear usb sleep status, device not prepare to sleep */ + ctx->USBHS_DevSleepStatus &= ~0x01; + } + else + { + goto sendstall; + } + } + else #endif - if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP) - { - if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_ENDP_HALT) - { - /* Clear End-point Feature */ - int ep = USBHS_SetupReqIndex & 0xf; - if ((USBHS_SetupReqIndex & DEF_UEP_IN) && ep < HUSB_CONFIG_EPS) - { - UEP_CTRL_H(ep) = USBHS_UEP_T_TOG_DATA0 | USBHS_UEP_T_RES_NAK; - } - else - { - goto sendstall; - } - } - else - { - goto sendstall; - } - } - else - { - goto sendstall; - } - break; + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) + { + /* Clear End-point Feature */ + int ep = USBHS_SetupReqIndex & 0xf; + if( ( USBHS_SetupReqIndex & DEF_UEP_IN ) && ep < HUSB_CONFIG_EPS ) + { + UEP_CTRL_H(ep) = USBHS_UEP_T_TOG_DATA0 | USBHS_UEP_T_RES_NAK; + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + } + else + { + goto sendstall; + } + break; - /* set or enable one usb feature */ - case USB_SET_FEATURE: - if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_DEVICE) - { + /* set or enable one usb feature */ + case USB_SET_FEATURE: + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { #if HUSB_SUPPORTS_SLEEP - /* Set Device Feature */ - if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_REMOTE_WAKEUP) - { - /* Set Wake-up flag, device prepare to sleep */ - USBHS_DevSleepStatus |= 0x01; - } - else + /* Set Device Feature */ + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP ) + { + /* Set Wake-up flag, device prepare to sleep */ + USBHS_DevSleepStatus |= 0x01; + } + else #endif - { - goto sendstall; - } - } - else if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP) - { - /* Set Endpoint Feature */ - if ((uint8_t)(USBHS_IndexValue & 0xFF) == USB_REQ_FEAT_ENDP_HALT) - { - int ep = USBHS_SetupReqIndex & 0xf; - if ((USBHS_SetupReqIndex & DEF_UEP_IN) && ep < HUSB_CONFIG_EPS) - UEP_CTRL_H(ep) = (UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_STALL; - } - else - goto sendstall; - } - else - goto sendstall; - break; + { + goto sendstall; + } + } + else if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + /* Set Endpoint Feature */ + if( (uint8_t)( USBHS_IndexValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT ) + { + int ep = USBHS_SetupReqIndex & 0xf; + if( ( USBHS_SetupReqIndex & DEF_UEP_IN ) && ep < HUSB_CONFIG_EPS ) + UEP_CTRL_H(ep) = ( UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_STALL; + } + else + goto sendstall; + } + else + goto sendstall; + break; - /* This request allows the host to select another setting for the specified interface */ - case USB_GET_INTERFACE: - ctrl0buff[0] = 0x00; - if (USBHS_SetupReqLen > 1) USBHS_SetupReqLen = 1; - break; + /* This request allows the host to select another setting for the specified interface */ + case USB_GET_INTERFACE: + ctrl0buff[0] = 0x00; + if( USBHS_SetupReqLen > 1 ) USBHS_SetupReqLen = 1; + break; - case USB_SET_INTERFACE: - break; + case USB_SET_INTERFACE: + break; - /* host get status of specified device/interface/end-points */ - case USB_GET_STATUS: - ctrl0buff[0] = 0x00; - ctrl0buff[1] = 0x00; - if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_DEVICE) - { + /* host get status of specified device/interface/end-points */ + case USB_GET_STATUS: + ctrl0buff[0] = 0x00; + ctrl0buff[1] = 0x00; + if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE ) + { #if FUSB_SUPPORTS_SLEEP - ctrl0buff[0] = (ctx->USBHS_DevSleepStatus & 0x01) << 1; + ctrl0buff[0] = (ctx->USBHS_DevSleepStatus & 0x01)<<1; #else - ctrl0buff[0] = 0x00; + ctrl0buff[0] = 0x00; #endif - } - else if ((USBHS_SetupReqType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP) - { - int ep = USBHS_SetupReqIndex & 0xf; - if ((USBHS_SetupReqIndex & DEF_UEP_IN) && ep < HUSB_CONFIG_EPS) - ctrl0buff[0] = (UEP_CTRL_H(ep) & USBHS_UEP_T_RES_MASK) == USBHS_UEP_T_RES_STALL; - else - goto sendstall; - } - else - goto sendstall; - if (USBHS_SetupReqLen > 2) - USBHS_SetupReqLen = 2; - break; + } + else if( ( USBHS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP ) + { + int ep = USBHS_SetupReqIndex & 0xf; + if( ( USBHS_SetupReqIndex & DEF_UEP_IN ) && ep < HUSB_CONFIG_EPS ) + ctrl0buff[0] = ( UEP_CTRL_H(ep) & USBHS_UEP_T_RES_MASK ) == USBHS_UEP_T_RES_STALL; + else + goto sendstall; + } + else + goto sendstall; + if( USBHS_SetupReqLen > 2 ) + USBHS_SetupReqLen = 2; + break; - default: - goto sendstall; - break; - } - } + default: + goto sendstall; + break; + } + } - { - /* end-point 0 data Tx/Rx */ - if (USBHS_SetupReqType & DEF_UEP_IN) - { - len = (USBHS_SetupReqLen > DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : USBHS_SetupReqLen; - USBHS_SetupReqLen -= len; - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - } - else - { - if (USBHS_SetupReqLen == 0) - { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; - } - else - { - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - } - } - } - goto replycomplete; + { + /* end-point 0 data Tx/Rx */ + if( USBHS_SetupReqType & DEF_UEP_IN ) + { + len = ( USBHS_SetupReqLen > DEF_USBD_UEP0_SIZE )? DEF_USBD_UEP0_SIZE : USBHS_SetupReqLen; + USBHS_SetupReqLen -= len; + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + } + else + { + if( USBHS_SetupReqLen == 0 ) + { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_ACK; + } + else + { + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + } + } + } - // This might look a little weird, for error handling but it saves a nontrivial amount of storage, and simplifies - // control flow to hard-abort here. - sendstall: - // if one request not support, return stall. Stall means permanent error. - USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_STALL; - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_STALL; - replycomplete:; - } - if (intfgst & (CRB_UIF_TRANSFER)) - { - int token = (intfgst & CMASK_UIS_TOKEN) >> 12; - int ep = (intfgst & CMASK_UIS_ENDP) >> 8; - switch (token) - { - case CUIS_TOKEN_IN: - if (ep) - { - if (ep < HUSB_CONFIG_EPS) - { - UEP_CTRL_H(ep) = (UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_NAK; - UEP_CTRL_H(ep) ^= USBHS_UEP_T_TOG_DATA1; - ctx->USBHS_Endp_Busy[ep] = 0; - // Don't set EP in here. Wait for out. - // Optimization: Could we set EP here? - } - } - else - { - /* end-point 0 data in interrupt */ - if (ctx->USBHS_SetupReqLen == 0) - { - USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; - } + goto replycomplete; - if (ctx->pCtrlPayloadPtr) - { - // Shortcut mechanism, for descriptors or if the user wants it. - len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; - // DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); // FYI -> Would need to do this if using DMA - memcpy(ctrl0buff, ctx->pCtrlPayloadPtr, len); - ctx->USBHS_SetupReqLen -= len; - if (ctx->USBHS_SetupReqLen > 0) - ctx->pCtrlPayloadPtr += len; - else - ctx->pCtrlPayloadPtr = 0; + // This might look a little weird, for error handling but it saves a nontrivial amount of storage, and simplifies + // control flow to hard-abort here. + sendstall: + // if one request not support, return stall. Stall means permanent error. + USBHSD->UEP0_TX_CTRL = USBHS_UEP_T_TOG_DATA1 | USBHS_UEP_T_RES_STALL; + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_STALL; + replycomplete: + ; + } + if( intfgst & ( CRB_UIF_TRANSFER ) ) + { + int token = ( intfgst & CMASK_UIS_TOKEN) >> 12; + int ep = ( intfgst & CMASK_UIS_ENDP ) >> 8; + switch ( token ) + { + case CUIS_TOKEN_IN: + if( ep ) + { + if( ep < HUSB_CONFIG_EPS ) + { + UEP_CTRL_H(ep) = ( UEP_CTRL_H(ep) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_NAK; + UEP_CTRL_H(ep) ^= USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_Endp_Busy[ ep ] = 0; + // Don't set EP in here. Wait for out. + // Optimization: Could we set EP here? + } + } + else + { + /* end-point 0 data in interrupt */ + if( ctx->USBHS_SetupReqLen == 0 ) + { + USBHSD->UEP0_RX_CTRL = USBHS_UEP_R_TOG_DATA1 | USBHS_UEP_R_RES_ACK; + } - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; - } - else if ((ctx->USBHS_SetupReqType & USB_REQ_TYP_MASK) != USB_REQ_TYP_STANDARD) - { -#if HUSB_HID_USER_REPORTS - len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; - if (len && HSUSBCTX.USBHS_SetupReqCode == HID_GET_REPORT) - { - len = HandleHidUserReportDataIn(ctx, ctrl0buff, len); - USBHSD->UEP0_TX_LEN = len; - USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; - ctx->USBHS_SetupReqLen -= len; - ctx->pCtrlPayloadPtr += len; - } -#endif - } - else - { - switch (HSUSBCTX.USBHS_SetupReqCode) - { - case USB_GET_DESCRIPTOR: - break; + if( ctx->pCtrlPayloadPtr ) + { + // Shortcut mechanism, for descriptors or if the user wants it. + len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; + //DMA7FastCopy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); // FYI -> Would need to do this if using DMA + memcpy( ctrl0buff, ctx->pCtrlPayloadPtr, len ); + ctx->USBHS_SetupReqLen -= len; + if( ctx->USBHS_SetupReqLen > 0 ) + ctx->pCtrlPayloadPtr += len; + else + ctx->pCtrlPayloadPtr = 0; - case USB_SET_ADDRESS: - USBHSD->DEV_AD = ctx->USBHS_DevAddr; - break; - - default: - break; - } - } - } - - /* data-out stage processing */ - case CUIS_TOKEN_OUT: - switch (ep) - { - /* end-point 0 data out interrupt */ - case DEF_UEP0: - { - // XXX WARNINGS: - // 1. intfgst & CRB_UIS_TOG_OK is not set for non-odd transactions, i.e. first, third, etc, are all fine. - // 2. HandleHidUserReportOutComplete doesn't seem to work. - // if( intfgst & CRB_UIS_TOG_OK ) + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; + } + else if ( ( ctx->USBHS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) + { #if HUSB_HID_USER_REPORTS - int len = USBHSD->RX_LEN; - uint8_t *cptr = ctx->pCtrlPayloadPtr; - if (!cptr) - { - HandleHidUserReportDataOut(ctx, ctrl0buff, len); - } - else - { - int remain = ctx->USBHS_SetupReqLen - len; - if (remain < 0) - { - len += remain; - remain = 0; - } - // DMA7FastCopy( cptr, ctrl0buff, len ); - memcpy(cptr, ctrl0buff, len); - ctx->USBHS_SetupReqLen = remain; - if (remain > 0) - ctx->pCtrlPayloadPtr = cptr + len; - else - ctx->pCtrlPayloadPtr = 0; - } + len = ctx->USBHS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : ctx->USBHS_SetupReqLen; + if( len && HSUSBCTX.USBHS_SetupReqCode == HID_GET_REPORT ) + { + len = HandleHidUserReportDataIn( ctx, ctrl0buff, len ); + USBHSD->UEP0_TX_LEN = len; + USBHSD->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; + ctx->USBHS_SetupReqLen -= len; + ctx->pCtrlPayloadPtr += len; + } #endif + } + else + { + switch( HSUSBCTX.USBHS_SetupReqCode ) + { + case USB_GET_DESCRIPTOR: + break; + + case USB_SET_ADDRESS: + USBHSD->DEV_AD = ctx->USBHS_DevAddr; + break; + + default: + break; + } + } + } + + /* data-out stage processing */ + case CUIS_TOKEN_OUT: + switch( ep ) + { + /* end-point 0 data out interrupt */ + case DEF_UEP0: + { + // XXX WARNINGS: + // 1. intfgst & CRB_UIS_TOG_OK is not set for non-odd transactions, i.e. first, third, etc, are all fine. + // 2. HandleHidUserReportOutComplete doesn't seem to work. + //if( intfgst & CRB_UIS_TOG_OK ) - if (ctx->USBHS_SetupReqLen == 0) - { #if HUSB_HID_USER_REPORTS - // DMA7FastCopyComplete(); - HandleHidUserReportOutComplete(ctx); + int len = USBHSD->RX_LEN; + uint8_t * cptr = ctx->pCtrlPayloadPtr; + if( !cptr ) + { + HandleHidUserReportDataOut( ctx, ctrl0buff, len ); + } + else + { + int remain = ctx->USBHS_SetupReqLen - len; + if( remain < 0 ) + { + len += remain; + remain = 0; + } + //DMA7FastCopy( cptr, ctrl0buff, len ); + memcpy( cptr, ctrl0buff, len ); + ctx->USBHS_SetupReqLen = remain; + if( remain > 0 ) + ctx->pCtrlPayloadPtr = cptr + len; + else + ctx->pCtrlPayloadPtr = 0; + } #endif - } - // See above comment - // //USBHSD->UEP0_RX_CTRL ^= USBFS_UEP_R_TOG; + if( ctx->USBHS_SetupReqLen == 0 ) + { +#if HUSB_HID_USER_REPORTS + //DMA7FastCopyComplete(); + HandleHidUserReportOutComplete( ctx ); +#endif + } - break; - } - default: - // Any other out. (also happens with In) - HSUSBCTX.USBHS_Endp_Busy[ep] = 0x02; - USBHSD_UEP_RXCTRL(ep) = ((USBHSD_UEP_RXCTRL(ep)) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_NAK; + // See above comment + // //USBHSD->UEP0_RX_CTRL ^= USBFS_UEP_R_TOG; + + break; + } + default: + // Any other out. (also happens with In) + HSUSBCTX.USBHS_Endp_Busy[ ep ] = 0x02; + USBHSD_UEP_RXCTRL( ep ) = ((USBHSD_UEP_RXCTRL( ep )) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_NAK; #if HUSB_BULK_USER_REPORTS - HandleGotEPComplete(ctx, ep); + HandleGotEPComplete( ctx, ep ); #endif - break; - } - break; - case CUIS_TOKEN_SETUP: // Not actually used on this chip (It's done as a separate flag) - case CUIS_TOKEN_SOF: // Sof pack processing - break; + break; + } + break; + case CUIS_TOKEN_SETUP: // Not actually used on this chip (It's done as a separate flag) + case CUIS_TOKEN_SOF: // Sof pack processing + break; - default: - break; - } - } - if (intfgst & USBHS_UIF_BUS_RST) - { - /* usb reset interrupt processing */ - ctx->USBHS_DevConfig = 0; - ctx->USBHS_DevAddr = 0; - ctx->USBHS_DevSleepStatus = 0; - ctx->USBHS_DevEnumStatus = 0; + default : + break; + } + } + if(intfgst & USBHS_UIF_BUS_RST) + { + /* usb reset interrupt processing */ + ctx->USBHS_DevConfig = 0; + ctx->USBHS_DevAddr = 0; + ctx->USBHS_DevSleepStatus = 0; + ctx->USBHS_DevEnumStatus = 0; - USBHSD->DEV_AD = 0; - USBHS_InternalFinishSetup(); - } - if (intfgst & USBHS_UIF_SUSPEND) - { - USBHSD->INT_FG = USBHS_UIF_SUSPEND; - Delay_Us(10); + USBHSD->DEV_AD = 0; + USBHS_InternalFinishSetup( ); + } + if(intfgst & USBHS_UIF_SUSPEND) + { + USBHSD->INT_FG = USBHS_UIF_SUSPEND; + Delay_Us(10); - // USB suspend interrupt processing - if (USBHSD->MIS_ST & USBHS_UMS_SUSPEND) - { - HSUSBCTX.USBHS_DevSleepStatus |= 0x02; - if (HSUSBCTX.USBHS_DevSleepStatus == 0x03) - { - // TODO: Handle usb sleep here - } - } - else - { - HSUSBCTX.USBHS_DevSleepStatus &= ~0x02; - } - } + // USB suspend interrupt processing + if(USBHSD->MIS_ST & USBHS_UMS_SUSPEND) + { + HSUSBCTX.USBHS_DevSleepStatus |= 0x02; + if(HSUSBCTX.USBHS_DevSleepStatus == 0x03) + { + // TODO: Handle usb sleep here + } + } + else + { + HSUSBCTX.USBHS_DevSleepStatus &= ~0x02; + } + } - USBHSD->INT_FG = intfgst; + USBHSD->INT_FG = intfgst; } void USBHS_InternalFinishSetup() { - // To reconfigure your endpoints for TX/RX do it here. + + // To reconfigure your endpoints for TX/RX do it here. #if HUSB_CONFIG_EPS > 5 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN | USBHS_UEP5_R_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN + | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN | USBHS_UEP5_R_EN; #elif HUSB_CONFIG_EPS > 4 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN + | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN | USBHS_UEP4_T_EN; #elif HUSB_CONFIG_EPS > 3 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN + | USBHS_UEP2_T_EN | USBHS_UEP3_T_EN; #elif HUSB_CONFIG_EPS > 2 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN | USBHS_UEP2_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN + | USBHS_UEP2_T_EN; #elif HUSB_CONFIG_EPS > 1 - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN | USBHS_UEP1_T_EN; #else - USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN; + USBHSD->ENDP_CONFIG = USBHS_UEP0_T_EN | USBHS_UEP0_R_EN; #endif - // This is really cursed. Somehow it doesn't explode. - // But, normally the USB wants a separate buffer here. + // This is really cursed. Somehow it doesn't explode. + // But, normally the USB wants a separate buffer here. #if HUSB_CONFIG_EPS > 5 - // Feel free to override any of these. - USBHSD->UEP5_MAX_LEN = 64; - USBHSD->UEP5_RX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[5]; - USBHSD->UEP5_RX_CTRL = USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_AUTO; // For bulk-out, I think you need to do this. + // Feel free to override any of these. + USBHSD->UEP5_MAX_LEN = 64; + USBHSD->UEP5_RX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[5]; + USBHSD->UEP5_RX_CTRL = USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_AUTO; // For bulk-out, I think you need to do this. #endif #if HUSB_CONFIG_EPS > 4 - USBHSD->UEP4_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP4_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[4]; + USBHSD->UEP4_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP4_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[4]; #endif #if HUSB_CONFIG_EPS > 3 - USBHSD->UEP3_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP3_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[3]; + USBHSD->UEP3_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP3_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[3]; #endif #if HUSB_CONFIG_EPS > 2 - USBHSD->UEP2_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP2_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[2]; + USBHSD->UEP2_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP2_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[2]; #endif #if HUSB_CONFIG_EPS > 1 - USBHSD->UEP1_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? - USBHSD->UEP1_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[1]; + USBHSD->UEP1_MAX_LEN = 64; // TODO: change to dynamic size, as USB HS supports more than 64? + USBHSD->UEP1_TX_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[1]; #endif #if HUSB_CONFIG_EPS > 0 - USBHSD->UEP0_MAX_LEN = 64; - USBHSD->UEP0_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[0]; + USBHSD->UEP0_MAX_LEN = 64; + USBHSD->UEP0_DMA = (uintptr_t)HSUSBCTX.ENDPOINTS[0]; #else #error You must have at least EP0! #endif - UEP_CTRL_H(0) = USBHS_UEP_R_RES_ACK | USBHS_UEP_T_RES_NAK; - int i; - for (i = 1; i < HUSB_CONFIG_EPS; i++) - UEP_CTRL_H(i) = USBFS_UEP_T_RES_NAK; + UEP_CTRL_H(0) = USBHS_UEP_R_RES_ACK | USBHS_UEP_T_RES_NAK; + int i; + for( i = 1; i < HUSB_CONFIG_EPS; i++ ) + UEP_CTRL_H(i) = USBFS_UEP_T_RES_NAK; - for (uint8_t i = 0; i < sizeof(HSUSBCTX.USBHS_Endp_Busy) / sizeof(HSUSBCTX.USBHS_Endp_Busy[0]); i++) - { - HSUSBCTX.USBHS_Endp_Busy[i] = 0; - } + for(uint8_t i=0; i< sizeof(HSUSBCTX.USBHS_Endp_Busy)/sizeof(HSUSBCTX.USBHS_Endp_Busy[0]); i++ ) + { + HSUSBCTX.USBHS_Endp_Busy[ i ] = 0; + } } int HSUSBSetup() { - // Set USB clock source to USBPHY - RCC->CFGR2 &= ~(1 << 31); - RCC->CFGR2 |= RCC_USBCLK48MCLKSource_USBPHY << 31; + // Set USB clock source to USBPHY + RCC->CFGR2 &= ~(1 << 31); + RCC->CFGR2 |= RCC_USBCLK48MCLKSource_USBPHY << 31; - // Set PLL clock source to HSE - RCC->CFGR2 &= ~(1 << 27); - RCC->CFGR2 |= RCC_HSBHSPLLCLKSource_HSE << 27; + // Set PLL clock source to HSE + RCC->CFGR2 &= ~(1 << 27); + RCC->CFGR2 |= RCC_HSBHSPLLCLKSource_HSE << 27; - // Configure PLL for USB - RCC->CFGR2 &= ~(7 << 24); - RCC->CFGR2 |= RCC_USBPLL_Div2 << 24; + // Configure PLL for USB + RCC->CFGR2 &= ~(7 << 24); + RCC->CFGR2 |= RCC_USBPLL_Div2 << 24; - // Configure reference clock - RCC->CFGR2 &= ~(3 << 28); - RCC->CFGR2 |= RCC_USBHSPLLCKREFCLK_4M << 28; + // Configure reference clock + RCC->CFGR2 &= ~(3 << 28); + RCC->CFGR2 |= RCC_USBHSPLLCKREFCLK_4M << 28; - // Enable USB high-speed peripheral - RCC->CFGR2 |= (1 << 30); - RCC->AHBPCENR |= RCC_AHBPeriph_USBHS | RCC_AHBPeriph_DMA1; + // Enable USB high-speed peripheral + RCC->CFGR2 |= (1 << 30); + RCC->AHBPCENR |= RCC_AHBPeriph_USBHS | RCC_AHBPeriph_DMA1; - // Initialize USB module - USBHSD->CONTROL = USBHS_UC_CLR_ALL | USBHS_UC_RESET_SIE; - Delay_Us(10); - USBHSD->CONTROL = 0; + // Initialize USB module + USBHSD->CONTROL = USBHS_UC_CLR_ALL | USBHS_UC_RESET_SIE; + Delay_Us(10); + USBHSD->CONTROL = 0; - // Initialize USB device config - USBHSD->HOST_CTRL = USBHS_UH_PHY_SUSPENDM; - USBHSD->CONTROL = USBHS_UC_DMA_EN | USBHS_UC_INT_BUSY | USBHS_UC_SPEED_HIGH; - USBHSD->INT_EN = USBHS_UIE_SETUP_ACT | USBHS_UIE_TRANSFER | USBHS_UIE_DETECT | USBHS_UIE_SUSPEND; + // Initialize USB device config + USBHSD->HOST_CTRL = USBHS_UH_PHY_SUSPENDM; + USBHSD->CONTROL = USBHS_UC_DMA_EN | USBHS_UC_INT_BUSY | USBHS_UC_SPEED_HIGH; + USBHSD->INT_EN = USBHS_UIE_SETUP_ACT | USBHS_UIE_TRANSFER | USBHS_UIE_DETECT | USBHS_UIE_SUSPEND; + + USBHS_InternalFinishSetup(); - USBHS_InternalFinishSetup(); + USBHSD->CONTROL |= USBHS_UC_DEV_PU_EN; + NVIC_EnableIRQ(USBHS_IRQn); - USBHSD->CONTROL |= USBHS_UC_DEV_PU_EN; - NVIC_EnableIRQ(USBHS_IRQn); - - // Go on-bus. - return 0; + // Go on-bus. + return 0; } + + diff --git a/inc/extralibs/hsusb_v30x.h b/inc/extralibs/hsusb_v30x.h index 49584be..013eb7d 100644 --- a/inc/extralibs/hsusb_v30x.h +++ b/inc/extralibs/hsusb_v30x.h @@ -7,74 +7,75 @@ This is referenced in Chapter 22 USB Host/Device Controller (USBHD) of CH32FV2x_V3xRM.pdf */ -#include "ch32fun.h" -#include "usb_config.h" -#include "usb_defines.h" #include +#include "ch32fun.h" +#include "usb_defines.h" +#include "usb_config.h" struct _USBState { - // Setup Request - uint8_t USBHS_SetupReqCode; - uint8_t USBHS_SetupReqType; - uint16_t USBHS_SetupReqLen; // Used for tracking place along send. - uint32_t USBHS_IndexValue; + // Setup Request + uint8_t USBHS_SetupReqCode; + uint8_t USBHS_SetupReqType; + uint16_t USBHS_SetupReqLen; // Used for tracking place along send. + uint32_t USBHS_IndexValue; - // USB Device Status - uint16_t USBHS_DevConfig; - uint16_t USBHS_DevAddr; - uint8_t USBHS_DevSleepStatus; - uint8_t USBHS_DevEnumStatus; + // USB Device Status + uint16_t USBHS_DevConfig; + uint16_t USBHS_DevAddr; + uint8_t USBHS_DevSleepStatus; + uint8_t USBHS_DevEnumStatus; - uint8_t *pCtrlPayloadPtr; + uint8_t * pCtrlPayloadPtr; - uint8_t ENDPOINTS[HUSB_CONFIG_EPS][64]; + uint8_t ENDPOINTS[HUSB_CONFIG_EPS][64]; -#define CTRL0BUFF (HSUSBCTX.ENDPOINTS[0]) -#define pUSBHS_SetupReqPak ((tusb_control_request_t *)CTRL0BUFF) + #define CTRL0BUFF (HSUSBCTX.ENDPOINTS[0]) + #define pUSBHS_SetupReqPak ((tusb_control_request_t*)CTRL0BUFF) #if HUSB_HID_INTERFACES > 0 - uint8_t USBHS_HidIdle[HUSB_HID_INTERFACES]; - uint8_t USBHS_HidProtocol[HUSB_HID_INTERFACES]; + uint8_t USBHS_HidIdle[HUSB_HID_INTERFACES]; + uint8_t USBHS_HidProtocol[HUSB_HID_INTERFACES]; #endif - volatile uint8_t USBHS_Endp_Busy[HUSB_CONFIG_EPS]; + volatile uint8_t USBHS_Endp_Busy[HUSB_CONFIG_EPS]; }; // Provided functions: -int HSUSBSetup(); +int HSUSBSetup(); uint8_t USBHS_Endp_DataUp(uint8_t endp, const uint8_t *pbuf, uint16_t len, uint8_t mod); // Implement the following: #if HUSB_HID_USER_REPORTS -int HandleHidUserGetReportSetup(struct _USBState *ctx, tusb_control_request_t *req); -int HandleHidUserSetReportSetup(struct _USBState *ctx, tusb_control_request_t *req); -void HandleHidUserReportDataOut(struct _USBState *ctx, uint8_t *data, int len); -int HandleHidUserReportDataIn(struct _USBState *ctx, uint8_t *data, int len); -void HandleHidUserReportOutComplete(struct _USBState *ctx); +int HandleHidUserGetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); +int HandleHidUserSetReportSetup( struct _USBState * ctx, tusb_control_request_t * req ); +void HandleHidUserReportDataOut( struct _USBState * ctx, uint8_t * data, int len ); +int HandleHidUserReportDataIn( struct _USBState * ctx, uint8_t * data, int len ); +void HandleHidUserReportOutComplete( struct _USBState * ctx ); #endif #if HUSB_BULK_USER_REPORTS -void HandleGotEPComplete(struct _USBState *ctx, int ep); +void HandleGotEPComplete( struct _USBState * ctx, int ep ); #endif extern struct _USBState HSUSBCTX; + // To TX, you can use USBFS_GetEPBufferIfAvailable or USBHSD_UEP_TXBUF( endp ) -static inline uint8_t *USBHS_GetEPBufferIfAvailable(int endp) +static inline uint8_t * USBHS_GetEPBufferIfAvailable( int endp ) { - if (HSUSBCTX.USBHS_Endp_Busy[endp]) return 0; - return USBHSD_UEP_TXBUF(endp); + if( HSUSBCTX.USBHS_Endp_Busy[ endp ] ) return 0; + return USBHSD_UEP_TXBUF( endp ); } -static inline void USBHS_SendEndpoint(int endp, int len, const uint8_t *data) +static inline void USBHS_SendEndpoint( int endp, int len, const uint8_t * data ) { - if (endp) - { - (((uint32_t *)(&USBHSD->UEP1_TX_DMA))[2 - 1]) = (uintptr_t)data; - } - USBHSD_UEP_TLEN(endp) = len; - USBHSD_UEP_TXCTRL(endp) = (USBHSD_UEP_TXCTRL(endp) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_ACK; - HSUSBCTX.USBHS_Endp_Busy[endp] = 0x01; + if( endp ) + { + (((uint32_t*)(&USBHSD->UEP1_TX_DMA))[2-1]) = (uintptr_t)data; + } + USBHSD_UEP_TLEN( endp ) = len; + USBHSD_UEP_TXCTRL( endp ) = ( USBHSD_UEP_TXCTRL( endp ) & ~USBHS_UEP_T_RES_MASK ) | USBHS_UEP_T_RES_ACK; + HSUSBCTX.USBHS_Endp_Busy[ endp ] = 0x01; } #endif diff --git a/inc/extralibs/iSLER.h b/inc/extralibs/iSLER.h new file mode 100644 index 0000000..ddee7cc --- /dev/null +++ b/inc/extralibs/iSLER.h @@ -0,0 +1,852 @@ +#include +#include +#include +#include + +#ifdef CH570_CH572 +#define CRCPOLY1 BB2 +#define ACCESSADDRESS1 BB3 +#define RSSI BB12 // ? couldn't find it, not sure +#define CTRL_TX BB13 +#define CRCINIT2 BB22 +#define CRCPOLY2 BB23 +#define ACCESSADDRESS2 BB24 +#define TMR LL25 +#define TXBUF LL30 +#define RXBUF LL31 +#define CTRL_MOD_RFSTOP 0xfffff8ff +#define DEVSETMODE_ON ((BB->CTRL_CFG & 0xfffcffff) | 0x20000) +#define DEVSETMODE_OFF ((BB->CTRL_CFG & 0xfffcffff) | 0x10000) +#define DEVSETMODE_TUNE 0x0558 +#define DEVSETMODE_TX 0x0258 +#define DEVSETMODE_RX 0x0158 +#define CTRL_CFG_PHY_1M ((BB->CTRL_CFG & 0xfffffcff) | 0x100) +#define CTRL_CFG_PHY_2M (BB->CTRL_CFG & 0xfffffcff) +#define LL_STATUS_TX 0x20000 +#define CTRL_CFG_START_TX 0x1000000 +#elif defined(CH571_CH573) +#define TXBUF DMA4 +#define ACCESSADDRESS1 BB2 +#define CTRL_TX BB11 +#define RSSI BB12 // ? couldn't find it, not sure +#define TMR LL24 +#define TXBUF LL28 +#define RXBUF LL29 +#define RFEND_TXCTUNE_INIT 0x180000 +#define CTRL_MOD_RFSTOP 0xfffffff8 +#define DEVSETMODE_TUNE 0x5d +#define DEVSETMODE_TX 0x5a +#define DEVSETMODE_RX 0x59 +#define CTRL_CFG_PHY_1M (BB->CTRL_CFG | 0x10000000) +#define LL_STATUS_TX 0x20000 +#define CTRL_CFG_START_TX (BB->CTRL_CFG & 0xefffffff) +#elif defined(CH582_CH583) +#define ACCESSADDRESS1 BB2 +#define CTRL_TX BB11 +#define RSSI BB12 +#define TMR LL25 +#define TXBUF LL28 +#define RXBUF LL29 +#define RFEND_TXCTUNE_INIT 0x880000 +#define CTRL_TX_TXPOWER 0x80010e78 +#define CTRL_MOD_RFSTOP 0xfffffff8 +#define DEVSETMODE_ON ((BB->CTRL_CFG & 0xfffffe7f) | 0x100) +#define DEVSETMODE_OFF ((BB->CTRL_CFG & 0xfffffe7f) | 0x80) +#define DEVSETMODE_TUNE 0x00dd +#define DEVSETMODE_TX 0x00da +#define DEVSETMODE_RX 0x00d9 +#define CTRL_CFG_PHY_1M ((BB->CTRL_CFG & 0xffff0fff) | 0x1000) +#define CTRL_CFG_PHY_2M (BB->CTRL_CFG & 0xffff0fff) +#define CTRL_CFG_PHY_CODED ((BB->CTRL_CFG & 0xffff0fff) | 0x2000) +#define LL_STATUS_TX 0x2000 +#define CTRL_CFG_START_TX 0x800000 +#elif (defined(CH584_CH585) || defined(CH591_CH592)) +#define ACCESSADDRESS1 BB2 +#define CTRL_TX BB11 +#define RSSI BB12 +#define TMR LL25 +#define TXBUF LL30 +#define RXBUF LL31 +#define CTRL_MOD_RFSTOP 0xfffff8ff +#define DEVSETMODE_ON ((BB->CTRL_CFG & 0xfffffcff) | 0x280) +#define DEVSETMODE_OFF ((BB->CTRL_CFG & 0xfffffcff) | 0x100) +#define DEVSETMODE_TUNE 0x0558 +#define DEVSETMODE_TX 0x0258 +#define DEVSETMODE_RX 0x0158 +#define CTRL_CFG_PHY_1M (BB->CTRL_CFG & 0xffffff7f) +#define CTRL_CFG_PHY_2M (BB->CTRL_CFG | 0x80) +#define LL_STATUS_TX 0x20000 +#define CTRL_CFG_START_TX 0x800000 +#elif defined(CH32V20x) +#define CH32V208 +#define ACCESSADDRESS1 BB2 +#define CTRL_TX BB11 +#define RSSI BB12 +#define TMR LL25 +#define TXBUF LL28 +#define RXBUF LL29 +#define RFEND_TXCTUNE_INIT 0x100000 +#define CTRL_TX_TXPOWER 0x80010ec8 +#define CTRL_MOD_RFSTOP 0xfffffff8 +#define DEVSETMODE_ON ((BB->CTRL_CFG & 0xfffffe7f) | 0x100) +#define DEVSETMODE_OFF ((BB->CTRL_CFG & 0xfffffe7f) | 0x80) +#define DEVSETMODE_TUNE 0x5d +#define DEVSETMODE_TX 0x5a +#define DEVSETMODE_RX 0x59 +#define CTRL_CFG_PHY_1M ((BB->CTRL_CFG & 0xffff0fff) | 0x1000) +#define CTRL_CFG_PHY_2M (BB->CTRL_CFG & 0xffff0fff) +#define CTRL_CFG_PHY_CODED ((BB->CTRL_CFG & 0xffff0fff) | 0x2000) +#define LL_STATUS_TX 0x2000 +#define CTRL_CFG_START_TX 0x800000 +#else +#error "MCU_TARGET selected in Makefile is not supported" +#endif + +#ifdef CH32V208 +#define BB_BASE (0x40024100) // Baseband, digital part of the PHY +#define LL_BASE (0x40024200) // Link Layer, MAC +#define RF_BASE (0x40025000) // Radio frontend, analog part of the PHY +#else +#define DMA_BASE (0x4000c000) +#define BB_BASE (0x4000c100) +#define LL_BASE (0x4000c200) +#define RF_BASE (0x4000d000) +#endif + +#define DMA ((DMA_Type *) DMA_BASE) +#define BB ((BB_Type *) BB_BASE) +#define LL ((LL_Type *) LL_BASE) +#define RF ((RF_Type *) RF_BASE) + +#ifdef CH571_CH573 +typedef struct { + volatile uint32_t DMA0; + volatile uint32_t DMA1; + volatile uint32_t DMA2; + volatile uint32_t DMA3; + volatile uint32_t DMA4; + volatile uint32_t DMA5; + volatile uint32_t DMA6; + volatile uint32_t DMA7; +} DMA_Type; +#endif + +typedef struct { + // bits 0..5 = Channel + // bit 6 = disable whitening. + // bit 8 = 1 during normal TX/operation, but clearing does not affect TX. Note: 0 at reset, set in software. + // bit 9 = settable, but unknown effect. + // bit 10 = 1 during normal TX/operation, but clearing does not affect TX. Note: 1 at reset, not touched in software. + // bit 16 = cleared by firmware upon TX, but does not seem to have an effect on the TX. + // bit 17 = settable, but unknown effect + // bit 20 = settable, but unknown effect. + // bit 24 = set at end of tx routine + // bit 29-31 = settable, but unknown effect. + volatile uint32_t CTRL_CFG; + + volatile uint32_t CRCINIT1; + volatile uint32_t BB2; // ch570/2: CRCPOLY1, [ch582/3 ch591/2]: ACCESSADDRESS1 + volatile uint32_t BB3; // ch570/2 ACCESSADDRESS1 + volatile uint32_t BB4; + volatile uint32_t BB5; + volatile uint32_t BB6; + volatile uint32_t BB7; + volatile uint32_t BB8; + volatile uint32_t BB9; + volatile uint32_t BB10; + volatile uint32_t BB11; // ch582/3, ch584/5, ch591/2: CTRL_TX + volatile uint32_t BB12; + + // default, pre TX is a4000009 + // bit 0: Set normally, but cleared in software when TXing (maybe a ready bit?) + // bit 1: Unset normally, but cleared anyway by software when TXing (maybe a fault bit?) + // bit 2: Disables TX. + // bit 4: Normally 0, but, if set to 1, seems to increase preamble length. + // bit 8: Normally 0, but, if set, no clear effect. + // bit 9: Normally 0, but, if set, no clear effect. + // bits 24-30: TX Power. Normally 0xA4 + // Oddly, bit 31 seems to maybe be always set. + volatile uint32_t BB13; // ch570/2: CTRL_TX + volatile uint32_t BB14; + volatile uint32_t BB15; + volatile uint32_t BB16; + volatile uint32_t BB17; + volatile uint32_t BB18; + volatile uint32_t BB19; + volatile uint32_t BB20; + volatile uint32_t BB21; + volatile uint32_t BB22; // ch570/2: CRCINIT2 + volatile uint32_t BB23; // ch570/2: CRCPOLY2 + volatile uint32_t BB24; // ch570/2: ACCESSADDRESS2 +} BB_Type; + +typedef struct { + volatile uint32_t LL0; + volatile uint32_t LL1; + volatile uint32_t STATUS; + volatile uint32_t INT_EN; + volatile uint32_t LL4; + volatile uint32_t LL5; + volatile uint32_t LL6; + volatile uint32_t LL7; + volatile uint32_t LL8; + volatile uint32_t LL9; + volatile uint32_t LL10; + volatile uint32_t LL11; + volatile uint32_t LL12; + volatile uint32_t LL13; + volatile uint32_t LL14; + volatile uint32_t LL15; + volatile uint32_t LL16; + volatile uint32_t LL17; + volatile uint32_t LL18; + volatile uint32_t LL19; + + // Controls a lot of higher-level functions. + // For Tuning: 0x30558 + // For Idle: 0x30000 + // For Sending:0x30258 + // Bit 3: Somehow, enables BB + // Bit 4: Normally 1, controls length/send times of BB, if unset, BB will double-send part of signals. + // Bit 6: Normally 1, Unknown effect. + // Bit 9: If 0, no output. + // Bit 10: Somehow required for TX? + // Bit 16-17: Normally 1, unknown effect. Seems to suppress odd carrier burst after message. + volatile uint32_t CTRL_MOD; + volatile uint32_t LL21; + volatile uint32_t LL22; + volatile uint32_t LL23; + volatile uint32_t LL24; // ch571/3: TMR + volatile uint32_t LL25; // ch570/2, ch582/3, ch591/2: TMR + volatile uint32_t LL26; + volatile uint32_t LL27; + volatile uint32_t LL28; // ch582/3: TXBUF + volatile uint32_t LL29; // ch582/3: RXBUF + volatile uint32_t LL30; // ch570/2, ch591/2: TXBUF + volatile uint32_t LL31; // ch570/2, ch591/2: RXBUF +} LL_Type; + +typedef struct { + volatile uint32_t RF0; + volatile uint32_t RF1; + volatile uint32_t RF2; + volatile uint32_t RF3; + volatile uint32_t RF4; + volatile uint32_t RF5; + volatile uint32_t RF6; + volatile uint32_t RF7; + volatile uint32_t RF8; + volatile uint32_t RF9; + volatile uint32_t RF10; + volatile uint32_t RF11; + volatile uint32_t RF12; + volatile uint32_t RF13; + volatile uint32_t TXTUNE_CTRL; + volatile uint32_t RF15; + volatile uint32_t RF16; + volatile uint32_t RF17; + volatile uint32_t RF18; + volatile uint32_t RF19; + volatile uint32_t RF20; + volatile uint32_t RF21; + volatile uint32_t RF22; + volatile uint32_t RF23; + volatile uint32_t RF24; + volatile uint32_t RF25; + volatile uint32_t RF26; + volatile uint32_t RF27; + volatile uint32_t RF28; + volatile uint32_t RF29; + volatile uint32_t RF30; + volatile uint32_t RF31; + volatile uint32_t RF32; + volatile uint32_t RF33; + volatile uint32_t RF34; + volatile uint32_t RF35; + volatile uint32_t TXCTUNE_CO_CTRL; + volatile uint32_t TXCTUNE_GA_CTRL; + volatile uint32_t RF38; + volatile uint32_t RXTUNE; + volatile uint32_t TXCTUNE_CO[10]; + volatile uint32_t TXCTUNE_GA[3]; +} RF_Type; + +uint8_t channel_map[] = {1,2,3,4,5,6,7,8,9,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,0,11,39}; +#define CO_MID (uint8_t)(RF->TXTUNE_CTRL & ~0xffffffc0) +#define GA_MID (uint8_t)((RF->TXTUNE_CTRL & ~0x80ffffff) >> 24) + +#define PHY_1M 1 +#define PHY_2M 2 +#define PHY_S2 4 +#define PHY_S8 8 + +void DevSetMode(uint16_t mode); +__attribute__((aligned(4))) uint32_t LLE_BUF[0x110]; +#ifdef CH571_CH573 +__attribute__((aligned(4))) uint32_t LLE_BUF2[0x110]; +#endif +volatile uint32_t tuneFilter; +volatile uint32_t tuneFilter2M; +volatile uint32_t rx_ready; + + + +#ifdef CH571_CH573 +__attribute__((interrupt)) +void BB_IRQHandler() { + // printf("BB\n"); + if(BB->BB14 & (1<<6)) { + BB->BB14 &= 0xffffff9f; + } + if(BB->BB14 & (1<<1)) { + BB->BB14 = 0xfffffffd; + BB->BB20 = 0x45; + } + if(BB->BB14 & (1<<4)) { + BB->BB14 = 0xffffffef; + BB->BB20 = 0; + } +} +#endif + +__attribute__((interrupt)) +void LLE_IRQHandler() { + // printf("LL\n"); +#ifdef CH571_CH573 + if(LL->STATUS & (1<<9)) { + LL->TMR = 400; + BB->CTRL_TX = (BB->CTRL_TX & 0xfffffffc) | 2; + BB->CTRL_CFG |= 0x10000000; + } + LL->STATUS = 0; +#elif defined(CH582_CH583) + if((LL->STATUS & (1<<14)) && (LL->INT_EN & (1<<14))) { + LL->LL26 = 0xffffffff; + LL->STATUS = 0x4000; + } + else +#endif + { + LL->STATUS &= LL->INT_EN; + BB->CTRL_TX = (BB->CTRL_TX & 0xfffffffc) | 1; + } + DevSetMode(0); + LL->CTRL_MOD &= CTRL_MOD_RFSTOP; + LL->LL0 |= 0x08; + +#ifdef ISLER_CALLBACK + ISLER_CALLBACK(); +#else + rx_ready = 1; +#endif +} + +void RFEND_Reset() { +#ifdef CH571_CH573 + RF->RF3 |= 0x1000; + ADD_N_NOPS(20); + RF->RF3 &= 0xffffefff; + ADD_N_NOPS(20); + RF->RF3 |= 0x1000; + ADD_N_NOPS(20); + RF->RF3 |= 1; + ADD_N_NOPS(20); + RF->RF3 &= 0xfffffffe; + ADD_N_NOPS(20); + RF->RF3 |= 1; + ADD_N_NOPS(20); + RF->RF3 |= 0x100; + ADD_N_NOPS(20); + RF->RF3 &= 0xfffffeff; + ADD_N_NOPS(20); + RF->RF3 |= 0x100; + ADD_N_NOPS(20); +#elif defined(CH32V208) + RF->RF3 = 0x1101; + ADD_N_NOPS(20); + RF->RF3 = 0; + ADD_N_NOPS(20); + RF->RF3 = 0x1101; +#endif +} + +void DevInit(uint8_t TxPower) { +#ifdef CH571_CH573 + DMA->DMA4 = (uint32_t)LLE_BUF; + DMA->DMA5 = (uint32_t)LLE_BUF; + DMA->DMA6 = (uint32_t)LLE_BUF2; + DMA->DMA7 = (uint32_t)LLE_BUF2; + DMA->DMA2 |= 0x2000; + DMA->DMA3 |= 0x2000; + DMA->DMA2 |= 0x1000; + DMA->DMA3 |= 0x1000; + DMA->DMA0 |= 2; + DMA->DMA0 |= 0x20; + + LL->LL5 = 0x50; + LL->LL7 = 10; + LL->LL9 = 0x8c; + LL->LL13 = 0x8c; + LL->LL17 = 0x50; + LL->LL19 = 10; +#elif defined(CH570_CH572) || defined(CH582_CH583) || defined(CH584_CH585) || defined(CH591_CH592) + LL->LL5 = 0x8c; + LL->LL7 = 0x76; + LL->LL9 = 0x8c; + LL->LL13 = 0x8c; + LL->LL17 = 0x8c; + LL->LL19 = 0x76; +#elif defined(CH32V208) + LL->LL5 = 0x8c; + LL->LL7 = 0x6c; + LL->LL9 = 0x8c; + LL->LL13 = 0x8c; + LL->LL17 = 0x8c; + LL->LL19 = 0x6c; +#endif + +#ifdef CH570_CH572 + LL->LL11 = 0x6c; + LL->LL15 = 0x6c; + LL->LL1 = 0x78; + LL->LL21 = 0; + LL->INT_EN = 0x16000f; +#elif defined(CH571_CH573) + LL->LL11 = 0x3c; + LL->LL15 = 0x3c; + LL->LL22 = 0xf6; + LL->INT_EN = 0xc303; + NVIC->FIBADDRR = 0x20000000; + NVIC->VTFADDR[2] = (uint32_t)LLE_IRQHandler -NVIC->FIBADDRR; +#elif defined(CH582_CH583) || defined(CH32V208) + LL->LL11 = 0x3c; + LL->LL15 = 0x3c; + LL->INT_EN = 0xf00f; +#elif defined(CH584_CH585) + LL->LL11 = 0x6e; + LL->LL15 = 0x6e; + LL->LL1 &= 0xffffffe1; + LL->LL21 = 0; + LL->INT_EN = 0x1f000f; +#elif defined(CH591_CH592) + LL->LL6 = 0x78; + LL->LL8 = 0xffffffff; + LL->LL11 = 0x6e; + LL->LL21 = 0x14; + LL->INT_EN = 0x1f000f; +#endif + + LL->RXBUF = (uint32_t)LLE_BUF; + LL->STATUS = 0xffffffff; + RF->RF10 = 0x480; + +#ifdef CH570_CH572 + RF->RF12 &= 0xfff9ffff; + RF->RF12 |= 0x70000000; + RF->RF15 = (RF->RF15 & 0xf8ffffff) | 0x2000000; + RF->RF15 = (RF->RF15 & 0x1fffffff) | 0x40000000; + RF->RF18 &= 0xfff8ffff; + RF->RF20 = (RF->RF20 & 0xfffff8ff) | 0x300; + RF->RF23 |= 0x70000; + RF->RF23 |= 0x700000; + + BB->BB14 = 0x2020c; + BB->BB15 = 0x50; + BB->CTRL_TX = (BB->CTRL_TX & 0x1ffffff) | (TxPower | 0x40) << 0x19; + BB->CTRL_CFG &= 0xfffffcff; +#elif defined(CH571_CH573) || defined(CH582_CH583) || defined(CH32V208) + RFEND_Reset(); + RF->RF18 = (RF->RF18 & 0x8fffffff) | 0x20000000; + RF->RF18 = (RF->RF18 & 0xf8ffffff) | 0x4000000; + RF->RF18 = (RF->RF18 & 0xfffffff0) | 9; + RF->RF18 &= 0xfff8ffff; + RF->RF18 |= 0x80000000; + RF->RF19 = (RF->RF19 & 0xfffffff8) | 3; + RF->RF19 = (RF->RF19 & 0xffffff8f) | 0x30; + RF->RF19 = (RF->RF19 & 0xfffff8ff) | 0x300; + RF->RF19 &= 0xfeffffff; + RF->RF19 |= 0x2000000; + RF->RF20 = (RF->RF20 & 0xffff0fff) | 0x4000; + RF->RF21 = (RF->RF21 & 0xfffffff0) | 0xc; + RF->RF21 |= 0x80; + RF->RF21 &= 0xffffefff; + RF->RF15 = (RF->RF15 & 0xffff0fff) | 0x8000; + RF->RF15 = (RF->RF15 & 0xf8ffffff) | 0x2000000; + RF->RF15 = (RF->RF15 & 0x1fffffff) | 0x40000000; + RF->RF11 |= 0x700000; + RF->RF11 &= 0xf8ffffff; + RF->RF11 = (RF->RF11 & 0xffffcfff) | 0x2000; + RF->RF11 = (RF->RF11 & 0xfffcffff) | 0x20000; + RF->RF12 &= 0xfffffff0; + RF->RF12 &= 0xffffff0f; + RF->RF12 &= 0xfffff8ff; + RF->RF12 |= 0x700000; + RF->RF12 = (RF->RF12 & 0x8fffffff) | 0x50000000; + RF->TXTUNE_CTRL = (RF->TXTUNE_CTRL & 0xff07ffff) | RFEND_TXCTUNE_INIT; + RF->TXTUNE_CTRL |= 0x80000000; + +#ifdef CH571_CH573 + BB->CTRL_CFG = (TxPower << 8) | BB->CTRL_CFG | 0x1008000; + BB->CTRL_CFG = (BB->CTRL_CFG & 0xffffc0ff) | (TxPower & 0x3f) << 8; + SYS_SAFE_ACCESS( + R16_AUX_POWER_ADJ = (TxPower < 0x15) ? (R16_AUX_POWER_ADJ & 0xffef): + (R16_AUX_POWER_ADJ | 0x10); + ); + BB->CTRL_TX = 0x10e78; + BB->BB6 |= 0x8000; + BB->BB6 = (BB->BB6 & 0xffff807f) | 0x3500; + BB->BB13 = 0x152; + + // NVIC->VTFADDR[3] = (uint32_t)BB_IRQHandler +0x14000000; // why 14000000? +#elif defined(CH582_CH583) || defined(CH32V208) + BB->CTRL_CFG |= 0x800000; + BB->CTRL_CFG |= 0x10000000; + BB->BB13 = 0x1d0; + BB->CTRL_TX = TxPower << 0x19 | CTRL_TX_TXPOWER; + BB->CTRL_TX = (BB->CTRL_TX & 0x81ffffff) | (TxPower & 0x3f) << 0x19; + BB->BB8 = 0x90083; + + // NVIC->VTFADDR[3] = (uint32_t)BB_IRQHandler +0x20000000; // why 20000000? +#endif +#elif defined(CH584_CH585) || defined(CH591_CH592) + RF->RF12 = (RF->RF12 & 0x8fffffff) | 0x10077700; + RF->RF15 = (RF->RF15 & 0x18ff0fff) | 0x42005000; + RF->RF19 &= 0xfffcff88; + RF->RF21 = (RF->RF21 & 0xfffffff0) | 9; + RF->RF23 &= 0xff88ffff; + + BB->CTRL_CFG |= 0x800000; + BB->BB14 = 0x3ff; // ch584/5 + BB->BB13 = 0x50; + BB->CTRL_TX = (BB->CTRL_TX & 0x81ffffff) | (TxPower & 0x3f) << 0x19; + uint32_t uVar3 = 0x1000000; + uint32_t uVar4 = RF->RF23 & 0xf8ffffff; + if(TxPower < 29) { // ch585: 27 + /* uVar3 and uVar4 are initialized properly already */ + } + else if(TxPower < 35) { + uVar3 = 0x3000000; + } + else if(TxPower < 59) { + uVar3 = 0x5000000; + } + else { + uVar4 = RF->RF23; + uVar3 = 0x7000000; + } + RF->RF23 = uVar4 | uVar3; + BB->BB15 = 0x2020c; // ch584/5 + BB->BB4 = (BB->BB4 & 0xffffffc0) | 0xe; +#endif + + NVIC->VTFIDR[3] = 0x14; +} + +void DevSetMode(uint16_t mode) { +#if !defined(CH571_CH573) + if(mode) { + BB->CTRL_CFG = DEVSETMODE_ON; + RF->RF2 |= 0x330000; + } + else { + BB->CTRL_CFG = DEVSETMODE_OFF; + RF->RF2 &= 0xffcdffff; + } +#ifdef CH582_CH583 + mode = (mode == 0) ? 0x80 : mode; +#elif !defined(CH32V208) + mode |= 0x30000; +#endif +#endif // ! CH571_CH573 + LL->CTRL_MOD = mode; +} + +uint32_t RFEND_TXCTune(uint8_t channel) { + // 0xbf = 2401 MHz + RF->RF1 &= 0xfffffffe; + RF->TXTUNE_CTRL = (RF->TXTUNE_CTRL & 0xfffe00ff) | (0xbf00 + (channel_map[channel] << 8)); + RF->RF1 |= 1; + + LL->TMR = 8000; + while(!(RF->TXCTUNE_CO_CTRL & (1 << 25)) || !(RF->TXCTUNE_CO_CTRL & (1 << 26))) { + if(LL->TMR == 0) { + break; + } + } + + uint8_t nCO = (uint8_t)RF->TXCTUNE_CO_CTRL & 0x3f; + uint8_t nGA = (uint8_t)(RF->TXCTUNE_GA_CTRL >> 10) & 0x7f; + + // printf("nCO,nGA ch:%u idx:%u %u,%u\n", channel, channel_map[channel], nCO,nGA); + + return (nGA << 24) | nCO; +} + +void RFEND_TXTune() { + RF->RF1 &= 0xfffffeff; + RF->RF10 &= 0xffffefff; + RF->RF11 &= 0xffffffef; + RF->RF2 |= 0x20000; + RF->RF1 |= 0x10; + + // 2401 MHz + uint32_t tune2401 = RFEND_TXCTune(37); + uint8_t nCO2401 = (uint8_t)(tune2401 & 0x3f); + uint8_t nGA2401 = (uint8_t)(tune2401 >> 24) & 0x7f; + + // 2480 MHz + uint32_t tune2480 = RFEND_TXCTune(39); + uint8_t nCO2480 = (uint8_t)(tune2480 & 0x3f); + uint8_t nGA2480 = (uint8_t)(tune2480 >> 24) & 0x7f; + + // 2440 MHz + uint32_t tune2440 = RFEND_TXCTune(18); + uint8_t nCO2440 = (uint8_t)(tune2440 & 0x3f); + uint8_t nGA2440 = (uint8_t)(tune2440 >> 24) & 0x7f; + + uint32_t dCO0140 = nCO2401 - nCO2440; + uint32_t dCO4080 = nCO2440 - nCO2480; + uint8_t tune = 0; + uint8_t int_points = sizeof(RF->TXCTUNE_CO) /2; + uint8_t txctune_co[sizeof(RF->TXCTUNE_CO)] = {0}; + for(int f = 0; f < int_points; f++) { + tune = (dCO0140 * (int_points -f)) / int_points; + txctune_co[f] = tune | (tune << 4); + } + for(int f = int_points; f < sizeof(RF->TXCTUNE_CO); f++) { + tune = (dCO4080 * (f -int_points)) / int_points; + txctune_co[f] = tune | (tune << 4); + } + for(int i = 0; i < sizeof(txctune_co) /4; i++) { + RF->TXCTUNE_CO[i] = ((uint32_t*)txctune_co)[i]; + } + + // This GA interpolating is not exactly what is done in EVT + // Actually the reception on a BLE monitor is better when this is left out completely + // This will need some proper experimentation by people with 2.4GHz SDRs + uint32_t dGA0140 = nGA2401 - nGA2440; + uint32_t dGA4080 = nGA2440 - nGA2480; + int_points = sizeof(RF->TXCTUNE_GA) /2; + uint8_t txctune_ga[sizeof(RF->TXCTUNE_GA)] = {0}; + for(int f = 1; f < int_points; f++) { + tune = (dGA0140 * (int_points -f)) / int_points; + txctune_ga[f] = tune | (tune << 4); + } + for(int f = int_points; f < sizeof(RF->TXCTUNE_GA) -1; f++) { + tune = (dGA4080 * (f -int_points)) / int_points; + txctune_ga[f] = tune | (tune << 4); + } + for(int i = 0; i < (sizeof(txctune_ga) /4); i++) { + RF->TXCTUNE_GA[i] = ((uint32_t*)txctune_ga)[i]; + } + + +#if 0 + printf("2401 2440 2480 CO: %u %u %u, GA: %u %u %u\n", nCO2401, nCO2440, nCO2480, nGA2401, nGA2440, nGA2480); + for(int i = 0; i < 10; i++ ) { + printf( "%d: %08lx\n", i, RF->TXCTUNE_CO[i] ); + } + for(int i = 0; i < 3; i++ ) { + printf( "%d: %08lx\n", i, RF->TXCTUNE_GA[i] ); + } +#endif + + RF->RF1 &= 0xffffffef; + RF->RF1 &= 0xfffffffe; + RF->RF10 |= 0x1000; + RF->RF11 |= 0x10; + RF->TXTUNE_CTRL = (RF->TXTUNE_CTRL & 0xffffffc0) | (tune2440 & 0x3f); + RF->TXTUNE_CTRL = (RF->TXTUNE_CTRL & 0x80ffffff) | (tune2440 & 0x7f000000); + + // FTune + RF->RF1 |= 0x100; +} + +void RFEND_RXTune() { + RF->RF20 &= 0xfffeffff; + RF->RF2 |= 0x200000; + RF->RF3 = (RF->RF3 & 0xffffffef) | 0x10; + RF->RF1 |= 0x1000; + + LL->TMR = 100; + while(LL->TMR && ((RF->RXTUNE >> 8) & 1)); + + tuneFilter = RF->RXTUNE & 0x1f; + RF->RF20 |= 0x10000; + RF->RF20 = (RF->RF20 & 0xffffffe0) | tuneFilter; + RF->RF2 &= 0xffdfffff; + tuneFilter2M = (tuneFilter +2 < 0x1f) ? (tuneFilter +2) : 0x1f; + + // RXADC + RF->RF22 &= 0xfffeffff; + RF->RF2 |= 0x10000; + RF->RF3 = (RF->RF3 & 0xfffffeff) | 0x100; + RF->RF1 = (RF->RF1 & 0xfffeffff) | 0x100000; +} + +void RegInit() { + DevSetMode(DEVSETMODE_TUNE); + RFEND_TXTune(); + RFEND_RXTune(); + DevSetMode(0); +} + +void RFCoreInit(uint8_t TxPower) { +#if defined(CH571_CH573) || defined(CH584_CH585) // maybe all? + NVIC->IENR[0] = 0x1000; + NVIC->IRER[0] = 0x1000; +#endif + DevInit(TxPower); + RegInit(); + NVIC->IPRIOR[0x15] |= 0x80; + NVIC_EnableIRQ(LLE_IRQn); +} + +void DevSetChannel(uint8_t channel) { +#ifdef CH571_CH573 + BB->BB6 = (BB->BB6 & 0xf8ffffff) | 0x4000000; + BB->BB6 = (BB->BB6 & 0xffffff83) | 0x1c; +#endif + RF->RF11 &= 0xfffffffd; + BB->CTRL_CFG = (BB->CTRL_CFG & 0xffffff80) | (channel & 0x7f); +} + +__HIGH_CODE +int8_t ReadRSSI() { + return (int8_t)(BB->RSSI >> 0xf); +} + +__HIGH_CODE +void Frame_TX(uint32_t access_address, uint8_t adv[], size_t len, uint8_t channel, uint8_t phy_mode) { + BB->CTRL_TX = (BB->CTRL_TX & 0xfffffffc) | 1; + + DevSetChannel(channel); + + // Uncomment to disable whitening to debug RF. + //BB->CTRL_CFG |= (1<<6); + DevSetMode(DEVSETMODE_TX); + + BB->ACCESSADDRESS1 = access_address; // access address + BB->CRCINIT1 = 0x555555; // crc init +#ifdef CH570_CH572 + BB->ACCESSADDRESS2 = access_address; + BB->CRCINIT2 = 0x555555; + BB->CRCPOLY1 = (BB->CRCPOLY1 & 0xff000000) | 0x80032d; // crc poly + BB->CRCPOLY2 = (BB->CRCPOLY2 & 0xff000000) | 0x80032d; +#endif + +#if defined(CH571_CH573) + DMA->TXBUF = (uint32_t)adv; +#else + LL->TXBUF = (uint32_t)adv; +#endif + + // Wait for tuning bit to clear. + for( int timeout = 3000; !(RF->RF26 & 0x1000000) && timeout >= 0; timeout-- ); + +#if defined(CH582_CH583) || defined(CH32V208) + BB->CTRL_CFG = (phy_mode == PHY_2M) ? CTRL_CFG_PHY_2M: + (phy_mode == PHY_S2) ? CTRL_CFG_PHY_CODED: + (phy_mode == PHY_S8) ? CTRL_CFG_PHY_CODED: + CTRL_CFG_PHY_1M; // default 1M for now + if(phy_mode > PHY_2M) { // coded phy + BB->CTRL_CFG = (BB->CTRL_CFG & 0xffff3fff) | ((phy_mode == PHY_S2) ? 0x4000 : 0); + } +#elif defined(CH571_CH573) + BB->CTRL_CFG = CTRL_CFG_PHY_1M; // no 2M PHY on ch571/3 +#else + BB->CTRL_CFG = (phy_mode == PHY_2M) ? CTRL_CFG_PHY_2M: + CTRL_CFG_PHY_1M; // default 1M for now +#endif + +#if defined(CH570_CH572) + BB->BB9 = (BB->BB9 & 0xf9ffffff) | ((phy_mode == PHY_2M) ? 0 : 0x2000000); +#endif + +#if defined(CH571_CH573) + BB->BB11 = (BB->BB11 & 0xfffffffc); // |2 for RX +#endif + + // This clears bit 17 (If set, seems to have no impact.) + LL->LL4 &= 0xfffdffff; + +#if !defined(CH571_CH573) + LL->STATUS = LL_STATUS_TX; +#endif + LL->TMR = (uint32_t)(len *512); // needs optimisation, per phy mode + + BB->CTRL_CFG |= CTRL_CFG_START_TX; + BB->CTRL_TX &= 0xfffffffc; + + LL->LL0 = 2; // Not sure what this does, but on RX it's 1 + + while(LL->TMR); // wait for tx buffer to empty + DevSetMode(0); + if(LL->LL0 & 3) { + LL->CTRL_MOD &= CTRL_MOD_RFSTOP; + LL->LL0 |= 0x08; + } +} + +__HIGH_CODE +void Frame_RX(uint32_t access_address, uint8_t channel, uint8_t phy_mode) { + DevSetMode(0); + if(LL->LL0 & 3) { + LL->CTRL_MOD &= CTRL_MOD_RFSTOP; + LL->LL0 |= 0x08; + } + LL->TMR = 0; + + DevSetChannel(channel); + DevSetMode(DEVSETMODE_RX); + +#if defined(CH582_CH583) || defined(CH32V208) + BB->CTRL_CFG = (phy_mode == PHY_2M) ? CTRL_CFG_PHY_2M: + (phy_mode == PHY_S2) ? CTRL_CFG_PHY_CODED: + (phy_mode == PHY_S8) ? CTRL_CFG_PHY_CODED: + CTRL_CFG_PHY_1M; // default 1M for now + if(phy_mode > PHY_2M) { // coded phy + BB->CTRL_CFG = (BB->CTRL_CFG & 0xffff3fff) | ((phy_mode == PHY_S2) ? 0x4000 : 0); + } +#elif defined(CH571_CH573) + BB->CTRL_CFG = CTRL_CFG_PHY_1M; // no 2M PHY on ch571/3 +#else + BB->CTRL_CFG = (phy_mode == PHY_2M) ? CTRL_CFG_PHY_2M: + CTRL_CFG_PHY_1M; // default 1M for now +#endif + +#ifdef CH570_CH572 + BB->BB9 = (BB->BB9 & 0xf9ffffff) | ((phy_mode == PHY_2M) ? 0 : 0x2000000); + RF->RF20 = (RF->RF20 & 0xffffffe0) | ((phy_mode == PHY_2M) ? (tuneFilter2M & 0x1f) : (tuneFilter & 0x1f)); + BB->BB5 = (BB->BB5 & 0xffffffc0) | ((phy_mode == PHY_2M) ? 0xd : 0xb); + BB->BB7 = (BB->BB7 & 0xff00fc00) | ((phy_mode == PHY_2M) ? 0x7f00a0 : 0x79009c); +#elif defined(CH571_CH573) + BB->BB11 = (BB->BB11 & 0xfffffffc) | 2; // no |2 for TX +#elif defined(CH582_CH583) || defined(CH32V208) +#if defined(CH582_CH583) + BB->BB4 = (phy_mode < PHY_S2) ? 0x3722d0 : 0x3722df; +#elif defined(CH32V208) + BB->BB4 = (phy_mode < PHY_S2) ? 0x3222d0 : 0x34a4df; +#endif + BB->BB5 = (phy_mode < PHY_S2) ? 0x8101901 : 0x8301ff1; + BB->BB6 = (phy_mode < PHY_S2) ? 0x31624 : 0x31619; + BB->BB8 = (phy_mode < PHY_S2) ? 0x90083 : 0x90086; + BB->BB9 = 0x1006310; + BB->BB10 = (phy_mode < PHY_S2) ? 0x28be : 0x28de; +#elif defined(CH584_CH585) || defined(CH591_CH592) + BB->BB6 = (BB->BB6 & 0xfffffc00) | ((phy_mode == PHY_2M) ? 0x13a : 0x132); + BB->BB4 = (BB->BB4 & 0x00ffffff) | ((phy_mode == PHY_2M) ? 0x78000000 : 0x7f000000); +#endif + + BB->ACCESSADDRESS1 = access_address; // access address + BB->CRCINIT1 = 0x555555; // crc init +#ifdef CH570_CH572 + BB->ACCESSADDRESS2 = access_address; + BB->CRCINIT2 = 0x555555; + BB->CRCPOLY1 = (BB->CRCPOLY1 & 0xff000000) | 0x80032d; // crc poly + BB->CRCPOLY2 = (BB->CRCPOLY2 & 0xff000000) | 0x80032d; +#endif + + LL->LL0 = 1; // Not sure what this does, but on TX it's 2 + rx_ready = 0; +} diff --git a/inc/extralibs/lib_crc.h b/inc/extralibs/lib_crc.h new file mode 100644 index 0000000..6bfae4d --- /dev/null +++ b/inc/extralibs/lib_crc.h @@ -0,0 +1,36 @@ +// should work for CH32v10x, CH32v20x, and CH32v30x +// Although has only been tested on CH32v303 + +static void CRC_init(void) { + // Enable CRC clock + RCC->AHBPCENR |= RCC_AHBPeriph_CRC; +} + +// Calculate CRC for a single 32-bit value +static u32 CRC_calculate32(u32 data) { + // Reset CRC unit + CRC->CTLR = CRC_CTLR_RESET; + + // Write data to trigger CRC calculation + CRC->DATAR = data; + + // Wait for CRC calculation + u32 timeout = 10000; + while (CRC->DATAR == 0 && --timeout); + + // read the CRC result + return CRC->DATAR; +} + +// Calculate CRC for an array of 32-bit values +static u32 CRC_calculateArray32(u32 *data, u32 length) { + CRC->CTLR = CRC_CTLR_RESET; + + // Process each 32-bit word + for(u32 i = 0; i < length; i++) { + CRC->DATAR = data[i]; + } + + // Return final CRC + return CRC->DATAR; +} diff --git a/inc/extralibs/lib_pvd.h b/inc/extralibs/lib_pvd.h new file mode 100644 index 0000000..3355dad --- /dev/null +++ b/inc/extralibs/lib_pvd.h @@ -0,0 +1,26 @@ +// Tested with CH32V002, CH32V006, and CH32V303 + +#include "ch32fun.h" + +static void PVD_init(u8 threshold) { + if (threshold > PVD_MAX_THRESHOLD_LVL) threshold = PVD_MAX_THRESHOLD_LVL; + + // Enable PWR clock + RCC->APB1PCENR |= RCC_APB1Periph_PWR; + + // Enable PVD + PWR->CTLR |= PWR_CTLR_PVDE; + + // Clear the existing PLS bits and set new threshold + PWR->CTLR = (PWR->CTLR & ~PWR_CTLR_PLS) | (threshold << 5); +} + +// Get threshold setting: the PLS[1:0] bits +static int PVD_getThreshold() { + return (PWR->CTLR & PWR_CTLR_PLS) >> 5; +} + +// return PVD flag: 1 if VDD below threshold +static int PVD_getAlert() { + return PWR->CSR & PWR_CSR_PVDO; +} diff --git a/inc/extralibs/lib_rand.h b/inc/extralibs/lib_rand.h index 98889b4..a6bcf74 100644 --- a/inc/extralibs/lib_rand.h +++ b/inc/extralibs/lib_rand.h @@ -1,30 +1,30 @@ /****************************************************************************** - * Psuedo Random Number Generator using a Linear Feedback Shift Register - * See the GitHub for more information: - * https://github.com/ADBeta/CH32V003_lib_rand - * - * Ver 1.1 09 Sep 2024 - * - * Released under the MIT Licence - * Copyright ADBeta (c) 2024 - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - ******************************************************************************/ +* Psuedo Random Number Generator using a Linear Feedback Shift Register +* See the GitHub for more information: +* https://github.com/ADBeta/CH32V003_lib_rand +* +* Ver 1.1 09 Sep 2024 +* +* Released under the MIT Licence +* Copyright ADBeta (c) 2024 +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to +* deal in the Software without restriction, including without limitation the +* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +* sell copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +* USE OR OTHER DEALINGS IN THE SOFTWARE. +******************************************************************************/ #ifndef CH32V003_LIB_RAND #define CH32V003_LIB_RAND @@ -34,13 +34,14 @@ // Strength 3: Genetate two 32bit values using the LFSR, then XOR them together // Example: #define RANDOM_STRENGTH 2 -#ifndef RANDOM_STRENGTH -#error "Error in lib_rand. Must define RANDOM_STRENGTH" +#ifndef RANDOM_STRENGTH + #error "Error in lib_rand. Must define RANDOM_STRENGTH" #endif // @brief set the random LFSR values seed by default to a known-good value static uint32_t _rand_lfsr = 0x747AA32F; + /*** Library specific Functions - Do Not Use *********************************/ /****************************************************************************/ /// @brief Updates the LFSR by getting a new tap bit, for MSB, then shifting @@ -50,59 +51,63 @@ static uint32_t _rand_lfsr = 0x747AA32F; /// @return 0x01 or 0x00, as a LSB translation of the tapped MSB for the LFSR uint8_t _rand_lfsr_update(void) { - // Shifting to MSB to make calculations more efficient later - uint32_t bit_31 = _rand_lfsr & 0x80000000; - uint32_t bit_21 = (_rand_lfsr << 10) & 0x80000000; - uint32_t bit_01 = (_rand_lfsr << 30) & 0x80000000; - uint32_t bit_00 = (_rand_lfsr << 31) & 0x80000000; + // Shifting to MSB to make calculations more efficient later + uint32_t bit_31 = _rand_lfsr & 0x80000000; + uint32_t bit_21 = (_rand_lfsr << 10) & 0x80000000; + uint32_t bit_01 = (_rand_lfsr << 30) & 0x80000000; + uint32_t bit_00 = (_rand_lfsr << 31) & 0x80000000; - // Calculate the MSB to be put into the LFSR - uint32_t msb = bit_31 ^ bit_21 ^ bit_01 ^ bit_00; - // Shift the lfsr and append the MSB to it - _rand_lfsr = (_rand_lfsr >> 1) | msb; - // Return the LSB instead of MSB - return msb >> 31; + // Calculate the MSB to be put into the LFSR + uint32_t msb = bit_31 ^ bit_21 ^ bit_01 ^ bit_00; + // Shift the lfsr and append the MSB to it + _rand_lfsr = (_rand_lfsr >> 1) | msb; + // Return the LSB instead of MSB + return msb >> 31; } + /// @brief Generates a Random 32-bit number, using the LFSR - by generating /// a random bit from LFSR taps, 32 times. /// @param None /// @return a (psuedo)random 32-bit value uint32_t _rand_gen_32b(void) { - uint32_t rand_out = 0; - - uint8_t bits = 32; - while (bits--) - { - // Shift the current rand value for the new LSB - rand_out = rand_out << 1; - // Append the LSB - rand_out |= _rand_lfsr_update(); - } - - return rand_out; + uint32_t rand_out = 0; + + uint8_t bits = 32; + while(bits--) + { + // Shift the current rand value for the new LSB + rand_out = rand_out << 1; + // Append the LSB + rand_out |= _rand_lfsr_update(); + } + + return rand_out; } + + /// @brief Generates a Random n-bit number, using the LFSR - by generating /// a random bit from LFSR taps, n times. /// @param None /// @return a (psuedo)random n-bit value -uint32_t _rand_gen_nb(int bits) +uint32_t _rand_gen_nb( int bits) { - uint32_t rand_out = 0; + uint32_t rand_out = 0; - while (bits--) - { - // Shift the current rand value for the new LSB - rand_out = rand_out << 1; - // Append the LSB - rand_out |= _rand_lfsr_update(); - } + while(bits--) + { + // Shift the current rand value for the new LSB + rand_out = rand_out << 1; + // Append the LSB + rand_out |= _rand_lfsr_update(); + } - return rand_out; + return rand_out; } + /*** API Functions ***********************************************************/ /*****************************************************************************/ /// @brief seeds the Random LFSR to the value passed @@ -110,39 +115,40 @@ uint32_t _rand_gen_nb(int bits) /// @return None void seed(const uint32_t seed_val) { - _rand_lfsr = seed_val; + _rand_lfsr = seed_val; } + /// @brief Generates a Random (32-bit) Number, based on the RANDOM_STRENGTH -/// you have selected +/// you have selected /// @param None /// @return 32bit Random value uint32_t rand(void) { - uint32_t rand_out = 0; + uint32_t rand_out = 0; -// If RANDOM_STRENGTH is level 1, Update LFSR Once, then return it -#if RANDOM_STRENGTH == 1 - // Update the LFSR, discard result, and return _lsfr raw - (void)_rand_lfsr_update(); - rand_out = _rand_lfsr; -#endif + // If RANDOM_STRENGTH is level 1, Update LFSR Once, then return it + #if RANDOM_STRENGTH == 1 + // Update the LFSR, discard result, and return _lsfr raw + (void)_rand_lfsr_update(); + rand_out = _rand_lfsr; + #endif -// If RANDOM_STRENGTH is level 2, generate a 32-bit output, using 32 random -// bits from the LFSR -#if RANDOM_STRENGTH == 2 - rand_out = _rand_gen_32b(); -#endif + // If RANDOM_STRENGTH is level 2, generate a 32-bit output, using 32 random + // bits from the LFSR + #if RANDOM_STRENGTH == 2 + rand_out = _rand_gen_32b(); + #endif -// If RANDOM_STRENGTH is level 3, generate 2 32-bit outputs, then XOR them -// together -#if RANDOM_STRENGTH == 3 - uint32_t rand_a = _rand_gen_32b(); - uint32_t rand_b = _rand_gen_32b(); - rand_out = rand_a ^ rand_b; -#endif + // If RANDOM_STRENGTH is level 3, generate 2 32-bit outputs, then XOR them + // together + #if RANDOM_STRENGTH == 3 + uint32_t rand_a = _rand_gen_32b(); + uint32_t rand_b = _rand_gen_32b(); + rand_out = rand_a ^ rand_b; + #endif - return rand_out; + return rand_out; } #endif diff --git a/inc/extralibs/register_debug_utilities.h b/inc/extralibs/register_debug_utilities.h new file mode 100644 index 0000000..f16f33c --- /dev/null +++ b/inc/extralibs/register_debug_utilities.h @@ -0,0 +1,142 @@ +#include + +//! #################################### +//! PRINT BITS +//! #################################### + +// eg: UTIL_PRINT_BITS(reg, 32, 16); +void UTIL_PRINT_BITS(u32 val, u8 len, u8 divider_len) { + const char* separator = "\n"; + + for (int i = (len)-1; i >= 0; i--) { + printf("%d| ", i); + if (i > 0) printf(i % divider_len ? "" : "%s", separator); + } + printf("\n"); + + for (int i = (len)-1; i >= 0; i--) { + printf(i < 10 ? "%2d" : "%3d", ((val) >> i) & 1); + if (i > 0) printf(i % divider_len ? " " : " %s", separator); + } +} + +//! #################################### +//! PRINT BITS VALUES +//! #################################### + +// eg: UTIL_PRINT_BITS_VALUES( +// reg, +// "a", 0, +// "b", 1, +// "c", 2, +// ); + +void UTIL_PRINT_BITS_VALUES(u32 reg, ...) { + struct BitPair { const char* name; int pos; }; + va_list args; + va_start(args, reg); + + // Count how many pairs were passed (until NULL name) + int pair_count = 0; + va_list count_args; + va_copy(count_args, args); + + while (1) { + const char* name = va_arg(count_args, const char*); + if (name == NULL) break; + int pos = va_arg(count_args, int); + (void)pos; + pair_count++; + } + va_end(count_args); + + // Read all the pairs + struct BitPair pairs[pair_count]; + for (int i = 0; i < pair_count; i++) { + pairs[i].name = va_arg(args, const char*); + pairs[i].pos = va_arg(args, int); + } + + va_end(args); + + // Print the pairs + for (int i = 0; i < pair_count; i++) { + if (i > 0) printf(", "); + printf("%s=%d", pairs[i].name, (unsigned int)((reg >> pairs[i].pos) & 1)); + } +} + +//! #################################### +//! PRINT BITS RANGE +//! #################################### + +// eg: UTIL_PRINT_BIT_RANGE( +// reg, +// "FIELD3", 5, 3, +// "FIELD2", 2, 1, +// "FIELD1", 0, 0, +// NULL +// ); + +// NOTE: NULL terminated REQUIRED +void UTIL_PRINT_BIT_RANGE(u32 reg, ...) { + // Define the struct + typedef struct { const char* name; int end; int start; } BitField; + + va_list args; + va_start(args, reg); + + // Count how many fields were passed (until NULL name) + int field_count = 0; + va_list count_args; + va_copy(count_args, args); + + while (1) { + const char* name = va_arg(count_args, const char*); + if (name == NULL) break; + int start = va_arg(count_args, int); + (void)start; + int end = va_arg(count_args, int); + (void)end; + field_count++; + } + va_end(count_args); + + // Read all the fields + BitField fields[field_count]; + for (int i = 0; i < field_count; i++) { + fields[i].name = va_arg(args, const char*); + fields[i].end = va_arg(args, int); // get end first + fields[i].start = va_arg(args, int); // then get start + } + + va_end(args); + + // Print the fields + for (int i = 0; i < field_count; i++) { + if (i > 0) printf(", "); + int start = fields[i].start; + int end = fields[i].end; + + if (end == start) { + // Single bit + printf("%s = %d [%d]", fields[i].name, (reg >> start) & 1, start); + } else { + // Multiple bits + int mask = ((1 << (end - start + 1)) - 1); + printf("%s = 0x%02X [%d:%d]", fields[i].name, (reg >> start) & mask, end, start); + } + } + printf("\n"); +} + + +//! #################################### +//! PRINT REGS +//! #################################### + +#define UTIL_PRINT_REG8(reg, label) printf("%s: 0x%02X\n", label, (unsigned int)(reg)); +#define UTIL_PRINT_REG16(reg, label) printf("%s: 0x%04X\n", label, (unsigned int)(reg)); +#define UTIL_PRINT_REG32(reg, label) printf("%s: 0x%08X\n", label, (unsigned int)(reg)); + + diff --git a/inc/extralibs/rtc_helper.h b/inc/extralibs/rtc_helper.h new file mode 100644 index 0000000..f1b31c6 --- /dev/null +++ b/inc/extralibs/rtc_helper.h @@ -0,0 +1,127 @@ +// MIT License +// Copyright (c) 2025 UniTheCat + +#define RTC_TICKS_PER_SECOND 32768 + +#define SECONDS_PER_MINUTE 60 +#define SECONDS_PER_HOUR 3600 +#define SECONDS_PER_DAY 86400 + +#define IS_LEAP_YEAR(year) ((((year) % 4 == 0) && ((year) % 100 != 0)) || ((year) % 400 == 0)) + +// Array of days in each month (non-leap year) +const u8 DAYS_IN_MONTH[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +typedef struct { + u16 year; + u8 month; + u8 day; +} rtc_date_t; + +typedef struct { + u8 hr; + u8 min; + u8 sec; + u16 ms; +} rtc_time_t; + +typedef struct { + rtc_date_t date; + rtc_time_t time; +} rtc_datetime_t; + +// calculate days of the current year. eg. 2020-02-05 is 36 day +u32 RTC_days_of_year(u16 year, u8 month, u8 day) { + u32 day_of_year = 0; + + // Add days from January to month-1 + for (u8 m = 0; m < month - 1; m++) { + day_of_year += DAYS_IN_MONTH[m]; + } + + // Add extra day for February (full month) if it's a leap year + if (month > 2 && IS_LEAP_YEAR(year)) { + day_of_year += 1; + } + + // Add days in the current month + day_of_year += day; + + return day_of_year; +} + +u32 RTC_get_seconds(u16 year, u8 month, u8 day, u8 hr, u8 min, u8 sec) { + //# Validate input + if (month < 1 || month > 12 || day < 1 || day > 31 || + hr > 23 || min > 59 || sec > 59 || year < 1970) { return 0; } + + // calculate days of the current year, -1 for 0-based days + u32 days = RTC_days_of_year(year, month, day) - 1; + + // add the days count excluding the current year + // (start from epoch time 1970-01-01 00:00:00) + for (int y=1970; y < year; y++) { + days += IS_LEAP_YEAR(y) ? 366 : 365; + } + + // calculate total seconds + return days * SECONDS_PER_DAY + + hr * SECONDS_PER_HOUR + + min * SECONDS_PER_MINUTE + sec; +} + +rtc_time_t RTC_get_time(u32 total_seconds, u32 ms) { + u32 minutes = total_seconds / 60; + + return (rtc_time_t) { + .sec = total_seconds % 60, + .min = minutes % 60, + .hr = (minutes / 60) % 24, + .ms = ms + }; +} + +rtc_date_t RTC_get_date(u32 total_seconds, u16 year_base) { + rtc_date_t output = { + .year = year_base, + .month = 1, + .day = 1 + }; + + // Days since epoch + u32 days_remaining = total_seconds / SECONDS_PER_DAY; + + // Find the year + while(1) { + u32 days_in_year = IS_LEAP_YEAR(output.year) ? 366 : 365; + if (days_remaining < days_in_year) break; + days_remaining -= days_in_year; + output.year++; + } + + // find the month + for (u8 m = 0; m < 12; m++) { + u8 days_in_month = DAYS_IN_MONTH[m]; + if (m == 1 && IS_LEAP_YEAR(output.year)) days_in_month = 29; + if (days_remaining < days_in_month) break; + + days_remaining -= days_in_month; + output.month++; + } + + // add 1 because days_remaining is 0-based + output.day = days_remaining + 1; + + return output; +} + +void RTC_print_date(rtc_date_t date, char *delimiter) { + printf("%04d", date.year); + printf("%s%02d", delimiter, date.month); + printf("%s%02d", delimiter, date.day); +} + +void RTC_print_time(rtc_time_t time) { + printf("%02d:%02d:%02d.%03d", + time.hr, time.min, time.sec, time.ms); +} \ No newline at end of file diff --git a/inc/extralibs/ssd1306.h b/inc/extralibs/ssd1306.h index d51811f..97edc67 100644 --- a/inc/extralibs/ssd1306.h +++ b/inc/extralibs/ssd1306.h @@ -6,19 +6,19 @@ #ifndef _SSD1306_H #define _SSD1306_H -#include "font_8x8.h" #include #include +#include "font_8x8.h" // comfortable packet size for this OLED #define SSD1306_PSZ 32 -#if defined(SSD1306_CUSTOM) +#if defined (SSD1306_CUSTOM) // Let the caller configure the OLED. #else // characteristics of each type -#if !defined(SSD1306_64X32) && !defined(SSD1306_128X32) && !defined(SSD1306_128X64) && !defined(SH1107_128x128) && !(defined(SSD1306_W) && defined(SSD1306_H) && defined(SSD1306_OFFSET)) -#error "Please define the SSD1306_WXH resolution used in your application" +#if !defined (SSD1306_64X32) && !defined (SSD1306_72X40) && !defined (SSD1306_128X32) && !defined (SSD1306_128X64) && !defined (SH1107_128x128) && !(defined(SSD1306_W) && defined(SSD1306_H) && defined(SSD1306_OFFSET) ) + #error "Please define the SSD1306_WXH resolution used in your application" #endif #ifdef SSD1306_64X32 @@ -28,6 +28,13 @@ #define SSD1306_OFFSET 32 #endif +#ifdef SSD1306_72X40 +#define SSD1306_W 72 +#define SSD1306_H 40 +#define SSD1306_FULLUSE +#define SSD1306_OFFSET 28 +#endif + #ifdef SSD1306_128X32 #define SSD1306_W 128 #define SSD1306_H 32 @@ -57,7 +64,7 @@ */ uint8_t ssd1306_cmd(uint8_t cmd) { - return ssd1306_pkt_send(&cmd, 1, 1); + return ssd1306_pkt_send(&cmd, 1, 1); } /* @@ -65,7 +72,7 @@ uint8_t ssd1306_cmd(uint8_t cmd) */ uint8_t ssd1306_data(uint8_t *data, int sz) { - return ssd1306_pkt_send(data, sz, 0); + return ssd1306_pkt_send(data, sz, 0); } #define SSD1306_SETCONTRAST 0x81 @@ -87,7 +94,7 @@ uint8_t ssd1306_data(uint8_t *data, int sz) #define SSD1306_SETSTARTLINE 0x40 #define SSD1306_MEMORYMODE 0x20 #define SSD1306_COLUMNADDR 0x21 -#define SSD1306_PAGEADDR 0x22 +#define SSD1306_PAGEADDR 0x22 #define SSD1306_COMSCANINC 0xC0 #define SSD1306_COMSCANDEC 0xC8 #define SSD1306_CHARGEPUMP 0x8D @@ -98,172 +105,130 @@ uint8_t ssd1306_data(uint8_t *data, int sz) /* choose VCC mode */ #define SSD1306_EXTERNALVCC 0x1 #define SSD1306_SWITCHCAPVCC 0x2 -// #define vccstate SSD1306_EXTERNALVCC +//#define vccstate SSD1306_EXTERNALVCC #define vccstate SSD1306_SWITCHCAPVCC #if !defined(SSD1306_CUSTOM_INIT_ARRAY) || !SSD1306_CUSTOM_INIT_ARRAY // OLED initialization commands for 128x32 const uint8_t ssd1306_init_array[] = - { +{ #ifdef SH1107 - SSD1306_DISPLAYOFF, // Turn OLED off - 0x00, // Low column - 0x10, // High column - 0xb0, // Page address - 0xdc, 0x00, // Set Display Start Line (Where in memory it reads from) - SSD1306_SETCONTRAST, 0x6f, // Set constrast - SSD1306_COLUMNADDR, // Set memory addressing mode - SSD1306_DISPLAYALLON_RESUME, // normal (as opposed to invert colors, always on or off.) - SSD1306_SETMULTIPLEX, (SSD1306_H - 1), // Iterate over all 128 rows (Multiplex Ratio) - SSD1306_SETDISPLAYOFFSET, 0x00, // Set display offset // Where this appears on-screen (Some displays will be different) - SSD1306_SETDISPLAYCLOCKDIV, 0xf0, // Set precharge properties. THIS IS A LIE This has todo with timing. <<< This makes it go brrrrrrrrr - SSD1306_SETPRECHARGE, 0x1d, // Set pre-charge period (This controls brightness) - SSD1306_SETVCOMDETECT, 0x35, // Set vcomh - SSD1306_SETSTARTLINE | 0x0, // 0x40 | line - 0xad, 0x80, // Set Charge pump - SSD1306_SEGREMAP, 0x01, // Default mapping - SSD1306_SETPRECHARGE, 0x06, // ???? No idea what this does, but this looks best. - SSD1306_SETCONTRAST, 0xfe, // Set constrast - SSD1306_SETVCOMDETECT, 0xfe, // Set vcomh - SSD1306_SETMULTIPLEX, (SSD1306_H - 1), // 128-wide. - SSD1306_DISPLAYON, // Display on. + SSD1306_DISPLAYOFF, // Turn OLED off + 0x00, // Low column + 0x10, // High column + 0xb0, // Page address + 0xdc, 0x00, // Set Display Start Line (Where in memory it reads from) + SSD1306_SETCONTRAST, 0x6f, // Set constrast + SSD1306_COLUMNADDR, // Set memory addressing mode + SSD1306_DISPLAYALLON_RESUME, // normal (as opposed to invert colors, always on or off.) + SSD1306_SETMULTIPLEX, (SSD1306_H-1), // Iterate over all 128 rows (Multiplex Ratio) + SSD1306_SETDISPLAYOFFSET, 0x00, // Set display offset // Where this appears on-screen (Some displays will be different) + SSD1306_SETDISPLAYCLOCKDIV, 0xf0, // Set precharge properties. THIS IS A LIE This has todo with timing. <<< This makes it go brrrrrrrrr + SSD1306_SETPRECHARGE, 0x1d, // Set pre-charge period (This controls brightness) + SSD1306_SETVCOMDETECT, 0x35, // Set vcomh + SSD1306_SETSTARTLINE | 0x0, // 0x40 | line + 0xad, 0x80, // Set Charge pump + SSD1306_SEGREMAP, 0x01, // Default mapping + SSD1306_SETPRECHARGE, 0x06, // ???? No idea what this does, but this looks best. + SSD1306_SETCONTRAST, 0xfe, // Set constrast + SSD1306_SETVCOMDETECT, 0xfe, // Set vcomh + SSD1306_SETMULTIPLEX, (SSD1306_H-1), // 128-wide. + SSD1306_DISPLAYON, // Display on. #else - SSD1306_DISPLAYOFF, // 0xAE - SSD1306_SETDISPLAYCLOCKDIV, // 0xD5 - 0x80, // the suggested ratio 0x80 - SSD1306_SETMULTIPLEX, // 0xA8 -#ifdef SSD1306_64X32 - 0x1F, // for 64-wide displays + SSD1306_DISPLAYOFF, // 0xAE + SSD1306_SETDISPLAYCLOCKDIV, // 0xD5 + 0x80, // the suggested ratio 0x80 + SSD1306_SETMULTIPLEX, // 0xA8 +#if defined(SSD1306_64X32) + 0x1F, // for 64-wide displays +#elif defined(SSD1306_72X40) + 0x27, #else - 0x3F, // for 128-wide displays + 0x3F, // for 128-wide displays #endif - SSD1306_SETDISPLAYOFFSET, // 0xD3 - 0x00, // no offset - SSD1306_SETSTARTLINE | 0x0, // 0x40 | line - SSD1306_CHARGEPUMP, // 0x8D - 0x14, // enable? - SSD1306_MEMORYMODE, // 0x20 - 0x00, // 0x0 act like ks0108 - SSD1306_SEGREMAP | 0x1, // 0xA0 | bit - SSD1306_COMSCANDEC, - SSD1306_SETCOMPINS, // 0xDA - 0x12, // - SSD1306_SETCONTRAST, // 0x81 - 0x8F, - SSD1306_SETPRECHARGE, // 0xd9 - 0xF1, - SSD1306_SETVCOMDETECT, // 0xDB - 0x40, - SSD1306_DISPLAYALLON_RESUME, // 0xA4 + SSD1306_SETDISPLAYOFFSET, // 0xD3 + 0x00, // no offset + SSD1306_SETSTARTLINE | 0x0, // 0x40 | line + SSD1306_CHARGEPUMP, // 0x8D + 0x14, // enable? + SSD1306_MEMORYMODE, // 0x20 + 0x00, // 0x0 act like ks0108 + SSD1306_SEGREMAP | 0x1, // 0xA0 | bit + SSD1306_COMSCANDEC, + SSD1306_SETCOMPINS, // 0xDA +#if defined(SSD1306_FULLUSE) + 0x12, // +#else + 0x22, // +#endif + SSD1306_SETCONTRAST, // 0x81 +#ifdef SSD1306_72X40 + 0xAF, +#else + 0x8F, +#endif + SSD1306_SETPRECHARGE, // 0xd9 + 0xF1, + SSD1306_SETVCOMDETECT, // 0xDB + 0x40, + SSD1306_DISPLAYALLON_RESUME, // 0xA4 #ifndef SSD1327 - SSD1306_NORMALDISPLAY, // 0xA6 + SSD1306_NORMALDISPLAY, // 0xA6 #endif - SSD1306_DISPLAYON, // 0xAF --turn on oled panel + SSD1306_DISPLAYON, // 0xAF --turn on oled panel #endif - SSD1306_TERMINATE_CMDS // 0xFF --fake command to mark end + SSD1306_TERMINATE_CMDS // 0xFF --fake command to mark end }; #endif // the display buffer -uint8_t ssd1306_buffer[SSD1306_W * SSD1306_H / 8]; +uint8_t ssd1306_buffer[SSD1306_W*SSD1306_H/8]; /* * set the buffer to a color */ void ssd1306_setbuf(uint8_t color) { - memset(ssd1306_buffer, color ? 0xFF : 0x00, sizeof(ssd1306_buffer)); + memset(ssd1306_buffer, color ? 0xFF : 0x00, sizeof(ssd1306_buffer)); } -#ifndef SSD1306_FULLUSE -/* - * expansion array for OLED with every other row unused - */ -const uint8_t expand[16] = - { - 0x00, - 0x02, - 0x08, - 0x0a, - 0x20, - 0x22, - 0x28, - 0x2a, - 0x80, - 0x82, - 0x88, - 0x8a, - 0xa0, - 0xa2, - 0xa8, - 0xaa, -}; -#endif - /* * Send the frame buffer */ void ssd1306_refresh(void) { - uint16_t i; - + uint16_t i; + #ifdef SH1107 - ssd1306_cmd(SSD1306_MEMORYMODE); // vertical addressing mode. + ssd1306_cmd(SSD1306_MEMORYMODE); // vertical addressing mode. - for (i = 0; i < SSD1306_H / 8; i++) - { - ssd1306_cmd(0xb0 | i); - ssd1306_cmd(0x00 | (0 & 0xf)); - ssd1306_cmd(0x10 | (0 >> 4)); - ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 0 * SSD1306_PSZ], SSD1306_PSZ); - ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 1 * SSD1306_PSZ], SSD1306_PSZ); - ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 2 * SSD1306_PSZ], SSD1306_PSZ); - ssd1306_data(&ssd1306_buffer[i * 4 * SSD1306_PSZ + 3 * SSD1306_PSZ], SSD1306_PSZ); - } + for(i=0;i>4) ); + ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+0*SSD1306_PSZ], SSD1306_PSZ); + ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+1*SSD1306_PSZ], SSD1306_PSZ); + ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+2*SSD1306_PSZ], SSD1306_PSZ); + ssd1306_data(&ssd1306_buffer[i*4*SSD1306_PSZ+3*SSD1306_PSZ], SSD1306_PSZ); + } #else - ssd1306_cmd(SSD1306_COLUMNADDR); - ssd1306_cmd(SSD1306_OFFSET); // Column start address (0 = reset) - ssd1306_cmd(SSD1306_OFFSET + SSD1306_W - 1); // Column end address (127 = reset) + ssd1306_cmd(SSD1306_COLUMNADDR); + ssd1306_cmd(SSD1306_OFFSET); // Column start address (0 = reset) + ssd1306_cmd(SSD1306_OFFSET+SSD1306_W-1); // Column end address (127 = reset) + + ssd1306_cmd(SSD1306_PAGEADDR); + ssd1306_cmd(0); // Page start address (0 = reset) + ssd1306_cmd(7); // Page end address - ssd1306_cmd(SSD1306_PAGEADDR); - ssd1306_cmd(0); // Page start address (0 = reset) - ssd1306_cmd(7); // Page end address - -#ifdef SSD1306_FULLUSE - /* for fully used rows just plow thru everything */ - for (i = 0; i < sizeof(ssd1306_buffer); i += SSD1306_PSZ) - { - /* send PSZ block of data */ - ssd1306_data(&ssd1306_buffer[i], SSD1306_PSZ); - } -#else - /* for displays with odd rows unused expand bytes */ - uint8_t tbuf[SSD1306_PSZ], j, k; - for (i = 0; i < sizeof(ssd1306_buffer); i += 128) - { - /* low nybble */ - for (j = 0; j < 128; j += SSD1306_PSZ) - { - for (k = 0; k < SSD1306_PSZ; k++) - tbuf[k] = expand[ssd1306_buffer[i + j + k] & 0xf]; - - /* send PSZ block of data */ - ssd1306_data(tbuf, SSD1306_PSZ); - } - - /* high nybble */ - for (j = 0; j < 128; j += SSD1306_PSZ) - { - for (k = 0; k < SSD1306_PSZ; k++) - tbuf[k] = expand[(ssd1306_buffer[i + j + k] >> 4) & 0xf]; - - /* send PSZ block of data */ - ssd1306_data(tbuf, SSD1306_PSZ); - } - } -#endif + for(i=0;i= SSD1306_W) - return; - if (y >= SSD1306_H) - return; - - /* compute buffer address */ - addr = x + SSD1306_W * (y / 8); - - /* set/clear bit in buffer */ - if (color) - ssd1306_buffer[addr] |= (1 << (y & 7)); - else - ssd1306_buffer[addr] &= ~(1 << (y & 7)); + uint32_t addr; + + /* clip */ + if(x >= SSD1306_W) + return; + if(y >= SSD1306_H) + return; + + /* compute buffer address */ + addr = x + SSD1306_W*(y/8); + + /* set/clear bit in buffer */ + if(color) + ssd1306_buffer[addr] |= (1<<(y&7)); + else + ssd1306_buffer[addr] &= ~(1<<(y&7)); } /* @@ -294,96 +259,89 @@ void ssd1306_drawPixel(uint32_t x, uint32_t y, int color) */ void ssd1306_xorPixel(uint32_t x, uint32_t y) { - uint32_t addr; - - /* clip */ - if (x >= SSD1306_W) - return; - if (y >= SSD1306_H) - return; - - /* compute buffer address */ - addr = x + SSD1306_W * (y / 8); - - ssd1306_buffer[addr] ^= (1 << (y & 7)); + uint32_t addr; + + /* clip */ + if(x >= SSD1306_W) + return; + if(y >= SSD1306_H) + return; + + /* compute buffer address */ + addr = x + SSD1306_W*(y/8); + + ssd1306_buffer[addr] ^= (1<<(y&7)); } /* * draw a an image from an array, directly into to the display buffer * the color modes allow for overwriting and even layering (sprites!) */ -void ssd1306_drawImage(uint32_t x, uint32_t y, const unsigned char *input, uint32_t width, uint32_t height, uint32_t color_mode) -{ - uint32_t x_absolute; - uint32_t y_absolute; - uint32_t pixel; - uint32_t bytes_to_draw = width / 8; - uint32_t buffer_addr; +void ssd1306_drawImage(uint32_t x, uint32_t y, const unsigned char* input, uint32_t width, uint32_t height, uint32_t color_mode) { + uint32_t x_absolute; + uint32_t y_absolute; + uint32_t pixel; + uint32_t bytes_to_draw = width / 8; + uint32_t buffer_addr; - for (uint32_t line = 0; line < height; line++) - { - y_absolute = y + line; - if (y_absolute >= SSD1306_H) - { - break; - } + for (uint32_t line = 0; line < height; line++) { + y_absolute = y + line; + if (y_absolute >= SSD1306_H) { + break; + } - // SSD1306 is in vertical mode, yet we want to draw horizontally, which necessitates assembling the output bytes from the input data - // bitmask for current pixel in vertical (output) byte - uint32_t v_mask = 1 << (y_absolute & 7); + // SSD1306 is in vertical mode, yet we want to draw horizontally, which necessitates assembling the output bytes from the input data + // bitmask for current pixel in vertical (output) byte + uint32_t v_mask = 1 << (y_absolute & 7); - for (uint32_t byte = 0; byte < bytes_to_draw; byte++) - { - uint32_t input_byte = input[byte + line * bytes_to_draw]; + for (uint32_t byte = 0; byte < bytes_to_draw; byte++) { + uint32_t input_byte = input[byte + line * bytes_to_draw]; - for (pixel = 0; pixel < 8; pixel++) - { - x_absolute = x + 8 * (bytes_to_draw - byte) + pixel; - if (x_absolute >= SSD1306_W) - { - break; - } - // looking at the horizontal display, we're drawing bytes bottom to top, not left to right, hence y / 8 - buffer_addr = x_absolute + SSD1306_W * (y_absolute / 8); - // state of current pixel - uint8_t input_pixel = input_byte & (1 << pixel); + for (pixel = 0; pixel < 8; pixel++) { + x_absolute = x + 8 * (bytes_to_draw - byte) + pixel; + if (x_absolute >= SSD1306_W) { + break; + } + // looking at the horizontal display, we're drawing bytes bottom to top, not left to right, hence y / 8 + buffer_addr = x_absolute + SSD1306_W * (y_absolute / 8); + // state of current pixel + uint8_t input_pixel = input_byte & (1 << pixel); - switch (color_mode) - { - case 0: - // write pixels as they are - ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (input_pixel ? v_mask : 0); - break; - case 1: - // write pixels after inversion - ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (!input_pixel ? v_mask : 0); - break; - case 2: - // 0 clears pixel - ssd1306_buffer[buffer_addr] &= input_pixel ? 0xFF : ~v_mask; - break; - case 3: - // 1 sets pixel - ssd1306_buffer[buffer_addr] |= input_pixel ? v_mask : 0; - break; - case 4: - // 0 sets pixel - ssd1306_buffer[buffer_addr] |= !input_pixel ? v_mask : 0; - break; - case 5: - // 1 clears pixel - ssd1306_buffer[buffer_addr] &= input_pixel ? ~v_mask : 0xFF; - break; - } - } -#if SSD1306_LOG_IMAGE == 1 - printf("%02x ", input_byte); -#endif - } -#if SSD1306_LOG_IMAGE == 1 - printf("\n\r"); -#endif - } + switch (color_mode) { + case 0: + // write pixels as they are + ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (input_pixel ? v_mask : 0); + break; + case 1: + // write pixels after inversion + ssd1306_buffer[buffer_addr] = (ssd1306_buffer[buffer_addr] & ~v_mask) | (!input_pixel ? v_mask : 0); + break; + case 2: + // 0 clears pixel + ssd1306_buffer[buffer_addr] &= input_pixel ? 0xFF : ~v_mask; + break; + case 3: + // 1 sets pixel + ssd1306_buffer[buffer_addr] |= input_pixel ? v_mask : 0; + break; + case 4: + // 0 sets pixel + ssd1306_buffer[buffer_addr] |= !input_pixel ? v_mask : 0; + break; + case 5: + // 1 clears pixel + ssd1306_buffer[buffer_addr] &= input_pixel ? ~v_mask : 0xFF; + break; + } + } + #if SSD1306_LOG_IMAGE == 1 + printf("%02x ", input_byte); + #endif + } + #if SSD1306_LOG_IMAGE == 1 + printf("\n\r"); + #endif + } } /* @@ -391,13 +349,13 @@ void ssd1306_drawImage(uint32_t x, uint32_t y, const unsigned char *input, uint3 */ void ssd1306_drawFastVLine(int32_t x, int32_t y, int32_t h, uint32_t color) { - // clipping - if ((x >= SSD1306_W) || (y >= SSD1306_H)) return; - if ((y + h - 1) >= SSD1306_H) h = SSD1306_H - y; - while (h--) - { + // clipping + if((x >= SSD1306_W) || (y >= SSD1306_H)) return; + if((y+h-1) >= SSD1306_H) h = SSD1306_H-y; + while(h--) + { ssd1306_drawPixel(x, y++, color); - } + } } /* @@ -405,14 +363,14 @@ void ssd1306_drawFastVLine(int32_t x, int32_t y, int32_t h, uint32_t color) */ void ssd1306_drawFastHLine(uint32_t x, uint32_t y, uint32_t w, uint32_t color) { - // clipping - if ((x >= SSD1306_W) || (y >= SSD1306_H)) return; - if ((x + w - 1) >= SSD1306_W) w = SSD1306_W - x; + // clipping + if((x >= SSD1306_W) || (y >= SSD1306_H)) return; + if((x+w-1) >= SSD1306_W) w = SSD1306_W-x; - while (w--) - { + while (w--) + { ssd1306_drawPixel(x++, y, color); - } + } } /* @@ -420,7 +378,7 @@ void ssd1306_drawFastHLine(uint32_t x, uint32_t y, uint32_t w, uint32_t color) */ int gfx_abs(int x) { - return (x < 0) ? -x : x; + return (x<0) ? -x : x; } /* @@ -428,9 +386,9 @@ int gfx_abs(int x) */ void gfx_swap(int *z0, int *z1) { - uint16_t temp = *z0; - *z0 = *z1; - *z1 = temp; + uint16_t temp = *z0; + *z0 = *z1; + *z1 = temp; } /* @@ -438,56 +396,56 @@ void gfx_swap(int *z0, int *z1) */ void ssd1306_drawLine(int x0, int y0, int x1, int y1, uint32_t color) { - int32_t steep; - int32_t deltax, deltay, error, ystep, x, y; + int32_t steep; + int32_t deltax, deltay, error, ystep, x, y; - /* flip sense 45deg to keep error calc in range */ - steep = (gfx_abs(y1 - y0) > gfx_abs(x1 - x0)); + /* flip sense 45deg to keep error calc in range */ + steep = (gfx_abs(y1 - y0) > gfx_abs(x1 - x0)); - if (steep) - { - gfx_swap(&x0, &y0); - gfx_swap(&x1, &y1); - } + if(steep) + { + gfx_swap(&x0, &y0); + gfx_swap(&x1, &y1); + } - /* run low->high */ - if (x0 > x1) - { - gfx_swap(&x0, &x1); - gfx_swap(&y0, &y1); - } + /* run low->high */ + if(x0 > x1) + { + gfx_swap(&x0, &x1); + gfx_swap(&y0, &y1); + } - /* set up loop initial conditions */ - deltax = x1 - x0; - deltay = gfx_abs(y1 - y0); - error = deltax / 2; - y = y0; - if (y0 < y1) - ystep = 1; - else - ystep = -1; + /* set up loop initial conditions */ + deltax = x1 - x0; + deltay = gfx_abs(y1 - y0); + error = deltax/2; + y = y0; + if(y0 < y1) + ystep = 1; + else + ystep = -1; - /* loop x */ - for (x = x0; x <= x1; x++) - { - /* plot point */ - if (steep) - /* flip point & plot */ - ssd1306_drawPixel(y, x, color); - else - /* just plot */ - ssd1306_drawPixel(x, y, color); + /* loop x */ + for(x=x0;x<=x1;x++) + { + /* plot point */ + if(steep) + /* flip point & plot */ + ssd1306_drawPixel(y, x, color); + else + /* just plot */ + ssd1306_drawPixel(x, y, color); - /* update error */ - error = error - deltay; + /* update error */ + error = error - deltay; - /* update y */ - if (error < 0) - { - y = y + ystep; - error = error + deltax; - } - } + /* update y */ + if(error < 0) + { + y = y + ystep; + error = error + deltax; + } + } } /* @@ -498,26 +456,22 @@ void ssd1306_drawCircle(int x, int y, int radius, int color) /* Bresenham algorithm */ int x_pos = -radius; int y_pos = 0; - int err = 2 - 2 * radius; + int err = 2 - 2 * radius; int e2; - do - { + do { ssd1306_drawPixel(x - x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y - y_pos, color); ssd1306_drawPixel(x - x_pos, y - y_pos, color); e2 = err; - if (e2 <= y_pos) - { + if (e2 <= y_pos) { err += ++y_pos * 2 + 1; - if (-x_pos == y_pos && e2 <= x_pos) - { - e2 = 0; + if(-x_pos == y_pos && e2 <= x_pos) { + e2 = 0; } } - if (e2 > x_pos) - { + if (e2 > x_pos) { err += ++x_pos * 2 + 1; } } while (x_pos <= 0); @@ -531,11 +485,10 @@ void ssd1306_fillCircle(int x, int y, int radius, int color) /* Bresenham algorithm */ int x_pos = -radius; int y_pos = 0; - int err = 2 - 2 * radius; + int err = 2 - 2 * radius; int e2; - do - { + do { ssd1306_drawPixel(x - x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y + y_pos, color); ssd1306_drawPixel(x + x_pos, y - y_pos, color); @@ -543,19 +496,16 @@ void ssd1306_fillCircle(int x, int y, int radius, int color) ssd1306_drawFastHLine(x + x_pos, y + y_pos, 2 * (-x_pos) + 1, color); ssd1306_drawFastHLine(x + x_pos, y - y_pos, 2 * (-x_pos) + 1, color); e2 = err; - if (e2 <= y_pos) - { + if (e2 <= y_pos) { err += ++y_pos * 2 + 1; - if (-x_pos == y_pos && e2 <= x_pos) - { + if(-x_pos == y_pos && e2 <= x_pos) { e2 = 0; } } - if (e2 > x_pos) - { + if(e2 > x_pos) { err += ++x_pos * 2 + 1; } - } while (x_pos <= 0); + } while(x_pos <= 0); } /* @@ -563,10 +513,10 @@ void ssd1306_fillCircle(int x, int y, int radius, int color) */ void ssd1306_drawRect(int32_t x, int32_t y, uint32_t w, uint32_t h, uint32_t color) { - ssd1306_drawFastVLine(x, y, h, color); - ssd1306_drawFastVLine(x + w - 1, y, h, color); - ssd1306_drawFastHLine(x, y, w, color); - ssd1306_drawFastHLine(x, y + h - 1, w, color); + ssd1306_drawFastVLine(x, y, h, color); + ssd1306_drawFastVLine(x+w-1, y, h, color); + ssd1306_drawFastHLine(x, y, w, color); + ssd1306_drawFastHLine(x, y+h-1, w, color); } /* @@ -574,21 +524,21 @@ void ssd1306_drawRect(int32_t x, int32_t y, uint32_t w, uint32_t h, uint32_t col */ void ssd1306_fillRect(uint32_t x, uint32_t y, uint8_t w, uint32_t h, uint32_t color) { - uint32_t m, n = y, iw = w; - - /* scan vertical */ - while (h--) - { - m = x; - w = iw; - /* scan horizontal */ - while (w--) - { - /* invert pixels */ - ssd1306_drawPixel(m++, n, color); - } - n++; - } + uint32_t m, n=y, iw = w; + + /* scan vertical */ + while(h--) + { + m=x; + w=iw; + /* scan horizontal */ + while(w--) + { + /* invert pixels */ + ssd1306_drawPixel(m++, n, color); + } + n++; + } } /* @@ -596,21 +546,21 @@ void ssd1306_fillRect(uint32_t x, uint32_t y, uint8_t w, uint32_t h, uint32_t co */ void ssd1306_xorrect(uint8_t x, uint8_t y, uint8_t w, uint8_t h) { - uint8_t m, n = y, iw = w; - - /* scan vertical */ - while (h--) - { - m = x; - w = iw; - /* scan horizontal */ - while (w--) - { - /* invert pixels */ - ssd1306_xorPixel(m++, n); - } - n++; - } + uint8_t m, n=y, iw = w; + + /* scan vertical */ + while(h--) + { + m=x; + w=iw; + /* scan horizontal */ + while(w--) + { + /* invert pixels */ + ssd1306_xorPixel(m++, n); + } + n++; + } } /* @@ -618,25 +568,25 @@ void ssd1306_xorrect(uint8_t x, uint8_t y, uint8_t w, uint8_t h) */ void ssd1306_drawchar(uint8_t x, uint8_t y, uint8_t chr, uint8_t color) { - uint16_t i, j, col; - uint8_t d; - - for (i = 0; i < 8; i++) - { - d = fontdata[(chr << 3) + i]; - for (j = 0; j < 8; j++) - { - if (d & 0x80) - col = color; - else - col = (~color) & 1; - - ssd1306_drawPixel(x + j, y + i, col); - - // next bit - d <<= 1; - } - } + uint16_t i, j, col; + uint8_t d; + + for(i=0;i<8;i++) + { + d = fontdata[(chr<<3)+i]; + for(j=0;j<8;j++) + { + if(d&0x80) + col = color; + else + col = (~color)&1; + + ssd1306_drawPixel(x+j, y+i, col); + + // next bit + d <<= 1; + } + } } /* @@ -644,26 +594,25 @@ void ssd1306_drawchar(uint8_t x, uint8_t y, uint8_t chr, uint8_t color) */ void ssd1306_drawstr(uint8_t x, uint8_t y, char *str, uint8_t color) { - uint8_t c; - - while ((c = *str++)) - { - ssd1306_drawchar(x, y, c, color); - x += 8; - if (x > 120) - break; - } + uint8_t c; + + while((c=*str++)) + { + ssd1306_drawchar(x, y, c, color); + x += 8; + if(x>120) + break; + } } /* * enum for font size */ -typedef enum -{ - fontsize_8x8 = 1, +typedef enum { + fontsize_8x8 = 1, fontsize_16x16 = 2, fontsize_32x32 = 4, - fontsize_64x64 = 8, + fontsize_64x64 = 8, } font_size_t; /* @@ -672,7 +621,7 @@ typedef enum void ssd1306_drawchar_sz(uint8_t x, uint8_t y, uint8_t chr, uint8_t color, font_size_t font_size) { uint16_t i, j, col; - uint8_t d; + uint8_t d; // Determine the font scale factor based on the font_size parameter uint8_t font_scale = (uint8_t)font_size; @@ -693,10 +642,8 @@ void ssd1306_drawchar_sz(uint8_t x, uint8_t y, uint8_t chr, uint8_t color, font_ col = (~color) & 1; // Draw the pixel at the original size and scaled size using nested for-loops - for (uint8_t k = 0; k < font_scale; k++) - { - for (uint8_t l = 0; l < font_scale; l++) - { + for (uint8_t k = 0; k < font_scale; k++) { + for (uint8_t l = 0; l < font_scale; l++) { ssd1306_drawPixel(x + (j * font_scale) + k, y + (i * font_scale) + l, col); } } @@ -712,15 +659,15 @@ void ssd1306_drawchar_sz(uint8_t x, uint8_t y, uint8_t chr, uint8_t color, font_ */ void ssd1306_drawstr_sz(uint8_t x, uint8_t y, char *str, uint8_t color, font_size_t font_size) { - uint8_t c; - - while ((c = *str++)) - { - ssd1306_drawchar_sz(x, y, c, color, font_size); - x += 8 * font_size; - if (x > 128 - 8 * font_size) - break; - } + uint8_t c; + + while((c=*str++)) + { + ssd1306_drawchar_sz(x, y, c, color, font_size); + x += 8 * font_size; + if(x>128 - 8 * font_size) + break; + } } /* @@ -728,25 +675,24 @@ void ssd1306_drawstr_sz(uint8_t x, uint8_t y, char *str, uint8_t color, font_siz */ uint8_t ssd1306_init(void) { - // pulse reset - ssd1306_rst(); + // pulse reset + ssd1306_rst(); - ssd1306_setbuf(0); - - // initialize OLED + ssd1306_setbuf(0); + + // initialize OLED #if !defined(SSD1306_CUSTOM_INIT_ARRAY) || !SSD1306_CUSTOM_INIT_ARRAY - uint8_t *cmd_list = (uint8_t *)ssd1306_init_array; - while (*cmd_list != SSD1306_TERMINATE_CMDS) - { - if (ssd1306_cmd(*cmd_list++)) - return 1; - } - - // clear display - ssd1306_refresh(); + uint8_t *cmd_list = (uint8_t *)ssd1306_init_array; + while(*cmd_list != SSD1306_TERMINATE_CMDS) + { + if(ssd1306_cmd(*cmd_list++)) + return 1; + } + + ssd1306_refresh(); #endif - return 0; + return 0; } #endif diff --git a/inc/extralibs/ssd1306_i2c.h b/inc/extralibs/ssd1306_i2c.h index 465985e..41b265d 100644 --- a/inc/extralibs/ssd1306_i2c.h +++ b/inc/extralibs/ssd1306_i2c.h @@ -27,14 +27,14 @@ #define TIMEOUT_MAX 100000 // uncomment this to enable IRQ-driven operation -// #define SSD1306_I2C_IRQ +//#define SSD1306_I2C_IRQ #ifdef SSD1306_I2C_IRQ // some stuff that IRQ mode needs volatile uint8_t ssd1306_i2c_send_buffer[64], *ssd1306_i2c_send_ptr, ssd1306_i2c_send_sz, ssd1306_i2c_irq_state; // uncomment this to enable time diags in IRQ -// #define IRQ_DIAG +//#define IRQ_DIAG #endif /* @@ -42,62 +42,62 @@ volatile uint8_t ssd1306_i2c_send_buffer[64], *ssd1306_i2c_send_ptr, ssd1306_i2c */ void ssd1306_i2c_setup(void) { - uint16_t tempreg; - - // Reset I2C1 to init all regs - RCC->APB1PRSTR |= RCC_APB1Periph_I2C1; - RCC->APB1PRSTR &= ~RCC_APB1Periph_I2C1; - - // set freq - tempreg = I2C1->CTLR2; - tempreg &= ~I2C_CTLR2_FREQ; - tempreg |= (FUNCONF_SYSTEM_CORE_CLOCK / SSD1306_I2C_PRERATE) & I2C_CTLR2_FREQ; - I2C1->CTLR2 = tempreg; - - // Set clock config - tempreg = 0; + uint16_t tempreg; + + // Reset I2C1 to init all regs + RCC->APB1PRSTR |= RCC_APB1Periph_I2C1; + RCC->APB1PRSTR &= ~RCC_APB1Periph_I2C1; + + // set freq + tempreg = I2C1->CTLR2; + tempreg &= ~I2C_CTLR2_FREQ; + tempreg |= (FUNCONF_SYSTEM_CORE_CLOCK/SSD1306_I2C_PRERATE)&I2C_CTLR2_FREQ; + I2C1->CTLR2 = tempreg; + + // Set clock config + tempreg = 0; #if (SSD1306_I2C_CLKRATE <= 100000) - // standard mode good to 100kHz - tempreg = (FUNCONF_SYSTEM_CORE_CLOCK / (2 * SSD1306_I2C_CLKRATE)) & I2C_CKCFGR_CCR; + // standard mode good to 100kHz + tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(2*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR; #else - // fast mode over 100kHz + // fast mode over 100kHz #ifndef SSD1306_I2C_DUTY - // 33% duty cycle - tempreg = (FUNCONF_SYSTEM_CORE_CLOCK / (3 * SSD1306_I2C_CLKRATE)) & I2C_CKCFGR_CCR; + // 33% duty cycle + tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(3*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR; #else - // 36% duty cycle - tempreg = (FUNCONF_SYSTEM_CORE_CLOCK / (25 * SSD1306_I2C_CLKRATE)) & I2C_CKCFGR_CCR; - tempreg |= I2C_CKCFGR_DUTY; + // 36% duty cycle + tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(25*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR; + tempreg |= I2C_CKCFGR_DUTY; #endif - tempreg |= I2C_CKCFGR_FS; + tempreg |= I2C_CKCFGR_FS; #endif - I2C1->CKCFGR = tempreg; + I2C1->CKCFGR = tempreg; #ifdef SSD1306_I2C_IRQ - // enable IRQ driven operation - NVIC_EnableIRQ(I2C1_EV_IRQn); - - // initialize the state - ssd1306_i2c_irq_state = 0; + // enable IRQ driven operation + NVIC_EnableIRQ(I2C1_EV_IRQn); + + // initialize the state + ssd1306_i2c_irq_state = 0; #endif + + // Enable I2C + I2C1->CTLR1 |= I2C_CTLR1_PE; - // Enable I2C - I2C1->CTLR1 |= I2C_CTLR1_PE; - - // set ACK mode - I2C1->CTLR1 |= I2C_CTLR1_ACK; + // set ACK mode + I2C1->CTLR1 |= I2C_CTLR1_ACK; } /* * error descriptions */ char *errstr[] = - { - "not busy", - "master mode", - "transmit mode", - "tx empty", - "transmit complete", +{ + "not busy", + "master mode", + "transmit mode", + "tx empty", + "transmit complete", }; /* @@ -105,28 +105,28 @@ char *errstr[] = */ uint8_t ssd1306_i2c_error(uint8_t err) { - // report error - printf("ssd1306_i2c_error - timeout waiting for %s\n\r", errstr[err]); + // report error + printf("ssd1306_i2c_error - timeout waiting for %s\n\r", errstr[err]); + + // reset & initialize I2C + ssd1306_i2c_setup(); - // reset & initialize I2C - ssd1306_i2c_setup(); - - return 1; + return 1; } // event codes we use -#define SSD1306_I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ -#define SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ +#define SSD1306_I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /* * check for 32-bit event codes */ uint8_t ssd1306_i2c_chk_evt(uint32_t event_mask) { - /* read order matters here! STAR1 before STAR2!! */ - uint32_t status = I2C1->STAR1 | (I2C1->STAR2 << 16); - return (status & event_mask) == event_mask; + /* read order matters here! STAR1 before STAR2!! */ + uint32_t status = I2C1->STAR1 | (I2C1->STAR2<<16); + return (status & event_mask) == event_mask; } #ifdef SSD1306_I2C_IRQ @@ -135,67 +135,63 @@ uint8_t ssd1306_i2c_chk_evt(uint32_t event_mask) */ uint8_t ssd1306_i2c_send(uint8_t addr, uint8_t *data, uint8_t sz) { - int32_t timeout; + int32_t timeout; + +#ifdef IRQ_DIAG + GPIOC->BSHR = (1<<(3)); +#endif + + // error out if buffer under/overflow + if((sz > sizeof(ssd1306_i2c_send_buffer)) || !sz) + return 2; + + // wait for previous packet to finish + while(ssd1306_i2c_irq_state); + +#ifdef IRQ_DIAG + GPIOC->BSHR = (1<<(16+3)); + GPIOC->BSHR = (1<<(4)); +#endif + + // init buffer for sending + ssd1306_i2c_send_sz = sz; + ssd1306_i2c_send_ptr = ssd1306_i2c_send_buffer; + memcpy((uint8_t *)ssd1306_i2c_send_buffer, data, sz); + + // wait for not busy + timeout = TIMEOUT_MAX; + while((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(0); + + // Set START condition + I2C1->CTLR1 |= I2C_CTLR1_START; + + // wait for master mode select + timeout = TIMEOUT_MAX; + while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(1); + + // send 7-bit address + write flag + I2C1->DATAR = addr<<1; + + // wait for transmit condition + timeout = TIMEOUT_MAX; + while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(2); + + // Enable TXE interrupt + I2C1->CTLR2 |= I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN; + ssd1306_i2c_irq_state = 1; #ifdef IRQ_DIAG - GPIOC->BSHR = (1 << (3)); + GPIOC->BSHR = (1<<(16+4)); #endif - - // error out if buffer under/overflow - if ((sz > sizeof(ssd1306_i2c_send_buffer)) || !sz) - return 2; - - // wait for previous packet to finish - while (ssd1306_i2c_irq_state) - ; - -#ifdef IRQ_DIAG - GPIOC->BSHR = (1 << (16 + 3)); - GPIOC->BSHR = (1 << (4)); -#endif - - // init buffer for sending - ssd1306_i2c_send_sz = sz; - ssd1306_i2c_send_ptr = ssd1306_i2c_send_buffer; - memcpy((uint8_t *)ssd1306_i2c_send_buffer, data, sz); - - // wait for not busy - timeout = TIMEOUT_MAX; - while ((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(0); - - // Set START condition - I2C1->CTLR1 |= I2C_CTLR1_START; - - // wait for master mode select - timeout = TIMEOUT_MAX; - while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(1); - - // send 7-bit address + write flag - I2C1->DATAR = addr << 1; - - // wait for transmit condition - timeout = TIMEOUT_MAX; - while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(2); - - // Enable TXE interrupt - I2C1->CTLR2 |= I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN; - ssd1306_i2c_irq_state = 1; - -#ifdef IRQ_DIAG - GPIOC->BSHR = (1 << (16 + 4)); -#endif - - // exit - return 0; + + // exit + return 0; } /* @@ -204,43 +200,42 @@ uint8_t ssd1306_i2c_send(uint8_t addr, uint8_t *data, uint8_t sz) void I2C1_EV_IRQHandler(void) __attribute__((interrupt)); void I2C1_EV_IRQHandler(void) { - uint16_t STAR1, STAR2 __attribute__((unused)); - + uint16_t STAR1, STAR2 __attribute__((unused)); + #ifdef IRQ_DIAG - GPIOC->BSHR = (1 << (4)); + GPIOC->BSHR = (1<<(4)); #endif - // read status, clear any events - STAR1 = I2C1->STAR1; - STAR2 = I2C1->STAR2; + // read status, clear any events + STAR1 = I2C1->STAR1; + STAR2 = I2C1->STAR2; + + /* check for TXE */ + if(STAR1 & I2C_STAR1_TXE) + { + /* check for remaining data */ + if(ssd1306_i2c_send_sz--) + I2C1->DATAR = *ssd1306_i2c_send_ptr++; - /* check for TXE */ - if (STAR1 & I2C_STAR1_TXE) - { - /* check for remaining data */ - if (ssd1306_i2c_send_sz--) - I2C1->DATAR = *ssd1306_i2c_send_ptr++; + /* was that the last byte? */ + if(!ssd1306_i2c_send_sz) + { + // disable TXE interrupt + I2C1->CTLR2 &= ~(I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN); + + // reset IRQ state + ssd1306_i2c_irq_state = 0; + + // wait for tx complete + while(!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)); - /* was that the last byte? */ - if (!ssd1306_i2c_send_sz) - { - // disable TXE interrupt - I2C1->CTLR2 &= ~(I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN); - - // reset IRQ state - ssd1306_i2c_irq_state = 0; - - // wait for tx complete - while (!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - ; - - // set STOP condition - I2C1->CTLR1 |= I2C_CTLR1_STOP; - } - } + // set STOP condition + I2C1->CTLR1 |= I2C_CTLR1_STOP; + } + } #ifdef IRQ_DIAG - GPIOC->BSHR = (1 << (16 + 4)); + GPIOC->BSHR = (1<<(16+4)); #endif } #else @@ -249,61 +244,56 @@ void I2C1_EV_IRQHandler(void) */ uint8_t ssd1306_i2c_send(uint8_t addr, const uint8_t *data, int sz) { - int32_t timeout; + int32_t timeout; + + // wait for not busy + timeout = TIMEOUT_MAX; + while((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(0); - // wait for not busy - timeout = TIMEOUT_MAX; - while ((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(0); + // Set START condition + I2C1->CTLR1 |= I2C_CTLR1_START; + + // wait for master mode select + timeout = TIMEOUT_MAX; + while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(1); + + // send 7-bit address + write flag + I2C1->DATAR = addr<<1; - // Set START condition - I2C1->CTLR1 |= I2C_CTLR1_START; + // wait for transmit condition + timeout = TIMEOUT_MAX; + while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(2); - // wait for master mode select - timeout = TIMEOUT_MAX; - while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(1); + // send data one byte at a time + while(sz--) + { + // wait for TX Empty + timeout = TIMEOUT_MAX; + while(!(I2C1->STAR1 & I2C_STAR1_TXE) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(3); + + // send command + I2C1->DATAR = *data++; + } - // send 7-bit address + write flag - I2C1->DATAR = addr << 1; + // wait for tx complete + timeout = TIMEOUT_MAX; + while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) && (timeout--)); + if(timeout==-1) + return ssd1306_i2c_error(4); - // wait for transmit condition - timeout = TIMEOUT_MAX; - while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(2); - - // send data one byte at a time - while (sz--) - { - // wait for TX Empty - timeout = TIMEOUT_MAX; - while (!(I2C1->STAR1 & I2C_STAR1_TXE) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(3); - - // send command - I2C1->DATAR = *data++; - } - - // wait for tx complete - timeout = TIMEOUT_MAX; - while ((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) && (timeout--)) - ; - if (timeout == -1) - return ssd1306_i2c_error(4); - - // set STOP condition - I2C1->CTLR1 |= I2C_CTLR1_STOP; - - // we're happy - return 0; + // set STOP condition + I2C1->CTLR1 |= I2C_CTLR1_STOP; + + // we're happy + return 0; } #endif @@ -312,20 +302,20 @@ uint8_t ssd1306_i2c_send(uint8_t addr, const uint8_t *data, int sz) */ uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) { - uint8_t pkt[33]; - - /* build command or data packets */ - if (cmd) - { - pkt[0] = 0; - pkt[1] = *data; - } - else - { - pkt[0] = 0x40; - memcpy(&pkt[1], data, sz); - } - return ssd1306_i2c_send(SSD1306_I2C_ADDR, pkt, sz + 1); + uint8_t pkt[33]; + + /* build command or data packets */ + if(cmd) + { + pkt[0] = 0; + pkt[1] = *data; + } + else + { + pkt[0] = 0x40; + memcpy(&pkt[1], data, sz); + } + return ssd1306_i2c_send(SSD1306_I2C_ADDR, pkt, sz+1); } /* @@ -333,51 +323,51 @@ uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) */ uint8_t ssd1306_i2c_init(void) { - // Enable GPIOC and I2C - RCC->APB1PCENR |= RCC_APB1Periph_I2C1; + // Enable GPIOC and I2C + RCC->APB1PCENR |= RCC_APB1Periph_I2C1; #ifdef CH32V20x - RCC->APB2PCENR |= RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO; + RCC->APB2PCENR |= RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO; #ifdef SSD1306_REMAP_I2C - AFIO->PCFR1 |= AFIO_PCFR1_I2C1_REMAP; - funPinMode(PB8, GPIO_CFGLR_OUT_10Mhz_AF_OD); - funPinMode(PB9, GPIO_CFGLR_OUT_10Mhz_AF_OD); + AFIO->PCFR1 |= AFIO_PCFR1_I2C1_REMAP; + funPinMode( PB8, GPIO_CFGLR_OUT_10Mhz_AF_OD ); + funPinMode( PB9, GPIO_CFGLR_OUT_10Mhz_AF_OD ); #else - funPinMode(PB6, GPIO_CFGLR_OUT_10Mhz_AF_OD); - funPinMode(PB7, GPIO_CFGLR_OUT_10Mhz_AF_OD); + funPinMode( PB6, GPIO_CFGLR_OUT_10Mhz_AF_OD ); + funPinMode( PB7, GPIO_CFGLR_OUT_10Mhz_AF_OD ); #endif #else - RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO; - // PC1 is SDA, 10MHz Output, alt func, open-drain - GPIOC->CFGLR &= ~(0xf << (4 * 1)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF) << (4 * 1); - - // PC2 is SCL, 10MHz Output, alt func, open-drain - GPIOC->CFGLR &= ~(0xf << (4 * 2)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF) << (4 * 2); + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO; + // PC1 is SDA, 10MHz Output, alt func, open-drain + GPIOC->CFGLR &= ~(0xf<<(4*1)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*1); + + // PC2 is SCL, 10MHz Output, alt func, open-drain + GPIOC->CFGLR &= ~(0xf<<(4*2)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*2); #endif #ifdef IRQ_DIAG - // GPIO diags on PC3/PC4 - GPIOC->CFGLR &= ~(0xf << (4 * 3)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 3); - GPIOC->BSHR = (1 << (16 + 3)); - GPIOC->CFGLR &= ~(0xf << (4 * 4)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4); - GPIOC->BSHR = (1 << (16 + 4)); + // GPIO diags on PC3/PC4 + GPIOC->CFGLR &= ~(0xf<<(4*3)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*3); + GPIOC->BSHR = (1<<(16+3)); + GPIOC->CFGLR &= ~(0xf<<(4*4)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*4); + GPIOC->BSHR = (1<<(16+4)); #endif - // load I2C regs - ssd1306_i2c_setup(); - + // load I2C regs + ssd1306_i2c_setup(); + #if 0 // test if SSD1306 is on the bus by sending display off command uint8_t command = 0xAF; return ssd1306_pkt_send(&command, 1, 1); #else - return 0; + return 0; #endif } diff --git a/inc/extralibs/ssd1306_i2c_bitbang.h b/inc/extralibs/ssd1306_i2c_bitbang.h index 92c3acf..31daa51 100644 --- a/inc/extralibs/ssd1306_i2c_bitbang.h +++ b/inc/extralibs/ssd1306_i2c_bitbang.h @@ -26,115 +26,120 @@ */ void ssd1306_i2c_setup(void) { - funGpioInitAll(); - funPinMode(SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP); - funDigitalWrite(SSD1306_I2C_BITBANG_SDA, 1); - funPinMode(SSD1306_I2C_BITBANG_SCL, GPIO_CFGLR_OUT_10Mhz_PP); - funDigitalWrite(SSD1306_I2C_BITBANG_SCL, 1); + funGpioInitAll(); + funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP ); + funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 1 ); + funPinMode( SSD1306_I2C_BITBANG_SCL, GPIO_CFGLR_OUT_10Mhz_PP ); + funDigitalWrite( SSD1306_I2C_BITBANG_SCL, 1 ); } -#define SDA_HIGH funDigitalWrite(SSD1306_I2C_BITBANG_SDA, 1); -#define SCL_HIGH funDigitalWrite(SSD1306_I2C_BITBANG_SCL, 1); -#define SDA_LOW funDigitalWrite(SSD1306_I2C_BITBANG_SDA, 0); -#define SCL_LOW funDigitalWrite(SSD1306_I2C_BITBANG_SCL, 0); -#define SDA_IN funDigitalRead(SSD1306_I2C_BITBANG_SDA); +#define SDA_HIGH funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 1 ); +#define SCL_HIGH funDigitalWrite( SSD1306_I2C_BITBANG_SCL, 1 ); +#define SDA_LOW funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 0 ); +#define SCL_LOW funDigitalWrite( SSD1306_I2C_BITBANG_SCL, 0 ); +#define SDA_RELEASE { funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_IN_PUPD ); funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 1 ); } +#define SDA_IN funDigitalRead( SSD1306_I2C_BITBANG_SDA ); +#define SDA_DRIVE { funDigitalWrite( SSD1306_I2C_BITBANG_SDA, 1 ); funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP ); } + +#ifndef I2CSPEEDBASE #define I2CSPEEDBASE 1 -#define I2CDELAY_FUNC(x) ADD_N_NOPS(x * 1) -// Delay_Us(x*1); +#endif +#ifndef I2CDELAY_FUNC +#define I2CDELAY_FUNC(x) ADD_N_NOPS(x*1) +#endif static void ssd1306_i2c_sendstart() { - SCL_HIGH - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SDA_LOW - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SCL_LOW - I2CDELAY_FUNC(1 * I2CSPEEDBASE); + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_HIGH + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SDA_LOW + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_LOW + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); } void ssd1306_i2c_sendstop() { - SDA_LOW - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SCL_LOW - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SCL_HIGH - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SDA_HIGH - I2CDELAY_FUNC(1 * I2CSPEEDBASE); + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SDA_LOW + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_LOW + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_HIGH + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SDA_HIGH + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); } -// Return nonzero on failure. -unsigned char ssd1306_i2c_sendbyte(unsigned char data) +//Return nonzero on failure. +unsigned char ssd1306_i2c_sendbyte( unsigned char data ) { - unsigned int i; - for (i = 0; i < 8; i++) - { - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - if (data & 0x80) - { - SDA_HIGH; - } - else - { - SDA_LOW; - } - data <<= 1; - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SCL_HIGH - I2CDELAY_FUNC(2 * I2CSPEEDBASE); - SCL_LOW - } + unsigned int i; + for( i = 0; i < 8; i++ ) + { + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + if( data & 0x80 ) + { SDA_HIGH; } + else + { SDA_LOW; } + data<<=1; + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_HIGH + I2CDELAY_FUNC( 2 * I2CSPEEDBASE ); + SCL_LOW + } - // Immediately after sending last bit, open up DDDR for control. - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - funPinMode(SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_IN_PUPD); - SDA_HIGH - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SCL_HIGH - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - i = SDA_IN; - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SCL_LOW - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - SDA_HIGH // Maybe? - funPinMode(SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP); - I2CDELAY_FUNC(1 * I2CSPEEDBASE); - return !!i; + //Immediately after sending last bit, open up DDDR for control. + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SDA_HIGH + SDA_RELEASE + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_HIGH + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + i = SDA_IN; + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SCL_LOW + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + SDA_DRIVE + SDA_HIGH + funPinMode( SSD1306_I2C_BITBANG_SDA, GPIO_CFGLR_OUT_10Mhz_PP ); + I2CDELAY_FUNC( 1 * I2CSPEEDBASE ); + return !!i; } uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) { - ssd1306_i2c_sendstart(); - int r = ssd1306_i2c_sendbyte(SSD1306_I2C_ADDR << 1); - if (r) return r; - // ssd1306_i2c_sendstart(); For some reason displays don't want repeated start - if (cmd) - { - if (ssd1306_i2c_sendbyte(0x00)) - return 1; // Control - } - else - { - if (ssd1306_i2c_sendbyte(0x40)) - return 1; // Data - } - for (int i = 0; i < sz; i++) - { - if (ssd1306_i2c_sendbyte(data[i])) - return 1; - } - ssd1306_i2c_sendstop(); - return 0; + ssd1306_i2c_sendstart(); + int r = ssd1306_i2c_sendbyte( SSD1306_I2C_ADDR<<1 ); + if( r ) return r; + //ssd1306_i2c_sendstart(); For some reason displays don't want repeated start + if(cmd) + { + if( ssd1306_i2c_sendbyte( 0x00 ) ) + return 1; // Control + } + else + { + if( ssd1306_i2c_sendbyte( 0x40 ) ) + return 1; // Data + } + for( int i = 0; i < sz; i++ ) + { + if( ssd1306_i2c_sendbyte( data[i] ) ) + return 1; + } + ssd1306_i2c_sendstop(); + return 0; } void ssd1306_rst(void) { - funPinMode(SSD1306_RST_PIN, GPIO_CFGLR_OUT_10Mhz_PP); - funDigitalWrite(SSD1306_RST_PIN, 0); - Delay_Ms(10); - funDigitalWrite(SSD1306_RST_PIN, 1); - Delay_Us(10); + funPinMode( SSD1306_RST_PIN, GPIO_CFGLR_OUT_10Mhz_PP ); + funDigitalWrite( SSD1306_RST_PIN, 0 ); + Delay_Ms(10); + funDigitalWrite( SSD1306_RST_PIN, 1 ); + Delay_Us(10); } #endif diff --git a/inc/extralibs/ssd1306_spi.h b/inc/extralibs/ssd1306_spi.h index 7112fe8..60c6ed0 100644 --- a/inc/extralibs/ssd1306_spi.h +++ b/inc/extralibs/ssd1306_spi.h @@ -24,43 +24,66 @@ #endif #ifndef SSD1306_SCK_PIN -#define SSD1306_SCK_PIN PC5 +#define SSD1306_SCK_PIN PC5 #endif #ifndef SSD1306_BAUD_RATE_PRESCALER #define SSD1306_BAUD_RATE_PRESCALER SPI_BaudRatePrescaler_2 #endif +#ifndef SSD1306_SOFT_SPI +#define SSD1306_SOFT_SPI 0 +#endif + /* * init SPI and GPIO for SSD1306 OLED */ uint8_t ssd1306_spi_init(void) { - // Enable GPIOC and SPI - RCC->APB2PCENR |= RCC_APB2Periph_SPI1; + // Enable GPIOC and SPI +#ifdef CH5xx +#else + RCC->APB2PCENR |= RCC_APB2Periph_SPI1; +#endif + + funGpioInitAll(); + funPinMode( SSD1306_RST_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); + funPinMode( SSD1306_CS_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); + funPinMode( SSD1306_DC_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); +#if defined( CH5xx ) || SSD1306_SOFT_SPI + funPinMode( SSD1306_MOSI_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); + funPinMode( SSD1306_SCK_PIN, GPIO_CFGLR_OUT_50Mhz_PP ); +#else + funPinMode( SSD1306_MOSI_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP ); + funPinMode( SSD1306_SCK_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP ); +#endif - funGpioInitAll(); - funPinMode(SSD1306_RST_PIN, GPIO_CFGLR_OUT_50Mhz_PP); - funPinMode(SSD1306_CS_PIN, GPIO_CFGLR_OUT_50Mhz_PP); - funPinMode(SSD1306_DC_PIN, GPIO_CFGLR_OUT_50Mhz_PP); - funPinMode(SSD1306_MOSI_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP); - funPinMode(SSD1306_SCK_PIN, GPIO_CFGLR_OUT_50Mhz_AF_PP); + funDigitalWrite( SSD1306_RST_PIN, FUN_HIGH ); + funDigitalWrite( SSD1306_CS_PIN, FUN_HIGH ); + funDigitalWrite( SSD1306_DC_PIN, FUN_LOW ); - funDigitalWrite(SSD1306_RST_PIN, FUN_HIGH); - funDigitalWrite(SSD1306_CS_PIN, FUN_HIGH); - funDigitalWrite(SSD1306_DC_PIN, FUN_LOW); + // Configure SPI +#if SSD1306_SOFT_SPI + funDigitalWrite( SSD1306_SCK_PIN, FUN_HIGH ); +#elif defined( CH5xx ) + R8_SPI0_CLOCK_DIV = FUNCONF_SYSTEM_CORE_CLOCK / 12000000; // 16MHz is the fastest I want to go - though it does seem to work up to ~60MHz. + R8_SPI0_CTRL_MOD = RB_SPI_ALL_CLEAR; + R8_SPI0_CTRL_MOD = RB_SPI_MOSI_OE | RB_SPI_2WIRE_MOD | RB_SPI_SCK_OE; + R8_SPI0_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + // | RB_SPI_MST_SCK_MOD; // Mode 3 / mode 0 + R8_SPI0_CTRL_CFG = RB_MST_CLK_SEL; +#else + SPI1->CTLR1 = + SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_8b | + SPI_Mode_Master | SPI_Direction_1Line_Tx | + SSD1306_BAUD_RATE_PRESCALER; - // Configure SPI - SPI1->CTLR1 = - SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_8b | - SPI_Mode_Master | SPI_Direction_1Line_Tx | - SSD1306_BAUD_RATE_PRESCALER; - - // enable SPI port - SPI1->CTLR1 |= CTLR1_SPE_Set; - - // always succeed - return 0; + // enable SPI port + SPI1->CTLR1 |= CTLR1_SPE_Set; +#endif + + // always succeed + return 0; } /* @@ -68,9 +91,9 @@ uint8_t ssd1306_spi_init(void) */ void ssd1306_rst(void) { - funDigitalWrite(SSD1306_RST_PIN, FUN_LOW); - Delay_Ms(10); - funDigitalWrite(SSD1306_RST_PIN, FUN_HIGH); + funDigitalWrite( SSD1306_RST_PIN, FUN_LOW ); + Delay_Ms(10); + funDigitalWrite( SSD1306_RST_PIN, FUN_HIGH ); } /* @@ -78,35 +101,56 @@ void ssd1306_rst(void) */ uint8_t ssd1306_pkt_send(const uint8_t *data, int sz, uint8_t cmd) { - if (cmd) - { - funDigitalWrite(SSD1306_DC_PIN, FUN_LOW); - } - else - { - funDigitalWrite(SSD1306_DC_PIN, FUN_HIGH); - } + if(cmd) + { + funDigitalWrite( SSD1306_DC_PIN, FUN_LOW ); + } + else + { + funDigitalWrite( SSD1306_DC_PIN, FUN_HIGH ); + } - funDigitalWrite(SSD1306_CS_PIN, FUN_LOW); + funDigitalWrite( SSD1306_CS_PIN, FUN_LOW ); + + // send data + while(sz--) + { +#if SSD1306_SOFT_SPI + uint8_t c = *data++; + int i = 8; + do + { + funDigitalWrite( SSD1306_SCK_PIN, FUN_LOW ); ADD_N_NOPS(1) + funDigitalWrite( SSD1306_MOSI_PIN, !!(c & 0x80) ); ADD_N_NOPS(1) + funDigitalWrite( SSD1306_SCK_PIN, FUN_HIGH ); ADD_N_NOPS(1) + c<<=1; + } while( --i ); - // send data - while (sz--) - { - // wait for TXE - while (!(SPI1->STATR & SPI_STATR_TXE)) - ; +#elif defined( CH5xx ) + while(! (R8_SPI0_INT_FLAG & RB_SPI_FREE) ); + R8_SPI0_BUFFER = *data++; +#else + // wait for TXE + while(!(SPI1->STATR & SPI_STATR_TXE)); + + // Send byte + SPI1->DATAR = *data++; +#endif + } + + // wait for not busy before exiting +#if SSD1306_SOFT_SPI + // Nothing needed here. +#elif defined( CH5xx ) + while( !(R8_SPI0_INT_FLAG & RB_SPI_FREE)) { } +#else + while(SPI1->STATR & SPI_STATR_BSY) { } +#endif - // Send byte - SPI1->DATAR = *data++; - } - - // wait for not busy before exiting - while (SPI1->STATR & SPI_STATR_BSY) {} - - funDigitalWrite(SSD1306_CS_PIN, FUN_HIGH); - - // we're happy - return 0; + funDigitalWrite( SSD1306_CS_PIN, FUN_HIGH ); + + // we're happy + return 0; } #endif diff --git a/inc/extralibs/static_i2c.h b/inc/extralibs/static_i2c.h new file mode 100644 index 0000000..7dc4b7e --- /dev/null +++ b/inc/extralibs/static_i2c.h @@ -0,0 +1,203 @@ +/* + Copyright 2012-2025 <>< Charles Lohr + This file may be used for any purposes (commercial or private) just please + leave this copyright notice in there somewhere. You may cross license + this as MIT or NewBSD. + + Now, generic I2C library for any GPIO-based system. + + Include this in your .c file only!!! + Include it after the following are defined: + + I2CDELAY_FUNC -> If you wish to override the internal delay functions. + I2CSPEEDBASE -> define speed base multiplier 1 = normal, 10 = slow, .1 = + fast; failure to define this will result in the clock being as fast as + possible. I2CNEEDGETBYTE -> Do we need to be able to read data? + + I2CPREFIX -> #define to be the prefix, i.e. BOB will cause BOBConfigI2C + to be generated. + I2CNOSTATIC -> #define if you want the functions to be generated as + not-static code. + + NOTE: You must initially configure the port to be outputs on both DSDA + and DSCL and set them both to be driven high. +*/ +/* Example: + + #define DELAY1 Delay_Us(1); + #define DELAY2 Delay_Us(2); + #define DSCL_IHIGH { funPinMode( PIN_SCL, GPIO_CFGLR_IN_PUPD ); funDigitalWrite( PIN_SCL, 1 ); } + #define DSDA_IHIGH { funPinMode( PIN_SDA, GPIO_CFGLR_IN_PUPD ); funDigitalWrite( PIN_SDA, 1 ); } + #define DSDA_INPUT { funPinMode( PIN_SDA, GPIO_CFGLR_IN_PUPD ); funDigitalWrite( PIN_SDA, 1 ); } + #define DSCL_OUTPUT { funDigitalWrite( PIN_SCL, 0 ); funPinMode( PIN_SCL, GPIO_CFGLR_OUT_2Mhz_PP ); } + #define DSDA_OUTPUT { funDigitalWrite( PIN_SDA, 0 ); funPinMode( PIN_SDA, GPIO_CFGLR_OUT_2Mhz_PP ); } + #define READ_DSDA funDigitalRead( PIN_SDA ) + #define I2CNEEDGETBYTE 1 + #define I2CNEEDSCAN 1 + + #include "static_i2c.h" + + ... +*/ + + + +#ifndef I2CPREFIX + #define I2CPREFIX +#endif + +#ifndef I2CNOSTATIC + #define I2CSTATICODE +#else + #define I2CSTATICODE static +#endif + +#ifndef I2CFNCOLLAPSE + #define INTI2CFNCOLLAPSE(PFX, name) PFX##name + #define I2CFNCOLLAPSE(PFX, name) INTI2CFNCOLLAPSE(PFX, name) +#endif + +#ifndef I2CNEEDGETBYTE + #define I2CNEEDGETBYTE 1 +#endif + +#ifndef DSCL_IHIGH + #define DSCL_IHIGH DSCL_INPUT +#endif + +#ifndef DSDA_IHIGH + #define DSDA_IHIGH DSDA_INPUT +#endif + +I2CSTATICODE void I2CFNCOLLAPSE(I2CPREFIX, ConfigI2C)() +{ + DSDA_IHIGH + DSCL_IHIGH +} + +I2CSTATICODE void I2CFNCOLLAPSE(I2CPREFIX, SendStart)() +{ + DELAY1 + DSCL_IHIGH + DELAY1 + DSDA_OUTPUT + DELAY1 + DSCL_OUTPUT + DELAY1 +} + +I2CSTATICODE void I2CFNCOLLAPSE(I2CPREFIX, SendStop)() +{ + DELAY1 + DSDA_OUTPUT + DELAY1 + DSCL_IHIGH + DELAY1 + DSDA_IHIGH + DELAY1 +} + +// Return nonzero on failure. +I2CSTATICODE unsigned char I2CFNCOLLAPSE(I2CPREFIX, SendByte)(unsigned char data) +{ + unsigned int i; + // Assume we are in a started state (DSCL = 0 & DSDA = 0) + + for (i = 0; i < 8; i++) + { + DELAY1 + if (data & 0x80) + { + DSDA_IHIGH + } + else + { + DSDA_OUTPUT + } + data <<= 1; + DELAY2 + DSCL_IHIGH + DELAY2 + DSCL_OUTPUT + } + + // Immediately after sending last bit, open up DDDR for control. + DELAY1 + DSDA_INPUT + DELAY1 + DSCL_IHIGH + DELAY1 + i = READ_DSDA; + DELAY1 + DSCL_OUTPUT + DELAY1 + return !!i; +} + +#if I2CNEEDGETBYTE + +I2CSTATICODE unsigned char I2CFNCOLLAPSE(I2CPREFIX, GetByte)(uint8_t send_nak) +{ + unsigned char i; + unsigned char ret = 0; + + DSDA_INPUT + + for (i = 0; i < 8; i++) + { + DELAY1 + DSCL_IHIGH + DELAY2 + ret <<= 1; + if (READ_DSDA) + ret |= 1; + DSCL_OUTPUT + } + + // Send ack. + if (send_nak) + { + } + else + { + DSDA_OUTPUT + } + + DELAY1 + DSCL_IHIGH + DELAY2 + DSCL_OUTPUT + DELAY1 + DSDA_IHIGH + + return ret; +} + +#endif + +// In case you want SCAN code + +#if I2CNEEDSCAN + +I2CSTATICODE void I2CFNCOLLAPSE(I2CPREFIX, Scan)() +{ + int i; + printf( " " ); + for( i = 0; i < 16; i++ ) + { + printf( " %x", i ); + } + for( i = 0; i < 128; i++ ) + { + if( ( i & 0xf ) == 0 ) + { + printf( "\n%02x ", i ); + } + SendStart(); + int b = SendByte( i<<1 ); + SendStop(); + printf( "%c ", b?'.':'#' ); + } + printf( "\n" ); +} +#endif diff --git a/inc/extralibs/usb_defines.h b/inc/extralibs/usb_defines.h index e588982..1e4b9a2 100644 --- a/inc/extralibs/usb_defines.h +++ b/inc/extralibs/usb_defines.h @@ -37,721 +37,714 @@ #include #include + /*------------------------------------------------------------------*/ /* From Linux *------------------------------------------------------------------*/ -#define USB_DIR_OUT 0 /* to device */ -#define USB_DIR_IN 0x80 /* to host */ -#define USB_TYPE_MASK (0x03 << 5) -#define USB_TYPE_STANDARD (0x00 << 5) -#define USB_TYPE_CLASS (0x01 << 5) -#define USB_TYPE_VENDOR (0x02 << 5) -#define USB_TYPE_RESERVED (0x03 << 5) +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ + +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + /* * USB recipients, the third of three bRequestType fields */ -#define USB_RECIP_MASK 0x1f -#define USB_RECIP_DEVICE 0x00 -#define USB_RECIP_INTERFACE 0x01 -#define USB_RECIP_ENDPOINT 0x02 -#define USB_RECIP_OTHER 0x03 +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 /* From Wireless USB 1.0 */ -#define USB_RECIP_PORT 0x04 -#define USB_RECIP_RPIPE 0x05 +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05 #define TU_ATTR_PACKED __attribute__((packed)) #ifndef TU_BIT -#define TU_BIT(n) (1U << (n)) +#define TU_BIT(n) (1U << (n)) #endif #ifndef TU_STRCAT -#define TU_STRCAT(a, b) a##b ///< concat without expand -#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat +#define TU_STRCAT(a, b) a##b ///< concat without expand +#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat #endif #ifndef _TU_COUNTER_ #if defined __COUNTER__ && __COUNTER__ != __COUNTER__ -#define _TU_COUNTER_ __COUNTER__ + #define _TU_COUNTER_ __COUNTER__ #else -#define _TU_COUNTER_ __LINE__ + #define _TU_COUNTER_ __LINE__ #endif #endif // Compile-time Assert -#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L -#define TU_VERIFY_STATIC _Static_assert -#elif defined(__cplusplus) && __cplusplus >= 201103L -#define TU_VERIFY_STATIC static_assert +#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define TU_VERIFY_STATIC _Static_assert +#elif defined (__cplusplus) && __cplusplus >= 201103L + #define TU_VERIFY_STATIC static_assert #else -#define TU_VERIFY_STATIC(const_expr, _mess) \ - enum \ - { \ - TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1 / (!!(const_expr)) \ - } + #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) } #endif #ifdef __cplusplus -extern "C" + extern "C" { +#endif + +/*------------------------------------------------------------------*/ +/* CONSTANTS + *------------------------------------------------------------------*/ + +/// defined base on EHCI specs value for Endpoint Speed +typedef enum { -#endif - - /*------------------------------------------------------------------*/ - /* CONSTANTS - *------------------------------------------------------------------*/ - - /// defined base on EHCI specs value for Endpoint Speed - typedef enum - { - TUSB_SPEED_FULL = 0, - TUSB_SPEED_LOW, - TUSB_SPEED_HIGH, - TUSB_SPEED_INVALID = 0xff, - } tusb_speed_t; - - /// defined base on USB Specs Endpoint's bmAttributes - typedef enum - { - TUSB_XFER_CONTROL = 0, - TUSB_XFER_ISOCHRONOUS, - TUSB_XFER_BULK, - TUSB_XFER_INTERRUPT - } tusb_xfer_type_t; - - typedef enum - { - TUSB_DIR_OUT = 0, - TUSB_DIR_IN = 1, - - TUSB_DIR_IN_MASK = 0x80 - } tusb_dir_t; - - /// USB Descriptor Types - typedef enum - { - TUSB_DESC_DEVICE = 0x01, - TUSB_DESC_CONFIGURATION = 0x02, - TUSB_DESC_STRING = 0x03, - TUSB_DESC_INTERFACE = 0x04, - TUSB_DESC_ENDPOINT = 0x05, - TUSB_DESC_DEVICE_QUALIFIER = 0x06, - TUSB_DESC_OTHER_SPEED_CONFIG = 0x07, - TUSB_DESC_INTERFACE_POWER = 0x08, - TUSB_DESC_OTG = 0x09, - TUSB_DESC_DEBUG = 0x0A, - TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B, - - TUSB_DESC_BOS = 0x0F, - TUSB_DESC_DEVICE_CAPABILITY = 0x10, - - TUSB_DESC_FUNCTIONAL = 0x21, - - // Class Specific Descriptor - TUSB_DESC_CS_DEVICE = 0x21, - TUSB_DESC_CS_CONFIGURATION = 0x22, - TUSB_DESC_CS_STRING = 0x23, - TUSB_DESC_CS_INTERFACE = 0x24, - TUSB_DESC_CS_ENDPOINT = 0x25, - - TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, - TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 - } tusb_desc_type_t; - - typedef enum - { - TUSB_REQ_GET_STATUS = 0, - TUSB_REQ_CLEAR_FEATURE = 1, - TUSB_REQ_RESERVED = 2, - TUSB_REQ_SET_FEATURE = 3, - TUSB_REQ_RESERVED2 = 4, - TUSB_REQ_SET_ADDRESS = 5, - TUSB_REQ_GET_DESCRIPTOR = 6, - TUSB_REQ_SET_DESCRIPTOR = 7, - TUSB_REQ_GET_CONFIGURATION = 8, - TUSB_REQ_SET_CONFIGURATION = 9, - TUSB_REQ_GET_INTERFACE = 10, - TUSB_REQ_SET_INTERFACE = 11, - TUSB_REQ_SYNCH_FRAME = 12 - } tusb_request_code_t; - - typedef enum - { - TUSB_REQ_FEATURE_EDPT_HALT = 0, - TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, - TUSB_REQ_FEATURE_TEST_MODE = 2 - } tusb_request_feature_selector_t; - - typedef enum - { - TUSB_REQ_TYPE_STANDARD = 0, - TUSB_REQ_TYPE_CLASS, - TUSB_REQ_TYPE_VENDOR, - TUSB_REQ_TYPE_INVALID - } tusb_request_type_t; - - typedef enum - { - TUSB_REQ_RCPT_DEVICE = 0, - TUSB_REQ_RCPT_INTERFACE, - TUSB_REQ_RCPT_ENDPOINT, - TUSB_REQ_RCPT_OTHER - } tusb_request_recipient_t; - - // https://www.usb.org/defined-class-codes - typedef enum - { - TUSB_CLASS_UNSPECIFIED = 0, - TUSB_CLASS_AUDIO = 1, - TUSB_CLASS_CDC = 2, - TUSB_CLASS_HID = 3, - TUSB_CLASS_RESERVED_4 = 4, - TUSB_CLASS_PHYSICAL = 5, - TUSB_CLASS_IMAGE = 6, - TUSB_CLASS_PRINTER = 7, - TUSB_CLASS_MSC = 8, - TUSB_CLASS_HUB = 9, - TUSB_CLASS_CDC_DATA = 10, - TUSB_CLASS_SMART_CARD = 11, - TUSB_CLASS_RESERVED_12 = 12, - TUSB_CLASS_CONTENT_SECURITY = 13, - TUSB_CLASS_VIDEO = 14, - TUSB_CLASS_PERSONAL_HEALTHCARE = 15, - TUSB_CLASS_AUDIO_VIDEO = 16, - - TUSB_CLASS_DIAGNOSTIC = 0xDC, - TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0, - TUSB_CLASS_MISC = 0xEF, - TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE, - TUSB_CLASS_VENDOR_SPECIFIC = 0xFF - } tusb_class_code_t; - - typedef enum - { - MISC_SUBCLASS_COMMON = 2 - } misc_subclass_type_t; - - typedef enum - { - MISC_PROTOCOL_IAD = 1 - } misc_protocol_type_t; - - typedef enum - { - APP_SUBCLASS_USBTMC = 0x03, - APP_SUBCLASS_DFU_RUNTIME = 0x01 - } app_subclass_type_t; - - typedef enum - { - DEVICE_CAPABILITY_WIRELESS_USB = 0x01, - DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, - DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, - DEVICE_CAPABILITY_CONTAINER_id = 0x04, - DEVICE_CAPABILITY_PLATFORM = 0x05, - DEVICE_CAPABILITY_POWER_DELIVERY = 0x06, - DEVICE_CAPABILITY_BATTERY_INFO = 0x07, - DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08, - DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09, - DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A, - DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B, - DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C, - DEVICE_CAPABILITY_BILLBOARD = 0x0D, - DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, - DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, - DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 - } device_capability_type_t; - - enum - { - TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), - TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6), - }; - -#define TUSB_DESC_CONFIG_POWER_MA(x) ((x) / 2) - - /// Device State TODO remove - typedef enum - { - TUSB_DEVICE_STATE_UNPLUG = 0, - TUSB_DEVICE_STATE_CONFIGURED, - TUSB_DEVICE_STATE_SUSPENDED, - } tusb_device_state_t; - - typedef enum - { - XFER_RESULT_SUCCESS, - XFER_RESULT_FAILED, - XFER_RESULT_STALLED, - } xfer_result_t; - - enum // TODO remove - { - DESC_OFFSET_LEN = 0, - DESC_OFFSET_TYPE = 1 - }; - - enum - { - INTERFACE_INVALID_NUMBER = 0xff - }; - - typedef enum - { - MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, - MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, - MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, - MS_OS_20_FEATURE_COMPATBLE_ID = 0x03, - MS_OS_20_FEATURE_REG_PROPERTY = 0x04, - MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05, - MS_OS_20_FEATURE_MODEL_ID = 0x06, - MS_OS_20_FEATURE_CCGP_DEVICE = 0x07, - MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 - } microsoft_os_20_type_t; - - enum - { - CONTROL_STAGE_SETUP, - CONTROL_STAGE_DATA, - CONTROL_STAGE_ACK - }; - - //--------------------------------------------------------------------+ - // USB Descriptors - //--------------------------------------------------------------------+ - - /// USB Device Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< DEVICE Descriptor Type. - uint16_t bcdUSB; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. - - uint8_t bDeviceClass; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific. - uint8_t bDeviceSubClass; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. - uint8_t bDeviceProtocol; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis. - uint8_t bMaxPacketSize0; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. - - uint16_t idVendor; ///< Vendor ID (assigned by the USB-IF). - uint16_t idProduct; ///< Product ID (assigned by the manufacturer). - uint16_t bcdDevice; ///< Device release number in binary-coded decimal. - uint8_t iManufacturer; ///< Index of string descriptor describing manufacturer. - uint8_t iProduct; ///< Index of string descriptor describing product. - uint8_t iSerialNumber; ///< Index of string descriptor describing the device's serial number. - - uint8_t bNumConfigurations; ///< Number of possible configurations. - } tusb_desc_device_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_device_t) == 18, "size is not correct"); - - // USB Binary Device Object Store (BOS) Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< CONFIGURATION Descriptor Type - uint16_t wTotalLength; ///< Total length of data returned for this descriptor - uint8_t bNumDeviceCaps; ///< Number of device capability descriptors in the BOS - } tusb_desc_bos_t; - - /// USB Configuration Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< CONFIGURATION Descriptor Type - uint16_t wTotalLength; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. - - uint8_t bNumInterfaces; ///< Number of interfaces supported by this configuration - uint8_t bConfigurationValue; ///< Value to use as an argument to the SetConfiguration() request to select this configuration. - uint8_t iConfiguration; ///< Index of string descriptor describing this configuration - uint8_t bmAttributes; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one. - uint8_t bMaxPower; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA). - } tusb_desc_configuration_t; - - /// USB Interface Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< INTERFACE Descriptor Type - - uint8_t bInterfaceNumber; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. - uint8_t bAlternateSetting; ///< Value used to select this alternate setting for the interface identified in the prior field - uint8_t bNumEndpoints; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe. - uint8_t bInterfaceClass; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF. - uint8_t bInterfaceSubClass; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. - uint8_t bInterfaceProtocol; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface. - uint8_t iInterface; ///< Index of string descriptor describing this interface - } tusb_desc_interface_t; - - /// USB Endpoint Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< ENDPOINT Descriptor Type - - uint8_t bEndpointAddress; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint. - - struct TU_ATTR_PACKED - { - uint8_t xfer : 2; - uint8_t sync : 2; - uint8_t usage : 2; - uint8_t : 2; - } bmAttributes; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host. - - struct TU_ATTR_PACKED - { - uint16_t size : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero. - uint16_t hs_period_mult : 2; - uint16_t TU_RESERVED : 3; - } wMaxPacketSize; - - uint8_t bInterval; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information. - } tusb_desc_endpoint_t; - - /// USB Other Speed Configuration Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of descriptor - uint8_t bDescriptorType; ///< Other_speed_Configuration Type - uint16_t wTotalLength; ///< Total length of data returned - - uint8_t bNumInterfaces; ///< Number of interfaces supported by this speed configuration - uint8_t bConfigurationValue; ///< Value to use to select configuration - uint8_t IConfiguration; ///< Index of string descriptor - uint8_t bmAttributes; ///< Same as Configuration descriptor - uint8_t bMaxPower; ///< Same as Configuration descriptor - } tusb_desc_other_speed_t; - - /// USB Device Qualifier Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of descriptor - uint8_t bDescriptorType; ///< Device Qualifier Type - uint16_t bcdUSB; ///< USB specification version number (e.g., 0200H for V2.00) - - uint8_t bDeviceClass; ///< Class Code - uint8_t bDeviceSubClass; ///< SubClass Code - uint8_t bDeviceProtocol; ///< Protocol Code - uint8_t bMaxPacketSize0; ///< Maximum packet size for other speed - uint8_t bNumConfigurations; ///< Number of Other-speed Configurations - uint8_t bReserved; ///< Reserved for future use, must be zero - } tusb_desc_device_qualifier_t; - - /// USB Interface Association Descriptor (IAD ECN) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of descriptor - uint8_t bDescriptorType; ///< Other_speed_Configuration Type - - uint8_t bFirstInterface; ///< Index of the first associated interface. - uint8_t bInterfaceCount; ///< Total number of associated interfaces. - - uint8_t bFunctionClass; ///< Interface class ID. - uint8_t bFunctionSubClass; ///< Interface subclass ID. - uint8_t bFunctionProtocol; ///< Interface protocol ID. - - uint8_t iFunction; ///< Index of the string descriptor describing the interface association. - } tusb_desc_interface_assoc_t; - - // USB String Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< Descriptor Type - uint16_t unicode_string[]; - } tusb_desc_string_t; - - // USB Binary Device Object Store (BOS) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t bReserved; - uint8_t PlatformCapabilityUUID[16]; - uint8_t CapabilityData[]; - } tusb_desc_bos_platform_t; - - // USB WebuSB URL Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bScheme; - char url[]; - } tusb_desc_webusb_url_t; - - /*------------------------------------------------------------------*/ - /* Types - *------------------------------------------------------------------*/ - typedef struct TU_ATTR_PACKED - { - union - { - struct TU_ATTR_PACKED - { - uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. - uint8_t type : 2; ///< Request type tusb_request_type_t. - uint8_t direction : 1; ///< Direction type. tusb_dir_t - } bmRequestType_bit; - - uint8_t bmRequestType; - }; - - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; - } tusb_control_request_t; - - TU_VERIFY_STATIC(sizeof(tusb_control_request_t) == 8, "size is not correct"); - - // TODO move to somewhere suitable - static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient) - { - return ((uint8_t)(direction << 7)) | ((uint8_t)(type << 5)) | (recipient); - } - - //--------------------------------------------------------------------+ - // Endpoint helper - //--------------------------------------------------------------------+ - - // Get direction from Endpoint address - static inline tusb_dir_t tu_edpt_dir(uint8_t addr) - { - return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - } - - // Get Endpoint number from address - static inline uint8_t tu_edpt_number(uint8_t addr) - { - return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); - } - - static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) - { - return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); - } - - //--------------------------------------------------------------------+ - // Descriptor helper - //--------------------------------------------------------------------+ - static inline uint8_t const *tu_desc_next(void const *desc) - { - uint8_t const *desc8 = (uint8_t const *)desc; - return desc8 + desc8[DESC_OFFSET_LEN]; - } - - static inline uint8_t tu_desc_type(void const *desc) - { - return ((uint8_t const *)desc)[DESC_OFFSET_TYPE]; - } - - static inline uint8_t tu_desc_len(void const *desc) - { - return ((uint8_t const *)desc)[DESC_OFFSET_LEN]; - } + TUSB_SPEED_FULL = 0, + TUSB_SPEED_LOW , + TUSB_SPEED_HIGH, + TUSB_SPEED_INVALID = 0xff, +}tusb_speed_t; + +/// defined base on USB Specs Endpoint's bmAttributes +typedef enum +{ + TUSB_XFER_CONTROL = 0 , + TUSB_XFER_ISOCHRONOUS , + TUSB_XFER_BULK , + TUSB_XFER_INTERRUPT +}tusb_xfer_type_t; + +typedef enum +{ + TUSB_DIR_OUT = 0, + TUSB_DIR_IN = 1, + + TUSB_DIR_IN_MASK = 0x80 +}tusb_dir_t; + +/// USB Descriptor Types +typedef enum +{ + TUSB_DESC_DEVICE = 0x01, + TUSB_DESC_CONFIGURATION = 0x02, + TUSB_DESC_STRING = 0x03, + TUSB_DESC_INTERFACE = 0x04, + TUSB_DESC_ENDPOINT = 0x05, + TUSB_DESC_DEVICE_QUALIFIER = 0x06, + TUSB_DESC_OTHER_SPEED_CONFIG = 0x07, + TUSB_DESC_INTERFACE_POWER = 0x08, + TUSB_DESC_OTG = 0x09, + TUSB_DESC_DEBUG = 0x0A, + TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B, + + TUSB_DESC_BOS = 0x0F, + TUSB_DESC_DEVICE_CAPABILITY = 0x10, + + TUSB_DESC_FUNCTIONAL = 0x21, + + // Class Specific Descriptor + TUSB_DESC_CS_DEVICE = 0x21, + TUSB_DESC_CS_CONFIGURATION = 0x22, + TUSB_DESC_CS_STRING = 0x23, + TUSB_DESC_CS_INTERFACE = 0x24, + TUSB_DESC_CS_ENDPOINT = 0x25, + + TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, + TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 +}tusb_desc_type_t; + +typedef enum +{ + TUSB_REQ_GET_STATUS = 0 , + TUSB_REQ_CLEAR_FEATURE = 1 , + TUSB_REQ_RESERVED = 2 , + TUSB_REQ_SET_FEATURE = 3 , + TUSB_REQ_RESERVED2 = 4 , + TUSB_REQ_SET_ADDRESS = 5 , + TUSB_REQ_GET_DESCRIPTOR = 6 , + TUSB_REQ_SET_DESCRIPTOR = 7 , + TUSB_REQ_GET_CONFIGURATION = 8 , + TUSB_REQ_SET_CONFIGURATION = 9 , + TUSB_REQ_GET_INTERFACE = 10 , + TUSB_REQ_SET_INTERFACE = 11 , + TUSB_REQ_SYNCH_FRAME = 12 +}tusb_request_code_t; + +typedef enum +{ + TUSB_REQ_FEATURE_EDPT_HALT = 0, + TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, + TUSB_REQ_FEATURE_TEST_MODE = 2 +}tusb_request_feature_selector_t; + +typedef enum +{ + TUSB_REQ_TYPE_STANDARD = 0, + TUSB_REQ_TYPE_CLASS, + TUSB_REQ_TYPE_VENDOR, + TUSB_REQ_TYPE_INVALID +} tusb_request_type_t; + +typedef enum +{ + TUSB_REQ_RCPT_DEVICE =0, + TUSB_REQ_RCPT_INTERFACE, + TUSB_REQ_RCPT_ENDPOINT, + TUSB_REQ_RCPT_OTHER +} tusb_request_recipient_t; + +// https://www.usb.org/defined-class-codes +typedef enum +{ + TUSB_CLASS_UNSPECIFIED = 0 , + TUSB_CLASS_AUDIO = 1 , + TUSB_CLASS_CDC = 2 , + TUSB_CLASS_HID = 3 , + TUSB_CLASS_RESERVED_4 = 4 , + TUSB_CLASS_PHYSICAL = 5 , + TUSB_CLASS_IMAGE = 6 , + TUSB_CLASS_PRINTER = 7 , + TUSB_CLASS_MSC = 8 , + TUSB_CLASS_HUB = 9 , + TUSB_CLASS_CDC_DATA = 10 , + TUSB_CLASS_SMART_CARD = 11 , + TUSB_CLASS_RESERVED_12 = 12 , + TUSB_CLASS_CONTENT_SECURITY = 13 , + TUSB_CLASS_VIDEO = 14 , + TUSB_CLASS_PERSONAL_HEALTHCARE = 15 , + TUSB_CLASS_AUDIO_VIDEO = 16 , + + TUSB_CLASS_DIAGNOSTIC = 0xDC , + TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0 , + TUSB_CLASS_MISC = 0xEF , + TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE , + TUSB_CLASS_VENDOR_SPECIFIC = 0xFF +}tusb_class_code_t; + +typedef enum +{ + MISC_SUBCLASS_COMMON = 2 +}misc_subclass_type_t; + +typedef enum +{ + MISC_PROTOCOL_IAD = 1 +}misc_protocol_type_t; + +typedef enum +{ + APP_SUBCLASS_USBTMC = 0x03, + APP_SUBCLASS_DFU_RUNTIME = 0x01 +} app_subclass_type_t; + +typedef enum +{ + DEVICE_CAPABILITY_WIRELESS_USB = 0x01, + DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, + DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, + DEVICE_CAPABILITY_CONTAINER_id = 0x04, + DEVICE_CAPABILITY_PLATFORM = 0x05, + DEVICE_CAPABILITY_POWER_DELIVERY = 0x06, + DEVICE_CAPABILITY_BATTERY_INFO = 0x07, + DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08, + DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09, + DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A, + DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B, + DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C, + DEVICE_CAPABILITY_BILLBOARD = 0x0D, + DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, + DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, + DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 +}device_capability_type_t; + +enum { + TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), + TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6), +}; + +#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2) + +/// Device State TODO remove +typedef enum +{ + TUSB_DEVICE_STATE_UNPLUG = 0 , + TUSB_DEVICE_STATE_CONFIGURED , + TUSB_DEVICE_STATE_SUSPENDED , +}tusb_device_state_t; + +typedef enum +{ + XFER_RESULT_SUCCESS, + XFER_RESULT_FAILED, + XFER_RESULT_STALLED, +}xfer_result_t; + +enum // TODO remove +{ + DESC_OFFSET_LEN = 0, + DESC_OFFSET_TYPE = 1 +}; + +enum +{ + INTERFACE_INVALID_NUMBER = 0xff +}; + + +typedef enum +{ + MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, + MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, + MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, + MS_OS_20_FEATURE_COMPATBLE_ID = 0x03, + MS_OS_20_FEATURE_REG_PROPERTY = 0x04, + MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05, + MS_OS_20_FEATURE_MODEL_ID = 0x06, + MS_OS_20_FEATURE_CCGP_DEVICE = 0x07, + MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 +} microsoft_os_20_type_t; + +enum +{ + CONTROL_STAGE_SETUP, + CONTROL_STAGE_DATA, + CONTROL_STAGE_ACK +}; + +//--------------------------------------------------------------------+ +// USB Descriptors +//--------------------------------------------------------------------+ + +/// USB Device Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType ; ///< DEVICE Descriptor Type. + uint16_t bcdUSB ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. + + uint8_t bDeviceClass ; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific. + uint8_t bDeviceSubClass ; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. + uint8_t bDeviceProtocol ; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis. + uint8_t bMaxPacketSize0 ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. + + uint16_t idVendor ; ///< Vendor ID (assigned by the USB-IF). + uint16_t idProduct ; ///< Product ID (assigned by the manufacturer). + uint16_t bcdDevice ; ///< Device release number in binary-coded decimal. + uint8_t iManufacturer ; ///< Index of string descriptor describing manufacturer. + uint8_t iProduct ; ///< Index of string descriptor describing product. + uint8_t iSerialNumber ; ///< Index of string descriptor describing the device's serial number. + + uint8_t bNumConfigurations ; ///< Number of possible configurations. +} tusb_desc_device_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct"); + +// USB Binary Device Object Store (BOS) Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type + uint16_t wTotalLength ; ///< Total length of data returned for this descriptor + uint8_t bNumDeviceCaps ; ///< Number of device capability descriptors in the BOS +} tusb_desc_bos_t; + +/// USB Configuration Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type + uint16_t wTotalLength ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. + + uint8_t bNumInterfaces ; ///< Number of interfaces supported by this configuration + uint8_t bConfigurationValue ; ///< Value to use as an argument to the SetConfiguration() request to select this configuration. + uint8_t iConfiguration ; ///< Index of string descriptor describing this configuration + uint8_t bmAttributes ; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one. + uint8_t bMaxPower ; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA). +} tusb_desc_configuration_t; + +/// USB Interface Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< INTERFACE Descriptor Type + + uint8_t bInterfaceNumber ; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. + uint8_t bAlternateSetting ; ///< Value used to select this alternate setting for the interface identified in the prior field + uint8_t bNumEndpoints ; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe. + uint8_t bInterfaceClass ; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF. + uint8_t bInterfaceSubClass ; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. + uint8_t bInterfaceProtocol ; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface. + uint8_t iInterface ; ///< Index of string descriptor describing this interface +} tusb_desc_interface_t; + +/// USB Endpoint Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< ENDPOINT Descriptor Type + + uint8_t bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint. + + struct TU_ATTR_PACKED { + uint8_t xfer : 2; + uint8_t sync : 2; + uint8_t usage : 2; + uint8_t : 2; + } bmAttributes ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host. + + struct TU_ATTR_PACKED { + uint16_t size : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero. + uint16_t hs_period_mult : 2; + uint16_t TU_RESERVED : 3; + }wMaxPacketSize; + + uint8_t bInterval ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information. +} tusb_desc_endpoint_t; + +/// USB Other Speed Configuration Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of descriptor + uint8_t bDescriptorType ; ///< Other_speed_Configuration Type + uint16_t wTotalLength ; ///< Total length of data returned + + uint8_t bNumInterfaces ; ///< Number of interfaces supported by this speed configuration + uint8_t bConfigurationValue ; ///< Value to use to select configuration + uint8_t IConfiguration ; ///< Index of string descriptor + uint8_t bmAttributes ; ///< Same as Configuration descriptor + uint8_t bMaxPower ; ///< Same as Configuration descriptor +} tusb_desc_other_speed_t; + +/// USB Device Qualifier Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of descriptor + uint8_t bDescriptorType ; ///< Device Qualifier Type + uint16_t bcdUSB ; ///< USB specification version number (e.g., 0200H for V2.00) + + uint8_t bDeviceClass ; ///< Class Code + uint8_t bDeviceSubClass ; ///< SubClass Code + uint8_t bDeviceProtocol ; ///< Protocol Code + uint8_t bMaxPacketSize0 ; ///< Maximum packet size for other speed + uint8_t bNumConfigurations ; ///< Number of Other-speed Configurations + uint8_t bReserved ; ///< Reserved for future use, must be zero +} tusb_desc_device_qualifier_t; + +/// USB Interface Association Descriptor (IAD ECN) +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of descriptor + uint8_t bDescriptorType ; ///< Other_speed_Configuration Type + + uint8_t bFirstInterface ; ///< Index of the first associated interface. + uint8_t bInterfaceCount ; ///< Total number of associated interfaces. + + uint8_t bFunctionClass ; ///< Interface class ID. + uint8_t bFunctionSubClass ; ///< Interface subclass ID. + uint8_t bFunctionProtocol ; ///< Interface protocol ID. + + uint8_t iFunction ; ///< Index of the string descriptor describing the interface association. +} tusb_desc_interface_assoc_t; + +// USB String Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< Descriptor Type + uint16_t unicode_string[]; +} tusb_desc_string_t; + +// USB Binary Device Object Store (BOS) +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength; + uint8_t bDescriptorType ; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; + uint8_t CapabilityData[]; +} tusb_desc_bos_platform_t; + +// USB WebuSB URL Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char url[]; +} tusb_desc_webusb_url_t; + +/*------------------------------------------------------------------*/ +/* Types + *------------------------------------------------------------------*/ +typedef struct TU_ATTR_PACKED{ + union { + struct TU_ATTR_PACKED { + uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. + uint8_t type : 2; ///< Request type tusb_request_type_t. + uint8_t direction : 1; ///< Direction type. tusb_dir_t + } bmRequestType_bit; + + uint8_t bmRequestType; + }; + + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} tusb_control_request_t; + +TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); + +// TODO move to somewhere suitable +static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient) +{ + return ((uint8_t) (direction << 7)) | ((uint8_t) (type << 5)) | (recipient); +} + +//--------------------------------------------------------------------+ +// Endpoint helper +//--------------------------------------------------------------------+ + +// Get direction from Endpoint address +static inline tusb_dir_t tu_edpt_dir(uint8_t addr) +{ + return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; +} + +// Get Endpoint number from address +static inline uint8_t tu_edpt_number(uint8_t addr) +{ + return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); +} + +static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) +{ + return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); +} + +//--------------------------------------------------------------------+ +// Descriptor helper +//--------------------------------------------------------------------+ +static inline uint8_t const * tu_desc_next(void const* desc) +{ + uint8_t const* desc8 = (uint8_t const*) desc; + return desc8 + desc8[DESC_OFFSET_LEN]; +} + +static inline uint8_t tu_desc_type(void const* desc) +{ + return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; +} + +static inline uint8_t tu_desc_len(void const* desc) +{ + return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; +} #ifdef __cplusplus -} + } #endif + // from tinyusb_hid.h #ifdef __cplusplus -extern "C" -{ + extern "C" { #endif -#define TU_U16_HIGH(u16) ((uint8_t)(((u16) >> 8) & 0x00ff)) -#define TU_U16_LOW(u16) ((uint8_t)((u16) & 0x00ff)) -#define U16_TO_U8S_BE(u16) TU_U16_HIGH(u16), TU_U16_LOW(u16) -#define U16_TO_U8S_LE(u16) TU_U16_LOW(u16), TU_U16_HIGH(u16) +#define TU_U16_HIGH(u16) ((uint8_t) (((u16) >> 8) & 0x00ff)) +#define TU_U16_LOW(u16) ((uint8_t) ((u16) & 0x00ff)) +#define U16_TO_U8S_BE(u16) TU_U16_HIGH(u16), TU_U16_LOW(u16) +#define U16_TO_U8S_LE(u16) TU_U16_LOW(u16), TU_U16_HIGH(u16) #ifndef TU_ATTR_PACKED #define TU_ATTR_PACKED __attribute__((packed)) #endif #ifndef TU_BIT -#define TU_BIT(x) (1 << (x)) +#define TU_BIT( x ) (1<<(x)) #endif /* USB constant and structure define */ /* USB PID */ #ifndef USB_PID_SETUP -#define USB_PID_NULL 0x00 /* reserved PID */ -#define USB_PID_SOF 0x05 -#define USB_PID_SETUP 0x0D -#define USB_PID_IN 0x09 -#define USB_PID_OUT 0x01 -#define USB_PID_ACK 0x02 -#define USB_PID_NAK 0x0A -#define USB_PID_STALL 0x0E -#define USB_PID_DATA0 0x03 -#define USB_PID_DATA1 0x0B -#define USB_PID_PRE 0x0C + #define USB_PID_NULL 0x00 /* reserved PID */ + #define USB_PID_SOF 0x05 + #define USB_PID_SETUP 0x0D + #define USB_PID_IN 0x09 + #define USB_PID_OUT 0x01 + #define USB_PID_ACK 0x02 + #define USB_PID_NAK 0x0A + #define USB_PID_STALL 0x0E + #define USB_PID_DATA0 0x03 + #define USB_PID_DATA1 0x0B + #define USB_PID_PRE 0x0C #endif /* USB standard device request code */ #ifndef USB_GET_DESCRIPTOR -#define USB_GET_STATUS 0x00 -#define USB_CLEAR_FEATURE 0x01 -#define USB_SET_FEATURE 0x03 -#define USB_SET_ADDRESS 0x05 -#define USB_GET_DESCRIPTOR 0x06 -#define USB_SET_DESCRIPTOR 0x07 -#define USB_GET_CONFIGURATION 0x08 -#define USB_SET_CONFIGURATION 0x09 -#define USB_GET_INTERFACE 0x0A -#define USB_SET_INTERFACE 0x0B -#define USB_SYNCH_FRAME 0x0C + #define USB_GET_STATUS 0x00 + #define USB_CLEAR_FEATURE 0x01 + #define USB_SET_FEATURE 0x03 + #define USB_SET_ADDRESS 0x05 + #define USB_GET_DESCRIPTOR 0x06 + #define USB_SET_DESCRIPTOR 0x07 + #define USB_GET_CONFIGURATION 0x08 + #define USB_SET_CONFIGURATION 0x09 + #define USB_GET_INTERFACE 0x0A + #define USB_SET_INTERFACE 0x0B + #define USB_SYNCH_FRAME 0x0C #endif /* USB hub class request code */ #ifndef HUB_GET_DESCRIPTOR -#define HUB_GET_STATUS 0x00 -#define HUB_CLEAR_FEATURE 0x01 -#define HUB_GET_STATE 0x02 -#define HUB_SET_FEATURE 0x03 -#define HUB_GET_DESCRIPTOR 0x06 -#define HUB_SET_DESCRIPTOR 0x07 + #define HUB_GET_STATUS 0x00 + #define HUB_CLEAR_FEATURE 0x01 + #define HUB_GET_STATE 0x02 + #define HUB_SET_FEATURE 0x03 + #define HUB_GET_DESCRIPTOR 0x06 + #define HUB_SET_DESCRIPTOR 0x07 #endif /* USB HID class request code */ #ifndef HID_GET_REPORT -#define HID_GET_REPORT 0x01 -#define HID_GET_IDLE 0x02 -#define HID_GET_PROTOCOL 0x03 -#define HID_SET_REPORT 0x09 -#define HID_SET_IDLE 0x0A -#define HID_SET_PROTOCOL 0x0B + #define HID_GET_REPORT 0x01 + #define HID_GET_IDLE 0x02 + #define HID_GET_PROTOCOL 0x03 + #define HID_SET_REPORT 0x09 + #define HID_SET_IDLE 0x0A + #define HID_SET_PROTOCOL 0x0B #endif /* USB CDC Class request code */ #ifndef CDC_GET_LINE_CODING -#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ -#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ -#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ -#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ #endif /* Bit define for USB request type */ #ifndef USB_REQ_TYP_MASK -#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ -#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ -#define USB_REQ_TYP_READ 0x80 /* control read, device to host */ -#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ -#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ -#define USB_REQ_TYP_STANDARD 0x00 -#define USB_REQ_TYP_CLASS 0x20 -#define USB_REQ_TYP_VENDOR 0x40 -#define USB_REQ_TYP_RESERVED 0x60 -#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ -#define USB_REQ_RECIP_DEVICE 0x00 -#define USB_REQ_RECIP_INTERF 0x01 -#define USB_REQ_RECIP_ENDP 0x02 -#define USB_REQ_RECIP_OTHER 0x03 -#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 -#define USB_REQ_FEAT_ENDP_HALT 0x00 + #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ + #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ + #define USB_REQ_TYP_READ 0x80 /* control read, device to host */ + #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ + #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ + #define USB_REQ_TYP_STANDARD 0x00 + #define USB_REQ_TYP_CLASS 0x20 + #define USB_REQ_TYP_VENDOR 0x40 + #define USB_REQ_TYP_RESERVED 0x60 + #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ + #define USB_REQ_RECIP_DEVICE 0x00 + #define USB_REQ_RECIP_INTERF 0x01 + #define USB_REQ_RECIP_ENDP 0x02 + #define USB_REQ_RECIP_OTHER 0x03 + #define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 + #define USB_REQ_FEAT_ENDP_HALT 0x00 #endif /* USB request type for hub class request */ #ifndef HUB_GET_HUB_DESCRIPTOR -#define HUB_CLEAR_HUB_FEATURE 0x20 -#define HUB_CLEAR_PORT_FEATURE 0x23 -#define HUB_GET_BUS_STATE 0xA3 -#define HUB_GET_HUB_DESCRIPTOR 0xA0 -#define HUB_GET_HUB_STATUS 0xA0 -#define HUB_GET_PORT_STATUS 0xA3 -#define HUB_SET_HUB_DESCRIPTOR 0x20 -#define HUB_SET_HUB_FEATURE 0x20 -#define HUB_SET_PORT_FEATURE 0x23 + #define HUB_CLEAR_HUB_FEATURE 0x20 + #define HUB_CLEAR_PORT_FEATURE 0x23 + #define HUB_GET_BUS_STATE 0xA3 + #define HUB_GET_HUB_DESCRIPTOR 0xA0 + #define HUB_GET_HUB_STATUS 0xA0 + #define HUB_GET_PORT_STATUS 0xA3 + #define HUB_SET_HUB_DESCRIPTOR 0x20 + #define HUB_SET_HUB_FEATURE 0x20 + #define HUB_SET_PORT_FEATURE 0x23 #endif /* Hub class feature selectors */ #ifndef HUB_PORT_RESET -#define HUB_C_HUB_LOCAL_POWER 0 -#define HUB_C_HUB_OVER_CURRENT 1 -#define HUB_PORT_CONNECTION 0 -#define HUB_PORT_ENABLE 1 -#define HUB_PORT_SUSPEND 2 -#define HUB_PORT_OVER_CURRENT 3 -#define HUB_PORT_RESET 4 -#define HUB_PORT_POWER 8 -#define HUB_PORT_LOW_SPEED 9 -#define HUB_C_PORT_CONNECTION 16 -#define HUB_C_PORT_ENABLE 17 -#define HUB_C_PORT_SUSPEND 18 -#define HUB_C_PORT_OVER_CURRENT 19 -#define HUB_C_PORT_RESET 20 + #define HUB_C_HUB_LOCAL_POWER 0 + #define HUB_C_HUB_OVER_CURRENT 1 + #define HUB_PORT_CONNECTION 0 + #define HUB_PORT_ENABLE 1 + #define HUB_PORT_SUSPEND 2 + #define HUB_PORT_OVER_CURRENT 3 + #define HUB_PORT_RESET 4 + #define HUB_PORT_POWER 8 + #define HUB_PORT_LOW_SPEED 9 + #define HUB_C_PORT_CONNECTION 16 + #define HUB_C_PORT_ENABLE 17 + #define HUB_C_PORT_SUSPEND 18 + #define HUB_C_PORT_OVER_CURRENT 19 + #define HUB_C_PORT_RESET 20 #endif /* USB descriptor type */ #ifndef USB_DESCR_TYP_DEVICE -#define USB_DESCR_TYP_DEVICE 0x01 -#define USB_DESCR_TYP_CONFIG 0x02 -#define USB_DESCR_TYP_STRING 0x03 -#define USB_DESCR_TYP_INTERF 0x04 -#define USB_DESCR_TYP_ENDP 0x05 -#define USB_DESCR_TYP_QUALIF 0x06 -#define USB_DESCR_TYP_SPEED 0x07 -#define USB_DESCR_TYP_OTG 0x09 -#define USB_DESCR_TYP_HID 0x21 -#define USB_DESCR_TYP_REPORT 0x22 -#define USB_DESCR_TYP_PHYSIC 0x23 -#define USB_DESCR_TYP_CS_INTF 0x24 -#define USB_DESCR_TYP_CS_ENDP 0x25 -#define USB_DESCR_TYP_HUB 0x29 + #define USB_DESCR_TYP_DEVICE 0x01 + #define USB_DESCR_TYP_CONFIG 0x02 + #define USB_DESCR_TYP_STRING 0x03 + #define USB_DESCR_TYP_INTERF 0x04 + #define USB_DESCR_TYP_ENDP 0x05 + #define USB_DESCR_TYP_QUALIF 0x06 + #define USB_DESCR_TYP_SPEED 0x07 + #define USB_DESCR_TYP_OTG 0x09 + #define USB_DESCR_TYP_HID 0x21 + #define USB_DESCR_TYP_REPORT 0x22 + #define USB_DESCR_TYP_PHYSIC 0x23 + #define USB_DESCR_TYP_CS_INTF 0x24 + #define USB_DESCR_TYP_CS_ENDP 0x25 + #define USB_DESCR_TYP_HUB 0x29 #endif /* USB device class */ #ifndef USB_DEV_CLASS_HUB -#define USB_DEV_CLASS_RESERVED 0x00 -#define USB_DEV_CLASS_AUDIO 0x01 -#define USB_DEV_CLASS_COMMUNIC 0x02 -#define USB_DEV_CLASS_HID 0x03 -#define USB_DEV_CLASS_MONITOR 0x04 -#define USB_DEV_CLASS_PHYSIC_IF 0x05 -#define USB_DEV_CLASS_IMAGE 0x06 -#define USB_DEV_CLASS_PRINTER 0x07 -#define USB_DEV_CLASS_STORAGE 0x08 -#define USB_DEV_CLASS_HUB 0x09 -#define USB_DEV_CLASS_VEN_SPEC 0xFF + #define USB_DEV_CLASS_RESERVED 0x00 + #define USB_DEV_CLASS_AUDIO 0x01 + #define USB_DEV_CLASS_COMMUNIC 0x02 + #define USB_DEV_CLASS_HID 0x03 + #define USB_DEV_CLASS_MONITOR 0x04 + #define USB_DEV_CLASS_PHYSIC_IF 0x05 + #define USB_DEV_CLASS_IMAGE 0x06 + #define USB_DEV_CLASS_PRINTER 0x07 + #define USB_DEV_CLASS_STORAGE 0x08 + #define USB_DEV_CLASS_HUB 0x09 + #define USB_DEV_CLASS_VEN_SPEC 0xFF #endif /* USB endpoint type and attributes */ #ifndef USB_ENDP_TYPE_MASK -#define USB_ENDP_DIR_MASK 0x80 -#define USB_ENDP_ADDR_MASK 0x0F -#define USB_ENDP_TYPE_MASK 0x03 -#define USB_ENDP_TYPE_CTRL 0x00 -#define USB_ENDP_TYPE_ISOCH 0x01 -#define USB_ENDP_TYPE_BULK 0x02 -#define USB_ENDP_TYPE_INTER 0x03 + #define USB_ENDP_DIR_MASK 0x80 + #define USB_ENDP_ADDR_MASK 0x0F + #define USB_ENDP_TYPE_MASK 0x03 + #define USB_ENDP_TYPE_CTRL 0x00 + #define USB_ENDP_TYPE_ISOCH 0x01 + #define USB_ENDP_TYPE_BULK 0x02 + #define USB_ENDP_TYPE_INTER 0x03 #endif #ifndef USB_DEVICE_ADDR -#define USB_DEVICE_ADDR 0x02 + #define USB_DEVICE_ADDR 0x02 #endif #ifndef DEFAULT_ENDP0_SIZE -#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ + #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ #endif #ifndef MAX_PACKET_SIZE -#define MAX_PACKET_SIZE 64 /* maximum packet size */ + #define MAX_PACKET_SIZE 64 /* maximum packet size */ #endif #ifndef USB_BO_CBW_SIZE -#define USB_BO_CBW_SIZE 0x1F -#define USB_BO_CSW_SIZE 0x0D + #define USB_BO_CBW_SIZE 0x1F + #define USB_BO_CSW_SIZE 0x0D #endif #ifndef USB_BO_CBW_SIG0 -#define USB_BO_CBW_SIG0 0x55 -#define USB_BO_CBW_SIG1 0x53 -#define USB_BO_CBW_SIG2 0x42 -#define USB_BO_CBW_SIG3 0x43 -#define USB_BO_CSW_SIG0 0x55 -#define USB_BO_CSW_SIG1 0x53 -#define USB_BO_CSW_SIG2 0x42 -#define USB_BO_CSW_SIG3 0x53 + #define USB_BO_CBW_SIG0 0x55 + #define USB_BO_CBW_SIG1 0x53 + #define USB_BO_CBW_SIG2 0x42 + #define USB_BO_CBW_SIG3 0x43 + #define USB_BO_CSW_SIG0 0x55 + #define USB_BO_CSW_SIG1 0x53 + #define USB_BO_CSW_SIG2 0x42 + #define USB_BO_CSW_SIG3 0x53 #endif #define DEF_STRING_DESC_LANG 0x00 @@ -759,490 +752,492 @@ extern "C" #define DEF_STRING_DESC_PROD 0x02 #define DEF_STRING_DESC_SERN 0x03 - //--------------------------------------------------------------------+ - // Common Definitions - //--------------------------------------------------------------------+ - /** \defgroup ClassDriver_HID_Common Common Definitions - * @{ */ - /// USB HID Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; /**< Numeric expression that is the total size of the HID descriptor */ - uint8_t bDescriptorType; /**< Constant name specifying type of HID descriptor. */ +//--------------------------------------------------------------------+ +// Common Definitions +//--------------------------------------------------------------------+ +/** \defgroup ClassDriver_HID_Common Common Definitions + * @{ */ - uint16_t bcdHID; /**< Numeric expression identifying the HID Class Specification release */ - uint8_t bCountryCode; /**< Numeric expression identifying country code of the localized hardware. */ - uint8_t bNumDescriptors; /**< Numeric expression specifying the number of class descriptors */ + /// USB HID Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength; /**< Numeric expression that is the total size of the HID descriptor */ + uint8_t bDescriptorType; /**< Constant name specifying type of HID descriptor. */ - uint8_t bReportType; /**< Type of HID class report. */ - uint16_t wReportLength; /**< the total size of the Report descriptor. */ - } tusb_hid_descriptor_hid_t; + uint16_t bcdHID; /**< Numeric expression identifying the HID Class Specification release */ + uint8_t bCountryCode; /**< Numeric expression identifying country code of the localized hardware. */ + uint8_t bNumDescriptors; /**< Numeric expression specifying the number of class descriptors */ - /// HID Subclass - typedef enum - { - HID_SUBCLASS_NONE = 0, ///< No Subclass - HID_SUBCLASS_BOOT = 1 ///< Boot Interface Subclass - } hid_subclass_type_t; + uint8_t bReportType; /**< Type of HID class report. */ + uint16_t wReportLength; /**< the total size of the Report descriptor. */ +} tusb_hid_descriptor_hid_t; - /// HID Protocol - typedef enum - { - HID_PROTOCOL_NONE = 0, ///< None - HID_PROTOCOL_KEYBOARD = 1, ///< Keyboard - HID_PROTOCOL_MOUSE = 2 ///< Mouse - } hid_protocol_type_t; +/// HID Subclass +typedef enum +{ + HID_SUBCLASS_NONE = 0, ///< No Subclass + HID_SUBCLASS_BOOT = 1 ///< Boot Interface Subclass +}hid_subclass_type_t; - /// HID Descriptor Type - typedef enum - { - HID_DESC_TYPE_HID = 0x21, ///< HID Descriptor - HID_DESC_TYPE_REPORT = 0x22, ///< Report Descriptor - HID_DESC_TYPE_PHYSICAL = 0x23 ///< Physical Descriptor - } hid_descriptor_type_t; +/// HID Protocol +typedef enum +{ + HID_PROTOCOL_NONE = 0, ///< None + HID_PROTOCOL_KEYBOARD = 1, ///< Keyboard + HID_PROTOCOL_MOUSE = 2 ///< Mouse +}hid_protocol_type_t; - /// HID Request Report Type - typedef enum - { - HID_REPORT_TYPE_INVALID = 0, - HID_REPORT_TYPE_INPUT, ///< Input - HID_REPORT_TYPE_OUTPUT, ///< Output - HID_REPORT_TYPE_FEATURE ///< Feature - } hid_report_type_t; +/// HID Descriptor Type +typedef enum +{ + HID_DESC_TYPE_HID = 0x21, ///< HID Descriptor + HID_DESC_TYPE_REPORT = 0x22, ///< Report Descriptor + HID_DESC_TYPE_PHYSICAL = 0x23 ///< Physical Descriptor +}hid_descriptor_type_t; - /// HID Class Specific Control Request - typedef enum - { - HID_REQ_CONTROL_GET_REPORT = 0x01, ///< Get Report - HID_REQ_CONTROL_GET_IDLE = 0x02, ///< Get Idle - HID_REQ_CONTROL_GET_PROTOCOL = 0x03, ///< Get Protocol - HID_REQ_CONTROL_SET_REPORT = 0x09, ///< Set Report - HID_REQ_CONTROL_SET_IDLE = 0x0a, ///< Set Idle - HID_REQ_CONTROL_SET_PROTOCOL = 0x0b ///< Set Protocol - } hid_request_type_t; +/// HID Request Report Type +typedef enum +{ + HID_REPORT_TYPE_INVALID = 0, + HID_REPORT_TYPE_INPUT, ///< Input + HID_REPORT_TYPE_OUTPUT, ///< Output + HID_REPORT_TYPE_FEATURE ///< Feature +}hid_report_type_t; - /// HID Country Code - typedef enum - { - HID_LOCAL_NotSupported = 0, ///< NotSupported - HID_LOCAL_Arabic, ///< Arabic - HID_LOCAL_Belgian, ///< Belgian - HID_LOCAL_Canadian_Bilingual, ///< Canadian_Bilingual - HID_LOCAL_Canadian_French, ///< Canadian_French - HID_LOCAL_Czech_Republic, ///< Czech_Republic - HID_LOCAL_Danish, ///< Danish - HID_LOCAL_Finnish, ///< Finnish - HID_LOCAL_French, ///< French - HID_LOCAL_German, ///< German - HID_LOCAL_Greek, ///< Greek - HID_LOCAL_Hebrew, ///< Hebrew - HID_LOCAL_Hungary, ///< Hungary - HID_LOCAL_International, ///< International - HID_LOCAL_Italian, ///< Italian - HID_LOCAL_Japan_Katakana, ///< Japan_Katakana - HID_LOCAL_Korean, ///< Korean - HID_LOCAL_Latin_American, ///< Latin_American - HID_LOCAL_Netherlands_Dutch, ///< Netherlands/Dutch - HID_LOCAL_Norwegian, ///< Norwegian - HID_LOCAL_Persian_Farsi, ///< Persian (Farsi) - HID_LOCAL_Poland, ///< Poland - HID_LOCAL_Portuguese, ///< Portuguese - HID_LOCAL_Russia, ///< Russia - HID_LOCAL_Slovakia, ///< Slovakia - HID_LOCAL_Spanish, ///< Spanish - HID_LOCAL_Swedish, ///< Swedish - HID_LOCAL_Swiss_French, ///< Swiss/French - HID_LOCAL_Swiss_German, ///< Swiss/German - HID_LOCAL_Switzerland, ///< Switzerland - HID_LOCAL_Taiwan, ///< Taiwan - HID_LOCAL_Turkish_Q, ///< Turkish-Q - HID_LOCAL_UK, ///< UK - HID_LOCAL_US, ///< US - HID_LOCAL_Yugoslavia, ///< Yugoslavia - HID_LOCAL_Turkish_F ///< Turkish-F - } hid_country_code_t; +/// HID Class Specific Control Request +typedef enum +{ + HID_REQ_CONTROL_GET_REPORT = 0x01, ///< Get Report + HID_REQ_CONTROL_GET_IDLE = 0x02, ///< Get Idle + HID_REQ_CONTROL_GET_PROTOCOL = 0x03, ///< Get Protocol + HID_REQ_CONTROL_SET_REPORT = 0x09, ///< Set Report + HID_REQ_CONTROL_SET_IDLE = 0x0a, ///< Set Idle + HID_REQ_CONTROL_SET_PROTOCOL = 0x0b ///< Set Protocol +}hid_request_type_t; - /** @} */ +/// HID Country Code +typedef enum +{ + HID_LOCAL_NotSupported = 0 , ///< NotSupported + HID_LOCAL_Arabic , ///< Arabic + HID_LOCAL_Belgian , ///< Belgian + HID_LOCAL_Canadian_Bilingual , ///< Canadian_Bilingual + HID_LOCAL_Canadian_French , ///< Canadian_French + HID_LOCAL_Czech_Republic , ///< Czech_Republic + HID_LOCAL_Danish , ///< Danish + HID_LOCAL_Finnish , ///< Finnish + HID_LOCAL_French , ///< French + HID_LOCAL_German , ///< German + HID_LOCAL_Greek , ///< Greek + HID_LOCAL_Hebrew , ///< Hebrew + HID_LOCAL_Hungary , ///< Hungary + HID_LOCAL_International , ///< International + HID_LOCAL_Italian , ///< Italian + HID_LOCAL_Japan_Katakana , ///< Japan_Katakana + HID_LOCAL_Korean , ///< Korean + HID_LOCAL_Latin_American , ///< Latin_American + HID_LOCAL_Netherlands_Dutch , ///< Netherlands/Dutch + HID_LOCAL_Norwegian , ///< Norwegian + HID_LOCAL_Persian_Farsi , ///< Persian (Farsi) + HID_LOCAL_Poland , ///< Poland + HID_LOCAL_Portuguese , ///< Portuguese + HID_LOCAL_Russia , ///< Russia + HID_LOCAL_Slovakia , ///< Slovakia + HID_LOCAL_Spanish , ///< Spanish + HID_LOCAL_Swedish , ///< Swedish + HID_LOCAL_Swiss_French , ///< Swiss/French + HID_LOCAL_Swiss_German , ///< Swiss/German + HID_LOCAL_Switzerland , ///< Switzerland + HID_LOCAL_Taiwan , ///< Taiwan + HID_LOCAL_Turkish_Q , ///< Turkish-Q + HID_LOCAL_UK , ///< UK + HID_LOCAL_US , ///< US + HID_LOCAL_Yugoslavia , ///< Yugoslavia + HID_LOCAL_Turkish_F ///< Turkish-F +} hid_country_code_t; - //--------------------------------------------------------------------+ - // GAMEPAD - //--------------------------------------------------------------------+ - /** \addtogroup ClassDriver_HID_Gamepad Gamepad - * @{ */ +/** @} */ - /* From https://www.kernel.org/doc/html/latest/input/gamepad.html - ____________________________ __ - / [__ZL__] [__ZR__] \ | - / [__ TL __] [__ TR __] \ | Front Triggers - __/________________________________\__ __| - / _ \ | - / /\ __ (N) \ | - / || __ |MO| __ _ _ \ | Main Pad - | <===DP===> |SE| |ST| (W) -|- (E) | | - \ || ___ ___ _ / | - /\ \/ / \ / \ (S) /\ __| - / \________ | LS | ____ | RS | ________/ \ | - | / \ \___/ / \ \___/ / \ | | Control Sticks - | / \_____/ \_____/ \ | __| - | / \ | - \_____/ \_____/ +//--------------------------------------------------------------------+ +// GAMEPAD +//--------------------------------------------------------------------+ +/** \addtogroup ClassDriver_HID_Gamepad Gamepad + * @{ */ - |________|______| |______|___________| - D-Pad Left Right Action Pad - Stick Stick +/* From https://www.kernel.org/doc/html/latest/input/gamepad.html + ____________________________ __ + / [__ZL__] [__ZR__] \ | + / [__ TL __] [__ TR __] \ | Front Triggers + __/________________________________\__ __| + / _ \ | + / /\ __ (N) \ | + / || __ |MO| __ _ _ \ | Main Pad + | <===DP===> |SE| |ST| (W) -|- (E) | | + \ || ___ ___ _ / | + /\ \/ / \ / \ (S) /\ __| + / \________ | LS | ____ | RS | ________/ \ | +| / \ \___/ / \ \___/ / \ | | Control Sticks +| / \_____/ \_____/ \ | __| +| / \ | + \_____/ \_____/ - |_____________| - Menu Pad + |________|______| |______|___________| + D-Pad Left Right Action Pad + Stick Stick - Most gamepads have the following features: - - Action-Pad 4 buttons in diamonds-shape (on the right side) NORTH, SOUTH, WEST and EAST. - - D-Pad (Direction-pad) 4 buttons (on the left side) that point up, down, left and right. - - Menu-Pad Different constellations, but most-times 2 buttons: SELECT - START. - - Analog-Sticks provide freely moveable sticks to control directions, Analog-sticks may also - provide a digital button if you press them. - - Triggers are located on the upper-side of the pad in vertical direction. The upper buttons - are normally named Left- and Right-Triggers, the lower buttons Z-Left and Z-Right. - - Rumble Many devices provide force-feedback features. But are mostly just simple rumble motors. - */ + |_____________| + Menu Pad - /// HID Gamepad Protocol Report. - typedef struct TU_ATTR_PACKED - { - int8_t x; ///< Delta x movement of left analog-stick - int8_t y; ///< Delta y movement of left analog-stick - int8_t z; ///< Delta z movement of right analog-joystick - int8_t rz; ///< Delta Rz movement of right analog-joystick - int8_t rx; ///< Delta Rx movement of analog left trigger - int8_t ry; ///< Delta Ry movement of analog right trigger - uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat - uint16_t buttons; ///< Buttons mask for currently pressed buttons - } hid_gamepad_report_t; + Most gamepads have the following features: + - Action-Pad 4 buttons in diamonds-shape (on the right side) NORTH, SOUTH, WEST and EAST. + - D-Pad (Direction-pad) 4 buttons (on the left side) that point up, down, left and right. + - Menu-Pad Different constellations, but most-times 2 buttons: SELECT - START. + - Analog-Sticks provide freely moveable sticks to control directions, Analog-sticks may also + provide a digital button if you press them. + - Triggers are located on the upper-side of the pad in vertical direction. The upper buttons + are normally named Left- and Right-Triggers, the lower buttons Z-Left and Z-Right. + - Rumble Many devices provide force-feedback features. But are mostly just simple rumble motors. + */ - /// HID Switch Gamepad Protocol Report. - typedef struct TU_ATTR_PACKED - { - uint16_t buttons; ///< Buttons mask for currently pressed buttons - uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat - int8_t x; ///< Delta x movement of left analog-stick - int8_t y; ///< Delta y movement of left analog-stick - int8_t rx; ///< Delta Rx movement of analog left trigger - int8_t ry; ///< Delta Ry movement of analog right trigger - int8_t z; ///< Delta z movement of right analog-joystick - int8_t rz; ///< Delta Rz movement of right analog-joystick - } hid_gamepad_ns_report_t; +/// HID Gamepad Protocol Report. +typedef struct TU_ATTR_PACKED +{ + int8_t x; ///< Delta x movement of left analog-stick + int8_t y; ///< Delta y movement of left analog-stick + int8_t z; ///< Delta z movement of right analog-joystick + int8_t rz; ///< Delta Rz movement of right analog-joystick + int8_t rx; ///< Delta Rx movement of analog left trigger + int8_t ry; ///< Delta Ry movement of analog right trigger + uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat + uint16_t buttons; ///< Buttons mask for currently pressed buttons +}hid_gamepad_report_t; - /// Standard Gamepad Buttons Bitmap (from Linux input event codes) - typedef enum - { - GAMEPAD_BUTTON_A = TU_BIT(0), ///< A/South button - GAMEPAD_BUTTON_B = TU_BIT(1), ///< B/East button - GAMEPAD_BUTTON_C = TU_BIT(2), ///< C button - GAMEPAD_BUTTON_X = TU_BIT(3), ///< X/North button - GAMEPAD_BUTTON_Y = TU_BIT(4), ///< Y/West button - GAMEPAD_BUTTON_Z = TU_BIT(5), ///< Z button - GAMEPAD_BUTTON_TL = TU_BIT(6), ///< L1 button - GAMEPAD_BUTTON_TR = TU_BIT(7), ///< R1 button - GAMEPAD_BUTTON_TL2 = TU_BIT(8), ///< L2 button - GAMEPAD_BUTTON_TR2 = TU_BIT(9), ///< R2 button - GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button - GAMEPAD_BUTTON_START = TU_BIT(11), ///< Start button - GAMEPAD_BUTTON_MODE = TU_BIT(12), ///< Mode button - GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button - GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button - // GAMEPAD_BUTTON_ = TU_BIT(15), ///< Undefined button - } hid_gamepad_button_bm_t; +/// HID Switch Gamepad Protocol Report. +typedef struct TU_ATTR_PACKED +{ + uint16_t buttons; ///< Buttons mask for currently pressed buttons + uint8_t hat; ///< Buttons mask for currently pressed buttons in the DPad/hat + int8_t x; ///< Delta x movement of left analog-stick + int8_t y; ///< Delta y movement of left analog-stick + int8_t rx; ///< Delta Rx movement of analog left trigger + int8_t ry; ///< Delta Ry movement of analog right trigger + int8_t z; ///< Delta z movement of right analog-joystick + int8_t rz; ///< Delta Rz movement of right analog-joystick +}hid_gamepad_ns_report_t; - /// Switch Gamepad Buttons Bitmap - typedef enum - { - GAMEPAD_NS_BUTTON_Y = 0x01, - GAMEPAD_NS_BUTTON_B = 0x02, - GAMEPAD_NS_BUTTON_A = 0x04, - GAMEPAD_NS_BUTTON_X = 0x08, - GAMEPAD_NS_BUTTON_TL = 0x10, - GAMEPAD_NS_BUTTON_TR = 0x20, - GAMEPAD_NS_BUTTON_TL2 = 0x40, - GAMEPAD_NS_BUTTON_TR2 = 0x80, - GAMEPAD_NS_BUTTON_MINUS = 0x100, - GAMEPAD_NS_BUTTON_PLUS = 0x200, - GAMEPAD_NS_BUTTON_THUMBL = 0x400, - GAMEPAD_NS_BUTTON_THUMBR = 0x800, - GAMEPAD_NS_BUTTON_HOME = 0x1000, - GAMEPAD_NS_BUTTON_CAPTURE = 0x2000, - GAMEPAD_NS_BUTTON_Z = 0x4000, /// UNUSED? - } hid_gamepad_ns_button_bm_t; +/// Standard Gamepad Buttons Bitmap (from Linux input event codes) +typedef enum +{ + GAMEPAD_BUTTON_A = TU_BIT(0), ///< A/South button + GAMEPAD_BUTTON_B = TU_BIT(1), ///< B/East button + GAMEPAD_BUTTON_C = TU_BIT(2), ///< C button + GAMEPAD_BUTTON_X = TU_BIT(3), ///< X/North button + GAMEPAD_BUTTON_Y = TU_BIT(4), ///< Y/West button + GAMEPAD_BUTTON_Z = TU_BIT(5), ///< Z button + GAMEPAD_BUTTON_TL = TU_BIT(6), ///< L1 button + GAMEPAD_BUTTON_TR = TU_BIT(7), ///< R1 button + GAMEPAD_BUTTON_TL2 = TU_BIT(8), ///< L2 button + GAMEPAD_BUTTON_TR2 = TU_BIT(9), ///< R2 button + GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button + GAMEPAD_BUTTON_START = TU_BIT(11), ///< Start button + GAMEPAD_BUTTON_MODE = TU_BIT(12), ///< Mode button + GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button + GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button +//GAMEPAD_BUTTON_ = TU_BIT(15), ///< Undefined button +}hid_gamepad_button_bm_t; - /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes) - typedef enum - { - GAMEPAD_HAT_CENTERED = 0, ///< DPAD_CENTERED - GAMEPAD_HAT_UP = 1, ///< DPAD_UP - GAMEPAD_HAT_UP_RIGHT = 2, ///< DPAD_UP_RIGHT - GAMEPAD_HAT_RIGHT = 3, ///< DPAD_RIGHT - GAMEPAD_HAT_DOWN_RIGHT = 4, ///< DPAD_DOWN_RIGHT - GAMEPAD_HAT_DOWN = 5, ///< DPAD_DOWN - GAMEPAD_HAT_DOWN_LEFT = 6, ///< DPAD_DOWN_LEFT - GAMEPAD_HAT_LEFT = 7, ///< DPAD_LEFT - GAMEPAD_HAT_UP_LEFT = 8, ///< DPAD_UP_LEFT - } hid_gamepad_hat_t; +/// Switch Gamepad Buttons Bitmap +typedef enum +{ + GAMEPAD_NS_BUTTON_Y = 0x01, + GAMEPAD_NS_BUTTON_B = 0x02, + GAMEPAD_NS_BUTTON_A = 0x04, + GAMEPAD_NS_BUTTON_X = 0x08, + GAMEPAD_NS_BUTTON_TL = 0x10, + GAMEPAD_NS_BUTTON_TR = 0x20, + GAMEPAD_NS_BUTTON_TL2 = 0x40, + GAMEPAD_NS_BUTTON_TR2 = 0x80, + GAMEPAD_NS_BUTTON_MINUS = 0x100, + GAMEPAD_NS_BUTTON_PLUS = 0x200, + GAMEPAD_NS_BUTTON_THUMBL = 0x400, + GAMEPAD_NS_BUTTON_THUMBR = 0x800, + GAMEPAD_NS_BUTTON_HOME = 0x1000, + GAMEPAD_NS_BUTTON_CAPTURE = 0x2000, + GAMEPAD_NS_BUTTON_Z = 0x4000, ///UNUSED? +}hid_gamepad_ns_button_bm_t; - /// Switch Gamepad HAT/DPAD Buttons (from Linux input event codes) - typedef enum - { - GAMEPAD_NS_HAT_CENTERED = 8, ///< DPAD_CENTERED - GAMEPAD_NS_HAT_UP = 0, ///< DPAD_UP - GAMEPAD_NS_HAT_UP_RIGHT = 1, ///< DPAD_UP_RIGHT - GAMEPAD_NS_HAT_RIGHT = 2, ///< DPAD_RIGHT - GAMEPAD_NS_HAT_DOWN_RIGHT = 3, ///< DPAD_DOWN_RIGHT - GAMEPAD_NS_HAT_DOWN = 4, ///< DPAD_DOWN - GAMEPAD_NS_HAT_DOWN_LEFT = 5, ///< DPAD_DOWN_LEFT - GAMEPAD_NS_HAT_LEFT = 6, ///< DPAD_LEFT - GAMEPAD_NS_HAT_UP_LEFT = 7, ///< DPAD_UP_LEFT - } hid_gamepad_ns_hat_t; +/// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes) +typedef enum +{ + GAMEPAD_HAT_CENTERED = 0, ///< DPAD_CENTERED + GAMEPAD_HAT_UP = 1, ///< DPAD_UP + GAMEPAD_HAT_UP_RIGHT = 2, ///< DPAD_UP_RIGHT + GAMEPAD_HAT_RIGHT = 3, ///< DPAD_RIGHT + GAMEPAD_HAT_DOWN_RIGHT = 4, ///< DPAD_DOWN_RIGHT + GAMEPAD_HAT_DOWN = 5, ///< DPAD_DOWN + GAMEPAD_HAT_DOWN_LEFT = 6, ///< DPAD_DOWN_LEFT + GAMEPAD_HAT_LEFT = 7, ///< DPAD_LEFT + GAMEPAD_HAT_UP_LEFT = 8, ///< DPAD_UP_LEFT +}hid_gamepad_hat_t; - /// @} +/// Switch Gamepad HAT/DPAD Buttons (from Linux input event codes) +typedef enum +{ + GAMEPAD_NS_HAT_CENTERED = 8, ///< DPAD_CENTERED + GAMEPAD_NS_HAT_UP = 0, ///< DPAD_UP + GAMEPAD_NS_HAT_UP_RIGHT = 1, ///< DPAD_UP_RIGHT + GAMEPAD_NS_HAT_RIGHT = 2, ///< DPAD_RIGHT + GAMEPAD_NS_HAT_DOWN_RIGHT = 3, ///< DPAD_DOWN_RIGHT + GAMEPAD_NS_HAT_DOWN = 4, ///< DPAD_DOWN + GAMEPAD_NS_HAT_DOWN_LEFT = 5, ///< DPAD_DOWN_LEFT + GAMEPAD_NS_HAT_LEFT = 6, ///< DPAD_LEFT + GAMEPAD_NS_HAT_UP_LEFT = 7, ///< DPAD_UP_LEFT +}hid_gamepad_ns_hat_t; - //--------------------------------------------------------------------+ - // MOUSE - //--------------------------------------------------------------------+ - /** \addtogroup ClassDriver_HID_Mouse Mouse - * @{ */ +/// @} - /// Standard HID Boot Protocol Mouse Report. - typedef struct TU_ATTR_PACKED - { - uint8_t buttons; /**< buttons mask for currently pressed buttons in the mouse. */ - int8_t x; /**< Current delta x movement of the mouse. */ - int8_t y; /**< Current delta y movement on the mouse. */ - int8_t wheel; /**< Current delta wheel movement on the mouse. */ - int8_t pan; // using AC Pan - } hid_mouse_report_t; +//--------------------------------------------------------------------+ +// MOUSE +//--------------------------------------------------------------------+ +/** \addtogroup ClassDriver_HID_Mouse Mouse + * @{ */ - /// Standard Mouse Buttons Bitmap - typedef enum - { - MOUSE_BUTTON_LEFT = TU_BIT(0), ///< Left button - MOUSE_BUTTON_RIGHT = TU_BIT(1), ///< Right button - MOUSE_BUTTON_MIDDLE = TU_BIT(2), ///< Middle button - MOUSE_BUTTON_BACKWARD = TU_BIT(3), ///< Backward button, - MOUSE_BUTTON_FORWARD = TU_BIT(4), ///< Forward button, - } hid_mouse_button_bm_t; +/// Standard HID Boot Protocol Mouse Report. +typedef struct TU_ATTR_PACKED +{ + uint8_t buttons; /**< buttons mask for currently pressed buttons in the mouse. */ + int8_t x; /**< Current delta x movement of the mouse. */ + int8_t y; /**< Current delta y movement on the mouse. */ + int8_t wheel; /**< Current delta wheel movement on the mouse. */ + int8_t pan; // using AC Pan +} hid_mouse_report_t; - /// @} +/// Standard Mouse Buttons Bitmap +typedef enum +{ + MOUSE_BUTTON_LEFT = TU_BIT(0), ///< Left button + MOUSE_BUTTON_RIGHT = TU_BIT(1), ///< Right button + MOUSE_BUTTON_MIDDLE = TU_BIT(2), ///< Middle button + MOUSE_BUTTON_BACKWARD = TU_BIT(3), ///< Backward button, + MOUSE_BUTTON_FORWARD = TU_BIT(4), ///< Forward button, +}hid_mouse_button_bm_t; - //--------------------------------------------------------------------+ - // Keyboard - //--------------------------------------------------------------------+ - /** \addtogroup ClassDriver_HID_Keyboard Keyboard - * @{ */ +/// @} - /// Standard HID Boot Protocol Keyboard Report. - typedef struct TU_ATTR_PACKED - { - uint8_t modifier; /**< Keyboard modifier (KEYBOARD_MODIFIER_* masks). */ - uint8_t reserved; /**< Reserved for OEM use, always set to 0. */ - uint8_t keycode[6]; /**< Key codes of the currently pressed keys. */ - } hid_keyboard_report_t; +//--------------------------------------------------------------------+ +// Keyboard +//--------------------------------------------------------------------+ +/** \addtogroup ClassDriver_HID_Keyboard Keyboard + * @{ */ - /// Keyboard modifier codes bitmap - typedef enum - { - KEYBOARD_MODIFIER_LEFTCTRL = TU_BIT(0), ///< Left Control - KEYBOARD_MODIFIER_LEFTSHIFT = TU_BIT(1), ///< Left Shift - KEYBOARD_MODIFIER_LEFTALT = TU_BIT(2), ///< Left Alt - KEYBOARD_MODIFIER_LEFTGUI = TU_BIT(3), ///< Left Window - KEYBOARD_MODIFIER_RIGHTCTRL = TU_BIT(4), ///< Right Control - KEYBOARD_MODIFIER_RIGHTSHIFT = TU_BIT(5), ///< Right Shift - KEYBOARD_MODIFIER_RIGHTALT = TU_BIT(6), ///< Right Alt - KEYBOARD_MODIFIER_RIGHTGUI = TU_BIT(7) ///< Right Window - } hid_keyboard_modifier_bm_t; +/// Standard HID Boot Protocol Keyboard Report. +typedef struct TU_ATTR_PACKED +{ + uint8_t modifier; /**< Keyboard modifier (KEYBOARD_MODIFIER_* masks). */ + uint8_t reserved; /**< Reserved for OEM use, always set to 0. */ + uint8_t keycode[6]; /**< Key codes of the currently pressed keys. */ +} hid_keyboard_report_t; - typedef enum - { - KEYBOARD_LED_NUMLOCK = TU_BIT(0), ///< Num Lock LED - KEYBOARD_LED_CAPSLOCK = TU_BIT(1), ///< Caps Lock LED - KEYBOARD_LED_SCROLLLOCK = TU_BIT(2), ///< Scroll Lock LED - KEYBOARD_LED_COMPOSE = TU_BIT(3), ///< Composition Mode - KEYBOARD_LED_KANA = TU_BIT(4) ///< Kana mode - } hid_keyboard_led_bm_t; +/// Keyboard modifier codes bitmap +typedef enum +{ + KEYBOARD_MODIFIER_LEFTCTRL = TU_BIT(0), ///< Left Control + KEYBOARD_MODIFIER_LEFTSHIFT = TU_BIT(1), ///< Left Shift + KEYBOARD_MODIFIER_LEFTALT = TU_BIT(2), ///< Left Alt + KEYBOARD_MODIFIER_LEFTGUI = TU_BIT(3), ///< Left Window + KEYBOARD_MODIFIER_RIGHTCTRL = TU_BIT(4), ///< Right Control + KEYBOARD_MODIFIER_RIGHTSHIFT = TU_BIT(5), ///< Right Shift + KEYBOARD_MODIFIER_RIGHTALT = TU_BIT(6), ///< Right Alt + KEYBOARD_MODIFIER_RIGHTGUI = TU_BIT(7) ///< Right Window +}hid_keyboard_modifier_bm_t; + +typedef enum +{ + KEYBOARD_LED_NUMLOCK = TU_BIT(0), ///< Num Lock LED + KEYBOARD_LED_CAPSLOCK = TU_BIT(1), ///< Caps Lock LED + KEYBOARD_LED_SCROLLLOCK = TU_BIT(2), ///< Scroll Lock LED + KEYBOARD_LED_COMPOSE = TU_BIT(3), ///< Composition Mode + KEYBOARD_LED_KANA = TU_BIT(4) ///< Kana mode +}hid_keyboard_led_bm_t; /// @} //--------------------------------------------------------------------+ // HID KEYCODE //--------------------------------------------------------------------+ -#define HID_KEY_NONE 0x00 -#define HID_KEY_A 0x04 -#define HID_KEY_B 0x05 -#define HID_KEY_C 0x06 -#define HID_KEY_D 0x07 -#define HID_KEY_E 0x08 -#define HID_KEY_F 0x09 -#define HID_KEY_G 0x0A -#define HID_KEY_H 0x0B -#define HID_KEY_I 0x0C -#define HID_KEY_J 0x0D -#define HID_KEY_K 0x0E -#define HID_KEY_L 0x0F -#define HID_KEY_M 0x10 -#define HID_KEY_N 0x11 -#define HID_KEY_O 0x12 -#define HID_KEY_P 0x13 -#define HID_KEY_Q 0x14 -#define HID_KEY_R 0x15 -#define HID_KEY_S 0x16 -#define HID_KEY_T 0x17 -#define HID_KEY_U 0x18 -#define HID_KEY_V 0x19 -#define HID_KEY_W 0x1A -#define HID_KEY_X 0x1B -#define HID_KEY_Y 0x1C -#define HID_KEY_Z 0x1D -#define HID_KEY_1 0x1E -#define HID_KEY_2 0x1F -#define HID_KEY_3 0x20 -#define HID_KEY_4 0x21 -#define HID_KEY_5 0x22 -#define HID_KEY_6 0x23 -#define HID_KEY_7 0x24 -#define HID_KEY_8 0x25 -#define HID_KEY_9 0x26 -#define HID_KEY_0 0x27 -#define HID_KEY_ENTER 0x28 -#define HID_KEY_ESCAPE 0x29 -#define HID_KEY_BACKSPACE 0x2A -#define HID_KEY_TAB 0x2B -#define HID_KEY_SPACE 0x2C -#define HID_KEY_MINUS 0x2D -#define HID_KEY_EQUAL 0x2E -#define HID_KEY_BRACKET_LEFT 0x2F -#define HID_KEY_BRACKET_RIGHT 0x30 -#define HID_KEY_BACKSLASH 0x31 -#define HID_KEY_EUROPE_1 0x32 -#define HID_KEY_SEMICOLON 0x33 -#define HID_KEY_APOSTROPHE 0x34 -#define HID_KEY_GRAVE 0x35 -#define HID_KEY_COMMA 0x36 -#define HID_KEY_PERIOD 0x37 -#define HID_KEY_SLASH 0x38 -#define HID_KEY_CAPS_LOCK 0x39 -#define HID_KEY_F1 0x3A -#define HID_KEY_F2 0x3B -#define HID_KEY_F3 0x3C -#define HID_KEY_F4 0x3D -#define HID_KEY_F5 0x3E -#define HID_KEY_F6 0x3F -#define HID_KEY_F7 0x40 -#define HID_KEY_F8 0x41 -#define HID_KEY_F9 0x42 -#define HID_KEY_F10 0x43 -#define HID_KEY_F11 0x44 -#define HID_KEY_F12 0x45 -#define HID_KEY_PRINT_SCREEN 0x46 -#define HID_KEY_SCROLL_LOCK 0x47 -#define HID_KEY_PAUSE 0x48 -#define HID_KEY_INSERT 0x49 -#define HID_KEY_HOME 0x4A -#define HID_KEY_PAGE_UP 0x4B -#define HID_KEY_DELETE 0x4C -#define HID_KEY_END 0x4D -#define HID_KEY_PAGE_DOWN 0x4E -#define HID_KEY_ARROW_RIGHT 0x4F -#define HID_KEY_ARROW_LEFT 0x50 -#define HID_KEY_ARROW_DOWN 0x51 -#define HID_KEY_ARROW_UP 0x52 -#define HID_KEY_NUM_LOCK 0x53 -#define HID_KEY_KEYPAD_DIVIDE 0x54 -#define HID_KEY_KEYPAD_MULTIPLY 0x55 -#define HID_KEY_KEYPAD_SUBTRACT 0x56 -#define HID_KEY_KEYPAD_ADD 0x57 -#define HID_KEY_KEYPAD_ENTER 0x58 -#define HID_KEY_KEYPAD_1 0x59 -#define HID_KEY_KEYPAD_2 0x5A -#define HID_KEY_KEYPAD_3 0x5B -#define HID_KEY_KEYPAD_4 0x5C -#define HID_KEY_KEYPAD_5 0x5D -#define HID_KEY_KEYPAD_6 0x5E -#define HID_KEY_KEYPAD_7 0x5F -#define HID_KEY_KEYPAD_8 0x60 -#define HID_KEY_KEYPAD_9 0x61 -#define HID_KEY_KEYPAD_0 0x62 -#define HID_KEY_KEYPAD_DECIMAL 0x63 -#define HID_KEY_EUROPE_2 0x64 -#define HID_KEY_APPLICATION 0x65 -#define HID_KEY_POWER 0x66 -#define HID_KEY_KEYPAD_EQUAL 0x67 -#define HID_KEY_F13 0x68 -#define HID_KEY_F14 0x69 -#define HID_KEY_F15 0x6A -#define HID_KEY_F16 0x6B -#define HID_KEY_F17 0x6C -#define HID_KEY_F18 0x6D -#define HID_KEY_F19 0x6E -#define HID_KEY_F20 0x6F -#define HID_KEY_F21 0x70 -#define HID_KEY_F22 0x71 -#define HID_KEY_F23 0x72 -#define HID_KEY_F24 0x73 -#define HID_KEY_EXECUTE 0x74 -#define HID_KEY_HELP 0x75 -#define HID_KEY_MENU 0x76 -#define HID_KEY_SELECT 0x77 -#define HID_KEY_STOP 0x78 -#define HID_KEY_AGAIN 0x79 -#define HID_KEY_UNDO 0x7A -#define HID_KEY_CUT 0x7B -#define HID_KEY_COPY 0x7C -#define HID_KEY_PASTE 0x7D -#define HID_KEY_FIND 0x7E -#define HID_KEY_MUTE 0x7F -#define HID_KEY_VOLUME_UP 0x80 -#define HID_KEY_VOLUME_DOWN 0x81 -#define HID_KEY_LOCKING_CAPS_LOCK 0x82 -#define HID_KEY_LOCKING_NUM_LOCK 0x83 -#define HID_KEY_LOCKING_SCROLL_LOCK 0x84 -#define HID_KEY_KEYPAD_COMMA 0x85 -#define HID_KEY_KEYPAD_EQUAL_SIGN 0x86 -#define HID_KEY_KANJI1 0x87 -#define HID_KEY_KANJI2 0x88 -#define HID_KEY_KANJI3 0x89 -#define HID_KEY_KANJI4 0x8A -#define HID_KEY_KANJI5 0x8B -#define HID_KEY_KANJI6 0x8C -#define HID_KEY_KANJI7 0x8D -#define HID_KEY_KANJI8 0x8E -#define HID_KEY_KANJI9 0x8F -#define HID_KEY_LANG1 0x90 -#define HID_KEY_LANG2 0x91 -#define HID_KEY_LANG3 0x92 -#define HID_KEY_LANG4 0x93 -#define HID_KEY_LANG5 0x94 -#define HID_KEY_LANG6 0x95 -#define HID_KEY_LANG7 0x96 -#define HID_KEY_LANG8 0x97 -#define HID_KEY_LANG9 0x98 -#define HID_KEY_ALTERNATE_ERASE 0x99 -#define HID_KEY_SYSREQ_ATTENTION 0x9A -#define HID_KEY_CANCEL 0x9B -#define HID_KEY_CLEAR 0x9C -#define HID_KEY_PRIOR 0x9D -#define HID_KEY_RETURN 0x9E -#define HID_KEY_SEPARATOR 0x9F -#define HID_KEY_OUT 0xA0 -#define HID_KEY_OPER 0xA1 -#define HID_KEY_CLEAR_AGAIN 0xA2 -#define HID_KEY_CRSEL_PROPS 0xA3 -#define HID_KEY_EXSEL 0xA4 +#define HID_KEY_NONE 0x00 +#define HID_KEY_A 0x04 +#define HID_KEY_B 0x05 +#define HID_KEY_C 0x06 +#define HID_KEY_D 0x07 +#define HID_KEY_E 0x08 +#define HID_KEY_F 0x09 +#define HID_KEY_G 0x0A +#define HID_KEY_H 0x0B +#define HID_KEY_I 0x0C +#define HID_KEY_J 0x0D +#define HID_KEY_K 0x0E +#define HID_KEY_L 0x0F +#define HID_KEY_M 0x10 +#define HID_KEY_N 0x11 +#define HID_KEY_O 0x12 +#define HID_KEY_P 0x13 +#define HID_KEY_Q 0x14 +#define HID_KEY_R 0x15 +#define HID_KEY_S 0x16 +#define HID_KEY_T 0x17 +#define HID_KEY_U 0x18 +#define HID_KEY_V 0x19 +#define HID_KEY_W 0x1A +#define HID_KEY_X 0x1B +#define HID_KEY_Y 0x1C +#define HID_KEY_Z 0x1D +#define HID_KEY_1 0x1E +#define HID_KEY_2 0x1F +#define HID_KEY_3 0x20 +#define HID_KEY_4 0x21 +#define HID_KEY_5 0x22 +#define HID_KEY_6 0x23 +#define HID_KEY_7 0x24 +#define HID_KEY_8 0x25 +#define HID_KEY_9 0x26 +#define HID_KEY_0 0x27 +#define HID_KEY_ENTER 0x28 +#define HID_KEY_ESCAPE 0x29 +#define HID_KEY_BACKSPACE 0x2A +#define HID_KEY_TAB 0x2B +#define HID_KEY_SPACE 0x2C +#define HID_KEY_MINUS 0x2D +#define HID_KEY_EQUAL 0x2E +#define HID_KEY_BRACKET_LEFT 0x2F +#define HID_KEY_BRACKET_RIGHT 0x30 +#define HID_KEY_BACKSLASH 0x31 +#define HID_KEY_EUROPE_1 0x32 +#define HID_KEY_SEMICOLON 0x33 +#define HID_KEY_APOSTROPHE 0x34 +#define HID_KEY_GRAVE 0x35 +#define HID_KEY_COMMA 0x36 +#define HID_KEY_PERIOD 0x37 +#define HID_KEY_SLASH 0x38 +#define HID_KEY_CAPS_LOCK 0x39 +#define HID_KEY_F1 0x3A +#define HID_KEY_F2 0x3B +#define HID_KEY_F3 0x3C +#define HID_KEY_F4 0x3D +#define HID_KEY_F5 0x3E +#define HID_KEY_F6 0x3F +#define HID_KEY_F7 0x40 +#define HID_KEY_F8 0x41 +#define HID_KEY_F9 0x42 +#define HID_KEY_F10 0x43 +#define HID_KEY_F11 0x44 +#define HID_KEY_F12 0x45 +#define HID_KEY_PRINT_SCREEN 0x46 +#define HID_KEY_SCROLL_LOCK 0x47 +#define HID_KEY_PAUSE 0x48 +#define HID_KEY_INSERT 0x49 +#define HID_KEY_HOME 0x4A +#define HID_KEY_PAGE_UP 0x4B +#define HID_KEY_DELETE 0x4C +#define HID_KEY_END 0x4D +#define HID_KEY_PAGE_DOWN 0x4E +#define HID_KEY_ARROW_RIGHT 0x4F +#define HID_KEY_ARROW_LEFT 0x50 +#define HID_KEY_ARROW_DOWN 0x51 +#define HID_KEY_ARROW_UP 0x52 +#define HID_KEY_NUM_LOCK 0x53 +#define HID_KEY_KEYPAD_DIVIDE 0x54 +#define HID_KEY_KEYPAD_MULTIPLY 0x55 +#define HID_KEY_KEYPAD_SUBTRACT 0x56 +#define HID_KEY_KEYPAD_ADD 0x57 +#define HID_KEY_KEYPAD_ENTER 0x58 +#define HID_KEY_KEYPAD_1 0x59 +#define HID_KEY_KEYPAD_2 0x5A +#define HID_KEY_KEYPAD_3 0x5B +#define HID_KEY_KEYPAD_4 0x5C +#define HID_KEY_KEYPAD_5 0x5D +#define HID_KEY_KEYPAD_6 0x5E +#define HID_KEY_KEYPAD_7 0x5F +#define HID_KEY_KEYPAD_8 0x60 +#define HID_KEY_KEYPAD_9 0x61 +#define HID_KEY_KEYPAD_0 0x62 +#define HID_KEY_KEYPAD_DECIMAL 0x63 +#define HID_KEY_EUROPE_2 0x64 +#define HID_KEY_APPLICATION 0x65 +#define HID_KEY_POWER 0x66 +#define HID_KEY_KEYPAD_EQUAL 0x67 +#define HID_KEY_F13 0x68 +#define HID_KEY_F14 0x69 +#define HID_KEY_F15 0x6A +#define HID_KEY_F16 0x6B +#define HID_KEY_F17 0x6C +#define HID_KEY_F18 0x6D +#define HID_KEY_F19 0x6E +#define HID_KEY_F20 0x6F +#define HID_KEY_F21 0x70 +#define HID_KEY_F22 0x71 +#define HID_KEY_F23 0x72 +#define HID_KEY_F24 0x73 +#define HID_KEY_EXECUTE 0x74 +#define HID_KEY_HELP 0x75 +#define HID_KEY_MENU 0x76 +#define HID_KEY_SELECT 0x77 +#define HID_KEY_STOP 0x78 +#define HID_KEY_AGAIN 0x79 +#define HID_KEY_UNDO 0x7A +#define HID_KEY_CUT 0x7B +#define HID_KEY_COPY 0x7C +#define HID_KEY_PASTE 0x7D +#define HID_KEY_FIND 0x7E +#define HID_KEY_MUTE 0x7F +#define HID_KEY_VOLUME_UP 0x80 +#define HID_KEY_VOLUME_DOWN 0x81 +#define HID_KEY_LOCKING_CAPS_LOCK 0x82 +#define HID_KEY_LOCKING_NUM_LOCK 0x83 +#define HID_KEY_LOCKING_SCROLL_LOCK 0x84 +#define HID_KEY_KEYPAD_COMMA 0x85 +#define HID_KEY_KEYPAD_EQUAL_SIGN 0x86 +#define HID_KEY_KANJI1 0x87 +#define HID_KEY_KANJI2 0x88 +#define HID_KEY_KANJI3 0x89 +#define HID_KEY_KANJI4 0x8A +#define HID_KEY_KANJI5 0x8B +#define HID_KEY_KANJI6 0x8C +#define HID_KEY_KANJI7 0x8D +#define HID_KEY_KANJI8 0x8E +#define HID_KEY_KANJI9 0x8F +#define HID_KEY_LANG1 0x90 +#define HID_KEY_LANG2 0x91 +#define HID_KEY_LANG3 0x92 +#define HID_KEY_LANG4 0x93 +#define HID_KEY_LANG5 0x94 +#define HID_KEY_LANG6 0x95 +#define HID_KEY_LANG7 0x96 +#define HID_KEY_LANG8 0x97 +#define HID_KEY_LANG9 0x98 +#define HID_KEY_ALTERNATE_ERASE 0x99 +#define HID_KEY_SYSREQ_ATTENTION 0x9A +#define HID_KEY_CANCEL 0x9B +#define HID_KEY_CLEAR 0x9C +#define HID_KEY_PRIOR 0x9D +#define HID_KEY_RETURN 0x9E +#define HID_KEY_SEPARATOR 0x9F +#define HID_KEY_OUT 0xA0 +#define HID_KEY_OPER 0xA1 +#define HID_KEY_CLEAR_AGAIN 0xA2 +#define HID_KEY_CRSEL_PROPS 0xA3 +#define HID_KEY_EXSEL 0xA4 // RESERVED 0xA5-DF -#define HID_KEY_CONTROL_LEFT 0xE0 -#define HID_KEY_SHIFT_LEFT 0xE1 -#define HID_KEY_ALT_LEFT 0xE2 -#define HID_KEY_GUI_LEFT 0xE3 -#define HID_KEY_CONTROL_RIGHT 0xE4 -#define HID_KEY_SHIFT_RIGHT 0xE5 -#define HID_KEY_ALT_RIGHT 0xE6 -#define HID_KEY_GUI_RIGHT 0xE7 +#define HID_KEY_CONTROL_LEFT 0xE0 +#define HID_KEY_SHIFT_LEFT 0xE1 +#define HID_KEY_ALT_LEFT 0xE2 +#define HID_KEY_GUI_LEFT 0xE3 +#define HID_KEY_CONTROL_RIGHT 0xE4 +#define HID_KEY_SHIFT_RIGHT 0xE5 +#define HID_KEY_ALT_RIGHT 0xE6 +#define HID_KEY_GUI_RIGHT 0xE7 + //--------------------------------------------------------------------+ // REPORT DESCRIPTOR @@ -1254,269 +1249,267 @@ extern "C" #define HID_REPORT_DATA_3(data) , U32_TO_U8S_LE(data) #define HID_REPORT_ITEM(data, tag, type, size) \ - (((tag) << 4) | ((type) << 2) | (size)) HID_REPORT_DATA_##size(data) + (((tag) << 4) | ((type) << 2) | (size)) HID_REPORT_DATA_##size(data) -#define RI_TYPE_MAIN 0 +#define RI_TYPE_MAIN 0 #define RI_TYPE_GLOBAL 1 -#define RI_TYPE_LOCAL 2 +#define RI_TYPE_LOCAL 2 //------------- MAIN ITEMS 6.2.2.4 -------------// -#define HID_INPUT(x) HID_REPORT_ITEM(x, 8, RI_TYPE_MAIN, 1) -#define HID_OUTPUT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_MAIN, 1) -#define HID_COLLECTION(x) HID_REPORT_ITEM(x, 10, RI_TYPE_MAIN, 1) -#define HID_FEATURE(x) HID_REPORT_ITEM(x, 11, RI_TYPE_MAIN, 1) -#define HID_COLLECTION_END HID_REPORT_ITEM(x, 12, RI_TYPE_MAIN, 0) +#define HID_INPUT(x) HID_REPORT_ITEM(x, 8, RI_TYPE_MAIN, 1) +#define HID_OUTPUT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_MAIN, 1) +#define HID_COLLECTION(x) HID_REPORT_ITEM(x, 10, RI_TYPE_MAIN, 1) +#define HID_FEATURE(x) HID_REPORT_ITEM(x, 11, RI_TYPE_MAIN, 1) +#define HID_COLLECTION_END HID_REPORT_ITEM(x, 12, RI_TYPE_MAIN, 0) //------------- INPUT, OUTPUT, FEATURE 6.2.2.5 -------------// -#define HID_DATA (0 << 0) -#define HID_CONSTANT (1 << 0) +#define HID_DATA (0<<0) +#define HID_CONSTANT (1<<0) -#define HID_ARRAY (0 << 1) -#define HID_VARIABLE (1 << 1) +#define HID_ARRAY (0<<1) +#define HID_VARIABLE (1<<1) -#define HID_ABSOLUTE (0 << 2) -#define HID_RELATIVE (1 << 2) +#define HID_ABSOLUTE (0<<2) +#define HID_RELATIVE (1<<2) -#define HID_WRAP_NO (0 << 3) -#define HID_WRAP (1 << 3) +#define HID_WRAP_NO (0<<3) +#define HID_WRAP (1<<3) -#define HID_LINEAR (0 << 4) -#define HID_NONLINEAR (1 << 4) +#define HID_LINEAR (0<<4) +#define HID_NONLINEAR (1<<4) -#define HID_PREFERRED_STATE (0 << 5) -#define HID_PREFERRED_NO (1 << 5) +#define HID_PREFERRED_STATE (0<<5) +#define HID_PREFERRED_NO (1<<5) -#define HID_NO_NULL_POSITION (0 << 6) -#define HID_NULL_STATE (1 << 6) +#define HID_NO_NULL_POSITION (0<<6) +#define HID_NULL_STATE (1<<6) -#define HID_NON_VOLATILE (0 << 7) -#define HID_VOLATILE (1 << 7) +#define HID_NON_VOLATILE (0<<7) +#define HID_VOLATILE (1<<7) -#define HID_BITFIELD (0 << 8) -#define HID_BUFFERED_BYTES (1 << 8) +#define HID_BITFIELD (0<<8) +#define HID_BUFFERED_BYTES (1<<8) - //------------- COLLECTION ITEM 6.2.2.6 -------------// - enum - { - HID_COLLECTION_PHYSICAL = 0, - HID_COLLECTION_APPLICATION, - HID_COLLECTION_LOGICAL, - HID_COLLECTION_REPORT, - HID_COLLECTION_NAMED_ARRAY, - HID_COLLECTION_USAGE_SWITCH, - HID_COLLECTION_USAGE_MODIFIER - }; +//------------- COLLECTION ITEM 6.2.2.6 -------------// +enum { + HID_COLLECTION_PHYSICAL = 0, + HID_COLLECTION_APPLICATION, + HID_COLLECTION_LOGICAL, + HID_COLLECTION_REPORT, + HID_COLLECTION_NAMED_ARRAY, + HID_COLLECTION_USAGE_SWITCH, + HID_COLLECTION_USAGE_MODIFIER +}; //------------- GLOBAL ITEMS 6.2.2.7 -------------// -#define HID_USAGE_PAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, 1) -#define HID_USAGE_PAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, n) +#define HID_USAGE_PAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, 1) +#define HID_USAGE_PAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_GLOBAL, n) -#define HID_LOGICAL_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, 1) -#define HID_LOGICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, n) +#define HID_LOGICAL_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, 1) +#define HID_LOGICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_GLOBAL, n) -#define HID_LOGICAL_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, 1) -#define HID_LOGICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, n) +#define HID_LOGICAL_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, 1) +#define HID_LOGICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_GLOBAL, n) -#define HID_PHYSICAL_MIN(x) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, 1) -#define HID_PHYSICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, n) +#define HID_PHYSICAL_MIN(x) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, 1) +#define HID_PHYSICAL_MIN_N(x, n) HID_REPORT_ITEM(x, 3, RI_TYPE_GLOBAL, n) -#define HID_PHYSICAL_MAX(x) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, 1) -#define HID_PHYSICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, n) +#define HID_PHYSICAL_MAX(x) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, 1) +#define HID_PHYSICAL_MAX_N(x, n) HID_REPORT_ITEM(x, 4, RI_TYPE_GLOBAL, n) -#define HID_UNIT_EXPONENT(x) HID_REPORT_ITEM(x, 5, RI_TYPE_GLOBAL, 1) +#define HID_UNIT_EXPONENT(x) HID_REPORT_ITEM(x, 5, RI_TYPE_GLOBAL, 1) #define HID_UNIT_EXPONENT_N(x, n) HID_REPORT_ITEM(x, 5, RI_TYPE_GLOBAL, n) -#define HID_UNIT(x) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, 1) -#define HID_UNIT_N(x, n) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, n) +#define HID_UNIT(x) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, 1) +#define HID_UNIT_N(x, n) HID_REPORT_ITEM(x, 6, RI_TYPE_GLOBAL, n) -#define HID_REPORT_SIZE(x) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, 1) -#define HID_REPORT_SIZE_N(x, n) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, n) +#define HID_REPORT_SIZE(x) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, 1) +#define HID_REPORT_SIZE_N(x, n) HID_REPORT_ITEM(x, 7, RI_TYPE_GLOBAL, n) -#define HID_REPORT_ID(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, 1), -#define HID_REPORT_ID_N(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, n), +#define HID_REPORT_ID(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, 1), +#define HID_REPORT_ID_N(x) HID_REPORT_ITEM(x, 8, RI_TYPE_GLOBAL, n), -#define HID_REPORT_COUNT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, 1) -#define HID_REPORT_COUNT_N(x, n) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, n) +#define HID_REPORT_COUNT(x) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, 1) +#define HID_REPORT_COUNT_N(x, n) HID_REPORT_ITEM(x, 9, RI_TYPE_GLOBAL, n) -#define HID_PUSH HID_REPORT_ITEM(x, 10, RI_TYPE_GLOBAL, 0) -#define HID_POP HID_REPORT_ITEM(x, 11, RI_TYPE_GLOBAL, 0) +#define HID_PUSH HID_REPORT_ITEM(x, 10, RI_TYPE_GLOBAL, 0) +#define HID_POP HID_REPORT_ITEM(x, 11, RI_TYPE_GLOBAL, 0) //------------- LOCAL ITEMS 6.2.2.8 -------------// -#define HID_USAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, 1) -#define HID_USAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, n) +#define HID_USAGE(x) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, 1) +#define HID_USAGE_N(x, n) HID_REPORT_ITEM(x, 0, RI_TYPE_LOCAL, n) -#define HID_USAGE_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, 1) -#define HID_USAGE_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, n) +#define HID_USAGE_MIN(x) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, 1) +#define HID_USAGE_MIN_N(x, n) HID_REPORT_ITEM(x, 1, RI_TYPE_LOCAL, n) -#define HID_USAGE_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, 1) -#define HID_USAGE_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, n) +#define HID_USAGE_MAX(x) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, 1) +#define HID_USAGE_MAX_N(x, n) HID_REPORT_ITEM(x, 2, RI_TYPE_LOCAL, n) - //--------------------------------------------------------------------+ - // Usage Table - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Usage Table +//--------------------------------------------------------------------+ - /// HID Usage Table - Table 1: Usage Page Summary - enum - { - HID_USAGE_PAGE_DESKTOP = 0x01, - HID_USAGE_PAGE_SIMULATE = 0x02, - HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03, - HID_USAGE_PAGE_SPORT = 0x04, - HID_USAGE_PAGE_GAME = 0x05, - HID_USAGE_PAGE_GENERIC_DEVICE = 0x06, - HID_USAGE_PAGE_KEYBOARD = 0x07, - HID_USAGE_PAGE_LED = 0x08, - HID_USAGE_PAGE_BUTTON = 0x09, - HID_USAGE_PAGE_ORDINAL = 0x0a, - HID_USAGE_PAGE_TELEPHONY = 0x0b, - HID_USAGE_PAGE_CONSUMER = 0x0c, - HID_USAGE_PAGE_DIGITIZER = 0x0d, - HID_USAGE_PAGE_PID = 0x0f, - HID_USAGE_PAGE_UNICODE = 0x10, - HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14, - HID_USAGE_PAGE_MEDICAL = 0x40, - HID_USAGE_PAGE_MONITOR = 0x80, // 0x80 - 0x83 - HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87 - HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c, - HID_USAGE_PAGE_SCALE = 0x8d, - HID_USAGE_PAGE_MSR = 0x8e, - HID_USAGE_PAGE_CAMERA = 0x90, - HID_USAGE_PAGE_ARCADE = 0x91, - HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF - }; +/// HID Usage Table - Table 1: Usage Page Summary +enum { + HID_USAGE_PAGE_DESKTOP = 0x01, + HID_USAGE_PAGE_SIMULATE = 0x02, + HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03, + HID_USAGE_PAGE_SPORT = 0x04, + HID_USAGE_PAGE_GAME = 0x05, + HID_USAGE_PAGE_GENERIC_DEVICE = 0x06, + HID_USAGE_PAGE_KEYBOARD = 0x07, + HID_USAGE_PAGE_LED = 0x08, + HID_USAGE_PAGE_BUTTON = 0x09, + HID_USAGE_PAGE_ORDINAL = 0x0a, + HID_USAGE_PAGE_TELEPHONY = 0x0b, + HID_USAGE_PAGE_CONSUMER = 0x0c, + HID_USAGE_PAGE_DIGITIZER = 0x0d, + HID_USAGE_PAGE_PID = 0x0f, + HID_USAGE_PAGE_UNICODE = 0x10, + HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14, + HID_USAGE_PAGE_MEDICAL = 0x40, + HID_USAGE_PAGE_MONITOR = 0x80, //0x80 - 0x83 + HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87 + HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c, + HID_USAGE_PAGE_SCALE = 0x8d, + HID_USAGE_PAGE_MSR = 0x8e, + HID_USAGE_PAGE_CAMERA = 0x90, + HID_USAGE_PAGE_ARCADE = 0x91, + HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF +}; - /// HID Usage Table - Table 6: Generic Desktop Page - enum - { - HID_USAGE_DESKTOP_POINTER = 0x01, - HID_USAGE_DESKTOP_MOUSE = 0x02, - HID_USAGE_DESKTOP_JOYSTICK = 0x04, - HID_USAGE_DESKTOP_GAMEPAD = 0x05, - HID_USAGE_DESKTOP_KEYBOARD = 0x06, - HID_USAGE_DESKTOP_KEYPAD = 0x07, - HID_USAGE_DESKTOP_MULTI_AXIS_CONTROLLER = 0x08, - HID_USAGE_DESKTOP_TABLET_PC_SYSTEM = 0x09, - HID_USAGE_DESKTOP_X = 0x30, - HID_USAGE_DESKTOP_Y = 0x31, - HID_USAGE_DESKTOP_Z = 0x32, - HID_USAGE_DESKTOP_RX = 0x33, - HID_USAGE_DESKTOP_RY = 0x34, - HID_USAGE_DESKTOP_RZ = 0x35, - HID_USAGE_DESKTOP_SLIDER = 0x36, - HID_USAGE_DESKTOP_DIAL = 0x37, - HID_USAGE_DESKTOP_WHEEL = 0x38, - HID_USAGE_DESKTOP_HAT_SWITCH = 0x39, - HID_USAGE_DESKTOP_COUNTED_BUFFER = 0x3a, - HID_USAGE_DESKTOP_BYTE_COUNT = 0x3b, - HID_USAGE_DESKTOP_MOTION_WAKEUP = 0x3c, - HID_USAGE_DESKTOP_START = 0x3d, - HID_USAGE_DESKTOP_SELECT = 0x3e, - HID_USAGE_DESKTOP_VX = 0x40, - HID_USAGE_DESKTOP_VY = 0x41, - HID_USAGE_DESKTOP_VZ = 0x42, - HID_USAGE_DESKTOP_VBRX = 0x43, - HID_USAGE_DESKTOP_VBRY = 0x44, - HID_USAGE_DESKTOP_VBRZ = 0x45, - HID_USAGE_DESKTOP_VNO = 0x46, - HID_USAGE_DESKTOP_FEATURE_NOTIFICATION = 0x47, - HID_USAGE_DESKTOP_RESOLUTION_MULTIPLIER = 0x48, - HID_USAGE_DESKTOP_SYSTEM_CONTROL = 0x80, - HID_USAGE_DESKTOP_SYSTEM_POWER_DOWN = 0x81, - HID_USAGE_DESKTOP_SYSTEM_SLEEP = 0x82, - HID_USAGE_DESKTOP_SYSTEM_WAKE_UP = 0x83, - HID_USAGE_DESKTOP_SYSTEM_CONTEXT_MENU = 0x84, - HID_USAGE_DESKTOP_SYSTEM_MAIN_MENU = 0x85, - HID_USAGE_DESKTOP_SYSTEM_APP_MENU = 0x86, - HID_USAGE_DESKTOP_SYSTEM_MENU_HELP = 0x87, - HID_USAGE_DESKTOP_SYSTEM_MENU_EXIT = 0x88, - HID_USAGE_DESKTOP_SYSTEM_MENU_SELECT = 0x89, - HID_USAGE_DESKTOP_SYSTEM_MENU_RIGHT = 0x8A, - HID_USAGE_DESKTOP_SYSTEM_MENU_LEFT = 0x8B, - HID_USAGE_DESKTOP_SYSTEM_MENU_UP = 0x8C, - HID_USAGE_DESKTOP_SYSTEM_MENU_DOWN = 0x8D, - HID_USAGE_DESKTOP_SYSTEM_COLD_RESTART = 0x8E, - HID_USAGE_DESKTOP_SYSTEM_WARM_RESTART = 0x8F, - HID_USAGE_DESKTOP_DPAD_UP = 0x90, - HID_USAGE_DESKTOP_DPAD_DOWN = 0x91, - HID_USAGE_DESKTOP_DPAD_RIGHT = 0x92, - HID_USAGE_DESKTOP_DPAD_LEFT = 0x93, - HID_USAGE_DESKTOP_SYSTEM_DOCK = 0xA0, - HID_USAGE_DESKTOP_SYSTEM_UNDOCK = 0xA1, - HID_USAGE_DESKTOP_SYSTEM_SETUP = 0xA2, - HID_USAGE_DESKTOP_SYSTEM_BREAK = 0xA3, - HID_USAGE_DESKTOP_SYSTEM_DEBUGGER_BREAK = 0xA4, - HID_USAGE_DESKTOP_APPLICATION_BREAK = 0xA5, - HID_USAGE_DESKTOP_APPLICATION_DEBUGGER_BREAK = 0xA6, - HID_USAGE_DESKTOP_SYSTEM_SPEAKER_MUTE = 0xA7, - HID_USAGE_DESKTOP_SYSTEM_HIBERNATE = 0xA8, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INVERT = 0xB0, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INTERNAL = 0xB1, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_EXTERNAL = 0xB2, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_BOTH = 0xB3, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_DUAL = 0xB4, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_TOGGLE_INT_EXT = 0xB5, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_SWAP_PRIMARY_SECONDARY = 0xB6, - HID_USAGE_DESKTOP_SYSTEM_DISPLAY_LCD_AUTOSCALE = 0xB7 - }; +/// HID Usage Table - Table 6: Generic Desktop Page +enum { + HID_USAGE_DESKTOP_POINTER = 0x01, + HID_USAGE_DESKTOP_MOUSE = 0x02, + HID_USAGE_DESKTOP_JOYSTICK = 0x04, + HID_USAGE_DESKTOP_GAMEPAD = 0x05, + HID_USAGE_DESKTOP_KEYBOARD = 0x06, + HID_USAGE_DESKTOP_KEYPAD = 0x07, + HID_USAGE_DESKTOP_MULTI_AXIS_CONTROLLER = 0x08, + HID_USAGE_DESKTOP_TABLET_PC_SYSTEM = 0x09, + HID_USAGE_DESKTOP_X = 0x30, + HID_USAGE_DESKTOP_Y = 0x31, + HID_USAGE_DESKTOP_Z = 0x32, + HID_USAGE_DESKTOP_RX = 0x33, + HID_USAGE_DESKTOP_RY = 0x34, + HID_USAGE_DESKTOP_RZ = 0x35, + HID_USAGE_DESKTOP_SLIDER = 0x36, + HID_USAGE_DESKTOP_DIAL = 0x37, + HID_USAGE_DESKTOP_WHEEL = 0x38, + HID_USAGE_DESKTOP_HAT_SWITCH = 0x39, + HID_USAGE_DESKTOP_COUNTED_BUFFER = 0x3a, + HID_USAGE_DESKTOP_BYTE_COUNT = 0x3b, + HID_USAGE_DESKTOP_MOTION_WAKEUP = 0x3c, + HID_USAGE_DESKTOP_START = 0x3d, + HID_USAGE_DESKTOP_SELECT = 0x3e, + HID_USAGE_DESKTOP_VX = 0x40, + HID_USAGE_DESKTOP_VY = 0x41, + HID_USAGE_DESKTOP_VZ = 0x42, + HID_USAGE_DESKTOP_VBRX = 0x43, + HID_USAGE_DESKTOP_VBRY = 0x44, + HID_USAGE_DESKTOP_VBRZ = 0x45, + HID_USAGE_DESKTOP_VNO = 0x46, + HID_USAGE_DESKTOP_FEATURE_NOTIFICATION = 0x47, + HID_USAGE_DESKTOP_RESOLUTION_MULTIPLIER = 0x48, + HID_USAGE_DESKTOP_SYSTEM_CONTROL = 0x80, + HID_USAGE_DESKTOP_SYSTEM_POWER_DOWN = 0x81, + HID_USAGE_DESKTOP_SYSTEM_SLEEP = 0x82, + HID_USAGE_DESKTOP_SYSTEM_WAKE_UP = 0x83, + HID_USAGE_DESKTOP_SYSTEM_CONTEXT_MENU = 0x84, + HID_USAGE_DESKTOP_SYSTEM_MAIN_MENU = 0x85, + HID_USAGE_DESKTOP_SYSTEM_APP_MENU = 0x86, + HID_USAGE_DESKTOP_SYSTEM_MENU_HELP = 0x87, + HID_USAGE_DESKTOP_SYSTEM_MENU_EXIT = 0x88, + HID_USAGE_DESKTOP_SYSTEM_MENU_SELECT = 0x89, + HID_USAGE_DESKTOP_SYSTEM_MENU_RIGHT = 0x8A, + HID_USAGE_DESKTOP_SYSTEM_MENU_LEFT = 0x8B, + HID_USAGE_DESKTOP_SYSTEM_MENU_UP = 0x8C, + HID_USAGE_DESKTOP_SYSTEM_MENU_DOWN = 0x8D, + HID_USAGE_DESKTOP_SYSTEM_COLD_RESTART = 0x8E, + HID_USAGE_DESKTOP_SYSTEM_WARM_RESTART = 0x8F, + HID_USAGE_DESKTOP_DPAD_UP = 0x90, + HID_USAGE_DESKTOP_DPAD_DOWN = 0x91, + HID_USAGE_DESKTOP_DPAD_RIGHT = 0x92, + HID_USAGE_DESKTOP_DPAD_LEFT = 0x93, + HID_USAGE_DESKTOP_SYSTEM_DOCK = 0xA0, + HID_USAGE_DESKTOP_SYSTEM_UNDOCK = 0xA1, + HID_USAGE_DESKTOP_SYSTEM_SETUP = 0xA2, + HID_USAGE_DESKTOP_SYSTEM_BREAK = 0xA3, + HID_USAGE_DESKTOP_SYSTEM_DEBUGGER_BREAK = 0xA4, + HID_USAGE_DESKTOP_APPLICATION_BREAK = 0xA5, + HID_USAGE_DESKTOP_APPLICATION_DEBUGGER_BREAK = 0xA6, + HID_USAGE_DESKTOP_SYSTEM_SPEAKER_MUTE = 0xA7, + HID_USAGE_DESKTOP_SYSTEM_HIBERNATE = 0xA8, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INVERT = 0xB0, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_INTERNAL = 0xB1, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_EXTERNAL = 0xB2, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_BOTH = 0xB3, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_DUAL = 0xB4, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_TOGGLE_INT_EXT = 0xB5, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_SWAP_PRIMARY_SECONDARY = 0xB6, + HID_USAGE_DESKTOP_SYSTEM_DISPLAY_LCD_AUTOSCALE = 0xB7 +}; - /// HID Usage Table: Consumer Page (0x0C) - /// Only contains controls that supported by Windows (whole list is too long) - enum - { - // Generic Control - HID_USAGE_CONSUMER_CONTROL = 0x0001, - // Power Control - HID_USAGE_CONSUMER_POWER = 0x0030, - HID_USAGE_CONSUMER_RESET = 0x0031, - HID_USAGE_CONSUMER_SLEEP = 0x0032, +/// HID Usage Table: Consumer Page (0x0C) +/// Only contains controls that supported by Windows (whole list is too long) +enum +{ + // Generic Control + HID_USAGE_CONSUMER_CONTROL = 0x0001, - // Screen Brightness - HID_USAGE_CONSUMER_BRIGHTNESS_INCREMENT = 0x006F, - HID_USAGE_CONSUMER_BRIGHTNESS_DECREMENT = 0x0070, + // Power Control + HID_USAGE_CONSUMER_POWER = 0x0030, + HID_USAGE_CONSUMER_RESET = 0x0031, + HID_USAGE_CONSUMER_SLEEP = 0x0032, - // These HID usages operate only on mobile systems (battery powered) and - // require Windows 8 (build 8302 or greater). - HID_USAGE_CONSUMER_WIRELESS_RADIO_CONTROLS = 0x000C, - HID_USAGE_CONSUMER_WIRELESS_RADIO_BUTTONS = 0x00C6, - HID_USAGE_CONSUMER_WIRELESS_RADIO_LED = 0x00C7, - HID_USAGE_CONSUMER_WIRELESS_RADIO_SLIDER_SWITCH = 0x00C8, + // Screen Brightness + HID_USAGE_CONSUMER_BRIGHTNESS_INCREMENT = 0x006F, + HID_USAGE_CONSUMER_BRIGHTNESS_DECREMENT = 0x0070, - // Media Control - HID_USAGE_CONSUMER_PLAY_PAUSE = 0x00CD, - HID_USAGE_CONSUMER_SCAN_NEXT = 0x00B5, - HID_USAGE_CONSUMER_SCAN_PREVIOUS = 0x00B6, - HID_USAGE_CONSUMER_STOP = 0x00B7, - HID_USAGE_CONSUMER_VOLUME = 0x00E0, - HID_USAGE_CONSUMER_MUTE = 0x00E2, - HID_USAGE_CONSUMER_BASS = 0x00E3, - HID_USAGE_CONSUMER_TREBLE = 0x00E4, - HID_USAGE_CONSUMER_BASS_BOOST = 0x00E5, - HID_USAGE_CONSUMER_VOLUME_INCREMENT = 0x00E9, - HID_USAGE_CONSUMER_VOLUME_DECREMENT = 0x00EA, - HID_USAGE_CONSUMER_BASS_INCREMENT = 0x0152, - HID_USAGE_CONSUMER_BASS_DECREMENT = 0x0153, - HID_USAGE_CONSUMER_TREBLE_INCREMENT = 0x0154, - HID_USAGE_CONSUMER_TREBLE_DECREMENT = 0x0155, + // These HID usages operate only on mobile systems (battery powered) and + // require Windows 8 (build 8302 or greater). + HID_USAGE_CONSUMER_WIRELESS_RADIO_CONTROLS = 0x000C, + HID_USAGE_CONSUMER_WIRELESS_RADIO_BUTTONS = 0x00C6, + HID_USAGE_CONSUMER_WIRELESS_RADIO_LED = 0x00C7, + HID_USAGE_CONSUMER_WIRELESS_RADIO_SLIDER_SWITCH = 0x00C8, - // Application Launcher - HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL_CONFIGURATION = 0x0183, - HID_USAGE_CONSUMER_AL_EMAIL_READER = 0x018A, - HID_USAGE_CONSUMER_AL_CALCULATOR = 0x0192, - HID_USAGE_CONSUMER_AL_LOCAL_BROWSER = 0x0194, + // Media Control + HID_USAGE_CONSUMER_PLAY_PAUSE = 0x00CD, + HID_USAGE_CONSUMER_SCAN_NEXT = 0x00B5, + HID_USAGE_CONSUMER_SCAN_PREVIOUS = 0x00B6, + HID_USAGE_CONSUMER_STOP = 0x00B7, + HID_USAGE_CONSUMER_VOLUME = 0x00E0, + HID_USAGE_CONSUMER_MUTE = 0x00E2, + HID_USAGE_CONSUMER_BASS = 0x00E3, + HID_USAGE_CONSUMER_TREBLE = 0x00E4, + HID_USAGE_CONSUMER_BASS_BOOST = 0x00E5, + HID_USAGE_CONSUMER_VOLUME_INCREMENT = 0x00E9, + HID_USAGE_CONSUMER_VOLUME_DECREMENT = 0x00EA, + HID_USAGE_CONSUMER_BASS_INCREMENT = 0x0152, + HID_USAGE_CONSUMER_BASS_DECREMENT = 0x0153, + HID_USAGE_CONSUMER_TREBLE_INCREMENT = 0x0154, + HID_USAGE_CONSUMER_TREBLE_DECREMENT = 0x0155, - // Browser/Explorer Specific - HID_USAGE_CONSUMER_AC_SEARCH = 0x0221, - HID_USAGE_CONSUMER_AC_HOME = 0x0223, - HID_USAGE_CONSUMER_AC_BACK = 0x0224, - HID_USAGE_CONSUMER_AC_FORWARD = 0x0225, - HID_USAGE_CONSUMER_AC_STOP = 0x0226, - HID_USAGE_CONSUMER_AC_REFRESH = 0x0227, - HID_USAGE_CONSUMER_AC_BOOKMARKS = 0x022A, + // Application Launcher + HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL_CONFIGURATION = 0x0183, + HID_USAGE_CONSUMER_AL_EMAIL_READER = 0x018A, + HID_USAGE_CONSUMER_AL_CALCULATOR = 0x0192, + HID_USAGE_CONSUMER_AL_LOCAL_BROWSER = 0x0194, - // Mouse Horizontal scroll - HID_USAGE_CONSUMER_AC_PAN = 0x0238, - }; + // Browser/Explorer Specific + HID_USAGE_CONSUMER_AC_SEARCH = 0x0221, + HID_USAGE_CONSUMER_AC_HOME = 0x0223, + HID_USAGE_CONSUMER_AC_BACK = 0x0224, + HID_USAGE_CONSUMER_AC_FORWARD = 0x0225, + HID_USAGE_CONSUMER_AC_STOP = 0x0226, + HID_USAGE_CONSUMER_AC_REFRESH = 0x0227, + HID_USAGE_CONSUMER_AC_BOOKMARKS = 0x022A, + + // Mouse Horizontal scroll + HID_USAGE_CONSUMER_AC_PAN = 0x0238, +}; /*-------------------------------------------------------------------- * ASCII to KEYCODE Conversion @@ -1534,140 +1527,138 @@ extern "C" * tud_hid_keyboard_report(report_id, modifier, keycode); * *--------------------------------------------------------------------*/ -#define HID_ASCII_TO_KEYCODE \ - {0, 0}, /* 0x00 Null */ \ - {0, 0}, /* 0x01 */ \ - {0, 0}, /* 0x02 */ \ - {0, 0}, /* 0x03 */ \ - {0, 0}, /* 0x04 */ \ - {0, 0}, /* 0x05 */ \ - {0, 0}, /* 0x06 */ \ - {0, 0}, /* 0x07 */ \ - {0, HID_KEY_BACKSPACE}, /* 0x08 Backspace */ \ - {0, HID_KEY_TAB}, /* 0x09 Tab */ \ - {0, HID_KEY_RETURN}, /* 0x0A Line Feed */ \ - {0, 0}, /* 0x0B */ \ - {0, 0}, /* 0x0C */ \ - {0, HID_KEY_RETURN}, /* 0x0D CR */ \ - {0, 0}, /* 0x0E */ \ - {0, 0}, /* 0x0F */ \ - {0, 0}, /* 0x10 */ \ - {0, 0}, /* 0x11 */ \ - {0, 0}, /* 0x12 */ \ - {0, 0}, /* 0x13 */ \ - {0, 0}, /* 0x14 */ \ - {0, 0}, /* 0x15 */ \ - {0, 0}, /* 0x16 */ \ - {0, 0}, /* 0x17 */ \ - {0, 0}, /* 0x18 */ \ - {0, 0}, /* 0x19 */ \ - {0, 0}, /* 0x1A */ \ - {0, HID_KEY_ESCAPE}, /* 0x1B Escape */ \ - {0, 0}, /* 0x1C */ \ - {0, 0}, /* 0x1D */ \ - {0, 0}, /* 0x1E */ \ - {0, 0}, /* 0x1F */ \ - \ - {0, HID_KEY_SPACE}, /* 0x20 */ \ - {1, HID_KEY_1}, /* 0x21 ! */ \ - {1, HID_KEY_APOSTROPHE}, /* 0x22 " */ \ - {1, HID_KEY_3}, /* 0x23 # */ \ - {1, HID_KEY_4}, /* 0x24 $ */ \ - {1, HID_KEY_5}, /* 0x25 % */ \ - {1, HID_KEY_7}, /* 0x26 & */ \ - {0, HID_KEY_APOSTROPHE}, /* 0x27 ' */ \ - {1, HID_KEY_9}, /* 0x28 ( */ \ - {1, HID_KEY_0}, /* 0x29 ) */ \ - {1, HID_KEY_8}, /* 0x2A * */ \ - {1, HID_KEY_EQUAL}, /* 0x2B + */ \ - {0, HID_KEY_COMMA}, /* 0x2C , */ \ - {0, HID_KEY_MINUS}, /* 0x2D - */ \ - {0, HID_KEY_PERIOD}, /* 0x2E . */ \ - {0, HID_KEY_SLASH}, /* 0x2F / */ \ - {0, HID_KEY_0}, /* 0x30 0 */ \ - {0, HID_KEY_1}, /* 0x31 1 */ \ - {0, HID_KEY_2}, /* 0x32 2 */ \ - {0, HID_KEY_3}, /* 0x33 3 */ \ - {0, HID_KEY_4}, /* 0x34 4 */ \ - {0, HID_KEY_5}, /* 0x35 5 */ \ - {0, HID_KEY_6}, /* 0x36 6 */ \ - {0, HID_KEY_7}, /* 0x37 7 */ \ - {0, HID_KEY_8}, /* 0x38 8 */ \ - {0, HID_KEY_9}, /* 0x39 9 */ \ - {1, HID_KEY_SEMICOLON}, /* 0x3A : */ \ - {0, HID_KEY_SEMICOLON}, /* 0x3B ; */ \ - {1, HID_KEY_COMMA}, /* 0x3C < */ \ - {0, HID_KEY_EQUAL}, /* 0x3D = */ \ - {1, HID_KEY_PERIOD}, /* 0x3E > */ \ - {1, HID_KEY_SLASH}, /* 0x3F ? */ \ - \ - {1, HID_KEY_2}, /* 0x40 @ */ \ - {1, HID_KEY_A}, /* 0x41 A */ \ - {1, HID_KEY_B}, /* 0x42 B */ \ - {1, HID_KEY_C}, /* 0x43 C */ \ - {1, HID_KEY_D}, /* 0x44 D */ \ - {1, HID_KEY_E}, /* 0x45 E */ \ - {1, HID_KEY_F}, /* 0x46 F */ \ - {1, HID_KEY_G}, /* 0x47 G */ \ - {1, HID_KEY_H}, /* 0x48 H */ \ - {1, HID_KEY_I}, /* 0x49 I */ \ - {1, HID_KEY_J}, /* 0x4A J */ \ - {1, HID_KEY_K}, /* 0x4B K */ \ - {1, HID_KEY_L}, /* 0x4C L */ \ - {1, HID_KEY_M}, /* 0x4D M */ \ - {1, HID_KEY_N}, /* 0x4E N */ \ - {1, HID_KEY_O}, /* 0x4F O */ \ - {1, HID_KEY_P}, /* 0x50 P */ \ - {1, HID_KEY_Q}, /* 0x51 Q */ \ - {1, HID_KEY_R}, /* 0x52 R */ \ - {1, HID_KEY_S}, /* 0x53 S */ \ - {1, HID_KEY_T}, /* 0x55 T */ \ - {1, HID_KEY_U}, /* 0x55 U */ \ - {1, HID_KEY_V}, /* 0x56 V */ \ - {1, HID_KEY_W}, /* 0x57 W */ \ - {1, HID_KEY_X}, /* 0x58 X */ \ - {1, HID_KEY_Y}, /* 0x59 Y */ \ - {1, HID_KEY_Z}, /* 0x5A Z */ \ - {0, HID_KEY_BRACKET_LEFT}, /* 0x5B [ */ \ - {0, HID_KEY_BACKSLASH}, /* 0x5C '\' */ \ - {0, HID_KEY_BRACKET_RIGHT}, /* 0x5D ] */ \ - {1, HID_KEY_6}, /* 0x5E ^ */ \ - {1, HID_KEY_MINUS}, /* 0x5F _ */ \ - \ - {0, HID_KEY_GRAVE}, /* 0x60 ` */ \ - {0, HID_KEY_A}, /* 0x61 a */ \ - {0, HID_KEY_B}, /* 0x62 b */ \ - {0, HID_KEY_C}, /* 0x63 c */ \ - {0, HID_KEY_D}, /* 0x66 d */ \ - {0, HID_KEY_E}, /* 0x65 e */ \ - {0, HID_KEY_F}, /* 0x66 f */ \ - {0, HID_KEY_G}, /* 0x67 g */ \ - {0, HID_KEY_H}, /* 0x68 h */ \ - {0, HID_KEY_I}, /* 0x69 i */ \ - {0, HID_KEY_J}, /* 0x6A j */ \ - {0, HID_KEY_K}, /* 0x6B k */ \ - {0, HID_KEY_L}, /* 0x6C l */ \ - {0, HID_KEY_M}, /* 0x6D m */ \ - {0, HID_KEY_N}, /* 0x6E n */ \ - {0, HID_KEY_O}, /* 0x6F o */ \ - {0, HID_KEY_P}, /* 0x70 p */ \ - {0, HID_KEY_Q}, /* 0x71 q */ \ - {0, HID_KEY_R}, /* 0x72 r */ \ - {0, HID_KEY_S}, /* 0x73 s */ \ - {0, HID_KEY_T}, /* 0x75 t */ \ - {0, HID_KEY_U}, /* 0x75 u */ \ - {0, HID_KEY_V}, /* 0x76 v */ \ - {0, HID_KEY_W}, /* 0x77 w */ \ - {0, HID_KEY_X}, /* 0x78 x */ \ - {0, HID_KEY_Y}, /* 0x79 y */ \ - {0, HID_KEY_Z}, /* 0x7A z */ \ - {1, HID_KEY_BRACKET_LEFT}, /* 0x7B { */ \ - {1, HID_KEY_BACKSLASH}, /* 0x7C | */ \ - {1, HID_KEY_BRACKET_RIGHT}, /* 0x7D } */ \ - {1, HID_KEY_GRAVE}, /* 0x7E ~ */ \ - { \ - 0, HID_KEY_DELETE \ - } /* 0x7F Delete */ +#define HID_ASCII_TO_KEYCODE \ + {0, 0 }, /* 0x00 Null */ \ + {0, 0 }, /* 0x01 */ \ + {0, 0 }, /* 0x02 */ \ + {0, 0 }, /* 0x03 */ \ + {0, 0 }, /* 0x04 */ \ + {0, 0 }, /* 0x05 */ \ + {0, 0 }, /* 0x06 */ \ + {0, 0 }, /* 0x07 */ \ + {0, HID_KEY_BACKSPACE }, /* 0x08 Backspace */ \ + {0, HID_KEY_TAB }, /* 0x09 Tab */ \ + {0, HID_KEY_RETURN }, /* 0x0A Line Feed */ \ + {0, 0 }, /* 0x0B */ \ + {0, 0 }, /* 0x0C */ \ + {0, HID_KEY_RETURN }, /* 0x0D CR */ \ + {0, 0 }, /* 0x0E */ \ + {0, 0 }, /* 0x0F */ \ + {0, 0 }, /* 0x10 */ \ + {0, 0 }, /* 0x11 */ \ + {0, 0 }, /* 0x12 */ \ + {0, 0 }, /* 0x13 */ \ + {0, 0 }, /* 0x14 */ \ + {0, 0 }, /* 0x15 */ \ + {0, 0 }, /* 0x16 */ \ + {0, 0 }, /* 0x17 */ \ + {0, 0 }, /* 0x18 */ \ + {0, 0 }, /* 0x19 */ \ + {0, 0 }, /* 0x1A */ \ + {0, HID_KEY_ESCAPE }, /* 0x1B Escape */ \ + {0, 0 }, /* 0x1C */ \ + {0, 0 }, /* 0x1D */ \ + {0, 0 }, /* 0x1E */ \ + {0, 0 }, /* 0x1F */ \ + \ + {0, HID_KEY_SPACE }, /* 0x20 */ \ + {1, HID_KEY_1 }, /* 0x21 ! */ \ + {1, HID_KEY_APOSTROPHE }, /* 0x22 " */ \ + {1, HID_KEY_3 }, /* 0x23 # */ \ + {1, HID_KEY_4 }, /* 0x24 $ */ \ + {1, HID_KEY_5 }, /* 0x25 % */ \ + {1, HID_KEY_7 }, /* 0x26 & */ \ + {0, HID_KEY_APOSTROPHE }, /* 0x27 ' */ \ + {1, HID_KEY_9 }, /* 0x28 ( */ \ + {1, HID_KEY_0 }, /* 0x29 ) */ \ + {1, HID_KEY_8 }, /* 0x2A * */ \ + {1, HID_KEY_EQUAL }, /* 0x2B + */ \ + {0, HID_KEY_COMMA }, /* 0x2C , */ \ + {0, HID_KEY_MINUS }, /* 0x2D - */ \ + {0, HID_KEY_PERIOD }, /* 0x2E . */ \ + {0, HID_KEY_SLASH }, /* 0x2F / */ \ + {0, HID_KEY_0 }, /* 0x30 0 */ \ + {0, HID_KEY_1 }, /* 0x31 1 */ \ + {0, HID_KEY_2 }, /* 0x32 2 */ \ + {0, HID_KEY_3 }, /* 0x33 3 */ \ + {0, HID_KEY_4 }, /* 0x34 4 */ \ + {0, HID_KEY_5 }, /* 0x35 5 */ \ + {0, HID_KEY_6 }, /* 0x36 6 */ \ + {0, HID_KEY_7 }, /* 0x37 7 */ \ + {0, HID_KEY_8 }, /* 0x38 8 */ \ + {0, HID_KEY_9 }, /* 0x39 9 */ \ + {1, HID_KEY_SEMICOLON }, /* 0x3A : */ \ + {0, HID_KEY_SEMICOLON }, /* 0x3B ; */ \ + {1, HID_KEY_COMMA }, /* 0x3C < */ \ + {0, HID_KEY_EQUAL }, /* 0x3D = */ \ + {1, HID_KEY_PERIOD }, /* 0x3E > */ \ + {1, HID_KEY_SLASH }, /* 0x3F ? */ \ + \ + {1, HID_KEY_2 }, /* 0x40 @ */ \ + {1, HID_KEY_A }, /* 0x41 A */ \ + {1, HID_KEY_B }, /* 0x42 B */ \ + {1, HID_KEY_C }, /* 0x43 C */ \ + {1, HID_KEY_D }, /* 0x44 D */ \ + {1, HID_KEY_E }, /* 0x45 E */ \ + {1, HID_KEY_F }, /* 0x46 F */ \ + {1, HID_KEY_G }, /* 0x47 G */ \ + {1, HID_KEY_H }, /* 0x48 H */ \ + {1, HID_KEY_I }, /* 0x49 I */ \ + {1, HID_KEY_J }, /* 0x4A J */ \ + {1, HID_KEY_K }, /* 0x4B K */ \ + {1, HID_KEY_L }, /* 0x4C L */ \ + {1, HID_KEY_M }, /* 0x4D M */ \ + {1, HID_KEY_N }, /* 0x4E N */ \ + {1, HID_KEY_O }, /* 0x4F O */ \ + {1, HID_KEY_P }, /* 0x50 P */ \ + {1, HID_KEY_Q }, /* 0x51 Q */ \ + {1, HID_KEY_R }, /* 0x52 R */ \ + {1, HID_KEY_S }, /* 0x53 S */ \ + {1, HID_KEY_T }, /* 0x55 T */ \ + {1, HID_KEY_U }, /* 0x55 U */ \ + {1, HID_KEY_V }, /* 0x56 V */ \ + {1, HID_KEY_W }, /* 0x57 W */ \ + {1, HID_KEY_X }, /* 0x58 X */ \ + {1, HID_KEY_Y }, /* 0x59 Y */ \ + {1, HID_KEY_Z }, /* 0x5A Z */ \ + {0, HID_KEY_BRACKET_LEFT }, /* 0x5B [ */ \ + {0, HID_KEY_BACKSLASH }, /* 0x5C '\' */ \ + {0, HID_KEY_BRACKET_RIGHT }, /* 0x5D ] */ \ + {1, HID_KEY_6 }, /* 0x5E ^ */ \ + {1, HID_KEY_MINUS }, /* 0x5F _ */ \ + \ + {0, HID_KEY_GRAVE }, /* 0x60 ` */ \ + {0, HID_KEY_A }, /* 0x61 a */ \ + {0, HID_KEY_B }, /* 0x62 b */ \ + {0, HID_KEY_C }, /* 0x63 c */ \ + {0, HID_KEY_D }, /* 0x66 d */ \ + {0, HID_KEY_E }, /* 0x65 e */ \ + {0, HID_KEY_F }, /* 0x66 f */ \ + {0, HID_KEY_G }, /* 0x67 g */ \ + {0, HID_KEY_H }, /* 0x68 h */ \ + {0, HID_KEY_I }, /* 0x69 i */ \ + {0, HID_KEY_J }, /* 0x6A j */ \ + {0, HID_KEY_K }, /* 0x6B k */ \ + {0, HID_KEY_L }, /* 0x6C l */ \ + {0, HID_KEY_M }, /* 0x6D m */ \ + {0, HID_KEY_N }, /* 0x6E n */ \ + {0, HID_KEY_O }, /* 0x6F o */ \ + {0, HID_KEY_P }, /* 0x70 p */ \ + {0, HID_KEY_Q }, /* 0x71 q */ \ + {0, HID_KEY_R }, /* 0x72 r */ \ + {0, HID_KEY_S }, /* 0x73 s */ \ + {0, HID_KEY_T }, /* 0x75 t */ \ + {0, HID_KEY_U }, /* 0x75 u */ \ + {0, HID_KEY_V }, /* 0x76 v */ \ + {0, HID_KEY_W }, /* 0x77 w */ \ + {0, HID_KEY_X }, /* 0x78 x */ \ + {0, HID_KEY_Y }, /* 0x79 y */ \ + {0, HID_KEY_Z }, /* 0x7A z */ \ + {1, HID_KEY_BRACKET_LEFT }, /* 0x7B { */ \ + {1, HID_KEY_BACKSLASH }, /* 0x7C | */ \ + {1, HID_KEY_BRACKET_RIGHT }, /* 0x7D } */ \ + {1, HID_KEY_GRAVE }, /* 0x7E ~ */ \ + {0, HID_KEY_DELETE } /* 0x7F Delete */ \ /*-------------------------------------------------------------------- * KEYCODE to Ascii Conversion @@ -1680,113 +1671,120 @@ extern "C" * char ch = shift ? conv_table[chr][1] : conv_table[chr][0]; * *--------------------------------------------------------------------*/ -#define HID_KEYCODE_TO_ASCII \ - {0, 0}, /* 0x00 */ \ - {0, 0}, /* 0x01 */ \ - {0, 0}, /* 0x02 */ \ - {0, 0}, /* 0x03 */ \ - {'a', 'A'}, /* 0x04 */ \ - {'b', 'B'}, /* 0x05 */ \ - {'c', 'C'}, /* 0x06 */ \ - {'d', 'D'}, /* 0x07 */ \ - {'e', 'E'}, /* 0x08 */ \ - {'f', 'F'}, /* 0x09 */ \ - {'g', 'G'}, /* 0x0a */ \ - {'h', 'H'}, /* 0x0b */ \ - {'i', 'I'}, /* 0x0c */ \ - {'j', 'J'}, /* 0x0d */ \ - {'k', 'K'}, /* 0x0e */ \ - {'l', 'L'}, /* 0x0f */ \ - {'m', 'M'}, /* 0x10 */ \ - {'n', 'N'}, /* 0x11 */ \ - {'o', 'O'}, /* 0x12 */ \ - {'p', 'P'}, /* 0x13 */ \ - {'q', 'Q'}, /* 0x14 */ \ - {'r', 'R'}, /* 0x15 */ \ - {'s', 'S'}, /* 0x16 */ \ - {'t', 'T'}, /* 0x17 */ \ - {'u', 'U'}, /* 0x18 */ \ - {'v', 'V'}, /* 0x19 */ \ - {'w', 'W'}, /* 0x1a */ \ - {'x', 'X'}, /* 0x1b */ \ - {'y', 'Y'}, /* 0x1c */ \ - {'z', 'Z'}, /* 0x1d */ \ - {'1', '!'}, /* 0x1e */ \ - {'2', '@'}, /* 0x1f */ \ - {'3', '#'}, /* 0x20 */ \ - {'4', '$'}, /* 0x21 */ \ - {'5', '%'}, /* 0x22 */ \ - {'6', '^'}, /* 0x23 */ \ - {'7', '&'}, /* 0x24 */ \ - {'8', '*'}, /* 0x25 */ \ - {'9', '('}, /* 0x26 */ \ - {'0', ')'}, /* 0x27 */ \ - {'\r', '\r'}, /* 0x28 */ \ - {'\x1b', '\x1b'}, /* 0x29 */ \ - {'\b', '\b'}, /* 0x2a */ \ - {'\t', '\t'}, /* 0x2b */ \ - {' ', ' '}, /* 0x2c */ \ - {'-', '_'}, /* 0x2d */ \ - {'=', '+'}, /* 0x2e */ \ - {'[', '{'}, /* 0x2f */ \ - {']', '}'}, /* 0x30 */ \ - {'\\', '|'}, /* 0x31 */ \ - {'#', '~'}, /* 0x32 */ \ - {';', ':'}, /* 0x33 */ \ - {'\'', '\"'}, /* 0x34 */ \ - {'`', '~'}, /* 0x35 */ \ - {',', '<'}, /* 0x36 */ \ - {'.', '>'}, /* 0x37 */ \ - {'/', '?'}, /* 0x38 */ \ - \ - {0, 0}, /* 0x39 */ \ - {0, 0}, /* 0x3a */ \ - {0, 0}, /* 0x3b */ \ - {0, 0}, /* 0x3c */ \ - {0, 0}, /* 0x3d */ \ - {0, 0}, /* 0x3e */ \ - {0, 0}, /* 0x3f */ \ - {0, 0}, /* 0x40 */ \ - {0, 0}, /* 0x41 */ \ - {0, 0}, /* 0x42 */ \ - {0, 0}, /* 0x43 */ \ - {0, 0}, /* 0x44 */ \ - {0, 0}, /* 0x45 */ \ - {0, 0}, /* 0x46 */ \ - {0, 0}, /* 0x47 */ \ - {0, 0}, /* 0x48 */ \ - {0, 0}, /* 0x49 */ \ - {0, 0}, /* 0x4a */ \ - {0, 0}, /* 0x4b */ \ - {0, 0}, /* 0x4c */ \ - {0, 0}, /* 0x4d */ \ - {0, 0}, /* 0x4e */ \ - {0, 0}, /* 0x4f */ \ - {0, 0}, /* 0x50 */ \ - {0, 0}, /* 0x51 */ \ - {0, 0}, /* 0x52 */ \ - {0, 0}, /* 0x53 */ \ - \ - {'/', '/'}, /* 0x54 */ \ - {'*', '*'}, /* 0x55 */ \ - {'-', '-'}, /* 0x56 */ \ - {'+', '+'}, /* 0x57 */ \ - {'\r', '\r'}, /* 0x58 */ \ - {'1', 0}, /* 0x59 */ \ - {'2', 0}, /* 0x5a */ \ - {'3', 0}, /* 0x5b */ \ - {'4', 0}, /* 0x5c */ \ - {'5', '5'}, /* 0x5d */ \ - {'6', 0}, /* 0x5e */ \ - {'7', 0}, /* 0x5f */ \ - {'8', 0}, /* 0x60 */ \ - {'9', 0}, /* 0x61 */ \ - {'0', 0}, /* 0x62 */ \ - {'0', 0}, /* 0x63 */ \ - {'=', '='}, /* 0x67 */ +#define HID_KEYCODE_TO_ASCII \ + {0 , 0 }, /* 0x00 */ \ + {0 , 0 }, /* 0x01 */ \ + {0 , 0 }, /* 0x02 */ \ + {0 , 0 }, /* 0x03 */ \ + {'a' , 'A' }, /* 0x04 */ \ + {'b' , 'B' }, /* 0x05 */ \ + {'c' , 'C' }, /* 0x06 */ \ + {'d' , 'D' }, /* 0x07 */ \ + {'e' , 'E' }, /* 0x08 */ \ + {'f' , 'F' }, /* 0x09 */ \ + {'g' , 'G' }, /* 0x0a */ \ + {'h' , 'H' }, /* 0x0b */ \ + {'i' , 'I' }, /* 0x0c */ \ + {'j' , 'J' }, /* 0x0d */ \ + {'k' , 'K' }, /* 0x0e */ \ + {'l' , 'L' }, /* 0x0f */ \ + {'m' , 'M' }, /* 0x10 */ \ + {'n' , 'N' }, /* 0x11 */ \ + {'o' , 'O' }, /* 0x12 */ \ + {'p' , 'P' }, /* 0x13 */ \ + {'q' , 'Q' }, /* 0x14 */ \ + {'r' , 'R' }, /* 0x15 */ \ + {'s' , 'S' }, /* 0x16 */ \ + {'t' , 'T' }, /* 0x17 */ \ + {'u' , 'U' }, /* 0x18 */ \ + {'v' , 'V' }, /* 0x19 */ \ + {'w' , 'W' }, /* 0x1a */ \ + {'x' , 'X' }, /* 0x1b */ \ + {'y' , 'Y' }, /* 0x1c */ \ + {'z' , 'Z' }, /* 0x1d */ \ + {'1' , '!' }, /* 0x1e */ \ + {'2' , '@' }, /* 0x1f */ \ + {'3' , '#' }, /* 0x20 */ \ + {'4' , '$' }, /* 0x21 */ \ + {'5' , '%' }, /* 0x22 */ \ + {'6' , '^' }, /* 0x23 */ \ + {'7' , '&' }, /* 0x24 */ \ + {'8' , '*' }, /* 0x25 */ \ + {'9' , '(' }, /* 0x26 */ \ + {'0' , ')' }, /* 0x27 */ \ + {'\r' , '\r' }, /* 0x28 */ \ + {'\x1b', '\x1b' }, /* 0x29 */ \ + {'\b' , '\b' }, /* 0x2a */ \ + {'\t' , '\t' }, /* 0x2b */ \ + {' ' , ' ' }, /* 0x2c */ \ + {'-' , '_' }, /* 0x2d */ \ + {'=' , '+' }, /* 0x2e */ \ + {'[' , '{' }, /* 0x2f */ \ + {']' , '}' }, /* 0x30 */ \ + {'\\' , '|' }, /* 0x31 */ \ + {'#' , '~' }, /* 0x32 */ \ + {';' , ':' }, /* 0x33 */ \ + {'\'' , '\"' }, /* 0x34 */ \ + {'`' , '~' }, /* 0x35 */ \ + {',' , '<' }, /* 0x36 */ \ + {'.' , '>' }, /* 0x37 */ \ + {'/' , '?' }, /* 0x38 */ \ + \ + {0 , 0 }, /* 0x39 */ \ + {0 , 0 }, /* 0x3a */ \ + {0 , 0 }, /* 0x3b */ \ + {0 , 0 }, /* 0x3c */ \ + {0 , 0 }, /* 0x3d */ \ + {0 , 0 }, /* 0x3e */ \ + {0 , 0 }, /* 0x3f */ \ + {0 , 0 }, /* 0x40 */ \ + {0 , 0 }, /* 0x41 */ \ + {0 , 0 }, /* 0x42 */ \ + {0 , 0 }, /* 0x43 */ \ + {0 , 0 }, /* 0x44 */ \ + {0 , 0 }, /* 0x45 */ \ + {0 , 0 }, /* 0x46 */ \ + {0 , 0 }, /* 0x47 */ \ + {0 , 0 }, /* 0x48 */ \ + {0 , 0 }, /* 0x49 */ \ + {0 , 0 }, /* 0x4a */ \ + {0 , 0 }, /* 0x4b */ \ + {0 , 0 }, /* 0x4c */ \ + {0 , 0 }, /* 0x4d */ \ + {0 , 0 }, /* 0x4e */ \ + {0 , 0 }, /* 0x4f */ \ + {0 , 0 }, /* 0x50 */ \ + {0 , 0 }, /* 0x51 */ \ + {0 , 0 }, /* 0x52 */ \ + {0 , 0 }, /* 0x53 */ \ + \ + {'/' , '/' }, /* 0x54 */ \ + {'*' , '*' }, /* 0x55 */ \ + {'-' , '-' }, /* 0x56 */ \ + {'+' , '+' }, /* 0x57 */ \ + {'\r' , '\r' }, /* 0x58 */ \ + {'1' , 0 }, /* 0x59 */ \ + {'2' , 0 }, /* 0x5a */ \ + {'3' , 0 }, /* 0x5b */ \ + {'4' , 0 }, /* 0x5c */ \ + {'5' , '5' }, /* 0x5d */ \ + {'6' , 0 }, /* 0x5e */ \ + {'7' , 0 }, /* 0x5f */ \ + {'8' , 0 }, /* 0x60 */ \ + {'9' , 0 }, /* 0x61 */ \ + {'0' , 0 }, /* 0x62 */ \ + {'0' , 0 }, /* 0x63 */ \ + {'=' , '=' }, /* 0x67 */ \ + #ifdef __cplusplus -} + } #endif + + + + #endif /* _TUSB_TYPES_H_ */ + + diff --git a/inc/extralibs/ws2812b_dma_spi_led_driver.h b/inc/extralibs/ws2812b_dma_spi_led_driver.h index 4b083e4..9aa6707 100644 --- a/inc/extralibs/ws2812b_dma_spi_led_driver.h +++ b/inc/extralibs/ws2812b_dma_spi_led_driver.h @@ -2,28 +2,30 @@ I may write another version of this to use DMA to timer ports, but, the SPI port can be used to generate outputs very efficiently. So, for now, SPI Port. Additionally, it uses FAR less internal bus resources than to do the same thing with timers. - + **For the CH32V003 this means output will be on PORTC Pin 6** + **For the CH570/2 - PORTA Pin 7** + **For the CH582/3 or CH591/2 PORTA Pin 14** Copyright 2023 <>< Charles Lohr, under the MIT-x11 or NewBSD License, you choose! - If you are including this in main, simply - #define WS2812DMA_IMPLEMENTATION + If you are including this in main, simply + #define WS2812DMA_IMPLEMENTATION Other defines inclue: - #define WSRAW - #define WSRBG - #define WSGRB - #define WS2812B_ALLOW_INTERRUPT_NESTING + #define WSRAW + #define WSRBG + #define WSGRB + #define WS2812B_ALLOW_INTERRUPT_NESTING You will need to implement the following two functions, as callbacks from the ISR. - uint32_t WS2812BLEDCallback( int ledno ); + uint32_t WS2812BLEDCallback( int ledno ); You willalso need to call - WS2812BDMAInit(); + WS2812BDMAInit(); Then, whenyou want to update the LEDs, call: - WS2812BDMAStart( int num_leds ); + WS2812BDMAStart( int num_leds ); */ #ifndef _WS2812_LED_DRIVER_H @@ -32,11 +34,11 @@ #include // Use DMA and SPI to stream out WS2812B LED Data via the MOSI pin. -void WS2812BDMAInit(); -void WS2812BDMAStart(int leds); +void WS2812BDMAInit( ); +void WS2812BDMAStart( int leds ); // Callbacks that you must implement. -uint32_t WS2812BLEDCallback(int ledno); +uint32_t WS2812BLEDCallback( int ledno ); #ifdef WS2812DMA_IMPLEMENTATION @@ -46,241 +48,293 @@ uint32_t WS2812BLEDCallback(int ledno); #endif // Note first n LEDs of DMA Buffer are 0's as a "break" -// Need one extra LED at end to leave line high. +// Need one extra LED at end to leave line high. // This must be greater than WS2812B_RESET_PERIOD. #define WS2812B_RESET_PERIOD 2 #ifdef WSRAW -#define DMA_BUFFER_LEN (((DMALEDS) / 2) * 8) +#define DMA_BUFFER_LEN (((DMALEDS)/2)*8) #else -#define DMA_BUFFER_LEN (((DMALEDS) / 2) * 6) +#define DMA_BUFFER_LEN (((DMALEDS)/2)*6) #endif -static uint16_t WS2812dmabuff[DMA_BUFFER_LEN]; +static uint16_t WS2812dmabuff[DMA_BUFFER_LEN]; static volatile int WS2812LEDs; static volatile int WS2812LEDPlace; static volatile int WS2812BLEDInUse; + +#ifdef CH5xx +#ifdef CH570_CH572 +#define bMOSI PA7 +#else +#define bMOSI PA14 +#endif +#endif // This is the code that updates a portion of the WS2812dmabuff with new data. // This effectively creates the bitstream that outputs to the LEDs. -static void WS2812FillBuffSec(uint16_t *ptr, int numhalfwords, int tce) +static void WS2812FillBuffSec( uint16_t * ptr, int numhalfwords, int tce ) { - const static uint16_t bitquartets[16] = { - 0b1000100010001000, - 0b1000100010001110, - 0b1000100011101000, - 0b1000100011101110, - 0b1000111010001000, - 0b1000111010001110, - 0b1000111011101000, - 0b1000111011101110, - 0b1110100010001000, - 0b1110100010001110, - 0b1110100011101000, - 0b1110100011101110, - 0b1110111010001000, - 0b1110111010001110, - 0b1110111011101000, - 0b1110111011101110, - }; - - int i; - uint16_t *end = ptr + numhalfwords; - int ledcount = WS2812LEDs; - int place = WS2812LEDPlace; - -#ifdef WSRAW - while (place < 0 && ptr != end) - { - uint32_t *lptr = (uint32_t *)ptr; - lptr[0] = 0; - lptr[1] = 0; - lptr[2] = 0; - lptr[3] = 0; - ptr += 8; - place++; - } - +#ifdef CH5xx + // Reversing bit order because CH5xx SPI FIFO is only half of what CH32 have + const static uint16_t bitquartets[16] = { + 0b0001000100010001, 0b0111000100010001, 0b0001011100010001, 0b0111011100010001, + 0b0001000101110001, 0b0111000101110001, 0b0001011101110001, 0b0111011101110001, + 0b0001000100010111, 0b0111000100010111, 0b0001011100010111, 0b0111011100010111, + 0b0001000101110111, 0b0111000101110111, 0b0001011101110111, 0b0111011101110111, }; #else - while (place < 0 && ptr != end) - { - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - (*ptr++) = 0; - place++; - } + const static uint16_t bitquartets[16] = { + 0b1000100010001000, 0b1000100010001110, 0b1000100011101000, 0b1000100011101110, + 0b1000111010001000, 0b1000111010001110, 0b1000111011101000, 0b1000111011101110, + 0b1110100010001000, 0b1110100010001110, 0b1110100011101000, 0b1110100011101110, + 0b1110111010001000, 0b1110111010001110, 0b1110111011101000, 0b1110111011101110, }; #endif - while (ptr != end) - { - if (place >= ledcount) - { - // Optionally, leave line high. - while (ptr != end) - (*ptr++) = 0; // 0xffff; - - // Only safe to do this when we're on the second leg. - if (tce) - { - if (place == ledcount) - { - // Take the DMA out of circular mode and let it expire. - DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; - WS2812BLEDInUse = 0; - } - place++; - } - - break; - } + int i; + uint16_t * end = ptr + numhalfwords; + int ledcount = WS2812LEDs; + int place = WS2812LEDPlace; #ifdef WSRAW - uint32_t ledval32bit = WS2812BLEDCallback(place++); - - ptr[6] = bitquartets[(ledval32bit >> 28) & 0xf]; - ptr[7] = bitquartets[(ledval32bit >> 24) & 0xf]; - ptr[4] = bitquartets[(ledval32bit >> 20) & 0xf]; - ptr[5] = bitquartets[(ledval32bit >> 16) & 0xf]; - ptr[2] = bitquartets[(ledval32bit >> 12) & 0xf]; - ptr[3] = bitquartets[(ledval32bit >> 8) & 0xf]; - ptr[0] = bitquartets[(ledval32bit >> 4) & 0xf]; - ptr[1] = bitquartets[(ledval32bit >> 0) & 0xf]; - - ptr += 8; - i += 8; + while( place < 0 && ptr != end ) + { + uint32_t * lptr = (uint32_t *)ptr; + lptr[0] = 0; + lptr[1] = 0; + lptr[2] = 0; + lptr[3] = 0; + ptr += 8; + place++; + } #else - // Use a LUT to figure out how we should set the SPI line. - uint32_t ledval24bit = WS2812BLEDCallback(place++); + while( place < 0 && ptr != end ) + { + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + (*ptr++) = 0; + place++; + } +#endif + + while( ptr != end ) + { + if( place >= ledcount ) + { + // Optionally, leave line high. + while( ptr != end ) + (*ptr++) = 0;//0xffff; + + // Only safe to do this when we're on the second leg. + if( tce ) + { + if( place == ledcount ) + { + // Take the DMA out of circular mode and let it expire. +#ifdef CH5xx + R8_SPI0_INTER_EN &= ~RB_SPI_IE_DMA_END; // Disable DMA end interrupt +#else + DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; +#endif + WS2812BLEDInUse = 0; + } + place++; + } + + break; + } + +#ifdef WSRAW + uint32_t ledval32bit = WS2812BLEDCallback( place++ ); + + ptr[6] = bitquartets[(ledval32bit>>28)&0xf]; + ptr[7] = bitquartets[(ledval32bit>>24)&0xf]; + ptr[4] = bitquartets[(ledval32bit>>20)&0xf]; + ptr[5] = bitquartets[(ledval32bit>>16)&0xf]; + ptr[2] = bitquartets[(ledval32bit>>12)&0xf]; + ptr[3] = bitquartets[(ledval32bit>>8)&0xf]; + ptr[0] = bitquartets[(ledval32bit>>4)&0xf]; + ptr[1] = bitquartets[(ledval32bit>>0)&0xf]; + + ptr += 8; + i += 8; + +#else + // Use a LUT to figure out how we should set the SPI line. + uint32_t ledval24bit = WS2812BLEDCallback( place++ ); #ifdef WSRBG - ptr[0] = bitquartets[(ledval24bit >> 12) & 0xf]; - ptr[1] = bitquartets[(ledval24bit >> 8) & 0xf]; - ptr[2] = bitquartets[(ledval24bit >> 20) & 0xf]; - ptr[3] = bitquartets[(ledval24bit >> 16) & 0xf]; - ptr[4] = bitquartets[(ledval24bit >> 4) & 0xf]; - ptr[5] = bitquartets[(ledval24bit >> 0) & 0xf]; -#elif defined(WSGRB) - ptr[0] = bitquartets[(ledval24bit >> 12) & 0xf]; - ptr[1] = bitquartets[(ledval24bit >> 8) & 0xf]; - ptr[2] = bitquartets[(ledval24bit >> 4) & 0xf]; - ptr[3] = bitquartets[(ledval24bit >> 0) & 0xf]; - ptr[4] = bitquartets[(ledval24bit >> 20) & 0xf]; - ptr[5] = bitquartets[(ledval24bit >> 16) & 0xf]; + ptr[0] = bitquartets[(ledval24bit>>12)&0xf]; + ptr[1] = bitquartets[(ledval24bit>>8)&0xf]; + ptr[2] = bitquartets[(ledval24bit>>20)&0xf]; + ptr[3] = bitquartets[(ledval24bit>>16)&0xf]; + ptr[4] = bitquartets[(ledval24bit>>4)&0xf]; + ptr[5] = bitquartets[(ledval24bit>>0)&0xf]; +#elif defined( WSGRB ) + ptr[0] = bitquartets[(ledval24bit>>12)&0xf]; + ptr[1] = bitquartets[(ledval24bit>>8)&0xf]; + ptr[2] = bitquartets[(ledval24bit>>4)&0xf]; + ptr[3] = bitquartets[(ledval24bit>>0)&0xf]; + ptr[4] = bitquartets[(ledval24bit>>20)&0xf]; + ptr[5] = bitquartets[(ledval24bit>>16)&0xf]; #else - ptr[0] = bitquartets[(ledval24bit >> 20) & 0xf]; - ptr[1] = bitquartets[(ledval24bit >> 16) & 0xf]; - ptr[2] = bitquartets[(ledval24bit >> 12) & 0xf]; - ptr[3] = bitquartets[(ledval24bit >> 8) & 0xf]; - ptr[4] = bitquartets[(ledval24bit >> 4) & 0xf]; - ptr[5] = bitquartets[(ledval24bit >> 0) & 0xf]; + ptr[0] = bitquartets[(ledval24bit>>20)&0xf]; + ptr[1] = bitquartets[(ledval24bit>>16)&0xf]; + ptr[2] = bitquartets[(ledval24bit>>12)&0xf]; + ptr[3] = bitquartets[(ledval24bit>>8)&0xf]; + ptr[4] = bitquartets[(ledval24bit>>4)&0xf]; + ptr[5] = bitquartets[(ledval24bit>>0)&0xf]; #endif - ptr += 6; - i += 6; + ptr += 6; + i += 6; #endif - } - WS2812LEDPlace = place; + + } + WS2812LEDPlace = place; } -void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt)); -void DMA1_Channel3_IRQHandler(void) +#ifdef CH5xx +void SPI0_IRQHandler( void ) __attribute__((interrupt)); +void SPI0_IRQHandler( void ) { - // GPIOD->BSHR = 1; // Turn on GPIOD0 for profiling + uint8_t intf = R8_SPI0_INT_FLAG; + if( (intf & RB_SPI_IF_DMA_END) ) + { + WS2812FillBuffSec( WS2812dmabuff, DMA_BUFFER_LEN, 1 ); + R16_SPI0_TOTAL_CNT = DMA_BUFFER_LEN * 2; + } +} +#else +void DMA1_Channel3_IRQHandler( void ) __attribute__((interrupt)); +void DMA1_Channel3_IRQHandler( void ) +{ + //GPIOD->BSHR = 1; // Turn on GPIOD0 for profiling - // Backup flags. - volatile int intfr = DMA1->INTFR; - do - { - // Clear all possible flags. - DMA1->INTFCR = DMA1_IT_GL3; + // Backup flags. + volatile int intfr = DMA1->INTFR; + do + { + // Clear all possible flags. + DMA1->INTFCR = DMA1_IT_GL3; - // Strange note: These are backwards. DMA1_IT_HT3 should be HALF and - // DMA1_IT_TC3 should be COMPLETE. But for some reason, doing this causes - // LED jitter. I am henseforth flipping the order. + // Strange note: These are backwards. DMA1_IT_HT3 should be HALF and + // DMA1_IT_TC3 should be COMPLETE. But for some reason, doing this causes + // LED jitter. I am henseforth flipping the order. - if (intfr & DMA1_IT_HT3) - { - // Halfwaay (Fill in first part) - WS2812FillBuffSec(WS2812dmabuff, DMA_BUFFER_LEN / 2, 1); - } - if (intfr & DMA1_IT_TC3) - { - // Complete (Fill in second part) - WS2812FillBuffSec(WS2812dmabuff + DMA_BUFFER_LEN / 2, DMA_BUFFER_LEN / 2, 0); - } - intfr = DMA1->INTFR; - } while (intfr & DMA1_IT_GL3); + if( intfr & DMA1_IT_HT3 ) + { + // Halfwaay (Fill in first part) + WS2812FillBuffSec( WS2812dmabuff, DMA_BUFFER_LEN / 2, 1 ); + } + if( intfr & DMA1_IT_TC3 ) + { + // Complete (Fill in second part) + WS2812FillBuffSec( WS2812dmabuff + DMA_BUFFER_LEN / 2, DMA_BUFFER_LEN / 2, 0 ); + } + intfr = DMA1->INTFR; + } while( intfr & DMA1_IT_GL3 ); - // GPIOD->BSHR = 1<<16; // Turn off GPIOD0 for profiling + //GPIOD->BSHR = 1<<16; // Turn off GPIOD0 for profiling +} +#endif + +void WS2812BDMAStart( int leds ) +{ + // Enter critical section. + __disable_irq(); + WS2812BLEDInUse = 1; +#ifdef CH5xx + R8_SPI0_INTER_EN &= ~RB_SPI_IE_DMA_END; + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; + R16_SPI0_TOTAL_CNT = 0; +#else + DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; + DMA1_Channel3->CNTR = 0; + DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; +#endif + __enable_irq(); + WS2812LEDs = leds; + WS2812LEDPlace = -WS2812B_RESET_PERIOD; + + +#ifdef CH5xx + WS2812FillBuffSec( WS2812dmabuff, DMA_BUFFER_LEN, 0 ); + R16_SPI0_TOTAL_CNT = DMA_BUFFER_LEN * 2; + R16_SPI0_DMA_BEG = (uint32_t)WS2812dmabuff; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END | RB_SPI_IF_DMA_END; + R8_SPI0_INTER_EN = RB_SPI_IE_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; +#else + WS2812FillBuffSec( WS2812dmabuff, DMA_BUFFER_LEN, 0 ); + DMA1_Channel3->CNTR = DMA_BUFFER_LEN; // Number of unique uint16_t entries. + DMA1_Channel3->CFGR |= DMA_Mode_Circular; +#endif } -void WS2812BDMAStart(int leds) +void WS2812BDMAInit( ) { - // Enter critical section. - __disable_irq(); - WS2812BLEDInUse = 1; - DMA1_Channel3->CFGR &= ~DMA_Mode_Circular; - DMA1_Channel3->CNTR = 0; - DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; - WS2812LEDs = leds; - WS2812LEDPlace = -WS2812B_RESET_PERIOD; - __enable_irq(); + // Enable DMA + Peripherals +#ifdef CH5xx + funPinMode( bMOSI, GPIO_CFGLR_OUT_2Mhz_PP ); + R8_SPI0_CLOCK_DIV = FUNCONF_SYSTEM_CORE_CLOCK / 3000000; // div = Fsys/3MHz + R8_SPI0_CTRL_MOD = RB_SPI_ALL_CLEAR; + R8_SPI0_CTRL_MOD = RB_SPI_MOSI_OE | RB_SPI_2WIRE_MOD; + R16_SPI0_DMA_END = ( (uint32_t)WS2812dmabuff + (DMA_BUFFER_LEN * 2) ); + R8_SPI0_CTRL_CFG |= RB_SPI_BIT_ORDER; - WS2812FillBuffSec(WS2812dmabuff, DMA_BUFFER_LEN, 0); + NVIC_EnableIRQ( SPI0_IRQn ); +#else + RCC->AHBPCENR |= RCC_AHBPeriph_DMA1; + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; - DMA1_Channel3->CNTR = DMA_BUFFER_LEN; // Number of unique uint16_t entries. - DMA1_Channel3->CFGR |= DMA_Mode_Circular; -} + // MOSI, Configure GPIO Pin + GPIOC->CFGLR &= ~(0xf<<(4*6)); + GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*6); -void WS2812BDMAInit() -{ - // Enable DMA + Peripherals - RCC->AHBPCENR |= RCC_AHBPeriph_DMA1; - RCC->APB2PCENR |= RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1; + // Configure SPI + SPI1->CTLR1 = + SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_16b | + SPI_Mode_Master | SPI_Direction_1Line_Tx | + 3<<3; // Divisior = 16 (48/16 = 3MHz) - // MOSI, Configure GPIO Pin - GPIOC->CFGLR &= ~(0xf << (4 * 6)); - GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 6); + SPI1->CTLR2 = SPI_CTLR2_TXDMAEN; // Enable Tx buffer DMA - // Configure SPI - SPI1->CTLR1 = - SPI_NSS_Soft | SPI_CPHA_1Edge | SPI_CPOL_Low | SPI_DataSize_16b | - SPI_Mode_Master | SPI_Direction_1Line_Tx | - 3 << 3; // Divisior = 16 (48/16 = 3MHz) +#if defined(CH32V003) + SPI1->HSCR = 1; // Enable high-speed read mode +#endif - SPI1->CTLR2 = SPI_CTLR2_TXDMAEN; - SPI1->HSCR = 1; + SPI1->CTLR1 |= CTLR1_SPE_Set; // Enable SPI - SPI1->CTLR1 |= CTLR1_SPE_Set; + SPI1->DATAR = 0; // Set SPI line Low. - SPI1->DATAR = 0; // Set SPI line Low. + //DMA1_Channel3 is for SPI1TX + DMA1_Channel3->PADDR = (uint32_t)&SPI1->DATAR; + DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; + DMA1_Channel3->CNTR = 0;// sizeof( bufferset )/2; // Number of unique copies. (Don't start, yet!) + DMA1_Channel3->CFGR = + DMA_M2M_Disable | + DMA_Priority_VeryHigh | + DMA_MemoryDataSize_HalfWord | + DMA_PeripheralDataSize_HalfWord | + DMA_MemoryInc_Enable | + DMA_Mode_Normal | // OR DMA_Mode_Circular or DMA_Mode_Normal + DMA_DIR_PeripheralDST | + DMA_IT_TC | DMA_IT_HT; // Transmission Complete + Half Empty Interrupts. - // DMA1_Channel3 is for SPI1TX - DMA1_Channel3->PADDR = (uint32_t)&SPI1->DATAR; - DMA1_Channel3->MADDR = (uint32_t)WS2812dmabuff; - DMA1_Channel3->CNTR = 0; // sizeof( bufferset )/2; // Number of unique copies. (Don't start, yet!) - DMA1_Channel3->CFGR = - DMA_M2M_Disable | - DMA_Priority_VeryHigh | - DMA_MemoryDataSize_HalfWord | - DMA_PeripheralDataSize_HalfWord | - DMA_MemoryInc_Enable | - DMA_Mode_Normal | // OR DMA_Mode_Circular or DMA_Mode_Normal - DMA_DIR_PeripheralDST | - DMA_IT_TC | DMA_IT_HT; // Transmission Complete + Half Empty Interrupts. - - // NVIC_SetPriority( DMA1_Channel3_IRQn, 0<<4 ); //We don't need to tweak priority. - NVIC_EnableIRQ(DMA1_Channel3_IRQn); - DMA1_Channel3->CFGR |= DMA_CFGR1_EN; +// NVIC_SetPriority( DMA1_Channel3_IRQn, 0<<4 ); //We don't need to tweak priority. + NVIC_EnableIRQ( DMA1_Channel3_IRQn ); + DMA1_Channel3->CFGR |= DMA_CFGR1_EN; #ifdef WS2812B_ALLOW_INTERRUPT_NESTING - __set_INTSYSCR(__get_INTSYSCR() | 2); // Enable interrupt nesting. - PFIC->IPRIOR[24] = 0b10000000; // Turn on preemption for DMA1Ch3 + __set_INTSYSCR( __get_INTSYSCR() | 2 ); // Enable interrupt nesting. + PFIC->IPRIOR[24] = 0b10000000; // Turn on preemption for DMA1Ch3 +#endif #endif } #endif #endif + diff --git a/inc/extralibs/ws2812b_simple.h b/inc/extralibs/ws2812b_simple.h index efc8c07..0e35add 100644 --- a/inc/extralibs/ws2812b_simple.h +++ b/inc/extralibs/ws2812b_simple.h @@ -3,10 +3,10 @@ Copyright 2023 <>< Charles Lohr, under the MIT-x11 or NewBSD License, you choose! If you are including this in main, simply - #define WS2812BSIMPLE_IMPLEMENTATION + #define WS2812BSIMPLE_IMPLEMENTATION You may also want to define - #define WS2812BSIMPLE_NO_IRQ_TWEAKING + #define WS2812BSIMPLE_NO_IRQ_TWEAKING */ @@ -15,7 +15,7 @@ #include -void WS2812BSimpleSend(GPIO_TypeDef *port, int pin, uint8_t *data, int len_in_bytes); +void WS2812BSimpleSend( GPIO_TypeDef * port, int pin, uint8_t * data, int len_in_bytes ); #ifdef WS2812BSIMPLE_IMPLEMENTATION @@ -25,58 +25,59 @@ void WS2812BSimpleSend(GPIO_TypeDef *port, int pin, uint8_t *data, int len_in_by #error WS2812B Driver Requires FUNCONF_SYSTICK_USE_HCLK #endif -void WS2812BSimpleSend(GPIO_TypeDef *port, int pin, uint8_t *data, int len_in_bytes) +void WS2812BSimpleSend( GPIO_TypeDef * port, int pin, uint8_t * data, int len_in_bytes ) { - int port_id = (((intptr_t)port - (intptr_t)GPIOA) >> 10); - RCC->APB2PCENR |= (RCC_APB2Periph_GPIOA << port_id); // Make sure port is enabled. + int port_id = (((intptr_t)port-(intptr_t)GPIOA)>>10); + RCC->APB2PCENR |= (RCC_APB2Periph_GPIOA<CFGLR = (port->CFGLR & (~(0xf << poffset))) | ((GPIO_Speed_2MHz | GPIO_CNF_OUT_PP) << (poffset)); + int poffset = (pin*4); + port->CFGLR = ( port->CFGLR & (~(0xf<BSHR = maskoff; + port->BSHR = maskoff; - uint8_t *end = data + len_in_bytes; - while (data != end) - { - uint8_t byte = *data; + uint8_t * end = data + len_in_bytes; + while( data != end ) + { + uint8_t byte = *data; - int i; - for (i = 0; i < 8; i++) - { - if (byte & 0x80) - { - // WS2812B's need AT LEAST 625ns for a logical "1" - port->BSHR = maskon; - DelaySysTick(25); - port->BSHR = maskoff; - DelaySysTick(1); - } - else - { - // WS2812B's need BETWEEN 62.5 to about 500 ns for a logical "0" + int i; + for( i = 0; i < 8; i++ ) + { + if( byte & 0x80 ) + { + // WS2812B's need AT LEAST 625ns for a logical "1" + port->BSHR = maskon; + DelaySysTick(25); + port->BSHR = maskoff; + DelaySysTick(1); + } + else + { + // WS2812B's need BETWEEN 62.5 to about 500 ns for a logical "0" #ifndef WS2812BSIMPLE_NO_IRQ_TWEAKING - __disable_irq(); + __disable_irq(); #endif - port->BSHR = maskon; - asm volatile("nop\nnop\nnop\nnop"); - port->BSHR = maskoff; + port->BSHR = maskon; + asm volatile( "nop\nnop\nnop\nnop" ); + port->BSHR = maskoff; #ifndef WS2812BSIMPLE_NO_IRQ_TWEAKING - __enable_irq(); + __enable_irq(); #endif - DelaySysTick(15); - } - byte <<= 1; - } + DelaySysTick(15); + } + byte <<= 1; + } - data++; - } + data++; + } - port->BSHR = maskoff; + port->BSHR = maskoff; } #endif #endif + diff --git a/inc/misc/attic/.clang-format b/inc/misc/attic/.clang-format deleted file mode 100644 index 659faab..0000000 --- a/inc/misc/attic/.clang-format +++ /dev/null @@ -1,5 +0,0 @@ -{ - "DisableFormat": true, - "SortIncludes": "Never" -} - diff --git a/inc/misc/attic/ch5xx_blobs_for_minichlink/build_blink.sh b/inc/misc/attic/ch5xx_blobs_for_minichlink/build_blink.sh new file mode 100755 index 0000000..0370001 --- /dev/null +++ b/inc/misc/attic/ch5xx_blobs_for_minichlink/build_blink.sh @@ -0,0 +1,5 @@ +#!/bin/bash +rm -f ch5xx_blink.o ch5xx_blink.bin +riscv64-unknown-elf-as ch5xx_blink.asm -march=rv32imac -mabi=ilp32 -o ch5xx_blink.o +riscv64-unknown-elf-objcopy -O binary ch5xx_blink.o ch5xx_blink.bin +xxd -i ch5xx_blink.bin > ch5xx_blink.h diff --git a/inc/misc/attic/ch5xx_blobs_for_minichlink/build_verify.sh b/inc/misc/attic/ch5xx_blobs_for_minichlink/build_verify.sh new file mode 100755 index 0000000..ec05407 --- /dev/null +++ b/inc/misc/attic/ch5xx_blobs_for_minichlink/build_verify.sh @@ -0,0 +1,5 @@ +#!/bin/bash +rm -f ch5xx_verify.o ch5xx_verify.bin +riscv64-unknown-elf-as ch5xx_verify.asm -march=rv32imac_zicsr -o ch5xx_verify.o +riscv64-unknown-elf-objcopy -O binary ch5xx_verify.o ch5xx_verify.bin +xxd -i ch5xx_verify.bin > ch5xx_verify.h diff --git a/inc/misc/attic/ch5xx_blobs_for_minichlink/build_write_block.sh b/inc/misc/attic/ch5xx_blobs_for_minichlink/build_write_block.sh new file mode 100755 index 0000000..2f7b7cd --- /dev/null +++ b/inc/misc/attic/ch5xx_blobs_for_minichlink/build_write_block.sh @@ -0,0 +1,5 @@ +#!/bin/bash +rm -f ch5xx_write_block.o ch5xx_write_block.bin +riscv64-unknown-elf-as ch5xx_write_block.asm -march=rv32imac_zicsr -o ch5xx_write_block.o +riscv64-unknown-elf-objcopy -O binary ch5xx_write_block.o ch5xx_write_block.bin +xxd -i ch5xx_write_block.bin > ch5xx_write_block.h diff --git a/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_blink.asm b/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_blink.asm new file mode 100644 index 0000000..39a6fbe --- /dev/null +++ b/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_blink.asm @@ -0,0 +1,23 @@ +# +# The simplest blink fuction that can fit into PROGBUF. +# This is the version suitable for CH5xx series of chips by WCH. +# You need to preload respective registers with values for port, pin and delay. +# Copyright 2025 monte-monte +# +#a2 = GPIO port (0 - A, 1 - B...) +#a3 = value to count down from for a delay between blinks +#a4 = pin mask +BEGIN: +c.sw a4, 0(a2); +c.mv a5, a3; +sw zero, 8(a2); +LOOP1: +c.addi a5, -1; +c.bnez a5, LOOP1; +c.mv a5, a3; +c.sw a4, 8(a2); +LOOP2: +c.addi a5, -1; +c.bnez a5, LOOP2; +c.j BEGIN; +c.ebreak diff --git a/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_verify.asm b/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_verify.asm new file mode 100644 index 0000000..504387a --- /dev/null +++ b/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_verify.asm @@ -0,0 +1,10 @@ +c.nop; +li a5,4; +LOOP: +lb a4,6(a3); +blt a4,zero,LOOP; +lb a4,4(a3); +c.addi a5,-1; +c.bnez a5,LOOP; +c.lw a1,0(a3); +c.sw a1,0(a0); diff --git a/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_write_block.asm b/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_write_block.asm new file mode 100644 index 0000000..3bcdb62 --- /dev/null +++ b/inc/misc/attic/ch5xx_blobs_for_minichlink/ch5xx_write_block.asm @@ -0,0 +1,116 @@ +# +# A procedure to write data to flash on CH5xx series of chips by WCH. +# This should be compiled into a binary blob and placed into RAM. +# Then you will be able to run it and send data via a programmer by writing it to DMDATA0/1 +# Copyright 2025 monte-monte +# +#s0 = incomming data from dmdata0 +#s1 = incomming data from dmdata1 +#t0 = general reg +#t1 = address global +#a0 = address in loop +#a1 = dmdata0 offset +#a2 = general reg +#a3 = R32_FLASH_DATA +#a4 = general operational +#a5 = len counter +PREAMBLE: +#c.li t0,0; +#c.li a2,0; +#c.li a4,0; +#c.li a5,0; +lw s0,0(a1); +lw s1,4(a1); +bne s1,s0,PREAMBLE;#Wait for DMDATA0/1 to be cleared; +c.bnez s0,PREAMBLE; +START: +#BEGIN +addi a0,t1,0; +sb zero,6(a3); +c.li a4,5; +sb a4,6(a3); +c.li a4,6; +sb a4,4(a3); +END: +lb a4,6(a3); +blt a4,zero,END; +sb zero,6(a3); +#BEGIN with CMD = 2 +sb zero,6(a3); +c.li a4,5; +sb a4,6(a3); +c.li a4,2; +sb a4,4(a3); +c.li a2,3; +OUT: +srli t0,a0,16; +andi t0,t0,0xff; +OUT_LOOP: +lb a4,6(a3); +blt a4,zero,OUT_LOOP; +sb t0,4(a3); +c.slli a0,8; +c.addi a2,-1; +c.bnez a2,OUT; +ADDRES_IS_SET: +sw zero,0(a1);#Clear DMDATA0 to indicate we are ready to write again +addi a5,zero,64;#Load up the byte counter +DATA_RETRIEVER: +c.lw s0,0(a1); +c.lw s1,4(a1); +c.bnez s1, WRITE_ZERO +c.beqz s0, DATA_RETRIEVER; +WRITE: +c.sw s0,0(a3); +c.li a4,0x4; +WRITE_LOOP1: +lb a2,6(a3); +blt a2,zero,WRITE_LOOP1; +c.li a2,21; +sb a2,6(a3); +c.addi a4,-1; +c.bnez a4,WRITE_LOOP1; +c.addi a5,-1; +sw zero,0(a1); +c.bnez a5,DATA_RETRIEVER; +addi t1,t1,256; +sw t1,0(a1);#Write current address to DMDATA0 to indicate that we are in wait loop +lui t0,0x80; +WAIT: +#END +lb a4,6(a3); +blt a4,zero,WAIT; +sb zero,6(a3) +#BEGIN with CMD = 5 +WAIT_LOOP: +sb zero,6(a3); +c.li a4,5; +sb a4,6(a3); +sb a4,4(a3) +IN_LOOP1: +lb a4,6(a3); +blt a4,zero,IN_LOOP1; +lbu a2,4(a3); +IN_LOOP2: +lb a4,6(a3); +blt a4,zero,IN_LOOP2; +lb a2,4(a3); +WAIT_END: +lb a4,6(a3); +blt a4,zero,WAIT_END; +sb zero,6(a3) +#IF +andi a4,a2,1; +c.bnez a4,WAIT_LOOP_BACK; +j START; +WAIT_LOOP_BACK: +c.addi t0,-1; +bne t0,zero,WAIT_LOOP; +EXIT: +c.ebreak; +WRITE_ZERO: +sw zero,4(a1); +beq s1,a1,WAIT; +sw zero,0(a3); +c.li a4,0x4; +c.j WRITE_LOOP1; diff --git a/inc/misc/attic/hardware_header_all_combined.h b/inc/misc/attic/hardware_header_all_combined.h index 45c50e3..c0c7e97 100644 --- a/inc/misc/attic/hardware_header_all_combined.h +++ b/inc/misc/attic/hardware_header_all_combined.h @@ -20,7 +20,7 @@ typedef enum IRQn Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ #endif - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ Software_IRQn = 14, /* 14 software Interrupt */ #if defined(CH32V003) || defined(CH32X03x) @@ -1864,8 +1864,6 @@ typedef struct -#define USB_PHY_V33 (1<<6) -#define USB_IOEN (1<<7) #define USBFSD_UEP_MOD_BASE 0x4002340C @@ -2266,11 +2264,7 @@ typedef struct #define ESIG_BASE ((uint32_t)0x1FFFF7E0) #define INFO_BASE ((uint32_t)0x1FFFF704) -#if defined(CH32V003) || defined(CH32V10x) -#define EXTEN_BASE ((uint32_t)0x40023800) -#elif defined(CH32V20x) || defined(CH32V30x) #define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) -#endif #define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) #define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) @@ -2283,118 +2277,6 @@ typedef struct -// AFIO CTLR Bits -#define PB6_FILT_EN (1<<27) -#define PB5_FILT_EN (1<<26) -#define PA4_FILT_EN (1<<25) -#define PA3_FILT_EN (1<<24) -#define UDM_BC_CMPO (1<<19) -#define UDP_BC_CMPO (1<<17) -#define UDM_BC_VSRC (1<<17) -#define UDP_BC_VSRC (1<<16) -#define USBPD_IN_HVT (1<<9) -#define USBPD_PHY_V33 (1<<8) -#define USB_IOEN (1<<7) -#define USB_PHY_V33 (1<<6) -#define UDP_PUE_00 (0b00<<2) -#define UDP_PUE_01 (0b01<<2) -#define UDP_PUE_10 (0b10<<2) -#define UDP_PUE_11 (0b11<<2) -#define UDM_PUE_00 (0b00<<0) -#define UDM_PUE_01 (0b01<<0) -#define UDM_PUE_10 (0b10<<0) -#define UDM_PUE_11 (0b11<<0) -#define UDP_PUE_MASK 0x0000000C -#define UDP_PUE_DISABLE 0x00000000 -#define UDP_PUE_35UA 0x00000004 -#define UDP_PUE_10K 0x00000008 -#define UDP_PUE_1K5 0x0000000C -#define UDM_PUE_MASK 0x00000003 -#define UDM_PUE_DISABLE 0x00000000 -#define UDM_PUE_35UA 0x00000001 -#define UDM_PUE_10K 0x00000002 -#define UDM_PUE_1K5 0x00000003 - - -// USB PD Bits -#define IE_TX_END (1<<15) -#define IE_RX_RESET (1<<14) -#define IE_RX_ACT (1<<13) -#define IE_RX_BYTE (1<<12) -#define IE_RX_BIT (1<<11) -#define IE_PD_IO (1<<10) -#define WAKE_POLAR (1<<5) -#define PD_RST_EN (1<<4) -#define PD_DMA_EN (1<<3) -#define CC_SEL (1<<2) -#define PD_ALL_CLR (1<<1) -#define PD_FILT_EN (1<<0) -#define BMC_CLK_CNT_MASK (0xff) - -//R8_CONTROL -#define BMC_BYTE_HI (1<<7) -#define TX_BIT_BACK (1<<6) -#define DATA_FLAG (1<<5) -#define RX_STATE_MASK (0x7<<2) -#define RX_STATE_0 (1<<2) -#define RX_STATE_1 (1<<3) -#define RX_STATE_2 (1<<4) -#define BMC_START (1<<1) -#define PD_TX_EN (1<<0) - -#define TX_SEL4_MASK (3<<6) -#define TX_SEL4_0 (1<<6) -#define TX_SEL4_1 (1<<7) - -#define TX_SEL3_MASK (3<<4) -#define TX_SEL3_0 (1<<4) -#define TX_SEL3_1 (1<<5) - -#define TX_SEL2_MASK (3<<2) -#define TX_SEL2_0 (1<<2) -#define TX_SEL2_1 (1<<3) - -#define TX_SEL1 (1<<0) - -#define BMC_TX_SZ_MASK (0x1ff) - -//R8_STATUS -#define IF_TX_END (1<<7) -#define IF_RX_RESET (1<<6) -#define IF_RX_ACT (1<<5) -#define IF_RX_BYTE (1<<4) -#define IF_RX_BIT (1<<3) -#define IFBUF_ERR (1<<2) -#define BMC_AUX_MASK (3<<0) -#define BMC_AUX_1 (1<<1) -#define BMC_AUX_0 (1<<0) - -// PORT CC1 -#define CC1_CE_MASK (7<<5) -#define CC1_CE_0 (1<<5) -#define CC1_CE_1 (2<<5) -#define CC1_CE_2 (4<<5) - -#define CC1_LVE (1<<4) -#define CC1_PU_MASK (3<<2) -#define CC1_PU_DISABLE (0<<2) -#define CC1_PU_330uA (1<<2) -#define CC1_PU_180uA (2<<2) -#define CC1_PU_80uA (3<<2) -#define PA_CC1_AI (1<<0) - -#define CC2_CE_MASK (7<<5) -#define CC2_CE_0 (1<<5) -#define CC2_CE_1 (2<<5) -#define CC2_CE_2 (4<<5) - -#define CC2_LVE (1<<4) -#define CC2_PU_MASK (3<<2) -#define CC2_PU_DISABLE (0<<2) -#define CC2_PU_330uA (1<<2) -#define CC2_PU_180uA (2<<2) -#define CC2_PU_80uA (3<<2) -#define PA_CC2_AI (1<<0) @@ -5356,33 +5238,33 @@ typedef struct #if defined(CH32V003) /***************** Bit definition for AFIO_EXTICR register *****************/ -#define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ -#define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ -#define AFIO_EXTICR_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ -#define AFIO_EXTICR_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ -#define AFIO_EXTICR_EXTI4 ((uint16_t)0x0300) /* EXTI 4 configuration */ -#define AFIO_EXTICR_EXTI5 ((uint16_t)0x0C00) /* EXTI 5 configuration */ -#define AFIO_EXTICR_EXTI6 ((uint16_t)0x3000) /* EXTI 6 configuration */ -#define AFIO_EXTICR_EXTI7 ((uint16_t)0xC000) /* EXTI 7 configuration */ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0300) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x3000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint16_t)0xC000) /* EXTI 7 configuration */ -#define AFIO_EXTICR_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ -#define AFIO_EXTICR_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ -#define AFIO_EXTICR_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ -#define AFIO_EXTICR_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ -#define AFIO_EXTICR_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ -#define AFIO_EXTICR_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ -#define AFIO_EXTICR_EXTI4_PC ((uint16_t)0x0200) /* PC[4] pin */ -#define AFIO_EXTICR_EXTI4_PD ((uint16_t)0x0300) /* PD[4] pin */ -#define AFIO_EXTICR_EXTI5_PC ((uint16_t)0x0800) /* PC[5] pin */ -#define AFIO_EXTICR_EXTI5_PD ((uint16_t)0x0C00) /* PD[5] pin */ -#define AFIO_EXTICR_EXTI6_PC ((uint16_t)0x2000) /* PC[6] pin */ -#define AFIO_EXTICR_EXTI6_PD ((uint16_t)0x3000) /* PD[6] pin */ -#define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ -#define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint16_t)0x0200) /* PC[4] pin */ +#define AFIO_EXTICR1_EXTI4_PD ((uint16_t)0x0300) /* PD[4] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint16_t)0x0800) /* PC[5] pin */ +#define AFIO_EXTICR1_EXTI5_PD ((uint16_t)0x0C00) /* PD[5] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint16_t)0x2000) /* PC[6] pin */ +#define AFIO_EXTICR1_EXTI6_PD ((uint16_t)0x3000) /* PD[6] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ +#define AFIO_EXTICR1_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ #endif #if defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) @@ -9507,7 +9389,7 @@ typedef enum #define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ #define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ #define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ -#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */ +#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */ #define OB_STARTMODE_BOOT ((uint16_t)0x0020) /* Start in BOOT area */ #define OB_STARTMODE_USER ((uint16_t)0x0000) /* Start in user area */ @@ -12586,6 +12468,349 @@ typedef volatile unsigned long *PUINT32V; #endif +/* ch32x035_usbpd.h ----------------------------------------------------------*/ + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#if defined(CH32X03x) +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#elif defined(CH641) +#define CC_ALL_SEL (3<<2) /* Select PD communication port ALL*/ +#define CC_SEL_Mask (3<<2) /* Clear PD communication port */ +#define CC_SEL_1 (0<<2) /* Select PD communication port1 */ +#define CC_SEL_2 (1<<2) /* Select PD communication port2 */ +#define CC_SEL_3 (2<<2) /* Select PD communication port3 */ +#define PD_DMA_EN (1<<4) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<5) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<6) /* PD port wake-up level */ +#endif +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#if defined(CH641) +/* USBPD->PORT_CC3 */ +#define CC_CMPO (1<<0) /* CC port comparator analog input */ +#elif defined(CH32X03x) +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#endif +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#if defined(CH32X03x) +#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ +#define USBPD_IN_HVT (1<<9) +#elif defined(CH641) +#define CC_CVS_Mask (3<<5) /* clear CC_CVS*/ +#define CC_CVS_55 (0<<5) /* 00-0.55V */ +#define CC_CVS_22 (1<<5) /* 01-0.22V */ +#define CC_CVS_66 (2<<5) /* 10-0.66V */ +#define CC_CVS_123 (3<<5) /* 11-1.23V */ +#define CC_CE (1<<7) /* Enable the voltage comparator on port CC */ +#endif + +#if defined(CH32X03x) + +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +#elif defined(CH641) + +/********************************************************* + * PD pin PB0/PB1/PB9 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_HVT (1<<19) + +#endif + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#if defined(CH32X03x) + +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_14 +#define PIN_CC2 GPIO_Pin_15 + +#elif defined(CH641) +#define PIN_CC1 GPIO_Pin_0 +#define PIN_CC2 GPIO_Pin_1 +#define PIN_CC3 GPIO_Pin_9 +#endif + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ + +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + /* ch32v00x_wwdg.h -----------------------------------------------------------*/ diff --git a/inc/misc/attic/temp_transition_helper.c b/inc/misc/attic/temp_transition_helper.c index 267e02d..a05b193 100644 --- a/inc/misc/attic/temp_transition_helper.c +++ b/inc/misc/attic/temp_transition_helper.c @@ -1,244 +1,226 @@ -#include #include -#include +#include #include +#include -const char *yes[] = {"SENTINEL_WILL_BE_REPLACED_BY_CMDLINE"}; // "CH32X03x", etc. element 0 is filled in by command-line -const char *no[] = {"CH32V10x", "CH32V30x", "CH32V20x", "CH32X03x", "CH32V003"}; +const char * yes[] = { "SENTINEL_WILL_BE_REPLACED_BY_CMDLINE" }; // "CH32X03x", etc. element 0 is filled in by command-line +const char * no[] = { "CH32V10x", "CH32V30x", "CH32V20x", "CH32X03x", "CH32V003" }; -char *WhitePull(const char **sti) +char * WhitePull( const char ** sti ) { - const char *st = *sti; - int len = 0; - while ((*st == ' ' || *st == '\t' || *st == '(') && *st) - { - st++; - } - const char *sts = st; - while (*st != ' ' && *st != '\t' && *st != '\n' && *st != ')' && *st != '(' && *st != 0) - { - st++; - len++; - } - if (*st == ')') { st++; } - char *ret = malloc(len + 1); - memcpy(ret, sts, len); - ret[len] = 0; - *sti = st; - return ret; + const char * st = *sti; + int len = 0; + while( ( *st == ' ' || *st == '\t' || *st == '(' ) && *st ) { st++; } + const char * sts = st; + while( *st != ' ' && *st != '\t' && *st != '\n' && *st != ')' && *st != '(' && *st != 0 ) { st++; len++; } + if( *st == ')' ) { st++; } + char * ret = malloc( len + 1 ); + memcpy( ret, sts, len ); + ret[len] = 0; + *sti = st; + return ret; } -int NYI(const char *s) +int NYI( const char * s ) { - int ret = 2; - char *wp = WhitePull(&s); - int i; - for (i = 0; i < sizeof(yes) / sizeof(yes[0]); i++) - if (strcmp(yes[i], wp) == 0) ret = 1; - if (ret != 1) - for (i = 0; i < sizeof(no) / sizeof(no[0]); i++) - if (strcmp(no[i], wp) == 0) ret = 0; - free(wp); - return ret; + int ret = 2; + char * wp = WhitePull( &s ); + int i; + for( i = 0; i < sizeof(yes)/sizeof(yes[0]); i++ ) + if( strcmp( yes[i], wp ) == 0 ) ret = 1; + if( ret != 1 ) + for( i = 0; i < sizeof(no)/sizeof(no[0]); i++ ) + if( strcmp( no[i], wp ) == 0 ) ret = 0; + free( wp ); + return ret; } -int EvalSpec(const char *spl) +int EvalSpec( const char * spl ) { - int rsofar = 0; - int i; - int lastv = 0; - int lasto = -1; - int ret = 0; + int rsofar = 0; + int i; + int lastv = 0; + int lasto = -1; + int ret = 0; cont: - char *wp = WhitePull(&spl); - int def = -1; - if (strcmp(wp, "defined") == 0) def = 1; - if (strcmp(wp, "!defined") == 0) def = 2; - if (def < 0) return 2; - char *wpn = WhitePull(&spl); - i = NYI(wpn); - // printf( "SPIN: %s/%s/%d/%d/%d\n", wp, wpn, i, def, lasto ); - if (i == 2) return 2; + char * wp = WhitePull( &spl ); + int def = -1; + if( strcmp( wp, "defined" ) == 0 ) def = 1; + if( strcmp( wp, "!defined" ) == 0 ) def = 2; + if( def < 0 ) return 2; + char * wpn = WhitePull( &spl ); + i = NYI( wpn ); +//printf( "SPIN: %s/%s/%d/%d/%d\n", wp, wpn, i, def, lasto ); + if( i == 2 ) return 2; - if (def == 2) i = !i; + if( def == 2 ) i = !i; - if (lasto == 1) - { - ret = lastv || i; - } - else if (lasto == 2) - ret = lastv && i; - else - ret = i; + if( lasto == 1 ) + { + ret = lastv || i; + } + else if( lasto == 2 ) + ret = lastv && i; + else + ret = i; - char *wpa = WhitePull(&spl); - // printf( "WPA: \"%s\"\n", wpa ); - lastv = ret; - lasto = -1; - // printf( "RET: %d\n", ret ); - if (strcmp(wpa, "||") == 0) - { - lasto = 1; - goto cont; - } - else if (strcmp(wpa, "&&") == 0) - { - lasto = 2; - goto cont; - } - else - return ret; + char * wpa = WhitePull( &spl ); +//printf( "WPA: \"%s\"\n", wpa ); + lastv = ret; + lasto = -1; +//printf( "RET: %d\n", ret ); + if( strcmp( wpa, "||" ) == 0 ) { lasto = 1; goto cont; } + else if( strcmp( wpa, "&&" ) == 0 ) { lasto = 2; goto cont; } + else return ret; } // 0 for no // 1 for yes // 2 for indeterminate -int NoYesInd(const char *preprocc) +int NoYesInd( const char * preprocc ) { - int ret; - int ofs = 0; - if (strncmp(preprocc, "#if ", 4) == 0) ofs = 4; - if (strncmp(preprocc, "#elif ", 6) == 0) ofs = 6; - if (ofs) - { - ret = EvalSpec(preprocc + ofs); - // printf( "SPEC: %d\n", ret ); - } - else if (strncmp(preprocc, "#ifdef ", 7) == 0) - { - const char *ep = preprocc + 6; - char *wp = WhitePull(&ep); - ret = NYI(wp); - free(wp); - } - else if (strncmp(preprocc, "#ifndef ", 8) == 0) - { - const char *ep = preprocc + 6; - char *wp = WhitePull(&ep); - ret = NYI(wp); - if (ret < 2) ret = !ret; - free(wp); - } - else - ret = 2; - // printf( "%d-> %s\n", ret, preprocc ); - return ret; + int ret; + int ofs = 0; + if( strncmp( preprocc, "#if ", 4 ) == 0 ) ofs = 4; + if( strncmp( preprocc, "#elif ", 6 ) == 0 ) ofs = 6; + if( ofs ) + { + ret = EvalSpec( preprocc + ofs ); + //printf( "SPEC: %d\n", ret ); + } + else if( strncmp( preprocc, "#ifdef ", 7 ) == 0 ) + { + const char * ep = preprocc + 6; + char * wp = WhitePull( &ep ); + ret = NYI( wp ); + free( wp ); + } + else if( strncmp( preprocc, "#ifndef ", 8 ) == 0 ) + { + const char * ep = preprocc + 6; + char * wp = WhitePull( &ep ); + ret = NYI( wp ); + if( ret < 2 ) ret = !ret; + free( wp ); + } + else + ret = 2; + //printf( "%d-> %s\n", ret, preprocc ); + return ret; } -const char *sslineis(const char *line, const char *match) +const char * sslineis( const char * line, const char * match ) { - while (*line == ' ' || *line == '\t') - line++; - const char *linestart = line; - while (*line && *match == *line) - { - line++; - match++; - } - if (*match == 0) - return linestart; - else - return 0; + while( *line == ' ' || *line == '\t' ) line++; + const char * linestart = line; + while( *line && *match == *line ) { line++; match++; } + if( *match == 0 ) + return linestart; + else + return 0; } -int main(int argc, char **argv) +int main( int argc, char ** argv ) { - if (argc != 3) - { - fprintf(stderr, "Syntax: transition [#define to trigger on] [file to convert]\nNo'd architectures:\n"); - int i; - for (i = 0; i < sizeof(no) / sizeof(no[0]); i++) - { - fprintf(stderr, "\t%s\n", no[i]); - } - return -1; - } + if( argc != 3 ) + { + fprintf( stderr, "Syntax: transition [#define to trigger on] [file to convert]\nNo'd architectures:\n" ); + int i; + for( i = 0; i < sizeof(no)/sizeof(no[0]); i++ ) + { + fprintf( stderr, "\t%s\n", no[i] ); + } + return -1; + } - yes[0] = argv[1]; + yes[0] = argv[1]; - FILE *f = fopen(argv[2], "r"); - if (!f) - { - fprintf(stderr, "Error: Could not open \"%s\"\n", argv[2]); - return -2; - } - char line[1024]; - char *l; + FILE * f = fopen( argv[2], "r" ); + if( !f ) + { + fprintf( stderr, "Error: Could not open \"%s\"\n", argv[2] ); + return -2; + } + char line[1024]; + char * l; - int depth = 0; - // 0 = no - // 1 = yes - // 2 = indeterminate - // 3 = super no. (I.e. after a true #if clause) - int yesnoind[1024]; - yesnoind[0] = 1; + int depth = 0; - while (l = fgets(line, sizeof(line) - 1, f)) - { - const char *ss = 0; - int nyi = yesnoind[depth]; - int waspre = 0; + // 0 = no + // 1 = yes + // 2 = indeterminate + // 3 = super no. (I.e. after a true #if clause) + int yesnoind[1024]; + yesnoind[0] = 1; - if ((ss = sslineis(line, "#if ")) || (ss = sslineis(line, "#ifdef ")) || (ss = sslineis(line, "#ifndef "))) - { - waspre = 1; - // printf( "CHECK: %d/%s\n", depth, l ); - nyi = NoYesInd(ss); - depth++; - yesnoind[depth] = nyi; - } - else if ((ss = sslineis(line, "#elif "))) - { - if (nyi != 2) - { - waspre = 1; - if (nyi == 1) - { - nyi = 3; - } - else - { - nyi = NoYesInd(ss); - } - // printf( "ELIF check: %s %d\n", ss, nyi ); - yesnoind[depth] = nyi; - } - } - else if ((ss = sslineis(line, "#else"))) - { - if (nyi != 2) - { - waspre = 1; - if (yesnoind[depth] == 1) - nyi = 3; - else - nyi = !yesnoind[depth]; - yesnoind[depth] = nyi; - } - } - else if ((ss = sslineis(line, "#endif"))) - { - waspre = 1; - depth--; - if (depth < 0) - { - fprintf(stderr, "UNTERMD IF\n"); - } - } + while( l = fgets( line, sizeof(line)-1, f ) ) + { + const char * ss = 0; + int nyi = yesnoind[depth]; + int waspre = 0; - int thisv = nyi; - int i; - for (i = 0; i <= depth; i++) - { - // printf( "%d", yesnoind[i] ); - if (yesnoind[i] == 0 || yesnoind[i] == 3) thisv = 0; - } - // printf( ">>%s", l ); + if( (ss = sslineis( line, "#if " ) ) || (ss = sslineis( line, "#ifdef " ) ) || (ss = sslineis( line, "#ifndef " ) ) ) + { + waspre = 1; + //printf( "CHECK: %d/%s\n", depth, l ); + nyi = NoYesInd( ss ); + depth++; + yesnoind[depth] = nyi; + } + else if( (ss = sslineis( line, "#elif " ) ) ) + { + if( nyi != 2 ) + { + waspre = 1; + if( nyi == 1 ) + { + nyi = 3; + } + else + { + nyi = NoYesInd( ss ); + } + //printf( "ELIF check: %s %d\n", ss, nyi ); + yesnoind[depth] = nyi; + } + } + else if( (ss = sslineis( line, "#else" ) ) ) + { + if( nyi != 2 ) + { + waspre = 1; + if( yesnoind[depth] == 1 ) + nyi = 3; + else + nyi = !yesnoind[depth]; + yesnoind[depth] = nyi; + } + } + else if( (ss = sslineis( line, "#endif" ) ) ) + { + waspre = 1; + depth--; + if( depth < 0 ) + { + fprintf( stderr, "UNTERMD IF\n" ); + } + } - if (thisv != 0 && thisv != 3 && (thisv != 1 || !waspre)) - { - printf("%s", l); - } - } + int thisv = nyi; + int i; + for( i = 0; i <= depth; i++ ) + { + //printf( "%d", yesnoind[i] ); + if( yesnoind[i] == 0 || yesnoind[i] == 3 ) thisv = 0; + } + //printf( ">>%s", l ); + + if( thisv != 0 && thisv != 3 && ( thisv != 1 || !waspre ) ) + { + printf( "%s", l ); + } + } } + + diff --git a/inc/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt b/inc/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt new file mode 100644 index 0000000..312ef5b --- /dev/null +++ b/inc/misc/drivers_for_WCH-LinkE/R0-1v3/README.txt @@ -0,0 +1,11 @@ +This only works for the WCH LinkE in RISC-V mode. If your programmer has the BLUE light ON shortly after boot your programmer is in ARM mode. + +Please follow instructions here to convert your programmer to RISC-V mode from ARM mode. + +Basically press-and-hold the ModeS button while plugging in the USB. + +Once powered, it will store that to default. + +The blue light should be OFF. + +Once you are in RISC-V mode, you can install this driver by right-clicking on the driver and saying install. diff --git a/inc/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).cat b/inc/misc/drivers_for_WCH-LinkE/R0-1v3/WCH-Link_(Interface_0).cat new file mode 100644 index 0000000000000000000000000000000000000000..53493be00e17f8ae3ea2fbc95122fd8d7143b9fe GIT binary patch literal 5072 zcmeHLdpwj`A3x9Y%#3@46xA4axt6#@0{=NHV+i4)H7s^ zM6*Qw3WO9X7OGT1p~@MOAlQmffguwrnngrXG?JhLD3o2wkTGTuG(yOeCB#D65X1_E z@(kHgraVE=lupNpZFkd8&fT08Ew?e?#hr-?981XNaG)gzT3H3aabv_uysC^T6cWGC zd@O(ya6rupK;QzL0T0nU;E1{v-~(&axqt&)5rsL@3u+l8 zNdg%AX%CX1u>+w$v>d}xg!&Xo7mHbi%&aNEPSWOraC9jNk_$;jmofu4s0C#hbmMUp zsX+%cRlCF9y=m#o^F-!5gNfvEfx`)BpCecsX+Aup9~U(Y85il~fb`)23#6Mf;yEGx zolwJIb5Q4_6Ix2nhb6g44xfaJWHG3&=qZ791@!);v^;{<5zhP*tY)baIF}>c!~X(Y z&Oe}HEB`A{Gope8#X28@rqmT4D&OcHaX!B6!-%h9Q?!(TioxU{XdEO!IUumGkFq6P z4&q_T3c-s3#^&pUItHGH-msB0=KkZWU)5I+yZUQCKQA^{*1n*ZdbqM`!FbujBfjc{ zJP&)JlLR1Vq?MDz>u?moK5T*BLG-jj&^e-x`Hm7~L?r_$h0y{Sqh4UDc=$1$Vd>jY?h7tt;fLzmJjhBxaE-7!y$|x*+pSrb9 z`Y#f=GrH>$r@>K^BT3dS=+>RBcl;Xbf-aIXyFAtn6h9NSO8`t zBVv#0!XHV&K_CTTAwVm$5kgoqeULcH!FGpN)(7#3gOP&>F|m;TI~39fp^)kjQzSu> zN+~-9E*s)9L@p%N(PDOxk89M?>Xnc~)no!Y9>y^!KN`gp06$ccIf5WCU!o4)7Z(_K zU++=Q=Y2g9XJlU%vLx*O07Kk{f|}77Omcqt#eKozYyuw%li$c z+;-T^*ni~LnKwI@_)m8qY)$)Zpv0@Oby=^Esr= zk;2Kw>_>ZgFX-fLkI2h)n|7!!Liqc~xbg~JW~O?H{f?#8mR(X#O+7R8d7X2mwWSBx z2l+zxVvqe+O9PH#b0vrZ;%@j?A9vztNov0&8qfXD;F$)7_pgrg%rJ^k!1_ znNuU+jhIIb`n9{xrsw-52CZdBhjc8Qq8}bJjvGwncMp5SM>pT{s}g^k*Xe)geNAfe z>3&^%{VOvB-tSuPM11==kE;@`GG~A3@~Eto&0U%)9g|qTt!?wymcrrw#b)}*%IL5cg2fs zR(Bf`MvHV_w$8mce3Ny%+OXSg9P7cO_nSOd7SeV5Yr5+1SNvdX^qAz*GIym-I(j{$ z(56|ruFkUgcBP|++2%R>E7s4`SA1BK+Od;G+iNe!;5g)_{j6=2c&oKH|5WG&z3JYK z^M)o9jd?zCc4}E}M+-EHez9fE=TKhhHpj9r#j6@HHl_L&mk!(bdvw+5DL3b77eBju z;ap#DTDW(2sM*jtY4ybFyWMMT4wherjg$BdQQajA`XZajh{-&Y*?TmURD%>PTwYAp zjDFZ|pWYMk4NO^K__l}%5>AUcJXTSD_f+1lFEP;HGGrjj4CGI3()jzKo>o6$J z(}X1WSKy_Vs!YD4Zo|xlCp0eWUQO{VDh0zTLd~8>1NA-XO_^6G-H1D~_wa;EIWy1L zq`LVLyS;Xjxdzis(oM9M8tzd5S004;pz`e(2>$Y3Wg6bkDwd-j^M7P(R zsZHUrhhx2-jE}q5Ru*c~Br1$I{K>uEvq^KPdi`*~tCn>QNrL-OtN)HWb63tr=|=s* z`ibfR9us?mMbibD#;=R&E3}Ujrc}IKCo%7Ad*D8?lW*3$+CnqFS!>pZviwuI>n8`i zH%u!l(THhZz2n1;`vteH8``2m)_F|bC)4ivX5#j)*tPjGMCnzXMSZ@T7az}2v3pDS zh8&^uSM}Sq4JXf$x2s$yUD|lGu3ofWqnk?5)Y^OVYE7qkzk$z&?z(2bseMuV4$nC8 zj_RT`D0-a2gRSf8qH}$V4>-55^TD+qe+5g8+TtrW)Qa{8t^Qa+dGr-+8wg{rnb)=* zl-x4mWxOh|wK1GTqXvgUIKS%EJTW@=#=!mIcuKQ&uQESog=yJVOOq{a$_(Lfujt{L z?mbGobsqFTS!NPV)STb8iat=Q+dTc^K;zb4b){XNY9~YIhTWN0w0z?kX>J5Y{sv6~>K=9`QU^s1cUhn6vWB%oa3bGCw!rri_f-0L zdju}_8W6Fg zyW8?5l}1mU2z@?yic*hch_q<-j#^Ad9jqyB-F>Cu|=Elxt0Gt&4R!G4b6&uZju>?9&r6$5o~$(5tt_;iK@7}9{}TL*cWQ1<>WpPU=j=q zj-X<>l{AAqTZ%RDO0!5Gs}Potf!lngU@m{sO2lep7b{g<8#+0ivgmY+mZveBtPj7_ zUULOMg~=oI3{D^PwRtK*ZAegq*y+ajwNCC8xVYwCUva~vL7u@!FEO2QwsH^GG{ZPK zar(MMg@|_qZP#?y4tB6JO?A@aOvpFtYQ7J=Vu@R7C3#<^yGrN^b!7INj0Y;f))j8| z_#zA)1BZjOMn2VQHps;=Ai?p;Dii!oZ0D|>GWP?mj$X(cFwq>W3;16~{ z^9m)Lq|wgvtzhCl&h$R(X2!*^9#161Xm%bCvzXg)fXFOIV^(o~-vmx3u*&lM6#twt zI87(8lC!0Ey2Uyqhz>E5fR58L(ZJc4ozfBQn%=}d)787{avIH$^Q;6sf7rE}>oviD zalcuFKXy^;s1?lvdcvm|S{u$DW?6`(=N!*TMN}O`fIjzGCY-3kOvn1m+Pj#;JcWDu zI*Ytx{=cjW-S%fzZA6u4v3KM6sDk{$bG@U`Y>#VYF||vgjO%otx7BgWEN6zX7V&&yCqZ^t z&$VLt#oCAJ99QP}L~gzN95O@S4jElb^RI-CGk=1Qt4I9Z`MC!xX$`r#CxiB@DTkYT fwupma;OAO: - 0: 00a037b3 snez a5,a0 - 4: 40b005b3 neg a1,a1 - 8: 40a00533 neg a0,a0 - -0000000c <.LVL1>: - c: 8d9d sub a1,a1,a5 - e: 8082 ret - -_lshrdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__lshrdi3>: - 0: ca19 beqz a2,16 <.L2> - 2: 02000793 li a5,32 - 6: 8f91 sub a5,a5,a2 - -00000008 <.LVL1>: - 8: 00f04863 bgtz a5,18 <.L3> - c: 1601 add a2,a2,-32 - -0000000e <.LVL2>: - e: 00c5d533 srl a0,a1,a2 - -00000012 <.LVL3>: - 12: 4701 li a4,0 - -00000014 <.L4>: - 14: 85ba mv a1,a4 - -00000016 <.L2>: - 16: 8082 ret - -00000018 <.L3>: - 18: 00c5d733 srl a4,a1,a2 - 1c: 00c55533 srl a0,a0,a2 - -00000020 <.LVL7>: - 20: 00f595b3 sll a1,a1,a5 - -00000024 <.LVL8>: - 24: 8d4d or a0,a0,a1 - 26: b7fd j 14 <.L4> - -_ashldi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ashldi3>: - 0: ca19 beqz a2,16 <.L2> - 2: 02000793 li a5,32 - 6: 8f91 sub a5,a5,a2 - -00000008 <.LVL1>: - 8: 00f04863 bgtz a5,18 <.L3> - c: 1601 add a2,a2,-32 - -0000000e <.LVL2>: - e: 00c515b3 sll a1,a0,a2 - 12: 4701 li a4,0 - -00000014 <.L4>: - 14: 853a mv a0,a4 - -00000016 <.L2>: - 16: 8082 ret - -00000018 <.L3>: - 18: 00c595b3 sll a1,a1,a2 - 1c: 00f557b3 srl a5,a0,a5 - -00000020 <.LVL6>: - 20: 00c51733 sll a4,a0,a2 - 24: 8ddd or a1,a1,a5 - 26: b7fd j 14 <.L4> - -_ashrdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ashrdi3>: - 0: ce01 beqz a2,18 <.L2> - 2: 02000793 li a5,32 - 6: 8f91 sub a5,a5,a2 - -00000008 <.LVL1>: - 8: 00f04963 bgtz a5,1a <.L3> - c: 1601 add a2,a2,-32 - -0000000e <.LVL2>: - e: 41f5d713 sra a4,a1,0x1f - 12: 40c5d533 sra a0,a1,a2 - -00000016 <.L4>: - 16: 85ba mv a1,a4 - -00000018 <.L2>: - 18: 8082 ret - -0000001a <.L3>: - 1a: 40c5d733 sra a4,a1,a2 - 1e: 00c55533 srl a0,a0,a2 - -00000022 <.LVL6>: - 22: 00f595b3 sll a1,a1,a5 - -00000026 <.LVL7>: - 26: 8d4d or a0,a0,a1 - 28: b7fd j 16 <.L4> - -_cmpdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__cmpdi2>: - 0: 4785 li a5,1 - 2: 00b6c763 blt a3,a1,10 <.L2> - 6: 00d59463 bne a1,a3,e <.L3> - a: 00a66363 bltu a2,a0,10 <.L2> - -0000000e <.L3>: - e: 4781 li a5,0 - -00000010 <.L2>: - 10: 4705 li a4,1 - 12: 00d5c763 blt a1,a3,20 <.L4> - 16: 00b69463 bne a3,a1,1e <.L5> - 1a: 00c56363 bltu a0,a2,20 <.L4> - -0000001e <.L5>: - 1e: 4701 li a4,0 - -00000020 <.L4>: - 20: 40e78533 sub a0,a5,a4 - -00000024 <.LVL1>: - 24: 0505 add a0,a0,1 - 26: 8082 ret - -_ucmpdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ucmpdi2>: - 0: 4785 li a5,1 - 2: 00b6e763 bltu a3,a1,10 <.L2> - 6: 00d59463 bne a1,a3,e <.L3> - a: 00a66363 bltu a2,a0,10 <.L2> - -0000000e <.L3>: - e: 4781 li a5,0 - -00000010 <.L2>: - 10: 4705 li a4,1 - 12: 00d5e763 bltu a1,a3,20 <.L4> - 16: 00b69463 bne a3,a1,1e <.L5> - 1a: 00c56363 bltu a0,a2,20 <.L4> - -0000001e <.L5>: - 1e: 4701 li a4,0 - -00000020 <.L4>: - 20: 40e78533 sub a0,a5,a4 - -00000024 <.LVL1>: - 24: 0505 add a0,a0,1 - 26: 8082 ret - -_clear_cache.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__clear_cache>: - 0: 8082 ret - -_trampoline.o: file format elf32-littleriscv - - -__main.o: file format elf32-littleriscv - - -_absvsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__absvsi2>: - 0: 41f55713 sra a4,a0,0x1f - -00000004 <.LVL1>: - 4: 00e506b3 add a3,a0,a4 - 8: 00072613 slti a2,a4,0 - c: 00a6a7b3 slt a5,a3,a0 - 10: 00f60863 beq a2,a5,20 <.L6> - 14: 1151 add sp,sp,-12 - 16: c406 sw ra,8(sp) - 18: 00000097 auipc ra,0x0 - 1c: 000080e7 jalr ra # 18 <.LVL1+0x14> - -00000020 <.L6>: - 20: 00e6c533 xor a0,a3,a4 - -00000024 <.LVL3>: - 24: 8082 ret - -_absvdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__absvdi2>: - 0: 41f5d613 sra a2,a1,0x1f - -00000004 <.LVL1>: - 4: 9532 add a0,a0,a2 - -00000006 <.LVL2>: - 6: 00c537b3 sltu a5,a0,a2 - a: 00b60733 add a4,a2,a1 - e: 973e add a4,a4,a5 - -00000010 <.LVL3>: - 10: 00b64333 xor t1,a2,a1 - 14: 00b747b3 xor a5,a4,a1 - 18: fff34593 not a1,t1 - 1c: 8fed and a5,a5,a1 - 1e: 0007d863 bgez a5,2e <.L5> - 22: 1151 add sp,sp,-12 - 24: c406 sw ra,8(sp) - 26: 00000097 auipc ra,0x0 - 2a: 000080e7 jalr ra # 26 <.LVL3+0x16> - -0000002e <.L5>: - 2e: 8d31 xor a0,a0,a2 - -00000030 <.LVL5>: - 30: 00c745b3 xor a1,a4,a2 - 34: 8082 ret - -_addvsi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__addvsi3>: - 0: 87aa mv a5,a0 - 2: 952e add a0,a0,a1 - -00000004 <.LVL1>: - 4: 00f527b3 slt a5,a0,a5 - -00000008 <.LVL2>: - 8: 0005a593 slti a1,a1,0 - -0000000c <.LVL3>: - c: 00f58863 beq a1,a5,1c <.L6> - 10: 1151 add sp,sp,-12 - 12: c406 sw ra,8(sp) - 14: 00000097 auipc ra,0x0 - 18: 000080e7 jalr ra # 14 <.LVL3+0x8> - -0000001c <.L6>: - 1c: 8082 ret - -_addvdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__addvdi3>: - 0: 872a mv a4,a0 - 2: 9532 add a0,a0,a2 - -00000004 <.LVL1>: - 4: 87ae mv a5,a1 - 6: 00e53733 sltu a4,a0,a4 - a: 95b6 add a1,a1,a3 - c: 8fb5 xor a5,a5,a3 - e: 95ba add a1,a1,a4 - -00000010 <.LVL2>: - 10: 8ead xor a3,a3,a1 - 12: fff7c793 not a5,a5 - 16: 8efd and a3,a3,a5 - 18: 0006d863 bgez a3,28 <.L1> - 1c: 1151 add sp,sp,-12 - 1e: c406 sw ra,8(sp) - 20: 00000097 auipc ra,0x0 - 24: 000080e7 jalr ra # 20 <.LVL2+0x10> - -00000028 <.L1>: - 28: 8082 ret - -_subvsi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__subvsi3>: - 0: 87aa mv a5,a0 - 2: 8d0d sub a0,a0,a1 - -00000004 <.LVL1>: - 4: 00a7a7b3 slt a5,a5,a0 - -00000008 <.LVL2>: - 8: 0005a593 slti a1,a1,0 - -0000000c <.LVL3>: - c: 00f58863 beq a1,a5,1c <.L6> - 10: 1151 add sp,sp,-12 - 12: c406 sw ra,8(sp) - 14: 00000097 auipc ra,0x0 - 18: 000080e7 jalr ra # 14 <.LVL3+0x8> - -0000001c <.L6>: - 1c: 8082 ret - -_subvdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__subvdi3>: - 0: 872a mv a4,a0 - 2: 8d11 sub a0,a0,a2 - -00000004 <.LVL1>: - 4: 87ae mv a5,a1 - 6: 00a73733 sltu a4,a4,a0 - a: 8d95 sub a1,a1,a3 - c: 8d99 sub a1,a1,a4 - -0000000e <.LVL2>: - e: 8fb5 xor a5,a5,a3 - 10: 8ead xor a3,a3,a1 - 12: fff6c693 not a3,a3 - 16: 8ff5 and a5,a5,a3 - 18: 0007d863 bgez a5,28 <.L1> - 1c: 1151 add sp,sp,-12 - 1e: c406 sw ra,8(sp) - 20: 00000097 auipc ra,0x0 - 24: 000080e7 jalr ra # 20 <.LVL2+0x12> - -00000028 <.L1>: - 28: 8082 ret - -_mulvsi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__mulvsi3>: - 0: 1121 add sp,sp,-24 - 2: 01051393 sll t2,a0,0x10 - 6: ca06 sw ra,20(sp) - 8: 4103d393 sra t2,t2,0x10 - c: 01059093 sll ra,a1,0x10 - 10: 40f3d293 sra t0,t2,0xf - 14: 4100d093 sra ra,ra,0x10 - 18: 40f0d313 sra t1,ra,0xf - 1c: 02c2 sll t0,t0,0x10 - 1e: c626 sw s1,12(sp) - 20: 0342 sll t1,t1,0x10 - 22: c822 sw s0,16(sp) - 24: 0102d293 srl t0,t0,0x10 - 28: 01055693 srl a3,a0,0x10 - 2c: 87aa mv a5,a0 - 2e: 872e mv a4,a1 - 30: 4105d613 sra a2,a1,0x10 - 34: 01035313 srl t1,t1,0x10 - 38: 0105d493 srl s1,a1,0x10 - 3c: 08d29c63 bne t0,a3,d4 <.L4> - 40: 00931d63 bne t1,s1,5a <.L5> - 44: 8586 mv a1,ra - -00000046 <.LVL1>: - 46: 851e mv a0,t2 - -00000048 <.LVL2>: - 48: 00000097 auipc ra,0x0 - 4c: 000080e7 jalr ra # 48 <.LVL2> - -00000050 <.L1>: - 50: 40d2 lw ra,20(sp) - 52: 4442 lw s0,16(sp) - 54: 44b2 lw s1,12(sp) - 56: 0161 add sp,sp,24 - 58: 8082 ret - -0000005a <.L5>: - 5a: 86ae mv a3,a1 - 5c: 8432 mv s0,a2 - 5e: 84aa mv s1,a0 - -00000060 <.L6>: - 60: 01079513 sll a0,a5,0x10 - -00000064 <.LVL5>: - 64: 01071593 sll a1,a4,0x10 - -00000068 <.LVL6>: - 68: 81c1 srl a1,a1,0x10 - 6a: 8141 srl a0,a0,0x10 - 6c: c436 sw a3,8(sp) - 6e: 00000097 auipc ra,0x0 - 72: 000080e7 jalr ra # 6e <.LVL6+0x6> - -00000076 <.LVL7>: - 76: 01049713 sll a4,s1,0x10 - 7a: 8341 srl a4,a4,0x10 - 7c: 01041593 sll a1,s0,0x10 - 80: c22a sw a0,4(sp) - 82: 81c1 srl a1,a1,0x10 - 84: 853a mv a0,a4 - 86: c03a sw a4,0(sp) - 88: 00000097 auipc ra,0x0 - 8c: 000080e7 jalr ra # 88 <.LVL7+0x12> - -00000090 <.LVL8>: - 90: 01041793 sll a5,s0,0x10 - 94: 4612 lw a2,4(sp) - 96: 46a2 lw a3,8(sp) - 98: 0007d663 bgez a5,a4 <.L8> - 9c: 4702 lw a4,0(sp) - 9e: 01071413 sll s0,a4,0x10 - a2: 8d01 sub a0,a0,s0 - -000000a4 <.L8>: - a4: 01049793 sll a5,s1,0x10 - a8: 0007d363 bgez a5,ae <.L9> - ac: 8d15 sub a0,a0,a3 - -000000ae <.L9>: - ae: 01065793 srl a5,a2,0x10 - b2: 953e add a0,a0,a5 - b4: 01051793 sll a5,a0,0x10 - b8: 87c1 sra a5,a5,0x10 - ba: 87bd sra a5,a5,0xf - bc: 07c2 sll a5,a5,0x10 - be: 83c1 srl a5,a5,0x10 - c0: 01055713 srl a4,a0,0x10 - c4: 04e79863 bne a5,a4,114 <.L13> - c8: 01061493 sll s1,a2,0x10 - cc: 0542 sll a0,a0,0x10 - ce: 80c1 srl s1,s1,0x10 - d0: 8d45 or a0,a0,s1 - d2: bfbd j 50 <.L1> - -000000d4 <.L4>: - d4: 41055413 sra s0,a0,0x10 - d8: 00931563 bne t1,s1,e2 <.L7> - dc: 86aa mv a3,a0 - de: 84ae mv s1,a1 - e0: b741 j 60 <.L6> - -000000e2 <.L7>: - e2: c236 sw a3,4(sp) - e4: c032 sw a2,0(sp) - e6: 0405 add s0,s0,1 - e8: 00000097 auipc ra,0x0 - ec: 000080e7 jalr ra # e8 <.L7+0x6> - -000000f0 <.LVL10>: - f0: 01041793 sll a5,s0,0x10 - f4: 83c1 srl a5,a5,0x10 - f6: 4705 li a4,1 - f8: 00f76e63 bltu a4,a5,114 <.L13> - fc: 4602 lw a2,0(sp) - fe: 00160413 add s0,a2,1 - 102: 0442 sll s0,s0,0x10 - 104: 8041 srl s0,s0,0x10 - 106: 00876763 bltu a4,s0,114 <.L13> - 10a: 4692 lw a3,4(sp) - 10c: 00969863 bne a3,s1,11c <.L11> - 110: f4a040e3 bgtz a0,50 <.L1> - -00000114 <.L13>: - 114: 00000097 auipc ra,0x0 - 118: 000080e7 jalr ra # 114 <.L13> - -0000011c <.L11>: - 11c: f2054ae3 bltz a0,50 <.L1> - 120: bfd5 j 114 <.L13> - -_mulvdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__mulvdi3>: - 0: 1121 add sp,sp,-24 - 2: c822 sw s0,16(sp) - 4: c626 sw s1,12(sp) - 6: ca06 sw ra,20(sp) - 8: 41f55713 sra a4,a0,0x1f - c: 84aa mv s1,a0 - e: 8432 mv s0,a2 - 10: 41f65793 sra a5,a2,0x1f - 14: 08b71163 bne a4,a1,96 <.L2> - 18: 00d79b63 bne a5,a3,2e <.L3> - 1c: 00000097 auipc ra,0x0 - 20: 000080e7 jalr ra # 1c <__mulvdi3+0x1c> - -00000024 <.L1>: - 24: 40d2 lw ra,20(sp) - 26: 4442 lw s0,16(sp) - 28: 44b2 lw s1,12(sp) - 2a: 0161 add sp,sp,24 - 2c: 8082 ret - -0000002e <.L3>: - 2e: 862a mv a2,a0 - -00000030 <.LVL3>: - 30: c036 sw a3,0(sp) - 32: 8522 mv a0,s0 - -00000034 <.LVL4>: - 34: 4681 li a3,0 - 36: 4581 li a1,0 - 38: 00000097 auipc ra,0x0 - 3c: 000080e7 jalr ra # 38 <.LVL4+0x4> - -00000040 <.LVL5>: - 40: 4302 lw t1,0(sp) - 42: c42a sw a0,8(sp) - 44: c22e sw a1,4(sp) - 46: 8626 mv a2,s1 - 48: 4681 li a3,0 - 4a: 851a mv a0,t1 - 4c: 4581 li a1,0 - 4e: 00000097 auipc ra,0x0 - 52: 000080e7 jalr ra # 4e <.LVL5+0xe> - -00000056 <.LVL6>: - 56: 4302 lw t1,0(sp) - 58: 4792 lw a5,4(sp) - 5a: 4722 lw a4,8(sp) - 5c: 86aa mv a3,a0 - 5e: 862e mv a2,a1 - 60: 00035463 bgez t1,68 <.L5> - 64: 40958633 sub a2,a1,s1 - -00000068 <.L5>: - 68: 0004d963 bgez s1,7a <.L11> - 6c: 408506b3 sub a3,a0,s0 - 70: 00d53533 sltu a0,a0,a3 - 74: 40660633 sub a2,a2,t1 - -00000078 <.L30>: - 78: 8e09 sub a2,a2,a0 - -0000007a <.L11>: - 7a: 00f685b3 add a1,a3,a5 - 7e: 00d5b6b3 sltu a3,a1,a3 - 82: 96b2 add a3,a3,a2 - 84: 41f5d793 sra a5,a1,0x1f - 88: 853a mv a0,a4 - 8a: f8d78de3 beq a5,a3,24 <.L1> - -0000008e <.L8>: - 8e: 00000097 auipc ra,0x0 - 92: 000080e7 jalr ra # 8e <.L8> - -00000096 <.L2>: - 96: 04d79663 bne a5,a3,e2 <.L9> - 9a: c02e sw a1,0(sp) - -0000009c <.LBB4>: - 9c: 4681 li a3,0 - 9e: 4581 li a1,0 - a0: 00000097 auipc ra,0x0 - a4: 000080e7 jalr ra # a0 <.LBB4+0x4> - -000000a8 <.LVL9>: - a8: 4282 lw t0,0(sp) - aa: c42a sw a0,8(sp) - ac: c22e sw a1,4(sp) - ae: 8622 mv a2,s0 - b0: 4681 li a3,0 - b2: 8516 mv a0,t0 - b4: 4581 li a1,0 - b6: 00000097 auipc ra,0x0 - ba: 000080e7 jalr ra # b6 <.LVL9+0xe> - -000000be <.LVL10>: - be: 4282 lw t0,0(sp) - c0: 4792 lw a5,4(sp) - c2: 4722 lw a4,8(sp) - c4: 86aa mv a3,a0 - c6: 862e mv a2,a1 - c8: 0002d463 bgez t0,d0 <.L10> - cc: 40858633 sub a2,a1,s0 - -000000d0 <.L10>: - d0: fa0455e3 bgez s0,7a <.L11> - d4: 409506b3 sub a3,a0,s1 - d8: 00d53533 sltu a0,a0,a3 - dc: 40560633 sub a2,a2,t0 - e0: bf61 j 78 <.L30> - -000000e2 <.L9>: - e2: 0205ce63 bltz a1,11e <.L13> - e6: 0006cf63 bltz a3,104 <.L14> - ea: 00b6e333 or t1,a3,a1 - ee: fa0310e3 bnez t1,8e <.L8> - -000000f2 <.LBB5>: - f2: 4681 li a3,0 - f4: 4581 li a1,0 - f6: 00000097 auipc ra,0x0 - fa: 000080e7 jalr ra # f6 <.LBB5+0x4> - -000000fe <.L25>: - fe: f205d3e3 bgez a1,24 <.L1> - 102: b771 j 8e <.L8> - -00000104 <.L14>: - 104: f5c9 bnez a1,8e <.L8> - 106: 57fd li a5,-1 - 108: f8f693e3 bne a3,a5,8e <.L8> - -0000010c <.LBB7>: - 10c: 4681 li a3,0 - 10e: 00000097 auipc ra,0x0 - 112: 000080e7 jalr ra # 10e <.LBB7+0x2> - -00000116 <.LVL14>: - 116: 8d85 sub a1,a1,s1 - -00000118 <.L27>: - 118: f005c6e3 bltz a1,24 <.L1> - 11c: bf8d j 8e <.L8> - -0000011e <.L13>: - 11e: 0006cd63 bltz a3,138 <.L17> - 122: 57fd li a5,-1 - 124: f6f595e3 bne a1,a5,8e <.L8> - 128: f2bd bnez a3,8e <.L8> - -0000012a <.LBB9>: - 12a: 4581 li a1,0 - 12c: 00000097 auipc ra,0x0 - 130: 000080e7 jalr ra # 12c <.LBB9+0x2> - -00000134 <.LVL16>: - 134: 8d81 sub a1,a1,s0 - 136: b7cd j 118 <.L27> - -00000138 <.L17>: - 138: 00b6f333 and t1,a3,a1 - 13c: 57fd li a5,-1 - 13e: f4f318e3 bne t1,a5,8e <.L8> - 142: 00a667b3 or a5,a2,a0 - 146: d7a1 beqz a5,8e <.L8> - -00000148 <.LBB10>: - 148: 4681 li a3,0 - 14a: 4581 li a1,0 - 14c: 00000097 auipc ra,0x0 - 150: 000080e7 jalr ra # 14c <.LBB10+0x4> - -00000154 <.LVL18>: - 154: 8d85 sub a1,a1,s1 - 156: 8d81 sub a1,a1,s0 - 158: b75d j fe <.L25> - -_negvsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__negvsi2>: - 0: 80000737 lui a4,0x80000 - 4: 00e51863 bne a0,a4,14 <.L1> - 8: 1151 add sp,sp,-12 - a: c406 sw ra,8(sp) - c: 00000097 auipc ra,0x0 - 10: 000080e7 jalr ra # c <__negvsi2+0xc> - -00000014 <.L1>: - 14: 40a00533 neg a0,a0 - -00000018 <.LVL2>: - 18: 8082 ret - -_negvdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__negvdi2>: - 0: 87aa mv a5,a0 - 2: 872e mv a4,a1 - 4: 00f03633 snez a2,a5 - 8: 40b005b3 neg a1,a1 - c: 4681 li a3,0 - e: 40a00533 neg a0,a0 - -00000012 <.LVL1>: - 12: 8d91 sub a1,a1,a2 - 14: e791 bnez a5,20 <.L2> - 16: 800007b7 lui a5,0x80000 - 1a: 00f71363 bne a4,a5,20 <.L2> - 1e: 4685 li a3,1 - -00000020 <.L2>: - 20: c699 beqz a3,2e <.L1> - 22: 1151 add sp,sp,-12 - 24: c406 sw ra,8(sp) - 26: 00000097 auipc ra,0x0 - 2a: 000080e7 jalr ra # 26 <.L2+0x6> - -0000002e <.L1>: - 2e: 8082 ret - -_ctors.o: file format elf32-littleriscv - - -_ffssi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ffssi2>: - 0: cd15 beqz a0,3c <.L5> - -00000002 <.LBB2>: - 2: 40a007b3 neg a5,a0 - 6: 8d7d and a0,a0,a5 - -00000008 <.LVL2>: - 8: 67c1 lui a5,0x10 - -0000000a <.LVL3>: - a: 02f57263 bgeu a0,a5,2e <.L3> - e: 10053793 sltiu a5,a0,256 - 12: 0017c793 xor a5,a5,1 - 16: 078e sll a5,a5,0x3 - -00000018 <.L4>: - 18: 00000737 lui a4,0x0 - 1c: 00f55533 srl a0,a0,a5 - -00000020 <.LVL5>: - 20: 00070713 mv a4,a4 - 24: 972a add a4,a4,a0 - 26: 00074503 lbu a0,0(a4) # 0 <__ffssi2> - 2a: 953e add a0,a0,a5 - -0000002c <.LBE6>: - 2c: 8082 ret - -0000002e <.L3>: - 2e: 01000737 lui a4,0x1000 - 32: 47c1 li a5,16 - 34: fee562e3 bltu a0,a4,18 <.L4> - 38: 47e1 li a5,24 - 3a: bff9 j 18 <.L4> - -0000003c <.L5>: - 3c: 4501 li a0,0 - -0000003e <.LVL8>: - 3e: 8082 ret - -_ffsdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ffsdi2>: - 0: c915 beqz a0,34 <.L2> - 2: 85aa mv a1,a0 - -00000004 <.LVL1>: - 4: 4601 li a2,0 - -00000006 <.L3>: - 6: 40b00733 neg a4,a1 - a: 8f6d and a4,a4,a1 - -0000000c <.LVL3>: - c: 67c1 lui a5,0x10 - e: 02f77863 bgeu a4,a5,3e <.L5> - 12: 10073793 sltiu a5,a4,256 - 16: 0017c793 xor a5,a5,1 - 1a: 078e sll a5,a5,0x3 - -0000001c <.L6>: - 1c: 000006b7 lui a3,0x0 - 20: 00f75733 srl a4,a4,a5 - -00000024 <.LVL5>: - 24: 00068693 mv a3,a3 - 28: 9736 add a4,a4,a3 - 2a: 00074503 lbu a0,0(a4) - -0000002e <.LBE6>: - 2e: 963e add a2,a2,a5 - -00000030 <.LVL6>: - 30: 9532 add a0,a0,a2 - -00000032 <.L1>: - 32: 8082 ret - -00000034 <.L2>: - 34: 852e mv a0,a1 - -00000036 <.LVL9>: - 36: ddf5 beqz a1,32 <.L1> - -00000038 <.LVL10>: - 38: 02000613 li a2,32 - 3c: b7e9 j 6 <.L3> - -0000003e <.L5>: - 3e: 010006b7 lui a3,0x1000 - 42: 47c1 li a5,16 - 44: fcd76ce3 bltu a4,a3,1c <.L6> - 48: 47e1 li a5,24 - 4a: bfc9 j 1c <.L6> - -_clz.o: file format elf32-littleriscv - - -_clzsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__clzsi2>: - 0: 67c1 lui a5,0x10 - 2: 02f57663 bgeu a0,a5,2e <.L2> - 6: 10053793 sltiu a5,a0,256 - a: 0017c793 xor a5,a5,1 - e: 078e sll a5,a5,0x3 - -00000010 <.L3>: - 10: 00000737 lui a4,0x0 - 14: 02000693 li a3,32 - 18: 8e9d sub a3,a3,a5 - 1a: 00f55533 srl a0,a0,a5 - -0000001e <.LVL2>: - 1e: 00070793 mv a5,a4 - -00000022 <.LVL3>: - 22: 97aa add a5,a5,a0 - 24: 0007c503 lbu a0,0(a5) # 10000 <.LASF5+0xfe54> - -00000028 <.LBE3>: - 28: 40a68533 sub a0,a3,a0 - 2c: 8082 ret - -0000002e <.L2>: - 2e: 01000737 lui a4,0x1000 - 32: 47c1 li a5,16 - 34: fce56ee3 bltu a0,a4,10 <.L3> - 38: 47e1 li a5,24 - 3a: bfd9 j 10 <.L3> - -_clzdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__clzdi2>: - 0: c995 beqz a1,34 <.L2> - -00000002 <.LVL1>: - 2: 4501 li a0,0 - -00000004 <.L3>: - 4: 67c1 lui a5,0x10 - 6: 02f5fb63 bgeu a1,a5,3c <.L4> - a: 1005b793 sltiu a5,a1,256 - e: 0017c793 xor a5,a5,1 - 12: 078e sll a5,a5,0x3 - -00000014 <.L5>: - 14: 000006b7 lui a3,0x0 - 18: 02000713 li a4,32 - 1c: 8f1d sub a4,a4,a5 - 1e: 00f5d5b3 srl a1,a1,a5 - -00000022 <.LVL4>: - 22: 00068793 mv a5,a3 - -00000026 <.LVL5>: - 26: 97ae add a5,a5,a1 - 28: 0007c783 lbu a5,0(a5) # 10000 <.LASF16+0xfe25> - 2c: 40f707b3 sub a5,a4,a5 - -00000030 <.LBE3>: - 30: 953e add a0,a0,a5 - -00000032 <.LVL6>: - 32: 8082 ret - -00000034 <.L2>: - 34: 85aa mv a1,a0 - -00000036 <.LVL8>: - 36: 02000513 li a0,32 - -0000003a <.LVL9>: - 3a: b7e9 j 4 <.L3> - -0000003c <.L4>: - 3c: 01000737 lui a4,0x1000 - 40: 47c1 li a5,16 - 42: fce5e9e3 bltu a1,a4,14 <.L5> - 46: 47e1 li a5,24 - 48: b7f1 j 14 <.L5> - -_ctzsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ctzsi2>: - 0: 40a007b3 neg a5,a0 - 4: 8d7d and a0,a0,a5 - -00000006 <.LVL1>: - 6: 67c1 lui a5,0x10 - -00000008 <.LVL2>: - 8: 02f57363 bgeu a0,a5,2e <.L2> - c: 10053793 sltiu a5,a0,256 - 10: 0017c793 xor a5,a5,1 - 14: 078e sll a5,a5,0x3 - -00000016 <.L3>: - 16: 00000737 lui a4,0x0 - 1a: 00f55533 srl a0,a0,a5 - -0000001e <.LVL4>: - 1e: 00070713 mv a4,a4 - 22: 972a add a4,a4,a0 - 24: 00074503 lbu a0,0(a4) # 0 <__ctzsi2> - -00000028 <.LBE4>: - 28: 17fd add a5,a5,-1 # ffff <.LASF5+0xfe43> - -0000002a <.LBE6>: - 2a: 953e add a0,a0,a5 - 2c: 8082 ret - -0000002e <.L2>: - 2e: 01000737 lui a4,0x1000 - 32: 47c1 li a5,16 - 34: fee561e3 bltu a0,a4,16 <.L3> - 38: 47e1 li a5,24 - 3a: bff1 j 16 <.L3> - -_ctzdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ctzdi2>: - 0: 02000613 li a2,32 - 4: c119 beqz a0,a <.L3> - 6: 85aa mv a1,a0 - -00000008 <.LVL1>: - 8: 4601 li a2,0 - -0000000a <.L3>: - a: 40b00733 neg a4,a1 - e: 8f6d and a4,a4,a1 - -00000010 <.LVL3>: - 10: 67c1 lui a5,0x10 - 12: 02f77463 bgeu a4,a5,3a <.L4> - 16: 10073793 sltiu a5,a4,256 - 1a: 0017c793 xor a5,a5,1 - 1e: 078e sll a5,a5,0x3 - -00000020 <.L5>: - 20: 000006b7 lui a3,0x0 - 24: 00f75733 srl a4,a4,a5 - -00000028 <.LVL5>: - 28: 00068693 mv a3,a3 - 2c: 9736 add a4,a4,a3 - 2e: 00074503 lbu a0,0(a4) - -00000032 <.LBE4>: - 32: 17fd add a5,a5,-1 # ffff <.LASF16+0xfe14> - -00000034 <.LVL7>: - 34: 953e add a0,a0,a5 - -00000036 <.LBE6>: - 36: 9532 add a0,a0,a2 - 38: 8082 ret - -0000003a <.L4>: - 3a: 010006b7 lui a3,0x1000 - 3e: 47c1 li a5,16 - 40: fed760e3 bltu a4,a3,20 <.L5> - 44: 47e1 li a5,24 - 46: bfe9 j 20 <.L5> - -_popcount_tab.o: file format elf32-littleriscv - - -_popcountsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__popcountsi2>: - 0: 55555737 lui a4,0x55555 - 4: 00155793 srl a5,a0,0x1 - 8: 55570713 add a4,a4,1365 # 55555555 <.LASF5+0x555553c2> - c: 8ff9 and a5,a5,a4 - e: 8d1d sub a0,a0,a5 - -00000010 <.LVL1>: - 10: 333337b7 lui a5,0x33333 - 14: 33378793 add a5,a5,819 # 33333333 <.LASF5+0x333331a0> - 18: 00f57733 and a4,a0,a5 - 1c: 8109 srl a0,a0,0x2 - -0000001e <.LVL2>: - 1e: 8d7d and a0,a0,a5 - 20: 972a add a4,a4,a0 - -00000022 <.LVL3>: - 22: 00475793 srl a5,a4,0x4 - 26: 97ba add a5,a5,a4 - -00000028 <.LVL4>: - 28: 0f0f1737 lui a4,0xf0f1 - 2c: f0f70713 add a4,a4,-241 # f0f0f0f <.LASF5+0xf0f0d7c> - 30: 8ff9 and a5,a5,a4 - -00000032 <.LVL5>: - 32: 00879513 sll a0,a5,0x8 - -00000036 <.LVL6>: - 36: 953e add a0,a0,a5 - 38: 01051793 sll a5,a0,0x10 - 3c: 953e add a0,a0,a5 - 3e: 8161 srl a0,a0,0x18 - 40: 8082 ret - -_popcountdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__popcountdi2>: - 0: 555557b7 lui a5,0x55555 - 4: 00155713 srl a4,a0,0x1 - 8: 55578793 add a5,a5,1365 # 55555555 <.LASF15+0x55555391> - c: 8f7d and a4,a4,a5 - e: 8d19 sub a0,a0,a4 - -00000010 <.LVL1>: - 10: 0015d713 srl a4,a1,0x1 - 14: 8ff9 and a5,a5,a4 - 16: 8d9d sub a1,a1,a5 - 18: 333337b7 lui a5,0x33333 - 1c: 33378793 add a5,a5,819 # 33333333 <.LASF15+0x3333316f> - 20: 00f576b3 and a3,a0,a5 - 24: 8109 srl a0,a0,0x2 - -00000026 <.LVL3>: - 26: 8d7d and a0,a0,a5 - 28: 00f5f633 and a2,a1,a5 - 2c: 8189 srl a1,a1,0x2 - -0000002e <.LVL4>: - 2e: 96aa add a3,a3,a0 - -00000030 <.LVL5>: - 30: 8dfd and a1,a1,a5 - 32: 962e add a2,a2,a1 - -00000034 <.LVL6>: - 34: 0046d713 srl a4,a3,0x4 - 38: 9736 add a4,a4,a3 - 3a: 00465793 srl a5,a2,0x4 - 3e: 0f0f16b7 lui a3,0xf0f1 - -00000042 <.LVL7>: - 42: f0f68693 add a3,a3,-241 # f0f0f0f <.LASF15+0xf0f0d4b> - 46: 97b2 add a5,a5,a2 - 48: 8f75 and a4,a4,a3 - -0000004a <.LVL8>: - 4a: 8ff5 and a5,a5,a3 - -0000004c <.LVL9>: - 4c: 97ba add a5,a5,a4 - 4e: 00879513 sll a0,a5,0x8 - 52: 953e add a0,a0,a5 - 54: 01051793 sll a5,a0,0x10 - 58: 953e add a0,a0,a5 - 5a: 8161 srl a0,a0,0x18 - 5c: 8082 ret - -_paritysi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__paritysi2>: - 0: 01055793 srl a5,a0,0x10 - 4: 8fa9 xor a5,a5,a0 - -00000006 <.LVL1>: - 6: 0087d513 srl a0,a5,0x8 - a: 8d3d xor a0,a0,a5 - -0000000c <.LVL2>: - c: 00455793 srl a5,a0,0x4 - 10: 8fa9 xor a5,a5,a0 - -00000012 <.LVL3>: - 12: 651d lui a0,0x7 - 14: 8bbd and a5,a5,15 - -00000016 <.LVL4>: - 16: 99650513 add a0,a0,-1642 # 6996 <.LASF5+0x6805> - 1a: 40f55533 sra a0,a0,a5 - 1e: 8905 and a0,a0,1 - 20: 8082 ret - -_paritydi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__paritydi2>: - 0: 8d2d xor a0,a0,a1 - -00000002 <.LVL1>: - 2: 01055793 srl a5,a0,0x10 - 6: 8fa9 xor a5,a5,a0 - -00000008 <.LVL2>: - 8: 0087d713 srl a4,a5,0x8 - c: 8f3d xor a4,a4,a5 - -0000000e <.LVL3>: - e: 00475793 srl a5,a4,0x4 - 12: 8fb9 xor a5,a5,a4 - -00000014 <.LVL4>: - 14: 651d lui a0,0x7 - 16: 8bbd and a5,a5,15 - -00000018 <.LVL5>: - 18: 99650513 add a0,a0,-1642 # 6996 <.LASF15+0x67d4> - 1c: 40f55533 sra a0,a0,a5 - 20: 8905 and a0,a0,1 - 22: 8082 ret - -_powisf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__powisf2>: - 0: 41f5d793 sra a5,a1,0x1f - 4: 00b7c733 xor a4,a5,a1 - 8: 1131 add sp,sp,-20 - a: 8f1d sub a4,a4,a5 - -0000000c <.LVL1>: - c: c622 sw s0,12(sp) - e: c426 sw s1,8(sp) - 10: c806 sw ra,16(sp) - 12: 00177793 and a5,a4,1 - 16: 86aa mv a3,a0 - 18: 84ae mv s1,a1 - 1a: 842a mv s0,a0 - 1c: e789 bnez a5,26 <.L4> - 1e: 000007b7 lui a5,0x0 - 22: 0007a403 lw s0,0(a5) # 0 <__powisf2> - -00000026 <.L4>: - 26: 8305 srl a4,a4,0x1 - 28: e31d bnez a4,4e <.L6> - 2a: 0004dc63 bgez s1,42 <.L1> - 2e: 000007b7 lui a5,0x0 - 32: 0007a503 lw a0,0(a5) # 0 <__powisf2> - 36: 85a2 mv a1,s0 - 38: 00000097 auipc ra,0x0 - 3c: 000080e7 jalr ra # 38 <.L4+0x12> - -00000040 <.LVL4>: - 40: 842a mv s0,a0 - -00000042 <.L1>: - 42: 40c2 lw ra,16(sp) - 44: 8522 mv a0,s0 - 46: 4432 lw s0,12(sp) - 48: 44a2 lw s1,8(sp) - -0000004a <.LVL6>: - 4a: 0151 add sp,sp,20 - 4c: 8082 ret - -0000004e <.L6>: - 4e: 85b6 mv a1,a3 - 50: 8536 mv a0,a3 - 52: c03a sw a4,0(sp) - 54: 00000097 auipc ra,0x0 - 58: 000080e7 jalr ra # 54 <.L6+0x6> - -0000005c <.LVL8>: - 5c: 4702 lw a4,0(sp) - 5e: 86aa mv a3,a0 - -00000060 <.LVL9>: - 60: 00177793 and a5,a4,1 - 64: d3e9 beqz a5,26 <.L4> - -00000066 <.LVL10>: - 66: 85aa mv a1,a0 - 68: c02a sw a0,0(sp) - 6a: 8522 mv a0,s0 - -0000006c <.LVL11>: - 6c: c23a sw a4,4(sp) - 6e: 00000097 auipc ra,0x0 - 72: 000080e7 jalr ra # 6e <.LVL11+0x2> - -00000076 <.LVL12>: - 76: 4712 lw a4,4(sp) - 78: 4682 lw a3,0(sp) - 7a: 842a mv s0,a0 - 7c: b76d j 26 <.L4> - -_powidf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__powidf2>: - 0: 41f65693 sra a3,a2,0x1f - 4: 00c6c333 xor t1,a3,a2 - 8: 1111 add sp,sp,-28 - a: 40d30333 sub t1,t1,a3 - -0000000e <.LVL1>: - e: ca22 sw s0,20(sp) - 10: c826 sw s1,16(sp) - 12: cc06 sw ra,24(sp) - 14: 00137693 and a3,t1,1 - 18: 87aa mv a5,a0 - 1a: 872e mv a4,a1 - 1c: 82b2 mv t0,a2 - 1e: 84aa mv s1,a0 - 20: 842e mv s0,a1 - 22: e699 bnez a3,30 <.L4> - 24: 000006b7 lui a3,0x0 - 28: 0006a483 lw s1,0(a3) # 0 <__powidf2> - 2c: 0046a403 lw s0,4(a3) - -00000030 <.L4>: - 30: 00135313 srl t1,t1,0x1 - 34: 02031963 bnez t1,66 <.L6> - 38: 0202d063 bgez t0,58 <.L1> - 3c: 000007b7 lui a5,0x0 - -00000040 <.LVL4>: - 40: 0007a503 lw a0,0(a5) # 0 <__powidf2> - 44: 0047a583 lw a1,4(a5) - 48: 8626 mv a2,s1 - 4a: 86a2 mv a3,s0 - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <.LVL4+0xc> - -00000054 <.LVL5>: - 54: 84aa mv s1,a0 - -00000056 <.LVL6>: - 56: 842e mv s0,a1 - -00000058 <.L1>: - 58: 40e2 lw ra,24(sp) - 5a: 85a2 mv a1,s0 - 5c: 4452 lw s0,20(sp) - 5e: 8526 mv a0,s1 - 60: 44c2 lw s1,16(sp) - 62: 0171 add sp,sp,28 - 64: 8082 ret - -00000066 <.L6>: - 66: 86ba mv a3,a4 - 68: 863e mv a2,a5 - 6a: 853e mv a0,a5 - 6c: 85ba mv a1,a4 - 6e: c216 sw t0,4(sp) - 70: c01a sw t1,0(sp) - 72: 00000097 auipc ra,0x0 - 76: 000080e7 jalr ra # 72 <.L6+0xc> - -0000007a <.LVL8>: - 7a: 4302 lw t1,0(sp) - 7c: 4292 lw t0,4(sp) - 7e: 87aa mv a5,a0 - 80: 00137693 and a3,t1,1 - 84: 872e mv a4,a1 - -00000086 <.LVL9>: - 86: d6cd beqz a3,30 <.L4> - -00000088 <.LVL10>: - 88: 862a mv a2,a0 - 8a: c22a sw a0,4(sp) - 8c: 86ae mv a3,a1 - 8e: c02e sw a1,0(sp) - 90: 8526 mv a0,s1 - -00000092 <.LVL11>: - 92: 85a2 mv a1,s0 - -00000094 <.LVL12>: - 94: c616 sw t0,12(sp) - 96: c41a sw t1,8(sp) - 98: 00000097 auipc ra,0x0 - 9c: 000080e7 jalr ra # 98 <.LVL12+0x4> - -000000a0 <.LVL13>: - a0: 42b2 lw t0,12(sp) - a2: 4322 lw t1,8(sp) - a4: 4792 lw a5,4(sp) - a6: 4702 lw a4,0(sp) - a8: 84aa mv s1,a0 - -000000aa <.LVL14>: - aa: 842e mv s0,a1 - -000000ac <.LVL15>: - ac: b751 j 30 <.L4> - -_powixf2.o: file format elf32-littleriscv - - -_powitf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__powitf2>: - 0: 41dc lw a5,4(a1) - 2: fa810113 add sp,sp,-88 - 6: c6a6 sw s1,76(sp) - 8: c23e sw a5,4(sp) - a: 41f65793 sra a5,a2,0x1f - e: 00c7c4b3 xor s1,a5,a2 - 12: 8c9d sub s1,s1,a5 - -00000014 <.LVL1>: - 14: c8a2 sw s0,80(sp) - 16: ca86 sw ra,84(sp) - 18: c02a sw a0,0(sp) - 1a: c432 sw a2,8(sp) - 1c: 0014f793 and a5,s1,1 - 20: 4180 lw s0,0(a1) - 22: 0085a283 lw t0,8(a1) - 26: 00c5a383 lw t2,12(a1) - 2a: efa9 bnez a5,84 <.L8> - 2c: 4301 li t1,0 - 2e: 4681 li a3,0 - 30: 4701 li a4,0 - 32: 3fff07b7 lui a5,0x3fff0 - -00000036 <.L4>: - 36: 8085 srl s1,s1,0x1 - 38: e8b9 bnez s1,8e <.L6> - 3a: 4622 lw a2,8(sp) - 3c: 02065763 bgez a2,6a <.L7> - 40: 3fff0637 lui a2,0x3fff0 - 44: dc32 sw a2,56(sp) - 46: 106c add a1,sp,44 - 48: 0870 add a2,sp,28 - 4a: 1868 add a0,sp,60 - 4c: ce1a sw t1,28(sp) - 4e: d036 sw a3,32(sp) - 50: d23a sw a4,36(sp) - 52: d43e sw a5,40(sp) - 54: d602 sw zero,44(sp) - 56: d802 sw zero,48(sp) - 58: da02 sw zero,52(sp) - 5a: 00000097 auipc ra,0x0 - 5e: 000080e7 jalr ra # 5a <.L4+0x24> - -00000062 <.LVL4>: - 62: 5372 lw t1,60(sp) - 64: 4686 lw a3,64(sp) - 66: 4716 lw a4,68(sp) - 68: 47a6 lw a5,72(sp) - -0000006a <.L7>: - 6a: 4602 lw a2,0(sp) - 6c: 40d6 lw ra,84(sp) - 6e: 4446 lw s0,80(sp) - 70: 00662023 sw t1,0(a2) # 3fff0000 <.LASF5+0x3ffefe60> - 74: c254 sw a3,4(a2) - 76: c618 sw a4,8(a2) - 78: c65c sw a5,12(a2) - 7a: 44b6 lw s1,76(sp) - -0000007c <.LVL5>: - 7c: 8532 mv a0,a2 - 7e: 05810113 add sp,sp,88 - -00000082 <.LVL6>: - 82: 8082 ret - -00000084 <.L8>: - 84: 4692 lw a3,4(sp) - 86: 8322 mv t1,s0 - 88: 8716 mv a4,t0 - 8a: 879e mv a5,t2 - 8c: b76d j 36 <.L4> - -0000008e <.L6>: - 8e: cc3e sw a5,24(sp) - 90: 4792 lw a5,4(sp) - -00000092 <.LVL9>: - 92: 0870 add a2,sp,28 - 94: 106c add a1,sp,44 - 96: 1868 add a0,sp,60 - 98: ca3a sw a4,20(sp) - 9a: c836 sw a3,16(sp) - 9c: c61a sw t1,12(sp) - 9e: d622 sw s0,44(sp) - a0: d83e sw a5,48(sp) - a2: da16 sw t0,52(sp) - a4: dc1e sw t2,56(sp) - a6: ce22 sw s0,28(sp) - a8: d03e sw a5,32(sp) - aa: d216 sw t0,36(sp) - ac: d41e sw t2,40(sp) - ae: 00000097 auipc ra,0x0 - b2: 000080e7 jalr ra # ae <.LVL9+0x1c> - -000000b6 <.LVL10>: - b6: 4786 lw a5,64(sp) - b8: 0014f613 and a2,s1,1 - bc: 5472 lw s0,60(sp) - be: c23e sw a5,4(sp) - c0: 4296 lw t0,68(sp) - c2: 43a6 lw t2,72(sp) - -000000c4 <.LVL11>: - c4: 4332 lw t1,12(sp) - c6: 46c2 lw a3,16(sp) - c8: 4752 lw a4,20(sp) - ca: 47e2 lw a5,24(sp) - -000000cc <.LVL12>: - cc: d62d beqz a2,36 <.L4> - ce: dc3e sw a5,56(sp) - d0: 4792 lw a5,4(sp) - d2: 0870 add a2,sp,28 - d4: 106c add a1,sp,44 - d6: 1868 add a0,sp,60 - d8: d61a sw t1,44(sp) - da: d836 sw a3,48(sp) - dc: da3a sw a4,52(sp) - de: d03e sw a5,32(sp) - e0: d216 sw t0,36(sp) - e2: c816 sw t0,16(sp) - -000000e4 <.LVL13>: - e4: d41e sw t2,40(sp) - e6: c61e sw t2,12(sp) - e8: ce22 sw s0,28(sp) - ea: 00000097 auipc ra,0x0 - ee: 000080e7 jalr ra # ea <.LVL13+0x6> - -000000f2 <.LVL14>: - f2: 5372 lw t1,60(sp) - f4: 4686 lw a3,64(sp) - f6: 4716 lw a4,68(sp) - f8: 47a6 lw a5,72(sp) - fa: 42c2 lw t0,16(sp) - fc: 43b2 lw t2,12(sp) - -000000fe <.LVL15>: - fe: bf25 j 36 <.L4> - -_mulhc3.o: file format elf32-littleriscv - - -_mulsc3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__mulsc3>: - 0: fc410113 add sp,sp,-60 - 4: c02e sw a1,0(sp) - 6: 85b2 mv a1,a2 - -00000008 <.LVL1>: - 8: dc06 sw ra,56(sp) - a: c232 sw a2,4(sp) - c: c436 sw a3,8(sp) - e: da22 sw s0,52(sp) - 10: d826 sw s1,48(sp) - 12: c62a sw a0,12(sp) - 14: 00000097 auipc ra,0x0 - 18: 000080e7 jalr ra # 14 <.LVL1+0xc> - -0000001c <.LVL2>: - 1c: 45a2 lw a1,8(sp) - 1e: d02a sw a0,32(sp) - -00000020 <.LVL3>: - 20: 4502 lw a0,0(sp) - -00000022 <.LVL4>: - 22: 00000097 auipc ra,0x0 - 26: 000080e7 jalr ra # 22 <.LVL4> - -0000002a <.LVL5>: - 2a: 45a2 lw a1,8(sp) - 2c: d22a sw a0,36(sp) - -0000002e <.LVL6>: - 2e: 4532 lw a0,12(sp) - -00000030 <.LVL7>: - 30: 00000097 auipc ra,0x0 - 34: 000080e7 jalr ra # 30 <.LVL7> - -00000038 <.LVL8>: - 38: 4582 lw a1,0(sp) - 3a: d42a sw a0,40(sp) - -0000003c <.LVL9>: - 3c: 4512 lw a0,4(sp) - -0000003e <.LVL10>: - 3e: 00000097 auipc ra,0x0 - 42: 000080e7 jalr ra # 3e <.LVL10> - -00000046 <.LVL11>: - 46: 5592 lw a1,36(sp) - 48: d62a sw a0,44(sp) - -0000004a <.LVL12>: - 4a: 5502 lw a0,32(sp) - -0000004c <.LVL13>: - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <.LVL13> - -00000054 <.LVL14>: - 54: 55b2 lw a1,44(sp) - 56: ca2a sw a0,20(sp) - -00000058 <.LVL15>: - 58: 5522 lw a0,40(sp) - -0000005a <.LVL16>: - 5a: 00000097 auipc ra,0x0 - 5e: 000080e7 jalr ra # 5a <.LVL16> - -00000062 <.LVL17>: - 62: 45d2 lw a1,20(sp) - 64: cc2a sw a0,24(sp) - -00000066 <.LVL18>: - 66: 852e mv a0,a1 - -00000068 <.LVL19>: - 68: 00000097 auipc ra,0x0 - 6c: 000080e7 jalr ra # 68 <.LVL19> - -00000070 <.LVL20>: - 70: 30050063 beqz a0,370 <.L2> - 74: 45e2 lw a1,24(sp) - 76: 852e mv a0,a1 - 78: 00000097 auipc ra,0x0 - 7c: 000080e7 jalr ra # 78 <.LVL20+0x8> - -00000080 <.LVL21>: - 80: 2e050863 beqz a0,370 <.L2> - -00000084 <.LBB2>: - 84: 4732 lw a4,12(sp) - 86: 800007b7 lui a5,0x80000 - 8a: fff7c793 not a5,a5 - 8e: 00f774b3 and s1,a4,a5 - 92: 00000437 lui s0,0x0 - 96: 4702 lw a4,0(sp) - 98: 00042583 lw a1,0(s0) # 0 <__mulsc3> - 9c: 8526 mv a0,s1 - 9e: 8ff9 and a5,a5,a4 - a0: c83e sw a5,16(sp) - a2: 00000097 auipc ra,0x0 - a6: 000080e7 jalr ra # a2 <.LBB2+0x1e> - -000000aa <.LVL23>: - aa: e911 bnez a0,be <.L45> - ac: 00042583 lw a1,0(s0) - b0: 8526 mv a0,s1 - b2: 00000097 auipc ra,0x0 - b6: 000080e7 jalr ra # b2 <.LVL23+0x8> - -000000ba <.LVL24>: - ba: 02a04563 bgtz a0,e4 <.L5> - -000000be <.L45>: - be: 00042583 lw a1,0(s0) - c2: 4542 lw a0,16(sp) - c4: 00000097 auipc ra,0x0 - c8: 000080e7 jalr ra # c4 <.L45+0x6> - -000000cc <.LVL25>: - cc: ed75 bnez a0,1c8 <.L41> - ce: 000007b7 lui a5,0x0 - d2: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - d6: 4542 lw a0,16(sp) - d8: 00000097 auipc ra,0x0 - dc: 000080e7 jalr ra # d8 <.LVL25+0xc> - -000000e0 <.LVL26>: - e0: 0ea05463 blez a0,1c8 <.L41> - -000000e4 <.L5>: - e4: 000007b7 lui a5,0x0 - e8: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - ec: 8526 mv a0,s1 - ee: 4405 li s0,1 - f0: 00000097 auipc ra,0x0 - f4: 000080e7 jalr ra # f0 <.L5+0xc> - -000000f8 <.LVL27>: - f8: ed09 bnez a0,112 <.L8> - fa: 000007b7 lui a5,0x0 - fe: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 102: 8526 mv a0,s1 - 104: 00000097 auipc ra,0x0 - 108: 000080e7 jalr ra # 104 <.LVL27+0xc> - -0000010c <.LVL28>: - 10c: 00a05363 blez a0,112 <.L8> - 110: 4401 li s0,0 - -00000112 <.L8>: - 112: 00144513 xor a0,s0,1 - 116: 8905 and a0,a0,1 - 118: 00000097 auipc ra,0x0 - 11c: 000080e7 jalr ra # 118 <.L8+0x6> - -00000120 <.LVL29>: - 120: 4732 lw a4,12(sp) - 122: 800007b7 lui a5,0x80000 - 126: 4405 li s0,1 - 128: 8f7d and a4,a4,a5 - 12a: fff7c793 not a5,a5 - 12e: 8fe9 and a5,a5,a0 - 130: 8fd9 or a5,a5,a4 - 132: c63e sw a5,12(sp) - -00000134 <.LVL30>: - 134: 000007b7 lui a5,0x0 - 138: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 13c: 4542 lw a0,16(sp) - -0000013e <.LVL31>: - 13e: 00000097 auipc ra,0x0 - 142: 000080e7 jalr ra # 13e <.LVL31> - -00000146 <.LVL32>: - 146: ed09 bnez a0,160 <.L9> - 148: 000007b7 lui a5,0x0 - 14c: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 150: 4542 lw a0,16(sp) - 152: 00000097 auipc ra,0x0 - 156: 000080e7 jalr ra # 152 <.LVL32+0xc> - -0000015a <.LVL33>: - 15a: 00a05363 blez a0,160 <.L9> - 15e: 4401 li s0,0 - -00000160 <.L9>: - 160: 00144513 xor a0,s0,1 - 164: 8905 and a0,a0,1 - 166: 00000097 auipc ra,0x0 - 16a: 000080e7 jalr ra # 166 <.L9+0x6> - -0000016e <.LVL34>: - 16e: 4702 lw a4,0(sp) - 170: 800007b7 lui a5,0x80000 - 174: 4592 lw a1,4(sp) - 176: 8f7d and a4,a4,a5 - 178: fff7c793 not a5,a5 - 17c: 8fe9 and a5,a5,a0 - 17e: 8fd9 or a5,a5,a4 - 180: 852e mv a0,a1 - 182: c03e sw a5,0(sp) - -00000184 <.LVL35>: - 184: 00000097 auipc ra,0x0 - 188: 000080e7 jalr ra # 184 <.LVL35> - -0000018c <.LVL36>: - 18c: c919 beqz a0,1a2 <.L10> - 18e: 4712 lw a4,4(sp) - 190: 00000793 li a5,0 - 194: 00075663 bgez a4,1a0 <.L12> - 198: 000007b7 lui a5,0x0 - 19c: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -000001a0 <.L12>: - 1a0: c23e sw a5,4(sp) - -000001a2 <.L10>: - 1a2: 45a2 lw a1,8(sp) - 1a4: 852e mv a0,a1 - 1a6: 00000097 auipc ra,0x0 - 1aa: 000080e7 jalr ra # 1a6 <.L10+0x4> - -000001ae <.LVL38>: - 1ae: c919 beqz a0,1c4 <.L82> - 1b0: 4722 lw a4,8(sp) - 1b2: 00000793 li a5,0 - 1b6: 00075663 bgez a4,1c2 <.L14> - 1ba: 000007b7 lui a5,0x0 - 1be: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -000001c2 <.L14>: - 1c2: c43e sw a5,8(sp) - -000001c4 <.L82>: - 1c4: 4485 li s1,1 - 1c6: a011 j 1ca <.L7> - -000001c8 <.L41>: - 1c8: 4481 li s1,0 - -000001ca <.L7>: - 1ca: 4712 lw a4,4(sp) - 1cc: 800007b7 lui a5,0x80000 - 1d0: fff7c793 not a5,a5 - 1d4: 8f7d and a4,a4,a5 - 1d6: c83a sw a4,16(sp) - 1d8: 00000437 lui s0,0x0 - 1dc: 4722 lw a4,8(sp) - 1de: 00042583 lw a1,0(s0) # 0 <__mulsc3> - 1e2: 4542 lw a0,16(sp) - 1e4: 8ff9 and a5,a5,a4 - 1e6: ce3e sw a5,28(sp) - 1e8: 00000097 auipc ra,0x0 - 1ec: 000080e7 jalr ra # 1e8 <.L7+0x1e> - -000001f0 <.LVL42>: - 1f0: e911 bnez a0,204 <.L48> - 1f2: 00042583 lw a1,0(s0) - 1f6: 4542 lw a0,16(sp) - 1f8: 00000097 auipc ra,0x0 - 1fc: 000080e7 jalr ra # 1f8 <.LVL42+0x8> - -00000200 <.LVL43>: - 200: 02a04663 bgtz a0,22c <.L15> - -00000204 <.L48>: - 204: 00042583 lw a1,0(s0) - 208: 4572 lw a0,28(sp) - 20a: 00000097 auipc ra,0x0 - 20e: 000080e7 jalr ra # 20a <.L48+0x6> - -00000212 <.LVL44>: - 212: 16051763 bnez a0,380 <.L17> - 216: 000007b7 lui a5,0x0 - 21a: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 21e: 4572 lw a0,28(sp) - 220: 00000097 auipc ra,0x0 - 224: 000080e7 jalr ra # 220 <.LVL44+0xe> - -00000228 <.LVL45>: - 228: 14a05c63 blez a0,380 <.L17> - -0000022c <.L15>: - 22c: 000004b7 lui s1,0x0 - -00000230 <.LVL46>: - 230: 0004a583 lw a1,0(s1) # 0 <__mulsc3> - 234: 4542 lw a0,16(sp) - 236: 4405 li s0,1 - 238: 00000097 auipc ra,0x0 - 23c: 000080e7 jalr ra # 238 <.LVL46+0x8> - -00000240 <.LVL47>: - 240: e919 bnez a0,256 <.L18> - 242: 0004a583 lw a1,0(s1) - 246: 4542 lw a0,16(sp) - 248: 00000097 auipc ra,0x0 - 24c: 000080e7 jalr ra # 248 <.LVL47+0x8> - -00000250 <.LVL48>: - 250: 00a05363 blez a0,256 <.L18> - 254: 4401 li s0,0 - -00000256 <.L18>: - 256: 00144513 xor a0,s0,1 - 25a: 8905 and a0,a0,1 - 25c: 00000097 auipc ra,0x0 - 260: 000080e7 jalr ra # 25c <.L18+0x6> - -00000264 <.LVL49>: - 264: 4712 lw a4,4(sp) - 266: 800007b7 lui a5,0x80000 - 26a: 0004a583 lw a1,0(s1) - 26e: 8f7d and a4,a4,a5 - 270: fff7c793 not a5,a5 - 274: 8fe9 and a5,a5,a0 - 276: 4572 lw a0,28(sp) - 278: 8fd9 or a5,a5,a4 - 27a: c23e sw a5,4(sp) - -0000027c <.LVL50>: - 27c: 4405 li s0,1 - 27e: 00000097 auipc ra,0x0 - 282: 000080e7 jalr ra # 27e <.LVL50+0x2> - -00000286 <.LVL51>: - 286: ed09 bnez a0,2a0 <.L19> - 288: 000007b7 lui a5,0x0 - 28c: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 290: 4572 lw a0,28(sp) - 292: 00000097 auipc ra,0x0 - 296: 000080e7 jalr ra # 292 <.LVL51+0xc> - -0000029a <.LVL52>: - 29a: 00a05363 blez a0,2a0 <.L19> - 29e: 4401 li s0,0 - -000002a0 <.L19>: - 2a0: 00144513 xor a0,s0,1 - 2a4: 8905 and a0,a0,1 - 2a6: 00000097 auipc ra,0x0 - 2aa: 000080e7 jalr ra # 2a6 <.L19+0x6> - -000002ae <.LVL53>: - 2ae: 4722 lw a4,8(sp) - 2b0: 800007b7 lui a5,0x80000 - 2b4: 45b2 lw a1,12(sp) - 2b6: 8f7d and a4,a4,a5 - 2b8: fff7c793 not a5,a5 - 2bc: 8fe9 and a5,a5,a0 - 2be: 8fd9 or a5,a5,a4 - 2c0: 852e mv a0,a1 - 2c2: c43e sw a5,8(sp) - -000002c4 <.LVL54>: - 2c4: 00000097 auipc ra,0x0 - 2c8: 000080e7 jalr ra # 2c4 <.LVL54> - -000002cc <.LVL55>: - 2cc: c919 beqz a0,2e2 <.L20> - 2ce: 4732 lw a4,12(sp) - 2d0: 00000793 li a5,0 - 2d4: 00075663 bgez a4,2e0 <.L22> - 2d8: 000007b7 lui a5,0x0 - 2dc: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -000002e0 <.L22>: - 2e0: c63e sw a5,12(sp) - -000002e2 <.L20>: - 2e2: 4582 lw a1,0(sp) - 2e4: 852e mv a0,a1 - 2e6: 00000097 auipc ra,0x0 - 2ea: 000080e7 jalr ra # 2e6 <.L20+0x4> - -000002ee <.LVL57>: - 2ee: c919 beqz a0,304 <.L23> - 2f0: 4702 lw a4,0(sp) - 2f2: 00000793 li a5,0 - 2f6: 00075663 bgez a4,302 <.L25> - 2fa: 000007b7 lui a5,0x0 - 2fe: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -00000302 <.L25>: - 302: c03e sw a5,0(sp) - -00000304 <.L23>: - 304: 4592 lw a1,4(sp) - 306: 4532 lw a0,12(sp) - 308: 000004b7 lui s1,0x0 - 30c: 00000097 auipc ra,0x0 - 310: 000080e7 jalr ra # 30c <.L23+0x8> - -00000314 <.LVL59>: - 314: 842a mv s0,a0 - 316: 45a2 lw a1,8(sp) - 318: 4502 lw a0,0(sp) - 31a: 00000097 auipc ra,0x0 - 31e: 000080e7 jalr ra # 31a <.LVL59+0x6> - -00000322 <.LVL60>: - 322: 85aa mv a1,a0 - 324: 8522 mv a0,s0 - 326: 00000097 auipc ra,0x0 - 32a: 000080e7 jalr ra # 326 <.LVL60+0x4> - -0000032e <.LVL61>: - 32e: 0004a583 lw a1,0(s1) # 0 <__mulsc3> - 332: 00000097 auipc ra,0x0 - 336: 000080e7 jalr ra # 332 <.LVL61+0x4> - -0000033a <.LVL62>: - 33a: 45a2 lw a1,8(sp) - 33c: ca2a sw a0,20(sp) - -0000033e <.LVL63>: - 33e: 4532 lw a0,12(sp) - -00000340 <.LVL64>: - 340: 00000097 auipc ra,0x0 - 344: 000080e7 jalr ra # 340 <.LVL64> - -00000348 <.LVL65>: - 348: 4592 lw a1,4(sp) - 34a: 842a mv s0,a0 - 34c: 4502 lw a0,0(sp) - 34e: 00000097 auipc ra,0x0 - 352: 000080e7 jalr ra # 34e <.LVL65+0x6> - -00000356 <.LVL66>: - 356: 85aa mv a1,a0 - 358: 8522 mv a0,s0 - 35a: 00000097 auipc ra,0x0 - 35e: 000080e7 jalr ra # 35a <.LVL66+0x4> - -00000362 <.LVL67>: - 362: 0004a583 lw a1,0(s1) - 366: 00000097 auipc ra,0x0 - 36a: 000080e7 jalr ra # 366 <.LVL67+0x4> - -0000036e <.LVL68>: - 36e: cc2a sw a0,24(sp) - -00000370 <.L2>: - 370: 50e2 lw ra,56(sp) - 372: 5452 lw s0,52(sp) - 374: 4552 lw a0,20(sp) - 376: 45e2 lw a1,24(sp) - 378: 54c2 lw s1,48(sp) - 37a: 03c10113 add sp,sp,60 - -0000037e <.LVL70>: - 37e: 8082 ret - -00000380 <.L17>: - 380: f0d1 bnez s1,304 <.L23> - 382: 5782 lw a5,32(sp) - 384: 000004b7 lui s1,0x0 - -00000388 <.LVL72>: - 388: 0004a583 lw a1,0(s1) # 0 <__mulsc3> - 38c: 00179413 sll s0,a5,0x1 - 390: 8005 srl s0,s0,0x1 - 392: 8522 mv a0,s0 - 394: 00000097 auipc ra,0x0 - 398: 000080e7 jalr ra # 394 <.LVL72+0xc> - -0000039c <.LVL73>: - 39c: e911 bnez a0,3b0 <.L51> - 39e: 0004a583 lw a1,0(s1) - 3a2: 8522 mv a0,s0 - 3a4: 00000097 auipc ra,0x0 - 3a8: 000080e7 jalr ra # 3a4 <.LVL73+0x8> - -000003ac <.LVL74>: - 3ac: 08a04763 bgtz a0,43a <.L26> - -000003b0 <.L51>: - 3b0: 5792 lw a5,36(sp) - 3b2: 0004a583 lw a1,0(s1) - 3b6: 00179413 sll s0,a5,0x1 - 3ba: 8005 srl s0,s0,0x1 - 3bc: 8522 mv a0,s0 - 3be: 00000097 auipc ra,0x0 - 3c2: 000080e7 jalr ra # 3be <.L51+0xe> - -000003c6 <.LVL75>: - 3c6: ed01 bnez a0,3de <.L52> - 3c8: 000007b7 lui a5,0x0 - 3cc: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 3d0: 8522 mv a0,s0 - 3d2: 00000097 auipc ra,0x0 - 3d6: 000080e7 jalr ra # 3d2 <.LVL75+0xc> - -000003da <.LVL76>: - 3da: 06a04063 bgtz a0,43a <.L26> - -000003de <.L52>: - 3de: 57a2 lw a5,40(sp) - 3e0: 0004a583 lw a1,0(s1) - 3e4: 00179413 sll s0,a5,0x1 - 3e8: 8005 srl s0,s0,0x1 - 3ea: 8522 mv a0,s0 - 3ec: 00000097 auipc ra,0x0 - 3f0: 000080e7 jalr ra # 3ec <.L52+0xe> - -000003f4 <.LVL77>: - 3f4: ed01 bnez a0,40c <.L53> - 3f6: 000007b7 lui a5,0x0 - 3fa: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 3fe: 8522 mv a0,s0 - 400: 00000097 auipc ra,0x0 - 404: 000080e7 jalr ra # 400 <.LVL77+0xc> - -00000408 <.LVL78>: - 408: 02a04963 bgtz a0,43a <.L26> - -0000040c <.L53>: - 40c: 57b2 lw a5,44(sp) - 40e: 0004a583 lw a1,0(s1) - 412: 00179413 sll s0,a5,0x1 - 416: 8005 srl s0,s0,0x1 - 418: 8522 mv a0,s0 - 41a: 00000097 auipc ra,0x0 - 41e: 000080e7 jalr ra # 41a <.L53+0xe> - -00000422 <.LVL79>: - 422: f539 bnez a0,370 <.L2> - 424: 000007b7 lui a5,0x0 - 428: 0007a583 lw a1,0(a5) # 0 <__mulsc3> - 42c: 8522 mv a0,s0 - 42e: 00000097 auipc ra,0x0 - 432: 000080e7 jalr ra # 42e <.LVL79+0xc> - -00000436 <.LVL80>: - 436: f2a05de3 blez a0,370 <.L2> - -0000043a <.L26>: - 43a: 45b2 lw a1,12(sp) - 43c: 852e mv a0,a1 - 43e: 00000097 auipc ra,0x0 - 442: 000080e7 jalr ra # 43e <.L26+0x4> - -00000446 <.LVL81>: - 446: c919 beqz a0,45c <.L30> - 448: 4732 lw a4,12(sp) - 44a: 00000793 li a5,0 - 44e: 00075663 bgez a4,45a <.L32> - 452: 000007b7 lui a5,0x0 - 456: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -0000045a <.L32>: - 45a: c63e sw a5,12(sp) - -0000045c <.L30>: - 45c: 4582 lw a1,0(sp) - 45e: 852e mv a0,a1 - 460: 00000097 auipc ra,0x0 - 464: 000080e7 jalr ra # 460 <.L30+0x4> - -00000468 <.LVL83>: - 468: c919 beqz a0,47e <.L33> - 46a: 4702 lw a4,0(sp) - 46c: 00000793 li a5,0 - 470: 00075663 bgez a4,47c <.L35> - 474: 000007b7 lui a5,0x0 - 478: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -0000047c <.L35>: - 47c: c03e sw a5,0(sp) - -0000047e <.L33>: - 47e: 4592 lw a1,4(sp) - 480: 852e mv a0,a1 - 482: 00000097 auipc ra,0x0 - 486: 000080e7 jalr ra # 482 <.L33+0x4> - -0000048a <.LVL85>: - 48a: c919 beqz a0,4a0 <.L36> - 48c: 4712 lw a4,4(sp) - 48e: 00000793 li a5,0 - 492: 00075663 bgez a4,49e <.L38> - 496: 000007b7 lui a5,0x0 - 49a: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -0000049e <.L38>: - 49e: c23e sw a5,4(sp) - -000004a0 <.L36>: - 4a0: 45a2 lw a1,8(sp) - 4a2: 852e mv a0,a1 - 4a4: 00000097 auipc ra,0x0 - 4a8: 000080e7 jalr ra # 4a4 <.L36+0x4> - -000004ac <.LVL87>: - 4ac: e4050ce3 beqz a0,304 <.L23> - 4b0: 4722 lw a4,8(sp) - 4b2: 00000793 li a5,0 - 4b6: 00075663 bgez a4,4c2 <.L40> - 4ba: 000007b7 lui a5,0x0 - 4be: 0007a783 lw a5,0(a5) # 0 <__mulsc3> - -000004c2 <.L40>: - 4c2: c43e sw a5,8(sp) - -000004c4 <.LVL88>: - 4c4: b581 j 304 <.L23> - -_muldc3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__muldc3>: - 0: 7119 add sp,sp,-128 - 2: c83e sw a5,16(sp) - 4: debe sw a5,124(sp) - 6: 478a lw a5,128(sp) - 8: c232 sw a2,4(sp) - a: c436 sw a3,8(sp) - c: ca3e sw a5,20(sp) - e: 47d2 lw a5,20(sp) - 10: c63a sw a4,12(sp) - 12: 4742 lw a4,16(sp) - 14: 86be mv a3,a5 - -00000016 <.LVL1>: - 16: 4792 lw a5,4(sp) - 18: 863a mv a2,a4 - 1a: c2aa sw a0,68(sp) - 1c: c02e sw a1,0(sp) - 1e: 852e mv a0,a1 - 20: 85be mv a1,a5 - -00000022 <.LVL3>: - 22: dc86 sw ra,120(sp) - 24: daa2 sw s0,116(sp) - 26: d8a6 sw s1,112(sp) - 28: 00000097 auipc ra,0x0 - 2c: 000080e7 jalr ra # 28 <.LVL3+0x6> - -00000030 <.LVL4>: - 30: 4722 lw a4,8(sp) - 32: 47b2 lw a5,12(sp) - 34: 449a lw s1,132(sp) - 36: 442a lw s0,136(sp) - 38: c4aa sw a0,72(sp) - 3a: d0ae sw a1,96(sp) - -0000003c <.LVL5>: - 3c: 8626 mv a2,s1 - 3e: 86a2 mv a3,s0 - 40: 853a mv a0,a4 - -00000042 <.LVL6>: - 42: 85be mv a1,a5 - -00000044 <.LVL7>: - 44: 00000097 auipc ra,0x0 - 48: 000080e7 jalr ra # 44 <.LVL7> - -0000004c <.LVL8>: - 4c: 4702 lw a4,0(sp) - 4e: 4792 lw a5,4(sp) - 50: c6aa sw a0,76(sp) - 52: d2ae sw a1,100(sp) - -00000054 <.LVL9>: - 54: 8626 mv a2,s1 - 56: 86a2 mv a3,s0 - 58: 853a mv a0,a4 - -0000005a <.LVL10>: - 5a: 85be mv a1,a5 - -0000005c <.LVL11>: - 5c: 00000097 auipc ra,0x0 - 60: 000080e7 jalr ra # 5c <.LVL11> - -00000064 <.LVL12>: - 64: 4722 lw a4,8(sp) - 66: 47b2 lw a5,12(sp) - 68: c8aa sw a0,80(sp) - 6a: 863a mv a2,a4 - 6c: 86be mv a3,a5 - 6e: 4742 lw a4,16(sp) - 70: 47d2 lw a5,20(sp) - 72: d4ae sw a1,104(sp) - -00000074 <.LVL13>: - 74: 853a mv a0,a4 - -00000076 <.LVL14>: - 76: 85be mv a1,a5 - -00000078 <.LVL15>: - 78: 00000097 auipc ra,0x0 - 7c: 000080e7 jalr ra # 78 <.LVL15> - -00000080 <.LVL16>: - 80: 4736 lw a4,76(sp) - 82: 5796 lw a5,100(sp) - 84: caaa sw a0,84(sp) - 86: 863a mv a2,a4 - 88: 86be mv a3,a5 - 8a: 4726 lw a4,72(sp) - 8c: 5786 lw a5,96(sp) - 8e: d6ae sw a1,108(sp) - -00000090 <.LVL17>: - 90: 853a mv a0,a4 - -00000092 <.LVL18>: - 92: 85be mv a1,a5 - -00000094 <.LVL19>: - 94: 00000097 auipc ra,0x0 - 98: 000080e7 jalr ra # 94 <.LVL19> - -0000009c <.LVL20>: - 9c: 4756 lw a4,84(sp) - 9e: 57b6 lw a5,108(sp) - a0: d22a sw a0,36(sp) - a2: 863a mv a2,a4 - a4: 86be mv a3,a5 - a6: 4746 lw a4,80(sp) - a8: 57a6 lw a5,104(sp) - aa: d62e sw a1,44(sp) - -000000ac <.LVL21>: - ac: 853a mv a0,a4 - -000000ae <.LVL22>: - ae: 85be mv a1,a5 - -000000b0 <.LVL23>: - b0: 00000097 auipc ra,0x0 - b4: 000080e7 jalr ra # b0 <.LVL23> - -000000b8 <.LVL24>: - b8: 5612 lw a2,36(sp) - ba: 56b2 lw a3,44(sp) - bc: da2a sw a0,52(sp) - be: dc2e sw a1,56(sp) - -000000c0 <.LVL25>: - c0: 8532 mv a0,a2 - -000000c2 <.LVL26>: - c2: 85b6 mv a1,a3 - -000000c4 <.LVL27>: - c4: 00000097 auipc ra,0x0 - c8: 000080e7 jalr ra # c4 <.LVL27> - -000000cc <.LVL28>: - cc: 46050263 beqz a0,530 <.L2> - d0: 5652 lw a2,52(sp) - d2: 56e2 lw a3,56(sp) - d4: 8532 mv a0,a2 - d6: 85b6 mv a1,a3 - d8: 00000097 auipc ra,0x0 - dc: 000080e7 jalr ra # d8 <.LVL28+0xc> - -000000e0 <.LVL29>: - e0: 44050863 beqz a0,530 <.L2> - -000000e4 <.LBB2>: - e4: 4712 lw a4,4(sp) - e6: 800007b7 lui a5,0x80000 - ea: fff7c793 not a5,a5 - ee: 8f7d and a4,a4,a5 - f0: cc3a sw a4,24(sp) - f2: 4732 lw a4,12(sp) - f4: 8ff9 and a5,a5,a4 - f6: d03e sw a5,32(sp) - f8: 000007b7 lui a5,0x0 - fc: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 100: 0047a783 lw a5,4(a5) - 104: de3a sw a4,60(sp) - 106: c0be sw a5,64(sp) - 108: 863a mv a2,a4 - 10a: 86be mv a3,a5 - 10c: 4702 lw a4,0(sp) - 10e: 47e2 lw a5,24(sp) - 110: 853a mv a0,a4 - 112: 85be mv a1,a5 - 114: 00000097 auipc ra,0x0 - 118: 000080e7 jalr ra # 114 <.LBB2+0x30> - -0000011c <.LVL31>: - 11c: ed09 bnez a0,136 <.L45> - 11e: 4702 lw a4,0(sp) - 120: 47e2 lw a5,24(sp) - 122: 5672 lw a2,60(sp) - 124: 4686 lw a3,64(sp) - 126: 853a mv a0,a4 - 128: 85be mv a1,a5 - 12a: 00000097 auipc ra,0x0 - 12e: 000080e7 jalr ra # 12a <.LVL31+0xe> - -00000132 <.LVL32>: - 132: 04a04263 bgtz a0,176 <.L5> - -00000136 <.L45>: - 136: 000007b7 lui a5,0x0 - 13a: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 13e: 0047a783 lw a5,4(a5) - 142: de3a sw a4,60(sp) - 144: c0be sw a5,64(sp) - 146: 863a mv a2,a4 - 148: 86be mv a3,a5 - 14a: 4722 lw a4,8(sp) - 14c: 5782 lw a5,32(sp) - 14e: 853a mv a0,a4 - 150: 85be mv a1,a5 - 152: 00000097 auipc ra,0x0 - 156: 000080e7 jalr ra # 152 <.L45+0x1c> - -0000015a <.LVL33>: - 15a: 14051a63 bnez a0,2ae <.L41> - 15e: 4722 lw a4,8(sp) - 160: 5782 lw a5,32(sp) - 162: 5672 lw a2,60(sp) - 164: 4686 lw a3,64(sp) - 166: 853a mv a0,a4 - 168: 85be mv a1,a5 - 16a: 00000097 auipc ra,0x0 - 16e: 000080e7 jalr ra # 16a <.LVL33+0x10> - -00000172 <.LVL34>: - 172: 12a05e63 blez a0,2ae <.L41> - -00000176 <.L5>: - 176: 4785 li a5,1 - 178: 02f10e23 sb a5,60(sp) - 17c: 000007b7 lui a5,0x0 - 180: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 184: 0047a783 lw a5,4(a5) - 188: ccba sw a4,88(sp) - 18a: cebe sw a5,92(sp) - 18c: 863a mv a2,a4 - 18e: 86be mv a3,a5 - 190: 4702 lw a4,0(sp) - 192: 47e2 lw a5,24(sp) - 194: 853a mv a0,a4 - 196: 85be mv a1,a5 - 198: 00000097 auipc ra,0x0 - 19c: 000080e7 jalr ra # 198 <.L5+0x22> - -000001a0 <.LVL35>: - 1a0: ed19 bnez a0,1be <.L8> - 1a2: 4702 lw a4,0(sp) - 1a4: 47e2 lw a5,24(sp) - 1a6: 4666 lw a2,88(sp) - 1a8: 46f6 lw a3,92(sp) - 1aa: 853a mv a0,a4 - 1ac: 85be mv a1,a5 - 1ae: 00000097 auipc ra,0x0 - 1b2: 000080e7 jalr ra # 1ae <.LVL35+0xe> - -000001b6 <.LVL36>: - 1b6: 00a05463 blez a0,1be <.L8> - 1ba: 02010e23 sb zero,60(sp) - -000001be <.L8>: - 1be: 57f2 lw a5,60(sp) - 1c0: 0017c513 xor a0,a5,1 - 1c4: 8905 and a0,a0,1 - 1c6: 00000097 auipc ra,0x0 - 1ca: 000080e7 jalr ra # 1c6 <.L8+0x8> - -000001ce <.LVL37>: - 1ce: 800007b7 lui a5,0x80000 - 1d2: fff7c713 not a4,a5 - 1d6: 8df9 and a1,a1,a4 - 1d8: 4712 lw a4,4(sp) - 1da: c02a sw a0,0(sp) - 1dc: 8ff9 and a5,a5,a4 - 1de: 8fcd or a5,a5,a1 - 1e0: c23e sw a5,4(sp) - -000001e2 <.LVL38>: - 1e2: 4785 li a5,1 - -000001e4 <.LVL39>: - 1e4: 00f10c23 sb a5,24(sp) - 1e8: 000007b7 lui a5,0x0 - 1ec: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 1f0: 0047a783 lw a5,4(a5) - 1f4: de3a sw a4,60(sp) - 1f6: c0be sw a5,64(sp) - 1f8: 863a mv a2,a4 - 1fa: 86be mv a3,a5 - 1fc: 4722 lw a4,8(sp) - 1fe: 5782 lw a5,32(sp) - 200: 853a mv a0,a4 - -00000202 <.LVL40>: - 202: 85be mv a1,a5 - 204: 00000097 auipc ra,0x0 - 208: 000080e7 jalr ra # 204 <.LVL40+0x2> - -0000020c <.LVL41>: - 20c: ed19 bnez a0,22a <.L9> - 20e: 4722 lw a4,8(sp) - 210: 5782 lw a5,32(sp) - 212: 5672 lw a2,60(sp) - 214: 4686 lw a3,64(sp) - 216: 853a mv a0,a4 - 218: 85be mv a1,a5 - 21a: 00000097 auipc ra,0x0 - 21e: 000080e7 jalr ra # 21a <.LVL41+0xe> - -00000222 <.LVL42>: - 222: 00a05463 blez a0,22a <.L9> - 226: 00010c23 sb zero,24(sp) - -0000022a <.L9>: - 22a: 47e2 lw a5,24(sp) - 22c: 0017c513 xor a0,a5,1 - 230: 8905 and a0,a0,1 - 232: 00000097 auipc ra,0x0 - 236: 000080e7 jalr ra # 232 <.L9+0x8> - -0000023a <.LVL43>: - 23a: 800007b7 lui a5,0x80000 - 23e: fff7c713 not a4,a5 - 242: 8df9 and a1,a1,a4 - 244: 4732 lw a4,12(sp) - 246: c42a sw a0,8(sp) - 248: 8ff9 and a5,a5,a4 - 24a: 8fcd or a5,a5,a1 - 24c: 4742 lw a4,16(sp) - 24e: c63e sw a5,12(sp) - -00000250 <.LVL44>: - 250: 47d2 lw a5,20(sp) - -00000252 <.LVL45>: - 252: 863a mv a2,a4 - 254: 853a mv a0,a4 - -00000256 <.LVL46>: - 256: 86be mv a3,a5 - 258: 85be mv a1,a5 - 25a: 00000097 auipc ra,0x0 - 25e: 000080e7 jalr ra # 25a <.LVL46+0x4> - -00000262 <.LVL47>: - 262: cd11 beqz a0,27e <.L10> - 264: 46d2 lw a3,20(sp) - 266: 4701 li a4,0 - 268: 4781 li a5,0 - 26a: 0006d863 bgez a3,27a <.L12> - 26e: 000007b7 lui a5,0x0 - 272: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 276: 0047a783 lw a5,4(a5) - -0000027a <.L12>: - 27a: c83a sw a4,16(sp) - 27c: ca3e sw a5,20(sp) - -0000027e <.L10>: - 27e: 8626 mv a2,s1 - 280: 86a2 mv a3,s0 - 282: 8526 mv a0,s1 - 284: 85a2 mv a1,s0 - 286: 00000097 auipc ra,0x0 - 28a: 000080e7 jalr ra # 286 <.L10+0x8> - -0000028e <.LVL49>: - 28e: cd09 beqz a0,2a8 <.L82> - 290: 4701 li a4,0 - 292: 4781 li a5,0 - 294: 00045863 bgez s0,2a4 <.L14> - 298: 000007b7 lui a5,0x0 - 29c: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 2a0: 0047a783 lw a5,4(a5) - -000002a4 <.L14>: - 2a4: 84ba mv s1,a4 - 2a6: 843e mv s0,a5 - -000002a8 <.L82>: - 2a8: 4785 li a5,1 - 2aa: de3e sw a5,60(sp) - 2ac: a011 j 2b0 <.L7> - -000002ae <.L41>: - 2ae: de02 sw zero,60(sp) - -000002b0 <.L7>: - 2b0: 4752 lw a4,20(sp) - 2b2: 800007b7 lui a5,0x80000 - 2b6: fff7c793 not a5,a5 - 2ba: 8f7d and a4,a4,a5 - 2bc: 8fe1 and a5,a5,s0 - 2be: d03e sw a5,32(sp) - 2c0: 000007b7 lui a5,0x0 - 2c4: cc3a sw a4,24(sp) - 2c6: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 2ca: 0047a783 lw a5,4(a5) - 2ce: ccba sw a4,88(sp) - 2d0: cebe sw a5,92(sp) - 2d2: 863a mv a2,a4 - 2d4: 86be mv a3,a5 - 2d6: 4742 lw a4,16(sp) - 2d8: 47e2 lw a5,24(sp) - 2da: 853a mv a0,a4 - 2dc: 85be mv a1,a5 - 2de: 00000097 auipc ra,0x0 - 2e2: 000080e7 jalr ra # 2de <.L7+0x2e> - -000002e6 <.LVL53>: - 2e6: ed09 bnez a0,300 <.L48> - 2e8: 4742 lw a4,16(sp) - 2ea: 47e2 lw a5,24(sp) - 2ec: 4666 lw a2,88(sp) - 2ee: 46f6 lw a3,92(sp) - 2f0: 853a mv a0,a4 - 2f2: 85be mv a1,a5 - 2f4: 00000097 auipc ra,0x0 - 2f8: 000080e7 jalr ra # 2f4 <.LVL53+0xe> - -000002fc <.LVL54>: - 2fc: 04a04063 bgtz a0,33c <.L15> - -00000300 <.L48>: - 300: 000007b7 lui a5,0x0 - 304: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 308: 0047a783 lw a5,4(a5) - 30c: 8526 mv a0,s1 - 30e: 863a mv a2,a4 - 310: cebe sw a5,92(sp) - 312: 86be mv a3,a5 - 314: 5782 lw a5,32(sp) - 316: ccba sw a4,88(sp) - 318: 85be mv a1,a5 - 31a: 00000097 auipc ra,0x0 - 31e: 000080e7 jalr ra # 31a <.L48+0x1a> - -00000322 <.LVL55>: - 322: 22051663 bnez a0,54e <.L17> - 326: 5782 lw a5,32(sp) - 328: 4666 lw a2,88(sp) - 32a: 46f6 lw a3,92(sp) - 32c: 8526 mv a0,s1 - 32e: 85be mv a1,a5 - 330: 00000097 auipc ra,0x0 - 334: 000080e7 jalr ra # 330 <.LVL55+0xe> - -00000338 <.LVL56>: - 338: 20a05b63 blez a0,54e <.L17> - -0000033c <.L15>: - 33c: 4785 li a5,1 - 33e: 02f10223 sb a5,36(sp) - -00000342 <.LVL57>: - 342: 000007b7 lui a5,0x0 - 346: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 34a: 0047a783 lw a5,4(a5) - 34e: d63a sw a4,44(sp) - 350: d83e sw a5,48(sp) - 352: 863a mv a2,a4 - 354: 86be mv a3,a5 - 356: 4742 lw a4,16(sp) - 358: 47e2 lw a5,24(sp) - 35a: 853a mv a0,a4 - 35c: 85be mv a1,a5 - 35e: 00000097 auipc ra,0x0 - 362: 000080e7 jalr ra # 35e <.LVL57+0x1c> - -00000366 <.LVL58>: - 366: ed19 bnez a0,384 <.L18> - 368: 4742 lw a4,16(sp) - 36a: 47e2 lw a5,24(sp) - 36c: 5632 lw a2,44(sp) - 36e: 56c2 lw a3,48(sp) - 370: 853a mv a0,a4 - 372: 85be mv a1,a5 - 374: 00000097 auipc ra,0x0 - 378: 000080e7 jalr ra # 374 <.LVL58+0xe> - -0000037c <.LVL59>: - 37c: 00a05463 blez a0,384 <.L18> - 380: 02010223 sb zero,36(sp) - -00000384 <.L18>: - 384: 5792 lw a5,36(sp) - 386: 0017c513 xor a0,a5,1 - 38a: 8905 and a0,a0,1 - 38c: 00000097 auipc ra,0x0 - 390: 000080e7 jalr ra # 38c <.L18+0x8> - -00000394 <.LVL60>: - 394: 800007b7 lui a5,0x80000 - 398: fff7c713 not a4,a5 - 39c: 8df9 and a1,a1,a4 - 39e: 4752 lw a4,20(sp) - 3a0: c82a sw a0,16(sp) - -000003a2 <.LVL61>: - 3a2: 8526 mv a0,s1 - 3a4: 8ff9 and a5,a5,a4 - 3a6: 8fcd or a5,a5,a1 - 3a8: ca3e sw a5,20(sp) - -000003aa <.LVL62>: - 3aa: 4785 li a5,1 - -000003ac <.LVL63>: - 3ac: 00f10c23 sb a5,24(sp) - 3b0: 000007b7 lui a5,0x0 - 3b4: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 3b8: 0047a783 lw a5,4(a5) - 3bc: 863a mv a2,a4 - 3be: d43e sw a5,40(sp) - 3c0: 86be mv a3,a5 - 3c2: 5782 lw a5,32(sp) - 3c4: d23a sw a4,36(sp) - 3c6: 85be mv a1,a5 - 3c8: 00000097 auipc ra,0x0 - 3cc: 000080e7 jalr ra # 3c8 <.LVL63+0x1c> - -000003d0 <.LVL64>: - 3d0: ed11 bnez a0,3ec <.L19> - 3d2: 5782 lw a5,32(sp) - 3d4: 5612 lw a2,36(sp) - 3d6: 56a2 lw a3,40(sp) - 3d8: 8526 mv a0,s1 - 3da: 85be mv a1,a5 - 3dc: 00000097 auipc ra,0x0 - 3e0: 000080e7 jalr ra # 3dc <.LVL64+0xc> - -000003e4 <.LVL65>: - 3e4: 00a05463 blez a0,3ec <.L19> - 3e8: 00010c23 sb zero,24(sp) - -000003ec <.L19>: - 3ec: 47e2 lw a5,24(sp) - 3ee: 0017c513 xor a0,a5,1 - 3f2: 8905 and a0,a0,1 - 3f4: 00000097 auipc ra,0x0 - 3f8: 000080e7 jalr ra # 3f4 <.L19+0x8> - -000003fc <.LVL66>: - 3fc: 800007b7 lui a5,0x80000 - 400: fff7c713 not a4,a5 - 404: 8df9 and a1,a1,a4 - 406: 8fe1 and a5,a5,s0 - 408: 4702 lw a4,0(sp) - 40a: 00f5e433 or s0,a1,a5 - -0000040e <.LVL67>: - 40e: 4792 lw a5,4(sp) - 410: 84aa mv s1,a0 - 412: 863a mv a2,a4 - 414: 86be mv a3,a5 - 416: 853a mv a0,a4 - -00000418 <.LVL68>: - 418: 85be mv a1,a5 - 41a: 00000097 auipc ra,0x0 - 41e: 000080e7 jalr ra # 41a <.LVL68+0x2> - -00000422 <.LVL69>: - 422: cd11 beqz a0,43e <.L20> - 424: 4692 lw a3,4(sp) - 426: 4701 li a4,0 - 428: 4781 li a5,0 - 42a: 0006d863 bgez a3,43a <.L22> - 42e: 000007b7 lui a5,0x0 - 432: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 436: 0047a783 lw a5,4(a5) - -0000043a <.L22>: - 43a: c03a sw a4,0(sp) - -0000043c <.LVL70>: - 43c: c23e sw a5,4(sp) - -0000043e <.L20>: - 43e: 4722 lw a4,8(sp) - 440: 47b2 lw a5,12(sp) - 442: 863a mv a2,a4 - 444: 86be mv a3,a5 - 446: 853a mv a0,a4 - 448: 85be mv a1,a5 - 44a: 00000097 auipc ra,0x0 - 44e: 000080e7 jalr ra # 44a <.L20+0xc> - -00000452 <.LVL72>: - 452: cd11 beqz a0,46e <.L23> - 454: 46b2 lw a3,12(sp) - 456: 4701 li a4,0 - 458: 4781 li a5,0 - 45a: 0006d863 bgez a3,46a <.L25> - 45e: 000007b7 lui a5,0x0 - 462: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 466: 0047a783 lw a5,4(a5) - -0000046a <.L25>: - 46a: c43a sw a4,8(sp) - -0000046c <.LVL73>: - 46c: c63e sw a5,12(sp) - -0000046e <.L23>: - 46e: 47c2 lw a5,16(sp) - 470: 43d2 lw t2,20(sp) - 472: 4712 lw a4,4(sp) - 474: 863e mv a2,a5 - 476: cc3e sw a5,24(sp) - 478: 4782 lw a5,0(sp) - 47a: 869e mv a3,t2 - 47c: 85ba mv a1,a4 - 47e: 853e mv a0,a5 - 480: dc1e sw t2,56(sp) - -00000482 <.LVL75>: - 482: c83a sw a4,16(sp) - 484: da3e sw a5,52(sp) - 486: 00000097 auipc ra,0x0 - 48a: 000080e7 jalr ra # 486 <.LVL75+0x4> - -0000048e <.LVL76>: - 48e: 8626 mv a2,s1 - 490: 86a2 mv a3,s0 - 492: ca26 sw s1,20(sp) - 494: c222 sw s0,4(sp) - 496: 44a2 lw s1,8(sp) - 498: 4432 lw s0,12(sp) - 49a: c02a sw a0,0(sp) - 49c: d02e sw a1,32(sp) - 49e: 8526 mv a0,s1 - 4a0: 85a2 mv a1,s0 - 4a2: 00000097 auipc ra,0x0 - 4a6: 000080e7 jalr ra # 4a2 <.LVL76+0x14> - -000004aa <.LVL77>: - 4aa: 5282 lw t0,32(sp) - 4ac: 862a mv a2,a0 - 4ae: 4502 lw a0,0(sp) - 4b0: 86ae mv a3,a1 - 4b2: 8596 mv a1,t0 - 4b4: 00000097 auipc ra,0x0 - 4b8: 000080e7 jalr ra # 4b4 <.LVL77+0xa> - -000004bc <.LVL78>: - 4bc: 000002b7 lui t0,0x0 - 4c0: 0002a603 lw a2,0(t0) # 0 <__muldc3> - 4c4: 0042a683 lw a3,4(t0) - 4c8: 00000097 auipc ra,0x0 - 4cc: 000080e7 jalr ra # 4c8 <.LVL78+0xc> - -000004d0 <.LVL79>: - 4d0: 4712 lw a4,4(sp) - 4d2: 4352 lw t1,20(sp) - 4d4: 57d2 lw a5,52(sp) - 4d6: 86ba mv a3,a4 - 4d8: 4742 lw a4,16(sp) - 4da: 861a mv a2,t1 - 4dc: d22a sw a0,36(sp) - 4de: d62e sw a1,44(sp) - -000004e0 <.LVL80>: - 4e0: 853e mv a0,a5 - -000004e2 <.LVL81>: - 4e2: 85ba mv a1,a4 - -000004e4 <.LVL82>: - 4e4: 00000097 auipc ra,0x0 - 4e8: 000080e7 jalr ra # 4e4 <.LVL82> - -000004ec <.LVL83>: - 4ec: 53e2 lw t2,56(sp) - 4ee: c22a sw a0,4(sp) - 4f0: 4562 lw a0,24(sp) - 4f2: 869e mv a3,t2 - 4f4: c02e sw a1,0(sp) - 4f6: 862a mv a2,a0 - 4f8: 85a2 mv a1,s0 - 4fa: 8526 mv a0,s1 - 4fc: 00000097 auipc ra,0x0 - 500: 000080e7 jalr ra # 4fc <.LVL83+0x10> - -00000504 <.LVL84>: - 504: 4712 lw a4,4(sp) - 506: 4782 lw a5,0(sp) - 508: 862a mv a2,a0 - 50a: 86ae mv a3,a1 - 50c: 853a mv a0,a4 - 50e: 85be mv a1,a5 - 510: 00000097 auipc ra,0x0 - 514: 000080e7 jalr ra # 510 <.LVL84+0xc> - -00000518 <.LVL85>: - 518: 000002b7 lui t0,0x0 - 51c: 0002a603 lw a2,0(t0) # 0 <__muldc3> - 520: 0042a683 lw a3,4(t0) - 524: 00000097 auipc ra,0x0 - 528: 000080e7 jalr ra # 524 <.LVL85+0xc> - -0000052c <.LVL86>: - 52c: da2a sw a0,52(sp) - 52e: dc2e sw a1,56(sp) - -00000530 <.L2>: - 530: 4696 lw a3,68(sp) - 532: 5712 lw a4,36(sp) - 534: 57b2 lw a5,44(sp) - 536: 50e6 lw ra,120(sp) - 538: c298 sw a4,0(a3) - 53a: c2dc sw a5,4(a3) - 53c: 5752 lw a4,52(sp) - 53e: 57e2 lw a5,56(sp) - 540: 5456 lw s0,116(sp) - 542: c698 sw a4,8(a3) - 544: c6dc sw a5,12(a3) - 546: 54c6 lw s1,112(sp) - 548: 8536 mv a0,a3 - 54a: 6109 add sp,sp,128 - 54c: 8082 ret - -0000054e <.L17>: - 54e: 57f2 lw a5,60(sp) - 550: ff99 bnez a5,46e <.L23> - 552: 5786 lw a5,96(sp) - 554: 00000737 lui a4,0x0 - 558: 00072683 lw a3,0(a4) # 0 <__muldc3> - 55c: 4326 lw t1,72(sp) - 55e: 00472703 lw a4,4(a4) - 562: 0786 sll a5,a5,0x1 - 564: 8385 srl a5,a5,0x1 - 566: cc36 sw a3,24(sp) - 568: 8636 mv a2,a3 - 56a: 851a mv a0,t1 - 56c: 86ba mv a3,a4 - 56e: 85be mv a1,a5 - 570: ce3a sw a4,28(sp) - 572: d03e sw a5,32(sp) - 574: 00000097 auipc ra,0x0 - 578: 000080e7 jalr ra # 574 <.L17+0x26> - -0000057c <.LVL89>: - 57c: ed09 bnez a0,596 <.L51> - 57e: 4326 lw t1,72(sp) - 580: 5782 lw a5,32(sp) - 582: 4662 lw a2,24(sp) - 584: 46f2 lw a3,28(sp) - 586: 851a mv a0,t1 - 588: 85be mv a1,a5 - 58a: 00000097 auipc ra,0x0 - 58e: 000080e7 jalr ra # 58a <.LVL89+0xe> - -00000592 <.LVL90>: - 592: 0ca04963 bgtz a0,664 <.L26> - -00000596 <.L51>: - 596: 5796 lw a5,100(sp) - 598: 00000737 lui a4,0x0 - 59c: 00072683 lw a3,0(a4) # 0 <__muldc3> - 5a0: 4336 lw t1,76(sp) - 5a2: 00472703 lw a4,4(a4) - 5a6: 0786 sll a5,a5,0x1 - 5a8: 8385 srl a5,a5,0x1 - 5aa: cc36 sw a3,24(sp) - 5ac: 8636 mv a2,a3 - 5ae: 851a mv a0,t1 - 5b0: 86ba mv a3,a4 - 5b2: 85be mv a1,a5 - 5b4: ce3a sw a4,28(sp) - 5b6: d03e sw a5,32(sp) - 5b8: 00000097 auipc ra,0x0 - 5bc: 000080e7 jalr ra # 5b8 <.L51+0x22> - -000005c0 <.LVL91>: - 5c0: ed09 bnez a0,5da <.L52> - 5c2: 4336 lw t1,76(sp) - 5c4: 5782 lw a5,32(sp) - 5c6: 4662 lw a2,24(sp) - 5c8: 46f2 lw a3,28(sp) - 5ca: 851a mv a0,t1 - 5cc: 85be mv a1,a5 - 5ce: 00000097 auipc ra,0x0 - 5d2: 000080e7 jalr ra # 5ce <.LVL91+0xe> - -000005d6 <.LVL92>: - 5d6: 08a04763 bgtz a0,664 <.L26> - -000005da <.L52>: - 5da: 57a6 lw a5,104(sp) - 5dc: 00000737 lui a4,0x0 - 5e0: 00072683 lw a3,0(a4) # 0 <__muldc3> - 5e4: 4346 lw t1,80(sp) - 5e6: 00472703 lw a4,4(a4) - 5ea: 0786 sll a5,a5,0x1 - 5ec: 8385 srl a5,a5,0x1 - 5ee: cc36 sw a3,24(sp) - 5f0: 8636 mv a2,a3 - 5f2: 851a mv a0,t1 - 5f4: 86ba mv a3,a4 - 5f6: 85be mv a1,a5 - 5f8: ce3a sw a4,28(sp) - 5fa: d03e sw a5,32(sp) - 5fc: 00000097 auipc ra,0x0 - 600: 000080e7 jalr ra # 5fc <.L52+0x22> - -00000604 <.LVL93>: - 604: ed09 bnez a0,61e <.L53> - 606: 4346 lw t1,80(sp) - 608: 5782 lw a5,32(sp) - 60a: 4662 lw a2,24(sp) - 60c: 46f2 lw a3,28(sp) - 60e: 851a mv a0,t1 - 610: 85be mv a1,a5 - 612: 00000097 auipc ra,0x0 - 616: 000080e7 jalr ra # 612 <.LVL93+0xe> - -0000061a <.LVL94>: - 61a: 04a04563 bgtz a0,664 <.L26> - -0000061e <.L53>: - 61e: 57b6 lw a5,108(sp) - 620: 00000737 lui a4,0x0 - 624: 00072683 lw a3,0(a4) # 0 <__muldc3> - 628: 4356 lw t1,84(sp) - 62a: 00472703 lw a4,4(a4) - 62e: 0786 sll a5,a5,0x1 - 630: 8385 srl a5,a5,0x1 - 632: cc36 sw a3,24(sp) - 634: 8636 mv a2,a3 - 636: 851a mv a0,t1 - 638: 86ba mv a3,a4 - 63a: 85be mv a1,a5 - 63c: ce3a sw a4,28(sp) - 63e: d03e sw a5,32(sp) - 640: 00000097 auipc ra,0x0 - 644: 000080e7 jalr ra # 640 <.L53+0x22> - -00000648 <.LVL95>: - 648: ee0514e3 bnez a0,530 <.L2> - 64c: 4356 lw t1,84(sp) - 64e: 5782 lw a5,32(sp) - 650: 4662 lw a2,24(sp) - 652: 46f2 lw a3,28(sp) - 654: 851a mv a0,t1 - 656: 85be mv a1,a5 - 658: 00000097 auipc ra,0x0 - 65c: 000080e7 jalr ra # 658 <.LVL95+0x10> - -00000660 <.LVL96>: - 660: eca058e3 blez a0,530 <.L2> - -00000664 <.L26>: - 664: 4702 lw a4,0(sp) - 666: 4792 lw a5,4(sp) - 668: 863a mv a2,a4 - 66a: 86be mv a3,a5 - 66c: 853a mv a0,a4 - 66e: 85be mv a1,a5 - 670: 00000097 auipc ra,0x0 - 674: 000080e7 jalr ra # 670 <.L26+0xc> - -00000678 <.LVL97>: - 678: cd11 beqz a0,694 <.L30> - 67a: 4692 lw a3,4(sp) - 67c: 4701 li a4,0 - 67e: 4781 li a5,0 - 680: 0006d863 bgez a3,690 <.L32> - 684: 000007b7 lui a5,0x0 - 688: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 68c: 0047a783 lw a5,4(a5) - -00000690 <.L32>: - 690: c03a sw a4,0(sp) - -00000692 <.LVL98>: - 692: c23e sw a5,4(sp) - -00000694 <.L30>: - 694: 4722 lw a4,8(sp) - 696: 47b2 lw a5,12(sp) - 698: 863a mv a2,a4 - 69a: 86be mv a3,a5 - 69c: 853a mv a0,a4 - 69e: 85be mv a1,a5 - 6a0: 00000097 auipc ra,0x0 - 6a4: 000080e7 jalr ra # 6a0 <.L30+0xc> - -000006a8 <.LVL100>: - 6a8: cd11 beqz a0,6c4 <.L33> - 6aa: 46b2 lw a3,12(sp) - 6ac: 4701 li a4,0 - 6ae: 4781 li a5,0 - 6b0: 0006d863 bgez a3,6c0 <.L35> - 6b4: 000007b7 lui a5,0x0 - 6b8: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 6bc: 0047a783 lw a5,4(a5) - -000006c0 <.L35>: - 6c0: c43a sw a4,8(sp) - -000006c2 <.LVL101>: - 6c2: c63e sw a5,12(sp) - -000006c4 <.L33>: - 6c4: 4742 lw a4,16(sp) - 6c6: 47d2 lw a5,20(sp) - 6c8: 863a mv a2,a4 - 6ca: 86be mv a3,a5 - 6cc: 853a mv a0,a4 - 6ce: 85be mv a1,a5 - 6d0: 00000097 auipc ra,0x0 - 6d4: 000080e7 jalr ra # 6d0 <.L33+0xc> - -000006d8 <.LVL103>: - 6d8: cd11 beqz a0,6f4 <.L36> - 6da: 46d2 lw a3,20(sp) - 6dc: 4701 li a4,0 - 6de: 4781 li a5,0 - 6e0: 0006d863 bgez a3,6f0 <.L38> - 6e4: 000007b7 lui a5,0x0 - 6e8: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 6ec: 0047a783 lw a5,4(a5) - -000006f0 <.L38>: - 6f0: c83a sw a4,16(sp) - -000006f2 <.LVL104>: - 6f2: ca3e sw a5,20(sp) - -000006f4 <.L36>: - 6f4: 8626 mv a2,s1 - 6f6: 86a2 mv a3,s0 - 6f8: 8526 mv a0,s1 - 6fa: 85a2 mv a1,s0 - 6fc: 00000097 auipc ra,0x0 - 700: 000080e7 jalr ra # 6fc <.L36+0x8> - -00000704 <.LVL106>: - 704: d60505e3 beqz a0,46e <.L23> - 708: 4701 li a4,0 - 70a: 4781 li a5,0 - 70c: 00045863 bgez s0,71c <.L40> - 710: 000007b7 lui a5,0x0 - 714: 0007a703 lw a4,0(a5) # 0 <__muldc3> - 718: 0047a783 lw a5,4(a5) - -0000071c <.L40>: - 71c: 84ba mv s1,a4 - -0000071e <.LVL107>: - 71e: 843e mv s0,a5 - -00000720 <.LVL108>: - 720: b3b9 j 46e <.L23> - -_mulxc3.o: file format elf32-littleriscv - - -_multc3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__multc3>: - 0: 419c lw a5,0(a1) - 2: ee810113 add sp,sp,-280 - 6: 10112a23 sw ra,276(sp) - a: c03e sw a5,0(sp) - c: 41dc lw a5,4(a1) - e: 10812823 sw s0,272(sp) - 12: 10912623 sw s1,268(sp) - 16: c23e sw a5,4(sp) - 18: 459c lw a5,8(a1) - 1a: c0aa sw a0,64(sp) - 1c: 19e8 add a0,sp,252 - 1e: c43e sw a5,8(sp) - 20: 45dc lw a5,12(a1) - 22: 11ec add a1,sp,236 - 24: c63e sw a5,12(sp) - 26: 421c lw a5,0(a2) - 28: c83e sw a5,16(sp) - 2a: 425c lw a5,4(a2) - 2c: ca3e sw a5,20(sp) - 2e: 461c lw a5,8(a2) - 30: cc3e sw a5,24(sp) - 32: 465c lw a5,12(a2) - 34: 09f0 add a2,sp,220 - 36: ce3e sw a5,28(sp) - 38: 429c lw a5,0(a3) - 3a: d03e sw a5,32(sp) - 3c: 42dc lw a5,4(a3) - 3e: d23e sw a5,36(sp) - 40: 469c lw a5,8(a3) - 42: d43e sw a5,40(sp) - 44: 46dc lw a5,12(a3) - 46: d63e sw a5,44(sp) - 48: 431c lw a5,0(a4) - 4a: d83e sw a5,48(sp) - 4c: 435c lw a5,4(a4) - 4e: da3e sw a5,52(sp) - 50: 471c lw a5,8(a4) - 52: dc3e sw a5,56(sp) - 54: 475c lw a5,12(a4) - 56: de3e sw a5,60(sp) - 58: 4782 lw a5,0(sp) - 5a: d7be sw a5,236(sp) - 5c: 4792 lw a5,4(sp) - 5e: d9be sw a5,240(sp) - 60: 47a2 lw a5,8(sp) - 62: dbbe sw a5,244(sp) - 64: 47b2 lw a5,12(sp) - 66: ddbe sw a5,248(sp) - 68: 5782 lw a5,32(sp) - 6a: cfbe sw a5,220(sp) - 6c: 5792 lw a5,36(sp) - 6e: d1be sw a5,224(sp) - 70: 57a2 lw a5,40(sp) - 72: d3be sw a5,228(sp) - 74: 57b2 lw a5,44(sp) - 76: d5be sw a5,232(sp) - 78: 00000097 auipc ra,0x0 - 7c: 000080e7 jalr ra # 78 <__multc3+0x78> - -00000080 <.LVL2>: - 80: 57fe lw a5,252(sp) - 82: 09f0 add a2,sp,220 - 84: 11ec add a1,sp,236 - 86: d4be sw a5,104(sp) - 88: 10012783 lw a5,256(sp) - 8c: 19e8 add a0,sp,252 - 8e: d6be sw a5,108(sp) - 90: 10412783 lw a5,260(sp) - 94: d8be sw a5,112(sp) - 96: 10812783 lw a5,264(sp) - 9a: cd3e sw a5,152(sp) - -0000009c <.LVL3>: - 9c: 47c2 lw a5,16(sp) - -0000009e <.LVL4>: - 9e: d7be sw a5,236(sp) - a0: 47d2 lw a5,20(sp) - a2: d9be sw a5,240(sp) - a4: 47e2 lw a5,24(sp) - a6: dbbe sw a5,244(sp) - a8: 47f2 lw a5,28(sp) - aa: ddbe sw a5,248(sp) - ac: 57c2 lw a5,48(sp) - ae: cfbe sw a5,220(sp) - b0: 57d2 lw a5,52(sp) - b2: d1be sw a5,224(sp) - b4: 57e2 lw a5,56(sp) - b6: d3be sw a5,228(sp) - b8: 57f2 lw a5,60(sp) - ba: d5be sw a5,232(sp) - bc: 00000097 auipc ra,0x0 - c0: 000080e7 jalr ra # bc <.LVL4+0x1e> - -000000c4 <.LVL5>: - c4: 57fe lw a5,252(sp) - c6: 09f0 add a2,sp,220 - c8: 11ec add a1,sp,236 - ca: dabe sw a5,116(sp) - cc: 10012783 lw a5,256(sp) - d0: 19e8 add a0,sp,252 - d2: dcbe sw a5,120(sp) - d4: 10412783 lw a5,260(sp) - d8: debe sw a5,124(sp) - da: 10812783 lw a5,264(sp) - de: cf3e sw a5,156(sp) - -000000e0 <.LVL6>: - e0: 4782 lw a5,0(sp) - -000000e2 <.LVL7>: - e2: d7be sw a5,236(sp) - e4: 4792 lw a5,4(sp) - e6: d9be sw a5,240(sp) - e8: 47a2 lw a5,8(sp) - ea: dbbe sw a5,244(sp) - ec: 47b2 lw a5,12(sp) - ee: ddbe sw a5,248(sp) - f0: 57c2 lw a5,48(sp) - f2: cfbe sw a5,220(sp) - f4: 57d2 lw a5,52(sp) - f6: d1be sw a5,224(sp) - f8: 57e2 lw a5,56(sp) - fa: d3be sw a5,228(sp) - fc: 57f2 lw a5,60(sp) - fe: d5be sw a5,232(sp) - 100: 00000097 auipc ra,0x0 - 104: 000080e7 jalr ra # 100 <.LVL7+0x1e> - -00000108 <.LVL8>: - 108: 57fe lw a5,252(sp) - 10a: 09f0 add a2,sp,220 - 10c: 11ec add a1,sp,236 - 10e: c13e sw a5,128(sp) - 110: 10012783 lw a5,256(sp) - 114: 19e8 add a0,sp,252 - 116: c33e sw a5,132(sp) - 118: 10412783 lw a5,260(sp) - 11c: c53e sw a5,136(sp) - 11e: 10812783 lw a5,264(sp) - 122: d13e sw a5,160(sp) - -00000124 <.LVL9>: - 124: 5782 lw a5,32(sp) - -00000126 <.LVL10>: - 126: d7be sw a5,236(sp) - 128: 5792 lw a5,36(sp) - 12a: d9be sw a5,240(sp) - 12c: 57a2 lw a5,40(sp) - 12e: dbbe sw a5,244(sp) - 130: 57b2 lw a5,44(sp) - 132: ddbe sw a5,248(sp) - 134: 47c2 lw a5,16(sp) - 136: cfbe sw a5,220(sp) - 138: 47d2 lw a5,20(sp) - 13a: d1be sw a5,224(sp) - 13c: 47e2 lw a5,24(sp) - 13e: d3be sw a5,228(sp) - 140: 47f2 lw a5,28(sp) - 142: d5be sw a5,232(sp) - 144: 00000097 auipc ra,0x0 - 148: 000080e7 jalr ra # 144 <.LVL10+0x1e> - -0000014c <.LVL11>: - 14c: 57fe lw a5,252(sp) - 14e: 09f0 add a2,sp,220 - 150: 11ec add a1,sp,236 - 152: c73e sw a5,140(sp) - 154: 10012783 lw a5,256(sp) - 158: 19e8 add a0,sp,252 - 15a: c93e sw a5,144(sp) - 15c: 10412783 lw a5,260(sp) - 160: cb3e sw a5,148(sp) - 162: 10812783 lw a5,264(sp) - 166: d33e sw a5,164(sp) - -00000168 <.LVL12>: - 168: 57a6 lw a5,104(sp) - -0000016a <.LVL13>: - 16a: d7be sw a5,236(sp) - 16c: 57b6 lw a5,108(sp) - 16e: d9be sw a5,240(sp) - 170: 57c6 lw a5,112(sp) - 172: dbbe sw a5,244(sp) - 174: 47ea lw a5,152(sp) - 176: ddbe sw a5,248(sp) - 178: 57d6 lw a5,116(sp) - 17a: cfbe sw a5,220(sp) - 17c: 57e6 lw a5,120(sp) - 17e: d1be sw a5,224(sp) - 180: 57f6 lw a5,124(sp) - 182: d3be sw a5,228(sp) - 184: 47fa lw a5,156(sp) - 186: d5be sw a5,232(sp) - 188: 00000097 auipc ra,0x0 - 18c: 000080e7 jalr ra # 188 <.LVL13+0x1e> - -00000190 <.LVL14>: - 190: 57fe lw a5,252(sp) - 192: 11ec add a1,sp,236 - 194: 19e8 add a0,sp,252 - 196: c2be sw a5,68(sp) - 198: 10012783 lw a5,256(sp) - 19c: 09f0 add a2,sp,220 - 19e: c4be sw a5,72(sp) - 1a0: 10412783 lw a5,260(sp) - 1a4: c6be sw a5,76(sp) - 1a6: 10812783 lw a5,264(sp) - 1aa: c8be sw a5,80(sp) - -000001ac <.LVL15>: - 1ac: 478a lw a5,128(sp) - -000001ae <.LVL16>: - 1ae: d7be sw a5,236(sp) - 1b0: 479a lw a5,132(sp) - 1b2: d9be sw a5,240(sp) - 1b4: 47aa lw a5,136(sp) - 1b6: dbbe sw a5,244(sp) - 1b8: 578a lw a5,160(sp) - 1ba: ddbe sw a5,248(sp) - 1bc: 47ba lw a5,140(sp) - 1be: cfbe sw a5,220(sp) - 1c0: 47ca lw a5,144(sp) - 1c2: d1be sw a5,224(sp) - 1c4: 47da lw a5,148(sp) - 1c6: d3be sw a5,228(sp) - 1c8: 579a lw a5,164(sp) - 1ca: d5be sw a5,232(sp) - 1cc: 00000097 auipc ra,0x0 - 1d0: 000080e7 jalr ra # 1cc <.LVL16+0x1e> - -000001d4 <.LVL17>: - 1d4: 57fe lw a5,252(sp) - 1d6: 11ec add a1,sp,236 - 1d8: 19e8 add a0,sp,252 - 1da: cabe sw a5,84(sp) - 1dc: 10012783 lw a5,256(sp) - 1e0: ccbe sw a5,88(sp) - 1e2: 10412783 lw a5,260(sp) - 1e6: cebe sw a5,92(sp) - 1e8: 10812783 lw a5,264(sp) - 1ec: d0be sw a5,96(sp) - -000001ee <.LVL18>: - 1ee: 4796 lw a5,68(sp) - -000001f0 <.LVL19>: - 1f0: dfbe sw a5,252(sp) - -000001f2 <.LVL20>: - 1f2: 47a6 lw a5,72(sp) - 1f4: 10f12023 sw a5,256(sp) - -000001f8 <.LVL21>: - 1f8: 47b6 lw a5,76(sp) - 1fa: 10f12223 sw a5,260(sp) - -000001fe <.LVL22>: - 1fe: 47c6 lw a5,80(sp) - 200: 10f12423 sw a5,264(sp) - -00000204 <.LVL23>: - 204: 4796 lw a5,68(sp) - 206: d7be sw a5,236(sp) - 208: 47a6 lw a5,72(sp) - 20a: d9be sw a5,240(sp) - 20c: 47b6 lw a5,76(sp) - 20e: dbbe sw a5,244(sp) - 210: 47c6 lw a5,80(sp) - 212: ddbe sw a5,248(sp) - 214: 00000097 auipc ra,0x0 - 218: 000080e7 jalr ra # 214 <.LVL23+0x10> - -0000021c <.LVL24>: - 21c: 66050063 beqz a0,87c <.L2> - 220: 47d6 lw a5,84(sp) - 222: 11ec add a1,sp,236 - 224: 19e8 add a0,sp,252 - 226: dfbe sw a5,252(sp) - 228: 47e6 lw a5,88(sp) - 22a: 10f12023 sw a5,256(sp) - 22e: 47f6 lw a5,92(sp) - 230: 10f12223 sw a5,260(sp) - 234: 5786 lw a5,96(sp) - 236: 10f12423 sw a5,264(sp) - 23a: 47d6 lw a5,84(sp) - 23c: d7be sw a5,236(sp) - 23e: 47e6 lw a5,88(sp) - 240: d9be sw a5,240(sp) - 242: 47f6 lw a5,92(sp) - 244: dbbe sw a5,244(sp) - 246: 5786 lw a5,96(sp) - 248: ddbe sw a5,248(sp) - 24a: 00000097 auipc ra,0x0 - 24e: 000080e7 jalr ra # 24a <.LVL24+0x2e> - -00000252 <.LVL25>: - 252: 62050563 beqz a0,87c <.L2> - -00000256 <.LBB2>: - 256: 4732 lw a4,12(sp) - 258: 800007b7 lui a5,0x80000 - 25c: fff7c793 not a5,a5 - 260: 00f774b3 and s1,a4,a5 - 264: 4772 lw a4,28(sp) - 266: 547d li s0,-1 - 268: 11ec add a1,sp,236 - 26a: 8ff9 and a5,a5,a4 - 26c: 00000737 lui a4,0x0 - 270: d2be sw a5,100(sp) - 272: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - 276: 19e8 add a0,sp,252 - 278: 10912423 sw s1,264(sp) - 27c: d53e sw a5,168(sp) - 27e: 4782 lw a5,0(sp) - 280: d7a2 sw s0,236(sp) - 282: d9a2 sw s0,240(sp) - 284: dfbe sw a5,252(sp) - 286: 4792 lw a5,4(sp) - 288: dba2 sw s0,244(sp) - 28a: 10f12023 sw a5,256(sp) - 28e: 47a2 lw a5,8(sp) - 290: 10f12223 sw a5,260(sp) - 294: 57aa lw a5,168(sp) - 296: ddbe sw a5,248(sp) - 298: 00000097 auipc ra,0x0 - 29c: 000080e7 jalr ra # 298 <.LBB2+0x42> - -000002a0 <.LVL27>: - 2a0: e909 bnez a0,2b2 <.L45> - 2a2: 11ec add a1,sp,236 - 2a4: 19e8 add a0,sp,252 - 2a6: 00000097 auipc ra,0x0 - 2aa: 000080e7 jalr ra # 2a6 <.LVL27+0x6> - -000002ae <.LVL28>: - 2ae: 04a04863 bgtz a0,2fe <.L5> - -000002b2 <.L45>: - 2b2: 00000737 lui a4,0x0 - 2b6: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - 2ba: 547d li s0,-1 - 2bc: 11ec add a1,sp,236 - 2be: d53e sw a5,168(sp) - 2c0: 47c2 lw a5,16(sp) - 2c2: 19e8 add a0,sp,252 - 2c4: d7a2 sw s0,236(sp) - 2c6: dfbe sw a5,252(sp) - 2c8: 47d2 lw a5,20(sp) - 2ca: d9a2 sw s0,240(sp) - 2cc: dba2 sw s0,244(sp) - 2ce: 10f12023 sw a5,256(sp) - 2d2: 47e2 lw a5,24(sp) - 2d4: 10f12223 sw a5,260(sp) - 2d8: 5796 lw a5,100(sp) - 2da: 10f12423 sw a5,264(sp) - 2de: 57aa lw a5,168(sp) - 2e0: ddbe sw a5,248(sp) - 2e2: 00000097 auipc ra,0x0 - 2e6: 000080e7 jalr ra # 2e2 <.L45+0x30> - -000002ea <.LVL29>: - 2ea: 1a051763 bnez a0,498 <.L41> - 2ee: 11ec add a1,sp,236 - 2f0: 19e8 add a0,sp,252 - 2f2: 00000097 auipc ra,0x0 - 2f6: 000080e7 jalr ra # 2f2 <.LVL29+0x8> - -000002fa <.LVL30>: - 2fa: 18a05f63 blez a0,498 <.L41> - -000002fe <.L5>: - 2fe: 00000737 lui a4,0x0 - 302: 00c72703 lw a4,12(a4) # c <__multc3+0xc> - 306: 57fd li a5,-1 - 308: d7be sw a5,236(sp) - 30a: d53a sw a4,168(sp) - 30c: 4702 lw a4,0(sp) - 30e: d9be sw a5,240(sp) - 310: dbbe sw a5,244(sp) - 312: dfba sw a4,252(sp) - 314: 4712 lw a4,4(sp) - 316: 57aa lw a5,168(sp) - 318: 11ec add a1,sp,236 - 31a: 10e12023 sw a4,256(sp) - 31e: 4722 lw a4,8(sp) - 320: 19e8 add a0,sp,252 - 322: 4405 li s0,1 - 324: 10e12223 sw a4,260(sp) - 328: 10912423 sw s1,264(sp) - 32c: ddbe sw a5,248(sp) - 32e: 00000097 auipc ra,0x0 - 332: 000080e7 jalr ra # 32e <.L5+0x30> - -00000336 <.LVL31>: - 336: e911 bnez a0,34a <.L8> - 338: 11ec add a1,sp,236 - 33a: 19e8 add a0,sp,252 - 33c: 00000097 auipc ra,0x0 - 340: 000080e7 jalr ra # 33c <.LVL31+0x6> - -00000344 <.LVL32>: - 344: 00a05363 blez a0,34a <.L8> - 348: 4401 li s0,0 - -0000034a <.L8>: - 34a: 00144593 xor a1,s0,1 - 34e: 8985 and a1,a1,1 - 350: 19e8 add a0,sp,252 - 352: 00000097 auipc ra,0x0 - 356: 000080e7 jalr ra # 352 <.L8+0x8> - -0000035a <.LVL33>: - 35a: 10812703 lw a4,264(sp) - 35e: 800007b7 lui a5,0x80000 - 362: fff7c693 not a3,a5 - 366: 8f75 and a4,a4,a3 - 368: 46b2 lw a3,12(sp) - 36a: 54fd li s1,-1 - 36c: 11ec add a1,sp,236 - 36e: 8ff5 and a5,a5,a3 - 370: 8fd9 or a5,a5,a4 - 372: 00000737 lui a4,0x0 - 376: c63e sw a5,12(sp) - -00000378 <.LVL34>: - 378: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - -0000037c <.LVL35>: - 37c: 56fe lw a3,252(sp) - 37e: 19e8 add a0,sp,252 - -00000380 <.LVL36>: - 380: d53e sw a5,168(sp) - 382: 47c2 lw a5,16(sp) - 384: c036 sw a3,0(sp) - 386: 10012683 lw a3,256(sp) - -0000038a <.LVL37>: - 38a: dfbe sw a5,252(sp) - 38c: 47d2 lw a5,20(sp) - 38e: c236 sw a3,4(sp) - 390: 10412683 lw a3,260(sp) - 394: 10f12023 sw a5,256(sp) - -00000398 <.LVL38>: - 398: 47e2 lw a5,24(sp) - 39a: c436 sw a3,8(sp) - 39c: 4405 li s0,1 - 39e: 10f12223 sw a5,260(sp) - -000003a2 <.LVL39>: - 3a2: 5796 lw a5,100(sp) - 3a4: d7a6 sw s1,236(sp) - 3a6: d9a6 sw s1,240(sp) - 3a8: 10f12423 sw a5,264(sp) - 3ac: 57aa lw a5,168(sp) - 3ae: dba6 sw s1,244(sp) - 3b0: ddbe sw a5,248(sp) - 3b2: 00000097 auipc ra,0x0 - 3b6: 000080e7 jalr ra # 3b2 <.LVL39+0x10> - -000003ba <.LVL40>: - 3ba: e911 bnez a0,3ce <.L9> - 3bc: 11ec add a1,sp,236 - 3be: 19e8 add a0,sp,252 - 3c0: 00000097 auipc ra,0x0 - 3c4: 000080e7 jalr ra # 3c0 <.LVL40+0x6> - -000003c8 <.LVL41>: - 3c8: 00a05363 blez a0,3ce <.L9> - 3cc: 4401 li s0,0 - -000003ce <.L9>: - 3ce: 00144593 xor a1,s0,1 - 3d2: 8985 and a1,a1,1 - 3d4: 19e8 add a0,sp,252 - 3d6: 00000097 auipc ra,0x0 - 3da: 000080e7 jalr ra # 3d6 <.L9+0x8> - -000003de <.LVL42>: - 3de: 10812703 lw a4,264(sp) - 3e2: 800007b7 lui a5,0x80000 - 3e6: fff7c693 not a3,a5 - 3ea: 8f75 and a4,a4,a3 - 3ec: 46f2 lw a3,28(sp) - 3ee: 11ec add a1,sp,236 - 3f0: 19e8 add a0,sp,252 - 3f2: 8ff5 and a5,a5,a3 - 3f4: 8fd9 or a5,a5,a4 - 3f6: ce3e sw a5,28(sp) - -000003f8 <.LVL43>: - 3f8: 5782 lw a5,32(sp) - -000003fa <.LVL44>: - 3fa: 56fe lw a3,252(sp) - 3fc: dfbe sw a5,252(sp) - -000003fe <.LVL45>: - 3fe: 5792 lw a5,36(sp) - 400: c836 sw a3,16(sp) - 402: 10012683 lw a3,256(sp) - -00000406 <.LVL46>: - 406: 10f12023 sw a5,256(sp) - -0000040a <.LVL47>: - 40a: 57a2 lw a5,40(sp) - 40c: ca36 sw a3,20(sp) - 40e: 10412683 lw a3,260(sp) - -00000412 <.LVL48>: - 412: 10f12223 sw a5,260(sp) - -00000416 <.LVL49>: - 416: 57b2 lw a5,44(sp) - 418: cc36 sw a3,24(sp) - 41a: 10f12423 sw a5,264(sp) - 41e: 5782 lw a5,32(sp) - 420: d7be sw a5,236(sp) - 422: 5792 lw a5,36(sp) - 424: d9be sw a5,240(sp) - 426: 57a2 lw a5,40(sp) - 428: dbbe sw a5,244(sp) - 42a: 57b2 lw a5,44(sp) - 42c: ddbe sw a5,248(sp) - 42e: 00000097 auipc ra,0x0 - 432: 000080e7 jalr ra # 42e <.LVL49+0x18> - -00000436 <.LVL50>: - 436: c919 beqz a0,44c <.L10> - 438: 5732 lw a4,44(sp) - 43a: 4781 li a5,0 - 43c: 00075463 bgez a4,444 <.L12> - 440: 800007b7 lui a5,0x80000 - -00000444 <.L12>: - 444: d002 sw zero,32(sp) - 446: d202 sw zero,36(sp) - 448: d402 sw zero,40(sp) - 44a: d63e sw a5,44(sp) - -0000044c <.L10>: - 44c: 57c2 lw a5,48(sp) - 44e: 11ec add a1,sp,236 - 450: 19e8 add a0,sp,252 - 452: dfbe sw a5,252(sp) - 454: 57d2 lw a5,52(sp) - 456: 10f12023 sw a5,256(sp) - 45a: 57e2 lw a5,56(sp) - 45c: 10f12223 sw a5,260(sp) - 460: 57f2 lw a5,60(sp) - 462: 10f12423 sw a5,264(sp) - 466: 57c2 lw a5,48(sp) - 468: d7be sw a5,236(sp) - 46a: 57d2 lw a5,52(sp) - 46c: d9be sw a5,240(sp) - 46e: 57e2 lw a5,56(sp) - 470: dbbe sw a5,244(sp) - 472: 57f2 lw a5,60(sp) - 474: ddbe sw a5,248(sp) - 476: 00000097 auipc ra,0x0 - 47a: 000080e7 jalr ra # 476 <.L10+0x2a> - -0000047e <.LVL52>: - 47e: c919 beqz a0,494 <.L82> - 480: 5772 lw a4,60(sp) - 482: 4781 li a5,0 - 484: 00075463 bgez a4,48c <.L14> - 488: 800007b7 lui a5,0x80000 - -0000048c <.L14>: - 48c: d802 sw zero,48(sp) - 48e: da02 sw zero,52(sp) - 490: dc02 sw zero,56(sp) - 492: de3e sw a5,60(sp) - -00000494 <.L82>: - 494: 4485 li s1,1 - 496: a011 j 49a <.L7> - -00000498 <.L41>: - 498: 4481 li s1,0 - -0000049a <.L7>: - 49a: 5732 lw a4,44(sp) - 49c: 800007b7 lui a5,0x80000 - 4a0: fff7c793 not a5,a5 - 4a4: 00f77433 and s0,a4,a5 - 4a8: 5772 lw a4,60(sp) - 4aa: 11ec add a1,sp,236 - 4ac: 19e8 add a0,sp,252 - 4ae: 8ff9 and a5,a5,a4 - 4b0: 00000737 lui a4,0x0 - 4b4: 00c72703 lw a4,12(a4) # c <__multc3+0xc> - 4b8: d2be sw a5,100(sp) - 4ba: 57fd li a5,-1 - 4bc: d53a sw a4,168(sp) - 4be: 5702 lw a4,32(sp) - 4c0: d7be sw a5,236(sp) - 4c2: d9be sw a5,240(sp) - 4c4: dfba sw a4,252(sp) - 4c6: 5712 lw a4,36(sp) - 4c8: dbbe sw a5,244(sp) - 4ca: 57aa lw a5,168(sp) - 4cc: 10e12023 sw a4,256(sp) - 4d0: 5722 lw a4,40(sp) - 4d2: 10812423 sw s0,264(sp) - 4d6: ddbe sw a5,248(sp) - 4d8: 10e12223 sw a4,260(sp) - 4dc: 00000097 auipc ra,0x0 - 4e0: 000080e7 jalr ra # 4dc <.L7+0x42> - -000004e4 <.LVL56>: - 4e4: e909 bnez a0,4f6 <.L48> - 4e6: 11ec add a1,sp,236 - 4e8: 19e8 add a0,sp,252 - 4ea: 00000097 auipc ra,0x0 - 4ee: 000080e7 jalr ra # 4ea <.LVL56+0x6> - -000004f2 <.LVL57>: - 4f2: 04a04863 bgtz a0,542 <.L15> - -000004f6 <.L48>: - 4f6: 00000737 lui a4,0x0 - 4fa: 00c72703 lw a4,12(a4) # c <__multc3+0xc> - 4fe: 57fd li a5,-1 - 500: d7be sw a5,236(sp) - 502: d53a sw a4,168(sp) - 504: 5742 lw a4,48(sp) - 506: d9be sw a5,240(sp) - 508: dbbe sw a5,244(sp) - 50a: dfba sw a4,252(sp) - 50c: 5752 lw a4,52(sp) - 50e: 57aa lw a5,168(sp) - 510: 11ec add a1,sp,236 - 512: 10e12023 sw a4,256(sp) - 516: 5762 lw a4,56(sp) - 518: 19e8 add a0,sp,252 - 51a: ddbe sw a5,248(sp) - 51c: 10e12223 sw a4,260(sp) - 520: 5716 lw a4,100(sp) - 522: 10e12423 sw a4,264(sp) - 526: 00000097 auipc ra,0x0 - 52a: 000080e7 jalr ra # 526 <.L48+0x30> - -0000052e <.LVL58>: - 52e: 38051263 bnez a0,8b2 <.L17> - 532: 11ec add a1,sp,236 - 534: 19e8 add a0,sp,252 - 536: 00000097 auipc ra,0x0 - 53a: 000080e7 jalr ra # 536 <.LVL58+0x8> - -0000053e <.LVL59>: - 53e: 36a05a63 blez a0,8b2 <.L17> - -00000542 <.L15>: - 542: 00000737 lui a4,0x0 - 546: 00c72703 lw a4,12(a4) # c <__multc3+0xc> - 54a: 57fd li a5,-1 - 54c: d7be sw a5,236(sp) - 54e: c2ba sw a4,68(sp) - -00000550 <.LVL60>: - 550: 5702 lw a4,32(sp) - 552: d9be sw a5,240(sp) - 554: dbbe sw a5,244(sp) - 556: dfba sw a4,252(sp) - 558: 5712 lw a4,36(sp) - 55a: 4796 lw a5,68(sp) - 55c: 11ec add a1,sp,236 - 55e: 10e12023 sw a4,256(sp) - 562: 5722 lw a4,40(sp) - 564: 19e8 add a0,sp,252 - 566: 4485 li s1,1 - -00000568 <.LVL61>: - 568: 10e12223 sw a4,260(sp) - 56c: 10812423 sw s0,264(sp) - 570: ddbe sw a5,248(sp) - 572: 00000097 auipc ra,0x0 - 576: 000080e7 jalr ra # 572 <.LVL61+0xa> - -0000057a <.LVL62>: - 57a: e911 bnez a0,58e <.L18> - 57c: 11ec add a1,sp,236 - 57e: 19e8 add a0,sp,252 - 580: 00000097 auipc ra,0x0 - 584: 000080e7 jalr ra # 580 <.LVL62+0x6> - -00000588 <.LVL63>: - 588: 00a05363 blez a0,58e <.L18> - 58c: 4481 li s1,0 - -0000058e <.L18>: - 58e: 0014c593 xor a1,s1,1 - 592: 8985 and a1,a1,1 - 594: 19e8 add a0,sp,252 - 596: 00000097 auipc ra,0x0 - 59a: 000080e7 jalr ra # 596 <.L18+0x8> - -0000059e <.LVL64>: - 59e: 10812703 lw a4,264(sp) - 5a2: 800007b7 lui a5,0x80000 - 5a6: fff7c693 not a3,a5 - 5aa: 8f75 and a4,a4,a3 - 5ac: 56b2 lw a3,44(sp) - 5ae: 54fd li s1,-1 - 5b0: 11ec add a1,sp,236 - 5b2: 8ff5 and a5,a5,a3 - 5b4: 8fd9 or a5,a5,a4 - 5b6: 00000737 lui a4,0x0 - 5ba: d63e sw a5,44(sp) - -000005bc <.LVL65>: - 5bc: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - -000005c0 <.LVL66>: - 5c0: 56fe lw a3,252(sp) - 5c2: 19e8 add a0,sp,252 - -000005c4 <.LVL67>: - 5c4: c2be sw a5,68(sp) - 5c6: 57c2 lw a5,48(sp) - 5c8: d036 sw a3,32(sp) - 5ca: 10012683 lw a3,256(sp) - -000005ce <.LVL68>: - 5ce: dfbe sw a5,252(sp) - -000005d0 <.LVL69>: - 5d0: 57d2 lw a5,52(sp) - 5d2: d236 sw a3,36(sp) - 5d4: 10412683 lw a3,260(sp) - 5d8: 10f12023 sw a5,256(sp) - -000005dc <.LVL70>: - 5dc: 57e2 lw a5,56(sp) - 5de: d436 sw a3,40(sp) - 5e0: 4405 li s0,1 - 5e2: 10f12223 sw a5,260(sp) - -000005e6 <.LVL71>: - 5e6: 5796 lw a5,100(sp) - 5e8: d7a6 sw s1,236(sp) - 5ea: d9a6 sw s1,240(sp) - 5ec: 10f12423 sw a5,264(sp) - 5f0: 4796 lw a5,68(sp) - 5f2: dba6 sw s1,244(sp) - 5f4: ddbe sw a5,248(sp) - 5f6: 00000097 auipc ra,0x0 - 5fa: 000080e7 jalr ra # 5f6 <.LVL71+0x10> - -000005fe <.LVL72>: - 5fe: e911 bnez a0,612 <.L19> - 600: 11ec add a1,sp,236 - 602: 19e8 add a0,sp,252 - 604: 00000097 auipc ra,0x0 - 608: 000080e7 jalr ra # 604 <.LVL72+0x6> - -0000060c <.LVL73>: - 60c: 00a05363 blez a0,612 <.L19> - 610: 4401 li s0,0 - -00000612 <.L19>: - 612: 00144593 xor a1,s0,1 - 616: 8985 and a1,a1,1 - 618: 19e8 add a0,sp,252 - 61a: 00000097 auipc ra,0x0 - 61e: 000080e7 jalr ra # 61a <.L19+0x8> - -00000622 <.LVL74>: - 622: 10812703 lw a4,264(sp) - 626: 800007b7 lui a5,0x80000 - 62a: fff7c693 not a3,a5 - 62e: 8f75 and a4,a4,a3 - 630: 56f2 lw a3,60(sp) - 632: 11ec add a1,sp,236 - 634: 19e8 add a0,sp,252 - 636: 8ff5 and a5,a5,a3 - 638: 8fd9 or a5,a5,a4 - 63a: de3e sw a5,60(sp) - -0000063c <.LVL75>: - 63c: 4782 lw a5,0(sp) - -0000063e <.LVL76>: - 63e: 56fe lw a3,252(sp) - 640: dfbe sw a5,252(sp) - -00000642 <.LVL77>: - 642: 4792 lw a5,4(sp) - 644: d836 sw a3,48(sp) - 646: 10012683 lw a3,256(sp) - -0000064a <.LVL78>: - 64a: 10f12023 sw a5,256(sp) - -0000064e <.LVL79>: - 64e: 47a2 lw a5,8(sp) - 650: da36 sw a3,52(sp) - 652: 10412683 lw a3,260(sp) - -00000656 <.LVL80>: - 656: 10f12223 sw a5,260(sp) - -0000065a <.LVL81>: - 65a: 47b2 lw a5,12(sp) - 65c: dc36 sw a3,56(sp) - 65e: 10f12423 sw a5,264(sp) - 662: 4782 lw a5,0(sp) - 664: d7be sw a5,236(sp) - 666: 4792 lw a5,4(sp) - 668: d9be sw a5,240(sp) - 66a: 47a2 lw a5,8(sp) - 66c: dbbe sw a5,244(sp) - 66e: 47b2 lw a5,12(sp) - 670: ddbe sw a5,248(sp) - 672: 00000097 auipc ra,0x0 - 676: 000080e7 jalr ra # 672 <.LVL81+0x18> - -0000067a <.LVL82>: - 67a: c919 beqz a0,690 <.L20> - 67c: 4732 lw a4,12(sp) - 67e: 4781 li a5,0 - 680: 00075463 bgez a4,688 <.L22> - 684: 800007b7 lui a5,0x80000 - -00000688 <.L22>: - 688: c002 sw zero,0(sp) - -0000068a <.LVL83>: - 68a: c202 sw zero,4(sp) - 68c: c402 sw zero,8(sp) - 68e: c63e sw a5,12(sp) - -00000690 <.L20>: - 690: 47c2 lw a5,16(sp) - 692: 11ec add a1,sp,236 - 694: 19e8 add a0,sp,252 - 696: dfbe sw a5,252(sp) - 698: 47d2 lw a5,20(sp) - 69a: 10f12023 sw a5,256(sp) - 69e: 47e2 lw a5,24(sp) - 6a0: 10f12223 sw a5,260(sp) - 6a4: 47f2 lw a5,28(sp) - 6a6: 10f12423 sw a5,264(sp) - 6aa: 47c2 lw a5,16(sp) - 6ac: d7be sw a5,236(sp) - 6ae: 47d2 lw a5,20(sp) - 6b0: d9be sw a5,240(sp) - 6b2: 47e2 lw a5,24(sp) - 6b4: dbbe sw a5,244(sp) - 6b6: 47f2 lw a5,28(sp) - 6b8: ddbe sw a5,248(sp) - 6ba: 00000097 auipc ra,0x0 - 6be: 000080e7 jalr ra # 6ba <.L20+0x2a> - -000006c2 <.LVL85>: - 6c2: c919 beqz a0,6d8 <.L23> - 6c4: 4772 lw a4,28(sp) - 6c6: 4781 li a5,0 - 6c8: 00075463 bgez a4,6d0 <.L25> - 6cc: 800007b7 lui a5,0x80000 - -000006d0 <.L25>: - 6d0: c802 sw zero,16(sp) - -000006d2 <.LVL86>: - 6d2: ca02 sw zero,20(sp) - 6d4: cc02 sw zero,24(sp) - 6d6: ce3e sw a5,28(sp) - -000006d8 <.L23>: - 6d8: 4782 lw a5,0(sp) - 6da: 09f0 add a2,sp,220 - 6dc: 11ec add a1,sp,236 - 6de: d7be sw a5,236(sp) - 6e0: 4792 lw a5,4(sp) - 6e2: 19e8 add a0,sp,252 - 6e4: d9be sw a5,240(sp) - 6e6: 47a2 lw a5,8(sp) - 6e8: dbbe sw a5,244(sp) - 6ea: 47b2 lw a5,12(sp) - 6ec: ddbe sw a5,248(sp) - 6ee: 5782 lw a5,32(sp) - 6f0: cfbe sw a5,220(sp) - 6f2: 5792 lw a5,36(sp) - 6f4: d1be sw a5,224(sp) - 6f6: 57a2 lw a5,40(sp) - 6f8: d3be sw a5,228(sp) - 6fa: 57b2 lw a5,44(sp) - 6fc: d5be sw a5,232(sp) - 6fe: 00000097 auipc ra,0x0 - 702: 000080e7 jalr ra # 6fe <.L23+0x26> - -00000706 <.LVL88>: - 706: 47c2 lw a5,16(sp) - 708: 537e lw t1,252(sp) - 70a: 10012683 lw a3,256(sp) - 70e: cfbe sw a5,220(sp) - 710: 47d2 lw a5,20(sp) - 712: 01f0 add a2,sp,204 - 714: 09ec add a1,sp,220 - 716: d1be sw a5,224(sp) - 718: 47e2 lw a5,24(sp) - 71a: 11e8 add a0,sp,236 - 71c: 10412483 lw s1,260(sp) - 720: d3be sw a5,228(sp) - 722: 47f2 lw a5,28(sp) - 724: 10812403 lw s0,264(sp) - 728: c49a sw t1,72(sp) - 72a: d5be sw a5,232(sp) - 72c: 57c2 lw a5,48(sp) - 72e: c2b6 sw a3,68(sp) - 730: c7be sw a5,204(sp) - 732: 57d2 lw a5,52(sp) - 734: c9be sw a5,208(sp) - 736: 57e2 lw a5,56(sp) - 738: cbbe sw a5,212(sp) - 73a: 57f2 lw a5,60(sp) - 73c: cdbe sw a5,216(sp) - 73e: 00000097 auipc ra,0x0 - 742: 000080e7 jalr ra # 73e <.LVL88+0x38> - -00000746 <.LVL89>: - 746: 55be lw a1,236(sp) - 748: 564e lw a2,240(sp) - 74a: 4326 lw t1,72(sp) - 74c: 575e lw a4,244(sp) - 74e: 57ee lw a5,248(sp) - 750: 4696 lw a3,68(sp) - 752: df2e sw a1,188(sp) - 754: c1b2 sw a2,192(sp) - 756: 01ec add a1,sp,204 - 758: 1970 add a2,sp,188 - 75a: 09e8 add a0,sp,220 - 75c: c79a sw t1,204(sp) - 75e: c9b6 sw a3,208(sp) - 760: cba6 sw s1,212(sp) - 762: cda2 sw s0,216(sp) - 764: c3ba sw a4,196(sp) - 766: c5be sw a5,200(sp) - 768: 00000097 auipc ra,0x0 - 76c: 000080e7 jalr ra # 768 <.LVL89+0x22> - -00000770 <.LVL90>: - 770: 467e lw a2,220(sp) - 772: 568e lw a3,224(sp) - 774: 571e lw a4,228(sp) - 776: 57ae lw a5,232(sp) - 778: 7fff0437 lui s0,0x7fff0 - 77c: df32 sw a2,188(sp) - 77e: 196c add a1,sp,188 - 780: 1170 add a2,sp,172 - 782: 01e8 add a0,sp,204 - 784: c1b6 sw a3,192(sp) - 786: c3ba sw a4,196(sp) - 788: c5be sw a5,200(sp) - 78a: d702 sw zero,172(sp) - 78c: d902 sw zero,176(sp) - 78e: db02 sw zero,180(sp) - 790: dd22 sw s0,184(sp) - 792: 00000097 auipc ra,0x0 - 796: 000080e7 jalr ra # 792 <.LVL90+0x22> - -0000079a <.LVL91>: - 79a: 47be lw a5,204(sp) - 79c: 09f0 add a2,sp,220 - 79e: 11ec add a1,sp,236 - 7a0: c2be sw a5,68(sp) - 7a2: 47ce lw a5,208(sp) - 7a4: 19e8 add a0,sp,252 - 7a6: c4be sw a5,72(sp) - 7a8: 47de lw a5,212(sp) - 7aa: c6be sw a5,76(sp) - 7ac: 47ee lw a5,216(sp) - 7ae: c8be sw a5,80(sp) - -000007b0 <.LVL92>: - 7b0: 4782 lw a5,0(sp) - -000007b2 <.LVL93>: - 7b2: d7be sw a5,236(sp) - 7b4: 4792 lw a5,4(sp) - 7b6: d9be sw a5,240(sp) - 7b8: 47a2 lw a5,8(sp) - 7ba: dbbe sw a5,244(sp) - 7bc: 47b2 lw a5,12(sp) - 7be: ddbe sw a5,248(sp) - 7c0: 57c2 lw a5,48(sp) - 7c2: cfbe sw a5,220(sp) - 7c4: 57d2 lw a5,52(sp) - 7c6: d1be sw a5,224(sp) - 7c8: 57e2 lw a5,56(sp) - 7ca: d3be sw a5,228(sp) - 7cc: 57f2 lw a5,60(sp) - 7ce: d5be sw a5,232(sp) - 7d0: 00000097 auipc ra,0x0 - 7d4: 000080e7 jalr ra # 7d0 <.LVL93+0x1e> - -000007d8 <.LVL94>: - 7d8: 47c2 lw a5,16(sp) - 7da: 537e lw t1,252(sp) - 7dc: 10012683 lw a3,256(sp) - 7e0: cfbe sw a5,220(sp) - 7e2: 47d2 lw a5,20(sp) - 7e4: 10412703 lw a4,260(sp) - 7e8: 01f0 add a2,sp,204 - 7ea: d1be sw a5,224(sp) - 7ec: 47e2 lw a5,24(sp) - 7ee: 09ec add a1,sp,220 - 7f0: 11e8 add a0,sp,236 - 7f2: d3be sw a5,228(sp) - 7f4: 47f2 lw a5,28(sp) - 7f6: 10812483 lw s1,264(sp) - 7fa: c41a sw t1,8(sp) - 7fc: d5be sw a5,232(sp) - 7fe: 5782 lw a5,32(sp) - 800: c236 sw a3,4(sp) - 802: c03a sw a4,0(sp) - 804: c7be sw a5,204(sp) - 806: 5792 lw a5,36(sp) - 808: c9be sw a5,208(sp) - 80a: 57a2 lw a5,40(sp) - 80c: cbbe sw a5,212(sp) - 80e: 57b2 lw a5,44(sp) - 810: cdbe sw a5,216(sp) - 812: 00000097 auipc ra,0x0 - 816: 000080e7 jalr ra # 812 <.LVL94+0x3a> - -0000081a <.LVL95>: - 81a: 553e lw a0,236(sp) - 81c: 55ce lw a1,240(sp) - 81e: 565e lw a2,244(sp) - 820: 57ee lw a5,248(sp) - 822: 4322 lw t1,8(sp) - 824: 4692 lw a3,4(sp) - 826: 4702 lw a4,0(sp) - 828: df2a sw a0,188(sp) - 82a: c1ae sw a1,192(sp) - 82c: c3b2 sw a2,196(sp) - 82e: 01ec add a1,sp,204 - 830: 1970 add a2,sp,188 - 832: 09e8 add a0,sp,220 - 834: c79a sw t1,204(sp) - 836: c9b6 sw a3,208(sp) - 838: cbba sw a4,212(sp) - 83a: c5be sw a5,200(sp) - 83c: cda6 sw s1,216(sp) - 83e: 00000097 auipc ra,0x0 - 842: 000080e7 jalr ra # 83e <.LVL95+0x24> - -00000846 <.LVL96>: - 846: 467e lw a2,220(sp) - 848: 57ae lw a5,232(sp) - 84a: 568e lw a3,224(sp) - 84c: 571e lw a4,228(sp) - 84e: df32 sw a2,188(sp) - 850: 196c add a1,sp,188 - 852: 1170 add a2,sp,172 - 854: 01e8 add a0,sp,204 - 856: c5be sw a5,200(sp) - 858: c1b6 sw a3,192(sp) - 85a: c3ba sw a4,196(sp) - 85c: d702 sw zero,172(sp) - 85e: d902 sw zero,176(sp) - 860: db02 sw zero,180(sp) - 862: dd22 sw s0,184(sp) - 864: 00000097 auipc ra,0x0 - 868: 000080e7 jalr ra # 864 <.LVL96+0x1e> - -0000086c <.LVL97>: - 86c: 47be lw a5,204(sp) - 86e: cabe sw a5,84(sp) - -00000870 <.LVL98>: - 870: 47ce lw a5,208(sp) - 872: ccbe sw a5,88(sp) - 874: 47de lw a5,212(sp) - 876: cebe sw a5,92(sp) - 878: 47ee lw a5,216(sp) - 87a: d0be sw a5,96(sp) - -0000087c <.L2>: - 87c: 4786 lw a5,64(sp) - 87e: 4716 lw a4,68(sp) - 880: 11412083 lw ra,276(sp) - 884: 11012403 lw s0,272(sp) - 888: c398 sw a4,0(a5) - 88a: 4726 lw a4,72(sp) - 88c: 10c12483 lw s1,268(sp) - 890: 853e mv a0,a5 - 892: c3d8 sw a4,4(a5) - 894: 4736 lw a4,76(sp) - 896: c798 sw a4,8(a5) - 898: 4746 lw a4,80(sp) - 89a: c7d8 sw a4,12(a5) - 89c: 4756 lw a4,84(sp) - 89e: cb98 sw a4,16(a5) - 8a0: 4766 lw a4,88(sp) - 8a2: cbd8 sw a4,20(a5) - 8a4: 4776 lw a4,92(sp) - 8a6: cf98 sw a4,24(a5) - 8a8: 5706 lw a4,96(sp) - 8aa: cfd8 sw a4,28(a5) - 8ac: 11810113 add sp,sp,280 - -000008b0 <.LVL100>: - 8b0: 8082 ret - -000008b2 <.L17>: - 8b2: e20493e3 bnez s1,6d8 <.L23> - 8b6: 47ea lw a5,152(sp) - 8b8: 00000737 lui a4,0x0 - 8bc: 547d li s0,-1 - 8be: 00179493 sll s1,a5,0x1 - -000008c2 <.LVL102>: - 8c2: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - 8c6: 8085 srl s1,s1,0x1 - 8c8: 11ec add a1,sp,236 - 8ca: d2be sw a5,100(sp) - 8cc: 57a6 lw a5,104(sp) - 8ce: 19e8 add a0,sp,252 - 8d0: 10912423 sw s1,264(sp) - 8d4: dfbe sw a5,252(sp) - 8d6: 57b6 lw a5,108(sp) - 8d8: d7a2 sw s0,236(sp) - 8da: d9a2 sw s0,240(sp) - 8dc: 10f12023 sw a5,256(sp) - 8e0: 57c6 lw a5,112(sp) - 8e2: dba2 sw s0,244(sp) - 8e4: 10f12223 sw a5,260(sp) - 8e8: 5796 lw a5,100(sp) - 8ea: ddbe sw a5,248(sp) - 8ec: 00000097 auipc ra,0x0 - 8f0: 000080e7 jalr ra # 8ec <.LVL102+0x2a> - -000008f4 <.LVL103>: - 8f4: e909 bnez a0,906 <.L51> - 8f6: 11ec add a1,sp,236 - 8f8: 19e8 add a0,sp,252 - 8fa: 00000097 auipc ra,0x0 - 8fe: 000080e7 jalr ra # 8fa <.LVL103+0x6> - -00000902 <.LVL104>: - 902: 0ea04b63 bgtz a0,9f8 <.L26> - -00000906 <.L51>: - 906: 47fa lw a5,156(sp) - 908: 00000737 lui a4,0x0 - 90c: 547d li s0,-1 - 90e: 00179493 sll s1,a5,0x1 - 912: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - 916: 8085 srl s1,s1,0x1 - 918: 11ec add a1,sp,236 - 91a: d2be sw a5,100(sp) - 91c: 57d6 lw a5,116(sp) - 91e: 19e8 add a0,sp,252 - 920: 10912423 sw s1,264(sp) - 924: dfbe sw a5,252(sp) - 926: 57e6 lw a5,120(sp) - 928: d7a2 sw s0,236(sp) - 92a: d9a2 sw s0,240(sp) - 92c: 10f12023 sw a5,256(sp) - 930: 57f6 lw a5,124(sp) - 932: dba2 sw s0,244(sp) - 934: 10f12223 sw a5,260(sp) - 938: 5796 lw a5,100(sp) - 93a: ddbe sw a5,248(sp) - 93c: 00000097 auipc ra,0x0 - 940: 000080e7 jalr ra # 93c <.L51+0x36> - -00000944 <.LVL105>: - 944: e909 bnez a0,956 <.L52> - 946: 11ec add a1,sp,236 - 948: 19e8 add a0,sp,252 - 94a: 00000097 auipc ra,0x0 - 94e: 000080e7 jalr ra # 94a <.LVL105+0x6> - -00000952 <.LVL106>: - 952: 0aa04363 bgtz a0,9f8 <.L26> - -00000956 <.L52>: - 956: 578a lw a5,160(sp) - 958: 00000737 lui a4,0x0 - 95c: 547d li s0,-1 - 95e: 00179493 sll s1,a5,0x1 - 962: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - 966: 8085 srl s1,s1,0x1 - 968: 11ec add a1,sp,236 - 96a: d2be sw a5,100(sp) - 96c: 478a lw a5,128(sp) - 96e: 19e8 add a0,sp,252 - 970: 10912423 sw s1,264(sp) - 974: dfbe sw a5,252(sp) - 976: 479a lw a5,132(sp) - 978: d7a2 sw s0,236(sp) - 97a: d9a2 sw s0,240(sp) - 97c: 10f12023 sw a5,256(sp) - 980: 47aa lw a5,136(sp) - 982: dba2 sw s0,244(sp) - 984: 10f12223 sw a5,260(sp) - 988: 5796 lw a5,100(sp) - 98a: ddbe sw a5,248(sp) - 98c: 00000097 auipc ra,0x0 - 990: 000080e7 jalr ra # 98c <.L52+0x36> - -00000994 <.LVL107>: - 994: e909 bnez a0,9a6 <.L53> - 996: 11ec add a1,sp,236 - 998: 19e8 add a0,sp,252 - 99a: 00000097 auipc ra,0x0 - 99e: 000080e7 jalr ra # 99a <.LVL107+0x6> - -000009a2 <.LVL108>: - 9a2: 04a04b63 bgtz a0,9f8 <.L26> - -000009a6 <.L53>: - 9a6: 579a lw a5,164(sp) - 9a8: 00000737 lui a4,0x0 - 9ac: 547d li s0,-1 - 9ae: 00179493 sll s1,a5,0x1 - 9b2: 00c72783 lw a5,12(a4) # c <__multc3+0xc> - 9b6: 8085 srl s1,s1,0x1 - 9b8: 11ec add a1,sp,236 - 9ba: d2be sw a5,100(sp) - 9bc: 47ba lw a5,140(sp) - 9be: 19e8 add a0,sp,252 - 9c0: 10912423 sw s1,264(sp) - 9c4: dfbe sw a5,252(sp) - 9c6: 47ca lw a5,144(sp) - 9c8: d7a2 sw s0,236(sp) - 9ca: d9a2 sw s0,240(sp) - 9cc: 10f12023 sw a5,256(sp) - 9d0: 47da lw a5,148(sp) - 9d2: dba2 sw s0,244(sp) - 9d4: 10f12223 sw a5,260(sp) - 9d8: 5796 lw a5,100(sp) - 9da: ddbe sw a5,248(sp) - 9dc: 00000097 auipc ra,0x0 - 9e0: 000080e7 jalr ra # 9dc <.L53+0x36> - -000009e4 <.LVL109>: - 9e4: e8051ce3 bnez a0,87c <.L2> - 9e8: 11ec add a1,sp,236 - 9ea: 19e8 add a0,sp,252 - 9ec: 00000097 auipc ra,0x0 - 9f0: 000080e7 jalr ra # 9ec <.LVL109+0x8> - -000009f4 <.LVL110>: - 9f4: e8a054e3 blez a0,87c <.L2> - -000009f8 <.L26>: - 9f8: 4782 lw a5,0(sp) - 9fa: 11ec add a1,sp,236 - 9fc: 19e8 add a0,sp,252 - 9fe: dfbe sw a5,252(sp) - a00: 4792 lw a5,4(sp) - a02: 10f12023 sw a5,256(sp) - a06: 47a2 lw a5,8(sp) - a08: 10f12223 sw a5,260(sp) - a0c: 47b2 lw a5,12(sp) - a0e: 10f12423 sw a5,264(sp) - a12: 4782 lw a5,0(sp) - a14: d7be sw a5,236(sp) - a16: 4792 lw a5,4(sp) - a18: d9be sw a5,240(sp) - a1a: 47a2 lw a5,8(sp) - a1c: dbbe sw a5,244(sp) - a1e: 47b2 lw a5,12(sp) - a20: ddbe sw a5,248(sp) - a22: 00000097 auipc ra,0x0 - a26: 000080e7 jalr ra # a22 <.L26+0x2a> - -00000a2a <.LVL111>: - a2a: c919 beqz a0,a40 <.L30> - a2c: 4732 lw a4,12(sp) - a2e: 4781 li a5,0 - a30: 00075463 bgez a4,a38 <.L32> - a34: 800007b7 lui a5,0x80000 - -00000a38 <.L32>: - a38: c002 sw zero,0(sp) - -00000a3a <.LVL112>: - a3a: c202 sw zero,4(sp) - a3c: c402 sw zero,8(sp) - a3e: c63e sw a5,12(sp) - -00000a40 <.L30>: - a40: 47c2 lw a5,16(sp) - a42: 11ec add a1,sp,236 - a44: 19e8 add a0,sp,252 - a46: dfbe sw a5,252(sp) - a48: 47d2 lw a5,20(sp) - a4a: 10f12023 sw a5,256(sp) - a4e: 47e2 lw a5,24(sp) - a50: 10f12223 sw a5,260(sp) - a54: 47f2 lw a5,28(sp) - a56: 10f12423 sw a5,264(sp) - a5a: 47c2 lw a5,16(sp) - a5c: d7be sw a5,236(sp) - a5e: 47d2 lw a5,20(sp) - a60: d9be sw a5,240(sp) - a62: 47e2 lw a5,24(sp) - a64: dbbe sw a5,244(sp) - a66: 47f2 lw a5,28(sp) - a68: ddbe sw a5,248(sp) - a6a: 00000097 auipc ra,0x0 - a6e: 000080e7 jalr ra # a6a <.L30+0x2a> - -00000a72 <.LVL114>: - a72: c919 beqz a0,a88 <.L33> - a74: 4772 lw a4,28(sp) - a76: 4781 li a5,0 - a78: 00075463 bgez a4,a80 <.L35> - a7c: 800007b7 lui a5,0x80000 - -00000a80 <.L35>: - a80: c802 sw zero,16(sp) - -00000a82 <.LVL115>: - a82: ca02 sw zero,20(sp) - a84: cc02 sw zero,24(sp) - a86: ce3e sw a5,28(sp) - -00000a88 <.L33>: - a88: 5782 lw a5,32(sp) - a8a: 11ec add a1,sp,236 - a8c: 19e8 add a0,sp,252 - a8e: dfbe sw a5,252(sp) - a90: 5792 lw a5,36(sp) - a92: 10f12023 sw a5,256(sp) - a96: 57a2 lw a5,40(sp) - a98: 10f12223 sw a5,260(sp) - a9c: 57b2 lw a5,44(sp) - a9e: 10f12423 sw a5,264(sp) - aa2: 5782 lw a5,32(sp) - aa4: d7be sw a5,236(sp) - aa6: 5792 lw a5,36(sp) - aa8: d9be sw a5,240(sp) - aaa: 57a2 lw a5,40(sp) - aac: dbbe sw a5,244(sp) - aae: 57b2 lw a5,44(sp) - ab0: ddbe sw a5,248(sp) - ab2: 00000097 auipc ra,0x0 - ab6: 000080e7 jalr ra # ab2 <.L33+0x2a> - -00000aba <.LVL117>: - aba: c919 beqz a0,ad0 <.L36> - abc: 5732 lw a4,44(sp) - abe: 4781 li a5,0 - ac0: 00075463 bgez a4,ac8 <.L38> - ac4: 800007b7 lui a5,0x80000 - -00000ac8 <.L38>: - ac8: d002 sw zero,32(sp) - -00000aca <.LVL118>: - aca: d202 sw zero,36(sp) - acc: d402 sw zero,40(sp) - ace: d63e sw a5,44(sp) - -00000ad0 <.L36>: - ad0: 57c2 lw a5,48(sp) - ad2: 11ec add a1,sp,236 - ad4: 19e8 add a0,sp,252 - ad6: dfbe sw a5,252(sp) - ad8: 57d2 lw a5,52(sp) - ada: 10f12023 sw a5,256(sp) - ade: 57e2 lw a5,56(sp) - ae0: 10f12223 sw a5,260(sp) - ae4: 57f2 lw a5,60(sp) - ae6: 10f12423 sw a5,264(sp) - aea: 57c2 lw a5,48(sp) - aec: d7be sw a5,236(sp) - aee: 57d2 lw a5,52(sp) - af0: d9be sw a5,240(sp) - af2: 57e2 lw a5,56(sp) - af4: dbbe sw a5,244(sp) - af6: 57f2 lw a5,60(sp) - af8: ddbe sw a5,248(sp) - afa: 00000097 auipc ra,0x0 - afe: 000080e7 jalr ra # afa <.L36+0x2a> - -00000b02 <.LVL120>: - b02: bc050be3 beqz a0,6d8 <.L23> - b06: 5772 lw a4,60(sp) - b08: 4781 li a5,0 - b0a: 00075463 bgez a4,b12 <.L40> - b0e: 800007b7 lui a5,0x80000 - -00000b12 <.L40>: - b12: d802 sw zero,48(sp) - -00000b14 <.LVL121>: - b14: da02 sw zero,52(sp) - b16: dc02 sw zero,56(sp) - b18: de3e sw a5,60(sp) - -00000b1a <.LVL122>: - b1a: be7d j 6d8 <.L23> - -_divhc3.o: file format elf32-littleriscv - - -_divsc3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divsc3>: - 0: fbc10113 add sp,sp,-68 - 4: c086 sw ra,64(sp) - 6: c232 sw a2,4(sp) - 8: c436 sw a3,8(sp) - a: de22 sw s0,60(sp) - c: dc26 sw s1,56(sp) - e: c62a sw a0,12(sp) - 10: c02e sw a1,0(sp) - 12: 00000097 auipc ra,0x0 - 16: 000080e7 jalr ra # 12 <__divsc3+0x12> - -0000001a <.LVL1>: - 1a: ce2a sw a0,28(sp) - 1c: 4502 lw a0,0(sp) - 1e: d02e sw a1,32(sp) - -00000020 <.LVL2>: - 20: 00000097 auipc ra,0x0 - 24: 000080e7 jalr ra # 20 <.LVL2> - -00000028 <.LVL3>: - 28: d22a sw a0,36(sp) - 2a: 4512 lw a0,4(sp) - 2c: d42e sw a1,40(sp) - -0000002e <.LVL4>: - 2e: 00000097 auipc ra,0x0 - 32: 000080e7 jalr ra # 2e <.LVL4> - -00000036 <.LVL5>: - 36: 842a mv s0,a0 - 38: 4522 lw a0,8(sp) - 3a: 84ae mv s1,a1 - -0000003c <.LVL6>: - 3c: 00000097 auipc ra,0x0 - 40: 000080e7 jalr ra # 3c <.LVL6> - -00000044 <.LVL7>: - 44: 8622 mv a2,s0 - 46: 86a6 mv a3,s1 - 48: ca2a sw a0,20(sp) - 4a: cc2e sw a1,24(sp) - -0000004c <.LVL8>: - 4c: 8522 mv a0,s0 - -0000004e <.LVL9>: - 4e: 85a6 mv a1,s1 - -00000050 <.LVL10>: - 50: 00000097 auipc ra,0x0 - 54: 000080e7 jalr ra # 50 <.LVL10> - -00000058 <.LVL11>: - 58: 4652 lw a2,20(sp) - 5a: 46e2 lw a3,24(sp) - 5c: d62a sw a0,44(sp) - 5e: c82e sw a1,16(sp) - 60: 8532 mv a0,a2 - 62: 85b6 mv a1,a3 - 64: 00000097 auipc ra,0x0 - 68: 000080e7 jalr ra # 64 <.LVL11+0xc> - -0000006c <.LVL12>: - 6c: 47c2 lw a5,16(sp) - 6e: 5732 lw a4,44(sp) - 70: 862a mv a2,a0 - 72: 86ae mv a3,a1 - 74: 853a mv a0,a4 - 76: 85be mv a1,a5 - 78: 00000097 auipc ra,0x0 - 7c: 000080e7 jalr ra # 78 <.LVL12+0xc> - -00000080 <.LVL13>: - 80: d62a sw a0,44(sp) - 82: d82e sw a1,48(sp) - -00000084 <.LVL14>: - 84: 4572 lw a0,28(sp) - -00000086 <.LVL15>: - 86: 5582 lw a1,32(sp) - -00000088 <.LVL16>: - 88: 8622 mv a2,s0 - 8a: 86a6 mv a3,s1 - 8c: 00000097 auipc ra,0x0 - 90: 000080e7 jalr ra # 8c <.LVL16+0x4> - -00000094 <.LVL17>: - 94: 4652 lw a2,20(sp) - 96: 46e2 lw a3,24(sp) - 98: da2a sw a0,52(sp) - 9a: c82e sw a1,16(sp) - 9c: 5512 lw a0,36(sp) - 9e: 55a2 lw a1,40(sp) - a0: 00000097 auipc ra,0x0 - a4: 000080e7 jalr ra # a0 <.LVL17+0xc> - -000000a8 <.LVL18>: - a8: 47c2 lw a5,16(sp) - aa: 5752 lw a4,52(sp) - ac: 862a mv a2,a0 - ae: 86ae mv a3,a1 - b0: 853a mv a0,a4 - b2: 85be mv a1,a5 - b4: 00000097 auipc ra,0x0 - b8: 000080e7 jalr ra # b4 <.LVL18+0xc> - -000000bc <.LVL19>: - bc: 5632 lw a2,44(sp) - be: 56c2 lw a3,48(sp) - c0: 00000097 auipc ra,0x0 - c4: 000080e7 jalr ra # c0 <.LVL19+0x4> - -000000c8 <.LVL20>: - c8: 00000097 auipc ra,0x0 - cc: 000080e7 jalr ra # c8 <.LVL20> - -000000d0 <.LVL21>: - d0: c82a sw a0,16(sp) - -000000d2 <.LVL22>: - d2: 55a2 lw a1,40(sp) - d4: 5512 lw a0,36(sp) - -000000d6 <.LVL23>: - d6: 8622 mv a2,s0 - d8: 86a6 mv a3,s1 - da: 00000097 auipc ra,0x0 - de: 000080e7 jalr ra # da <.LVL23+0x4> - -000000e2 <.LVL24>: - e2: 4652 lw a2,20(sp) - e4: 46e2 lw a3,24(sp) - e6: 84aa mv s1,a0 - -000000e8 <.LVL25>: - e8: 842e mv s0,a1 - ea: 4572 lw a0,28(sp) - ec: 5582 lw a1,32(sp) - ee: 00000097 auipc ra,0x0 - f2: 000080e7 jalr ra # ee <.LVL25+0x6> - -000000f6 <.LVL26>: - f6: 862a mv a2,a0 - f8: 86ae mv a3,a1 - fa: 8526 mv a0,s1 - fc: 85a2 mv a1,s0 - fe: 00000097 auipc ra,0x0 - 102: 000080e7 jalr ra # fe <.LVL26+0x8> - -00000106 <.LVL27>: - 106: 5632 lw a2,44(sp) - 108: 56c2 lw a3,48(sp) - 10a: 00000097 auipc ra,0x0 - 10e: 000080e7 jalr ra # 10a <.LVL27+0x4> - -00000112 <.LVL28>: - 112: 00000097 auipc ra,0x0 - 116: 000080e7 jalr ra # 112 <.LVL28> - -0000011a <.LVL29>: - 11a: 45c2 lw a1,16(sp) - 11c: ca2a sw a0,20(sp) - -0000011e <.LVL30>: - 11e: 852e mv a0,a1 - -00000120 <.LVL31>: - 120: 00000097 auipc ra,0x0 - 124: 000080e7 jalr ra # 120 <.LVL31> - -00000128 <.LVL32>: - 128: cd3d beqz a0,1a6 <.L2> - 12a: 45d2 lw a1,20(sp) - 12c: 852e mv a0,a1 - 12e: 00000097 auipc ra,0x0 - 132: 000080e7 jalr ra # 12e <.LVL32+0x6> - -00000136 <.LVL33>: - 136: c925 beqz a0,1a6 <.L2> - 138: 4512 lw a0,4(sp) - 13a: 00000593 li a1,0 - 13e: 00000097 auipc ra,0x0 - 142: 000080e7 jalr ra # 13e <.LVL33+0x8> - -00000146 <.LVL34>: - 146: e925 bnez a0,1b6 <.L5> - 148: 4522 lw a0,8(sp) - 14a: 00000593 li a1,0 - 14e: 00000097 auipc ra,0x0 - 152: 000080e7 jalr ra # 14e <.LVL34+0x8> - -00000156 <.LVL35>: - 156: e125 bnez a0,1b6 <.L5> - 158: 45b2 lw a1,12(sp) - 15a: 852e mv a0,a1 - 15c: 00000097 auipc ra,0x0 - 160: 000080e7 jalr ra # 15c <.LVL35+0x6> - -00000164 <.LVL36>: - 164: c901 beqz a0,174 <.L8> - 166: 4582 lw a1,0(sp) - 168: 852e mv a0,a1 - 16a: 00000097 auipc ra,0x0 - 16e: 000080e7 jalr ra # 16a <.LVL36+0x6> - -00000172 <.LVL37>: - 172: e131 bnez a0,1b6 <.L5> - -00000174 <.L8>: - 174: 000007b7 lui a5,0x0 - 178: 0007a403 lw s0,0(a5) # 0 <__divsc3> - 17c: 4792 lw a5,4(sp) - 17e: 0007d663 bgez a5,18a <.L10> - 182: 000007b7 lui a5,0x0 - 186: 0007a403 lw s0,0(a5) # 0 <__divsc3> - -0000018a <.L10>: - 18a: 45b2 lw a1,12(sp) - 18c: 8522 mv a0,s0 - 18e: 00000097 auipc ra,0x0 - 192: 000080e7 jalr ra # 18e <.L10+0x4> - -00000196 <.LVL38>: - 196: 4582 lw a1,0(sp) - 198: c82a sw a0,16(sp) - -0000019a <.LVL39>: - 19a: 8522 mv a0,s0 - -0000019c <.L31>: - 19c: 00000097 auipc ra,0x0 - 1a0: 000080e7 jalr ra # 19c <.L31> - -000001a4 <.LVL41>: - 1a4: ca2a sw a0,20(sp) - -000001a6 <.L2>: - 1a6: 4086 lw ra,64(sp) - 1a8: 5472 lw s0,60(sp) - 1aa: 4542 lw a0,16(sp) - 1ac: 45d2 lw a1,20(sp) - 1ae: 54e2 lw s1,56(sp) - 1b0: 04410113 add sp,sp,68 - -000001b4 <.LVL43>: - 1b4: 8082 ret - -000001b6 <.L5>: - 1b6: 47b2 lw a5,12(sp) - 1b8: 00179413 sll s0,a5,0x1 - 1bc: 000007b7 lui a5,0x0 - 1c0: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 1c4: 8005 srl s0,s0,0x1 - 1c6: 8522 mv a0,s0 - 1c8: 84be mv s1,a5 - 1ca: 00000097 auipc ra,0x0 - 1ce: 000080e7 jalr ra # 1ca <.L5+0x14> - -000001d2 <.LVL45>: - 1d2: e911 bnez a0,1e6 <.L25> - 1d4: 0004a583 lw a1,0(s1) - 1d8: 8522 mv a0,s0 - 1da: 00000097 auipc ra,0x0 - 1de: 000080e7 jalr ra # 1da <.LVL45+0x8> - -000001e2 <.LVL46>: - 1e2: 02a04c63 bgtz a0,21a <.L11> - -000001e6 <.L25>: - 1e6: 4782 lw a5,0(sp) - 1e8: 00179493 sll s1,a5,0x1 - 1ec: 000007b7 lui a5,0x0 - 1f0: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 1f4: 8085 srl s1,s1,0x1 - 1f6: 8526 mv a0,s1 - 1f8: 00000097 auipc ra,0x0 - 1fc: 000080e7 jalr ra # 1f8 <.L25+0x12> - -00000200 <.LVL47>: - 200: 18051463 bnez a0,388 <.L13> - 204: 000007b7 lui a5,0x0 - 208: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 20c: 8526 mv a0,s1 - 20e: 00000097 auipc ra,0x0 - 212: 000080e7 jalr ra # 20e <.LVL47+0xe> - -00000216 <.LVL48>: - 216: 16a05963 blez a0,388 <.L13> - -0000021a <.L11>: - 21a: 800007b7 lui a5,0x80000 - 21e: fff7c493 not s1,a5 - 222: 4792 lw a5,4(sp) - 224: 8fe5 and a5,a5,s1 - 226: cc3e sw a5,24(sp) - 228: 000007b7 lui a5,0x0 - 22c: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 230: 4562 lw a0,24(sp) - 232: 00000097 auipc ra,0x0 - 236: 000080e7 jalr ra # 232 <.L11+0x18> - -0000023a <.LVL49>: - 23a: 14051763 bnez a0,388 <.L13> - 23e: 000007b7 lui a5,0x0 - 242: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 246: 4562 lw a0,24(sp) - 248: 00000097 auipc ra,0x0 - 24c: 000080e7 jalr ra # 248 <.LVL49+0xe> - -00000250 <.LVL50>: - 250: 12a04c63 bgtz a0,388 <.L13> - 254: 4722 lw a4,8(sp) - 256: 000007b7 lui a5,0x0 - 25a: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 25e: 8cf9 and s1,s1,a4 - 260: 8526 mv a0,s1 - 262: 00000097 auipc ra,0x0 - 266: 000080e7 jalr ra # 262 <.LVL50+0x12> - -0000026a <.LVL51>: - 26a: 10051f63 bnez a0,388 <.L13> - 26e: 000007b7 lui a5,0x0 - 272: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 276: 8526 mv a0,s1 - 278: 00000097 auipc ra,0x0 - 27c: 000080e7 jalr ra # 278 <.LVL51+0xe> - -00000280 <.LVL52>: - 280: 10a04463 bgtz a0,388 <.L13> - 284: 000007b7 lui a5,0x0 - 288: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 28c: 8522 mv a0,s0 - 28e: 4485 li s1,1 - 290: 00000097 auipc ra,0x0 - 294: 000080e7 jalr ra # 290 <.LVL52+0x10> - -00000298 <.LVL53>: - 298: ed09 bnez a0,2b2 <.L14> - 29a: 000007b7 lui a5,0x0 - 29e: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 2a2: 8522 mv a0,s0 - 2a4: 00000097 auipc ra,0x0 - 2a8: 000080e7 jalr ra # 2a4 <.LVL53+0xc> - -000002ac <.LVL54>: - 2ac: 00a05363 blez a0,2b2 <.L14> - 2b0: 4481 li s1,0 - -000002b2 <.L14>: - 2b2: 0014c513 xor a0,s1,1 - 2b6: 8905 and a0,a0,1 - 2b8: 00000097 auipc ra,0x0 - 2bc: 000080e7 jalr ra # 2b8 <.L14+0x6> - -000002c0 <.LVL55>: - 2c0: 47b2 lw a5,12(sp) - 2c2: 80000437 lui s0,0x80000 - 2c6: 8fe1 and a5,a5,s0 - 2c8: fff44413 not s0,s0 - 2cc: 00a474b3 and s1,s0,a0 - 2d0: 8fc5 or a5,a5,s1 - 2d2: c63e sw a5,12(sp) - 2d4: 4782 lw a5,0(sp) - 2d6: 4485 li s1,1 - 2d8: 8c7d and s0,s0,a5 - 2da: 000007b7 lui a5,0x0 - 2de: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 2e2: 8522 mv a0,s0 - 2e4: 00000097 auipc ra,0x0 - 2e8: 000080e7 jalr ra # 2e4 <.LVL55+0x24> - -000002ec <.LVL57>: - 2ec: ed09 bnez a0,306 <.L15> - 2ee: 000007b7 lui a5,0x0 - 2f2: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 2f6: 8522 mv a0,s0 - 2f8: 00000097 auipc ra,0x0 - 2fc: 000080e7 jalr ra # 2f8 <.LVL57+0xc> - -00000300 <.LVL58>: - 300: 00a05363 blez a0,306 <.L15> - 304: 4481 li s1,0 - -00000306 <.L15>: - 306: 0014c513 xor a0,s1,1 - 30a: 8905 and a0,a0,1 - 30c: 00000097 auipc ra,0x0 - 310: 000080e7 jalr ra # 30c <.L15+0x6> - -00000314 <.LVL59>: - 314: 4782 lw a5,0(sp) - 316: 80000437 lui s0,0x80000 - 31a: 45b2 lw a1,12(sp) - 31c: 8fe1 and a5,a5,s0 - 31e: fff44413 not s0,s0 - 322: 8c69 and s0,s0,a0 - 324: 4512 lw a0,4(sp) - 326: 8c5d or s0,s0,a5 - -00000328 <.LVL60>: - 328: 00000097 auipc ra,0x0 - 32c: 000080e7 jalr ra # 328 <.LVL60> - -00000330 <.LVL61>: - 330: 84aa mv s1,a0 - 332: 4522 lw a0,8(sp) - 334: 85a2 mv a1,s0 - 336: 00000097 auipc ra,0x0 - 33a: 000080e7 jalr ra # 336 <.LVL61+0x6> - -0000033e <.LVL62>: - 33e: 85aa mv a1,a0 - 340: 8526 mv a0,s1 - 342: 00000097 auipc ra,0x0 - 346: 000080e7 jalr ra # 342 <.LVL62+0x4> - -0000034a <.LVL63>: - 34a: 000004b7 lui s1,0x0 - 34e: 0004a583 lw a1,0(s1) # 0 <__divsc3> - 352: 00000097 auipc ra,0x0 - 356: 000080e7 jalr ra # 352 <.LVL63+0x8> - -0000035a <.LVL64>: - 35a: c82a sw a0,16(sp) - -0000035c <.LVL65>: - 35c: 4512 lw a0,4(sp) - -0000035e <.LVL66>: - 35e: 85a2 mv a1,s0 - 360: 00000097 auipc ra,0x0 - 364: 000080e7 jalr ra # 360 <.LVL66+0x2> - -00000368 <.LVL67>: - 368: 45b2 lw a1,12(sp) - 36a: 842a mv s0,a0 - -0000036c <.LVL68>: - 36c: 4522 lw a0,8(sp) - 36e: 00000097 auipc ra,0x0 - 372: 000080e7 jalr ra # 36e <.LVL68+0x2> - -00000376 <.LVL69>: - 376: 85aa mv a1,a0 - 378: 8522 mv a0,s0 - 37a: 00000097 auipc ra,0x0 - 37e: 000080e7 jalr ra # 37a <.LVL69+0x4> - -00000382 <.LVL70>: - 382: 0004a583 lw a1,0(s1) - 386: bd19 j 19c <.L31> - -00000388 <.L13>: - 388: 4792 lw a5,4(sp) - 38a: 0786 sll a5,a5,0x1 - 38c: 8385 srl a5,a5,0x1 - 38e: cc3e sw a5,24(sp) - 390: 000007b7 lui a5,0x0 - 394: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 398: 4562 lw a0,24(sp) - 39a: 84be mv s1,a5 - 39c: 00000097 auipc ra,0x0 - 3a0: 000080e7 jalr ra # 39c <.L13+0x14> - -000003a4 <.LVL72>: - 3a4: e911 bnez a0,3b8 <.L26> - 3a6: 0004a583 lw a1,0(s1) - 3aa: 4562 lw a0,24(sp) - 3ac: 00000097 auipc ra,0x0 - 3b0: 000080e7 jalr ra # 3ac <.LVL72+0x8> - -000003b4 <.LVL73>: - 3b4: 02a04c63 bgtz a0,3ec <.L16> - -000003b8 <.L26>: - 3b8: 47a2 lw a5,8(sp) - 3ba: 00179493 sll s1,a5,0x1 - 3be: 000007b7 lui a5,0x0 - 3c2: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 3c6: 8085 srl s1,s1,0x1 - 3c8: 8526 mv a0,s1 - 3ca: 00000097 auipc ra,0x0 - 3ce: 000080e7 jalr ra # 3ca <.L26+0x12> - -000003d2 <.LVL74>: - 3d2: dc051ae3 bnez a0,1a6 <.L2> - 3d6: 000007b7 lui a5,0x0 - 3da: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 3de: 8526 mv a0,s1 - 3e0: 00000097 auipc ra,0x0 - 3e4: 000080e7 jalr ra # 3e0 <.LVL74+0xe> - -000003e8 <.LVL75>: - 3e8: daa05fe3 blez a0,1a6 <.L2> - -000003ec <.L16>: - 3ec: 000007b7 lui a5,0x0 - 3f0: 0007a483 lw s1,0(a5) # 0 <__divsc3> - 3f4: 8522 mv a0,s0 - 3f6: 85a6 mv a1,s1 - 3f8: 00000097 auipc ra,0x0 - 3fc: 000080e7 jalr ra # 3f8 <.L16+0xc> - -00000400 <.LVL76>: - 400: da0513e3 bnez a0,1a6 <.L2> - 404: 85a6 mv a1,s1 - 406: 8522 mv a0,s0 - 408: 00000097 auipc ra,0x0 - 40c: 000080e7 jalr ra # 408 <.LVL76+0x8> - -00000410 <.LVL77>: - 410: d8a04be3 bgtz a0,1a6 <.L2> - 414: 4782 lw a5,0(sp) - 416: 85a6 mv a1,s1 - 418: 00179413 sll s0,a5,0x1 - 41c: 8005 srl s0,s0,0x1 - 41e: 8522 mv a0,s0 - 420: 00000097 auipc ra,0x0 - 424: 000080e7 jalr ra # 420 <.LVL77+0x10> - -00000428 <.LVL78>: - 428: d6051fe3 bnez a0,1a6 <.L2> - 42c: 85a6 mv a1,s1 - 42e: 8522 mv a0,s0 - 430: 00000097 auipc ra,0x0 - 434: 000080e7 jalr ra # 430 <.LVL78+0x8> - -00000438 <.LVL79>: - 438: d6a047e3 bgtz a0,1a6 <.L2> - 43c: 4562 lw a0,24(sp) - 43e: 85a6 mv a1,s1 - 440: 4405 li s0,1 - 442: 00000097 auipc ra,0x0 - 446: 000080e7 jalr ra # 442 <.LVL79+0xa> - -0000044a <.LVL80>: - 44a: e911 bnez a0,45e <.L18> - 44c: 4562 lw a0,24(sp) - 44e: 85a6 mv a1,s1 - 450: 00000097 auipc ra,0x0 - 454: 000080e7 jalr ra # 450 <.LVL80+0x6> - -00000458 <.LVL81>: - 458: 00a05363 blez a0,45e <.L18> - 45c: 4401 li s0,0 - -0000045e <.L18>: - 45e: 00144513 xor a0,s0,1 - 462: 8905 and a0,a0,1 - 464: 00000097 auipc ra,0x0 - 468: 000080e7 jalr ra # 464 <.L18+0x6> - -0000046c <.LVL82>: - 46c: 4792 lw a5,4(sp) - 46e: 80000437 lui s0,0x80000 - 472: 8fe1 and a5,a5,s0 - 474: fff44413 not s0,s0 - 478: 00a474b3 and s1,s0,a0 - 47c: 8cdd or s1,s1,a5 - -0000047e <.LVL83>: - 47e: 47a2 lw a5,8(sp) - 480: 8fe1 and a5,a5,s0 - 482: c23e sw a5,4(sp) - 484: 000007b7 lui a5,0x0 - 488: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 48c: 4512 lw a0,4(sp) - 48e: 4405 li s0,1 - 490: 00000097 auipc ra,0x0 - 494: 000080e7 jalr ra # 490 <.LVL83+0x12> - -00000498 <.LVL84>: - 498: ed09 bnez a0,4b2 <.L19> - 49a: 000007b7 lui a5,0x0 - 49e: 0007a583 lw a1,0(a5) # 0 <__divsc3> - 4a2: 4512 lw a0,4(sp) - 4a4: 00000097 auipc ra,0x0 - 4a8: 000080e7 jalr ra # 4a4 <.LVL84+0xc> - -000004ac <.LVL85>: - 4ac: 00a05363 blez a0,4b2 <.L19> - 4b0: 4401 li s0,0 - -000004b2 <.L19>: - 4b2: 00144513 xor a0,s0,1 - 4b6: 8905 and a0,a0,1 - 4b8: 00000097 auipc ra,0x0 - 4bc: 000080e7 jalr ra # 4b8 <.L19+0x6> - -000004c0 <.LVL86>: - 4c0: 47a2 lw a5,8(sp) - 4c2: 80000437 lui s0,0x80000 - 4c6: 85a6 mv a1,s1 - 4c8: 8fe1 and a5,a5,s0 - 4ca: fff44413 not s0,s0 - 4ce: 8c69 and s0,s0,a0 - 4d0: 4532 lw a0,12(sp) - 4d2: 8c5d or s0,s0,a5 - -000004d4 <.LVL87>: - 4d4: 00000097 auipc ra,0x0 - 4d8: 000080e7 jalr ra # 4d4 <.LVL87> - -000004dc <.LVL88>: - 4dc: c22a sw a0,4(sp) - 4de: 4502 lw a0,0(sp) - 4e0: 85a2 mv a1,s0 - 4e2: 00000097 auipc ra,0x0 - 4e6: 000080e7 jalr ra # 4e2 <.LVL88+0x6> - -000004ea <.LVL89>: - 4ea: 85aa mv a1,a0 - 4ec: 4512 lw a0,4(sp) - 4ee: 00000097 auipc ra,0x0 - 4f2: 000080e7 jalr ra # 4ee <.LVL89+0x4> - -000004f6 <.LVL90>: - 4f6: 00000593 li a1,0 - 4fa: 00000097 auipc ra,0x0 - 4fe: 000080e7 jalr ra # 4fa <.LVL90+0x4> - -00000502 <.LVL91>: - 502: c82a sw a0,16(sp) - -00000504 <.LVL92>: - 504: 4502 lw a0,0(sp) - -00000506 <.LVL93>: - 506: 85a6 mv a1,s1 - 508: 00000097 auipc ra,0x0 - 50c: 000080e7 jalr ra # 508 <.LVL93+0x2> - -00000510 <.LVL94>: - 510: 84aa mv s1,a0 - -00000512 <.LVL95>: - 512: 4532 lw a0,12(sp) - 514: 85a2 mv a1,s0 - 516: 00000097 auipc ra,0x0 - 51a: 000080e7 jalr ra # 516 <.LVL95+0x4> - -0000051e <.LVL96>: - 51e: 85aa mv a1,a0 - 520: 8526 mv a0,s1 - 522: 00000097 auipc ra,0x0 - 526: 000080e7 jalr ra # 522 <.LVL96+0x4> - -0000052a <.LVL97>: - 52a: 00000593 li a1,0 - 52e: b1bd j 19c <.L31> - -_divdc3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divdc3>: - 0: fa810113 add sp,sp,-88 - 4: c23e sw a5,4(sp) - 6: cabe sw a5,84(sp) - 8: 47e6 lw a5,88(sp) - a: c6a2 sw s0,76(sp) - c: c83a sw a4,16(sp) - e: ce3e sw a5,28(sp) - 10: 47f6 lw a5,92(sp) - 12: 80000437 lui s0,0x80000 - 16: fff44413 not s0,s0 - 1a: c63e sw a5,12(sp) - 1c: 5786 lw a5,96(sp) - 1e: 4732 lw a4,12(sp) - 20: ca32 sw a2,20(sp) - 22: d03e sw a5,32(sp) - 24: 47f2 lw a5,28(sp) - 26: 863a mv a2,a4 - 28: 4712 lw a4,4(sp) - 2a: 0087f333 and t1,a5,s0 - 2e: 5782 lw a5,32(sp) - 30: c4a6 sw s1,72(sp) - 32: c2aa sw a0,68(sp) - 34: 8c7d and s0,s0,a5 - 36: c036 sw a3,0(sp) - 38: 84ae mv s1,a1 - 3a: 86a2 mv a3,s0 - -0000003c <.LVL1>: - 3c: 859a mv a1,t1 - -0000003e <.LVL2>: - 3e: 853a mv a0,a4 - 40: d21a sw t1,36(sp) - 42: c886 sw ra,80(sp) - 44: 00000097 auipc ra,0x0 - 48: 000080e7 jalr ra # 44 <.LVL2+0x6> - -0000004c <.LVL4>: - 4c: 000007b7 lui a5,0x0 - 50: 5312 lw t1,36(sp) - 52: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 56: 0047a683 lw a3,4(a5) - 5a: 3e055d63 bgez a0,454 <.L72> - 5e: 4732 lw a4,12(sp) - 60: 85a2 mv a1,s0 - 62: 853a mv a0,a4 - 64: 00000097 auipc ra,0x0 - 68: 000080e7 jalr ra # 64 <.LVL4+0x18> - -0000006c <.LVL5>: - 6c: 06054b63 bltz a0,e2 <.L4> - 70: 00000437 lui s0,0x0 - 74: 47d2 lw a5,20(sp) - 76: 00042603 lw a2,0(s0) # 0 <__divdc3> - 7a: 00442683 lw a3,4(s0) - 7e: 8526 mv a0,s1 - 80: 85be mv a1,a5 - 82: 00000097 auipc ra,0x0 - 86: 000080e7 jalr ra # 82 <.LVL5+0x16> - -0000008a <.LVL6>: - 8a: 4702 lw a4,0(sp) - 8c: 47c2 lw a5,16(sp) - 8e: 00042603 lw a2,0(s0) - 92: 00442683 lw a3,4(s0) - 96: ca2e sw a1,20(sp) - -00000098 <.LVL7>: - 98: 84aa mv s1,a0 - 9a: 85be mv a1,a5 - 9c: 853a mv a0,a4 - 9e: 00000097 auipc ra,0x0 - a2: 000080e7 jalr ra # 9e <.LVL7+0x6> - -000000a6 <.LVL10>: - a6: 4712 lw a4,4(sp) - a8: 47f2 lw a5,28(sp) - aa: 00042603 lw a2,0(s0) - ae: 00442683 lw a3,4(s0) - b2: c02a sw a0,0(sp) - b4: c82e sw a1,16(sp) - -000000b6 <.LVL11>: - b6: 853a mv a0,a4 - b8: 85be mv a1,a5 - ba: 00000097 auipc ra,0x0 - be: 000080e7 jalr ra # ba <.LVL11+0x4> - -000000c2 <.LVL14>: - c2: 4732 lw a4,12(sp) - c4: 5782 lw a5,32(sp) - c6: 00042603 lw a2,0(s0) - ca: 00442683 lw a3,4(s0) - ce: c22a sw a0,4(sp) - d0: ce2e sw a1,28(sp) - -000000d2 <.LVL15>: - d2: 853a mv a0,a4 - d4: 85be mv a1,a5 - d6: 00000097 auipc ra,0x0 - da: 000080e7 jalr ra # d6 <.LVL15+0x4> - -000000de <.LVL18>: - de: c62a sw a0,12(sp) - e0: d02e sw a1,32(sp) - -000000e2 <.L4>: - e2: 5782 lw a5,32(sp) - e4: 80000437 lui s0,0x80000 - e8: fff44413 not s0,s0 - ec: 8fe1 and a5,a5,s0 - ee: d23e sw a5,36(sp) - f0: 000007b7 lui a5,0x0 - f4: 0007a603 lw a2,0(a5) # 0 <__divdc3> - f8: 0047a683 lw a3,4(a5) - fc: 4732 lw a4,12(sp) - fe: 5792 lw a5,36(sp) - 100: 853a mv a0,a4 - 102: 85be mv a1,a5 - 104: 00000097 auipc ra,0x0 - 108: 000080e7 jalr ra # 104 <.L4+0x22> - -0000010c <.LVL20>: - 10c: 06055c63 bgez a0,184 <.L73> - -00000110 <.L78>: - 110: 00000437 lui s0,0x0 - 114: 47d2 lw a5,20(sp) - 116: 00042603 lw a2,0(s0) # 0 <__divdc3> - 11a: 00442683 lw a3,4(s0) - 11e: 8526 mv a0,s1 - 120: 85be mv a1,a5 - 122: 00000097 auipc ra,0x0 - 126: 000080e7 jalr ra # 122 <.L78+0x12> - -0000012a <.LVL21>: - 12a: 4702 lw a4,0(sp) - 12c: 47c2 lw a5,16(sp) - 12e: 00042603 lw a2,0(s0) - 132: 00442683 lw a3,4(s0) - 136: ca2e sw a1,20(sp) - -00000138 <.LVL22>: - 138: 84aa mv s1,a0 - 13a: 85be mv a1,a5 - 13c: 853a mv a0,a4 - 13e: 00000097 auipc ra,0x0 - 142: 000080e7 jalr ra # 13e <.LVL22+0x6> - -00000146 <.LVL25>: - 146: 4712 lw a4,4(sp) - 148: 47f2 lw a5,28(sp) - 14a: 00042603 lw a2,0(s0) - 14e: 00442683 lw a3,4(s0) - 152: c02a sw a0,0(sp) - -00000154 <.LVL26>: - 154: c82e sw a1,16(sp) - 156: 853a mv a0,a4 - 158: 85be mv a1,a5 - 15a: 00000097 auipc ra,0x0 - 15e: 000080e7 jalr ra # 15a <.LVL26+0x6> - -00000162 <.LVL30>: - 162: 4732 lw a4,12(sp) - 164: 5782 lw a5,32(sp) - 166: 00042603 lw a2,0(s0) - 16a: 00442683 lw a3,4(s0) - 16e: c22a sw a0,4(sp) - -00000170 <.LVL31>: - 170: ce2e sw a1,28(sp) - 172: 853a mv a0,a4 - 174: 85be mv a1,a5 - 176: 00000097 auipc ra,0x0 - 17a: 000080e7 jalr ra # 176 <.LVL31+0x6> - -0000017e <.LVL35>: - 17e: c62a sw a0,12(sp) - -00000180 <.LVL36>: - 180: d02e sw a1,32(sp) - 182: a055 j 226 <.L8> - -00000184 <.L73>: - 184: 47d2 lw a5,20(sp) - 186: 8526 mv a0,s1 - 188: 8fe1 and a5,a5,s0 - 18a: d43e sw a5,40(sp) - 18c: 47c2 lw a5,16(sp) - 18e: 8c7d and s0,s0,a5 - 190: 000007b7 lui a5,0x0 - 194: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 198: 0047a683 lw a3,4(a5) - 19c: 57a2 lw a5,40(sp) - 19e: 85be mv a1,a5 - 1a0: 00000097 auipc ra,0x0 - 1a4: 000080e7 jalr ra # 1a0 <.L73+0x1c> - -000001a8 <.LVL39>: - 1a8: 02055163 bgez a0,1ca <.L9> - 1ac: 000007b7 lui a5,0x0 - 1b0: 4702 lw a4,0(sp) - 1b2: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 1b6: 0047a683 lw a3,4(a5) - 1ba: 853a mv a0,a4 - 1bc: 85a2 mv a1,s0 - 1be: 00000097 auipc ra,0x0 - 1c2: 000080e7 jalr ra # 1be <.LVL39+0x16> - -000001c6 <.LVL40>: - 1c6: 04054063 bltz a0,206 <.L11> - -000001ca <.L9>: - 1ca: 000007b7 lui a5,0x0 - 1ce: 4702 lw a4,0(sp) - 1d0: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 1d4: 0047a683 lw a3,4(a5) - 1d8: 853a mv a0,a4 - 1da: 85a2 mv a1,s0 - 1dc: 00000097 auipc ra,0x0 - 1e0: 000080e7 jalr ra # 1dc <.L9+0x12> - -000001e4 <.LVL41>: - 1e4: 04055163 bgez a0,226 <.L8> - 1e8: 000007b7 lui a5,0x0 - 1ec: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 1f0: 0047a683 lw a3,4(a5) - 1f4: 57a2 lw a5,40(sp) - 1f6: 8526 mv a0,s1 - 1f8: 85be mv a1,a5 - 1fa: 00000097 auipc ra,0x0 - 1fe: 000080e7 jalr ra # 1fa <.LVL41+0x16> - -00000202 <.LVL42>: - 202: 02055263 bgez a0,226 <.L8> - -00000206 <.L11>: - 206: 000007b7 lui a5,0x0 - 20a: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 20e: 0047a683 lw a3,4(a5) - 212: 4732 lw a4,12(sp) - 214: 5792 lw a5,36(sp) - 216: 853a mv a0,a4 - 218: 85be mv a1,a5 - 21a: 00000097 auipc ra,0x0 - 21e: 000080e7 jalr ra # 21a <.L11+0x14> - -00000222 <.LVL43>: - 222: ee0547e3 bltz a0,110 <.L78> - -00000226 <.L8>: - 226: 4732 lw a4,12(sp) - 228: 5782 lw a5,32(sp) - 22a: 863a mv a2,a4 - 22c: 86be mv a3,a5 - 22e: 4712 lw a4,4(sp) - 230: 47f2 lw a5,28(sp) - 232: 853a mv a0,a4 - 234: 85be mv a1,a5 - 236: 00000097 auipc ra,0x0 - 23a: 000080e7 jalr ra # 236 <.L8+0x10> - -0000023e <.LVL45>: - 23e: 4712 lw a4,4(sp) - 240: 47f2 lw a5,28(sp) - 242: 862a mv a2,a0 - 244: 86ae mv a3,a1 - 246: d62a sw a0,44(sp) - 248: 842e mv s0,a1 - -0000024a <.LVL46>: - 24a: 853a mv a0,a4 - -0000024c <.LVL47>: - 24c: 85be mv a1,a5 - 24e: 00000097 auipc ra,0x0 - 252: 000080e7 jalr ra # 24e <.LVL47+0x2> - -00000256 <.LVL48>: - 256: 4732 lw a4,12(sp) - 258: 5782 lw a5,32(sp) - 25a: 863a mv a2,a4 - 25c: 86be mv a3,a5 - 25e: 00000097 auipc ra,0x0 - 262: 000080e7 jalr ra # 25e <.LVL48+0x8> - -00000266 <.LVL49>: - 266: 000007b7 lui a5,0x0 - 26a: 5732 lw a4,44(sp) - 26c: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 270: 0047a683 lw a3,4(a5) - 274: da2e sw a1,52(sp) - -00000276 <.LVL50>: - 276: 00141593 sll a1,s0,0x1 - -0000027a <.LVL51>: - 27a: 0015d793 srl a5,a1,0x1 - 27e: d82a sw a0,48(sp) - -00000280 <.LVL52>: - 280: 85be mv a1,a5 - 282: 853a mv a0,a4 - 284: 00000097 auipc ra,0x0 - 288: 000080e7 jalr ra # 284 <.LVL52+0x4> - -0000028c <.LVL53>: - 28c: 16a05063 blez a0,3ec <.L74> - 290: 5732 lw a4,44(sp) - 292: 47d2 lw a5,20(sp) - 294: 86a2 mv a3,s0 - 296: 863a mv a2,a4 - 298: 85be mv a1,a5 - 29a: 8526 mv a0,s1 - 29c: 00000097 auipc ra,0x0 - 2a0: 000080e7 jalr ra # 29c <.LVL53+0x10> - -000002a4 <.LVL54>: - 2a4: 4702 lw a4,0(sp) - 2a6: 47c2 lw a5,16(sp) - 2a8: 863a mv a2,a4 - 2aa: 86be mv a3,a5 - 2ac: 00000097 auipc ra,0x0 - 2b0: 000080e7 jalr ra # 2ac <.LVL54+0x8> - -000002b4 <.LVL55>: - 2b4: 5642 lw a2,48(sp) - 2b6: 56d2 lw a3,52(sp) - 2b8: 00000097 auipc ra,0x0 - 2bc: 000080e7 jalr ra # 2b8 <.LVL55+0x4> - -000002c0 <.LVL56>: - 2c0: 5732 lw a4,44(sp) - 2c2: 47c2 lw a5,16(sp) - 2c4: d22a sw a0,36(sp) - 2c6: 863a mv a2,a4 - 2c8: 4702 lw a4,0(sp) - 2ca: d42e sw a1,40(sp) - -000002cc <.LVL57>: - 2cc: 86a2 mv a3,s0 - 2ce: 853a mv a0,a4 - -000002d0 <.LVL58>: - 2d0: 85be mv a1,a5 - -000002d2 <.L83>: - 2d2: 00000097 auipc ra,0x0 - 2d6: 000080e7 jalr ra # 2d2 <.L83> - -000002da <.LVL60>: - 2da: 47d2 lw a5,20(sp) - 2dc: 8626 mv a2,s1 - 2de: 86be mv a3,a5 - -000002e0 <.L80>: - 2e0: 00000097 auipc ra,0x0 - 2e4: 000080e7 jalr ra # 2e0 <.L80> - -000002e8 <.LVL62>: - 2e8: 5642 lw a2,48(sp) - 2ea: 56d2 lw a3,52(sp) - 2ec: 00000097 auipc ra,0x0 - 2f0: 000080e7 jalr ra # 2ec <.LVL62+0x4> - -000002f4 <.LVL63>: - 2f4: 5612 lw a2,36(sp) - 2f6: 56a2 lw a3,40(sp) - 2f8: d62a sw a0,44(sp) - 2fa: d82e sw a1,48(sp) - -000002fc <.LVL64>: - 2fc: 8532 mv a0,a2 - -000002fe <.LVL65>: - 2fe: 85b6 mv a1,a3 - -00000300 <.LVL66>: - 300: 00000097 auipc ra,0x0 - 304: 000080e7 jalr ra # 300 <.LVL66> - -00000308 <.LVL67>: - 308: c171 beqz a0,3cc <.L31> - 30a: 5632 lw a2,44(sp) - 30c: 56c2 lw a3,48(sp) - 30e: 8532 mv a0,a2 - 310: 85b6 mv a1,a3 - 312: 00000097 auipc ra,0x0 - 316: 000080e7 jalr ra # 312 <.LVL67+0xa> - -0000031a <.LVL68>: - 31a: c94d beqz a0,3cc <.L31> - 31c: 4712 lw a4,4(sp) - 31e: 47f2 lw a5,28(sp) - 320: 4601 li a2,0 - 322: 4681 li a3,0 - 324: 853a mv a0,a4 - 326: 85be mv a1,a5 - 328: 00000097 auipc ra,0x0 - 32c: 000080e7 jalr ra # 328 <.LVL68+0xe> - -00000330 <.LVL69>: - 330: 40051963 bnez a0,742 <.L34> - 334: 4732 lw a4,12(sp) - 336: 5782 lw a5,32(sp) - 338: 4601 li a2,0 - 33a: 4681 li a3,0 - 33c: 853a mv a0,a4 - 33e: 85be mv a1,a5 - 340: 00000097 auipc ra,0x0 - 344: 000080e7 jalr ra # 340 <.LVL69+0x10> - -00000348 <.LVL70>: - 348: 3e051d63 bnez a0,742 <.L34> - 34c: 47d2 lw a5,20(sp) - 34e: 8626 mv a2,s1 - 350: 8526 mv a0,s1 - 352: 86be mv a3,a5 - 354: 85be mv a1,a5 - 356: 00000097 auipc ra,0x0 - 35a: 000080e7 jalr ra # 356 <.LVL70+0xe> - -0000035e <.LVL71>: - 35e: cd09 beqz a0,378 <.L37> - 360: 4702 lw a4,0(sp) - 362: 47c2 lw a5,16(sp) - 364: 863a mv a2,a4 - 366: 86be mv a3,a5 - 368: 853a mv a0,a4 - 36a: 85be mv a1,a5 - 36c: 00000097 auipc ra,0x0 - 370: 000080e7 jalr ra # 36c <.LVL71+0xe> - -00000374 <.LVL72>: - 374: 3c051763 bnez a0,742 <.L34> - -00000378 <.L37>: - 378: 000007b7 lui a5,0x0 - 37c: 0007a303 lw t1,0(a5) # 0 <__divdc3> - 380: 0047a383 lw t2,4(a5) - 384: 47f2 lw a5,28(sp) - 386: 0007d863 bgez a5,396 <.L39> - 38a: 000007b7 lui a5,0x0 - 38e: 0007a303 lw t1,0(a5) # 0 <__divdc3> - 392: 0047a383 lw t2,4(a5) - -00000396 <.L39>: - 396: 47d2 lw a5,20(sp) - 398: 8626 mv a2,s1 - 39a: 851a mv a0,t1 - 39c: 86be mv a3,a5 - 39e: 859e mv a1,t2 - 3a0: c21a sw t1,4(sp) - -000003a2 <.LVL73>: - 3a2: c41e sw t2,8(sp) - 3a4: 00000097 auipc ra,0x0 - 3a8: 000080e7 jalr ra # 3a4 <.LVL73+0x2> - -000003ac <.LVL74>: - 3ac: 4702 lw a4,0(sp) - 3ae: 47c2 lw a5,16(sp) - 3b0: 4312 lw t1,4(sp) - 3b2: 43a2 lw t2,8(sp) - 3b4: d22a sw a0,36(sp) - -000003b6 <.LVL75>: - 3b6: d42e sw a1,40(sp) - -000003b8 <.LVL76>: - 3b8: 863a mv a2,a4 - 3ba: 86be mv a3,a5 - 3bc: 851a mv a0,t1 - -000003be <.LVL77>: - 3be: 859e mv a1,t2 - -000003c0 <.L82>: - 3c0: 00000097 auipc ra,0x0 - 3c4: 000080e7 jalr ra # 3c0 <.L82> - -000003c8 <.LVL79>: - 3c8: d62a sw a0,44(sp) - 3ca: d82e sw a1,48(sp) - -000003cc <.L31>: - 3cc: 4696 lw a3,68(sp) - 3ce: 5712 lw a4,36(sp) - 3d0: 57a2 lw a5,40(sp) - 3d2: 40c6 lw ra,80(sp) - 3d4: c298 sw a4,0(a3) - 3d6: c2dc sw a5,4(a3) - 3d8: 5732 lw a4,44(sp) - 3da: 57c2 lw a5,48(sp) - 3dc: 4436 lw s0,76(sp) - 3de: c698 sw a4,8(a3) - 3e0: c6dc sw a5,12(a3) - 3e2: 44a6 lw s1,72(sp) - 3e4: 8536 mv a0,a3 - 3e6: 05810113 add sp,sp,88 - 3ea: 8082 ret - -000003ec <.L74>: - 3ec: 5782 lw a5,32(sp) - 3ee: 4732 lw a4,12(sp) - 3f0: 8526 mv a0,s1 - 3f2: 86be mv a3,a5 - 3f4: 47d2 lw a5,20(sp) - 3f6: 863a mv a2,a4 - 3f8: 85be mv a1,a5 - 3fa: 00000097 auipc ra,0x0 - 3fe: 000080e7 jalr ra # 3fa <.L74+0xe> - -00000402 <.LVL82>: - 402: 4712 lw a4,4(sp) - 404: 47f2 lw a5,28(sp) - 406: 863a mv a2,a4 - 408: 86be mv a3,a5 - 40a: 00000097 auipc ra,0x0 - 40e: 000080e7 jalr ra # 40a <.LVL82+0x8> - -00000412 <.LVL83>: - 412: 4702 lw a4,0(sp) - 414: 47c2 lw a5,16(sp) - 416: 863a mv a2,a4 - 418: 86be mv a3,a5 - 41a: 00000097 auipc ra,0x0 - 41e: 000080e7 jalr ra # 41a <.LVL83+0x8> - -00000422 <.LVL84>: - 422: 5642 lw a2,48(sp) - 424: 56d2 lw a3,52(sp) - 426: 00000097 auipc ra,0x0 - 42a: 000080e7 jalr ra # 426 <.LVL84+0x4> - -0000042e <.LVL85>: - 42e: 4732 lw a4,12(sp) - 430: 5782 lw a5,32(sp) - 432: d22a sw a0,36(sp) - 434: 863a mv a2,a4 - 436: 86be mv a3,a5 - 438: 4702 lw a4,0(sp) - 43a: 47c2 lw a5,16(sp) - 43c: d42e sw a1,40(sp) - -0000043e <.LVL86>: - 43e: 853a mv a0,a4 - -00000440 <.LVL87>: - 440: 85be mv a1,a5 - -00000442 <.LVL88>: - 442: 00000097 auipc ra,0x0 - 446: 000080e7 jalr ra # 442 <.LVL88> - -0000044a <.LVL89>: - 44a: 4712 lw a4,4(sp) - 44c: 47f2 lw a5,28(sp) - 44e: 863a mv a2,a4 - 450: 86be mv a3,a5 - 452: b541 j 2d2 <.L83> - -00000454 <.L72>: - 454: 4712 lw a4,4(sp) - 456: 859a mv a1,t1 - 458: 853a mv a0,a4 - 45a: 00000097 auipc ra,0x0 - 45e: 000080e7 jalr ra # 45a <.L72+0x6> - -00000462 <.LVL91>: - 462: 06054b63 bltz a0,4d8 <.L18> - 466: 00000437 lui s0,0x0 - 46a: 47d2 lw a5,20(sp) - 46c: 00042603 lw a2,0(s0) # 0 <__divdc3> - 470: 00442683 lw a3,4(s0) - 474: 8526 mv a0,s1 - 476: 85be mv a1,a5 - 478: 00000097 auipc ra,0x0 - 47c: 000080e7 jalr ra # 478 <.LVL91+0x16> - -00000480 <.LVL92>: - 480: 4702 lw a4,0(sp) - 482: 47c2 lw a5,16(sp) - 484: 00042603 lw a2,0(s0) - 488: 00442683 lw a3,4(s0) - 48c: ca2e sw a1,20(sp) - -0000048e <.LVL93>: - 48e: 84aa mv s1,a0 - 490: 85be mv a1,a5 - 492: 853a mv a0,a4 - 494: 00000097 auipc ra,0x0 - 498: 000080e7 jalr ra # 494 <.LVL93+0x6> - -0000049c <.LVL96>: - 49c: 4712 lw a4,4(sp) - 49e: 47f2 lw a5,28(sp) - 4a0: 00042603 lw a2,0(s0) - 4a4: 00442683 lw a3,4(s0) - 4a8: c02a sw a0,0(sp) - 4aa: c82e sw a1,16(sp) - -000004ac <.LVL97>: - 4ac: 853a mv a0,a4 - 4ae: 85be mv a1,a5 - 4b0: 00000097 auipc ra,0x0 - 4b4: 000080e7 jalr ra # 4b0 <.LVL97+0x4> - -000004b8 <.LVL100>: - 4b8: 4732 lw a4,12(sp) - 4ba: 5782 lw a5,32(sp) - 4bc: 00042603 lw a2,0(s0) - 4c0: 00442683 lw a3,4(s0) - 4c4: c22a sw a0,4(sp) - 4c6: ce2e sw a1,28(sp) - -000004c8 <.LVL101>: - 4c8: 853a mv a0,a4 - 4ca: 85be mv a1,a5 - 4cc: 00000097 auipc ra,0x0 - 4d0: 000080e7 jalr ra # 4cc <.LVL101+0x4> - -000004d4 <.LVL104>: - 4d4: c62a sw a0,12(sp) - 4d6: d02e sw a1,32(sp) - -000004d8 <.L18>: - 4d8: 47f2 lw a5,28(sp) - 4da: 80000437 lui s0,0x80000 - 4de: fff44413 not s0,s0 - 4e2: 8fe1 and a5,a5,s0 - 4e4: d23e sw a5,36(sp) - 4e6: 000007b7 lui a5,0x0 - 4ea: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 4ee: 0047a683 lw a3,4(a5) - 4f2: 4712 lw a4,4(sp) - 4f4: 5792 lw a5,36(sp) - 4f6: 853a mv a0,a4 - 4f8: 85be mv a1,a5 - 4fa: 00000097 auipc ra,0x0 - 4fe: 000080e7 jalr ra # 4fa <.L18+0x22> - -00000502 <.LVL106>: - 502: 06055c63 bgez a0,57a <.L75> - -00000506 <.L79>: - 506: 00000437 lui s0,0x0 - 50a: 47d2 lw a5,20(sp) - 50c: 00042603 lw a2,0(s0) # 0 <__divdc3> - 510: 00442683 lw a3,4(s0) - 514: 8526 mv a0,s1 - 516: 85be mv a1,a5 - 518: 00000097 auipc ra,0x0 - 51c: 000080e7 jalr ra # 518 <.L79+0x12> - -00000520 <.LVL107>: - 520: 4702 lw a4,0(sp) - 522: 47c2 lw a5,16(sp) - 524: 00042603 lw a2,0(s0) - 528: 00442683 lw a3,4(s0) - 52c: ca2e sw a1,20(sp) - -0000052e <.LVL108>: - 52e: 84aa mv s1,a0 - 530: 85be mv a1,a5 - 532: 853a mv a0,a4 - 534: 00000097 auipc ra,0x0 - 538: 000080e7 jalr ra # 534 <.LVL108+0x6> - -0000053c <.LVL111>: - 53c: 4712 lw a4,4(sp) - 53e: 47f2 lw a5,28(sp) - 540: 00042603 lw a2,0(s0) - 544: 00442683 lw a3,4(s0) - 548: c02a sw a0,0(sp) - -0000054a <.LVL112>: - 54a: c82e sw a1,16(sp) - 54c: 853a mv a0,a4 - 54e: 85be mv a1,a5 - 550: 00000097 auipc ra,0x0 - 554: 000080e7 jalr ra # 550 <.LVL112+0x6> - -00000558 <.LVL116>: - 558: 4732 lw a4,12(sp) - 55a: 5782 lw a5,32(sp) - 55c: 00042603 lw a2,0(s0) - 560: 00442683 lw a3,4(s0) - 564: c22a sw a0,4(sp) - -00000566 <.LVL117>: - 566: ce2e sw a1,28(sp) - 568: 853a mv a0,a4 - 56a: 85be mv a1,a5 - 56c: 00000097 auipc ra,0x0 - 570: 000080e7 jalr ra # 56c <.LVL117+0x6> - -00000574 <.LVL121>: - 574: c62a sw a0,12(sp) - -00000576 <.LVL122>: - 576: d02e sw a1,32(sp) - 578: a055 j 61c <.L22> - -0000057a <.L75>: - 57a: 47d2 lw a5,20(sp) - 57c: 8526 mv a0,s1 - 57e: 8fe1 and a5,a5,s0 - 580: d43e sw a5,40(sp) - 582: 47c2 lw a5,16(sp) - 584: 8c7d and s0,s0,a5 - 586: 000007b7 lui a5,0x0 - 58a: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 58e: 0047a683 lw a3,4(a5) - 592: 57a2 lw a5,40(sp) - 594: 85be mv a1,a5 - 596: 00000097 auipc ra,0x0 - 59a: 000080e7 jalr ra # 596 <.L75+0x1c> - -0000059e <.LVL125>: - 59e: 02055163 bgez a0,5c0 <.L23> - 5a2: 000007b7 lui a5,0x0 - 5a6: 4702 lw a4,0(sp) - 5a8: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 5ac: 0047a683 lw a3,4(a5) - 5b0: 853a mv a0,a4 - 5b2: 85a2 mv a1,s0 - 5b4: 00000097 auipc ra,0x0 - 5b8: 000080e7 jalr ra # 5b4 <.LVL125+0x16> - -000005bc <.LVL126>: - 5bc: 04054063 bltz a0,5fc <.L25> - -000005c0 <.L23>: - 5c0: 000007b7 lui a5,0x0 - 5c4: 4702 lw a4,0(sp) - 5c6: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 5ca: 0047a683 lw a3,4(a5) - 5ce: 853a mv a0,a4 - 5d0: 85a2 mv a1,s0 - 5d2: 00000097 auipc ra,0x0 - 5d6: 000080e7 jalr ra # 5d2 <.L23+0x12> - -000005da <.LVL127>: - 5da: 04055163 bgez a0,61c <.L22> - 5de: 000007b7 lui a5,0x0 - 5e2: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 5e6: 0047a683 lw a3,4(a5) - 5ea: 57a2 lw a5,40(sp) - 5ec: 8526 mv a0,s1 - 5ee: 85be mv a1,a5 - 5f0: 00000097 auipc ra,0x0 - 5f4: 000080e7 jalr ra # 5f0 <.LVL127+0x16> - -000005f8 <.LVL128>: - 5f8: 02055263 bgez a0,61c <.L22> - -000005fc <.L25>: - 5fc: 000007b7 lui a5,0x0 - 600: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 604: 0047a683 lw a3,4(a5) - 608: 4712 lw a4,4(sp) - 60a: 5792 lw a5,36(sp) - 60c: 853a mv a0,a4 - 60e: 85be mv a1,a5 - 610: 00000097 auipc ra,0x0 - 614: 000080e7 jalr ra # 610 <.L25+0x14> - -00000618 <.LVL129>: - 618: ee0547e3 bltz a0,506 <.L79> - -0000061c <.L22>: - 61c: 4712 lw a4,4(sp) - 61e: 47f2 lw a5,28(sp) - 620: 863a mv a2,a4 - 622: 86be mv a3,a5 - 624: 4732 lw a4,12(sp) - 626: 5782 lw a5,32(sp) - 628: 853a mv a0,a4 - 62a: 85be mv a1,a5 - 62c: 00000097 auipc ra,0x0 - 630: 000080e7 jalr ra # 62c <.L22+0x10> - -00000634 <.LVL131>: - 634: 4732 lw a4,12(sp) - 636: 5782 lw a5,32(sp) - 638: 862a mv a2,a0 - 63a: 86ae mv a3,a1 - 63c: d62a sw a0,44(sp) - 63e: 842e mv s0,a1 - -00000640 <.LVL132>: - 640: 853a mv a0,a4 - -00000642 <.LVL133>: - 642: 85be mv a1,a5 - 644: 00000097 auipc ra,0x0 - 648: 000080e7 jalr ra # 644 <.LVL133+0x2> - -0000064c <.LVL134>: - 64c: 4712 lw a4,4(sp) - 64e: 47f2 lw a5,28(sp) - 650: 863a mv a2,a4 - 652: 86be mv a3,a5 - 654: 00000097 auipc ra,0x0 - 658: 000080e7 jalr ra # 654 <.LVL134+0x8> - -0000065c <.LVL135>: - 65c: 000007b7 lui a5,0x0 - 660: 5732 lw a4,44(sp) - 662: 0007a603 lw a2,0(a5) # 0 <__divdc3> - 666: 0047a683 lw a3,4(a5) - 66a: da2e sw a1,52(sp) - -0000066c <.LVL136>: - 66c: 00141593 sll a1,s0,0x1 - -00000670 <.LVL137>: - 670: 0015d793 srl a5,a1,0x1 - 674: d82a sw a0,48(sp) - -00000676 <.LVL138>: - 676: 85be mv a1,a5 - 678: 853a mv a0,a4 - 67a: 00000097 auipc ra,0x0 - 67e: 000080e7 jalr ra # 67a <.LVL138+0x4> - -00000682 <.LVL139>: - 682: 04a05d63 blez a0,6dc <.L76> - 686: 5732 lw a4,44(sp) - 688: 47c2 lw a5,16(sp) - 68a: 86a2 mv a3,s0 - 68c: 863a mv a2,a4 - 68e: 4702 lw a4,0(sp) - 690: 85be mv a1,a5 - 692: 853a mv a0,a4 - 694: 00000097 auipc ra,0x0 - 698: 000080e7 jalr ra # 694 <.LVL139+0x12> - -0000069c <.LVL140>: - 69c: 47d2 lw a5,20(sp) - 69e: 8626 mv a2,s1 - 6a0: 86be mv a3,a5 - 6a2: 00000097 auipc ra,0x0 - 6a6: 000080e7 jalr ra # 6a2 <.LVL140+0x6> - -000006aa <.LVL141>: - 6aa: 5642 lw a2,48(sp) - 6ac: 56d2 lw a3,52(sp) - 6ae: 00000097 auipc ra,0x0 - 6b2: 000080e7 jalr ra # 6ae <.LVL141+0x4> - -000006b6 <.LVL142>: - 6b6: 5732 lw a4,44(sp) - 6b8: 47d2 lw a5,20(sp) - 6ba: d22a sw a0,36(sp) - 6bc: d42e sw a1,40(sp) - -000006be <.LVL143>: - 6be: 863a mv a2,a4 - 6c0: 86a2 mv a3,s0 - 6c2: 8526 mv a0,s1 - -000006c4 <.LVL144>: - 6c4: 85be mv a1,a5 - -000006c6 <.L81>: - 6c6: 00000097 auipc ra,0x0 - 6ca: 000080e7 jalr ra # 6c6 <.L81> - -000006ce <.LVL146>: - 6ce: 4702 lw a4,0(sp) - 6d0: 47c2 lw a5,16(sp) - 6d2: 862a mv a2,a0 - 6d4: 86ae mv a3,a1 - 6d6: 853a mv a0,a4 - 6d8: 85be mv a1,a5 - 6da: b119 j 2e0 <.L80> - -000006dc <.L76>: - 6dc: 4712 lw a4,4(sp) - 6de: 47f2 lw a5,28(sp) - 6e0: 863a mv a2,a4 - 6e2: 86be mv a3,a5 - 6e4: 4702 lw a4,0(sp) - 6e6: 47c2 lw a5,16(sp) - 6e8: 853a mv a0,a4 - 6ea: 85be mv a1,a5 - 6ec: 00000097 auipc ra,0x0 - 6f0: 000080e7 jalr ra # 6ec <.L76+0x10> - -000006f4 <.LVL147>: - 6f4: 4732 lw a4,12(sp) - 6f6: 5782 lw a5,32(sp) - 6f8: 863a mv a2,a4 - 6fa: 86be mv a3,a5 - 6fc: 00000097 auipc ra,0x0 - 700: 000080e7 jalr ra # 6fc <.LVL147+0x8> - -00000704 <.LVL148>: - 704: 47d2 lw a5,20(sp) - 706: 8626 mv a2,s1 - 708: 86be mv a3,a5 - 70a: 00000097 auipc ra,0x0 - 70e: 000080e7 jalr ra # 70a <.LVL148+0x6> - -00000712 <.LVL149>: - 712: 5642 lw a2,48(sp) - 714: 56d2 lw a3,52(sp) - 716: 00000097 auipc ra,0x0 - 71a: 000080e7 jalr ra # 716 <.LVL149+0x4> - -0000071e <.LVL150>: - 71e: 47f2 lw a5,28(sp) - 720: 4712 lw a4,4(sp) - 722: d22a sw a0,36(sp) - 724: 86be mv a3,a5 - 726: 47d2 lw a5,20(sp) - 728: 863a mv a2,a4 - 72a: d42e sw a1,40(sp) - -0000072c <.LVL151>: - 72c: 8526 mv a0,s1 - -0000072e <.LVL152>: - 72e: 85be mv a1,a5 - -00000730 <.LVL153>: - 730: 00000097 auipc ra,0x0 - 734: 000080e7 jalr ra # 730 <.LVL153> - -00000738 <.LVL154>: - 738: 4732 lw a4,12(sp) - 73a: 5782 lw a5,32(sp) - 73c: 863a mv a2,a4 - 73e: 86be mv a3,a5 - 740: b759 j 6c6 <.L81> - -00000742 <.L34>: - 742: 47d2 lw a5,20(sp) - 744: 8526 mv a0,s1 - 746: 0786 sll a5,a5,0x1 - 748: 8385 srl a5,a5,0x1 - 74a: de3e sw a5,60(sp) - 74c: 000007b7 lui a5,0x0 - 750: 0007a703 lw a4,0(a5) # 0 <__divdc3> - 754: 0047a783 lw a5,4(a5) - 758: 863a mv a2,a4 - 75a: dc3e sw a5,56(sp) - 75c: 86be mv a3,a5 - 75e: 57f2 lw a5,60(sp) - 760: da3a sw a4,52(sp) - 762: 85be mv a1,a5 - 764: 00000097 auipc ra,0x0 - 768: 000080e7 jalr ra # 764 <.L34+0x22> - -0000076c <.LVL156>: - 76c: ed01 bnez a0,784 <.L67> - 76e: 57f2 lw a5,60(sp) - 770: 5652 lw a2,52(sp) - 772: 56e2 lw a3,56(sp) - 774: 8526 mv a0,s1 - 776: 85be mv a1,a5 - 778: 00000097 auipc ra,0x0 - 77c: 000080e7 jalr ra # 778 <.LVL156+0xc> - -00000780 <.LVL157>: - 780: 04a04463 bgtz a0,7c8 <.L40> - -00000784 <.L67>: - 784: 47c2 lw a5,16(sp) - 786: 00000737 lui a4,0x0 - 78a: 4302 lw t1,0(sp) - 78c: 0786 sll a5,a5,0x1 - 78e: 0017d413 srl s0,a5,0x1 - 792: 00472783 lw a5,4(a4) # 4 <__divdc3+0x4> - 796: 00072703 lw a4,0(a4) - 79a: 851a mv a0,t1 - 79c: 86be mv a3,a5 - 79e: 863a mv a2,a4 - 7a0: 85a2 mv a1,s0 - 7a2: da3a sw a4,52(sp) - 7a4: dc3e sw a5,56(sp) - 7a6: 00000097 auipc ra,0x0 - 7aa: 000080e7 jalr ra # 7a6 <.L67+0x22> - -000007ae <.LVL158>: - 7ae: 20051263 bnez a0,9b2 <.L42> - 7b2: 4302 lw t1,0(sp) - 7b4: 5652 lw a2,52(sp) - 7b6: 56e2 lw a3,56(sp) - 7b8: 851a mv a0,t1 - 7ba: 85a2 mv a1,s0 - 7bc: 00000097 auipc ra,0x0 - 7c0: 000080e7 jalr ra # 7bc <.LVL158+0xe> - -000007c4 <.LVL159>: - 7c4: 1ea05763 blez a0,9b2 <.L42> - -000007c8 <.L40>: - 7c8: 47f2 lw a5,28(sp) - 7ca: 80000437 lui s0,0x80000 - 7ce: fff44413 not s0,s0 - 7d2: 0087f333 and t1,a5,s0 - 7d6: 000007b7 lui a5,0x0 - 7da: 0007a703 lw a4,0(a5) # 0 <__divdc3> - 7de: 0047a783 lw a5,4(a5) - 7e2: 859a mv a1,t1 - 7e4: da3a sw a4,52(sp) - 7e6: 863a mv a2,a4 - 7e8: 4712 lw a4,4(sp) - 7ea: 86be mv a3,a5 - 7ec: dc3e sw a5,56(sp) - 7ee: 853a mv a0,a4 - 7f0: c09a sw t1,64(sp) - 7f2: 00000097 auipc ra,0x0 - 7f6: 000080e7 jalr ra # 7f2 <.L40+0x2a> - -000007fa <.LVL160>: - 7fa: 1a051c63 bnez a0,9b2 <.L42> - 7fe: 4712 lw a4,4(sp) - 800: 4306 lw t1,64(sp) - 802: 5652 lw a2,52(sp) - 804: 56e2 lw a3,56(sp) - 806: 853a mv a0,a4 - 808: 859a mv a1,t1 - 80a: 00000097 auipc ra,0x0 - 80e: 000080e7 jalr ra # 80a <.LVL160+0x10> - -00000812 <.LVL161>: - 812: 1aa04063 bgtz a0,9b2 <.L42> - 816: 5782 lw a5,32(sp) - 818: 4732 lw a4,12(sp) - 81a: 5652 lw a2,52(sp) - 81c: 56e2 lw a3,56(sp) - 81e: 8c7d and s0,s0,a5 - 820: 853a mv a0,a4 - 822: 85a2 mv a1,s0 - 824: 00000097 auipc ra,0x0 - 828: 000080e7 jalr ra # 824 <.LVL161+0x12> - -0000082c <.LVL162>: - 82c: 18051363 bnez a0,9b2 <.L42> - 830: 4732 lw a4,12(sp) - 832: 5652 lw a2,52(sp) - 834: 56e2 lw a3,56(sp) - 836: 853a mv a0,a4 - 838: 85a2 mv a1,s0 - 83a: 00000097 auipc ra,0x0 - 83e: 000080e7 jalr ra # 83a <.LVL162+0xe> - -00000842 <.LVL163>: - 842: 16a04863 bgtz a0,9b2 <.L42> - 846: 57f2 lw a5,60(sp) - 848: 5652 lw a2,52(sp) - 84a: 56e2 lw a3,56(sp) - 84c: 8526 mv a0,s1 - 84e: 85be mv a1,a5 - 850: 4405 li s0,1 - 852: 00000097 auipc ra,0x0 - 856: 000080e7 jalr ra # 852 <.LVL163+0x10> - -0000085a <.LVL164>: - 85a: ed09 bnez a0,874 <.L43> - 85c: 57f2 lw a5,60(sp) - 85e: 5652 lw a2,52(sp) - 860: 56e2 lw a3,56(sp) - 862: 8526 mv a0,s1 - 864: 85be mv a1,a5 - 866: 00000097 auipc ra,0x0 - 86a: 000080e7 jalr ra # 866 <.LVL164+0xc> - -0000086e <.LVL165>: - 86e: 00a05363 blez a0,874 <.L43> - 872: 4401 li s0,0 - -00000874 <.L43>: - 874: 00144513 xor a0,s0,1 - 878: 8905 and a0,a0,1 - 87a: 00000097 auipc ra,0x0 - 87e: 000080e7 jalr ra # 87a <.L43+0x6> - -00000882 <.LVL166>: - 882: 46d2 lw a3,20(sp) - 884: 80000737 lui a4,0x80000 - 888: fff74793 not a5,a4 - 88c: 8dfd and a1,a1,a5 - 88e: 8f75 and a4,a4,a3 - 890: 8f4d or a4,a4,a1 - 892: d23a sw a4,36(sp) - -00000894 <.LVL167>: - 894: 4742 lw a4,16(sp) - 896: 4302 lw t1,0(sp) - 898: 84aa mv s1,a0 - -0000089a <.LVL168>: - 89a: 8ff9 and a5,a5,a4 - 89c: 00000737 lui a4,0x0 - 8a0: 00072683 lw a3,0(a4) # 0 <__divdc3> - 8a4: 00472703 lw a4,4(a4) - 8a8: 851a mv a0,t1 - 8aa: ca36 sw a3,20(sp) - 8ac: 8636 mv a2,a3 - 8ae: 85be mv a1,a5 - 8b0: 86ba mv a3,a4 - 8b2: 4405 li s0,1 - 8b4: cc3a sw a4,24(sp) - 8b6: d43e sw a5,40(sp) - 8b8: 00000097 auipc ra,0x0 - 8bc: 000080e7 jalr ra # 8b8 <.LVL168+0x1e> - -000008c0 <.LVL169>: - 8c0: ed11 bnez a0,8dc <.L44> - 8c2: 4302 lw t1,0(sp) - 8c4: 57a2 lw a5,40(sp) - 8c6: 4652 lw a2,20(sp) - 8c8: 46e2 lw a3,24(sp) - 8ca: 851a mv a0,t1 - 8cc: 85be mv a1,a5 - 8ce: 00000097 auipc ra,0x0 - 8d2: 000080e7 jalr ra # 8ce <.LVL169+0xe> - -000008d6 <.LVL170>: - 8d6: 00a05363 blez a0,8dc <.L44> - 8da: 4401 li s0,0 - -000008dc <.L44>: - 8dc: 00144513 xor a0,s0,1 - 8e0: 8905 and a0,a0,1 - 8e2: 00000097 auipc ra,0x0 - 8e6: 000080e7 jalr ra # 8e2 <.L44+0x6> - -000008ea <.LVL171>: - 8ea: 800007b7 lui a5,0x80000 - 8ee: fff7c713 not a4,a5 - 8f2: 00e5f433 and s0,a1,a4 - 8f6: 4742 lw a4,16(sp) - 8f8: 5292 lw t0,36(sp) - 8fa: 8626 mv a2,s1 - 8fc: 8ff9 and a5,a5,a4 - 8fe: 8c5d or s0,s0,a5 - -00000900 <.LVL172>: - 900: c026 sw s1,0(sp) - 902: 47f2 lw a5,28(sp) - 904: 4492 lw s1,4(sp) - -00000906 <.LVL173>: - 906: 8696 mv a3,t0 - 908: 85be mv a1,a5 - 90a: ca2a sw a0,20(sp) - -0000090c <.LVL174>: - 90c: 8526 mv a0,s1 - 90e: d616 sw t0,44(sp) - -00000910 <.LVL175>: - 910: c83e sw a5,16(sp) - 912: 00000097 auipc ra,0x0 - 916: 000080e7 jalr ra # 912 <.LVL175+0x2> - -0000091a <.LVL176>: - 91a: 43d2 lw t2,20(sp) - 91c: 86a2 mv a3,s0 - 91e: ca22 sw s0,20(sp) - 920: 861e mv a2,t2 - 922: 5402 lw s0,32(sp) - 924: ce1e sw t2,28(sp) - -00000926 <.LVL177>: - 926: 43b2 lw t2,12(sp) - 928: c22a sw a0,4(sp) - 92a: d22e sw a1,36(sp) - -0000092c <.LVL178>: - 92c: 851e mv a0,t2 - 92e: 85a2 mv a1,s0 - 930: 00000097 auipc ra,0x0 - 934: 000080e7 jalr ra # 930 <.LVL178+0x4> - -00000938 <.LVL179>: - 938: 5312 lw t1,36(sp) - 93a: 862a mv a2,a0 - 93c: 4512 lw a0,4(sp) - 93e: 86ae mv a3,a1 - 940: 859a mv a1,t1 - 942: 00000097 auipc ra,0x0 - 946: 000080e7 jalr ra # 942 <.LVL179+0xa> - -0000094a <.LVL180>: - 94a: 00000337 lui t1,0x0 - 94e: 00032603 lw a2,0(t1) # 0 <__divdc3> - 952: 00432683 lw a3,4(t1) - 956: 00000097 auipc ra,0x0 - 95a: 000080e7 jalr ra # 956 <.LVL180+0xc> - -0000095e <.LVL181>: - 95e: 47d2 lw a5,20(sp) - 960: 4772 lw a4,28(sp) - 962: d22a sw a0,36(sp) - 964: 86be mv a3,a5 - 966: 47c2 lw a5,16(sp) - 968: 863a mv a2,a4 - 96a: d42e sw a1,40(sp) - -0000096c <.LVL182>: - 96c: 8526 mv a0,s1 - -0000096e <.LVL183>: - 96e: 85be mv a1,a5 - -00000970 <.LVL184>: - 970: 00000097 auipc ra,0x0 - 974: 000080e7 jalr ra # 970 <.LVL184> - -00000978 <.LVL185>: - 978: 52b2 lw t0,44(sp) - 97a: 43b2 lw t2,12(sp) - 97c: 84ae mv s1,a1 - 97e: 4582 lw a1,0(sp) - 980: 8696 mv a3,t0 - 982: c22a sw a0,4(sp) - 984: 862e mv a2,a1 - 986: 851e mv a0,t2 - 988: 85a2 mv a1,s0 - 98a: 00000097 auipc ra,0x0 - 98e: 000080e7 jalr ra # 98a <.LVL185+0x12> - -00000992 <.LVL186>: - 992: 4792 lw a5,4(sp) - 994: 862a mv a2,a0 - 996: 86ae mv a3,a1 - 998: 853e mv a0,a5 - 99a: 85a6 mv a1,s1 - 99c: 00000097 auipc ra,0x0 - 9a0: 000080e7 jalr ra # 99c <.LVL186+0xa> - -000009a4 <.LVL187>: - 9a4: 00000337 lui t1,0x0 - 9a8: 00032603 lw a2,0(t1) # 0 <__divdc3> - 9ac: 00432683 lw a3,4(t1) - 9b0: bc01 j 3c0 <.L82> - -000009b2 <.L42>: - 9b2: 47f2 lw a5,28(sp) - 9b4: 0786 sll a5,a5,0x1 - 9b6: 8385 srl a5,a5,0x1 - 9b8: c0be sw a5,64(sp) - 9ba: 000007b7 lui a5,0x0 - 9be: 0007a703 lw a4,0(a5) # 0 <__divdc3> - 9c2: 0047a783 lw a5,4(a5) - 9c6: da3a sw a4,52(sp) - 9c8: dc3e sw a5,56(sp) - 9ca: 863a mv a2,a4 - 9cc: 86be mv a3,a5 - 9ce: 4712 lw a4,4(sp) - 9d0: 4786 lw a5,64(sp) - 9d2: 853a mv a0,a4 - 9d4: 85be mv a1,a5 - 9d6: 00000097 auipc ra,0x0 - 9da: 000080e7 jalr ra # 9d6 <.L42+0x24> - -000009de <.LVL189>: - 9de: ed09 bnez a0,9f8 <.L68> - 9e0: 4712 lw a4,4(sp) - 9e2: 4786 lw a5,64(sp) - 9e4: 5652 lw a2,52(sp) - 9e6: 56e2 lw a3,56(sp) - 9e8: 853a mv a0,a4 - 9ea: 85be mv a1,a5 - 9ec: 00000097 auipc ra,0x0 - 9f0: 000080e7 jalr ra # 9ec <.LVL189+0xe> - -000009f4 <.LVL190>: - 9f4: 04a04463 bgtz a0,a3c <.L45> - -000009f8 <.L68>: - 9f8: 5782 lw a5,32(sp) - 9fa: 00000737 lui a4,0x0 - 9fe: 4332 lw t1,12(sp) - a00: 0786 sll a5,a5,0x1 - a02: 0017d413 srl s0,a5,0x1 - a06: 00472783 lw a5,4(a4) # 4 <__divdc3+0x4> - a0a: 00072703 lw a4,0(a4) - a0e: 851a mv a0,t1 - a10: 86be mv a3,a5 - a12: 863a mv a2,a4 - a14: 85a2 mv a1,s0 - a16: da3a sw a4,52(sp) - a18: dc3e sw a5,56(sp) - a1a: 00000097 auipc ra,0x0 - a1e: 000080e7 jalr ra # a1a <.L68+0x22> - -00000a22 <.LVL191>: - a22: 9a0515e3 bnez a0,3cc <.L31> - a26: 4332 lw t1,12(sp) - a28: 5652 lw a2,52(sp) - a2a: 56e2 lw a3,56(sp) - a2c: 851a mv a0,t1 - a2e: 85a2 mv a1,s0 - a30: 00000097 auipc ra,0x0 - a34: 000080e7 jalr ra # a30 <.LVL191+0xe> - -00000a38 <.LVL192>: - a38: 98a05ae3 blez a0,3cc <.L31> - -00000a3c <.L45>: - a3c: 000007b7 lui a5,0x0 - a40: 0007a703 lw a4,0(a5) # 0 <__divdc3> - a44: 0047a783 lw a5,4(a5) - a48: 8526 mv a0,s1 - a4a: 863a mv a2,a4 - a4c: dc3e sw a5,56(sp) - a4e: 86be mv a3,a5 - a50: 57f2 lw a5,60(sp) - a52: da3a sw a4,52(sp) - a54: 85be mv a1,a5 - a56: 00000097 auipc ra,0x0 - a5a: 000080e7 jalr ra # a56 <.L45+0x1a> - -00000a5e <.LVL193>: - a5e: 960517e3 bnez a0,3cc <.L31> - a62: 57f2 lw a5,60(sp) - a64: 5652 lw a2,52(sp) - a66: 56e2 lw a3,56(sp) - a68: 8526 mv a0,s1 - a6a: 85be mv a1,a5 - a6c: 00000097 auipc ra,0x0 - a70: 000080e7 jalr ra # a6c <.LVL193+0xe> - -00000a74 <.LVL194>: - a74: 94a04ce3 bgtz a0,3cc <.L31> - a78: 47c2 lw a5,16(sp) - a7a: 4702 lw a4,0(sp) - a7c: 5652 lw a2,52(sp) - a7e: 00179413 sll s0,a5,0x1 - a82: 56e2 lw a3,56(sp) - a84: 8005 srl s0,s0,0x1 - a86: 853a mv a0,a4 - a88: 85a2 mv a1,s0 - a8a: 00000097 auipc ra,0x0 - a8e: 000080e7 jalr ra # a8a <.LVL194+0x16> - -00000a92 <.LVL195>: - a92: 92051de3 bnez a0,3cc <.L31> - a96: 4702 lw a4,0(sp) - a98: 5652 lw a2,52(sp) - a9a: 56e2 lw a3,56(sp) - a9c: 853a mv a0,a4 - a9e: 85a2 mv a1,s0 - aa0: 00000097 auipc ra,0x0 - aa4: 000080e7 jalr ra # aa0 <.LVL195+0xe> - -00000aa8 <.LVL196>: - aa8: 92a042e3 bgtz a0,3cc <.L31> - aac: 4712 lw a4,4(sp) - aae: 4786 lw a5,64(sp) - ab0: 5652 lw a2,52(sp) - ab2: 56e2 lw a3,56(sp) - ab4: 853a mv a0,a4 - ab6: 85be mv a1,a5 - ab8: 4405 li s0,1 - aba: 00000097 auipc ra,0x0 - abe: 000080e7 jalr ra # aba <.LVL196+0x12> - -00000ac2 <.LVL197>: - ac2: ed11 bnez a0,ade <.L47> - ac4: 4712 lw a4,4(sp) - ac6: 4786 lw a5,64(sp) - ac8: 5652 lw a2,52(sp) - aca: 56e2 lw a3,56(sp) - acc: 853a mv a0,a4 - ace: 85be mv a1,a5 - ad0: 00000097 auipc ra,0x0 - ad4: 000080e7 jalr ra # ad0 <.LVL197+0xe> - -00000ad8 <.LVL198>: - ad8: 00a05363 blez a0,ade <.L47> - adc: 4401 li s0,0 - -00000ade <.L47>: - ade: 00144513 xor a0,s0,1 - ae2: 8905 and a0,a0,1 - ae4: 00000097 auipc ra,0x0 - ae8: 000080e7 jalr ra # ae4 <.L47+0x6> - -00000aec <.LVL199>: - aec: 46f2 lw a3,28(sp) - aee: 80000737 lui a4,0x80000 - af2: fff74793 not a5,a4 - af6: 8dfd and a1,a1,a5 - af8: 8f75 and a4,a4,a3 - afa: 8f4d or a4,a4,a1 - afc: ce3a sw a4,28(sp) - -00000afe <.LVL200>: - afe: 5702 lw a4,32(sp) - -00000b00 <.LVL201>: - b00: 4332 lw t1,12(sp) - b02: d22a sw a0,36(sp) - -00000b04 <.LVL202>: - b04: 8ff9 and a5,a5,a4 - b06: 00000737 lui a4,0x0 - b0a: 00072683 lw a3,0(a4) # 0 <__divdc3> - b0e: 00472703 lw a4,4(a4) - b12: 851a mv a0,t1 - b14: c236 sw a3,4(sp) - b16: 8636 mv a2,a3 - b18: 85be mv a1,a5 - b1a: 86ba mv a3,a4 - b1c: 4405 li s0,1 - b1e: c43a sw a4,8(sp) - b20: d43e sw a5,40(sp) - b22: 00000097 auipc ra,0x0 - b26: 000080e7 jalr ra # b22 <.LVL202+0x1e> - -00000b2a <.LVL203>: - b2a: ed11 bnez a0,b46 <.L48> - b2c: 4332 lw t1,12(sp) - b2e: 57a2 lw a5,40(sp) - b30: 4612 lw a2,4(sp) - b32: 46a2 lw a3,8(sp) - b34: 851a mv a0,t1 - b36: 85be mv a1,a5 - b38: 00000097 auipc ra,0x0 - b3c: 000080e7 jalr ra # b38 <.LVL203+0xe> - -00000b40 <.LVL204>: - b40: 00a05363 blez a0,b46 <.L48> - b44: 4401 li s0,0 - -00000b46 <.L48>: - b46: 00144513 xor a0,s0,1 - b4a: 8905 and a0,a0,1 - b4c: 00000097 auipc ra,0x0 - b50: 000080e7 jalr ra # b4c <.L48+0x6> - -00000b54 <.LVL205>: - b54: 800007b7 lui a5,0x80000 - b58: fff7c713 not a4,a5 - b5c: 00e5f433 and s0,a1,a4 - b60: 5702 lw a4,32(sp) - b62: 42d2 lw t0,20(sp) - b64: 5312 lw t1,36(sp) - b66: 8ff9 and a5,a5,a4 - b68: 4772 lw a4,28(sp) - b6a: 861a mv a2,t1 - b6c: 8596 mv a1,t0 - b6e: 86ba mv a3,a4 - b70: d42a sw a0,40(sp) - b72: 8526 mv a0,s1 - b74: 8c5d or s0,s0,a5 - -00000b76 <.LVL206>: - b76: d016 sw t0,32(sp) - b78: d81a sw t1,48(sp) - -00000b7a <.LVL207>: - b7a: d63a sw a4,44(sp) - b7c: c226 sw s1,4(sp) - b7e: 00000097 auipc ra,0x0 - b82: 000080e7 jalr ra # b7e <.LVL207+0x4> - -00000b86 <.LVL208>: - b86: 53a2 lw t2,40(sp) - b88: 86a2 mv a3,s0 - b8a: 84a2 mv s1,s0 - -00000b8c <.LVL209>: - b8c: 861e mv a2,t2 - b8e: 4442 lw s0,16(sp) - -00000b90 <.LVL210>: - b90: ce1e sw t2,28(sp) - b92: 4382 lw t2,0(sp) - b94: c62a sw a0,12(sp) - b96: ca2e sw a1,20(sp) - -00000b98 <.LVL211>: - b98: 851e mv a0,t2 - b9a: 85a2 mv a1,s0 - b9c: 00000097 auipc ra,0x0 - ba0: 000080e7 jalr ra # b9c <.LVL211+0x4> - -00000ba4 <.LVL212>: - ba4: 862a mv a2,a0 - ba6: 86ae mv a3,a1 - ba8: 4532 lw a0,12(sp) - baa: 45d2 lw a1,20(sp) - bac: 00000097 auipc ra,0x0 - bb0: 000080e7 jalr ra # bac <.LVL212+0x8> - -00000bb4 <.LVL213>: - bb4: 4601 li a2,0 - bb6: 4681 li a3,0 - bb8: 00000097 auipc ra,0x0 - bbc: 000080e7 jalr ra # bb8 <.LVL213+0x4> - -00000bc0 <.LVL214>: - bc0: 4382 lw t2,0(sp) - bc2: 5732 lw a4,44(sp) - bc4: 5342 lw t1,48(sp) - bc6: d22a sw a0,36(sp) - bc8: 86ba mv a3,a4 - bca: 861a mv a2,t1 - bcc: 851e mv a0,t2 - bce: d42e sw a1,40(sp) - -00000bd0 <.LVL215>: - bd0: 85a2 mv a1,s0 - -00000bd2 <.LVL216>: - bd2: 00000097 auipc ra,0x0 - bd6: 000080e7 jalr ra # bd2 <.LVL216> - -00000bda <.LVL217>: - bda: 47f2 lw a5,28(sp) - bdc: 4312 lw t1,4(sp) - bde: 5282 lw t0,32(sp) - be0: 863e mv a2,a5 - be2: c02a sw a0,0(sp) - -00000be4 <.LVL218>: - be4: 842e mv s0,a1 - be6: 86a6 mv a3,s1 - be8: 851a mv a0,t1 - bea: 8596 mv a1,t0 - bec: 00000097 auipc ra,0x0 - bf0: 000080e7 jalr ra # bec <.LVL218+0x8> - -00000bf4 <.LVL219>: - bf4: 4702 lw a4,0(sp) - bf6: 862a mv a2,a0 - bf8: 86ae mv a3,a1 - bfa: 853a mv a0,a4 - bfc: 85a2 mv a1,s0 - bfe: 00000097 auipc ra,0x0 - c02: 000080e7 jalr ra # bfe <.LVL219+0xa> - -00000c06 <.LVL220>: - c06: 4601 li a2,0 - c08: 4681 li a3,0 - c0a: fb6ff06f j 3c0 <.L82> - -_divxc3.o: file format elf32-littleriscv - - -_divtc3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divtc3>: - 0: 419c lw a5,0(a1) - 2: f2410113 add sp,sp,-220 - 6: cd86 sw ra,216(sp) - 8: c03e sw a5,0(sp) - a: 41dc lw a5,4(a1) - c: cba2 sw s0,212(sp) - e: c9a6 sw s1,208(sp) - 10: c23e sw a5,4(sp) - 12: 459c lw a5,8(a1) - 14: c0aa sw a0,64(sp) - 16: 80000437 lui s0,0x80000 - 1a: c43e sw a5,8(sp) - 1c: 45dc lw a5,12(a1) - 1e: fff44413 not s0,s0 - 22: 190c add a1,sp,176 - 24: da3e sw a5,52(sp) - 26: 421c lw a5,0(a2) - 28: 0188 add a0,sp,192 - 2a: c63e sw a5,12(sp) - 2c: 425c lw a5,4(a2) - 2e: c83e sw a5,16(sp) - 30: 461c lw a5,8(a2) - 32: ca3e sw a5,20(sp) - 34: 465c lw a5,12(a2) - 36: d83e sw a5,48(sp) - 38: 429c lw a5,0(a3) - 3a: cc3e sw a5,24(sp) - 3c: 42dc lw a5,4(a3) - 3e: ce3e sw a5,28(sp) - 40: 469c lw a5,8(a3) - 42: d03e sw a5,32(sp) - 44: 46dc lw a5,12(a3) - 46: dc3e sw a5,56(sp) - 48: 431c lw a5,0(a4) - 4a: d23e sw a5,36(sp) - 4c: 435c lw a5,4(a4) - 4e: d43e sw a5,40(sp) - 50: 471c lw a5,8(a4) - 52: d63e sw a5,44(sp) - 54: 475c lw a5,12(a4) - 56: de3e sw a5,60(sp) - 58: 57e2 lw a5,56(sp) - 5a: 0087f4b3 and s1,a5,s0 - 5e: 57f2 lw a5,60(sp) - 60: c7a6 sw s1,204(sp) - 62: 8c7d and s0,s0,a5 - 64: 47e2 lw a5,24(sp) - 66: df22 sw s0,188(sp) - 68: c1be sw a5,192(sp) - 6a: 47f2 lw a5,28(sp) - 6c: c3be sw a5,196(sp) - 6e: 5782 lw a5,32(sp) - 70: c5be sw a5,200(sp) - 72: 5792 lw a5,36(sp) - 74: d93e sw a5,176(sp) - 76: 57a2 lw a5,40(sp) - 78: db3e sw a5,180(sp) - 7a: 57b2 lw a5,44(sp) - 7c: dd3e sw a5,184(sp) - 7e: 00000097 auipc ra,0x0 - 82: 000080e7 jalr ra # 7e <__divtc3+0x7e> - -00000086 <.LVL2>: - 86: 00000737 lui a4,0x0 - 8a: 00c72703 lw a4,12(a4) # c <__divtc3+0xc> - 8e: 57fd li a5,-1 - 90: 020558e3 bgez a0,8c0 <.L72> - 94: 5692 lw a3,36(sp) - 96: 190c add a1,sp,176 - 98: 0188 add a0,sp,192 - 9a: c1b6 sw a3,192(sp) - 9c: 56a2 lw a3,40(sp) - 9e: c7a2 sw s0,204(sp) - a0: d93e sw a5,176(sp) - a2: c3b6 sw a3,196(sp) - a4: 56b2 lw a3,44(sp) - a6: db3e sw a5,180(sp) - a8: dd3e sw a5,184(sp) - aa: c5b6 sw a3,200(sp) - ac: df3a sw a4,188(sp) - ae: 00000097 auipc ra,0x0 - b2: 000080e7 jalr ra # ae <.LVL2+0x28> - -000000b6 <.LVL3>: - b6: 0e054063 bltz a0,196 <.L4> - ba: 4782 lw a5,0(sp) - bc: 3ffe0437 lui s0,0x3ffe0 - c0: 1110 add a2,sp,160 - c2: d93e sw a5,176(sp) - c4: 4792 lw a5,4(sp) - c6: 190c add a1,sp,176 - c8: 0188 add a0,sp,192 - ca: db3e sw a5,180(sp) - cc: 47a2 lw a5,8(sp) - ce: d102 sw zero,160(sp) - d0: d302 sw zero,164(sp) - d2: dd3e sw a5,184(sp) - d4: 57d2 lw a5,52(sp) - d6: d502 sw zero,168(sp) - d8: d722 sw s0,172(sp) - da: df3e sw a5,188(sp) - dc: 00000097 auipc ra,0x0 - e0: 000080e7 jalr ra # dc <.LVL3+0x26> - -000000e4 <.LVL4>: - e4: 478e lw a5,192(sp) - e6: 1110 add a2,sp,160 - e8: 190c add a1,sp,176 - ea: c03e sw a5,0(sp) - ec: 479e lw a5,196(sp) - ee: 0188 add a0,sp,192 - f0: d102 sw zero,160(sp) - f2: c23e sw a5,4(sp) - f4: 47ae lw a5,200(sp) - f6: d302 sw zero,164(sp) - f8: d502 sw zero,168(sp) - fa: c43e sw a5,8(sp) - fc: 47be lw a5,204(sp) - fe: d722 sw s0,172(sp) - 100: da3e sw a5,52(sp) - -00000102 <.LVL5>: - 102: 47b2 lw a5,12(sp) - -00000104 <.LVL6>: - 104: d93e sw a5,176(sp) - 106: 47c2 lw a5,16(sp) - 108: db3e sw a5,180(sp) - 10a: 47d2 lw a5,20(sp) - 10c: dd3e sw a5,184(sp) - 10e: 57c2 lw a5,48(sp) - 110: df3e sw a5,188(sp) - 112: 00000097 auipc ra,0x0 - 116: 000080e7 jalr ra # 112 <.LVL6+0xe> - -0000011a <.LVL7>: - 11a: 478e lw a5,192(sp) - 11c: 1110 add a2,sp,160 - 11e: 190c add a1,sp,176 - 120: c63e sw a5,12(sp) - 122: 479e lw a5,196(sp) - 124: 0188 add a0,sp,192 - 126: d102 sw zero,160(sp) - 128: c83e sw a5,16(sp) - 12a: 47ae lw a5,200(sp) - 12c: d302 sw zero,164(sp) - 12e: d502 sw zero,168(sp) - 130: ca3e sw a5,20(sp) - 132: 47be lw a5,204(sp) - 134: d722 sw s0,172(sp) - 136: d83e sw a5,48(sp) - -00000138 <.LVL8>: - 138: 47e2 lw a5,24(sp) - -0000013a <.LVL9>: - 13a: d93e sw a5,176(sp) - 13c: 47f2 lw a5,28(sp) - 13e: db3e sw a5,180(sp) - 140: 5782 lw a5,32(sp) - 142: dd3e sw a5,184(sp) - 144: 57e2 lw a5,56(sp) - 146: df3e sw a5,188(sp) - 148: 00000097 auipc ra,0x0 - 14c: 000080e7 jalr ra # 148 <.LVL9+0xe> - -00000150 <.LVL10>: - 150: 478e lw a5,192(sp) - 152: 1110 add a2,sp,160 - 154: 190c add a1,sp,176 - 156: cc3e sw a5,24(sp) - 158: 479e lw a5,196(sp) - 15a: 0188 add a0,sp,192 - 15c: d102 sw zero,160(sp) - 15e: ce3e sw a5,28(sp) - 160: 47ae lw a5,200(sp) - 162: d302 sw zero,164(sp) - 164: d502 sw zero,168(sp) - 166: d03e sw a5,32(sp) - 168: 47be lw a5,204(sp) - 16a: d722 sw s0,172(sp) - 16c: dc3e sw a5,56(sp) - -0000016e <.LVL11>: - 16e: 5792 lw a5,36(sp) - -00000170 <.LVL12>: - 170: d93e sw a5,176(sp) - 172: 57a2 lw a5,40(sp) - 174: db3e sw a5,180(sp) - 176: 57b2 lw a5,44(sp) - 178: dd3e sw a5,184(sp) - 17a: 57f2 lw a5,60(sp) - 17c: df3e sw a5,188(sp) - 17e: 00000097 auipc ra,0x0 - 182: 000080e7 jalr ra # 17e <.LVL12+0xe> - -00000186 <.LVL13>: - 186: 478e lw a5,192(sp) - 188: d23e sw a5,36(sp) - 18a: 479e lw a5,196(sp) - 18c: d43e sw a5,40(sp) - 18e: 47ae lw a5,200(sp) - 190: d63e sw a5,44(sp) - 192: 47be lw a5,204(sp) - 194: de3e sw a5,60(sp) - -00000196 <.L4>: - 196: 57f2 lw a5,60(sp) - 198: 80000437 lui s0,0x80000 - 19c: fff44413 not s0,s0 - 1a0: 8fe1 and a5,a5,s0 - 1a2: c2be sw a5,68(sp) - 1a4: 5792 lw a5,36(sp) - 1a6: 190c add a1,sp,176 - 1a8: 0188 add a0,sp,192 - 1aa: c1be sw a5,192(sp) - 1ac: 57a2 lw a5,40(sp) - 1ae: d902 sw zero,176(sp) - 1b0: db02 sw zero,180(sp) - 1b2: c3be sw a5,196(sp) - 1b4: 57b2 lw a5,44(sp) - 1b6: dd02 sw zero,184(sp) - 1b8: c5be sw a5,200(sp) - 1ba: 4796 lw a5,68(sp) - 1bc: c7be sw a5,204(sp) - 1be: 3f8f07b7 lui a5,0x3f8f0 - 1c2: df3e sw a5,188(sp) - 1c4: 00000097 auipc ra,0x0 - 1c8: 000080e7 jalr ra # 1c4 <.L4+0x2e> - -000001cc <.LVL15>: - 1cc: 0e055163 bgez a0,2ae <.L73> - -000001d0 <.L78>: - 1d0: 4782 lw a5,0(sp) - 1d2: 406f0437 lui s0,0x406f0 - 1d6: 1110 add a2,sp,160 - 1d8: d93e sw a5,176(sp) - 1da: 4792 lw a5,4(sp) - 1dc: 190c add a1,sp,176 - 1de: 0188 add a0,sp,192 - 1e0: db3e sw a5,180(sp) - 1e2: 47a2 lw a5,8(sp) - 1e4: d102 sw zero,160(sp) - 1e6: d302 sw zero,164(sp) - 1e8: dd3e sw a5,184(sp) - 1ea: 57d2 lw a5,52(sp) - 1ec: d502 sw zero,168(sp) - 1ee: d722 sw s0,172(sp) - 1f0: df3e sw a5,188(sp) - 1f2: 00000097 auipc ra,0x0 - 1f6: 000080e7 jalr ra # 1f2 <.L78+0x22> - -000001fa <.LVL16>: - 1fa: 478e lw a5,192(sp) - 1fc: 1110 add a2,sp,160 - 1fe: 190c add a1,sp,176 - 200: c03e sw a5,0(sp) - -00000202 <.LVL17>: - 202: 479e lw a5,196(sp) - 204: 0188 add a0,sp,192 - 206: d102 sw zero,160(sp) - 208: c23e sw a5,4(sp) - 20a: 47ae lw a5,200(sp) - 20c: d302 sw zero,164(sp) - 20e: d502 sw zero,168(sp) - 210: c43e sw a5,8(sp) - 212: 47be lw a5,204(sp) - 214: d722 sw s0,172(sp) - 216: da3e sw a5,52(sp) - -00000218 <.LVL18>: - 218: 47b2 lw a5,12(sp) - -0000021a <.LVL19>: - 21a: d93e sw a5,176(sp) - 21c: 47c2 lw a5,16(sp) - 21e: db3e sw a5,180(sp) - 220: 47d2 lw a5,20(sp) - 222: dd3e sw a5,184(sp) - 224: 57c2 lw a5,48(sp) - 226: df3e sw a5,188(sp) - 228: 00000097 auipc ra,0x0 - 22c: 000080e7 jalr ra # 228 <.LVL19+0xe> - -00000230 <.LVL20>: - 230: 478e lw a5,192(sp) - 232: 1110 add a2,sp,160 - 234: 190c add a1,sp,176 - 236: c63e sw a5,12(sp) - -00000238 <.LVL21>: - 238: 479e lw a5,196(sp) - 23a: 0188 add a0,sp,192 - 23c: d102 sw zero,160(sp) - 23e: c83e sw a5,16(sp) - 240: 47ae lw a5,200(sp) - 242: d302 sw zero,164(sp) - 244: d502 sw zero,168(sp) - 246: ca3e sw a5,20(sp) - 248: 47be lw a5,204(sp) - 24a: d722 sw s0,172(sp) - 24c: d83e sw a5,48(sp) - -0000024e <.LVL22>: - 24e: 47e2 lw a5,24(sp) - -00000250 <.LVL23>: - 250: d93e sw a5,176(sp) - 252: 47f2 lw a5,28(sp) - 254: db3e sw a5,180(sp) - 256: 5782 lw a5,32(sp) - 258: dd3e sw a5,184(sp) - 25a: 57e2 lw a5,56(sp) - 25c: df3e sw a5,188(sp) - 25e: 00000097 auipc ra,0x0 - 262: 000080e7 jalr ra # 25e <.LVL23+0xe> - -00000266 <.LVL24>: - 266: 478e lw a5,192(sp) - 268: 1110 add a2,sp,160 - 26a: 190c add a1,sp,176 - 26c: cc3e sw a5,24(sp) - -0000026e <.LVL25>: - 26e: 479e lw a5,196(sp) - 270: 0188 add a0,sp,192 - 272: d102 sw zero,160(sp) - 274: ce3e sw a5,28(sp) - 276: 47ae lw a5,200(sp) - 278: d302 sw zero,164(sp) - 27a: d502 sw zero,168(sp) - 27c: d03e sw a5,32(sp) - 27e: 47be lw a5,204(sp) - 280: d722 sw s0,172(sp) - 282: dc3e sw a5,56(sp) - -00000284 <.LVL26>: - 284: 5792 lw a5,36(sp) - -00000286 <.LVL27>: - 286: d93e sw a5,176(sp) - 288: 57a2 lw a5,40(sp) - 28a: db3e sw a5,180(sp) - 28c: 57b2 lw a5,44(sp) - 28e: dd3e sw a5,184(sp) - 290: 57f2 lw a5,60(sp) - 292: df3e sw a5,188(sp) - 294: 00000097 auipc ra,0x0 - 298: 000080e7 jalr ra # 294 <.LVL27+0xe> - -0000029c <.LVL28>: - 29c: 478e lw a5,192(sp) - 29e: d23e sw a5,36(sp) - -000002a0 <.LVL29>: - 2a0: 479e lw a5,196(sp) - 2a2: d43e sw a5,40(sp) - 2a4: 47ae lw a5,200(sp) - 2a6: d63e sw a5,44(sp) - 2a8: 47be lw a5,204(sp) - 2aa: de3e sw a5,60(sp) - -000002ac <.LVL30>: - 2ac: a0fd j 39a <.L8> - -000002ae <.L73>: - 2ae: 57d2 lw a5,52(sp) - 2b0: 190c add a1,sp,176 - 2b2: 0188 add a0,sp,192 - 2b4: 0087f4b3 and s1,a5,s0 - 2b8: 57c2 lw a5,48(sp) - 2ba: c7a6 sw s1,204(sp) - 2bc: d902 sw zero,176(sp) - 2be: 8c7d and s0,s0,a5 - 2c0: 4782 lw a5,0(sp) - 2c2: db02 sw zero,180(sp) - 2c4: dd02 sw zero,184(sp) - 2c6: c1be sw a5,192(sp) - 2c8: 4792 lw a5,4(sp) - 2ca: c3be sw a5,196(sp) - 2cc: 47a2 lw a5,8(sp) - 2ce: c5be sw a5,200(sp) - 2d0: 67c1 lui a5,0x10 - 2d2: df3e sw a5,188(sp) - 2d4: 00000097 auipc ra,0x0 - 2d8: 000080e7 jalr ra # 2d4 <.L73+0x26> - -000002dc <.LVL32>: - 2dc: 02055a63 bgez a0,310 <.L9> - 2e0: 46b2 lw a3,12(sp) - 2e2: 57fd li a5,-1 - 2e4: 00000737 lui a4,0x0 - 2e8: c1b6 sw a3,192(sp) - 2ea: 46c2 lw a3,16(sp) - 2ec: d93e sw a5,176(sp) - 2ee: db3e sw a5,180(sp) - 2f0: c3b6 sw a3,196(sp) - 2f2: dd3e sw a5,184(sp) - 2f4: 46d2 lw a3,20(sp) - 2f6: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - 2fa: 190c add a1,sp,176 - 2fc: 0188 add a0,sp,192 - 2fe: c5b6 sw a3,200(sp) - 300: c7a2 sw s0,204(sp) - 302: df3e sw a5,188(sp) - 304: 00000097 auipc ra,0x0 - 308: 000080e7 jalr ra # 304 <.LVL32+0x28> - -0000030c <.LVL33>: - 30c: 04054e63 bltz a0,368 <.L11> - -00000310 <.L9>: - 310: 47b2 lw a5,12(sp) - 312: 190c add a1,sp,176 - 314: 0188 add a0,sp,192 - 316: c1be sw a5,192(sp) - 318: 47c2 lw a5,16(sp) - 31a: c7a2 sw s0,204(sp) - 31c: d902 sw zero,176(sp) - 31e: c3be sw a5,196(sp) - 320: 47d2 lw a5,20(sp) - 322: db02 sw zero,180(sp) - 324: dd02 sw zero,184(sp) - 326: c5be sw a5,200(sp) - 328: 67c1 lui a5,0x10 - 32a: df3e sw a5,188(sp) - 32c: 00000097 auipc ra,0x0 - 330: 000080e7 jalr ra # 32c <.L9+0x1c> - -00000334 <.LVL34>: - 334: 06055363 bgez a0,39a <.L8> - 338: 4682 lw a3,0(sp) - 33a: 57fd li a5,-1 - 33c: 00000737 lui a4,0x0 - 340: c1b6 sw a3,192(sp) - 342: 4692 lw a3,4(sp) - 344: d93e sw a5,176(sp) - 346: db3e sw a5,180(sp) - 348: c3b6 sw a3,196(sp) - 34a: dd3e sw a5,184(sp) - 34c: 46a2 lw a3,8(sp) - 34e: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - 352: 190c add a1,sp,176 - 354: 0188 add a0,sp,192 - 356: c5b6 sw a3,200(sp) - 358: c7a6 sw s1,204(sp) - 35a: df3e sw a5,188(sp) - 35c: 00000097 auipc ra,0x0 - 360: 000080e7 jalr ra # 35c <.LVL34+0x28> - -00000364 <.LVL35>: - 364: 02055b63 bgez a0,39a <.L8> - -00000368 <.L11>: - 368: 5692 lw a3,36(sp) - 36a: 57fd li a5,-1 - 36c: 00000737 lui a4,0x0 - 370: c1b6 sw a3,192(sp) - 372: 56a2 lw a3,40(sp) - 374: d93e sw a5,176(sp) - 376: db3e sw a5,180(sp) - 378: c3b6 sw a3,196(sp) - 37a: 56b2 lw a3,44(sp) - 37c: dd3e sw a5,184(sp) - 37e: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - 382: c5b6 sw a3,200(sp) - 384: 4696 lw a3,68(sp) - 386: 190c add a1,sp,176 - 388: 0188 add a0,sp,192 - 38a: c7b6 sw a3,204(sp) - 38c: df3e sw a5,188(sp) - 38e: 00000097 auipc ra,0x0 - 392: 000080e7 jalr ra # 38e <.L11+0x26> - -00000396 <.LVL36>: - 396: e2054de3 bltz a0,1d0 <.L78> - -0000039a <.L8>: - 39a: 47e2 lw a5,24(sp) - 39c: 1110 add a2,sp,160 - 39e: 190c add a1,sp,176 - 3a0: d93e sw a5,176(sp) - 3a2: 47f2 lw a5,28(sp) - 3a4: 0188 add a0,sp,192 - 3a6: db3e sw a5,180(sp) - 3a8: 5782 lw a5,32(sp) - 3aa: dd3e sw a5,184(sp) - 3ac: 57e2 lw a5,56(sp) - 3ae: df3e sw a5,188(sp) - 3b0: 5792 lw a5,36(sp) - 3b2: d13e sw a5,160(sp) - 3b4: 57a2 lw a5,40(sp) - 3b6: d33e sw a5,164(sp) - 3b8: 57b2 lw a5,44(sp) - 3ba: d53e sw a5,168(sp) - 3bc: 57f2 lw a5,60(sp) - 3be: d73e sw a5,172(sp) - 3c0: 00000097 auipc ra,0x0 - 3c4: 000080e7 jalr ra # 3c0 <.L8+0x26> - -000003c8 <.LVL38>: - 3c8: 47ae lw a5,200(sp) - 3ca: 448e lw s1,192(sp) - 3cc: 441e lw s0,196(sp) - 3ce: cabe sw a5,84(sp) - 3d0: 47be lw a5,204(sp) - 3d2: 1110 add a2,sp,160 - 3d4: 190c add a1,sp,176 - 3d6: ccbe sw a5,88(sp) - -000003d8 <.LVL39>: - 3d8: 47e2 lw a5,24(sp) - -000003da <.LVL40>: - 3da: 0188 add a0,sp,192 - 3dc: d126 sw s1,160(sp) - 3de: d93e sw a5,176(sp) - 3e0: 47f2 lw a5,28(sp) - 3e2: d322 sw s0,164(sp) - 3e4: db3e sw a5,180(sp) - 3e6: 5782 lw a5,32(sp) - 3e8: dd3e sw a5,184(sp) - 3ea: 57e2 lw a5,56(sp) - 3ec: df3e sw a5,188(sp) - 3ee: 47d6 lw a5,84(sp) - 3f0: d53e sw a5,168(sp) - 3f2: 47e6 lw a5,88(sp) - 3f4: d73e sw a5,172(sp) - 3f6: 00000097 auipc ra,0x0 - 3fa: 000080e7 jalr ra # 3f6 <.LVL40+0x1c> - -000003fe <.LVL41>: - 3fe: 47be lw a5,204(sp) - 400: 460e lw a2,192(sp) - 402: 469e lw a3,196(sp) - 404: d73e sw a5,172(sp) - 406: 5792 lw a5,36(sp) - 408: 472e lw a4,200(sp) - 40a: d132 sw a2,160(sp) - 40c: c93e sw a5,144(sp) - 40e: 57a2 lw a5,40(sp) - 410: 0910 add a2,sp,144 - 412: 110c add a1,sp,160 - 414: cb3e sw a5,148(sp) - 416: 57b2 lw a5,44(sp) - 418: 1908 add a0,sp,176 - 41a: d336 sw a3,164(sp) - 41c: cd3e sw a5,152(sp) - 41e: 57f2 lw a5,60(sp) - 420: d53a sw a4,168(sp) - 422: cf3e sw a5,156(sp) - 424: 00000097 auipc ra,0x0 - 428: 000080e7 jalr ra # 424 <.LVL41+0x26> - -0000042c <.LVL42>: - 42c: 57ca lw a5,176(sp) - 42e: 4756 lw a4,84(sp) - 430: 190c add a1,sp,176 - 432: cebe sw a5,92(sp) - 434: 57da lw a5,180(sp) - 436: 0188 add a0,sp,192 - 438: c1a6 sw s1,192(sp) - 43a: d0be sw a5,96(sp) - 43c: 57ea lw a5,184(sp) - 43e: c3a2 sw s0,196(sp) - 440: c5ba sw a4,200(sp) - 442: d2be sw a5,100(sp) - 444: 57fa lw a5,188(sp) - 446: d902 sw zero,176(sp) - 448: db02 sw zero,180(sp) - 44a: d4be sw a5,104(sp) - -0000044c <.LVL43>: - 44c: 47e6 lw a5,88(sp) - -0000044e <.LVL44>: - 44e: dd02 sw zero,184(sp) - -00000450 <.LVL45>: - 450: 0786 sll a5,a5,0x1 - 452: 8385 srl a5,a5,0x1 - 454: c7be sw a5,204(sp) - 456: 67c1 lui a5,0x10 - 458: df3e sw a5,188(sp) - -0000045a <.LVL46>: - 45a: 00000097 auipc ra,0x0 - 45e: 000080e7 jalr ra # 45a <.LVL46> - -00000462 <.LVL47>: - 462: 4782 lw a5,0(sp) - 464: d93e sw a5,176(sp) - 466: 4792 lw a5,4(sp) - 468: db3e sw a5,180(sp) - 46a: 47a2 lw a5,8(sp) - 46c: dd3e sw a5,184(sp) - 46e: 57d2 lw a5,52(sp) - 470: df3e sw a5,188(sp) - 472: 2ca05763 blez a0,740 <.L74> - 476: 47d6 lw a5,84(sp) - 478: 1110 add a2,sp,160 - 47a: 190c add a1,sp,176 - 47c: d53e sw a5,168(sp) - 47e: 47e6 lw a5,88(sp) - 480: 0188 add a0,sp,192 - 482: d126 sw s1,160(sp) - 484: d73e sw a5,172(sp) - 486: d322 sw s0,164(sp) - 488: 00000097 auipc ra,0x0 - 48c: 000080e7 jalr ra # 488 <.LVL47+0x26> - -00000490 <.LVL48>: - 490: 47be lw a5,204(sp) - 492: 460e lw a2,192(sp) - 494: 469e lw a3,196(sp) - 496: d73e sw a5,172(sp) - 498: 47b2 lw a5,12(sp) - 49a: 472e lw a4,200(sp) - 49c: d132 sw a2,160(sp) - 49e: c93e sw a5,144(sp) - 4a0: 47c2 lw a5,16(sp) - 4a2: 0910 add a2,sp,144 - 4a4: 110c add a1,sp,160 - 4a6: cb3e sw a5,148(sp) - 4a8: 47d2 lw a5,20(sp) - 4aa: 1908 add a0,sp,176 - 4ac: d336 sw a3,164(sp) - 4ae: cd3e sw a5,152(sp) - 4b0: 57c2 lw a5,48(sp) - 4b2: d53a sw a4,168(sp) - 4b4: cf3e sw a5,156(sp) - 4b6: 00000097 auipc ra,0x0 - 4ba: 000080e7 jalr ra # 4b6 <.LVL48+0x26> - -000004be <.LVL49>: - 4be: 57fa lw a5,188(sp) - 4c0: 564a lw a2,176(sp) - 4c2: 56da lw a3,180(sp) - 4c4: cf3e sw a5,156(sp) - 4c6: 47f6 lw a5,92(sp) - 4c8: 576a lw a4,184(sp) - 4ca: c932 sw a2,144(sp) - 4cc: c13e sw a5,128(sp) - 4ce: 5786 lw a5,96(sp) - 4d0: 0110 add a2,sp,128 - 4d2: 090c add a1,sp,144 - 4d4: c33e sw a5,132(sp) - 4d6: 5796 lw a5,100(sp) - 4d8: 1108 add a0,sp,160 - 4da: cb36 sw a3,148(sp) - 4dc: c53e sw a5,136(sp) - 4de: 57a6 lw a5,104(sp) - 4e0: cd3a sw a4,152(sp) - 4e2: c73e sw a5,140(sp) - 4e4: 00000097 auipc ra,0x0 - 4e8: 000080e7 jalr ra # 4e4 <.LVL49+0x26> - -000004ec <.LVL50>: - 4ec: 578a lw a5,160(sp) - 4ee: 1110 add a2,sp,160 - 4f0: 190c add a1,sp,176 - 4f2: c2be sw a5,68(sp) - 4f4: 579a lw a5,164(sp) - 4f6: 0188 add a0,sp,192 - 4f8: d126 sw s1,160(sp) - 4fa: c4be sw a5,72(sp) - 4fc: 57aa lw a5,168(sp) - 4fe: d322 sw s0,164(sp) - 500: c6be sw a5,76(sp) - 502: 57ba lw a5,172(sp) - 504: c8be sw a5,80(sp) - -00000506 <.LVL51>: - 506: 47b2 lw a5,12(sp) - -00000508 <.LVL52>: - 508: d93e sw a5,176(sp) - 50a: 47c2 lw a5,16(sp) - 50c: db3e sw a5,180(sp) - 50e: 47d2 lw a5,20(sp) - 510: dd3e sw a5,184(sp) - 512: 57c2 lw a5,48(sp) - 514: df3e sw a5,188(sp) - 516: 47d6 lw a5,84(sp) - 518: d53e sw a5,168(sp) - -0000051a <.LVL53>: - 51a: 47e6 lw a5,88(sp) - 51c: d73e sw a5,172(sp) - -0000051e <.LVL54>: - 51e: 00000097 auipc ra,0x0 - 522: 000080e7 jalr ra # 51e <.LVL54> - -00000526 <.LVL55>: - 526: 47be lw a5,204(sp) - 528: 460e lw a2,192(sp) - 52a: 469e lw a3,196(sp) - 52c: d73e sw a5,172(sp) - 52e: 4782 lw a5,0(sp) - 530: 472e lw a4,200(sp) - 532: d132 sw a2,160(sp) - 534: c93e sw a5,144(sp) - 536: 4792 lw a5,4(sp) - 538: d336 sw a3,164(sp) - 53a: d53a sw a4,168(sp) - 53c: cb3e sw a5,148(sp) - 53e: 47a2 lw a5,8(sp) - 540: cd3e sw a5,152(sp) - 542: 57d2 lw a5,52(sp) - -00000544 <.L84>: - 544: 0910 add a2,sp,144 - 546: 110c add a1,sp,160 - 548: 1908 add a0,sp,176 - 54a: cf3e sw a5,156(sp) - 54c: 00000097 auipc ra,0x0 - 550: 000080e7 jalr ra # 54c <.L84+0x8> - -00000554 <.LVL57>: - 554: 57fa lw a5,188(sp) - 556: 564a lw a2,176(sp) - 558: 56da lw a3,180(sp) - 55a: cf3e sw a5,156(sp) - 55c: 47f6 lw a5,92(sp) - 55e: 576a lw a4,184(sp) - 560: c932 sw a2,144(sp) - 562: c13e sw a5,128(sp) - 564: 5786 lw a5,96(sp) - 566: 0110 add a2,sp,128 - 568: 090c add a1,sp,144 - 56a: c33e sw a5,132(sp) - 56c: 5796 lw a5,100(sp) - 56e: 1108 add a0,sp,160 - 570: cb36 sw a3,148(sp) - 572: c53e sw a5,136(sp) - 574: 57a6 lw a5,104(sp) - 576: cd3a sw a4,152(sp) - 578: c73e sw a5,140(sp) - 57a: 00000097 auipc ra,0x0 - 57e: 000080e7 jalr ra # 57a <.LVL57+0x26> - -00000582 <.LVL58>: - 582: 578a lw a5,160(sp) - 584: cabe sw a5,84(sp) - 586: 579a lw a5,164(sp) - 588: ccbe sw a5,88(sp) - 58a: 57aa lw a5,168(sp) - 58c: cebe sw a5,92(sp) - 58e: 57ba lw a5,172(sp) - -00000590 <.L80>: - 590: d0be sw a5,96(sp) - -00000592 <.LVL59>: - 592: 4796 lw a5,68(sp) - -00000594 <.LVL60>: - 594: 190c add a1,sp,176 - 596: 0188 add a0,sp,192 - 598: c1be sw a5,192(sp) - 59a: 47a6 lw a5,72(sp) - 59c: c3be sw a5,196(sp) - 59e: 47b6 lw a5,76(sp) - 5a0: c5be sw a5,200(sp) - 5a2: 47c6 lw a5,80(sp) - 5a4: c7be sw a5,204(sp) - 5a6: 4796 lw a5,68(sp) - 5a8: d93e sw a5,176(sp) - 5aa: 47a6 lw a5,72(sp) - 5ac: db3e sw a5,180(sp) - 5ae: 47b6 lw a5,76(sp) - 5b0: dd3e sw a5,184(sp) - 5b2: 47c6 lw a5,80(sp) - 5b4: df3e sw a5,188(sp) - 5b6: 00000097 auipc ra,0x0 - 5ba: 000080e7 jalr ra # 5b6 <.LVL60+0x22> - -000005be <.LVL61>: - 5be: 14050963 beqz a0,710 <.L31> - 5c2: 47d6 lw a5,84(sp) - 5c4: 190c add a1,sp,176 - 5c6: 0188 add a0,sp,192 - 5c8: c1be sw a5,192(sp) - 5ca: 47e6 lw a5,88(sp) - 5cc: c3be sw a5,196(sp) - 5ce: 47f6 lw a5,92(sp) - 5d0: c5be sw a5,200(sp) - 5d2: 5786 lw a5,96(sp) - 5d4: c7be sw a5,204(sp) - 5d6: 47d6 lw a5,84(sp) - 5d8: d93e sw a5,176(sp) - 5da: 47e6 lw a5,88(sp) - 5dc: db3e sw a5,180(sp) - 5de: 47f6 lw a5,92(sp) - 5e0: dd3e sw a5,184(sp) - 5e2: 5786 lw a5,96(sp) - 5e4: df3e sw a5,188(sp) - 5e6: 00000097 auipc ra,0x0 - 5ea: 000080e7 jalr ra # 5e6 <.LVL61+0x28> - -000005ee <.LVL62>: - 5ee: 12050163 beqz a0,710 <.L31> - 5f2: 47e2 lw a5,24(sp) - 5f4: 190c add a1,sp,176 - 5f6: 0188 add a0,sp,192 - 5f8: c1be sw a5,192(sp) - 5fa: 47f2 lw a5,28(sp) - 5fc: d902 sw zero,176(sp) - 5fe: db02 sw zero,180(sp) - 600: c3be sw a5,196(sp) - 602: 5782 lw a5,32(sp) - 604: dd02 sw zero,184(sp) - 606: df02 sw zero,188(sp) - 608: c5be sw a5,200(sp) - 60a: 57e2 lw a5,56(sp) - 60c: c7be sw a5,204(sp) - 60e: 00000097 auipc ra,0x0 - 612: 000080e7 jalr ra # 60e <.LVL62+0x20> - -00000616 <.LVL63>: - 616: 080519e3 bnez a0,ea8 <.L34> - 61a: 5792 lw a5,36(sp) - 61c: 190c add a1,sp,176 - 61e: 0188 add a0,sp,192 - 620: c1be sw a5,192(sp) - 622: 57a2 lw a5,40(sp) - 624: c3be sw a5,196(sp) - 626: 57b2 lw a5,44(sp) - 628: c5be sw a5,200(sp) - 62a: 57f2 lw a5,60(sp) - 62c: c7be sw a5,204(sp) - 62e: 00000097 auipc ra,0x0 - 632: 000080e7 jalr ra # 62e <.LVL63+0x18> - -00000636 <.LVL64>: - 636: 060519e3 bnez a0,ea8 <.L34> - 63a: 4782 lw a5,0(sp) - 63c: 190c add a1,sp,176 - 63e: 0188 add a0,sp,192 - 640: c1be sw a5,192(sp) - 642: 4792 lw a5,4(sp) - 644: c3be sw a5,196(sp) - 646: 47a2 lw a5,8(sp) - 648: c5be sw a5,200(sp) - 64a: 57d2 lw a5,52(sp) - 64c: c7be sw a5,204(sp) - 64e: 4782 lw a5,0(sp) - 650: d93e sw a5,176(sp) - 652: 4792 lw a5,4(sp) - 654: db3e sw a5,180(sp) - 656: 47a2 lw a5,8(sp) - 658: dd3e sw a5,184(sp) - 65a: 57d2 lw a5,52(sp) - 65c: df3e sw a5,188(sp) - 65e: 00000097 auipc ra,0x0 - 662: 000080e7 jalr ra # 65e <.LVL64+0x28> - -00000666 <.LVL65>: - 666: c90d beqz a0,698 <.L37> - 668: 47b2 lw a5,12(sp) - 66a: 190c add a1,sp,176 - 66c: 0188 add a0,sp,192 - 66e: c1be sw a5,192(sp) - 670: 47c2 lw a5,16(sp) - 672: c3be sw a5,196(sp) - 674: 47d2 lw a5,20(sp) - 676: c5be sw a5,200(sp) - 678: 57c2 lw a5,48(sp) - 67a: c7be sw a5,204(sp) - 67c: 47b2 lw a5,12(sp) - 67e: d93e sw a5,176(sp) - 680: 47c2 lw a5,16(sp) - 682: db3e sw a5,180(sp) - 684: 47d2 lw a5,20(sp) - 686: dd3e sw a5,184(sp) - 688: 57c2 lw a5,48(sp) - 68a: df3e sw a5,188(sp) - 68c: 00000097 auipc ra,0x0 - 690: 000080e7 jalr ra # 68c <.LVL65+0x26> - -00000694 <.LVL66>: - 694: 00051ae3 bnez a0,ea8 <.L34> - -00000698 <.L37>: - 698: 57e2 lw a5,56(sp) - 69a: 7fff0437 lui s0,0x7fff0 - 69e: 0007d363 bgez a5,6a4 <.L39> - 6a2: 7441 lui s0,0xffff0 - -000006a4 <.L39>: - 6a4: 4782 lw a5,0(sp) - 6a6: 1110 add a2,sp,160 - 6a8: 190c add a1,sp,176 - 6aa: d13e sw a5,160(sp) - 6ac: 4792 lw a5,4(sp) - 6ae: 0188 add a0,sp,192 - 6b0: d902 sw zero,176(sp) - 6b2: d33e sw a5,164(sp) - 6b4: 47a2 lw a5,8(sp) - 6b6: db02 sw zero,180(sp) - 6b8: dd02 sw zero,184(sp) - 6ba: d53e sw a5,168(sp) - 6bc: 57d2 lw a5,52(sp) - 6be: df22 sw s0,188(sp) - 6c0: d73e sw a5,172(sp) - 6c2: 00000097 auipc ra,0x0 - 6c6: 000080e7 jalr ra # 6c2 <.L39+0x1e> - -000006ca <.LVL67>: - 6ca: 478e lw a5,192(sp) - 6cc: 1110 add a2,sp,160 - 6ce: 190c add a1,sp,176 - 6d0: c2be sw a5,68(sp) - -000006d2 <.LVL68>: - 6d2: 479e lw a5,196(sp) - 6d4: 0188 add a0,sp,192 - 6d6: d902 sw zero,176(sp) - 6d8: c4be sw a5,72(sp) - 6da: 47ae lw a5,200(sp) - 6dc: db02 sw zero,180(sp) - 6de: dd02 sw zero,184(sp) - 6e0: c6be sw a5,76(sp) - 6e2: 47be lw a5,204(sp) - 6e4: df22 sw s0,188(sp) - 6e6: c8be sw a5,80(sp) - -000006e8 <.LVL69>: - 6e8: 47b2 lw a5,12(sp) - -000006ea <.LVL70>: - 6ea: d13e sw a5,160(sp) - 6ec: 47c2 lw a5,16(sp) - 6ee: d33e sw a5,164(sp) - 6f0: 47d2 lw a5,20(sp) - 6f2: d53e sw a5,168(sp) - 6f4: 57c2 lw a5,48(sp) - 6f6: d73e sw a5,172(sp) - 6f8: 00000097 auipc ra,0x0 - 6fc: 000080e7 jalr ra # 6f8 <.LVL70+0xe> - -00000700 <.LVL71>: - 700: 478e lw a5,192(sp) - 702: cabe sw a5,84(sp) - -00000704 <.LVL72>: - 704: 479e lw a5,196(sp) - 706: ccbe sw a5,88(sp) - 708: 47ae lw a5,200(sp) - 70a: cebe sw a5,92(sp) - 70c: 47be lw a5,204(sp) - -0000070e <.L82>: - 70e: d0be sw a5,96(sp) - -00000710 <.L31>: - 710: 4786 lw a5,64(sp) - 712: 4716 lw a4,68(sp) - 714: 40ee lw ra,216(sp) - 716: 445e lw s0,212(sp) - 718: c398 sw a4,0(a5) - 71a: 4726 lw a4,72(sp) - 71c: 44ce lw s1,208(sp) - 71e: 853e mv a0,a5 - 720: c3d8 sw a4,4(a5) - 722: 4736 lw a4,76(sp) - 724: c798 sw a4,8(a5) - 726: 4746 lw a4,80(sp) - 728: c7d8 sw a4,12(a5) - 72a: 4756 lw a4,84(sp) - 72c: cb98 sw a4,16(a5) - 72e: 4766 lw a4,88(sp) - 730: cbd8 sw a4,20(a5) - 732: 4776 lw a4,92(sp) - 734: cf98 sw a4,24(a5) - 736: 5706 lw a4,96(sp) - 738: cfd8 sw a4,28(a5) - 73a: 0dc10113 add sp,sp,220 - -0000073e <.LVL75>: - 73e: 8082 ret - -00000740 <.L74>: - 740: 5792 lw a5,36(sp) - 742: 1110 add a2,sp,160 - 744: 190c add a1,sp,176 - 746: d13e sw a5,160(sp) - 748: 57a2 lw a5,40(sp) - 74a: 0188 add a0,sp,192 - 74c: d33e sw a5,164(sp) - 74e: 57b2 lw a5,44(sp) - 750: d53e sw a5,168(sp) - 752: 57f2 lw a5,60(sp) - 754: d73e sw a5,172(sp) - 756: 00000097 auipc ra,0x0 - 75a: 000080e7 jalr ra # 756 <.L74+0x16> - -0000075e <.LVL77>: - 75e: 47be lw a5,204(sp) - 760: 460e lw a2,192(sp) - 762: 469e lw a3,196(sp) - 764: d73e sw a5,172(sp) - 766: 47e2 lw a5,24(sp) - 768: 472e lw a4,200(sp) - 76a: d132 sw a2,160(sp) - 76c: c93e sw a5,144(sp) - 76e: 47f2 lw a5,28(sp) - 770: 0910 add a2,sp,144 - 772: 110c add a1,sp,160 - 774: cb3e sw a5,148(sp) - 776: 5782 lw a5,32(sp) - 778: 1908 add a0,sp,176 - 77a: d336 sw a3,164(sp) - 77c: cd3e sw a5,152(sp) - 77e: 57e2 lw a5,56(sp) - 780: d53a sw a4,168(sp) - 782: cf3e sw a5,156(sp) - 784: 00000097 auipc ra,0x0 - 788: 000080e7 jalr ra # 784 <.LVL77+0x26> - -0000078c <.LVL78>: - 78c: 57fa lw a5,188(sp) - 78e: 564a lw a2,176(sp) - 790: 56da lw a3,180(sp) - 792: cf3e sw a5,156(sp) - 794: 47b2 lw a5,12(sp) - 796: 576a lw a4,184(sp) - 798: c932 sw a2,144(sp) - 79a: c13e sw a5,128(sp) - 79c: 47c2 lw a5,16(sp) - 79e: 0110 add a2,sp,128 - 7a0: 090c add a1,sp,144 - 7a2: c33e sw a5,132(sp) - 7a4: 47d2 lw a5,20(sp) - 7a6: 1108 add a0,sp,160 - 7a8: cb36 sw a3,148(sp) - 7aa: c53e sw a5,136(sp) - 7ac: 57c2 lw a5,48(sp) - 7ae: cd3a sw a4,152(sp) - 7b0: c73e sw a5,140(sp) - 7b2: 00000097 auipc ra,0x0 - 7b6: 000080e7 jalr ra # 7b2 <.LVL78+0x26> - -000007ba <.LVL79>: - 7ba: 57ba lw a5,172(sp) - 7bc: 560a lw a2,160(sp) - 7be: 569a lw a3,164(sp) - 7c0: c73e sw a5,140(sp) - 7c2: 47f6 lw a5,92(sp) - 7c4: 572a lw a4,168(sp) - 7c6: c132 sw a2,128(sp) - 7c8: d8be sw a5,112(sp) - 7ca: 5786 lw a5,96(sp) - 7cc: 1890 add a2,sp,112 - 7ce: 010c add a1,sp,128 - 7d0: dabe sw a5,116(sp) - 7d2: 5796 lw a5,100(sp) - 7d4: 0908 add a0,sp,144 - 7d6: c336 sw a3,132(sp) - 7d8: dcbe sw a5,120(sp) - 7da: 57a6 lw a5,104(sp) - 7dc: c53a sw a4,136(sp) - 7de: debe sw a5,124(sp) - 7e0: 00000097 auipc ra,0x0 - 7e4: 000080e7 jalr ra # 7e0 <.LVL79+0x26> - -000007e8 <.LVL80>: - 7e8: 47ca lw a5,144(sp) - 7ea: 1110 add a2,sp,160 - 7ec: 190c add a1,sp,176 - 7ee: c2be sw a5,68(sp) - 7f0: 47da lw a5,148(sp) - 7f2: 0188 add a0,sp,192 - 7f4: c4be sw a5,72(sp) - 7f6: 47ea lw a5,152(sp) - 7f8: c6be sw a5,76(sp) - 7fa: 47fa lw a5,156(sp) - 7fc: c8be sw a5,80(sp) - -000007fe <.LVL81>: - 7fe: 47b2 lw a5,12(sp) - -00000800 <.LVL82>: - 800: d93e sw a5,176(sp) - 802: 47c2 lw a5,16(sp) - 804: db3e sw a5,180(sp) - 806: 47d2 lw a5,20(sp) - 808: dd3e sw a5,184(sp) - 80a: 57c2 lw a5,48(sp) - 80c: df3e sw a5,188(sp) - 80e: 5792 lw a5,36(sp) - 810: d13e sw a5,160(sp) - 812: 57a2 lw a5,40(sp) - 814: d33e sw a5,164(sp) - 816: 57b2 lw a5,44(sp) - 818: d53e sw a5,168(sp) - 81a: 57f2 lw a5,60(sp) - 81c: d73e sw a5,172(sp) - 81e: 00000097 auipc ra,0x0 - 822: 000080e7 jalr ra # 81e <.LVL82+0x1e> - -00000826 <.LVL83>: - 826: 47be lw a5,204(sp) - 828: 460e lw a2,192(sp) - 82a: 469e lw a3,196(sp) - 82c: d73e sw a5,172(sp) - 82e: 47e2 lw a5,24(sp) - 830: 472e lw a4,200(sp) - 832: d132 sw a2,160(sp) - 834: c93e sw a5,144(sp) - 836: 47f2 lw a5,28(sp) - 838: 0910 add a2,sp,144 - 83a: 110c add a1,sp,160 - 83c: cb3e sw a5,148(sp) - 83e: 5782 lw a5,32(sp) - 840: 1908 add a0,sp,176 - 842: d336 sw a3,164(sp) - 844: cd3e sw a5,152(sp) - 846: 57e2 lw a5,56(sp) - 848: d53a sw a4,168(sp) - 84a: cf3e sw a5,156(sp) - 84c: 00000097 auipc ra,0x0 - 850: 000080e7 jalr ra # 84c <.LVL83+0x26> - -00000854 <.LVL84>: - 854: 57fa lw a5,188(sp) - 856: 564a lw a2,176(sp) - 858: 56da lw a3,180(sp) - 85a: cf3e sw a5,156(sp) - 85c: 4782 lw a5,0(sp) - 85e: 576a lw a4,184(sp) - 860: c932 sw a2,144(sp) - 862: c13e sw a5,128(sp) - 864: 4792 lw a5,4(sp) - 866: cb36 sw a3,148(sp) - 868: cd3a sw a4,152(sp) - 86a: c33e sw a5,132(sp) - 86c: 47a2 lw a5,8(sp) - 86e: c53e sw a5,136(sp) - 870: 57d2 lw a5,52(sp) - -00000872 <.L81>: - 872: 0110 add a2,sp,128 - 874: 090c add a1,sp,144 - 876: 1108 add a0,sp,160 - 878: c73e sw a5,140(sp) - 87a: 00000097 auipc ra,0x0 - 87e: 000080e7 jalr ra # 87a <.L81+0x8> - -00000882 <.LVL86>: - 882: 57ba lw a5,172(sp) - 884: 560a lw a2,160(sp) - 886: 569a lw a3,164(sp) - 888: c73e sw a5,140(sp) - 88a: 47f6 lw a5,92(sp) - 88c: 572a lw a4,168(sp) - 88e: c132 sw a2,128(sp) - 890: d8be sw a5,112(sp) - 892: 5786 lw a5,96(sp) - 894: 1890 add a2,sp,112 - 896: 010c add a1,sp,128 - 898: dabe sw a5,116(sp) - 89a: 5796 lw a5,100(sp) - 89c: 0908 add a0,sp,144 - 89e: c336 sw a3,132(sp) - 8a0: dcbe sw a5,120(sp) - 8a2: 57a6 lw a5,104(sp) - 8a4: c53a sw a4,136(sp) - 8a6: debe sw a5,124(sp) - 8a8: 00000097 auipc ra,0x0 - 8ac: 000080e7 jalr ra # 8a8 <.LVL86+0x26> - -000008b0 <.LVL87>: - 8b0: 47ca lw a5,144(sp) - 8b2: cabe sw a5,84(sp) - 8b4: 47da lw a5,148(sp) - 8b6: ccbe sw a5,88(sp) - 8b8: 47ea lw a5,152(sp) - 8ba: cebe sw a5,92(sp) - 8bc: 47fa lw a5,156(sp) - 8be: b9c9 j 590 <.L80> - -000008c0 <.L72>: - 8c0: 46e2 lw a3,24(sp) - 8c2: 190c add a1,sp,176 - 8c4: 0188 add a0,sp,192 - 8c6: c1b6 sw a3,192(sp) - 8c8: 46f2 lw a3,28(sp) - 8ca: c7a6 sw s1,204(sp) - 8cc: d93e sw a5,176(sp) - 8ce: c3b6 sw a3,196(sp) - 8d0: 5682 lw a3,32(sp) - 8d2: db3e sw a5,180(sp) - 8d4: dd3e sw a5,184(sp) - 8d6: c5b6 sw a3,200(sp) - 8d8: df3a sw a4,188(sp) - 8da: 00000097 auipc ra,0x0 - 8de: 000080e7 jalr ra # 8da <.L72+0x1a> - -000008e2 <.LVL89>: - 8e2: 0e054063 bltz a0,9c2 <.L18> - 8e6: 4782 lw a5,0(sp) - 8e8: 3ffe0437 lui s0,0x3ffe0 - 8ec: 1110 add a2,sp,160 - 8ee: d93e sw a5,176(sp) - 8f0: 4792 lw a5,4(sp) - 8f2: 190c add a1,sp,176 - 8f4: 0188 add a0,sp,192 - 8f6: db3e sw a5,180(sp) - 8f8: 47a2 lw a5,8(sp) - 8fa: d102 sw zero,160(sp) - 8fc: d302 sw zero,164(sp) - 8fe: dd3e sw a5,184(sp) - 900: 57d2 lw a5,52(sp) - 902: d502 sw zero,168(sp) - 904: d722 sw s0,172(sp) - 906: df3e sw a5,188(sp) - 908: 00000097 auipc ra,0x0 - 90c: 000080e7 jalr ra # 908 <.LVL89+0x26> - -00000910 <.LVL90>: - 910: 478e lw a5,192(sp) - 912: 1110 add a2,sp,160 - 914: 190c add a1,sp,176 - 916: c03e sw a5,0(sp) - 918: 479e lw a5,196(sp) - 91a: 0188 add a0,sp,192 - 91c: d102 sw zero,160(sp) - 91e: c23e sw a5,4(sp) - 920: 47ae lw a5,200(sp) - 922: d302 sw zero,164(sp) - 924: d502 sw zero,168(sp) - 926: c43e sw a5,8(sp) - 928: 47be lw a5,204(sp) - 92a: d722 sw s0,172(sp) - 92c: da3e sw a5,52(sp) - -0000092e <.LVL91>: - 92e: 47b2 lw a5,12(sp) - -00000930 <.LVL92>: - 930: d93e sw a5,176(sp) - 932: 47c2 lw a5,16(sp) - 934: db3e sw a5,180(sp) - 936: 47d2 lw a5,20(sp) - 938: dd3e sw a5,184(sp) - 93a: 57c2 lw a5,48(sp) - 93c: df3e sw a5,188(sp) - 93e: 00000097 auipc ra,0x0 - 942: 000080e7 jalr ra # 93e <.LVL92+0xe> - -00000946 <.LVL93>: - 946: 478e lw a5,192(sp) - 948: 1110 add a2,sp,160 - 94a: 190c add a1,sp,176 - 94c: c63e sw a5,12(sp) - 94e: 479e lw a5,196(sp) - 950: 0188 add a0,sp,192 - 952: d102 sw zero,160(sp) - 954: c83e sw a5,16(sp) - 956: 47ae lw a5,200(sp) - 958: d302 sw zero,164(sp) - 95a: d502 sw zero,168(sp) - 95c: ca3e sw a5,20(sp) - 95e: 47be lw a5,204(sp) - 960: d722 sw s0,172(sp) - 962: d83e sw a5,48(sp) - -00000964 <.LVL94>: - 964: 47e2 lw a5,24(sp) - -00000966 <.LVL95>: - 966: d93e sw a5,176(sp) - 968: 47f2 lw a5,28(sp) - 96a: db3e sw a5,180(sp) - 96c: 5782 lw a5,32(sp) - 96e: dd3e sw a5,184(sp) - 970: 57e2 lw a5,56(sp) - 972: df3e sw a5,188(sp) - 974: 00000097 auipc ra,0x0 - 978: 000080e7 jalr ra # 974 <.LVL95+0xe> - -0000097c <.LVL96>: - 97c: 478e lw a5,192(sp) - 97e: 1110 add a2,sp,160 - 980: 190c add a1,sp,176 - 982: cc3e sw a5,24(sp) - 984: 479e lw a5,196(sp) - 986: 0188 add a0,sp,192 - 988: d102 sw zero,160(sp) - 98a: ce3e sw a5,28(sp) - 98c: 47ae lw a5,200(sp) - 98e: d302 sw zero,164(sp) - 990: d502 sw zero,168(sp) - 992: d03e sw a5,32(sp) - 994: 47be lw a5,204(sp) - 996: d722 sw s0,172(sp) - 998: dc3e sw a5,56(sp) - -0000099a <.LVL97>: - 99a: 5792 lw a5,36(sp) - -0000099c <.LVL98>: - 99c: d93e sw a5,176(sp) - 99e: 57a2 lw a5,40(sp) - 9a0: db3e sw a5,180(sp) - 9a2: 57b2 lw a5,44(sp) - 9a4: dd3e sw a5,184(sp) - 9a6: 57f2 lw a5,60(sp) - 9a8: df3e sw a5,188(sp) - 9aa: 00000097 auipc ra,0x0 - 9ae: 000080e7 jalr ra # 9aa <.LVL98+0xe> - -000009b2 <.LVL99>: - 9b2: 478e lw a5,192(sp) - 9b4: d23e sw a5,36(sp) - 9b6: 479e lw a5,196(sp) - 9b8: d43e sw a5,40(sp) - 9ba: 47ae lw a5,200(sp) - 9bc: d63e sw a5,44(sp) - 9be: 47be lw a5,204(sp) - 9c0: de3e sw a5,60(sp) - -000009c2 <.L18>: - 9c2: 57e2 lw a5,56(sp) - 9c4: 80000437 lui s0,0x80000 - 9c8: fff44413 not s0,s0 - 9cc: 8fe1 and a5,a5,s0 - 9ce: c2be sw a5,68(sp) - 9d0: 47e2 lw a5,24(sp) - 9d2: 190c add a1,sp,176 - 9d4: 0188 add a0,sp,192 - 9d6: c1be sw a5,192(sp) - 9d8: 47f2 lw a5,28(sp) - 9da: d902 sw zero,176(sp) - 9dc: db02 sw zero,180(sp) - 9de: c3be sw a5,196(sp) - 9e0: 5782 lw a5,32(sp) - 9e2: dd02 sw zero,184(sp) - 9e4: c5be sw a5,200(sp) - 9e6: 4796 lw a5,68(sp) - 9e8: c7be sw a5,204(sp) - 9ea: 3f8f07b7 lui a5,0x3f8f0 - 9ee: df3e sw a5,188(sp) - 9f0: 00000097 auipc ra,0x0 - 9f4: 000080e7 jalr ra # 9f0 <.L18+0x2e> - -000009f8 <.LVL101>: - 9f8: 0e055163 bgez a0,ada <.L75> - -000009fc <.L79>: - 9fc: 4782 lw a5,0(sp) - 9fe: 406f0437 lui s0,0x406f0 - a02: 1110 add a2,sp,160 - a04: d93e sw a5,176(sp) - a06: 4792 lw a5,4(sp) - a08: 190c add a1,sp,176 - a0a: 0188 add a0,sp,192 - a0c: db3e sw a5,180(sp) - a0e: 47a2 lw a5,8(sp) - a10: d102 sw zero,160(sp) - a12: d302 sw zero,164(sp) - a14: dd3e sw a5,184(sp) - a16: 57d2 lw a5,52(sp) - a18: d502 sw zero,168(sp) - a1a: d722 sw s0,172(sp) - a1c: df3e sw a5,188(sp) - a1e: 00000097 auipc ra,0x0 - a22: 000080e7 jalr ra # a1e <.L79+0x22> - -00000a26 <.LVL102>: - a26: 478e lw a5,192(sp) - a28: 1110 add a2,sp,160 - a2a: 190c add a1,sp,176 - a2c: c03e sw a5,0(sp) - -00000a2e <.LVL103>: - a2e: 479e lw a5,196(sp) - a30: 0188 add a0,sp,192 - a32: d102 sw zero,160(sp) - a34: c23e sw a5,4(sp) - a36: 47ae lw a5,200(sp) - a38: d302 sw zero,164(sp) - a3a: d502 sw zero,168(sp) - a3c: c43e sw a5,8(sp) - a3e: 47be lw a5,204(sp) - a40: d722 sw s0,172(sp) - a42: da3e sw a5,52(sp) - -00000a44 <.LVL104>: - a44: 47b2 lw a5,12(sp) - -00000a46 <.LVL105>: - a46: d93e sw a5,176(sp) - a48: 47c2 lw a5,16(sp) - a4a: db3e sw a5,180(sp) - a4c: 47d2 lw a5,20(sp) - a4e: dd3e sw a5,184(sp) - a50: 57c2 lw a5,48(sp) - a52: df3e sw a5,188(sp) - a54: 00000097 auipc ra,0x0 - a58: 000080e7 jalr ra # a54 <.LVL105+0xe> - -00000a5c <.LVL106>: - a5c: 478e lw a5,192(sp) - a5e: 1110 add a2,sp,160 - a60: 190c add a1,sp,176 - a62: c63e sw a5,12(sp) - -00000a64 <.LVL107>: - a64: 479e lw a5,196(sp) - a66: 0188 add a0,sp,192 - a68: d102 sw zero,160(sp) - a6a: c83e sw a5,16(sp) - a6c: 47ae lw a5,200(sp) - a6e: d302 sw zero,164(sp) - a70: d502 sw zero,168(sp) - a72: ca3e sw a5,20(sp) - a74: 47be lw a5,204(sp) - a76: d722 sw s0,172(sp) - a78: d83e sw a5,48(sp) - -00000a7a <.LVL108>: - a7a: 47e2 lw a5,24(sp) - -00000a7c <.LVL109>: - a7c: d93e sw a5,176(sp) - a7e: 47f2 lw a5,28(sp) - a80: db3e sw a5,180(sp) - a82: 5782 lw a5,32(sp) - a84: dd3e sw a5,184(sp) - a86: 57e2 lw a5,56(sp) - a88: df3e sw a5,188(sp) - a8a: 00000097 auipc ra,0x0 - a8e: 000080e7 jalr ra # a8a <.LVL109+0xe> - -00000a92 <.LVL110>: - a92: 478e lw a5,192(sp) - a94: 1110 add a2,sp,160 - a96: 190c add a1,sp,176 - a98: cc3e sw a5,24(sp) - -00000a9a <.LVL111>: - a9a: 479e lw a5,196(sp) - a9c: 0188 add a0,sp,192 - a9e: d102 sw zero,160(sp) - aa0: ce3e sw a5,28(sp) - aa2: 47ae lw a5,200(sp) - aa4: d302 sw zero,164(sp) - aa6: d502 sw zero,168(sp) - aa8: d03e sw a5,32(sp) - aaa: 47be lw a5,204(sp) - aac: d722 sw s0,172(sp) - aae: dc3e sw a5,56(sp) - -00000ab0 <.LVL112>: - ab0: 5792 lw a5,36(sp) - -00000ab2 <.LVL113>: - ab2: d93e sw a5,176(sp) - ab4: 57a2 lw a5,40(sp) - ab6: db3e sw a5,180(sp) - ab8: 57b2 lw a5,44(sp) - aba: dd3e sw a5,184(sp) - abc: 57f2 lw a5,60(sp) - abe: df3e sw a5,188(sp) - ac0: 00000097 auipc ra,0x0 - ac4: 000080e7 jalr ra # ac0 <.LVL113+0xe> - -00000ac8 <.LVL114>: - ac8: 478e lw a5,192(sp) - aca: d23e sw a5,36(sp) - -00000acc <.LVL115>: - acc: 479e lw a5,196(sp) - ace: d43e sw a5,40(sp) - ad0: 47ae lw a5,200(sp) - ad2: d63e sw a5,44(sp) - ad4: 47be lw a5,204(sp) - ad6: de3e sw a5,60(sp) - -00000ad8 <.LVL116>: - ad8: a0fd j bc6 <.L22> - -00000ada <.L75>: - ada: 57d2 lw a5,52(sp) - adc: 190c add a1,sp,176 - ade: 0188 add a0,sp,192 - ae0: 0087f4b3 and s1,a5,s0 - ae4: 57c2 lw a5,48(sp) - ae6: c7a6 sw s1,204(sp) - ae8: d902 sw zero,176(sp) - aea: 8c7d and s0,s0,a5 - aec: 4782 lw a5,0(sp) - aee: db02 sw zero,180(sp) - af0: dd02 sw zero,184(sp) - af2: c1be sw a5,192(sp) - af4: 4792 lw a5,4(sp) - af6: c3be sw a5,196(sp) - af8: 47a2 lw a5,8(sp) - afa: c5be sw a5,200(sp) - afc: 67c1 lui a5,0x10 - afe: df3e sw a5,188(sp) - b00: 00000097 auipc ra,0x0 - b04: 000080e7 jalr ra # b00 <.L75+0x26> - -00000b08 <.LVL118>: - b08: 02055a63 bgez a0,b3c <.L23> - b0c: 46b2 lw a3,12(sp) - b0e: 57fd li a5,-1 - b10: 00000737 lui a4,0x0 - b14: c1b6 sw a3,192(sp) - b16: 46c2 lw a3,16(sp) - b18: d93e sw a5,176(sp) - b1a: db3e sw a5,180(sp) - b1c: c3b6 sw a3,196(sp) - b1e: dd3e sw a5,184(sp) - b20: 46d2 lw a3,20(sp) - b22: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - b26: 190c add a1,sp,176 - b28: 0188 add a0,sp,192 - b2a: c5b6 sw a3,200(sp) - b2c: c7a2 sw s0,204(sp) - b2e: df3e sw a5,188(sp) - b30: 00000097 auipc ra,0x0 - b34: 000080e7 jalr ra # b30 <.LVL118+0x28> - -00000b38 <.LVL119>: - b38: 04054e63 bltz a0,b94 <.L25> - -00000b3c <.L23>: - b3c: 47b2 lw a5,12(sp) - b3e: 190c add a1,sp,176 - b40: 0188 add a0,sp,192 - b42: c1be sw a5,192(sp) - b44: 47c2 lw a5,16(sp) - b46: c7a2 sw s0,204(sp) - b48: d902 sw zero,176(sp) - b4a: c3be sw a5,196(sp) - b4c: 47d2 lw a5,20(sp) - b4e: db02 sw zero,180(sp) - b50: dd02 sw zero,184(sp) - b52: c5be sw a5,200(sp) - b54: 67c1 lui a5,0x10 - b56: df3e sw a5,188(sp) - b58: 00000097 auipc ra,0x0 - b5c: 000080e7 jalr ra # b58 <.L23+0x1c> - -00000b60 <.LVL120>: - b60: 06055363 bgez a0,bc6 <.L22> - b64: 4682 lw a3,0(sp) - b66: 57fd li a5,-1 - b68: 00000737 lui a4,0x0 - b6c: c1b6 sw a3,192(sp) - b6e: 4692 lw a3,4(sp) - b70: d93e sw a5,176(sp) - b72: db3e sw a5,180(sp) - b74: c3b6 sw a3,196(sp) - b76: dd3e sw a5,184(sp) - b78: 46a2 lw a3,8(sp) - b7a: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - b7e: 190c add a1,sp,176 - b80: 0188 add a0,sp,192 - b82: c5b6 sw a3,200(sp) - b84: c7a6 sw s1,204(sp) - b86: df3e sw a5,188(sp) - b88: 00000097 auipc ra,0x0 - b8c: 000080e7 jalr ra # b88 <.LVL120+0x28> - -00000b90 <.LVL121>: - b90: 02055b63 bgez a0,bc6 <.L22> - -00000b94 <.L25>: - b94: 46e2 lw a3,24(sp) - b96: 57fd li a5,-1 - b98: 00000737 lui a4,0x0 - b9c: c1b6 sw a3,192(sp) - b9e: 46f2 lw a3,28(sp) - ba0: d93e sw a5,176(sp) - ba2: db3e sw a5,180(sp) - ba4: c3b6 sw a3,196(sp) - ba6: 5682 lw a3,32(sp) - ba8: dd3e sw a5,184(sp) - baa: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - bae: c5b6 sw a3,200(sp) - bb0: 4696 lw a3,68(sp) - bb2: 190c add a1,sp,176 - bb4: 0188 add a0,sp,192 - bb6: c7b6 sw a3,204(sp) - bb8: df3e sw a5,188(sp) - bba: 00000097 auipc ra,0x0 - bbe: 000080e7 jalr ra # bba <.L25+0x26> - -00000bc2 <.LVL122>: - bc2: e2054de3 bltz a0,9fc <.L79> - -00000bc6 <.L22>: - bc6: 5792 lw a5,36(sp) - bc8: 1110 add a2,sp,160 - bca: 190c add a1,sp,176 - bcc: d93e sw a5,176(sp) - bce: 57a2 lw a5,40(sp) - bd0: 0188 add a0,sp,192 - bd2: db3e sw a5,180(sp) - bd4: 57b2 lw a5,44(sp) - bd6: dd3e sw a5,184(sp) - bd8: 57f2 lw a5,60(sp) - bda: df3e sw a5,188(sp) - bdc: 47e2 lw a5,24(sp) - bde: d13e sw a5,160(sp) - be0: 47f2 lw a5,28(sp) - be2: d33e sw a5,164(sp) - be4: 5782 lw a5,32(sp) - be6: d53e sw a5,168(sp) - be8: 57e2 lw a5,56(sp) - bea: d73e sw a5,172(sp) - bec: 00000097 auipc ra,0x0 - bf0: 000080e7 jalr ra # bec <.L22+0x26> - -00000bf4 <.LVL124>: - bf4: 47ae lw a5,200(sp) - bf6: 448e lw s1,192(sp) - bf8: 441e lw s0,196(sp) - bfa: cabe sw a5,84(sp) - bfc: 47be lw a5,204(sp) - bfe: 1110 add a2,sp,160 - c00: 190c add a1,sp,176 - c02: ccbe sw a5,88(sp) - -00000c04 <.LVL125>: - c04: 5792 lw a5,36(sp) - -00000c06 <.LVL126>: - c06: 0188 add a0,sp,192 - c08: d126 sw s1,160(sp) - c0a: d93e sw a5,176(sp) - c0c: 57a2 lw a5,40(sp) - c0e: d322 sw s0,164(sp) - c10: db3e sw a5,180(sp) - c12: 57b2 lw a5,44(sp) - c14: dd3e sw a5,184(sp) - c16: 57f2 lw a5,60(sp) - c18: df3e sw a5,188(sp) - c1a: 47d6 lw a5,84(sp) - c1c: d53e sw a5,168(sp) - c1e: 47e6 lw a5,88(sp) - c20: d73e sw a5,172(sp) - c22: 00000097 auipc ra,0x0 - c26: 000080e7 jalr ra # c22 <.LVL126+0x1c> - -00000c2a <.LVL127>: - c2a: 47be lw a5,204(sp) - c2c: 460e lw a2,192(sp) - c2e: 469e lw a3,196(sp) - c30: d73e sw a5,172(sp) - c32: 47e2 lw a5,24(sp) - c34: 472e lw a4,200(sp) - c36: d132 sw a2,160(sp) - c38: c93e sw a5,144(sp) - c3a: 47f2 lw a5,28(sp) - c3c: 0910 add a2,sp,144 - c3e: 110c add a1,sp,160 - c40: cb3e sw a5,148(sp) - c42: 5782 lw a5,32(sp) - c44: 1908 add a0,sp,176 - c46: d336 sw a3,164(sp) - c48: cd3e sw a5,152(sp) - c4a: 57e2 lw a5,56(sp) - c4c: d53a sw a4,168(sp) - c4e: cf3e sw a5,156(sp) - c50: 00000097 auipc ra,0x0 - c54: 000080e7 jalr ra # c50 <.LVL127+0x26> - -00000c58 <.LVL128>: - c58: 57ca lw a5,176(sp) - c5a: 4756 lw a4,84(sp) - c5c: 190c add a1,sp,176 - c5e: cebe sw a5,92(sp) - c60: 57da lw a5,180(sp) - c62: 0188 add a0,sp,192 - c64: c1a6 sw s1,192(sp) - c66: d0be sw a5,96(sp) - c68: 57ea lw a5,184(sp) - c6a: c3a2 sw s0,196(sp) - c6c: c5ba sw a4,200(sp) - c6e: d2be sw a5,100(sp) - c70: 57fa lw a5,188(sp) - c72: d902 sw zero,176(sp) - c74: db02 sw zero,180(sp) - c76: d4be sw a5,104(sp) - -00000c78 <.LVL129>: - c78: 47e6 lw a5,88(sp) - -00000c7a <.LVL130>: - c7a: dd02 sw zero,184(sp) - -00000c7c <.LVL131>: - c7c: 0786 sll a5,a5,0x1 - c7e: 8385 srl a5,a5,0x1 - c80: c7be sw a5,204(sp) - c82: 67c1 lui a5,0x10 - c84: df3e sw a5,188(sp) - -00000c86 <.LVL132>: - c86: 00000097 auipc ra,0x0 - c8a: 000080e7 jalr ra # c86 <.LVL132> - -00000c8e <.LVL133>: - c8e: 47b2 lw a5,12(sp) - c90: d93e sw a5,176(sp) - c92: 47c2 lw a5,16(sp) - c94: db3e sw a5,180(sp) - c96: 47d2 lw a5,20(sp) - c98: dd3e sw a5,184(sp) - c9a: 57c2 lw a5,48(sp) - c9c: df3e sw a5,188(sp) - c9e: 0ca05b63 blez a0,d74 <.L76> - ca2: 47d6 lw a5,84(sp) - ca4: 1110 add a2,sp,160 - ca6: 190c add a1,sp,176 - ca8: d53e sw a5,168(sp) - caa: 47e6 lw a5,88(sp) - cac: 0188 add a0,sp,192 - cae: d126 sw s1,160(sp) - cb0: d73e sw a5,172(sp) - cb2: d322 sw s0,164(sp) - cb4: 00000097 auipc ra,0x0 - cb8: 000080e7 jalr ra # cb4 <.LVL133+0x26> - -00000cbc <.LVL134>: - cbc: 47be lw a5,204(sp) - cbe: 460e lw a2,192(sp) - cc0: 469e lw a3,196(sp) - cc2: d73e sw a5,172(sp) - cc4: 4782 lw a5,0(sp) - cc6: 472e lw a4,200(sp) - cc8: d132 sw a2,160(sp) - cca: c93e sw a5,144(sp) - ccc: 4792 lw a5,4(sp) - cce: 0910 add a2,sp,144 - cd0: 110c add a1,sp,160 - cd2: cb3e sw a5,148(sp) - cd4: 47a2 lw a5,8(sp) - cd6: 1908 add a0,sp,176 - cd8: d336 sw a3,164(sp) - cda: cd3e sw a5,152(sp) - cdc: 57d2 lw a5,52(sp) - cde: d53a sw a4,168(sp) - ce0: cf3e sw a5,156(sp) - ce2: 00000097 auipc ra,0x0 - ce6: 000080e7 jalr ra # ce2 <.LVL134+0x26> - -00000cea <.LVL135>: - cea: 57fa lw a5,188(sp) - cec: 564a lw a2,176(sp) - cee: 56da lw a3,180(sp) - cf0: cf3e sw a5,156(sp) - cf2: 47f6 lw a5,92(sp) - cf4: 576a lw a4,184(sp) - cf6: c932 sw a2,144(sp) - cf8: c13e sw a5,128(sp) - cfa: 5786 lw a5,96(sp) - cfc: 0110 add a2,sp,128 - cfe: 090c add a1,sp,144 - d00: c33e sw a5,132(sp) - d02: 5796 lw a5,100(sp) - d04: 1108 add a0,sp,160 - d06: cb36 sw a3,148(sp) - d08: c53e sw a5,136(sp) - d0a: 57a6 lw a5,104(sp) - d0c: cd3a sw a4,152(sp) - d0e: c73e sw a5,140(sp) - d10: 00000097 auipc ra,0x0 - d14: 000080e7 jalr ra # d10 <.LVL135+0x26> - -00000d18 <.LVL136>: - d18: 578a lw a5,160(sp) - d1a: 1110 add a2,sp,160 - d1c: 190c add a1,sp,176 - d1e: c2be sw a5,68(sp) - d20: 579a lw a5,164(sp) - d22: 0188 add a0,sp,192 - d24: d126 sw s1,160(sp) - d26: c4be sw a5,72(sp) - d28: 57aa lw a5,168(sp) - d2a: d322 sw s0,164(sp) - d2c: c6be sw a5,76(sp) - d2e: 57ba lw a5,172(sp) - d30: c8be sw a5,80(sp) - -00000d32 <.LVL137>: - d32: 4782 lw a5,0(sp) - -00000d34 <.LVL138>: - d34: d93e sw a5,176(sp) - d36: 4792 lw a5,4(sp) - d38: db3e sw a5,180(sp) - d3a: 47a2 lw a5,8(sp) - d3c: dd3e sw a5,184(sp) - d3e: 57d2 lw a5,52(sp) - d40: df3e sw a5,188(sp) - d42: 47d6 lw a5,84(sp) - d44: d53e sw a5,168(sp) - -00000d46 <.LVL139>: - d46: 47e6 lw a5,88(sp) - d48: d73e sw a5,172(sp) - -00000d4a <.LVL140>: - d4a: 00000097 auipc ra,0x0 - d4e: 000080e7 jalr ra # d4a <.LVL140> - -00000d52 <.LVL141>: - d52: 45b2 lw a1,12(sp) - d54: 460e lw a2,192(sp) - d56: 469e lw a3,196(sp) - d58: d12e sw a1,160(sp) - d5a: 45c2 lw a1,16(sp) - d5c: 472e lw a4,200(sp) - d5e: 47be lw a5,204(sp) - d60: d32e sw a1,164(sp) - d62: 45d2 lw a1,20(sp) - d64: c932 sw a2,144(sp) - d66: cb36 sw a3,148(sp) - d68: d52e sw a1,168(sp) - d6a: 55c2 lw a1,48(sp) - d6c: cd3a sw a4,152(sp) - d6e: d72e sw a1,172(sp) - d70: fd4ff06f j 544 <.L84> - -00000d74 <.L76>: - d74: 47e2 lw a5,24(sp) - d76: 1110 add a2,sp,160 - d78: 190c add a1,sp,176 - d7a: d13e sw a5,160(sp) - d7c: 47f2 lw a5,28(sp) - d7e: 0188 add a0,sp,192 - d80: d33e sw a5,164(sp) - d82: 5782 lw a5,32(sp) - d84: d53e sw a5,168(sp) - d86: 57e2 lw a5,56(sp) - d88: d73e sw a5,172(sp) - d8a: 00000097 auipc ra,0x0 - d8e: 000080e7 jalr ra # d8a <.L76+0x16> - -00000d92 <.LVL143>: - d92: 47be lw a5,204(sp) - d94: 460e lw a2,192(sp) - d96: 469e lw a3,196(sp) - d98: d73e sw a5,172(sp) - d9a: 5792 lw a5,36(sp) - d9c: 472e lw a4,200(sp) - d9e: d132 sw a2,160(sp) - da0: c93e sw a5,144(sp) - da2: 57a2 lw a5,40(sp) - da4: 0910 add a2,sp,144 - da6: 110c add a1,sp,160 - da8: cb3e sw a5,148(sp) - daa: 57b2 lw a5,44(sp) - dac: 1908 add a0,sp,176 - dae: d336 sw a3,164(sp) - db0: cd3e sw a5,152(sp) - db2: 57f2 lw a5,60(sp) - db4: d53a sw a4,168(sp) - db6: cf3e sw a5,156(sp) - db8: 00000097 auipc ra,0x0 - dbc: 000080e7 jalr ra # db8 <.LVL143+0x26> - -00000dc0 <.LVL144>: - dc0: 57fa lw a5,188(sp) - dc2: 564a lw a2,176(sp) - dc4: 56da lw a3,180(sp) - dc6: cf3e sw a5,156(sp) - dc8: 4782 lw a5,0(sp) - dca: 576a lw a4,184(sp) - dcc: c932 sw a2,144(sp) - dce: c13e sw a5,128(sp) - dd0: 4792 lw a5,4(sp) - dd2: 0110 add a2,sp,128 - dd4: 090c add a1,sp,144 - dd6: c33e sw a5,132(sp) - dd8: 47a2 lw a5,8(sp) - dda: 1108 add a0,sp,160 - ddc: cb36 sw a3,148(sp) - dde: c53e sw a5,136(sp) - de0: 57d2 lw a5,52(sp) - de2: cd3a sw a4,152(sp) - de4: c73e sw a5,140(sp) - de6: 00000097 auipc ra,0x0 - dea: 000080e7 jalr ra # de6 <.LVL144+0x26> - -00000dee <.LVL145>: - dee: 57ba lw a5,172(sp) - df0: 560a lw a2,160(sp) - df2: 569a lw a3,164(sp) - df4: c73e sw a5,140(sp) - df6: 47f6 lw a5,92(sp) - df8: 572a lw a4,168(sp) - dfa: c132 sw a2,128(sp) - dfc: d8be sw a5,112(sp) - dfe: 5786 lw a5,96(sp) - e00: 1890 add a2,sp,112 - e02: 010c add a1,sp,128 - e04: dabe sw a5,116(sp) - e06: 5796 lw a5,100(sp) - e08: 0908 add a0,sp,144 - e0a: c336 sw a3,132(sp) - e0c: dcbe sw a5,120(sp) - e0e: 57a6 lw a5,104(sp) - e10: c53a sw a4,136(sp) - e12: debe sw a5,124(sp) - e14: 00000097 auipc ra,0x0 - e18: 000080e7 jalr ra # e14 <.LVL145+0x26> - -00000e1c <.LVL146>: - e1c: 47ca lw a5,144(sp) - e1e: 1110 add a2,sp,160 - e20: 190c add a1,sp,176 - e22: c2be sw a5,68(sp) - e24: 47da lw a5,148(sp) - e26: 0188 add a0,sp,192 - e28: c4be sw a5,72(sp) - e2a: 47ea lw a5,152(sp) - e2c: c6be sw a5,76(sp) - e2e: 47fa lw a5,156(sp) - e30: c8be sw a5,80(sp) - -00000e32 <.LVL147>: - e32: 4782 lw a5,0(sp) - -00000e34 <.LVL148>: - e34: d93e sw a5,176(sp) - e36: 4792 lw a5,4(sp) - e38: db3e sw a5,180(sp) - e3a: 47a2 lw a5,8(sp) - e3c: dd3e sw a5,184(sp) - e3e: 57d2 lw a5,52(sp) - e40: df3e sw a5,188(sp) - e42: 47e2 lw a5,24(sp) - e44: d13e sw a5,160(sp) - e46: 47f2 lw a5,28(sp) - e48: d33e sw a5,164(sp) - e4a: 5782 lw a5,32(sp) - e4c: d53e sw a5,168(sp) - e4e: 57e2 lw a5,56(sp) - e50: d73e sw a5,172(sp) - e52: 00000097 auipc ra,0x0 - e56: 000080e7 jalr ra # e52 <.LVL148+0x1e> - -00000e5a <.LVL149>: - e5a: 47be lw a5,204(sp) - e5c: 460e lw a2,192(sp) - e5e: 469e lw a3,196(sp) - e60: d73e sw a5,172(sp) - e62: 5792 lw a5,36(sp) - e64: 472e lw a4,200(sp) - e66: d132 sw a2,160(sp) - e68: c93e sw a5,144(sp) - e6a: 57a2 lw a5,40(sp) - e6c: 0910 add a2,sp,144 - e6e: 110c add a1,sp,160 - e70: cb3e sw a5,148(sp) - e72: 57b2 lw a5,44(sp) - e74: 1908 add a0,sp,176 - e76: d336 sw a3,164(sp) - e78: cd3e sw a5,152(sp) - e7a: 57f2 lw a5,60(sp) - e7c: d53a sw a4,168(sp) - e7e: cf3e sw a5,156(sp) - e80: 00000097 auipc ra,0x0 - e84: 000080e7 jalr ra # e80 <.LVL149+0x26> - -00000e88 <.LVL150>: - e88: 45b2 lw a1,12(sp) - e8a: 564a lw a2,176(sp) - e8c: 56da lw a3,180(sp) - e8e: c92e sw a1,144(sp) - e90: 45c2 lw a1,16(sp) - e92: 576a lw a4,184(sp) - e94: 57fa lw a5,188(sp) - e96: cb2e sw a1,148(sp) - e98: 45d2 lw a1,20(sp) - e9a: c132 sw a2,128(sp) - e9c: c336 sw a3,132(sp) - e9e: cd2e sw a1,152(sp) - ea0: 55c2 lw a1,48(sp) - ea2: c53a sw a4,136(sp) - ea4: cf2e sw a1,156(sp) - ea6: b2f1 j 872 <.L81> - -00000ea8 <.L34>: - ea8: 57d2 lw a5,52(sp) - eaa: 54fd li s1,-1 - eac: 190c add a1,sp,176 - eae: 0786 sll a5,a5,0x1 - eb0: 8385 srl a5,a5,0x1 - eb2: d2be sw a5,100(sp) - eb4: 000007b7 lui a5,0x0 - eb8: 00c7a403 lw s0,12(a5) # c <__divtc3+0xc> - ebc: 4782 lw a5,0(sp) - ebe: 0188 add a0,sp,192 - ec0: d926 sw s1,176(sp) - ec2: c1be sw a5,192(sp) - ec4: 4792 lw a5,4(sp) - ec6: db26 sw s1,180(sp) - ec8: dd26 sw s1,184(sp) - eca: c3be sw a5,196(sp) - ecc: 47a2 lw a5,8(sp) - ece: df22 sw s0,188(sp) - ed0: c5be sw a5,200(sp) - ed2: 5796 lw a5,100(sp) - ed4: c7be sw a5,204(sp) - ed6: 00000097 auipc ra,0x0 - eda: 000080e7 jalr ra # ed6 <.L34+0x2e> - -00000ede <.LVL152>: - ede: e909 bnez a0,ef0 <.L67> - ee0: 190c add a1,sp,176 - ee2: 0188 add a0,sp,192 - ee4: 00000097 auipc ra,0x0 - ee8: 000080e7 jalr ra # ee4 <.LVL152+0x6> - -00000eec <.LVL153>: - eec: 04a04863 bgtz a0,f3c <.L40> - -00000ef0 <.L67>: - ef0: 57c2 lw a5,48(sp) - ef2: 00000737 lui a4,0x0 - ef6: 54fd li s1,-1 - ef8: 0786 sll a5,a5,0x1 - efa: 0017d413 srl s0,a5,0x1 - efe: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - f02: 190c add a1,sp,176 - f04: 0188 add a0,sp,192 - f06: d4be sw a5,104(sp) - f08: 47b2 lw a5,12(sp) - f0a: c7a2 sw s0,204(sp) - f0c: d926 sw s1,176(sp) - f0e: c1be sw a5,192(sp) - f10: 47c2 lw a5,16(sp) - f12: db26 sw s1,180(sp) - f14: dd26 sw s1,184(sp) - f16: c3be sw a5,196(sp) - f18: 47d2 lw a5,20(sp) - f1a: c5be sw a5,200(sp) - f1c: 57a6 lw a5,104(sp) - f1e: df3e sw a5,188(sp) - f20: 00000097 auipc ra,0x0 - f24: 000080e7 jalr ra # f20 <.L67+0x30> - -00000f28 <.LVL154>: - f28: 30051763 bnez a0,1236 <.L42> - f2c: 190c add a1,sp,176 - f2e: 0188 add a0,sp,192 - f30: 00000097 auipc ra,0x0 - f34: 000080e7 jalr ra # f30 <.LVL154+0x8> - -00000f38 <.LVL155>: - f38: 2ea05f63 blez a0,1236 <.L42> - -00000f3c <.L40>: - f3c: 57e2 lw a5,56(sp) - f3e: 80000437 lui s0,0x80000 - f42: fff44413 not s0,s0 - f46: 000006b7 lui a3,0x0 - f4a: 0087f733 and a4,a5,s0 - f4e: 00c6a783 lw a5,12(a3) # c <__divtc3+0xc> - f52: 54fd li s1,-1 - f54: 190c add a1,sp,176 - f56: d4be sw a5,104(sp) - f58: 47e2 lw a5,24(sp) - f5a: 0188 add a0,sp,192 - f5c: c7ba sw a4,204(sp) - f5e: c1be sw a5,192(sp) - f60: 47f2 lw a5,28(sp) - f62: d6ba sw a4,108(sp) - f64: d926 sw s1,176(sp) - f66: c3be sw a5,196(sp) - f68: 5782 lw a5,32(sp) - f6a: db26 sw s1,180(sp) - f6c: dd26 sw s1,184(sp) - f6e: c5be sw a5,200(sp) - f70: 57a6 lw a5,104(sp) - f72: df3e sw a5,188(sp) - f74: 00000097 auipc ra,0x0 - f78: 000080e7 jalr ra # f74 <.L40+0x38> - -00000f7c <.LVL156>: - f7c: 2a051d63 bnez a0,1236 <.L42> - f80: 190c add a1,sp,176 - f82: 0188 add a0,sp,192 - f84: 00000097 auipc ra,0x0 - f88: 000080e7 jalr ra # f84 <.LVL156+0x8> - -00000f8c <.LVL157>: - f8c: 2aa04563 bgtz a0,1236 <.L42> - f90: 57f2 lw a5,60(sp) - f92: 190c add a1,sp,176 - f94: 0188 add a0,sp,192 - f96: 8c7d and s0,s0,a5 - f98: 5792 lw a5,36(sp) - f9a: c7a2 sw s0,204(sp) - f9c: c1be sw a5,192(sp) - f9e: 57a2 lw a5,40(sp) - fa0: c3be sw a5,196(sp) - fa2: 57b2 lw a5,44(sp) - fa4: c5be sw a5,200(sp) - fa6: 00000097 auipc ra,0x0 - faa: 000080e7 jalr ra # fa6 <.LVL157+0x1a> - -00000fae <.LVL158>: - fae: 28051463 bnez a0,1236 <.L42> - fb2: 190c add a1,sp,176 - fb4: 0188 add a0,sp,192 - fb6: 00000097 auipc ra,0x0 - fba: 000080e7 jalr ra # fb6 <.LVL158+0x8> - -00000fbe <.LVL159>: - fbe: 26a04c63 bgtz a0,1236 <.L42> - fc2: 4782 lw a5,0(sp) - fc4: 190c add a1,sp,176 - fc6: 0188 add a0,sp,192 - fc8: c1be sw a5,192(sp) - fca: 4792 lw a5,4(sp) - fcc: 4405 li s0,1 - fce: c3be sw a5,196(sp) - fd0: 47a2 lw a5,8(sp) - fd2: c5be sw a5,200(sp) - fd4: 5796 lw a5,100(sp) - fd6: c7be sw a5,204(sp) - fd8: 00000097 auipc ra,0x0 - fdc: 000080e7 jalr ra # fd8 <.LVL159+0x1a> - -00000fe0 <.LVL160>: - fe0: e911 bnez a0,ff4 <.L43> - fe2: 190c add a1,sp,176 - fe4: 0188 add a0,sp,192 - fe6: 00000097 auipc ra,0x0 - fea: 000080e7 jalr ra # fe6 <.LVL160+0x6> - -00000fee <.LVL161>: - fee: 00a05363 blez a0,ff4 <.L43> - ff2: 4401 li s0,0 - -00000ff4 <.L43>: - ff4: 00144593 xor a1,s0,1 - ff8: 8985 and a1,a1,1 - ffa: 0188 add a0,sp,192 - ffc: 00000097 auipc ra,0x0 - 1000: 000080e7 jalr ra # ffc <.L43+0x8> - -00001004 <.LVL162>: - 1004: 478e lw a5,192(sp) - 1006: 46be lw a3,204(sp) - 1008: 5652 lw a2,52(sp) - 100a: cabe sw a5,84(sp) - -0000100c <.LVL163>: - 100c: 479e lw a5,196(sp) - 100e: 54fd li s1,-1 - 1010: 190c add a1,sp,176 - 1012: ccbe sw a5,88(sp) - 1014: 47ae lw a5,200(sp) - 1016: 0188 add a0,sp,192 - 1018: 4405 li s0,1 - 101a: cebe sw a5,92(sp) - 101c: 800007b7 lui a5,0x80000 - 1020: fff7c713 not a4,a5 - 1024: 8ef9 and a3,a3,a4 - 1026: 8ff1 and a5,a5,a2 - 1028: 8fd5 or a5,a5,a3 - 102a: c43e sw a5,8(sp) - -0000102c <.LVL164>: - 102c: 57c2 lw a5,48(sp) - -0000102e <.LVL165>: - 102e: 000006b7 lui a3,0x0 - 1032: d926 sw s1,176(sp) - 1034: 8f7d and a4,a4,a5 - 1036: 00c6a783 lw a5,12(a3) # c <__divtc3+0xc> - 103a: c7ba sw a4,204(sp) - 103c: c23a sw a4,4(sp) - 103e: c03e sw a5,0(sp) - 1040: 47b2 lw a5,12(sp) - 1042: db26 sw s1,180(sp) - 1044: dd26 sw s1,184(sp) - 1046: c1be sw a5,192(sp) - -00001048 <.LVL166>: - 1048: 47c2 lw a5,16(sp) - 104a: c3be sw a5,196(sp) - -0000104c <.LVL167>: - 104c: 47d2 lw a5,20(sp) - 104e: c5be sw a5,200(sp) - -00001050 <.LVL168>: - 1050: 4782 lw a5,0(sp) - 1052: df3e sw a5,188(sp) - 1054: 00000097 auipc ra,0x0 - 1058: 000080e7 jalr ra # 1054 <.LVL168+0x4> - -0000105c <.LVL169>: - 105c: e911 bnez a0,1070 <.L44> - 105e: 190c add a1,sp,176 - 1060: 0188 add a0,sp,192 - 1062: 00000097 auipc ra,0x0 - 1066: 000080e7 jalr ra # 1062 <.LVL169+0x6> - -0000106a <.LVL170>: - 106a: 00a05363 blez a0,1070 <.L44> - 106e: 4401 li s0,0 - -00001070 <.L44>: - 1070: 00144593 xor a1,s0,1 - 1074: 8985 and a1,a1,1 - 1076: 0188 add a0,sp,192 - 1078: 00000097 auipc ra,0x0 - 107c: 000080e7 jalr ra # 1078 <.L44+0x8> - -00001080 <.LVL171>: - 1080: 479e lw a5,196(sp) - 1082: 443e lw s0,204(sp) - 1084: 1110 add a2,sp,160 - 1086: c03e sw a5,0(sp) - 1088: 47ae lw a5,200(sp) - 108a: 190c add a1,sp,176 - 108c: 0188 add a0,sp,192 - 108e: c23e sw a5,4(sp) - 1090: 800007b7 lui a5,0x80000 - 1094: fff7c713 not a4,a5 - 1098: 8c79 and s0,s0,a4 - 109a: 5742 lw a4,48(sp) - 109c: 448e lw s1,192(sp) - 109e: 8ff9 and a5,a5,a4 - 10a0: 8c5d or s0,s0,a5 - -000010a2 <.LVL172>: - 10a2: 47e2 lw a5,24(sp) - 10a4: d93e sw a5,176(sp) - 10a6: 47f2 lw a5,28(sp) - 10a8: db3e sw a5,180(sp) - 10aa: 5782 lw a5,32(sp) - 10ac: dd3e sw a5,184(sp) - 10ae: 57e2 lw a5,56(sp) - 10b0: df3e sw a5,188(sp) - 10b2: 47d6 lw a5,84(sp) - 10b4: d13e sw a5,160(sp) - 10b6: 47e6 lw a5,88(sp) - 10b8: d33e sw a5,164(sp) - 10ba: 47f6 lw a5,92(sp) - 10bc: d53e sw a5,168(sp) - 10be: 47a2 lw a5,8(sp) - 10c0: d73e sw a5,172(sp) - 10c2: 00000097 auipc ra,0x0 - 10c6: 000080e7 jalr ra # 10c2 <.LVL172+0x20> - -000010ca <.LVL173>: - 10ca: 5792 lw a5,36(sp) - 10cc: 438e lw t2,192(sp) - 10ce: 429e lw t0,196(sp) - 10d0: d13e sw a5,160(sp) - 10d2: 57a2 lw a5,40(sp) - 10d4: 432e lw t1,200(sp) - 10d6: 46be lw a3,204(sp) - 10d8: d33e sw a5,164(sp) - 10da: 57b2 lw a5,44(sp) - 10dc: 0910 add a2,sp,144 - 10de: 110c add a1,sp,160 - 10e0: d53e sw a5,168(sp) - 10e2: 57f2 lw a5,60(sp) - 10e4: 1908 add a0,sp,176 - 10e6: d81e sw t2,48(sp) - 10e8: d73e sw a5,172(sp) - 10ea: 4782 lw a5,0(sp) - 10ec: ca16 sw t0,20(sp) - 10ee: c81a sw t1,16(sp) - 10f0: cb3e sw a5,148(sp) - 10f2: 4792 lw a5,4(sp) - 10f4: c636 sw a3,12(sp) - 10f6: c926 sw s1,144(sp) - 10f8: cd3e sw a5,152(sp) - 10fa: cf22 sw s0,156(sp) - 10fc: 00000097 auipc ra,0x0 - 1100: 000080e7 jalr ra # 10fc <.LVL173+0x32> - -00001104 <.LVL174>: - 1104: 55ca lw a1,176(sp) - 1106: 565a lw a2,180(sp) - 1108: 53c2 lw t2,48(sp) - 110a: 42d2 lw t0,20(sp) - 110c: 4342 lw t1,16(sp) - 110e: 576a lw a4,184(sp) - 1110: 57fa lw a5,188(sp) - 1112: 46b2 lw a3,12(sp) - 1114: c12e sw a1,128(sp) - 1116: c332 sw a2,132(sp) - 1118: 090c add a1,sp,144 - 111a: 0110 add a2,sp,128 - 111c: 1108 add a0,sp,160 - 111e: c91e sw t2,144(sp) - 1120: cb16 sw t0,148(sp) - 1122: cd1a sw t1,152(sp) - 1124: cf36 sw a3,156(sp) - 1126: c53a sw a4,136(sp) - 1128: c73e sw a5,140(sp) - 112a: 00000097 auipc ra,0x0 - 112e: 000080e7 jalr ra # 112a <.LVL174+0x26> - -00001132 <.LVL175>: - 1132: 558a lw a1,160(sp) - 1134: 561a lw a2,164(sp) - 1136: 573a lw a4,172(sp) - 1138: 56aa lw a3,168(sp) - 113a: 7fff07b7 lui a5,0x7fff0 - 113e: c12e sw a1,128(sp) - 1140: c332 sw a2,132(sp) - 1142: 010c add a1,sp,128 - 1144: 1890 add a2,sp,112 - 1146: 0908 add a0,sp,144 - 1148: c73a sw a4,140(sp) - 114a: c536 sw a3,136(sp) - 114c: debe sw a5,124(sp) - 114e: d882 sw zero,112(sp) - 1150: da82 sw zero,116(sp) - 1152: dc82 sw zero,120(sp) - 1154: 00000097 auipc ra,0x0 - 1158: 000080e7 jalr ra # 1154 <.LVL175+0x22> - -0000115c <.LVL176>: - 115c: 47ca lw a5,144(sp) - 115e: 1110 add a2,sp,160 - 1160: 190c add a1,sp,176 - 1162: c2be sw a5,68(sp) - -00001164 <.LVL177>: - 1164: 47da lw a5,148(sp) - 1166: 0188 add a0,sp,192 - 1168: d126 sw s1,160(sp) - 116a: c4be sw a5,72(sp) - 116c: 47ea lw a5,152(sp) - 116e: d722 sw s0,172(sp) - 1170: c6be sw a5,76(sp) - 1172: 47fa lw a5,156(sp) - 1174: c8be sw a5,80(sp) - -00001176 <.LVL178>: - 1176: 47e2 lw a5,24(sp) - -00001178 <.LVL179>: - 1178: d93e sw a5,176(sp) - 117a: 47f2 lw a5,28(sp) - 117c: db3e sw a5,180(sp) - 117e: 5782 lw a5,32(sp) - 1180: dd3e sw a5,184(sp) - 1182: 57e2 lw a5,56(sp) - 1184: df3e sw a5,188(sp) - 1186: 4782 lw a5,0(sp) - 1188: d33e sw a5,164(sp) - 118a: 4792 lw a5,4(sp) - 118c: d53e sw a5,168(sp) - 118e: 00000097 auipc ra,0x0 - 1192: 000080e7 jalr ra # 118e <.LVL179+0x16> - -00001196 <.LVL180>: - 1196: 5792 lw a5,36(sp) - 1198: 430e lw t1,192(sp) - 119a: 469e lw a3,196(sp) - 119c: d13e sw a5,160(sp) - 119e: 57a2 lw a5,40(sp) - 11a0: 0910 add a2,sp,144 - 11a2: 110c add a1,sp,160 - 11a4: d33e sw a5,164(sp) - 11a6: 57b2 lw a5,44(sp) - 11a8: 1908 add a0,sp,176 - 11aa: 44ae lw s1,200(sp) - -000011ac <.LVL181>: - 11ac: d53e sw a5,168(sp) - 11ae: 57f2 lw a5,60(sp) - 11b0: 443e lw s0,204(sp) - 11b2: c21a sw t1,4(sp) - 11b4: d73e sw a5,172(sp) - 11b6: 47d6 lw a5,84(sp) - 11b8: c036 sw a3,0(sp) - 11ba: c93e sw a5,144(sp) - 11bc: 47e6 lw a5,88(sp) - 11be: cb3e sw a5,148(sp) - 11c0: 47f6 lw a5,92(sp) - 11c2: cd3e sw a5,152(sp) - 11c4: 47a2 lw a5,8(sp) - 11c6: cf3e sw a5,156(sp) - 11c8: 00000097 auipc ra,0x0 - 11cc: 000080e7 jalr ra # 11c8 <.LVL181+0x1c> - -000011d0 <.LVL182>: - 11d0: 554a lw a0,176(sp) - 11d2: 55da lw a1,180(sp) - 11d4: 566a lw a2,184(sp) - 11d6: 577a lw a4,188(sp) - 11d8: 4682 lw a3,0(sp) - 11da: 4312 lw t1,4(sp) - 11dc: c12a sw a0,128(sp) - 11de: c32e sw a1,132(sp) - 11e0: c532 sw a2,136(sp) - 11e2: 090c add a1,sp,144 - 11e4: 0110 add a2,sp,128 - 11e6: 1108 add a0,sp,160 - 11e8: cb36 sw a3,148(sp) - 11ea: c73a sw a4,140(sp) - 11ec: c91a sw t1,144(sp) - 11ee: cd26 sw s1,152(sp) - 11f0: cf22 sw s0,156(sp) - 11f2: 00000097 auipc ra,0x0 - 11f6: 000080e7 jalr ra # 11f2 <.LVL182+0x22> - -000011fa <.LVL183>: - 11fa: 558a lw a1,160(sp) - 11fc: 561a lw a2,164(sp) - 11fe: 56aa lw a3,168(sp) - 1200: 573a lw a4,172(sp) - 1202: 7fff07b7 lui a5,0x7fff0 - 1206: c12e sw a1,128(sp) - 1208: c332 sw a2,132(sp) - 120a: c536 sw a3,136(sp) - 120c: c73a sw a4,140(sp) - 120e: d882 sw zero,112(sp) - 1210: da82 sw zero,116(sp) - 1212: dc82 sw zero,120(sp) - 1214: debe sw a5,124(sp) - -00001216 <.L83>: - 1216: 1890 add a2,sp,112 - 1218: 010c add a1,sp,128 - 121a: 0908 add a0,sp,144 - 121c: 00000097 auipc ra,0x0 - 1220: 000080e7 jalr ra # 121c <.L83+0x6> - -00001224 <.LVL185>: - 1224: 47ca lw a5,144(sp) - 1226: cabe sw a5,84(sp) - 1228: 47da lw a5,148(sp) - 122a: ccbe sw a5,88(sp) - 122c: 47ea lw a5,152(sp) - 122e: cebe sw a5,92(sp) - 1230: 47fa lw a5,156(sp) - 1232: cdcff06f j 70e <.L82> - -00001236 <.L42>: - 1236: 57e2 lw a5,56(sp) - 1238: 54fd li s1,-1 - 123a: 190c add a1,sp,176 - 123c: 0786 sll a5,a5,0x1 - 123e: 8385 srl a5,a5,0x1 - 1240: d6be sw a5,108(sp) - 1242: 000007b7 lui a5,0x0 - 1246: 00c7a403 lw s0,12(a5) # c <__divtc3+0xc> - 124a: 47e2 lw a5,24(sp) - 124c: 0188 add a0,sp,192 - 124e: d926 sw s1,176(sp) - 1250: c1be sw a5,192(sp) - 1252: 47f2 lw a5,28(sp) - 1254: db26 sw s1,180(sp) - 1256: dd26 sw s1,184(sp) - 1258: c3be sw a5,196(sp) - 125a: 5782 lw a5,32(sp) - 125c: df22 sw s0,188(sp) - 125e: c5be sw a5,200(sp) - 1260: 57b6 lw a5,108(sp) - 1262: c7be sw a5,204(sp) - 1264: 00000097 auipc ra,0x0 - 1268: 000080e7 jalr ra # 1264 <.L42+0x2e> - -0000126c <.LVL187>: - 126c: e909 bnez a0,127e <.L68> - 126e: 190c add a1,sp,176 - 1270: 0188 add a0,sp,192 - 1272: 00000097 auipc ra,0x0 - 1276: 000080e7 jalr ra # 1272 <.LVL187+0x6> - -0000127a <.LVL188>: - 127a: 04a04863 bgtz a0,12ca <.L45> - -0000127e <.L68>: - 127e: 57f2 lw a5,60(sp) - 1280: 00000737 lui a4,0x0 - 1284: 54fd li s1,-1 - 1286: 0786 sll a5,a5,0x1 - 1288: 0017d413 srl s0,a5,0x1 - 128c: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - 1290: 190c add a1,sp,176 - 1292: 0188 add a0,sp,192 - 1294: d4be sw a5,104(sp) - 1296: 5792 lw a5,36(sp) - 1298: c7a2 sw s0,204(sp) - 129a: d926 sw s1,176(sp) - 129c: c1be sw a5,192(sp) - 129e: 57a2 lw a5,40(sp) - 12a0: db26 sw s1,180(sp) - 12a2: dd26 sw s1,184(sp) - 12a4: c3be sw a5,196(sp) - 12a6: 57b2 lw a5,44(sp) - 12a8: c5be sw a5,200(sp) - 12aa: 57a6 lw a5,104(sp) - 12ac: df3e sw a5,188(sp) - 12ae: 00000097 auipc ra,0x0 - 12b2: 000080e7 jalr ra # 12ae <.L68+0x30> - -000012b6 <.LVL189>: - 12b6: c4051d63 bnez a0,710 <.L31> - 12ba: 190c add a1,sp,176 - 12bc: 0188 add a0,sp,192 - 12be: 00000097 auipc ra,0x0 - 12c2: 000080e7 jalr ra # 12be <.LVL189+0x8> - -000012c6 <.LVL190>: - 12c6: c4a05563 blez a0,710 <.L31> - -000012ca <.L45>: - 12ca: 00000737 lui a4,0x0 - 12ce: 00c72783 lw a5,12(a4) # c <__divtc3+0xc> - 12d2: 547d li s0,-1 - 12d4: 190c add a1,sp,176 - 12d6: d4be sw a5,104(sp) - 12d8: 4782 lw a5,0(sp) - 12da: 0188 add a0,sp,192 - 12dc: d922 sw s0,176(sp) - 12de: c1be sw a5,192(sp) - 12e0: 4792 lw a5,4(sp) - 12e2: db22 sw s0,180(sp) - 12e4: dd22 sw s0,184(sp) - 12e6: c3be sw a5,196(sp) - 12e8: 47a2 lw a5,8(sp) - 12ea: c5be sw a5,200(sp) - 12ec: 5796 lw a5,100(sp) - 12ee: c7be sw a5,204(sp) - 12f0: 57a6 lw a5,104(sp) - 12f2: df3e sw a5,188(sp) - 12f4: 00000097 auipc ra,0x0 - 12f8: 000080e7 jalr ra # 12f4 <.L45+0x2a> - -000012fc <.LVL191>: - 12fc: c0051a63 bnez a0,710 <.L31> - 1300: 190c add a1,sp,176 - 1302: 0188 add a0,sp,192 - 1304: 00000097 auipc ra,0x0 - 1308: 000080e7 jalr ra # 1304 <.LVL191+0x8> - -0000130c <.LVL192>: - 130c: c0a04263 bgtz a0,710 <.L31> - 1310: 57c2 lw a5,48(sp) - 1312: 190c add a1,sp,176 - 1314: 0188 add a0,sp,192 - 1316: 00179493 sll s1,a5,0x1 - 131a: 47b2 lw a5,12(sp) - 131c: 8085 srl s1,s1,0x1 - 131e: c7a6 sw s1,204(sp) - 1320: c1be sw a5,192(sp) - 1322: 47c2 lw a5,16(sp) - 1324: c3be sw a5,196(sp) - 1326: 47d2 lw a5,20(sp) - 1328: c5be sw a5,200(sp) - 132a: 00000097 auipc ra,0x0 - 132e: 000080e7 jalr ra # 132a <.LVL192+0x1e> - -00001332 <.LVL193>: - 1332: bc051f63 bnez a0,710 <.L31> - 1336: 190c add a1,sp,176 - 1338: 0188 add a0,sp,192 - 133a: 00000097 auipc ra,0x0 - 133e: 000080e7 jalr ra # 133a <.LVL193+0x8> - -00001342 <.LVL194>: - 1342: bca04763 bgtz a0,710 <.L31> - 1346: 47e2 lw a5,24(sp) - 1348: 190c add a1,sp,176 - 134a: 0188 add a0,sp,192 - 134c: c1be sw a5,192(sp) - 134e: 47f2 lw a5,28(sp) - 1350: 4485 li s1,1 - 1352: c3be sw a5,196(sp) - 1354: 5782 lw a5,32(sp) - 1356: c5be sw a5,200(sp) - 1358: 57b6 lw a5,108(sp) - 135a: c7be sw a5,204(sp) - 135c: 00000097 auipc ra,0x0 - 1360: 000080e7 jalr ra # 135c <.LVL194+0x1a> - -00001364 <.LVL195>: - 1364: e911 bnez a0,1378 <.L47> - 1366: 190c add a1,sp,176 - 1368: 0188 add a0,sp,192 - 136a: 00000097 auipc ra,0x0 - 136e: 000080e7 jalr ra # 136a <.LVL195+0x6> - -00001372 <.LVL196>: - 1372: 00a05363 blez a0,1378 <.L47> - 1376: 4481 li s1,0 - -00001378 <.L47>: - 1378: 0014c593 xor a1,s1,1 - 137c: 8985 and a1,a1,1 - 137e: 0188 add a0,sp,192 - 1380: 00000097 auipc ra,0x0 - 1384: 000080e7 jalr ra # 1380 <.L47+0x8> - -00001388 <.LVL197>: - 1388: 478e lw a5,192(sp) - 138a: 46be lw a3,204(sp) - 138c: 5662 lw a2,56(sp) - 138e: cabe sw a5,84(sp) - -00001390 <.LVL198>: - 1390: 479e lw a5,196(sp) - 1392: 54fd li s1,-1 - 1394: 190c add a1,sp,176 - 1396: ccbe sw a5,88(sp) - 1398: 47ae lw a5,200(sp) - 139a: 0188 add a0,sp,192 - 139c: 4405 li s0,1 - 139e: cebe sw a5,92(sp) - 13a0: 800007b7 lui a5,0x80000 - 13a4: fff7c713 not a4,a5 - 13a8: 8ef9 and a3,a3,a4 - 13aa: 8ff1 and a5,a5,a2 - 13ac: 8fd5 or a5,a5,a3 - 13ae: d03e sw a5,32(sp) - -000013b0 <.LVL199>: - 13b0: 57f2 lw a5,60(sp) - -000013b2 <.LVL200>: - 13b2: 000006b7 lui a3,0x0 - 13b6: d926 sw s1,176(sp) - 13b8: 8f7d and a4,a4,a5 - 13ba: 00c6a783 lw a5,12(a3) # c <__divtc3+0xc> - 13be: c7ba sw a4,204(sp) - 13c0: ce3a sw a4,28(sp) - 13c2: cc3e sw a5,24(sp) - 13c4: 5792 lw a5,36(sp) - 13c6: db26 sw s1,180(sp) - 13c8: dd26 sw s1,184(sp) - 13ca: c1be sw a5,192(sp) - -000013cc <.LVL201>: - 13cc: 57a2 lw a5,40(sp) - 13ce: c3be sw a5,196(sp) - -000013d0 <.LVL202>: - 13d0: 57b2 lw a5,44(sp) - 13d2: c5be sw a5,200(sp) - -000013d4 <.LVL203>: - 13d4: 47e2 lw a5,24(sp) - 13d6: df3e sw a5,188(sp) - 13d8: 00000097 auipc ra,0x0 - 13dc: 000080e7 jalr ra # 13d8 <.LVL203+0x4> - -000013e0 <.LVL204>: - 13e0: e911 bnez a0,13f4 <.L48> - 13e2: 190c add a1,sp,176 - 13e4: 0188 add a0,sp,192 - 13e6: 00000097 auipc ra,0x0 - 13ea: 000080e7 jalr ra # 13e6 <.LVL204+0x6> - -000013ee <.LVL205>: - 13ee: 00a05363 blez a0,13f4 <.L48> - 13f2: 4401 li s0,0 - -000013f4 <.L48>: - 13f4: 00144593 xor a1,s0,1 - 13f8: 8985 and a1,a1,1 - 13fa: 0188 add a0,sp,192 - 13fc: 00000097 auipc ra,0x0 - 1400: 000080e7 jalr ra # 13fc <.L48+0x8> - -00001404 <.LVL206>: - 1404: 478e lw a5,192(sp) - 1406: 443e lw s0,204(sp) - 1408: 1110 add a2,sp,160 - 140a: cc3e sw a5,24(sp) - 140c: 479e lw a5,196(sp) - 140e: 190c add a1,sp,176 - 1410: 0188 add a0,sp,192 - 1412: ce3e sw a5,28(sp) - 1414: 800007b7 lui a5,0x80000 - 1418: fff7c713 not a4,a5 - 141c: 8c79 and s0,s0,a4 - 141e: 5772 lw a4,60(sp) - 1420: 44ae lw s1,200(sp) - 1422: 8ff9 and a5,a5,a4 - 1424: 8c5d or s0,s0,a5 - -00001426 <.LVL207>: - 1426: 4782 lw a5,0(sp) - 1428: d93e sw a5,176(sp) - 142a: 4792 lw a5,4(sp) - 142c: db3e sw a5,180(sp) - 142e: 47a2 lw a5,8(sp) - 1430: dd3e sw a5,184(sp) - 1432: 57d2 lw a5,52(sp) - 1434: df3e sw a5,188(sp) - 1436: 47d6 lw a5,84(sp) - 1438: d13e sw a5,160(sp) - 143a: 47e6 lw a5,88(sp) - 143c: d33e sw a5,164(sp) - 143e: 47f6 lw a5,92(sp) - 1440: d53e sw a5,168(sp) - 1442: 5782 lw a5,32(sp) - 1444: d73e sw a5,172(sp) - 1446: 00000097 auipc ra,0x0 - 144a: 000080e7 jalr ra # 1446 <.LVL207+0x20> - -0000144e <.LVL208>: - 144e: 47b2 lw a5,12(sp) - 1450: 438e lw t2,192(sp) - 1452: 429e lw t0,196(sp) - 1454: d13e sw a5,160(sp) - 1456: 47c2 lw a5,16(sp) - 1458: 432e lw t1,200(sp) - 145a: 46be lw a3,204(sp) - 145c: d33e sw a5,164(sp) - 145e: 47d2 lw a5,20(sp) - 1460: 0910 add a2,sp,144 - 1462: 110c add a1,sp,160 - 1464: d53e sw a5,168(sp) - 1466: 57c2 lw a5,48(sp) - 1468: 1908 add a0,sp,176 - 146a: dc1e sw t2,56(sp) - 146c: d73e sw a5,172(sp) - 146e: 47e2 lw a5,24(sp) - 1470: d616 sw t0,44(sp) - 1472: d41a sw t1,40(sp) - 1474: c93e sw a5,144(sp) - 1476: 47f2 lw a5,28(sp) - 1478: d236 sw a3,36(sp) - 147a: cd26 sw s1,152(sp) - 147c: cb3e sw a5,148(sp) - 147e: cf22 sw s0,156(sp) - 1480: 00000097 auipc ra,0x0 - 1484: 000080e7 jalr ra # 1480 <.LVL208+0x32> - -00001488 <.LVL209>: - 1488: 55ca lw a1,176(sp) - 148a: 565a lw a2,180(sp) - 148c: 53e2 lw t2,56(sp) - 148e: 52b2 lw t0,44(sp) - 1490: 5322 lw t1,40(sp) - 1492: 576a lw a4,184(sp) - 1494: 57fa lw a5,188(sp) - 1496: 5692 lw a3,36(sp) - 1498: c12e sw a1,128(sp) - 149a: c332 sw a2,132(sp) - 149c: 090c add a1,sp,144 - 149e: 0110 add a2,sp,128 - 14a0: 1108 add a0,sp,160 - 14a2: c91e sw t2,144(sp) - 14a4: cb16 sw t0,148(sp) - 14a6: cd1a sw t1,152(sp) - 14a8: cf36 sw a3,156(sp) - 14aa: c53a sw a4,136(sp) - 14ac: c73e sw a5,140(sp) - 14ae: 00000097 auipc ra,0x0 - 14b2: 000080e7 jalr ra # 14ae <.LVL209+0x26> - -000014b6 <.LVL210>: - 14b6: 560a lw a2,160(sp) - 14b8: 572a lw a4,168(sp) - 14ba: 569a lw a3,164(sp) - 14bc: 57ba lw a5,172(sp) - 14be: c132 sw a2,128(sp) - 14c0: 010c add a1,sp,128 - 14c2: 1890 add a2,sp,112 - 14c4: 0908 add a0,sp,144 - 14c6: c53a sw a4,136(sp) - 14c8: c336 sw a3,132(sp) - 14ca: c73e sw a5,140(sp) - 14cc: d882 sw zero,112(sp) - 14ce: da82 sw zero,116(sp) - 14d0: dc82 sw zero,120(sp) - 14d2: de82 sw zero,124(sp) - 14d4: 00000097 auipc ra,0x0 - 14d8: 000080e7 jalr ra # 14d4 <.LVL210+0x1e> - -000014dc <.LVL211>: - 14dc: 47ca lw a5,144(sp) - 14de: 1110 add a2,sp,160 - 14e0: 190c add a1,sp,176 - 14e2: c2be sw a5,68(sp) - -000014e4 <.LVL212>: - 14e4: 47da lw a5,148(sp) - 14e6: 0188 add a0,sp,192 - 14e8: c4be sw a5,72(sp) - 14ea: 47ea lw a5,152(sp) - 14ec: c6be sw a5,76(sp) - 14ee: 47fa lw a5,156(sp) - 14f0: c8be sw a5,80(sp) - -000014f2 <.LVL213>: - 14f2: 47b2 lw a5,12(sp) - -000014f4 <.LVL214>: - 14f4: d93e sw a5,176(sp) - 14f6: 47c2 lw a5,16(sp) - 14f8: db3e sw a5,180(sp) - 14fa: 47d2 lw a5,20(sp) - 14fc: dd3e sw a5,184(sp) - 14fe: 57c2 lw a5,48(sp) - 1500: df3e sw a5,188(sp) - 1502: 47d6 lw a5,84(sp) - 1504: d13e sw a5,160(sp) - 1506: 47e6 lw a5,88(sp) - 1508: d33e sw a5,164(sp) - 150a: 47f6 lw a5,92(sp) - 150c: d53e sw a5,168(sp) - 150e: 5782 lw a5,32(sp) - 1510: d73e sw a5,172(sp) - 1512: 00000097 auipc ra,0x0 - 1516: 000080e7 jalr ra # 1512 <.LVL214+0x1e> - -0000151a <.LVL215>: - 151a: 4782 lw a5,0(sp) - 151c: 438e lw t2,192(sp) - 151e: 429e lw t0,196(sp) - 1520: d13e sw a5,160(sp) - 1522: 4792 lw a5,4(sp) - 1524: 432e lw t1,200(sp) - 1526: 46be lw a3,204(sp) - 1528: d33e sw a5,164(sp) - 152a: 47a2 lw a5,8(sp) - 152c: 0910 add a2,sp,144 - 152e: 110c add a1,sp,160 - 1530: d53e sw a5,168(sp) - 1532: 57d2 lw a5,52(sp) - 1534: 1908 add a0,sp,176 - 1536: d01e sw t2,32(sp) - -00001538 <.LVL216>: - 1538: d73e sw a5,172(sp) - 153a: 47e2 lw a5,24(sp) - 153c: ca16 sw t0,20(sp) - -0000153e <.LVL217>: - 153e: c81a sw t1,16(sp) - 1540: c93e sw a5,144(sp) - 1542: 47f2 lw a5,28(sp) - 1544: c636 sw a3,12(sp) - 1546: cd26 sw s1,152(sp) - 1548: cb3e sw a5,148(sp) - 154a: cf22 sw s0,156(sp) - 154c: 00000097 auipc ra,0x0 - 1550: 000080e7 jalr ra # 154c <.LVL217+0xe> - -00001554 <.LVL218>: - 1554: 55ca lw a1,176(sp) - 1556: 565a lw a2,180(sp) - 1558: 576a lw a4,184(sp) - 155a: 57fa lw a5,188(sp) - 155c: 46b2 lw a3,12(sp) - 155e: 5382 lw t2,32(sp) - 1560: 42d2 lw t0,20(sp) - 1562: 4342 lw t1,16(sp) - 1564: c12e sw a1,128(sp) - 1566: c332 sw a2,132(sp) - 1568: 090c add a1,sp,144 - 156a: 0110 add a2,sp,128 - 156c: 1108 add a0,sp,160 - 156e: cf36 sw a3,156(sp) - 1570: c53a sw a4,136(sp) - 1572: c73e sw a5,140(sp) - 1574: c91e sw t2,144(sp) - 1576: cb16 sw t0,148(sp) - 1578: cd1a sw t1,152(sp) - 157a: 00000097 auipc ra,0x0 - 157e: 000080e7 jalr ra # 157a <.LVL218+0x26> - -00001582 <.LVL219>: - 1582: 560a lw a2,160(sp) - 1584: 569a lw a3,164(sp) - 1586: 572a lw a4,168(sp) - 1588: 57ba lw a5,172(sp) - 158a: c132 sw a2,128(sp) - 158c: c336 sw a3,132(sp) - 158e: c53a sw a4,136(sp) - 1590: c73e sw a5,140(sp) - 1592: d882 sw zero,112(sp) - 1594: da82 sw zero,116(sp) - 1596: dc82 sw zero,120(sp) - 1598: de82 sw zero,124(sp) - 159a: b9b5 j 1216 <.L83> - -_bswapsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__bswapsi2>: - 0: 01851713 sll a4,a0,0x18 - 4: 01855793 srl a5,a0,0x18 - 8: 66c1 lui a3,0x10 - a: 8fd9 or a5,a5,a4 - c: f0068693 add a3,a3,-256 # ff00 <.LASF5+0xfd71> - 10: 00855713 srl a4,a0,0x8 - 14: 8f75 and a4,a4,a3 - 16: 8fd9 or a5,a5,a4 - 18: 0522 sll a0,a0,0x8 - -0000001a <.LVL1>: - 1a: 00ff0737 lui a4,0xff0 - 1e: 8d79 and a0,a0,a4 - 20: 8d5d or a0,a0,a5 - 22: 8082 ret - -_bswapdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__bswapdi2>: - 0: 6341 lui t1,0x10 - 2: f0030313 add t1,t1,-256 # ff00 <.LASF6+0xfd71> - 6: 0085d713 srl a4,a1,0x8 - a: 87aa mv a5,a0 - c: 00677733 and a4,a4,t1 - 10: 0185d513 srl a0,a1,0x18 - -00000014 <.LVL1>: - 14: 00859613 sll a2,a1,0x8 - 18: 8d59 or a0,a0,a4 - 1a: 0187d713 srl a4,a5,0x18 - 1e: 8f51 or a4,a4,a2 - 20: 00ff0637 lui a2,0xff0 - 24: 8f71 and a4,a4,a2 - 26: 0187d293 srl t0,a5,0x18 - 2a: 01879693 sll a3,a5,0x18 - 2e: 8d59 or a0,a0,a4 - 30: 01859713 sll a4,a1,0x18 - 34: 00879593 sll a1,a5,0x8 - 38: 83a1 srl a5,a5,0x8 - 3a: 8fd9 or a5,a5,a4 - 3c: 0056e6b3 or a3,a3,t0 - 40: 0067f7b3 and a5,a5,t1 - 44: 8fd5 or a5,a5,a3 - 46: 8df1 and a1,a1,a2 - 48: 8d59 or a0,a0,a4 - 4a: 8ddd or a1,a1,a5 - 4c: 8082 ret - -_clrsbsi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__clrsbsi2>: - 0: 41f55793 sra a5,a0,0x1f - 4: 00f54733 xor a4,a0,a5 - -00000008 <.LVL1>: - 8: 02f50e63 beq a0,a5,44 <.L5> - -0000000c <.LBB2>: - c: 67c1 lui a5,0x10 - e: 02f75463 bge a4,a5,36 <.L3> - 12: 10072793 slti a5,a4,256 - 16: 0017c793 xor a5,a5,1 - 1a: 078e sll a5,a5,0x3 - -0000001c <.L4>: - 1c: 000006b7 lui a3,0x0 - -00000020 <.LBE3>: - 20: 457d li a0,31 - -00000022 <.LBB4>: - 22: 00f75733 srl a4,a4,a5 - -00000026 <.LBE4>: - 26: 8d1d sub a0,a0,a5 - -00000028 <.LBB5>: - 28: 00068793 mv a5,a3 - -0000002c <.LVL5>: - 2c: 97ba add a5,a5,a4 - 2e: 0007c783 lbu a5,0(a5) # 10000 <.LASF5+0xfe52> - -00000032 <.LBE5>: - 32: 8d1d sub a0,a0,a5 - 34: 8082 ret - -00000036 <.L3>: - 36: 010006b7 lui a3,0x1000 - 3a: 47e1 li a5,24 - 3c: fed750e3 bge a4,a3,1c <.L4> - 40: 47c1 li a5,16 - 42: bfe9 j 1c <.L4> - -00000044 <.L5>: - 44: 457d li a0,31 - 46: 8082 ret - -_clrsbdi2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__clrsbdi2>: - 0: c1b9 beqz a1,46 <.L3> - 2: 57fd li a5,-1 - 4: fff54513 not a0,a0 - -00000008 <.LVL1>: - 8: 02f58f63 beq a1,a5,46 <.L3> - c: 41f5d513 sra a0,a1,0x1f - 10: 8d2d xor a0,a0,a1 - 12: 4681 li a3,0 - -00000014 <.L5>: - 14: 67c1 lui a5,0x10 - 16: 02f57e63 bgeu a0,a5,52 <.L7> - 1a: 10053713 sltiu a4,a0,256 - 1e: 00174713 xor a4,a4,1 - 22: 070e sll a4,a4,0x3 - -00000024 <.L8>: - 24: 02000793 li a5,32 - 28: 00000637 lui a2,0x0 - 2c: 00e55533 srl a0,a0,a4 - -00000030 <.LVL4>: - 30: 8f99 sub a5,a5,a4 - 32: 00060713 mv a4,a2 - -00000036 <.LVL5>: - 36: 972a add a4,a4,a0 - 38: 00074703 lbu a4,0(a4) - 3c: 40e78533 sub a0,a5,a4 - -00000040 <.L6>: - 40: 9536 add a0,a0,a3 - -00000042 <.LVL7>: - 42: 157d add a0,a0,-1 - 44: 8082 ret - -00000046 <.L3>: - 46: 02000693 li a3,32 - 4a: f569 bnez a0,14 <.L5> - 4c: 02000513 li a0,32 - -00000050 <.LVL9>: - 50: bfc5 j 40 <.L6> - -00000052 <.L7>: - 52: 010007b7 lui a5,0x1000 - 56: 4741 li a4,16 - 58: fcf566e3 bltu a0,a5,24 <.L8> - 5c: 4761 li a4,24 - 5e: b7d9 j 24 <.L8> - -_fixunsxfsi.o: file format elf32-littleriscv - - -_fixxfdi.o: file format elf32-littleriscv - - -_fixunsxfdi.o: file format elf32-littleriscv - - -_floatdixf.o: file format elf32-littleriscv - - -_floatundixf.o: file format elf32-littleriscv - - -_eprintf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__eprintf>: - 0: 1151 add sp,sp,-12 - 2: c222 sw s0,4(sp) - 4: 00000437 lui s0,0x0 - 8: 00042783 lw a5,0(s0) # 0 <__eprintf> - c: 8736 mv a4,a3 - e: 86b2 mv a3,a2 - -00000010 <.LVL1>: - 10: 862e mv a2,a1 - -00000012 <.LVL2>: - 12: 85aa mv a1,a0 - -00000014 <.LVL3>: - 14: 47c8 lw a0,12(a5) - -00000016 <.LVL4>: - 16: c406 sw ra,8(sp) - 18: 00000097 auipc ra,0x0 - 1c: 000080e7 jalr ra # 18 <.LVL4+0x2> - -00000020 <.LVL5>: - 20: 00042783 lw a5,0(s0) - 24: 47c8 lw a0,12(a5) - 26: 00000097 auipc ra,0x0 - 2a: 000080e7 jalr ra # 26 <.LVL5+0x6> - -0000002e <.LVL6>: - 2e: 00000097 auipc ra,0x0 - 32: 000080e7 jalr ra # 2e <.LVL6> - -__gcc_bcmp.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__gcc_bcmp>: - 0: 4701 li a4,0 - -00000002 <.L2>: - 2: 00e61463 bne a2,a4,a <.L4> - 6: 4501 li a0,0 - -00000008 <.LVL2>: - 8: 8082 ret - -0000000a <.L4>: - a: 00e507b3 add a5,a0,a4 - e: 0705 add a4,a4,1 - -00000010 <.LVL4>: - 10: 00e586b3 add a3,a1,a4 - 14: 0007c783 lbu a5,0(a5) - -00000018 <.LVL5>: - 18: fff6c683 lbu a3,-1(a3) - 1c: fed783e3 beq a5,a3,2 <.L2> - 20: 40d78533 sub a0,a5,a3 - -00000024 <.LVL7>: - 24: 8082 ret - -_divdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divdi3>: - 0: fcc10113 add sp,sp,-52 - 4: d806 sw ra,48(sp) - 6: d622 sw s0,44(sp) - 8: d426 sw s1,40(sp) - a: c002 sw zero,0(sp) - c: 832a mv t1,a0 - -0000000e <.LVL1>: - e: 0005db63 bgez a1,24 <.L2> - -00000012 <.LVL2>: - 12: 00a037b3 snez a5,a0 - 16: 40b005b3 neg a1,a1 - 1a: 8d9d sub a1,a1,a5 - 1c: 57fd li a5,-1 - 1e: 40a00333 neg t1,a0 - 22: c03e sw a5,0(sp) - -00000024 <.L2>: - 24: 0006dd63 bgez a3,3e <.L3> - 28: 4782 lw a5,0(sp) - 2a: 40d006b3 neg a3,a3 - -0000002e <.LVL4>: - 2e: fff7c793 not a5,a5 - 32: c03e sw a5,0(sp) - -00000034 <.LVL5>: - 34: 00c037b3 snez a5,a2 - -00000038 <.LVL6>: - 38: 8e9d sub a3,a3,a5 - 3a: 40c00633 neg a2,a2 - -0000003e <.L3>: - 3e: 82b2 mv t0,a2 - -00000040 <.LVL8>: - 40: 841a mv s0,t1 - -00000042 <.LVL9>: - 42: 84ae mv s1,a1 - 44: 30069c63 bnez a3,35c <.L4> - 48: 000006b7 lui a3,0x0 - 4c: 00068693 mv a3,a3 - 50: 10c5f763 bgeu a1,a2,15e <.L5> - -00000054 <.LBB22>: - 54: 67c1 lui a5,0x10 - 56: 0ef67d63 bgeu a2,a5,150 <.L6> - 5a: 10063793 sltiu a5,a2,256 - 5e: 0017c793 xor a5,a5,1 - 62: 078e sll a5,a5,0x3 - -00000064 <.L7>: - 64: 00f65533 srl a0,a2,a5 - 68: 96aa add a3,a3,a0 - 6a: 0006c683 lbu a3,0(a3) # 0 <__divdi3> - 6e: 02000513 li a0,32 - 72: 97b6 add a5,a5,a3 - -00000074 <.LVL13>: - 74: 40f506b3 sub a3,a0,a5 - -00000078 <.LBE22>: - 78: 00f50c63 beq a0,a5,90 <.L8> - -0000007c <.LVL15>: - 7c: 00d59733 sll a4,a1,a3 - 80: 00f357b3 srl a5,t1,a5 - 84: 00d612b3 sll t0,a2,a3 - -00000088 <.LVL16>: - 88: 00e7e4b3 or s1,a5,a4 - -0000008c <.LVL17>: - 8c: 00d31433 sll s0,t1,a3 - -00000090 <.L8>: - 90: 0102d793 srl a5,t0,0x10 - 94: c23e sw a5,4(sp) - -00000096 <.LVL19>: - 96: 4592 lw a1,4(sp) - 98: 01029793 sll a5,t0,0x10 - -0000009c <.LVL20>: - 9c: 83c1 srl a5,a5,0x10 - 9e: 8526 mv a0,s1 - a0: ca16 sw t0,20(sp) - a2: c43e sw a5,8(sp) - -000000a4 <.LVL21>: - a4: 00000097 auipc ra,0x0 - a8: 000080e7 jalr ra # a4 <.LVL21> - -000000ac <.LVL22>: - ac: 85aa mv a1,a0 - ae: c82a sw a0,16(sp) - b0: 4522 lw a0,8(sp) - -000000b2 <.LVL23>: - b2: 00000097 auipc ra,0x0 - b6: 000080e7 jalr ra # b2 <.LVL23> - -000000ba <.LVL24>: - ba: 4592 lw a1,4(sp) - bc: c62a sw a0,12(sp) - -000000be <.LVL25>: - be: 8526 mv a0,s1 - -000000c0 <.LVL26>: - c0: 00000097 auipc ra,0x0 - c4: 000080e7 jalr ra # c0 <.LVL26> - -000000c8 <.LVL27>: - c8: 4642 lw a2,16(sp) - ca: 46b2 lw a3,12(sp) - cc: 0542 sll a0,a0,0x10 - ce: 01045713 srl a4,s0,0x10 - d2: 8f49 or a4,a4,a0 - -000000d4 <.LVL28>: - d4: 42d2 lw t0,20(sp) - d6: 84b2 mv s1,a2 - -000000d8 <.LVL29>: - d8: 00d77c63 bgeu a4,a3,f0 <.L9> - dc: 9716 add a4,a4,t0 - -000000de <.LVL30>: - de: fff60493 add s1,a2,-1 - -000000e2 <.LVL31>: - e2: 00576763 bltu a4,t0,f0 <.L9> - e6: 00d77563 bgeu a4,a3,f0 <.L9> - ea: ffe60493 add s1,a2,-2 - ee: 9716 add a4,a4,t0 - -000000f0 <.L9>: - f0: 4592 lw a1,4(sp) - f2: 40d707b3 sub a5,a4,a3 - f6: 853e mv a0,a5 - f8: ca16 sw t0,20(sp) - -000000fa <.LVL34>: - fa: c63e sw a5,12(sp) - -000000fc <.LVL35>: - fc: 00000097 auipc ra,0x0 - 100: 000080e7 jalr ra # fc <.LVL35> - -00000104 <.LVL36>: - 104: 85aa mv a1,a0 - 106: c82a sw a0,16(sp) - 108: 4522 lw a0,8(sp) - -0000010a <.LVL37>: - 10a: 0442 sll s0,s0,0x10 - -0000010c <.LVL38>: - 10c: 8041 srl s0,s0,0x10 - 10e: 00000097 auipc ra,0x0 - 112: 000080e7 jalr ra # 10e <.LVL38+0x2> - -00000116 <.LVL39>: - 116: c42a sw a0,8(sp) - -00000118 <.LVL40>: - 118: 4592 lw a1,4(sp) - 11a: 4532 lw a0,12(sp) - -0000011c <.LVL41>: - 11c: 00000097 auipc ra,0x0 - 120: 000080e7 jalr ra # 11c <.LVL41> - -00000124 <.LVL42>: - 124: 4742 lw a4,16(sp) - 126: 46a2 lw a3,8(sp) - 128: 0542 sll a0,a0,0x10 - 12a: 8c49 or s0,s0,a0 - -0000012c <.LVL43>: - 12c: 863a mv a2,a4 - 12e: 00d47c63 bgeu s0,a3,146 <.L12> - 132: 42d2 lw t0,20(sp) - 134: fff70613 add a2,a4,-1 - -00000138 <.LVL44>: - 138: 9416 add s0,s0,t0 - -0000013a <.LVL45>: - 13a: 00546663 bltu s0,t0,146 <.L12> - -0000013e <.LVL46>: - 13e: 00d47463 bgeu s0,a3,146 <.L12> - 142: ffe70613 add a2,a4,-2 - -00000146 <.L12>: - 146: 01049793 sll a5,s1,0x10 - 14a: 8fd1 or a5,a5,a2 - -0000014c <.L59>: - 14c: 4481 li s1,0 - 14e: a211 j 252 <.L15> - -00000150 <.L6>: - 150: 01000537 lui a0,0x1000 - -00000154 <.LVL50>: - 154: 47c1 li a5,16 - 156: f0a667e3 bltu a2,a0,64 <.L7> - 15a: 47e1 li a5,24 - 15c: b721 j 64 <.L7> - -0000015e <.L5>: - 15e: 4781 li a5,0 - -00000160 <.LBE37>: - 160: ca09 beqz a2,172 <.L16> - -00000162 <.LBB38>: - 162: 67c1 lui a5,0x10 - 164: 10f67863 bgeu a2,a5,274 <.L17> - -00000168 <.LVL53>: - 168: 10063793 sltiu a5,a2,256 - 16c: 0017c793 xor a5,a5,1 - 170: 078e sll a5,a5,0x3 - -00000172 <.L16>: - 172: 00f65733 srl a4,a2,a5 - 176: 9736 add a4,a4,a3 - 178: 00074703 lbu a4,0(a4) - 17c: 02000693 li a3,32 - 180: 97ba add a5,a5,a4 - -00000182 <.LVL55>: - 182: 40f68733 sub a4,a3,a5 - -00000186 <.LBE38>: - 186: 0ef69e63 bne a3,a5,282 <.L18> - 18a: 40c58633 sub a2,a1,a2 - -0000018e <.LVL57>: - 18e: 4485 li s1,1 - -00000190 <.L19>: - 190: 0102d793 srl a5,t0,0x10 - 194: c23e sw a5,4(sp) - -00000196 <.LVL59>: - 196: 4592 lw a1,4(sp) - 198: 01029793 sll a5,t0,0x10 - -0000019c <.LVL60>: - 19c: 83c1 srl a5,a5,0x10 - 19e: 8532 mv a0,a2 - 1a0: cc16 sw t0,24(sp) - 1a2: c43e sw a5,8(sp) - -000001a4 <.LVL61>: - 1a4: ca32 sw a2,20(sp) - 1a6: 00000097 auipc ra,0x0 - 1aa: 000080e7 jalr ra # 1a6 <.LVL61+0x2> - -000001ae <.LVL62>: - 1ae: 85aa mv a1,a0 - 1b0: c82a sw a0,16(sp) - 1b2: 4522 lw a0,8(sp) - -000001b4 <.LVL63>: - 1b4: 00000097 auipc ra,0x0 - 1b8: 000080e7 jalr ra # 1b4 <.LVL63> - -000001bc <.LVL64>: - 1bc: 4652 lw a2,20(sp) - 1be: 4592 lw a1,4(sp) - 1c0: c62a sw a0,12(sp) - -000001c2 <.LVL65>: - 1c2: 8532 mv a0,a2 - -000001c4 <.LVL66>: - 1c4: 00000097 auipc ra,0x0 - 1c8: 000080e7 jalr ra # 1c4 <.LVL66> - -000001cc <.LVL67>: - 1cc: 43c2 lw t2,16(sp) - 1ce: 4332 lw t1,12(sp) - 1d0: 0542 sll a0,a0,0x10 - 1d2: 01045693 srl a3,s0,0x10 - 1d6: 8ec9 or a3,a3,a0 - -000001d8 <.LVL68>: - 1d8: 42e2 lw t0,24(sp) - 1da: 879e mv a5,t2 - 1dc: 0066fc63 bgeu a3,t1,1f4 <.L26> - 1e0: 9696 add a3,a3,t0 - -000001e2 <.LVL69>: - 1e2: fff38793 add a5,t2,-1 - -000001e6 <.LVL70>: - 1e6: 0056e763 bltu a3,t0,1f4 <.L26> - 1ea: 0066f563 bgeu a3,t1,1f4 <.L26> - 1ee: ffe38793 add a5,t2,-2 - 1f2: 9696 add a3,a3,t0 - -000001f4 <.L26>: - 1f4: 4592 lw a1,4(sp) - 1f6: cc3e sw a5,24(sp) - -000001f8 <.LVL73>: - 1f8: 406687b3 sub a5,a3,t1 - -000001fc <.LVL74>: - 1fc: 853e mv a0,a5 - 1fe: c63e sw a5,12(sp) - -00000200 <.LVL75>: - 200: ca16 sw t0,20(sp) - -00000202 <.LVL76>: - 202: 00000097 auipc ra,0x0 - 206: 000080e7 jalr ra # 202 <.LVL76> - -0000020a <.LVL77>: - 20a: 85aa mv a1,a0 - 20c: c82a sw a0,16(sp) - 20e: 4522 lw a0,8(sp) - -00000210 <.LVL78>: - 210: 0442 sll s0,s0,0x10 - -00000212 <.LVL79>: - 212: 8041 srl s0,s0,0x10 - 214: 00000097 auipc ra,0x0 - 218: 000080e7 jalr ra # 214 <.LVL79+0x2> - -0000021c <.LVL80>: - 21c: 4592 lw a1,4(sp) - 21e: c42a sw a0,8(sp) - -00000220 <.LVL81>: - 220: 4532 lw a0,12(sp) - -00000222 <.LVL82>: - 222: 00000097 auipc ra,0x0 - 226: 000080e7 jalr ra # 222 <.LVL82> - -0000022a <.LVL83>: - 22a: 46c2 lw a3,16(sp) - 22c: 4622 lw a2,8(sp) - 22e: 0542 sll a0,a0,0x10 - 230: 8c49 or s0,s0,a0 - -00000232 <.LVL84>: - 232: 47e2 lw a5,24(sp) - 234: 85b6 mv a1,a3 - 236: 00c47c63 bgeu s0,a2,24e <.L29> - 23a: 42d2 lw t0,20(sp) - 23c: fff68593 add a1,a3,-1 - -00000240 <.LVL85>: - 240: 9416 add s0,s0,t0 - -00000242 <.LVL86>: - 242: 00546663 bltu s0,t0,24e <.L29> - -00000246 <.LVL87>: - 246: 00c47463 bgeu s0,a2,24e <.L29> - 24a: ffe68593 add a1,a3,-2 - -0000024e <.L29>: - 24e: 07c2 sll a5,a5,0x10 - 250: 8fcd or a5,a5,a1 - -00000252 <.L15>: - 252: 853e mv a0,a5 - -00000254 <.LBE20>: - 254: 4782 lw a5,0(sp) - -00000256 <.LBB46>: - 256: 85a6 mv a1,s1 - -00000258 <.LBE46>: - 258: cb81 beqz a5,268 <.L1> - 25a: 00a037b3 snez a5,a0 - 25e: 409005b3 neg a1,s1 - 262: 8d9d sub a1,a1,a5 - 264: 40a00533 neg a0,a0 - -00000268 <.L1>: - 268: 50c2 lw ra,48(sp) - 26a: 5432 lw s0,44(sp) - 26c: 54a2 lw s1,40(sp) - 26e: 03410113 add sp,sp,52 - -00000272 <.LVL93>: - 272: 8082 ret - -00000274 <.L17>: - 274: 01000737 lui a4,0x1000 - 278: 47c1 li a5,16 - 27a: eee66ce3 bltu a2,a4,172 <.L16> - 27e: 47e1 li a5,24 - 280: bdcd j 172 <.L16> - -00000282 <.L18>: - 282: 00f5d4b3 srl s1,a1,a5 - 286: 00e595b3 sll a1,a1,a4 - 28a: 00f357b3 srl a5,t1,a5 - -0000028e <.LVL96>: - 28e: 00e612b3 sll t0,a2,a4 - -00000292 <.LVL97>: - 292: 8fcd or a5,a5,a1 - 294: c43e sw a5,8(sp) - -00000296 <.LBB41>: - 296: 0102d793 srl a5,t0,0x10 - -0000029a <.LVL99>: - 29a: c23e sw a5,4(sp) - 29c: 4592 lw a1,4(sp) - 29e: 01029793 sll a5,t0,0x10 - 2a2: 83c1 srl a5,a5,0x10 - 2a4: 8526 mv a0,s1 - -000002a6 <.LVL100>: - 2a6: cc16 sw t0,24(sp) - 2a8: c63e sw a5,12(sp) - -000002aa <.LBE41>: - 2aa: 00e31433 sll s0,t1,a4 - -000002ae <.LBB42>: - 2ae: 00000097 auipc ra,0x0 - 2b2: 000080e7 jalr ra # 2ae <.LBB42> - -000002b6 <.LVL102>: - 2b6: 85aa mv a1,a0 - 2b8: ca2a sw a0,20(sp) - 2ba: 4532 lw a0,12(sp) - -000002bc <.LVL103>: - 2bc: 00000097 auipc ra,0x0 - 2c0: 000080e7 jalr ra # 2bc <.LVL103> - -000002c4 <.LVL104>: - 2c4: 4592 lw a1,4(sp) - 2c6: c82a sw a0,16(sp) - -000002c8 <.LVL105>: - 2c8: 8526 mv a0,s1 - -000002ca <.LVL106>: - 2ca: 00000097 auipc ra,0x0 - 2ce: 000080e7 jalr ra # 2ca <.LVL106> - -000002d2 <.LVL107>: - 2d2: 47a2 lw a5,8(sp) - 2d4: 4652 lw a2,20(sp) - 2d6: 46c2 lw a3,16(sp) - 2d8: 0542 sll a0,a0,0x10 - 2da: 83c1 srl a5,a5,0x10 - 2dc: 8fc9 or a5,a5,a0 - -000002de <.LVL108>: - 2de: 42e2 lw t0,24(sp) - 2e0: 84b2 mv s1,a2 - -000002e2 <.LVL109>: - 2e2: 00d7fc63 bgeu a5,a3,2fa <.L20> - 2e6: 9796 add a5,a5,t0 - -000002e8 <.LVL110>: - 2e8: fff60493 add s1,a2,-1 - -000002ec <.LVL111>: - 2ec: 0057e763 bltu a5,t0,2fa <.L20> - 2f0: 00d7f563 bgeu a5,a3,2fa <.L20> - 2f4: ffe60493 add s1,a2,-2 - 2f8: 9796 add a5,a5,t0 - -000002fa <.L20>: - 2fa: 4592 lw a1,4(sp) - 2fc: 8f95 sub a5,a5,a3 - -000002fe <.LVL114>: - 2fe: 853e mv a0,a5 - 300: cc16 sw t0,24(sp) - -00000302 <.LVL115>: - 302: c83e sw a5,16(sp) - -00000304 <.LVL116>: - 304: 00000097 auipc ra,0x0 - 308: 000080e7 jalr ra # 304 <.LVL116> - -0000030c <.LVL117>: - 30c: 85aa mv a1,a0 - 30e: ca2a sw a0,20(sp) - 310: 4532 lw a0,12(sp) - -00000312 <.LVL118>: - 312: 00000097 auipc ra,0x0 - 316: 000080e7 jalr ra # 312 <.LVL118> - -0000031a <.LVL119>: - 31a: 4592 lw a1,4(sp) - 31c: c62a sw a0,12(sp) - -0000031e <.LVL120>: - 31e: 4542 lw a0,16(sp) - -00000320 <.LVL121>: - 320: 00000097 auipc ra,0x0 - 324: 000080e7 jalr ra # 320 <.LVL121> - -00000328 <.LVL122>: - 328: 00815603 lhu a2,8(sp) - 32c: 46d2 lw a3,20(sp) - 32e: 47b2 lw a5,12(sp) - 330: 0542 sll a0,a0,0x10 - 332: 8e49 or a2,a2,a0 - -00000334 <.LVL123>: - 334: 42e2 lw t0,24(sp) - 336: 85b6 mv a1,a3 - 338: 00f67c63 bgeu a2,a5,350 <.L23> - -0000033c <.LVL124>: - 33c: 9616 add a2,a2,t0 - -0000033e <.LVL125>: - 33e: fff68593 add a1,a3,-1 - -00000342 <.LVL126>: - 342: 00566763 bltu a2,t0,350 <.L23> - 346: 00f67563 bgeu a2,a5,350 <.L23> - 34a: ffe68593 add a1,a3,-2 - 34e: 9616 add a2,a2,t0 - -00000350 <.L23>: - 350: 01049713 sll a4,s1,0x10 - 354: 8e1d sub a2,a2,a5 - 356: 00b764b3 or s1,a4,a1 - -0000035a <.LVL130>: - 35a: bd1d j 190 <.L19> - -0000035c <.L4>: - 35c: 1cd5e663 bltu a1,a3,528 <.L54> - -00000360 <.LBB43>: - 360: 67c1 lui a5,0x10 - 362: 02f6ff63 bgeu a3,a5,3a0 <.L32> - 366: 1006b793 sltiu a5,a3,256 - 36a: 0017c793 xor a5,a5,1 - 36e: 078e sll a5,a5,0x3 - -00000370 <.L33>: - 370: 00000737 lui a4,0x0 - 374: 00f6d533 srl a0,a3,a5 - -00000378 <.LVL134>: - 378: 00070713 mv a4,a4 - 37c: 972a add a4,a4,a0 - 37e: 00074503 lbu a0,0(a4) # 0 <__divdi3> - 382: 953e add a0,a0,a5 - 384: 02000793 li a5,32 - -00000388 <.LVL135>: - 388: 40a784b3 sub s1,a5,a0 - -0000038c <.LBE43>: - 38c: 02a79163 bne a5,a0,3ae <.L34> - 390: 4785 li a5,1 - 392: ecb6e0e3 bltu a3,a1,252 <.L15> - 396: 00c33633 sltu a2,t1,a2 - 39a: 00164793 xor a5,a2,1 - 39e: bd55 j 252 <.L15> - -000003a0 <.L32>: - 3a0: 01000737 lui a4,0x1000 - 3a4: 47c1 li a5,16 - 3a6: fce6e5e3 bltu a3,a4,370 <.L33> - 3aa: 47e1 li a5,24 - 3ac: b7d1 j 370 <.L33> - -000003ae <.L34>: - 3ae: 009697b3 sll a5,a3,s1 - 3b2: 00a656b3 srl a3,a2,a0 - -000003b6 <.LVL139>: - 3b6: 8edd or a3,a3,a5 - -000003b8 <.LVL140>: - 3b8: 00a5d433 srl s0,a1,a0 - 3bc: 009617b3 sll a5,a2,s1 - 3c0: 00a35533 srl a0,t1,a0 - -000003c4 <.LVL141>: - 3c4: 009595b3 sll a1,a1,s1 - 3c8: c43e sw a5,8(sp) - -000003ca <.LVL142>: - 3ca: 00b567b3 or a5,a0,a1 - -000003ce <.LVL143>: - 3ce: c63e sw a5,12(sp) - -000003d0 <.LBB25>: - 3d0: 0106d793 srl a5,a3,0x10 - -000003d4 <.LVL145>: - 3d4: c23e sw a5,4(sp) - -000003d6 <.LVL146>: - 3d6: 4592 lw a1,4(sp) - 3d8: 01069793 sll a5,a3,0x10 - -000003dc <.LVL147>: - 3dc: 83c1 srl a5,a5,0x10 - 3de: 8522 mv a0,s0 - -000003e0 <.LBE25>: - 3e0: d01a sw t1,32(sp) - -000003e2 <.LBB26>: - 3e2: ce36 sw a3,28(sp) - 3e4: c83e sw a5,16(sp) - -000003e6 <.LVL149>: - 3e6: 00000097 auipc ra,0x0 - 3ea: 000080e7 jalr ra # 3e6 <.LVL149> - -000003ee <.LVL150>: - 3ee: 85aa mv a1,a0 - 3f0: cc2a sw a0,24(sp) - 3f2: 4542 lw a0,16(sp) - -000003f4 <.LVL151>: - 3f4: 00000097 auipc ra,0x0 - 3f8: 000080e7 jalr ra # 3f4 <.LVL151> - -000003fc <.LVL152>: - 3fc: 4592 lw a1,4(sp) - 3fe: ca2a sw a0,20(sp) - -00000400 <.LVL153>: - 400: 8522 mv a0,s0 - -00000402 <.LVL154>: - 402: 00000097 auipc ra,0x0 - 406: 000080e7 jalr ra # 402 <.LVL154> - -0000040a <.LVL155>: - 40a: 47b2 lw a5,12(sp) - 40c: 42e2 lw t0,24(sp) - 40e: 4652 lw a2,20(sp) - 410: 0107d413 srl s0,a5,0x10 - -00000414 <.LVL156>: - 414: 0542 sll a0,a0,0x10 - 416: 8c49 or s0,s0,a0 - -00000418 <.LVL157>: - 418: 46f2 lw a3,28(sp) - 41a: 5302 lw t1,32(sp) - 41c: 8796 mv a5,t0 - 41e: 00c47c63 bgeu s0,a2,436 <.L35> - 422: 9436 add s0,s0,a3 - -00000424 <.LVL158>: - 424: fff28793 add a5,t0,-1 - -00000428 <.LVL159>: - 428: 00d46763 bltu s0,a3,436 <.L35> - 42c: 00c47563 bgeu s0,a2,436 <.L35> - 430: ffe28793 add a5,t0,-2 - 434: 9436 add s0,s0,a3 - -00000436 <.L35>: - 436: 4592 lw a1,4(sp) - 438: d03e sw a5,32(sp) - 43a: 40c407b3 sub a5,s0,a2 - -0000043e <.LVL162>: - 43e: 853e mv a0,a5 - 440: d21a sw t1,36(sp) - 442: ca3e sw a5,20(sp) - -00000444 <.LVL163>: - 444: ce36 sw a3,28(sp) - -00000446 <.LVL164>: - 446: 00000097 auipc ra,0x0 - 44a: 000080e7 jalr ra # 446 <.LVL164> - -0000044e <.LVL165>: - 44e: 85aa mv a1,a0 - 450: cc2a sw a0,24(sp) - 452: 4542 lw a0,16(sp) - -00000454 <.LVL166>: - 454: 00000097 auipc ra,0x0 - 458: 000080e7 jalr ra # 454 <.LVL166> - -0000045c <.LVL167>: - 45c: 4592 lw a1,4(sp) - 45e: 842a mv s0,a0 - -00000460 <.LVL168>: - 460: 4552 lw a0,20(sp) - 462: 00000097 auipc ra,0x0 - 466: 000080e7 jalr ra # 462 <.LVL168+0x2> - -0000046a <.LVL169>: - 46a: 00c15603 lhu a2,12(sp) - 46e: 43e2 lw t2,24(sp) - 470: 0542 sll a0,a0,0x10 - 472: 8e49 or a2,a2,a0 - -00000474 <.LVL170>: - 474: 5782 lw a5,32(sp) - 476: 5312 lw t1,36(sp) - 478: 859e mv a1,t2 - 47a: 00867d63 bgeu a2,s0,494 <.L38> - 47e: 46f2 lw a3,28(sp) - 480: fff38593 add a1,t2,-1 - -00000484 <.LVL171>: - 484: 9636 add a2,a2,a3 - 486: 00d66763 bltu a2,a3,494 <.L38> - -0000048a <.LVL173>: - 48a: 00867563 bgeu a2,s0,494 <.L38> - 48e: ffe38593 add a1,t2,-2 - 492: 9636 add a2,a2,a3 - -00000494 <.L38>: - 494: 40860733 sub a4,a2,s0 - -00000498 <.LBB27>: - 498: 4622 lw a2,8(sp) - 49a: 66c1 lui a3,0x10 - -0000049c <.LBB32>: - 49c: 07c2 sll a5,a5,0x10 - 49e: 8fcd or a5,a5,a1 - -000004a0 <.LBB33>: - 4a0: fff68293 add t0,a3,-1 # ffff <.LLST68+0xf2ae> - 4a4: 0057f433 and s0,a5,t0 - -000004a8 <.LVL178>: - 4a8: 005672b3 and t0,a2,t0 - -000004ac <.LVL179>: - 4ac: 8241 srl a2,a2,0x10 - 4ae: c232 sw a2,4(sp) - -000004b0 <.LBB28>: - 4b0: 8522 mv a0,s0 - 4b2: 8596 mv a1,t0 - -000004b4 <.LVL181>: - 4b4: 00000097 auipc ra,0x0 - 4b8: 000080e7 jalr ra # 4b4 <.LVL181> - -000004bc <.LVL182>: - 4bc: 83aa mv t2,a0 - -000004be <.LBB29>: - 4be: 4592 lw a1,4(sp) - 4c0: 8522 mv a0,s0 - 4c2: 00000097 auipc ra,0x0 - 4c6: 000080e7 jalr ra # 4c2 <.LBB29+0x4> - 4ca: 842a mv s0,a0 - -000004cc <.LBB30>: - 4cc: 8596 mv a1,t0 - 4ce: 0107d513 srl a0,a5,0x10 - -000004d2 <.LVL185>: - 4d2: 00000097 auipc ra,0x0 - 4d6: 000080e7 jalr ra # 4d2 <.LVL185> - -000004da <.LVL186>: - 4da: 82aa mv t0,a0 - -000004dc <.LBB31>: - 4dc: 4592 lw a1,4(sp) - 4de: 0107d513 srl a0,a5,0x10 - -000004e2 <.LVL188>: - 4e2: 00000097 auipc ra,0x0 - 4e6: 000080e7 jalr ra # 4e2 <.LVL188> - -000004ea <.LBE31>: - 4ea: 0103d613 srl a2,t2,0x10 - 4ee: 005406b3 add a3,s0,t0 - 4f2: 00d60433 add s0,a2,a3 - -000004f6 <.LVL190>: - 4f6: 00547463 bgeu s0,t0,4fe <.L41> - 4fa: 66c1 lui a3,0x10 - -000004fc <.LVL191>: - 4fc: 9536 add a0,a0,a3 - -000004fe <.L41>: - 4fe: 01045693 srl a3,s0,0x10 - 502: 9536 add a0,a0,a3 - -00000504 <.LBE33>: - 504: 02a76063 bltu a4,a0,524 <.L42> - 508: c4a712e3 bne a4,a0,14c <.L59> - -0000050c <.LBB34>: - 50c: 6741 lui a4,0x10 - -0000050e <.LVL194>: - 50e: 177d add a4,a4,-1 # ffff <.LLST68+0xf2ae> - -00000510 <.LVL195>: - 510: 8c79 and s0,s0,a4 - -00000512 <.LVL196>: - 512: 0442 sll s0,s0,0x10 - 514: 00e3f733 and a4,t2,a4 - -00000518 <.LBE34>: - 518: 00931333 sll t1,t1,s1 - -0000051c <.LBB35>: - 51c: 943a add s0,s0,a4 - -0000051e <.LBE35>: - 51e: 4481 li s1,0 - -00000520 <.LVL198>: - 520: d28379e3 bgeu t1,s0,252 <.L15> - -00000524 <.L42>: - 524: 17fd add a5,a5,-1 # ffff <.LLST68+0xf2ae> - -00000526 <.LBE45>: - 526: b11d j 14c <.L59> - -00000528 <.L54>: - 528: 4481 li s1,0 - 52a: 4781 li a5,0 - 52c: b31d j 252 <.L15> - -_moddi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__moddi3>: - 0: fc810113 add sp,sp,-56 - 4: da06 sw ra,52(sp) - 6: d822 sw s0,48(sp) - 8: d626 sw s1,44(sp) - a: c802 sw zero,16(sp) - c: 0005db63 bgez a1,22 <.L2> - -00000010 <.LVL1>: - 10: 00a037b3 snez a5,a0 - 14: 40b005b3 neg a1,a1 - 18: 8d9d sub a1,a1,a5 - 1a: 57fd li a5,-1 - 1c: 40a00533 neg a0,a0 - -00000020 <.LVL2>: - 20: c83e sw a5,16(sp) - -00000022 <.L2>: - 22: 0006d963 bgez a3,34 <.L3> - -00000026 <.LVL4>: - 26: 00c037b3 snez a5,a2 - 2a: 40d006b3 neg a3,a3 - 2e: 8e9d sub a3,a3,a5 - 30: 40c00633 neg a2,a2 - -00000034 <.L3>: - 34: 84b2 mv s1,a2 - -00000036 <.LVL8>: - 36: 842a mv s0,a0 - -00000038 <.LVL9>: - 38: 872e mv a4,a1 - 3a: 24069a63 bnez a3,28e <.L4> - -0000003e <.LVL11>: - 3e: 000006b7 lui a3,0x0 - -00000042 <.LVL12>: - 42: 00068313 mv t1,a3 - 46: 10c5fa63 bgeu a1,a2,15a <.L5> - -0000004a <.LBB22>: - 4a: 66c1 lui a3,0x10 - 4c: 10d67063 bgeu a2,a3,14c <.L6> - 50: 10063693 sltiu a3,a2,256 - 54: 0016c693 xor a3,a3,1 - 58: 068e sll a3,a3,0x3 - -0000005a <.L7>: - 5a: 00d652b3 srl t0,a2,a3 - 5e: 9316 add t1,t1,t0 - 60: 00034303 lbu t1,0(t1) - 64: 969a add a3,a3,t1 - -00000066 <.LVL15>: - 66: 02000313 li t1,32 - 6a: 40d307b3 sub a5,t1,a3 - 6e: c03e sw a5,0(sp) - -00000070 <.LBE22>: - 70: 00d30b63 beq t1,a3,86 <.L8> - 74: 00f59733 sll a4,a1,a5 - 78: 00d556b3 srl a3,a0,a3 - 7c: 00f614b3 sll s1,a2,a5 - -00000080 <.LVL17>: - 80: 8f55 or a4,a4,a3 - -00000082 <.LVL18>: - 82: 00f51433 sll s0,a0,a5 - -00000086 <.L8>: - 86: 01049793 sll a5,s1,0x10 - -0000008a <.LVL20>: - 8a: 83c1 srl a5,a5,0x10 - 8c: 853a mv a0,a4 - 8e: 0104d593 srl a1,s1,0x10 - 92: c43a sw a4,8(sp) - 94: c23e sw a5,4(sp) - -00000096 <.LVL21>: - 96: 00000097 auipc ra,0x0 - 9a: 000080e7 jalr ra # 96 <.LVL21> - -0000009e <.LVL22>: - 9e: 01049593 sll a1,s1,0x10 - a2: 81c1 srl a1,a1,0x10 - a4: 00000097 auipc ra,0x0 - a8: 000080e7 jalr ra # a4 <.LVL22+0x6> - -000000ac <.LVL23>: - ac: 4722 lw a4,8(sp) - ae: c22a sw a0,4(sp) - -000000b0 <.LVL24>: - b0: 0104d593 srl a1,s1,0x10 - b4: 853a mv a0,a4 - -000000b6 <.L82>: - b6: 00000097 auipc ra,0x0 - ba: 000080e7 jalr ra # b6 <.L82> - -000000be <.LVL26>: - be: 4692 lw a3,4(sp) - c0: 0542 sll a0,a0,0x10 - c2: 01045713 srl a4,s0,0x10 - c6: 8f49 or a4,a4,a0 - -000000c8 <.LVL27>: - c8: 00d77863 bgeu a4,a3,d8 <.L26> - cc: 9726 add a4,a4,s1 - ce: 00976563 bltu a4,s1,d8 <.L26> - d2: 00d77363 bgeu a4,a3,d8 <.L26> - d6: 9726 add a4,a4,s1 - -000000d8 <.L26>: - d8: 40d707b3 sub a5,a4,a3 - dc: 853e mv a0,a5 - de: 0104d593 srl a1,s1,0x10 - e2: c23e sw a5,4(sp) - -000000e4 <.LVL31>: - e4: 00000097 auipc ra,0x0 - e8: 000080e7 jalr ra # e4 <.LVL31> - -000000ec <.LVL32>: - ec: 01049593 sll a1,s1,0x10 - f0: 81c1 srl a1,a1,0x10 - f2: 00000097 auipc ra,0x0 - f6: 000080e7 jalr ra # f2 <.LVL32+0x6> - -000000fa <.LVL33>: - fa: c42a sw a0,8(sp) - -000000fc <.LVL34>: - fc: 4512 lw a0,4(sp) - -000000fe <.LVL35>: - fe: 0104d593 srl a1,s1,0x10 - 102: 0442 sll s0,s0,0x10 - 104: 00000097 auipc ra,0x0 - 108: 000080e7 jalr ra # 104 <.LVL35+0x6> - -0000010c <.LVL36>: - 10c: 4722 lw a4,8(sp) - 10e: 0542 sll a0,a0,0x10 - 110: 8041 srl s0,s0,0x10 - 112: 8c49 or s0,s0,a0 - -00000114 <.LVL37>: - 114: 00e47863 bgeu s0,a4,124 <.L29> - -00000118 <.LVL38>: - 118: 9426 add s0,s0,s1 - 11a: 00946563 bltu s0,s1,124 <.L29> - 11e: 00e47363 bgeu s0,a4,124 <.L29> - -00000122 <.LVL40>: - 122: 9426 add s0,s0,s1 - -00000124 <.L29>: - 124: 4782 lw a5,0(sp) - -00000126 <.LBB25>: - 126: 8c19 sub s0,s0,a4 - -00000128 <.LBE25>: - 128: 4581 li a1,0 - 12a: 00f45533 srl a0,s0,a5 - -0000012e <.L32>: - 12e: 47c2 lw a5,16(sp) - 130: cb81 beqz a5,140 <.L1> - 132: 00a037b3 snez a5,a0 - 136: 40b005b3 neg a1,a1 - -0000013a <.LVL44>: - 13a: 8d9d sub a1,a1,a5 - 13c: 40a00533 neg a0,a0 - -00000140 <.L1>: - 140: 50d2 lw ra,52(sp) - 142: 5442 lw s0,48(sp) - 144: 54b2 lw s1,44(sp) - 146: 03810113 add sp,sp,56 - -0000014a <.LVL47>: - 14a: 8082 ret - -0000014c <.L6>: - 14c: 010002b7 lui t0,0x1000 - 150: 46c1 li a3,16 - 152: f05664e3 bltu a2,t0,5a <.L7> - 156: 46e1 li a3,24 - 158: b709 j 5a <.L7> - -0000015a <.L5>: - 15a: 4701 li a4,0 - -0000015c <.LBE27>: - 15c: ca09 beqz a2,16e <.L16> - -0000015e <.LBB28>: - 15e: 6741 lui a4,0x10 - 160: 04e67f63 bgeu a2,a4,1be <.L17> - -00000164 <.LVL51>: - 164: 10063713 sltiu a4,a2,256 - 168: 00174713 xor a4,a4,1 - 16c: 070e sll a4,a4,0x3 - -0000016e <.L16>: - 16e: 00e656b3 srl a3,a2,a4 - 172: 969a add a3,a3,t1 - 174: 0006c683 lbu a3,0(a3) # 10000 <.LLST68+0xf454> - 178: 9736 add a4,a4,a3 - -0000017a <.LVL53>: - 17a: 02000693 li a3,32 - 17e: 40e687b3 sub a5,a3,a4 - 182: c03e sw a5,0(sp) - -00000184 <.LBE28>: - 184: 04e69463 bne a3,a4,1cc <.L18> - 188: 40c58633 sub a2,a1,a2 - -0000018c <.L19>: - 18c: 01049793 sll a5,s1,0x10 - 190: 83c1 srl a5,a5,0x10 - 192: 8532 mv a0,a2 - 194: 0104d593 srl a1,s1,0x10 - 198: c432 sw a2,8(sp) - 19a: c23e sw a5,4(sp) - -0000019c <.LVL56>: - 19c: 00000097 auipc ra,0x0 - 1a0: 000080e7 jalr ra # 19c <.LVL56> - -000001a4 <.LVL57>: - 1a4: 01049593 sll a1,s1,0x10 - 1a8: 81c1 srl a1,a1,0x10 - 1aa: 00000097 auipc ra,0x0 - 1ae: 000080e7 jalr ra # 1aa <.LVL57+0x6> - -000001b2 <.LVL58>: - 1b2: 4622 lw a2,8(sp) - 1b4: c22a sw a0,4(sp) - -000001b6 <.LVL59>: - 1b6: 0104d593 srl a1,s1,0x10 - 1ba: 8532 mv a0,a2 - -000001bc <.LVL60>: - 1bc: bded j b6 <.L82> - -000001be <.L17>: - 1be: 010006b7 lui a3,0x1000 - 1c2: 4741 li a4,16 - 1c4: fad665e3 bltu a2,a3,16e <.L16> - 1c8: 4761 li a4,24 - 1ca: b755 j 16e <.L16> - -000001cc <.L18>: - 1cc: 4782 lw a5,0(sp) - -000001ce <.LVL63>: - 1ce: 00f614b3 sll s1,a2,a5 - -000001d2 <.LVL64>: - 1d2: 00e5d7b3 srl a5,a1,a4 - 1d6: c23e sw a5,4(sp) - -000001d8 <.LVL65>: - 1d8: 4782 lw a5,0(sp) - -000001da <.LVL66>: - 1da: 00e55733 srl a4,a0,a4 - -000001de <.LVL67>: - 1de: 00f595b3 sll a1,a1,a5 - 1e2: 00b767b3 or a5,a4,a1 - 1e6: c43e sw a5,8(sp) - -000001e8 <.LVL68>: - 1e8: 4782 lw a5,0(sp) - -000001ea <.LBB31>: - 1ea: 0104d593 srl a1,s1,0x10 - -000001ee <.LBE31>: - 1ee: 00f51433 sll s0,a0,a5 - -000001f2 <.LBB32>: - 1f2: 4512 lw a0,4(sp) - -000001f4 <.LVL71>: - 1f4: 01049793 sll a5,s1,0x10 - 1f8: 83c1 srl a5,a5,0x10 - 1fa: c63e sw a5,12(sp) - -000001fc <.LVL72>: - 1fc: 00000097 auipc ra,0x0 - 200: 000080e7 jalr ra # 1fc <.LVL72> - -00000204 <.LVL73>: - 204: 01049593 sll a1,s1,0x10 - 208: 81c1 srl a1,a1,0x10 - 20a: 00000097 auipc ra,0x0 - 20e: 000080e7 jalr ra # 20a <.LVL73+0x6> - -00000212 <.LVL74>: - 212: c62a sw a0,12(sp) - -00000214 <.LVL75>: - 214: 4512 lw a0,4(sp) - -00000216 <.LVL76>: - 216: 0104d593 srl a1,s1,0x10 - 21a: 00000097 auipc ra,0x0 - 21e: 000080e7 jalr ra # 21a <.LVL76+0x4> - -00000222 <.LVL77>: - 222: 47a2 lw a5,8(sp) - 224: 46b2 lw a3,12(sp) - 226: 0542 sll a0,a0,0x10 - 228: 0107d713 srl a4,a5,0x10 - 22c: 8f49 or a4,a4,a0 - -0000022e <.LVL78>: - 22e: 00d77863 bgeu a4,a3,23e <.L20> - -00000232 <.LVL79>: - 232: 9726 add a4,a4,s1 - 234: 00976563 bltu a4,s1,23e <.L20> - 238: 00d77363 bgeu a4,a3,23e <.L20> - -0000023c <.LVL81>: - 23c: 9726 add a4,a4,s1 - -0000023e <.L20>: - 23e: 40d707b3 sub a5,a4,a3 - 242: 853e mv a0,a5 - 244: 0104d593 srl a1,s1,0x10 - 248: c23e sw a5,4(sp) - -0000024a <.LVL83>: - 24a: 00000097 auipc ra,0x0 - 24e: 000080e7 jalr ra # 24a <.LVL83> - -00000252 <.LVL84>: - 252: 01049593 sll a1,s1,0x10 - 256: 81c1 srl a1,a1,0x10 - 258: 00000097 auipc ra,0x0 - 25c: 000080e7 jalr ra # 258 <.LVL84+0x6> - -00000260 <.LVL85>: - 260: c62a sw a0,12(sp) - -00000262 <.LVL86>: - 262: 4512 lw a0,4(sp) - -00000264 <.LVL87>: - 264: 0104d593 srl a1,s1,0x10 - 268: 00000097 auipc ra,0x0 - 26c: 000080e7 jalr ra # 268 <.LVL87+0x4> - -00000270 <.LVL88>: - 270: 00815603 lhu a2,8(sp) - 274: 4732 lw a4,12(sp) - 276: 0542 sll a0,a0,0x10 - 278: 8e49 or a2,a2,a0 - -0000027a <.LVL89>: - 27a: 00e67863 bgeu a2,a4,28a <.L23> - 27e: 9626 add a2,a2,s1 - 280: 00966563 bltu a2,s1,28a <.L23> - 284: 00e67363 bgeu a2,a4,28a <.L23> - 288: 9626 add a2,a2,s1 - -0000028a <.L23>: - 28a: 8e19 sub a2,a2,a4 - -0000028c <.LVL92>: - 28c: b701 j 18c <.L19> - -0000028e <.L4>: - 28e: ead5e0e3 bltu a1,a3,12e <.L32> - -00000292 <.LBB33>: - 292: 67c1 lui a5,0x10 - 294: 04f6f863 bgeu a3,a5,2e4 <.L34> - 298: 1006b793 sltiu a5,a3,256 - 29c: 0017c793 xor a5,a5,1 - 2a0: 078e sll a5,a5,0x3 - -000002a2 <.L35>: - 2a2: 00000337 lui t1,0x0 - 2a6: 00f6d2b3 srl t0,a3,a5 - 2aa: 00030313 mv t1,t1 - 2ae: 9316 add t1,t1,t0 - 2b0: 00034283 lbu t0,0(t1) # 0 <__moddi3> - 2b4: 92be add t0,t0,a5 - 2b6: 02000793 li a5,32 - -000002ba <.LVL96>: - 2ba: 405784b3 sub s1,a5,t0 - -000002be <.LVL97>: - 2be: c026 sw s1,0(sp) - -000002c0 <.LBE33>: - 2c0: 02579963 bne a5,t0,2f2 <.L36> - 2c4: 00b6e463 bltu a3,a1,2cc <.L37> - 2c8: 00c56b63 bltu a0,a2,2de <.L38> - -000002cc <.L37>: - 2cc: 40c50633 sub a2,a0,a2 - -000002d0 <.LVL100>: - 2d0: 40d586b3 sub a3,a1,a3 - -000002d4 <.LVL101>: - 2d4: 00c53733 sltu a4,a0,a2 - 2d8: 8432 mv s0,a2 - -000002da <.LVL102>: - 2da: 40e68733 sub a4,a3,a4 - -000002de <.L38>: - 2de: 8522 mv a0,s0 - 2e0: 85ba mv a1,a4 - 2e2: b5b1 j 12e <.L32> - -000002e4 <.L34>: - 2e4: 01000337 lui t1,0x1000 - 2e8: 47c1 li a5,16 - 2ea: fa66ece3 bltu a3,t1,2a2 <.L35> - 2ee: 47e1 li a5,24 - 2f0: bf4d j 2a2 <.L35> - -000002f2 <.L36>: - 2f2: 4782 lw a5,0(sp) - 2f4: 0055d4b3 srl s1,a1,t0 - -000002f8 <.LVL107>: - 2f8: 00565333 srl t1,a2,t0 - 2fc: 00f696b3 sll a3,a3,a5 - -00000300 <.LVL108>: - 300: 00f617b3 sll a5,a2,a5 - 304: c43e sw a5,8(sp) - 306: 4782 lw a5,0(sp) - 308: 00d36333 or t1,t1,a3 - -0000030c <.LVL109>: - 30c: d416 sw t0,40(sp) - 30e: 00f595b3 sll a1,a1,a5 - 312: 005557b3 srl a5,a0,t0 - 316: 8fcd or a5,a5,a1 - 318: ca3e sw a5,20(sp) - -0000031a <.LVL110>: - 31a: 4782 lw a5,0(sp) - -0000031c <.LBB37>: - 31c: d21a sw t1,36(sp) - -0000031e <.LBE37>: - 31e: 00f517b3 sll a5,a0,a5 - 322: c63e sw a5,12(sp) - -00000324 <.LBB38>: - 324: 01035793 srl a5,t1,0x10 - -00000328 <.LVL113>: - 328: c23e sw a5,4(sp) - -0000032a <.LVL114>: - 32a: 4592 lw a1,4(sp) - 32c: 01031793 sll a5,t1,0x10 - -00000330 <.LVL115>: - 330: 83c1 srl a5,a5,0x10 - 332: 8526 mv a0,s1 - 334: cc3e sw a5,24(sp) - -00000336 <.LVL116>: - 336: 00000097 auipc ra,0x0 - 33a: 000080e7 jalr ra # 336 <.LVL116> - -0000033e <.LVL117>: - 33e: 85aa mv a1,a0 - 340: d02a sw a0,32(sp) - 342: 4562 lw a0,24(sp) - -00000344 <.LVL118>: - 344: 00000097 auipc ra,0x0 - 348: 000080e7 jalr ra # 344 <.LVL118> - -0000034c <.LVL119>: - 34c: 4592 lw a1,4(sp) - 34e: ce2a sw a0,28(sp) - -00000350 <.LVL120>: - 350: 8526 mv a0,s1 - -00000352 <.LVL121>: - 352: 00000097 auipc ra,0x0 - 356: 000080e7 jalr ra # 352 <.LVL121> - -0000035a <.LVL122>: - 35a: 47d2 lw a5,20(sp) - 35c: 5682 lw a3,32(sp) - 35e: 0542 sll a0,a0,0x10 - 360: 0107d493 srl s1,a5,0x10 - -00000364 <.LVL123>: - 364: 47f2 lw a5,28(sp) - 366: 8cc9 or s1,s1,a0 - -00000368 <.LVL124>: - 368: 5312 lw t1,36(sp) - 36a: 52a2 lw t0,40(sp) - 36c: 8436 mv s0,a3 - 36e: 00f4fc63 bgeu s1,a5,386 <.L41> - -00000372 <.LVL125>: - 372: 949a add s1,s1,t1 - -00000374 <.LVL126>: - 374: fff68413 add s0,a3,-1 # ffffff <.LLST68+0xfff453> - -00000378 <.LVL127>: - 378: 0064e763 bltu s1,t1,386 <.L41> - 37c: 00f4f563 bgeu s1,a5,386 <.L41> - 380: ffe68413 add s0,a3,-2 - 384: 949a add s1,s1,t1 - -00000386 <.L41>: - 386: 4592 lw a1,4(sp) - 388: 40f487b3 sub a5,s1,a5 - 38c: 853e mv a0,a5 - 38e: d41a sw t1,40(sp) - 390: d216 sw t0,36(sp) - -00000392 <.LVL130>: - 392: ce3e sw a5,28(sp) - -00000394 <.LVL131>: - 394: 00000097 auipc ra,0x0 - 398: 000080e7 jalr ra # 394 <.LVL131> - -0000039c <.LVL132>: - 39c: 85aa mv a1,a0 - 39e: d02a sw a0,32(sp) - 3a0: 4562 lw a0,24(sp) - -000003a2 <.LVL133>: - 3a2: 00000097 auipc ra,0x0 - 3a6: 000080e7 jalr ra # 3a2 <.LVL133> - -000003aa <.LVL134>: - 3aa: 4592 lw a1,4(sp) - 3ac: 84aa mv s1,a0 - -000003ae <.LVL135>: - 3ae: 4572 lw a0,28(sp) - 3b0: 00000097 auipc ra,0x0 - 3b4: 000080e7 jalr ra # 3b0 <.LVL135+0x2> - -000003b8 <.LVL136>: - 3b8: 01415603 lhu a2,20(sp) - 3bc: 5682 lw a3,32(sp) - 3be: 0542 sll a0,a0,0x10 - 3c0: 8e49 or a2,a2,a0 - -000003c2 <.LVL137>: - 3c2: 5292 lw t0,36(sp) - 3c4: 5322 lw t1,40(sp) - 3c6: 85b6 mv a1,a3 - 3c8: 00967c63 bgeu a2,s1,3e0 <.L44> - -000003cc <.LVL138>: - 3cc: 961a add a2,a2,t1 - -000003ce <.LVL139>: - 3ce: fff68593 add a1,a3,-1 - -000003d2 <.LVL140>: - 3d2: 00666763 bltu a2,t1,3e0 <.L44> - 3d6: 00967563 bgeu a2,s1,3e0 <.L44> - 3da: ffe68593 add a1,a3,-2 - 3de: 961a add a2,a2,t1 - -000003e0 <.L44>: - 3e0: 46a2 lw a3,8(sp) - -000003e2 <.LBB44>: - 3e2: 01041713 sll a4,s0,0x10 - -000003e6 <.LBB45>: - 3e6: 67c1 lui a5,0x10 - -000003e8 <.LBB46>: - 3e8: 8f4d or a4,a4,a1 - -000003ea <.LBB47>: - 3ea: fff78413 add s0,a5,-1 # ffff <.LLST68+0xf453> - -000003ee <.LVL143>: - 3ee: 008777b3 and a5,a4,s0 - 3f2: 8c75 and s0,s0,a3 - -000003f4 <.LBB48>: - 3f4: 409603b3 sub t2,a2,s1 - -000003f8 <.LBB49>: - 3f8: 8341 srl a4,a4,0x10 - -000003fa <.LVL145>: - 3fa: 0106d493 srl s1,a3,0x10 - -000003fe <.LBB40>: - 3fe: 853e mv a0,a5 - 400: 85a2 mv a1,s0 - -00000402 <.LVL147>: - 402: 00000097 auipc ra,0x0 - 406: 000080e7 jalr ra # 402 <.LVL147> - 40a: c22a sw a0,4(sp) - -0000040c <.LBB41>: - 40c: 85a6 mv a1,s1 - 40e: 853e mv a0,a5 - -00000410 <.LVL149>: - 410: 00000097 auipc ra,0x0 - 414: 000080e7 jalr ra # 410 <.LVL149> - 418: 87aa mv a5,a0 - -0000041a <.LBB42>: - 41a: 85a2 mv a1,s0 - 41c: 853a mv a0,a4 - -0000041e <.LVL151>: - 41e: 00000097 auipc ra,0x0 - 422: 000080e7 jalr ra # 41e <.LVL151> - 426: 842a mv s0,a0 - -00000428 <.LBB43>: - 428: 85a6 mv a1,s1 - 42a: 853a mv a0,a4 - 42c: 00000097 auipc ra,0x0 - 430: 000080e7 jalr ra # 42c <.LBB43+0x4> - -00000434 <.LBE43>: - 434: 4692 lw a3,4(sp) - 436: 97a2 add a5,a5,s0 - -00000438 <.LVL154>: - 438: 0106d713 srl a4,a3,0x10 - -0000043c <.LVL155>: - 43c: 97ba add a5,a5,a4 - -0000043e <.LVL156>: - 43e: 0087f463 bgeu a5,s0,446 <.L47> - 442: 6741 lui a4,0x10 - -00000444 <.LVL157>: - 444: 953a add a0,a0,a4 - -00000446 <.L47>: - 446: 0107d713 srl a4,a5,0x10 - 44a: 953a add a0,a0,a4 - -0000044c <.LVL159>: - 44c: 6741 lui a4,0x10 - -0000044e <.LVL160>: - 44e: 177d add a4,a4,-1 # ffff <.LLST68+0xf453> - -00000450 <.LVL161>: - 450: 00e7f433 and s0,a5,a4 - -00000454 <.LVL162>: - 454: 4792 lw a5,4(sp) - -00000456 <.LVL163>: - 456: 0442 sll s0,s0,0x10 - 458: 8ff9 and a5,a5,a4 - 45a: 943e add s0,s0,a5 - -0000045c <.LBE49>: - 45c: 00a3e763 bltu t2,a0,46a <.L48> - 460: 00a39e63 bne t2,a0,47c <.L49> - 464: 47b2 lw a5,12(sp) - 466: 0087fb63 bgeu a5,s0,47c <.L49> - -0000046a <.L48>: - 46a: 47a2 lw a5,8(sp) - 46c: 40f407b3 sub a5,s0,a5 - 470: 00f43733 sltu a4,s0,a5 - -00000474 <.LVL165>: - 474: 843e mv s0,a5 - -00000476 <.LVL166>: - 476: 006707b3 add a5,a4,t1 - 47a: 8d1d sub a0,a0,a5 - -0000047c <.L49>: - 47c: 47b2 lw a5,12(sp) - 47e: 40a385b3 sub a1,t2,a0 - 482: 40878433 sub s0,a5,s0 - -00000486 <.LVL168>: - 486: 0087b7b3 sltu a5,a5,s0 - 48a: 8d9d sub a1,a1,a5 - -0000048c <.LBE51>: - 48c: 4782 lw a5,0(sp) - 48e: 005592b3 sll t0,a1,t0 - -00000492 <.LVL170>: - 492: 00f45433 srl s0,s0,a5 - -00000496 <.LVL171>: - 496: 0082e533 or a0,t0,s0 - -0000049a <.LVL172>: - 49a: 00f5d5b3 srl a1,a1,a5 - -0000049e <.LVL173>: - 49e: b941 j 12e <.L32> - -_divmoddi4.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divmoddi4>: - 0: 7139 add sp,sp,-64 - 2: de06 sw ra,60(sp) - 4: dc22 sw s0,56(sp) - 6: da26 sw s1,52(sp) - 8: d23a sw a4,36(sp) - a: c402 sw zero,8(sp) - c: 0005db63 bgez a1,22 <.L2> - -00000010 <.LVL1>: - 10: 00a037b3 snez a5,a0 - 14: 40b005b3 neg a1,a1 - 18: 8d9d sub a1,a1,a5 - 1a: 57fd li a5,-1 - 1c: 40a00533 neg a0,a0 - -00000020 <.LVL2>: - 20: c43e sw a5,8(sp) - -00000022 <.L2>: - 22: 47a2 lw a5,8(sp) - 24: ca3e sw a5,20(sp) - 26: 0006dc63 bgez a3,3e <.L3> - 2a: fff7c793 not a5,a5 - 2e: ca3e sw a5,20(sp) - -00000030 <.LVL4>: - 30: 40d006b3 neg a3,a3 - 34: 00c037b3 snez a5,a2 - -00000038 <.LVL6>: - 38: 8e9d sub a3,a3,a5 - 3a: 40c00633 neg a2,a2 - -0000003e <.L3>: - 3e: c636 sw a3,12(sp) - 40: c02a sw a0,0(sp) - 42: 84b2 mv s1,a2 - -00000044 <.LVL9>: - 44: 842e mv s0,a1 - 46: 28069663 bnez a3,2d2 <.L4> - -0000004a <.LVL11>: - 4a: 00000737 lui a4,0x0 - -0000004e <.LVL12>: - 4e: 00070713 mv a4,a4 - 52: 14c5fb63 bgeu a1,a2,1a8 <.L5> - -00000056 <.LBB22>: - 56: 67c1 lui a5,0x10 - 58: 14f67163 bgeu a2,a5,19a <.L6> - 5c: 10063793 sltiu a5,a2,256 - 60: 0017c793 xor a5,a5,1 - 64: 078e sll a5,a5,0x3 - -00000066 <.L7>: - 66: 00f656b3 srl a3,a2,a5 - 6a: 9736 add a4,a4,a3 - 6c: 00074703 lbu a4,0(a4) # 0 <__divmoddi4> - 70: 97ba add a5,a5,a4 - -00000072 <.LVL15>: - 72: 02000713 li a4,32 - 76: 40f706b3 sub a3,a4,a5 - 7a: c236 sw a3,4(sp) - -0000007c <.LBE22>: - 7c: 00f70c63 beq a4,a5,94 <.L95> - 80: 00f557b3 srl a5,a0,a5 - 84: 00d59433 sll s0,a1,a3 - 88: 8c5d or s0,s0,a5 - 8a: 00d517b3 sll a5,a0,a3 - 8e: 00d614b3 sll s1,a2,a3 - -00000092 <.LVL17>: - 92: c03e sw a5,0(sp) - -00000094 <.L95>: - 94: 01049793 sll a5,s1,0x10 - 98: 83c1 srl a5,a5,0x10 - 9a: 0104d593 srl a1,s1,0x10 - 9e: 8522 mv a0,s0 - a0: c83e sw a5,16(sp) - -000000a2 <.LVL19>: - a2: 00000097 auipc ra,0x0 - a6: 000080e7 jalr ra # a2 <.LVL19> - -000000aa <.LVL20>: - aa: 85aa mv a1,a0 - ac: cc2a sw a0,24(sp) - ae: 01049513 sll a0,s1,0x10 - -000000b2 <.LVL21>: - b2: 8141 srl a0,a0,0x10 - b4: 00000097 auipc ra,0x0 - b8: 000080e7 jalr ra # b4 <.LVL21+0x2> - -000000bc <.LVL22>: - bc: c82a sw a0,16(sp) - -000000be <.LVL23>: - be: 0104d593 srl a1,s1,0x10 - c2: 8522 mv a0,s0 - -000000c4 <.LVL24>: - c4: 00000097 auipc ra,0x0 - c8: 000080e7 jalr ra # c4 <.LVL24> - -000000cc <.LVL25>: - cc: 4782 lw a5,0(sp) - ce: 46e2 lw a3,24(sp) - d0: 4742 lw a4,16(sp) - d2: 0107d413 srl s0,a5,0x10 - -000000d6 <.LVL26>: - d6: 0542 sll a0,a0,0x10 - d8: 8c49 or s0,s0,a0 - -000000da <.LVL27>: - da: 87b6 mv a5,a3 - dc: 00e47c63 bgeu s0,a4,f4 <.L26> - e0: 9426 add s0,s0,s1 - -000000e2 <.LVL28>: - e2: fff68793 add a5,a3,-1 - -000000e6 <.LVL29>: - e6: 00946763 bltu s0,s1,f4 <.L26> - ea: 00e47563 bgeu s0,a4,f4 <.L26> - ee: ffe68793 add a5,a3,-2 - f2: 9426 add s0,s0,s1 - -000000f4 <.L26>: - f4: ce3e sw a5,28(sp) - -000000f6 <.LVL32>: - f6: 40e407b3 sub a5,s0,a4 - fa: 853e mv a0,a5 - fc: 0104d593 srl a1,s1,0x10 - 100: c83e sw a5,16(sp) - -00000102 <.LVL33>: - 102: 00000097 auipc ra,0x0 - 106: 000080e7 jalr ra # 102 <.LVL33> - -0000010a <.LVL34>: - 10a: 85aa mv a1,a0 - 10c: cc2a sw a0,24(sp) - 10e: 01049513 sll a0,s1,0x10 - -00000112 <.LVL35>: - 112: 8141 srl a0,a0,0x10 - 114: 00000097 auipc ra,0x0 - 118: 000080e7 jalr ra # 114 <.LVL35+0x2> - -0000011c <.LVL36>: - 11c: 842a mv s0,a0 - -0000011e <.LVL37>: - 11e: 4542 lw a0,16(sp) - 120: 0104d593 srl a1,s1,0x10 - 124: 00000097 auipc ra,0x0 - 128: 000080e7 jalr ra # 124 <.LVL37+0x6> - -0000012c <.LVL38>: - 12c: 00015703 lhu a4,0(sp) - 130: 4662 lw a2,24(sp) - 132: 0542 sll a0,a0,0x10 - 134: 8f49 or a4,a4,a0 - -00000136 <.LVL39>: - 136: 47f2 lw a5,28(sp) - 138: 85b2 mv a1,a2 - 13a: 00877c63 bgeu a4,s0,152 <.L29> - 13e: 9726 add a4,a4,s1 - -00000140 <.LVL40>: - 140: fff60593 add a1,a2,-1 - -00000144 <.LVL41>: - 144: 00976763 bltu a4,s1,152 <.L29> - 148: 00877563 bgeu a4,s0,152 <.L29> - 14c: ffe60593 add a1,a2,-2 - 150: 9726 add a4,a4,s1 - -00000152 <.L29>: - 152: 4692 lw a3,4(sp) - 154: 44b2 lw s1,12(sp) - -00000156 <.LBB26>: - 156: 8f01 sub a4,a4,s0 - 158: 07c2 sll a5,a5,0x10 - 15a: 8fcd or a5,a5,a1 - -0000015c <.LBE26>: - 15c: 00d75733 srl a4,a4,a3 - -00000160 <.LVL47>: - 160: 4401 li s0,0 - -00000162 <.L32>: - 162: 853e mv a0,a5 - -00000164 <.LBE20>: - 164: 47d2 lw a5,20(sp) - -00000166 <.LBB52>: - 166: 85a6 mv a1,s1 - -00000168 <.LBE52>: - 168: cb81 beqz a5,178 <.L54> - 16a: 00a037b3 snez a5,a0 - 16e: 409005b3 neg a1,s1 - 172: 8d9d sub a1,a1,a5 - 174: 40a00533 neg a0,a0 - -00000178 <.L54>: - 178: 47a2 lw a5,8(sp) - 17a: cb81 beqz a5,18a <.L55> - 17c: 00e037b3 snez a5,a4 - 180: 40800433 neg s0,s0 - -00000184 <.LVL52>: - 184: 8c1d sub s0,s0,a5 - 186: 40e00733 neg a4,a4 - -0000018a <.L55>: - 18a: 5792 lw a5,36(sp) - 18c: 50f2 lw ra,60(sp) - 18e: 54d2 lw s1,52(sp) - 190: c3c0 sw s0,4(a5) - -00000192 <.LVL55>: - 192: 5462 lw s0,56(sp) - 194: c398 sw a4,0(a5) - 196: 6121 add sp,sp,64 - -00000198 <.LVL56>: - 198: 8082 ret - -0000019a <.L6>: - 19a: 010006b7 lui a3,0x1000 - -0000019e <.LVL58>: - 19e: 47c1 li a5,16 - 1a0: ecd663e3 bltu a2,a3,66 <.L7> - 1a4: 47e1 li a5,24 - 1a6: b5c1 j 66 <.L7> - -000001a8 <.L5>: - 1a8: 4781 li a5,0 - -000001aa <.LBE28>: - 1aa: ca09 beqz a2,1bc <.L16> - -000001ac <.LBB29>: - 1ac: 67c1 lui a5,0x10 - 1ae: 02f67963 bgeu a2,a5,1e0 <.L17> - -000001b2 <.LVL61>: - 1b2: 10063793 sltiu a5,a2,256 - 1b6: 0017c793 xor a5,a5,1 - 1ba: 078e sll a5,a5,0x3 - -000001bc <.L16>: - 1bc: 00f656b3 srl a3,a2,a5 - 1c0: 9736 add a4,a4,a3 - 1c2: 00074703 lbu a4,0(a4) - 1c6: 97ba add a5,a5,a4 - -000001c8 <.LVL63>: - 1c8: 02000713 li a4,32 - 1cc: 40f706b3 sub a3,a4,a5 - 1d0: c236 sw a3,4(sp) - -000001d2 <.LBE29>: - 1d2: 00f71e63 bne a4,a5,1ee <.L18> - 1d6: 40c58433 sub s0,a1,a2 - -000001da <.LVL65>: - 1da: 4785 li a5,1 - -000001dc <.L82>: - 1dc: c63e sw a5,12(sp) - 1de: bd5d j 94 <.L95> - -000001e0 <.L17>: - 1e0: 010006b7 lui a3,0x1000 - -000001e4 <.LVL68>: - 1e4: 47c1 li a5,16 - 1e6: fcd66be3 bltu a2,a3,1bc <.L16> - 1ea: 47e1 li a5,24 - 1ec: bfc1 j 1bc <.L16> - -000001ee <.L18>: - 1ee: 4712 lw a4,4(sp) - 1f0: 00f5d433 srl s0,a1,a5 - 1f4: 00f557b3 srl a5,a0,a5 - -000001f8 <.LVL70>: - 1f8: 00e595b3 sll a1,a1,a4 - 1fc: 8fcd or a5,a5,a1 - 1fe: 00e614b3 sll s1,a2,a4 - -00000202 <.LVL71>: - 202: c63e sw a5,12(sp) - -00000204 <.LVL72>: - 204: 00e517b3 sll a5,a0,a4 - -00000208 <.LVL73>: - 208: c03e sw a5,0(sp) - -0000020a <.LBB32>: - 20a: 01049793 sll a5,s1,0x10 - 20e: 83c1 srl a5,a5,0x10 - 210: 0104d593 srl a1,s1,0x10 - 214: 8522 mv a0,s0 - -00000216 <.LVL75>: - 216: c83e sw a5,16(sp) - -00000218 <.LVL76>: - 218: 00000097 auipc ra,0x0 - 21c: 000080e7 jalr ra # 218 <.LVL76> - -00000220 <.LVL77>: - 220: 85aa mv a1,a0 - 222: cc2a sw a0,24(sp) - 224: 01049513 sll a0,s1,0x10 - -00000228 <.LVL78>: - 228: 8141 srl a0,a0,0x10 - 22a: 00000097 auipc ra,0x0 - 22e: 000080e7 jalr ra # 22a <.LVL78+0x2> - -00000232 <.LVL79>: - 232: c82a sw a0,16(sp) - -00000234 <.LVL80>: - 234: 0104d593 srl a1,s1,0x10 - 238: 8522 mv a0,s0 - -0000023a <.LVL81>: - 23a: 00000097 auipc ra,0x0 - 23e: 000080e7 jalr ra # 23a <.LVL81> - -00000242 <.LVL82>: - 242: 47b2 lw a5,12(sp) - 244: 46e2 lw a3,24(sp) - 246: 4742 lw a4,16(sp) - 248: 0107d413 srl s0,a5,0x10 - -0000024c <.LVL83>: - 24c: 0542 sll a0,a0,0x10 - 24e: 8c49 or s0,s0,a0 - -00000250 <.LVL84>: - 250: 87b6 mv a5,a3 - 252: 00e47c63 bgeu s0,a4,26a <.L20> - 256: 9426 add s0,s0,s1 - -00000258 <.LVL85>: - 258: fff68793 add a5,a3,-1 # ffffff <.LLST64+0xfff13e> - -0000025c <.LVL86>: - 25c: 00946763 bltu s0,s1,26a <.L20> - 260: 00e47563 bgeu s0,a4,26a <.L20> - 264: ffe68793 add a5,a3,-2 - 268: 9426 add s0,s0,s1 - -0000026a <.L20>: - 26a: ce3e sw a5,28(sp) - -0000026c <.LVL89>: - 26c: 40e407b3 sub a5,s0,a4 - 270: 853e mv a0,a5 - 272: 0104d593 srl a1,s1,0x10 - 276: c83e sw a5,16(sp) - -00000278 <.LVL90>: - 278: 00000097 auipc ra,0x0 - 27c: 000080e7 jalr ra # 278 <.LVL90> - -00000280 <.LVL91>: - 280: 85aa mv a1,a0 - 282: cc2a sw a0,24(sp) - 284: 01049513 sll a0,s1,0x10 - -00000288 <.LVL92>: - 288: 8141 srl a0,a0,0x10 - 28a: 00000097 auipc ra,0x0 - 28e: 000080e7 jalr ra # 28a <.LVL92+0x2> - -00000292 <.LVL93>: - 292: 842a mv s0,a0 - -00000294 <.LVL94>: - 294: 4542 lw a0,16(sp) - 296: 0104d593 srl a1,s1,0x10 - 29a: 00000097 auipc ra,0x0 - 29e: 000080e7 jalr ra # 29a <.LVL94+0x6> - -000002a2 <.LVL95>: - 2a2: 00c15603 lhu a2,12(sp) - 2a6: 46e2 lw a3,24(sp) - 2a8: 0542 sll a0,a0,0x10 - 2aa: 8e49 or a2,a2,a0 - -000002ac <.LVL96>: - 2ac: 47f2 lw a5,28(sp) - 2ae: 85b6 mv a1,a3 - 2b0: 00867c63 bgeu a2,s0,2c8 <.L23> - 2b4: 9626 add a2,a2,s1 - -000002b6 <.LVL97>: - 2b6: fff68593 add a1,a3,-1 - -000002ba <.LVL98>: - 2ba: 00966763 bltu a2,s1,2c8 <.L23> - 2be: 00867563 bgeu a2,s0,2c8 <.L23> - 2c2: ffe68593 add a1,a3,-2 - 2c6: 9626 add a2,a2,s1 - -000002c8 <.L23>: - 2c8: 07c2 sll a5,a5,0x10 - 2ca: 40860433 sub s0,a2,s0 - -000002ce <.LVL101>: - 2ce: 8fcd or a5,a5,a1 - 2d0: b731 j 1dc <.L82> - -000002d2 <.L4>: - 2d2: 00d5f663 bgeu a1,a3,2de <.L33> - -000002d6 <.LVL103>: - 2d6: 872a mv a4,a0 - -000002d8 <.LVL104>: - 2d8: 4481 li s1,0 - -000002da <.LVL105>: - 2da: 4781 li a5,0 - 2dc: b559 j 162 <.L32> - -000002de <.L33>: - 2de: 67c1 lui a5,0x10 - 2e0: 04f6fa63 bgeu a3,a5,334 <.L34> - 2e4: 1006b793 sltiu a5,a3,256 - 2e8: 0017c793 xor a5,a5,1 - 2ec: 078e sll a5,a5,0x3 - -000002ee <.L35>: - 2ee: 00000737 lui a4,0x0 - 2f2: 00f6d333 srl t1,a3,a5 - 2f6: 00070713 mv a4,a4 - 2fa: 971a add a4,a4,t1 - 2fc: 00074703 lbu a4,0(a4) # 0 <__divmoddi4> - 300: 97ba add a5,a5,a4 - -00000302 <.LVL108>: - 302: c23e sw a5,4(sp) - 304: 4712 lw a4,4(sp) - 306: 02000793 li a5,32 - 30a: 40e784b3 sub s1,a5,a4 - -0000030e <.LBE33>: - 30e: 02e79a63 bne a5,a4,342 <.L36> - 312: 00b6e563 bltu a3,a1,31c <.L37> - 316: 4781 li a5,0 - 318: 00c56c63 bltu a0,a2,330 <.L38> - -0000031c <.L37>: - 31c: 40c50633 sub a2,a0,a2 - -00000320 <.LVL111>: - 320: 40d586b3 sub a3,a1,a3 - -00000324 <.LVL112>: - 324: 00c53433 sltu s0,a0,a2 - 328: c032 sw a2,0(sp) - -0000032a <.LVL113>: - 32a: 40868433 sub s0,a3,s0 - -0000032e <.LBE34>: - 32e: 4785 li a5,1 - -00000330 <.L38>: - 330: 4702 lw a4,0(sp) - 332: bd05 j 162 <.L32> - -00000334 <.L34>: - 334: 01000737 lui a4,0x1000 - -00000338 <.LVL118>: - 338: 47c1 li a5,16 - 33a: fae6eae3 bltu a3,a4,2ee <.L35> - 33e: 47e1 li a5,24 - 340: b77d j 2ee <.L35> - -00000342 <.L36>: - 342: 4792 lw a5,4(sp) - 344: 009696b3 sll a3,a3,s1 - -00000348 <.LVL120>: - 348: 00f657b3 srl a5,a2,a5 - 34c: 00d7e333 or t1,a5,a3 - -00000350 <.LVL121>: - 350: 009617b3 sll a5,a2,s1 - 354: c63e sw a5,12(sp) - -00000356 <.LVL122>: - 356: 4792 lw a5,4(sp) - -00000358 <.LBB37>: - 358: d61a sw t1,44(sp) - -0000035a <.LBE37>: - 35a: 00f5d433 srl s0,a1,a5 - -0000035e <.LVL124>: - 35e: 009595b3 sll a1,a1,s1 - 362: 00f557b3 srl a5,a0,a5 - 366: 8fcd or a5,a5,a1 - 368: cc3e sw a5,24(sp) - -0000036a <.LVL125>: - 36a: 009517b3 sll a5,a0,s1 - -0000036e <.LVL126>: - 36e: c83e sw a5,16(sp) - -00000370 <.LBB38>: - 370: 01035793 srl a5,t1,0x10 - -00000374 <.LVL128>: - 374: c03e sw a5,0(sp) - -00000376 <.LVL129>: - 376: 4582 lw a1,0(sp) - 378: 01031793 sll a5,t1,0x10 - -0000037c <.LVL130>: - 37c: 83c1 srl a5,a5,0x10 - 37e: 8522 mv a0,s0 - 380: ce3e sw a5,28(sp) - -00000382 <.LVL131>: - 382: 00000097 auipc ra,0x0 - 386: 000080e7 jalr ra # 382 <.LVL131> - -0000038a <.LVL132>: - 38a: 85aa mv a1,a0 - 38c: d42a sw a0,40(sp) - 38e: 4572 lw a0,28(sp) - -00000390 <.LVL133>: - 390: 00000097 auipc ra,0x0 - 394: 000080e7 jalr ra # 390 <.LVL133> - -00000398 <.LVL134>: - 398: 4582 lw a1,0(sp) - 39a: d02a sw a0,32(sp) - -0000039c <.LVL135>: - 39c: 8522 mv a0,s0 - -0000039e <.LVL136>: - 39e: 00000097 auipc ra,0x0 - 3a2: 000080e7 jalr ra # 39e <.LVL136> - -000003a6 <.LVL137>: - 3a6: 47e2 lw a5,24(sp) - 3a8: 56a2 lw a3,40(sp) - 3aa: 5702 lw a4,32(sp) - 3ac: 0107d413 srl s0,a5,0x10 - -000003b0 <.LVL138>: - 3b0: 0542 sll a0,a0,0x10 - 3b2: 8c49 or s0,s0,a0 - -000003b4 <.LVL139>: - 3b4: 5332 lw t1,44(sp) - 3b6: 87b6 mv a5,a3 - 3b8: 00e47c63 bgeu s0,a4,3d0 <.L41> - 3bc: 941a add s0,s0,t1 - -000003be <.LVL140>: - 3be: fff68793 add a5,a3,-1 - -000003c2 <.LVL141>: - 3c2: 00646763 bltu s0,t1,3d0 <.L41> - 3c6: 00e47563 bgeu s0,a4,3d0 <.L41> - 3ca: ffe68793 add a5,a3,-2 - 3ce: 941a add s0,s0,t1 - -000003d0 <.L41>: - 3d0: 4582 lw a1,0(sp) - 3d2: d83e sw a5,48(sp) - 3d4: 40e407b3 sub a5,s0,a4 - -000003d8 <.LVL144>: - 3d8: 853e mv a0,a5 - 3da: d61a sw t1,44(sp) - -000003dc <.LVL145>: - 3dc: d03e sw a5,32(sp) - -000003de <.LVL146>: - 3de: 00000097 auipc ra,0x0 - 3e2: 000080e7 jalr ra # 3de <.LVL146> - -000003e6 <.LVL147>: - 3e6: 85aa mv a1,a0 - 3e8: d42a sw a0,40(sp) - 3ea: 4572 lw a0,28(sp) - -000003ec <.LVL148>: - 3ec: 00000097 auipc ra,0x0 - 3f0: 000080e7 jalr ra # 3ec <.LVL148> - -000003f4 <.LVL149>: - 3f4: 4582 lw a1,0(sp) - 3f6: 842a mv s0,a0 - -000003f8 <.LVL150>: - 3f8: 5502 lw a0,32(sp) - 3fa: 00000097 auipc ra,0x0 - 3fe: 000080e7 jalr ra # 3fa <.LVL150+0x2> - -00000402 <.LVL151>: - 402: 01815603 lhu a2,24(sp) - 406: 56a2 lw a3,40(sp) - 408: 0542 sll a0,a0,0x10 - 40a: 8e49 or a2,a2,a0 - -0000040c <.LVL152>: - 40c: 5332 lw t1,44(sp) - 40e: 57c2 lw a5,48(sp) - 410: 85b6 mv a1,a3 - 412: 00867c63 bgeu a2,s0,42a <.L44> - -00000416 <.LVL153>: - 416: 961a add a2,a2,t1 - -00000418 <.LVL154>: - 418: fff68593 add a1,a3,-1 - -0000041c <.LVL155>: - 41c: 00666763 bltu a2,t1,42a <.L44> - 420: 00867563 bgeu a2,s0,42a <.L44> - 424: ffe68593 add a1,a3,-2 - 428: 961a add a2,a2,t1 - -0000042a <.L44>: - 42a: 40860733 sub a4,a2,s0 - -0000042e <.LBB39>: - 42e: 4632 lw a2,12(sp) - -00000430 <.LBB44>: - 430: c03a sw a4,0(sp) - -00000432 <.LVL159>: - 432: 07c2 sll a5,a5,0x10 - -00000434 <.LBB45>: - 434: 6741 lui a4,0x10 - -00000436 <.LBB46>: - 436: 8fcd or a5,a5,a1 - -00000438 <.LBB47>: - 438: fff70393 add t2,a4,-1 # ffff <.LLST64+0xf13e> - 43c: 0077f733 and a4,a5,t2 - -00000440 <.LVL162>: - 440: 007673b3 and t2,a2,t2 - -00000444 <.LVL163>: - 444: 01065413 srl s0,a2,0x10 - -00000448 <.LBB40>: - 448: 853a mv a0,a4 - 44a: 859e mv a1,t2 - -0000044c <.LVL165>: - 44c: 00000097 auipc ra,0x0 - 450: 000080e7 jalr ra # 44c <.LVL165> - 454: 82aa mv t0,a0 - -00000456 <.LBB41>: - 456: 85a2 mv a1,s0 - 458: 853a mv a0,a4 - 45a: 00000097 auipc ra,0x0 - 45e: 000080e7 jalr ra # 45a <.LBB41+0x4> - 462: 872a mv a4,a0 - -00000464 <.LBB42>: - 464: 859e mv a1,t2 - 466: 0107d513 srl a0,a5,0x10 - -0000046a <.LVL168>: - 46a: 00000097 auipc ra,0x0 - 46e: 000080e7 jalr ra # 46a <.LVL168> - -00000472 <.LVL169>: - 472: 83aa mv t2,a0 - -00000474 <.LBB43>: - 474: 85a2 mv a1,s0 - 476: 0107d513 srl a0,a5,0x10 - -0000047a <.LVL171>: - 47a: 00000097 auipc ra,0x0 - 47e: 000080e7 jalr ra # 47a <.LVL171> - -00000482 <.LBE43>: - 482: 971e add a4,a4,t2 - -00000484 <.LVL173>: - 484: 0102d693 srl a3,t0,0x10 - 488: 9736 add a4,a4,a3 - -0000048a <.LVL174>: - 48a: 00777463 bgeu a4,t2,492 <.L47> - 48e: 66c1 lui a3,0x10 - -00000490 <.LVL175>: - 490: 9536 add a0,a0,a3 - -00000492 <.L47>: - 492: 01075693 srl a3,a4,0x10 - 496: 9536 add a0,a0,a3 - -00000498 <.LVL177>: - 498: 66c1 lui a3,0x10 - -0000049a <.LVL178>: - 49a: 16fd add a3,a3,-1 # ffff <.LLST64+0xf13e> - -0000049c <.LVL179>: - 49c: 8f75 and a4,a4,a3 - -0000049e <.LVL180>: - 49e: 0742 sll a4,a4,0x10 - 4a0: 00d2f2b3 and t0,t0,a3 - -000004a4 <.LVL181>: - 4a4: 92ba add t0,t0,a4 - -000004a6 <.LBE47>: - 4a6: 4702 lw a4,0(sp) - 4a8: 00a76763 bltu a4,a0,4b6 <.L48> - 4ac: 00a71f63 bne a4,a0,4ca <.L49> - 4b0: 4742 lw a4,16(sp) - 4b2: 00577c63 bgeu a4,t0,4ca <.L49> - -000004b6 <.L48>: - 4b6: 4732 lw a4,12(sp) - 4b8: 17fd add a5,a5,-1 # ffff <.LLST64+0xf13e> - -000004ba <.LBB48>: - 4ba: 40e28733 sub a4,t0,a4 - 4be: 00e2b6b3 sltu a3,t0,a4 - -000004c2 <.LVL184>: - 4c2: 82ba mv t0,a4 - -000004c4 <.LVL185>: - 4c4: 00668733 add a4,a3,t1 - 4c8: 8d19 sub a0,a0,a4 - -000004ca <.L49>: - 4ca: 4742 lw a4,16(sp) - 4cc: 405702b3 sub t0,a4,t0 - -000004d0 <.LVL187>: - 4d0: 4702 lw a4,0(sp) - 4d2: 40a70433 sub s0,a4,a0 - 4d6: 4742 lw a4,16(sp) - 4d8: 00573733 sltu a4,a4,t0 - 4dc: 8c19 sub s0,s0,a4 - -000004de <.LBE49>: - 4de: 4712 lw a4,4(sp) - 4e0: 0092d2b3 srl t0,t0,s1 - -000004e4 <.LVL189>: - 4e4: 00e41733 sll a4,s0,a4 - 4e8: 00576733 or a4,a4,t0 - 4ec: 00945433 srl s0,s0,s1 - -000004f0 <.LVL190>: - 4f0: 4481 li s1,0 - -000004f2 <.LVL191>: - 4f2: b985 j 162 <.L32> - -_udivdi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__udivdi3>: - 0: fd810113 add sp,sp,-40 - 4: d206 sw ra,36(sp) - 6: d022 sw s0,32(sp) - 8: ce26 sw s1,28(sp) - a: 832a mv t1,a0 - -0000000c <.LBB48>: - c: 30069663 bnez a3,318 <.L2> - 10: 000006b7 lui a3,0x0 - -00000014 <.LVL1>: - 14: 82b2 mv t0,a2 - 16: 842a mv s0,a0 - 18: 00068693 mv a3,a3 - 1c: 10c5f863 bgeu a1,a2,12c <.L3> - -00000020 <.LBB22>: - 20: 67c1 lui a5,0x10 - 22: 84ae mv s1,a1 - -00000024 <.LBB23>: - 24: 0ef67d63 bgeu a2,a5,11e <.L4> - 28: 10063793 sltiu a5,a2,256 - 2c: 0017c793 xor a5,a5,1 - 30: 078e sll a5,a5,0x3 - -00000032 <.L5>: - 32: 00f65533 srl a0,a2,a5 - 36: 96aa add a3,a3,a0 - 38: 0006c683 lbu a3,0(a3) # 0 <__udivdi3> - 3c: 02000513 li a0,32 - 40: 97b6 add a5,a5,a3 - -00000042 <.LVL4>: - 42: 40f506b3 sub a3,a0,a5 - -00000046 <.LBE23>: - 46: 00f50c63 beq a0,a5,5e <.L6> - -0000004a <.LVL6>: - 4a: 00d59733 sll a4,a1,a3 - 4e: 00f357b3 srl a5,t1,a5 - 52: 00d612b3 sll t0,a2,a3 - -00000056 <.LVL7>: - 56: 00e7e4b3 or s1,a5,a4 - -0000005a <.LVL8>: - 5a: 00d31433 sll s0,t1,a3 - -0000005e <.L6>: - 5e: 0102d793 srl a5,t0,0x10 - 62: c03e sw a5,0(sp) - -00000064 <.LVL10>: - 64: 4582 lw a1,0(sp) - -00000066 <.LVL11>: - 66: 01029793 sll a5,t0,0x10 - -0000006a <.LVL12>: - 6a: 83c1 srl a5,a5,0x10 - 6c: 8526 mv a0,s1 - 6e: c816 sw t0,16(sp) - 70: c23e sw a5,4(sp) - -00000072 <.LVL13>: - 72: 00000097 auipc ra,0x0 - 76: 000080e7 jalr ra # 72 <.LVL13> - -0000007a <.LVL14>: - 7a: 85aa mv a1,a0 - 7c: c62a sw a0,12(sp) - 7e: 4512 lw a0,4(sp) - -00000080 <.LVL15>: - 80: 00000097 auipc ra,0x0 - 84: 000080e7 jalr ra # 80 <.LVL15> - -00000088 <.LVL16>: - 88: 4582 lw a1,0(sp) - 8a: c42a sw a0,8(sp) - -0000008c <.LVL17>: - 8c: 8526 mv a0,s1 - -0000008e <.LVL18>: - 8e: 00000097 auipc ra,0x0 - 92: 000080e7 jalr ra # 8e <.LVL18> - -00000096 <.LVL19>: - 96: 4632 lw a2,12(sp) - 98: 46a2 lw a3,8(sp) - 9a: 0542 sll a0,a0,0x10 - 9c: 01045713 srl a4,s0,0x10 - a0: 8f49 or a4,a4,a0 - -000000a2 <.LVL20>: - a2: 42c2 lw t0,16(sp) - a4: 84b2 mv s1,a2 - -000000a6 <.LVL21>: - a6: 00d77c63 bgeu a4,a3,be <.L7> - aa: 9716 add a4,a4,t0 - -000000ac <.LVL22>: - ac: fff60493 add s1,a2,-1 - -000000b0 <.LVL23>: - b0: 00576763 bltu a4,t0,be <.L7> - b4: 00d77563 bgeu a4,a3,be <.L7> - b8: ffe60493 add s1,a2,-2 - bc: 9716 add a4,a4,t0 - -000000be <.L7>: - be: 4582 lw a1,0(sp) - c0: 40d707b3 sub a5,a4,a3 - c4: 853e mv a0,a5 - c6: c816 sw t0,16(sp) - -000000c8 <.LVL26>: - c8: c43e sw a5,8(sp) - -000000ca <.LVL27>: - ca: 00000097 auipc ra,0x0 - ce: 000080e7 jalr ra # ca <.LVL27> - -000000d2 <.LVL28>: - d2: 85aa mv a1,a0 - d4: c62a sw a0,12(sp) - d6: 4512 lw a0,4(sp) - -000000d8 <.LVL29>: - d8: 0442 sll s0,s0,0x10 - -000000da <.LVL30>: - da: 8041 srl s0,s0,0x10 - dc: 00000097 auipc ra,0x0 - e0: 000080e7 jalr ra # dc <.LVL30+0x2> - -000000e4 <.LVL31>: - e4: c22a sw a0,4(sp) - -000000e6 <.LVL32>: - e6: 4582 lw a1,0(sp) - e8: 4522 lw a0,8(sp) - -000000ea <.LVL33>: - ea: 00000097 auipc ra,0x0 - ee: 000080e7 jalr ra # ea <.LVL33> - -000000f2 <.LVL34>: - f2: 4732 lw a4,12(sp) - f4: 4692 lw a3,4(sp) - f6: 0542 sll a0,a0,0x10 - f8: 8c49 or s0,s0,a0 - -000000fa <.LVL35>: - fa: 863a mv a2,a4 - fc: 00d47c63 bgeu s0,a3,114 <.L10> - 100: 42c2 lw t0,16(sp) - 102: fff70613 add a2,a4,-1 - -00000106 <.LVL36>: - 106: 9416 add s0,s0,t0 - -00000108 <.LVL37>: - 108: 00546663 bltu s0,t0,114 <.L10> - -0000010c <.LVL38>: - 10c: 00d47463 bgeu s0,a3,114 <.L10> - 110: ffe70613 add a2,a4,-2 - -00000114 <.L10>: - 114: 01049793 sll a5,s1,0x10 - 118: 8fd1 or a5,a5,a2 - -0000011a <.L55>: - 11a: 4481 li s1,0 - 11c: a211 j 220 <.L13> - -0000011e <.L4>: - 11e: 01000537 lui a0,0x1000 - -00000122 <.LVL42>: - 122: 47c1 li a5,16 - 124: f0a667e3 bltu a2,a0,32 <.L5> - 128: 47e1 li a5,24 - 12a: b721 j 32 <.L5> - -0000012c <.L3>: - 12c: 4781 li a5,0 - -0000012e <.LBE39>: - 12e: ca09 beqz a2,140 <.L14> - -00000130 <.LBB40>: - 130: 67c1 lui a5,0x10 - 132: 0ef67f63 bgeu a2,a5,230 <.L15> - -00000136 <.LVL45>: - 136: 10063793 sltiu a5,a2,256 - 13a: 0017c793 xor a5,a5,1 - 13e: 078e sll a5,a5,0x3 - -00000140 <.L14>: - 140: 00f65733 srl a4,a2,a5 - 144: 96ba add a3,a3,a4 - 146: 0006c703 lbu a4,0(a3) - 14a: 02000693 li a3,32 - 14e: 97ba add a5,a5,a4 - -00000150 <.LVL47>: - 150: 40f68733 sub a4,a3,a5 - -00000154 <.LBE40>: - 154: 0ef69563 bne a3,a5,23e <.L16> - 158: 40c58633 sub a2,a1,a2 - -0000015c <.LVL49>: - 15c: 4485 li s1,1 - -0000015e <.L17>: - 15e: 0102d793 srl a5,t0,0x10 - 162: c03e sw a5,0(sp) - -00000164 <.LVL51>: - 164: 4582 lw a1,0(sp) - 166: 01029793 sll a5,t0,0x10 - -0000016a <.LVL52>: - 16a: 83c1 srl a5,a5,0x10 - 16c: 8532 mv a0,a2 - 16e: ca16 sw t0,20(sp) - 170: c23e sw a5,4(sp) - -00000172 <.LVL53>: - 172: c832 sw a2,16(sp) - 174: 00000097 auipc ra,0x0 - 178: 000080e7 jalr ra # 174 <.LVL53+0x2> - -0000017c <.LVL54>: - 17c: 85aa mv a1,a0 - 17e: c62a sw a0,12(sp) - 180: 4512 lw a0,4(sp) - -00000182 <.LVL55>: - 182: 00000097 auipc ra,0x0 - 186: 000080e7 jalr ra # 182 <.LVL55> - -0000018a <.LVL56>: - 18a: 4642 lw a2,16(sp) - 18c: 4582 lw a1,0(sp) - 18e: c42a sw a0,8(sp) - -00000190 <.LVL57>: - 190: 8532 mv a0,a2 - -00000192 <.LVL58>: - 192: 00000097 auipc ra,0x0 - 196: 000080e7 jalr ra # 192 <.LVL58> - -0000019a <.LVL59>: - 19a: 43b2 lw t2,12(sp) - 19c: 4322 lw t1,8(sp) - 19e: 0542 sll a0,a0,0x10 - 1a0: 01045693 srl a3,s0,0x10 - 1a4: 8ec9 or a3,a3,a0 - -000001a6 <.LVL60>: - 1a6: 42d2 lw t0,20(sp) - 1a8: 879e mv a5,t2 - 1aa: 0066fc63 bgeu a3,t1,1c2 <.L24> - 1ae: 9696 add a3,a3,t0 - -000001b0 <.LVL61>: - 1b0: fff38793 add a5,t2,-1 - -000001b4 <.LVL62>: - 1b4: 0056e763 bltu a3,t0,1c2 <.L24> - 1b8: 0066f563 bgeu a3,t1,1c2 <.L24> - 1bc: ffe38793 add a5,t2,-2 - 1c0: 9696 add a3,a3,t0 - -000001c2 <.L24>: - 1c2: 4582 lw a1,0(sp) - 1c4: ca3e sw a5,20(sp) - -000001c6 <.LVL65>: - 1c6: 406687b3 sub a5,a3,t1 - -000001ca <.LVL66>: - 1ca: 853e mv a0,a5 - 1cc: c43e sw a5,8(sp) - -000001ce <.LVL67>: - 1ce: c816 sw t0,16(sp) - -000001d0 <.LVL68>: - 1d0: 00000097 auipc ra,0x0 - 1d4: 000080e7 jalr ra # 1d0 <.LVL68> - -000001d8 <.LVL69>: - 1d8: 85aa mv a1,a0 - 1da: c62a sw a0,12(sp) - 1dc: 4512 lw a0,4(sp) - -000001de <.LVL70>: - 1de: 0442 sll s0,s0,0x10 - -000001e0 <.LVL71>: - 1e0: 8041 srl s0,s0,0x10 - 1e2: 00000097 auipc ra,0x0 - 1e6: 000080e7 jalr ra # 1e2 <.LVL71+0x2> - -000001ea <.LVL72>: - 1ea: 4582 lw a1,0(sp) - 1ec: c22a sw a0,4(sp) - -000001ee <.LVL73>: - 1ee: 4522 lw a0,8(sp) - -000001f0 <.LVL74>: - 1f0: 00000097 auipc ra,0x0 - 1f4: 000080e7 jalr ra # 1f0 <.LVL74> - -000001f8 <.LVL75>: - 1f8: 46b2 lw a3,12(sp) - 1fa: 4612 lw a2,4(sp) - 1fc: 0542 sll a0,a0,0x10 - 1fe: 8c49 or s0,s0,a0 - -00000200 <.LVL76>: - 200: 47d2 lw a5,20(sp) - 202: 85b6 mv a1,a3 - 204: 00c47c63 bgeu s0,a2,21c <.L27> - 208: 42c2 lw t0,16(sp) - 20a: fff68593 add a1,a3,-1 - -0000020e <.LVL77>: - 20e: 9416 add s0,s0,t0 - -00000210 <.LVL78>: - 210: 00546663 bltu s0,t0,21c <.L27> - -00000214 <.LVL79>: - 214: 00c47463 bgeu s0,a2,21c <.L27> - 218: ffe68593 add a1,a3,-2 - -0000021c <.L27>: - 21c: 07c2 sll a5,a5,0x10 - 21e: 8fcd or a5,a5,a1 - -00000220 <.L13>: - 220: 5092 lw ra,36(sp) - 222: 5402 lw s0,32(sp) - 224: 85a6 mv a1,s1 - 226: 853e mv a0,a5 - 228: 44f2 lw s1,28(sp) - 22a: 02810113 add sp,sp,40 - 22e: 8082 ret - -00000230 <.L15>: - 230: 01000737 lui a4,0x1000 - 234: 47c1 li a5,16 - 236: f0e665e3 bltu a2,a4,140 <.L14> - 23a: 47e1 li a5,24 - 23c: b711 j 140 <.L14> - -0000023e <.L16>: - 23e: 00f5d4b3 srl s1,a1,a5 - 242: 00e595b3 sll a1,a1,a4 - -00000246 <.LVL84>: - 246: 00f357b3 srl a5,t1,a5 - -0000024a <.LVL85>: - 24a: 00e612b3 sll t0,a2,a4 - -0000024e <.LVL86>: - 24e: 8fcd or a5,a5,a1 - 250: c23e sw a5,4(sp) - -00000252 <.LBB43>: - 252: 0102d793 srl a5,t0,0x10 - -00000256 <.LVL88>: - 256: c03e sw a5,0(sp) - 258: 4582 lw a1,0(sp) - 25a: 01029793 sll a5,t0,0x10 - 25e: 83c1 srl a5,a5,0x10 - 260: 8526 mv a0,s1 - -00000262 <.LVL89>: - 262: ca16 sw t0,20(sp) - 264: c43e sw a5,8(sp) - -00000266 <.LBE43>: - 266: 00e31433 sll s0,t1,a4 - -0000026a <.LBB44>: - 26a: 00000097 auipc ra,0x0 - 26e: 000080e7 jalr ra # 26a <.LBB44> - -00000272 <.LVL91>: - 272: 85aa mv a1,a0 - 274: c82a sw a0,16(sp) - 276: 4522 lw a0,8(sp) - -00000278 <.LVL92>: - 278: 00000097 auipc ra,0x0 - 27c: 000080e7 jalr ra # 278 <.LVL92> - -00000280 <.LVL93>: - 280: 4582 lw a1,0(sp) - 282: c62a sw a0,12(sp) - -00000284 <.LVL94>: - 284: 8526 mv a0,s1 - -00000286 <.LVL95>: - 286: 00000097 auipc ra,0x0 - 28a: 000080e7 jalr ra # 286 <.LVL95> - -0000028e <.LVL96>: - 28e: 4792 lw a5,4(sp) - 290: 4642 lw a2,16(sp) - 292: 46b2 lw a3,12(sp) - 294: 0542 sll a0,a0,0x10 - 296: 83c1 srl a5,a5,0x10 - 298: 8fc9 or a5,a5,a0 - -0000029a <.LVL97>: - 29a: 42d2 lw t0,20(sp) - 29c: 84b2 mv s1,a2 - -0000029e <.LVL98>: - 29e: 00d7fc63 bgeu a5,a3,2b6 <.L18> - 2a2: 9796 add a5,a5,t0 - -000002a4 <.LVL99>: - 2a4: fff60493 add s1,a2,-1 - -000002a8 <.LVL100>: - 2a8: 0057e763 bltu a5,t0,2b6 <.L18> - 2ac: 00d7f563 bgeu a5,a3,2b6 <.L18> - 2b0: ffe60493 add s1,a2,-2 - 2b4: 9796 add a5,a5,t0 - -000002b6 <.L18>: - 2b6: 4582 lw a1,0(sp) - 2b8: 8f95 sub a5,a5,a3 - -000002ba <.LVL103>: - 2ba: 853e mv a0,a5 - 2bc: ca16 sw t0,20(sp) - -000002be <.LVL104>: - 2be: c63e sw a5,12(sp) - -000002c0 <.LVL105>: - 2c0: 00000097 auipc ra,0x0 - 2c4: 000080e7 jalr ra # 2c0 <.LVL105> - -000002c8 <.LVL106>: - 2c8: 85aa mv a1,a0 - 2ca: c82a sw a0,16(sp) - 2cc: 4522 lw a0,8(sp) - -000002ce <.LVL107>: - 2ce: 00000097 auipc ra,0x0 - 2d2: 000080e7 jalr ra # 2ce <.LVL107> - -000002d6 <.LVL108>: - 2d6: 4582 lw a1,0(sp) - 2d8: c42a sw a0,8(sp) - -000002da <.LVL109>: - 2da: 4532 lw a0,12(sp) - -000002dc <.LVL110>: - 2dc: 00000097 auipc ra,0x0 - 2e0: 000080e7 jalr ra # 2dc <.LVL110> - -000002e4 <.LVL111>: - 2e4: 00415603 lhu a2,4(sp) - 2e8: 46c2 lw a3,16(sp) - 2ea: 47a2 lw a5,8(sp) - 2ec: 0542 sll a0,a0,0x10 - 2ee: 8e49 or a2,a2,a0 - -000002f0 <.LVL112>: - 2f0: 42d2 lw t0,20(sp) - 2f2: 85b6 mv a1,a3 - 2f4: 00f67c63 bgeu a2,a5,30c <.L21> - -000002f8 <.LVL113>: - 2f8: 9616 add a2,a2,t0 - -000002fa <.LVL114>: - 2fa: fff68593 add a1,a3,-1 - -000002fe <.LVL115>: - 2fe: 00566763 bltu a2,t0,30c <.L21> - 302: 00f67563 bgeu a2,a5,30c <.L21> - 306: ffe68593 add a1,a3,-2 - 30a: 9616 add a2,a2,t0 - -0000030c <.L21>: - 30c: 01049713 sll a4,s1,0x10 - 310: 8e1d sub a2,a2,a5 - 312: 00b764b3 or s1,a4,a1 - -00000316 <.LVL119>: - 316: b5a1 j 15e <.L17> - -00000318 <.L2>: - 318: 1cd5ea63 bltu a1,a3,4ec <.L50> - -0000031c <.LBB45>: - 31c: 67c1 lui a5,0x10 - 31e: 02f6ff63 bgeu a3,a5,35c <.L30> - 322: 1006b793 sltiu a5,a3,256 - 326: 0017c793 xor a5,a5,1 - 32a: 078e sll a5,a5,0x3 - -0000032c <.L31>: - 32c: 00000737 lui a4,0x0 - 330: 00f6d533 srl a0,a3,a5 - -00000334 <.LVL123>: - 334: 00070713 mv a4,a4 - 338: 972a add a4,a4,a0 - 33a: 00074503 lbu a0,0(a4) # 0 <__udivdi3> - 33e: 953e add a0,a0,a5 - 340: 02000793 li a5,32 - -00000344 <.LVL124>: - 344: 40a784b3 sub s1,a5,a0 - -00000348 <.LBE45>: - 348: 02a79163 bne a5,a0,36a <.L32> - 34c: 4785 li a5,1 - 34e: ecb6e9e3 bltu a3,a1,220 <.L13> - 352: 00c33633 sltu a2,t1,a2 - -00000356 <.LVL126>: - 356: 00164793 xor a5,a2,1 - 35a: b5d9 j 220 <.L13> - -0000035c <.L30>: - 35c: 01000737 lui a4,0x1000 - 360: 47c1 li a5,16 - 362: fce6e5e3 bltu a3,a4,32c <.L31> - 366: 47e1 li a5,24 - 368: b7d1 j 32c <.L31> - -0000036a <.L32>: - 36a: 009697b3 sll a5,a3,s1 - 36e: 00a656b3 srl a3,a2,a0 - -00000372 <.LVL129>: - 372: 00f6e433 or s0,a3,a5 - -00000376 <.LVL130>: - 376: 009617b3 sll a5,a2,s1 - 37a: c03e sw a5,0(sp) - -0000037c <.LVL131>: - 37c: 00a5d7b3 srl a5,a1,a0 - -00000380 <.LVL132>: - 380: c23e sw a5,4(sp) - -00000382 <.LVL133>: - 382: 00a35533 srl a0,t1,a0 - -00000386 <.LVL134>: - 386: 009595b3 sll a1,a1,s1 - -0000038a <.LVL135>: - 38a: 00b567b3 or a5,a0,a1 - -0000038e <.LBB26>: - 38e: 4512 lw a0,4(sp) - -00000390 <.LBE26>: - 390: c43e sw a5,8(sp) - -00000392 <.LBB27>: - 392: 01041793 sll a5,s0,0x10 - -00000396 <.LVL138>: - 396: 83c1 srl a5,a5,0x10 - 398: 01045593 srl a1,s0,0x10 - -0000039c <.LBE27>: - 39c: ca1a sw t1,20(sp) - -0000039e <.LBB28>: - 39e: c63e sw a5,12(sp) - -000003a0 <.LVL140>: - 3a0: 00000097 auipc ra,0x0 - 3a4: 000080e7 jalr ra # 3a0 <.LVL140> - -000003a8 <.LVL141>: - 3a8: 85aa mv a1,a0 - 3aa: c82a sw a0,16(sp) - 3ac: 01041513 sll a0,s0,0x10 - -000003b0 <.LVL142>: - 3b0: 8141 srl a0,a0,0x10 - 3b2: 00000097 auipc ra,0x0 - 3b6: 000080e7 jalr ra # 3b2 <.LVL142+0x2> - -000003ba <.LVL143>: - 3ba: c62a sw a0,12(sp) - -000003bc <.LVL144>: - 3bc: 4512 lw a0,4(sp) - -000003be <.LVL145>: - 3be: 01045593 srl a1,s0,0x10 - 3c2: 00000097 auipc ra,0x0 - 3c6: 000080e7 jalr ra # 3c2 <.LVL145+0x4> - -000003ca <.LVL146>: - 3ca: 47a2 lw a5,8(sp) - 3cc: 43c2 lw t2,16(sp) - 3ce: 42b2 lw t0,12(sp) - 3d0: 0107d613 srl a2,a5,0x10 - 3d4: 0542 sll a0,a0,0x10 - 3d6: 8e49 or a2,a2,a0 - -000003d8 <.LVL147>: - 3d8: 4352 lw t1,20(sp) - 3da: 879e mv a5,t2 - 3dc: 00567c63 bgeu a2,t0,3f4 <.L33> - 3e0: 9622 add a2,a2,s0 - -000003e2 <.LVL148>: - 3e2: fff38793 add a5,t2,-1 - -000003e6 <.LVL149>: - 3e6: 00866763 bltu a2,s0,3f4 <.L33> - 3ea: 00567563 bgeu a2,t0,3f4 <.L33> - 3ee: ffe38793 add a5,t2,-2 - 3f2: 9622 add a2,a2,s0 - -000003f4 <.L33>: - 3f4: ca3e sw a5,20(sp) - -000003f6 <.LVL152>: - 3f6: 405607b3 sub a5,a2,t0 - 3fa: 853e mv a0,a5 - 3fc: 01045593 srl a1,s0,0x10 - 400: cc1a sw t1,24(sp) - 402: c23e sw a5,4(sp) - -00000404 <.LVL153>: - 404: 00000097 auipc ra,0x0 - 408: 000080e7 jalr ra # 404 <.LVL153> - -0000040c <.LVL154>: - 40c: 85aa mv a1,a0 - 40e: c82a sw a0,16(sp) - 410: 01041513 sll a0,s0,0x10 - -00000414 <.LVL155>: - 414: 8141 srl a0,a0,0x10 - 416: 00000097 auipc ra,0x0 - 41a: 000080e7 jalr ra # 416 <.LVL155+0x2> - -0000041e <.LVL156>: - 41e: c62a sw a0,12(sp) - -00000420 <.LVL157>: - 420: 4512 lw a0,4(sp) - -00000422 <.LVL158>: - 422: 01045593 srl a1,s0,0x10 - 426: 00000097 auipc ra,0x0 - 42a: 000080e7 jalr ra # 426 <.LVL158+0x4> - -0000042e <.LVL159>: - 42e: 00815603 lhu a2,8(sp) - 432: 43c2 lw t2,16(sp) - 434: 4732 lw a4,12(sp) - 436: 0542 sll a0,a0,0x10 - 438: 8e49 or a2,a2,a0 - -0000043a <.LVL160>: - 43a: 47d2 lw a5,20(sp) - 43c: 4362 lw t1,24(sp) - 43e: 859e mv a1,t2 - 440: 00e67c63 bgeu a2,a4,458 <.L36> - 444: 9622 add a2,a2,s0 - -00000446 <.LVL161>: - 446: fff38593 add a1,t2,-1 - -0000044a <.LVL162>: - 44a: 00866763 bltu a2,s0,458 <.L36> - 44e: 00e67563 bgeu a2,a4,458 <.L36> - 452: ffe38593 add a1,t2,-2 - 456: 9622 add a2,a2,s0 - -00000458 <.L36>: - 458: 40e60733 sub a4,a2,a4 - -0000045c <.LBB29>: - 45c: 4602 lw a2,0(sp) - 45e: 66c1 lui a3,0x10 - -00000460 <.LBB34>: - 460: 07c2 sll a5,a5,0x10 - 462: 8fcd or a5,a5,a1 - -00000464 <.LBB35>: - 464: fff68293 add t0,a3,-1 # ffff <.LLST66+0xf1f8> - 468: 0057f433 and s0,a5,t0 - -0000046c <.LVL167>: - 46c: 005672b3 and t0,a2,t0 - -00000470 <.LVL168>: - 470: 8241 srl a2,a2,0x10 - 472: c032 sw a2,0(sp) - -00000474 <.LBB30>: - 474: 8522 mv a0,s0 - 476: 8596 mv a1,t0 - -00000478 <.LVL170>: - 478: 00000097 auipc ra,0x0 - 47c: 000080e7 jalr ra # 478 <.LVL170> - -00000480 <.LVL171>: - 480: 83aa mv t2,a0 - -00000482 <.LBB31>: - 482: 4582 lw a1,0(sp) - 484: 8522 mv a0,s0 - 486: 00000097 auipc ra,0x0 - 48a: 000080e7 jalr ra # 486 <.LBB31+0x4> - 48e: 842a mv s0,a0 - -00000490 <.LBB32>: - 490: 8596 mv a1,t0 - 492: 0107d513 srl a0,a5,0x10 - -00000496 <.LVL174>: - 496: 00000097 auipc ra,0x0 - 49a: 000080e7 jalr ra # 496 <.LVL174> - -0000049e <.LVL175>: - 49e: 82aa mv t0,a0 - -000004a0 <.LBB33>: - 4a0: 4582 lw a1,0(sp) - 4a2: 0107d513 srl a0,a5,0x10 - -000004a6 <.LVL177>: - 4a6: 00000097 auipc ra,0x0 - 4aa: 000080e7 jalr ra # 4a6 <.LVL177> - -000004ae <.LBE33>: - 4ae: 0103d613 srl a2,t2,0x10 - 4b2: 005406b3 add a3,s0,t0 - 4b6: 00d60433 add s0,a2,a3 - -000004ba <.LVL179>: - 4ba: 00547463 bgeu s0,t0,4c2 <.L39> - 4be: 66c1 lui a3,0x10 - -000004c0 <.LVL180>: - 4c0: 9536 add a0,a0,a3 - -000004c2 <.L39>: - 4c2: 01045693 srl a3,s0,0x10 - 4c6: 96aa add a3,a3,a0 - -000004c8 <.LBE35>: - 4c8: 02d76063 bltu a4,a3,4e8 <.L40> - 4cc: c4d717e3 bne a4,a3,11a <.L55> - -000004d0 <.LBB36>: - 4d0: 6741 lui a4,0x10 - -000004d2 <.LVL183>: - 4d2: 177d add a4,a4,-1 # ffff <.LLST66+0xf1f8> - -000004d4 <.LVL184>: - 4d4: 8c79 and s0,s0,a4 - -000004d6 <.LVL185>: - 4d6: 0442 sll s0,s0,0x10 - 4d8: 00e3f733 and a4,t2,a4 - -000004dc <.LBE36>: - 4dc: 00931333 sll t1,t1,s1 - -000004e0 <.LBB37>: - 4e0: 943a add s0,s0,a4 - -000004e2 <.LBE37>: - 4e2: 4481 li s1,0 - -000004e4 <.LVL187>: - 4e4: d2837ee3 bgeu t1,s0,220 <.L13> - -000004e8 <.L40>: - 4e8: 17fd add a5,a5,-1 # ffff <.LLST66+0xf1f8> - -000004ea <.LBE47>: - 4ea: b905 j 11a <.L55> - -000004ec <.L50>: - 4ec: 4481 li s1,0 - 4ee: 4781 li a5,0 - 4f0: bb05 j 220 <.L13> - -_umoddi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__umoddi3>: - 0: fcc10113 add sp,sp,-52 - 4: d622 sw s0,44(sp) - 6: d806 sw ra,48(sp) - 8: d426 sw s1,40(sp) - -0000000a <.LBB54>: - a: 842a mv s0,a0 - -0000000c <.LVL1>: - c: 872e mv a4,a1 - -0000000e <.LVL2>: - e: 24069263 bnez a3,252 <.L2> - 12: 00000337 lui t1,0x0 - 16: 84b2 mv s1,a2 - 18: 00030313 mv t1,t1 - 1c: 10c5f163 bgeu a1,a2,11e <.L3> - -00000020 <.LBB22>: - 20: 66c1 lui a3,0x10 - -00000022 <.LVL4>: - 22: 0ed67763 bgeu a2,a3,110 <.L4> - 26: 10063693 sltiu a3,a2,256 - 2a: 0016c693 xor a3,a3,1 - 2e: 068e sll a3,a3,0x3 - -00000030 <.L5>: - 30: 00d652b3 srl t0,a2,a3 - 34: 9316 add t1,t1,t0 - 36: 00034303 lbu t1,0(t1) # 0 <__umoddi3> - 3a: 969a add a3,a3,t1 - -0000003c <.LVL6>: - 3c: 02000313 li t1,32 - 40: 40d307b3 sub a5,t1,a3 - 44: c03e sw a5,0(sp) - -00000046 <.LBE22>: - 46: 00d30b63 beq t1,a3,5c <.L6> - 4a: 00f59733 sll a4,a1,a5 - 4e: 00d556b3 srl a3,a0,a3 - 52: 00f614b3 sll s1,a2,a5 - -00000056 <.LVL8>: - 56: 8f55 or a4,a4,a3 - -00000058 <.LVL9>: - 58: 00f51433 sll s0,a0,a5 - -0000005c <.L6>: - 5c: 01049793 sll a5,s1,0x10 - -00000060 <.LVL11>: - 60: 83c1 srl a5,a5,0x10 - 62: 853a mv a0,a4 - -00000064 <.LVL12>: - 64: 0104d593 srl a1,s1,0x10 - 68: c43a sw a4,8(sp) - 6a: c23e sw a5,4(sp) - -0000006c <.LVL13>: - 6c: 00000097 auipc ra,0x0 - 70: 000080e7 jalr ra # 6c <.LVL13> - -00000074 <.LVL14>: - 74: 01049593 sll a1,s1,0x10 - 78: 81c1 srl a1,a1,0x10 - 7a: 00000097 auipc ra,0x0 - 7e: 000080e7 jalr ra # 7a <.LVL14+0x6> - -00000082 <.LVL15>: - 82: 4722 lw a4,8(sp) - 84: c22a sw a0,4(sp) - -00000086 <.LVL16>: - 86: 0104d593 srl a1,s1,0x10 - 8a: 853a mv a0,a4 - -0000008c <.L75>: - 8c: 00000097 auipc ra,0x0 - 90: 000080e7 jalr ra # 8c <.L75> - -00000094 <.LVL18>: - 94: 4692 lw a3,4(sp) - 96: 0542 sll a0,a0,0x10 - 98: 01045713 srl a4,s0,0x10 - 9c: 8f49 or a4,a4,a0 - -0000009e <.LVL19>: - 9e: 00d77863 bgeu a4,a3,ae <.L24> - a2: 9726 add a4,a4,s1 - a4: 00976563 bltu a4,s1,ae <.L24> - a8: 00d77363 bgeu a4,a3,ae <.L24> - ac: 9726 add a4,a4,s1 - -000000ae <.L24>: - ae: 40d707b3 sub a5,a4,a3 - b2: 853e mv a0,a5 - b4: 0104d593 srl a1,s1,0x10 - b8: c23e sw a5,4(sp) - -000000ba <.LVL23>: - ba: 00000097 auipc ra,0x0 - be: 000080e7 jalr ra # ba <.LVL23> - -000000c2 <.LVL24>: - c2: 01049593 sll a1,s1,0x10 - c6: 81c1 srl a1,a1,0x10 - c8: 00000097 auipc ra,0x0 - cc: 000080e7 jalr ra # c8 <.LVL24+0x6> - -000000d0 <.LVL25>: - d0: c42a sw a0,8(sp) - -000000d2 <.LVL26>: - d2: 4512 lw a0,4(sp) - -000000d4 <.LVL27>: - d4: 0104d593 srl a1,s1,0x10 - d8: 0442 sll s0,s0,0x10 - da: 00000097 auipc ra,0x0 - de: 000080e7 jalr ra # da <.LVL27+0x6> - -000000e2 <.LVL28>: - e2: 4722 lw a4,8(sp) - e4: 0542 sll a0,a0,0x10 - e6: 8041 srl s0,s0,0x10 - e8: 8c49 or s0,s0,a0 - -000000ea <.LVL29>: - ea: 00e47863 bgeu s0,a4,fa <.L27> - -000000ee <.LVL30>: - ee: 9426 add s0,s0,s1 - f0: 00946563 bltu s0,s1,fa <.L27> - f4: 00e47363 bgeu s0,a4,fa <.L27> - -000000f8 <.LVL32>: - f8: 9426 add s0,s0,s1 - -000000fa <.L27>: - fa: 4782 lw a5,0(sp) - -000000fc <.LBB25>: - fc: 8c19 sub s0,s0,a4 - -000000fe <.LBE25>: - fe: 4581 li a1,0 - 100: 00f45533 srl a0,s0,a5 - -00000104 <.L30>: - 104: 50c2 lw ra,48(sp) - 106: 5432 lw s0,44(sp) - 108: 54a2 lw s1,40(sp) - 10a: 03410113 add sp,sp,52 - 10e: 8082 ret - -00000110 <.L4>: - 110: 010002b7 lui t0,0x1000 - 114: 46c1 li a3,16 - 116: f0566de3 bltu a2,t0,30 <.L5> - 11a: 46e1 li a3,24 - 11c: bf11 j 30 <.L5> - -0000011e <.L3>: - 11e: 4701 li a4,0 - -00000120 <.LBE27>: - 120: ca09 beqz a2,132 <.L14> - -00000122 <.LBB28>: - 122: 6741 lui a4,0x10 - 124: 04e67f63 bgeu a2,a4,182 <.L15> - -00000128 <.LVL39>: - 128: 10063713 sltiu a4,a2,256 - 12c: 00174713 xor a4,a4,1 - 130: 070e sll a4,a4,0x3 - -00000132 <.L14>: - 132: 00e656b3 srl a3,a2,a4 - 136: 9336 add t1,t1,a3 - 138: 00034683 lbu a3,0(t1) - 13c: 9736 add a4,a4,a3 - -0000013e <.LVL41>: - 13e: 02000693 li a3,32 - 142: 40e687b3 sub a5,a3,a4 - 146: c03e sw a5,0(sp) - -00000148 <.LBE28>: - 148: 04e69463 bne a3,a4,190 <.L16> - 14c: 40c58633 sub a2,a1,a2 - -00000150 <.L17>: - 150: 01049793 sll a5,s1,0x10 - 154: 83c1 srl a5,a5,0x10 - 156: 8532 mv a0,a2 - 158: 0104d593 srl a1,s1,0x10 - 15c: c432 sw a2,8(sp) - 15e: c23e sw a5,4(sp) - -00000160 <.LVL44>: - 160: 00000097 auipc ra,0x0 - 164: 000080e7 jalr ra # 160 <.LVL44> - -00000168 <.LVL45>: - 168: 01049593 sll a1,s1,0x10 - 16c: 81c1 srl a1,a1,0x10 - 16e: 00000097 auipc ra,0x0 - 172: 000080e7 jalr ra # 16e <.LVL45+0x6> - -00000176 <.LVL46>: - 176: 4622 lw a2,8(sp) - 178: c22a sw a0,4(sp) - -0000017a <.LVL47>: - 17a: 0104d593 srl a1,s1,0x10 - 17e: 8532 mv a0,a2 - -00000180 <.LVL48>: - 180: b731 j 8c <.L75> - -00000182 <.L15>: - 182: 010006b7 lui a3,0x1000 - -00000186 <.LVL50>: - 186: 4741 li a4,16 - 188: fad665e3 bltu a2,a3,132 <.L14> - 18c: 4761 li a4,24 - 18e: b755 j 132 <.L14> - -00000190 <.L16>: - 190: 4782 lw a5,0(sp) - -00000192 <.LVL52>: - 192: 00f614b3 sll s1,a2,a5 - -00000196 <.LVL53>: - 196: 00e5d7b3 srl a5,a1,a4 - 19a: c23e sw a5,4(sp) - -0000019c <.LVL54>: - 19c: 4782 lw a5,0(sp) - -0000019e <.LVL55>: - 19e: 00e55733 srl a4,a0,a4 - -000001a2 <.LVL56>: - 1a2: 00f595b3 sll a1,a1,a5 - -000001a6 <.LVL57>: - 1a6: 00b767b3 or a5,a4,a1 - 1aa: c43e sw a5,8(sp) - -000001ac <.LVL58>: - 1ac: 4782 lw a5,0(sp) - -000001ae <.LBB31>: - 1ae: 0104d593 srl a1,s1,0x10 - -000001b2 <.LBE31>: - 1b2: 00f51433 sll s0,a0,a5 - -000001b6 <.LBB32>: - 1b6: 4512 lw a0,4(sp) - -000001b8 <.LVL61>: - 1b8: 01049793 sll a5,s1,0x10 - 1bc: 83c1 srl a5,a5,0x10 - 1be: c63e sw a5,12(sp) - -000001c0 <.LVL62>: - 1c0: 00000097 auipc ra,0x0 - 1c4: 000080e7 jalr ra # 1c0 <.LVL62> - -000001c8 <.LVL63>: - 1c8: 01049593 sll a1,s1,0x10 - 1cc: 81c1 srl a1,a1,0x10 - 1ce: 00000097 auipc ra,0x0 - 1d2: 000080e7 jalr ra # 1ce <.LVL63+0x6> - -000001d6 <.LVL64>: - 1d6: c62a sw a0,12(sp) - -000001d8 <.LVL65>: - 1d8: 4512 lw a0,4(sp) - -000001da <.LVL66>: - 1da: 0104d593 srl a1,s1,0x10 - 1de: 00000097 auipc ra,0x0 - 1e2: 000080e7 jalr ra # 1de <.LVL66+0x4> - -000001e6 <.LVL67>: - 1e6: 47a2 lw a5,8(sp) - 1e8: 46b2 lw a3,12(sp) - 1ea: 0542 sll a0,a0,0x10 - 1ec: 0107d713 srl a4,a5,0x10 - 1f0: 8f49 or a4,a4,a0 - -000001f2 <.LVL68>: - 1f2: 00d77863 bgeu a4,a3,202 <.L18> - -000001f6 <.LVL69>: - 1f6: 9726 add a4,a4,s1 - 1f8: 00976563 bltu a4,s1,202 <.L18> - 1fc: 00d77363 bgeu a4,a3,202 <.L18> - -00000200 <.LVL71>: - 200: 9726 add a4,a4,s1 - -00000202 <.L18>: - 202: 40d707b3 sub a5,a4,a3 - 206: 853e mv a0,a5 - 208: 0104d593 srl a1,s1,0x10 - 20c: c23e sw a5,4(sp) - -0000020e <.LVL73>: - 20e: 00000097 auipc ra,0x0 - 212: 000080e7 jalr ra # 20e <.LVL73> - -00000216 <.LVL74>: - 216: 01049593 sll a1,s1,0x10 - 21a: 81c1 srl a1,a1,0x10 - 21c: 00000097 auipc ra,0x0 - 220: 000080e7 jalr ra # 21c <.LVL74+0x6> - -00000224 <.LVL75>: - 224: c62a sw a0,12(sp) - -00000226 <.LVL76>: - 226: 4512 lw a0,4(sp) - -00000228 <.LVL77>: - 228: 0104d593 srl a1,s1,0x10 - 22c: 00000097 auipc ra,0x0 - 230: 000080e7 jalr ra # 22c <.LVL77+0x4> - -00000234 <.LVL78>: - 234: 00815603 lhu a2,8(sp) - 238: 4732 lw a4,12(sp) - 23a: 0542 sll a0,a0,0x10 - 23c: 8e49 or a2,a2,a0 - -0000023e <.LVL79>: - 23e: 00e67863 bgeu a2,a4,24e <.L21> - 242: 9626 add a2,a2,s1 - 244: 00966563 bltu a2,s1,24e <.L21> - 248: 00e67363 bgeu a2,a4,24e <.L21> - 24c: 9626 add a2,a2,s1 - -0000024e <.L21>: - 24e: 8e19 sub a2,a2,a4 - -00000250 <.LVL82>: - 250: b701 j 150 <.L17> - -00000252 <.L2>: - 252: ead5e9e3 bltu a1,a3,104 <.L30> - -00000256 <.LBB33>: - 256: 67c1 lui a5,0x10 - 258: 04f6f863 bgeu a3,a5,2a8 <.L32> - 25c: 1006b793 sltiu a5,a3,256 - 260: 0017c793 xor a5,a5,1 - 264: 078e sll a5,a5,0x3 - -00000266 <.L33>: - 266: 00000337 lui t1,0x0 - 26a: 00f6d2b3 srl t0,a3,a5 - 26e: 00030313 mv t1,t1 - 272: 9316 add t1,t1,t0 - 274: 00034303 lbu t1,0(t1) # 0 <__umoddi3> - 278: 933e add t1,t1,a5 - 27a: 02000793 li a5,32 - -0000027e <.LVL86>: - 27e: 406784b3 sub s1,a5,t1 - 282: c026 sw s1,0(sp) - -00000284 <.LBE33>: - 284: 02679963 bne a5,t1,2b6 <.L34> - 288: 00b6e463 bltu a3,a1,290 <.L35> - 28c: 00c56b63 bltu a0,a2,2a2 <.L36> - -00000290 <.L35>: - 290: 40c50633 sub a2,a0,a2 - -00000294 <.LVL89>: - 294: 40d586b3 sub a3,a1,a3 - -00000298 <.LVL90>: - 298: 00c53733 sltu a4,a0,a2 - 29c: 8432 mv s0,a2 - -0000029e <.LVL91>: - 29e: 40e68733 sub a4,a3,a4 - -000002a2 <.L36>: - 2a2: 8522 mv a0,s0 - -000002a4 <.LVL93>: - 2a4: 85ba mv a1,a4 - 2a6: bdb9 j 104 <.L30> - -000002a8 <.L32>: - 2a8: 01000337 lui t1,0x1000 - 2ac: 47c1 li a5,16 - 2ae: fa66ece3 bltu a3,t1,266 <.L33> - 2b2: 47e1 li a5,24 - 2b4: bf4d j 266 <.L33> - -000002b6 <.L34>: - 2b6: 4782 lw a5,0(sp) - 2b8: 0065d4b3 srl s1,a1,t1 - -000002bc <.LVL97>: - 2bc: 00665733 srl a4,a2,t1 - 2c0: 00f696b3 sll a3,a3,a5 - -000002c4 <.LVL98>: - 2c4: 00f617b3 sll a5,a2,a5 - 2c8: c43e sw a5,8(sp) - 2ca: 4782 lw a5,0(sp) - 2cc: 8f55 or a4,a4,a3 - -000002ce <.LVL99>: - 2ce: d21a sw t1,36(sp) - 2d0: 00f595b3 sll a1,a1,a5 - -000002d4 <.LVL100>: - 2d4: 006557b3 srl a5,a0,t1 - 2d8: 8fcd or a5,a5,a1 - 2da: c83e sw a5,16(sp) - -000002dc <.LVL101>: - 2dc: 4782 lw a5,0(sp) - -000002de <.LBB37>: - 2de: d03a sw a4,32(sp) - -000002e0 <.LBE37>: - 2e0: 00f517b3 sll a5,a0,a5 - 2e4: c63e sw a5,12(sp) - -000002e6 <.LBB38>: - 2e6: 01075793 srl a5,a4,0x10 - -000002ea <.LVL104>: - 2ea: c23e sw a5,4(sp) - -000002ec <.LVL105>: - 2ec: 4592 lw a1,4(sp) - 2ee: 01071793 sll a5,a4,0x10 - -000002f2 <.LVL106>: - 2f2: 83c1 srl a5,a5,0x10 - 2f4: 8526 mv a0,s1 - -000002f6 <.LVL107>: - 2f6: ca3e sw a5,20(sp) - -000002f8 <.LVL108>: - 2f8: 00000097 auipc ra,0x0 - 2fc: 000080e7 jalr ra # 2f8 <.LVL108> - -00000300 <.LVL109>: - 300: 85aa mv a1,a0 - 302: ce2a sw a0,28(sp) - 304: 4552 lw a0,20(sp) - -00000306 <.LVL110>: - 306: 00000097 auipc ra,0x0 - 30a: 000080e7 jalr ra # 306 <.LVL110> - -0000030e <.LVL111>: - 30e: 4592 lw a1,4(sp) - 310: cc2a sw a0,24(sp) - -00000312 <.LVL112>: - 312: 8526 mv a0,s1 - -00000314 <.LVL113>: - 314: 00000097 auipc ra,0x0 - 318: 000080e7 jalr ra # 314 <.LVL113> - -0000031c <.LVL114>: - 31c: 47c2 lw a5,16(sp) - 31e: 4672 lw a2,28(sp) - 320: 46e2 lw a3,24(sp) - 322: 0542 sll a0,a0,0x10 - 324: 0107d493 srl s1,a5,0x10 - -00000328 <.LVL115>: - 328: 8cc9 or s1,s1,a0 - -0000032a <.LVL116>: - 32a: 5702 lw a4,32(sp) - 32c: 5312 lw t1,36(sp) - 32e: 8432 mv s0,a2 - 330: 00d4fc63 bgeu s1,a3,348 <.L39> - -00000334 <.LVL117>: - 334: 94ba add s1,s1,a4 - -00000336 <.LVL118>: - 336: fff60413 add s0,a2,-1 - -0000033a <.LVL119>: - 33a: 00e4e763 bltu s1,a4,348 <.L39> - 33e: 00d4f563 bgeu s1,a3,348 <.L39> - 342: ffe60413 add s0,a2,-2 - 346: 94ba add s1,s1,a4 - -00000348 <.L39>: - 348: 4592 lw a1,4(sp) - 34a: 40d487b3 sub a5,s1,a3 - 34e: 853e mv a0,a5 - 350: d23a sw a4,36(sp) - 352: d01a sw t1,32(sp) - -00000354 <.LVL122>: - 354: cc3e sw a5,24(sp) - -00000356 <.LVL123>: - 356: 00000097 auipc ra,0x0 - 35a: 000080e7 jalr ra # 356 <.LVL123> - -0000035e <.LVL124>: - 35e: 85aa mv a1,a0 - 360: ce2a sw a0,28(sp) - 362: 4552 lw a0,20(sp) - -00000364 <.LVL125>: - 364: 00000097 auipc ra,0x0 - 368: 000080e7 jalr ra # 364 <.LVL125> - -0000036c <.LVL126>: - 36c: 4592 lw a1,4(sp) - 36e: 84aa mv s1,a0 - -00000370 <.LVL127>: - 370: 4562 lw a0,24(sp) - 372: 00000097 auipc ra,0x0 - 376: 000080e7 jalr ra # 372 <.LVL127+0x2> - -0000037a <.LVL128>: - 37a: 01015583 lhu a1,16(sp) - 37e: 4672 lw a2,28(sp) - 380: 0542 sll a0,a0,0x10 - 382: 8dc9 or a1,a1,a0 - -00000384 <.LVL129>: - 384: 5302 lw t1,32(sp) - 386: 5712 lw a4,36(sp) - 388: 8532 mv a0,a2 - 38a: 0095fc63 bgeu a1,s1,3a2 <.L42> - -0000038e <.LVL130>: - 38e: 95ba add a1,a1,a4 - -00000390 <.LVL131>: - 390: fff60513 add a0,a2,-1 - -00000394 <.LVL132>: - 394: 00e5e763 bltu a1,a4,3a2 <.L42> - 398: 0095f563 bgeu a1,s1,3a2 <.L42> - 39c: ffe60513 add a0,a2,-2 - 3a0: 95ba add a1,a1,a4 - -000003a2 <.L42>: - 3a2: 4622 lw a2,8(sp) - -000003a4 <.LBB44>: - 3a4: 01041793 sll a5,s0,0x10 - -000003a8 <.LBB45>: - 3a8: 66c1 lui a3,0x10 - -000003aa <.LBB46>: - 3aa: 8fc9 or a5,a5,a0 - -000003ac <.LBB47>: - 3ac: fff68393 add t2,a3,-1 # ffff <.LLST64+0xf395> - -000003b0 <.LBB48>: - 3b0: 409582b3 sub t0,a1,s1 - -000003b4 <.LBB49>: - 3b4: 0077f4b3 and s1,a5,t2 - -000003b8 <.LVL136>: - 3b8: 007673b3 and t2,a2,t2 - 3bc: 83c1 srl a5,a5,0x10 - -000003be <.LVL137>: - 3be: 01065413 srl s0,a2,0x10 - -000003c2 <.LBB40>: - 3c2: 8526 mv a0,s1 - -000003c4 <.LVL139>: - 3c4: 859e mv a1,t2 - 3c6: 00000097 auipc ra,0x0 - 3ca: 000080e7 jalr ra # 3c6 <.LVL139+0x2> - 3ce: c22a sw a0,4(sp) - -000003d0 <.LBB41>: - 3d0: 85a2 mv a1,s0 - 3d2: 8526 mv a0,s1 - -000003d4 <.LVL141>: - 3d4: 00000097 auipc ra,0x0 - 3d8: 000080e7 jalr ra # 3d4 <.LVL141> - 3dc: 84aa mv s1,a0 - -000003de <.LBB42>: - 3de: 859e mv a1,t2 - 3e0: 853e mv a0,a5 - 3e2: 00000097 auipc ra,0x0 - 3e6: 000080e7 jalr ra # 3e2 <.LBB42+0x4> - 3ea: 83aa mv t2,a0 - -000003ec <.LBB43>: - 3ec: 85a2 mv a1,s0 - 3ee: 853e mv a0,a5 - 3f0: 00000097 auipc ra,0x0 - 3f4: 000080e7 jalr ra # 3f0 <.LBB43+0x4> - -000003f8 <.LBE43>: - 3f8: 4792 lw a5,4(sp) - -000003fa <.LVL145>: - 3fa: 949e add s1,s1,t2 - -000003fc <.LVL146>: - 3fc: 0107d413 srl s0,a5,0x10 - 400: 9426 add s0,s0,s1 - -00000402 <.LVL147>: - 402: 00747463 bgeu s0,t2,40a <.L45> - 406: 66c1 lui a3,0x10 - -00000408 <.LVL148>: - 408: 9536 add a0,a0,a3 - -0000040a <.L45>: - 40a: 01045793 srl a5,s0,0x10 - 40e: 4692 lw a3,4(sp) - 410: 953e add a0,a0,a5 - -00000412 <.LVL150>: - 412: 67c1 lui a5,0x10 - -00000414 <.LVL151>: - 414: 17fd add a5,a5,-1 # ffff <.LLST64+0xf395> - -00000416 <.LVL152>: - 416: 8c7d and s0,s0,a5 - -00000418 <.LVL153>: - 418: 0442 sll s0,s0,0x10 - 41a: 8ff5 and a5,a5,a3 - -0000041c <.LVL154>: - 41c: 943e add s0,s0,a5 - -0000041e <.LBE49>: - 41e: 00a2e763 bltu t0,a0,42c <.L46> - 422: 00a29e63 bne t0,a0,43e <.L47> - 426: 47b2 lw a5,12(sp) - 428: 0087fb63 bgeu a5,s0,43e <.L47> - -0000042c <.L46>: - 42c: 47a2 lw a5,8(sp) - 42e: 40f407b3 sub a5,s0,a5 - 432: 00f436b3 sltu a3,s0,a5 - 436: 843e mv s0,a5 - -00000438 <.LVL156>: - 438: 00e687b3 add a5,a3,a4 - 43c: 8d1d sub a0,a0,a5 - -0000043e <.L47>: - 43e: 47b2 lw a5,12(sp) - 440: 40a285b3 sub a1,t0,a0 - 444: 40878433 sub s0,a5,s0 - -00000448 <.LVL158>: - 448: 0087b7b3 sltu a5,a5,s0 - 44c: 8d9d sub a1,a1,a5 - -0000044e <.LBE51>: - 44e: 4782 lw a5,0(sp) - 450: 00659333 sll t1,a1,t1 - -00000454 <.LVL160>: - 454: 00f45433 srl s0,s0,a5 - -00000458 <.LVL161>: - 458: 00836533 or a0,t1,s0 - -0000045c <.LVL162>: - 45c: 00f5d5b3 srl a1,a1,a5 - -00000460 <.LVL163>: - 460: b155 j 104 <.L30> - -_udivmoddi4.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__udivmoddi4>: - 0: 7179 add sp,sp,-48 - 2: d422 sw s0,40(sp) - 4: d606 sw ra,44(sp) - 6: d226 sw s1,36(sp) - 8: c03a sw a4,0(sp) - a: c436 sw a3,8(sp) - -0000000c <.LVL1>: - c: 842a mv s0,a0 - -0000000e <.LVL2>: - e: 832e mv t1,a1 - -00000010 <.LVL3>: - 10: 2c069f63 bnez a3,2ee <.L2> - 14: 000006b7 lui a3,0x0 - -00000018 <.LVL4>: - 18: 84b2 mv s1,a2 - 1a: 00068693 mv a3,a3 - 1e: 12c5f763 bgeu a1,a2,14c <.L3> - -00000022 <.LBB2>: - 22: 67c1 lui a5,0x10 - 24: 10f67d63 bgeu a2,a5,13e <.L4> - 28: 10063793 sltiu a5,a2,256 - 2c: 0017c793 xor a5,a5,1 - 30: 078e sll a5,a5,0x3 - -00000032 <.L5>: - 32: 00f652b3 srl t0,a2,a5 - 36: 9696 add a3,a3,t0 - 38: 0006c683 lbu a3,0(a3) # 0 <__udivmoddi4> - 3c: 97b6 add a5,a5,a3 - -0000003e <.LVL7>: - 3e: 02000693 li a3,32 - 42: 40f68733 sub a4,a3,a5 - -00000046 <.LVL8>: - 46: c23a sw a4,4(sp) - -00000048 <.LBE2>: - 48: 00f68c63 beq a3,a5,60 <.L6> - 4c: 00e59333 sll t1,a1,a4 - -00000050 <.LVL10>: - 50: 00f557b3 srl a5,a0,a5 - 54: 00e614b3 sll s1,a2,a4 - -00000058 <.LVL11>: - 58: 0067e333 or t1,a5,t1 - -0000005c <.LVL12>: - 5c: 00e51433 sll s0,a0,a4 - -00000060 <.L6>: - 60: 01049793 sll a5,s1,0x10 - 64: 83c1 srl a5,a5,0x10 - 66: 851a mv a0,t1 - -00000068 <.LVL14>: - 68: 0104d593 srl a1,s1,0x10 - 6c: c63e sw a5,12(sp) - -0000006e <.LVL15>: - 6e: ca1a sw t1,20(sp) - 70: 00000097 auipc ra,0x0 - 74: 000080e7 jalr ra # 70 <.LVL15+0x2> - -00000078 <.LVL16>: - 78: 85aa mv a1,a0 - 7a: c82a sw a0,16(sp) - 7c: 01049513 sll a0,s1,0x10 - -00000080 <.LVL17>: - 80: 8141 srl a0,a0,0x10 - 82: 00000097 auipc ra,0x0 - 86: 000080e7 jalr ra # 82 <.LVL17+0x2> - -0000008a <.LVL18>: - 8a: 4352 lw t1,20(sp) - 8c: c62a sw a0,12(sp) - -0000008e <.LVL19>: - 8e: 0104d593 srl a1,s1,0x10 - 92: 851a mv a0,t1 - -00000094 <.LVL20>: - 94: 00000097 auipc ra,0x0 - 98: 000080e7 jalr ra # 94 <.LVL20> - -0000009c <.LVL21>: - 9c: 42c2 lw t0,16(sp) - 9e: 4632 lw a2,12(sp) - a0: 0542 sll a0,a0,0x10 - a2: 01045693 srl a3,s0,0x10 - a6: 8ec9 or a3,a3,a0 - -000000a8 <.LVL22>: - a8: 8796 mv a5,t0 - aa: 00c6fc63 bgeu a3,a2,c2 <.L7> - ae: 96a6 add a3,a3,s1 - -000000b0 <.LVL23>: - b0: fff28793 add a5,t0,-1 - -000000b4 <.LVL24>: - b4: 0096e763 bltu a3,s1,c2 <.L7> - b8: 00c6f563 bgeu a3,a2,c2 <.L7> - bc: ffe28793 add a5,t0,-2 - c0: 96a6 add a3,a3,s1 - -000000c2 <.L7>: - c2: cc3e sw a5,24(sp) - -000000c4 <.LVL27>: - c4: 40c687b3 sub a5,a3,a2 - -000000c8 <.L87>: - c8: 853e mv a0,a5 - ca: 0104d593 srl a1,s1,0x10 - ce: c63e sw a5,12(sp) - -000000d0 <.LVL29>: - d0: 00000097 auipc ra,0x0 - d4: 000080e7 jalr ra # d0 <.LVL29> - -000000d8 <.LVL30>: - d8: 85aa mv a1,a0 - da: ca2a sw a0,20(sp) - -000000dc <.LVL31>: - dc: 01049513 sll a0,s1,0x10 - -000000e0 <.LVL32>: - e0: 8141 srl a0,a0,0x10 - e2: 00000097 auipc ra,0x0 - e6: 000080e7 jalr ra # e2 <.LVL32+0x2> - -000000ea <.LVL33>: - ea: c82a sw a0,16(sp) - -000000ec <.LVL34>: - ec: 4532 lw a0,12(sp) - -000000ee <.LVL35>: - ee: 0104d593 srl a1,s1,0x10 - f2: 0442 sll s0,s0,0x10 - -000000f4 <.LVL36>: - f4: 00000097 auipc ra,0x0 - f8: 000080e7 jalr ra # f4 <.LVL36> - -000000fc <.LVL37>: - fc: 4652 lw a2,20(sp) - fe: 46c2 lw a3,16(sp) - 100: 0542 sll a0,a0,0x10 - 102: 8041 srl s0,s0,0x10 - 104: 8c49 or s0,s0,a0 - -00000106 <.LVL38>: - 106: 47e2 lw a5,24(sp) - 108: 85b2 mv a1,a2 - 10a: 00d47c63 bgeu s0,a3,122 <.L27> - 10e: 9426 add s0,s0,s1 - -00000110 <.LVL39>: - 110: fff60593 add a1,a2,-1 - -00000114 <.LVL40>: - 114: 00946763 bltu s0,s1,122 <.L27> - 118: 00d47563 bgeu s0,a3,122 <.L27> - 11c: ffe60593 add a1,a2,-2 - 120: 9426 add s0,s0,s1 - -00000122 <.L27>: - 122: 4702 lw a4,0(sp) - -00000124 <.LBB5>: - 124: 07c2 sll a5,a5,0x10 - 126: 8c15 sub s0,s0,a3 - 128: 8fcd or a5,a5,a1 - -0000012a <.LBE5>: - 12a: 1a071a63 bnez a4,2de <.L30> - -0000012e <.L32>: - 12e: 4722 lw a4,8(sp) - -00000130 <.L31>: - 130: 50b2 lw ra,44(sp) - 132: 5422 lw s0,40(sp) - 134: 5492 lw s1,36(sp) - 136: 853e mv a0,a5 - 138: 85ba mv a1,a4 - 13a: 6145 add sp,sp,48 - -0000013c <.LVL47>: - 13c: 8082 ret - -0000013e <.L4>: - 13e: 010002b7 lui t0,0x1000 - 142: 47c1 li a5,16 - 144: ee5667e3 bltu a2,t0,32 <.L5> - 148: 47e1 li a5,24 - 14a: b5e5 j 32 <.L5> - -0000014c <.L3>: - 14c: 4781 li a5,0 - -0000014e <.LBE22>: - 14e: ca09 beqz a2,160 <.L14> - -00000150 <.LBB23>: - 150: 67c1 lui a5,0x10 - 152: 08f67d63 bgeu a2,a5,1ec <.L15> - -00000156 <.LVL51>: - 156: 10063793 sltiu a5,a2,256 - 15a: 0017c793 xor a5,a5,1 - 15e: 078e sll a5,a5,0x3 - -00000160 <.L14>: - 160: 00f65333 srl t1,a2,a5 - 164: 969a add a3,a3,t1 - 166: 0006c683 lbu a3,0(a3) - 16a: 97b6 add a5,a5,a3 - -0000016c <.LVL53>: - 16c: 02000693 li a3,32 - 170: 40f68733 sub a4,a3,a5 - -00000174 <.LVL54>: - 174: c23a sw a4,4(sp) - -00000176 <.LBE23>: - 176: 08f69263 bne a3,a5,1fa <.L16> - 17a: 40c58633 sub a2,a1,a2 - -0000017e <.LVL56>: - 17e: 4785 li a5,1 - -00000180 <.L80>: - 180: c43e sw a5,8(sp) - -00000182 <.LBB25>: - 182: 01049793 sll a5,s1,0x10 - -00000186 <.LVL59>: - 186: 83c1 srl a5,a5,0x10 - 188: 8532 mv a0,a2 - 18a: 0104d593 srl a1,s1,0x10 - 18e: c63e sw a5,12(sp) - -00000190 <.LVL60>: - 190: ca32 sw a2,20(sp) - 192: 00000097 auipc ra,0x0 - 196: 000080e7 jalr ra # 192 <.LVL60+0x2> - -0000019a <.LVL61>: - 19a: 85aa mv a1,a0 - 19c: c82a sw a0,16(sp) - 19e: 01049513 sll a0,s1,0x10 - -000001a2 <.LVL62>: - 1a2: 8141 srl a0,a0,0x10 - 1a4: 00000097 auipc ra,0x0 - 1a8: 000080e7 jalr ra # 1a4 <.LVL62+0x2> - -000001ac <.LVL63>: - 1ac: 4652 lw a2,20(sp) - 1ae: c62a sw a0,12(sp) - -000001b0 <.LVL64>: - 1b0: 0104d593 srl a1,s1,0x10 - 1b4: 8532 mv a0,a2 - -000001b6 <.LVL65>: - 1b6: 00000097 auipc ra,0x0 - 1ba: 000080e7 jalr ra # 1b6 <.LVL65> - -000001be <.LVL66>: - 1be: 42c2 lw t0,16(sp) - 1c0: 4332 lw t1,12(sp) - 1c2: 0542 sll a0,a0,0x10 - 1c4: 01045693 srl a3,s0,0x10 - 1c8: 8ec9 or a3,a3,a0 - -000001ca <.LVL67>: - 1ca: 8796 mv a5,t0 - 1cc: 0066fc63 bgeu a3,t1,1e4 <.L24> - 1d0: 96a6 add a3,a3,s1 - -000001d2 <.LVL68>: - 1d2: fff28793 add a5,t0,-1 # ffffff <.LLST46+0xfff21d> - -000001d6 <.LVL69>: - 1d6: 0096e763 bltu a3,s1,1e4 <.L24> - 1da: 0066f563 bgeu a3,t1,1e4 <.L24> - 1de: ffe28793 add a5,t0,-2 - 1e2: 96a6 add a3,a3,s1 - -000001e4 <.L24>: - 1e4: cc3e sw a5,24(sp) - -000001e6 <.LVL72>: - 1e6: 406687b3 sub a5,a3,t1 - 1ea: bdf9 j c8 <.L87> - -000001ec <.L15>: - 1ec: 01000337 lui t1,0x1000 - -000001f0 <.LVL74>: - 1f0: 47c1 li a5,16 - 1f2: f66667e3 bltu a2,t1,160 <.L14> - 1f6: 47e1 li a5,24 - 1f8: b7a5 j 160 <.L14> - -000001fa <.L16>: - 1fa: 4712 lw a4,4(sp) - -000001fc <.LVL76>: - 1fc: 00e614b3 sll s1,a2,a4 - -00000200 <.LVL77>: - 200: 00f5d733 srl a4,a1,a5 - 204: c43a sw a4,8(sp) - -00000206 <.LVL78>: - 206: 4712 lw a4,4(sp) - -00000208 <.LVL79>: - 208: 00f557b3 srl a5,a0,a5 - -0000020c <.LVL80>: - 20c: 00e595b3 sll a1,a1,a4 - -00000210 <.LVL81>: - 210: 00e51433 sll s0,a0,a4 - -00000214 <.LVL82>: - 214: 8fcd or a5,a5,a1 - -00000216 <.LBB27>: - 216: 4522 lw a0,8(sp) - -00000218 <.LBE27>: - 218: c63e sw a5,12(sp) - -0000021a <.LBB28>: - 21a: 01049793 sll a5,s1,0x10 - -0000021e <.LVL85>: - 21e: 83c1 srl a5,a5,0x10 - 220: 0104d593 srl a1,s1,0x10 - 224: c83e sw a5,16(sp) - -00000226 <.LVL86>: - 226: 00000097 auipc ra,0x0 - 22a: 000080e7 jalr ra # 226 <.LVL86> - -0000022e <.LVL87>: - 22e: 85aa mv a1,a0 - 230: ca2a sw a0,20(sp) - 232: 01049513 sll a0,s1,0x10 - -00000236 <.LVL88>: - 236: 8141 srl a0,a0,0x10 - 238: 00000097 auipc ra,0x0 - 23c: 000080e7 jalr ra # 238 <.LVL88+0x2> - -00000240 <.LVL89>: - 240: c82a sw a0,16(sp) - -00000242 <.LVL90>: - 242: 4522 lw a0,8(sp) - -00000244 <.LVL91>: - 244: 0104d593 srl a1,s1,0x10 - 248: 00000097 auipc ra,0x0 - 24c: 000080e7 jalr ra # 248 <.LVL91+0x4> - -00000250 <.LVL92>: - 250: 47b2 lw a5,12(sp) - 252: 4352 lw t1,20(sp) - 254: 4642 lw a2,16(sp) - 256: 0542 sll a0,a0,0x10 - 258: 83c1 srl a5,a5,0x10 - 25a: 8fc9 or a5,a5,a0 - -0000025c <.LVL93>: - 25c: 869a mv a3,t1 - 25e: 00c7fc63 bgeu a5,a2,276 <.L18> - 262: 97a6 add a5,a5,s1 - -00000264 <.LVL94>: - 264: fff30693 add a3,t1,-1 # ffffff <.LLST46+0xfff21d> - -00000268 <.LVL95>: - 268: 0097e763 bltu a5,s1,276 <.L18> - 26c: 00c7f563 bgeu a5,a2,276 <.L18> - 270: ffe30693 add a3,t1,-2 - 274: 97a6 add a5,a5,s1 - -00000276 <.L18>: - 276: 8f91 sub a5,a5,a2 - -00000278 <.LVL98>: - 278: 853e mv a0,a5 - 27a: 0104d593 srl a1,s1,0x10 - 27e: cc36 sw a3,24(sp) - -00000280 <.LVL99>: - 280: c43e sw a5,8(sp) - -00000282 <.LVL100>: - 282: 00000097 auipc ra,0x0 - 286: 000080e7 jalr ra # 282 <.LVL100> - -0000028a <.LVL101>: - 28a: 85aa mv a1,a0 - 28c: ca2a sw a0,20(sp) - 28e: 01049513 sll a0,s1,0x10 - -00000292 <.LVL102>: - 292: 8141 srl a0,a0,0x10 - 294: 00000097 auipc ra,0x0 - 298: 000080e7 jalr ra # 294 <.LVL102+0x2> - -0000029c <.LVL103>: - 29c: c82a sw a0,16(sp) - -0000029e <.LVL104>: - 29e: 4522 lw a0,8(sp) - -000002a0 <.LVL105>: - 2a0: 0104d593 srl a1,s1,0x10 - 2a4: 00000097 auipc ra,0x0 - 2a8: 000080e7 jalr ra # 2a4 <.LVL105+0x4> - -000002ac <.LVL106>: - 2ac: 00c15603 lhu a2,12(sp) - 2b0: 4352 lw t1,20(sp) - 2b2: 47c2 lw a5,16(sp) - 2b4: 0542 sll a0,a0,0x10 - 2b6: 8e49 or a2,a2,a0 - -000002b8 <.LVL107>: - 2b8: 46e2 lw a3,24(sp) - 2ba: 859a mv a1,t1 - 2bc: 00f67c63 bgeu a2,a5,2d4 <.L21> - 2c0: 9626 add a2,a2,s1 - -000002c2 <.LVL108>: - 2c2: fff30593 add a1,t1,-1 - -000002c6 <.LVL109>: - 2c6: 00966763 bltu a2,s1,2d4 <.L21> - 2ca: 00f67563 bgeu a2,a5,2d4 <.L21> - 2ce: ffe30593 add a1,t1,-2 - 2d2: 9626 add a2,a2,s1 - -000002d4 <.L21>: - 2d4: 06c2 sll a3,a3,0x10 - 2d6: 8e1d sub a2,a2,a5 - 2d8: 00b6e7b3 or a5,a3,a1 - 2dc: b555 j 180 <.L80> - -000002de <.L30>: - 2de: 4712 lw a4,4(sp) - 2e0: 00e45433 srl s0,s0,a4 - -000002e4 <.LVL114>: - 2e4: 4702 lw a4,0(sp) - 2e6: c300 sw s0,0(a4) - 2e8: 00072223 sw zero,4(a4) - 2ec: b589 j 12e <.L32> - -000002ee <.L2>: - 2ee: 00d5fb63 bgeu a1,a3,304 <.L33> - -000002f2 <.LVL116>: - 2f2: 4782 lw a5,0(sp) - 2f4: e781 bnez a5,2fc <.L34> - -000002f6 <.L35>: - 2f6: 4701 li a4,0 - -000002f8 <.LVL117>: - 2f8: 4781 li a5,0 - 2fa: bd1d j 130 <.L31> - -000002fc <.L34>: - 2fc: 4782 lw a5,0(sp) - 2fe: c388 sw a0,0(a5) - 300: c3cc sw a1,4(a5) - 302: bfd5 j 2f6 <.L35> - -00000304 <.L33>: - 304: 67c1 lui a5,0x10 - 306: 04f6fe63 bgeu a3,a5,362 <.L36> - 30a: 1006b793 sltiu a5,a3,256 - 30e: 0017c793 xor a5,a5,1 - 312: 078e sll a5,a5,0x3 - -00000314 <.L37>: - 314: 00000737 lui a4,0x0 - 318: 00f6d2b3 srl t0,a3,a5 - 31c: 00070713 mv a4,a4 - 320: 9716 add a4,a4,t0 - 322: 00074703 lbu a4,0(a4) # 0 <__udivmoddi4> - 326: 00f703b3 add t2,a4,a5 - 32a: 02000793 li a5,32 - -0000032e <.LVL121>: - 32e: 40778733 sub a4,a5,t2 - -00000332 <.LBE29>: - 332: 02779f63 bne a5,t2,370 <.L38> - 336: 00b6e563 bltu a3,a1,340 <.L39> - 33a: 4781 li a5,0 - 33c: 00c56c63 bltu a0,a2,354 <.L40> - -00000340 <.L39>: - 340: 40c50633 sub a2,a0,a2 - -00000344 <.LVL124>: - 344: 40d586b3 sub a3,a1,a3 - -00000348 <.LVL125>: - 348: 00c53333 sltu t1,a0,a2 - -0000034c <.LVL126>: - 34c: 8432 mv s0,a2 - -0000034e <.LVL127>: - 34e: 40668333 sub t1,a3,t1 - -00000352 <.LBE30>: - 352: 4785 li a5,1 - -00000354 <.L40>: - 354: 4682 lw a3,0(sp) - 356: dc068de3 beqz a3,130 <.L31> - 35a: c280 sw s0,0(a3) - 35c: 0066a223 sw t1,4(a3) - 360: bbc1 j 130 <.L31> - -00000362 <.L36>: - 362: 01000737 lui a4,0x1000 - -00000366 <.LVL131>: - 366: 47c1 li a5,16 - 368: fae6e6e3 bltu a3,a4,314 <.L37> - 36c: 47e1 li a5,24 - 36e: b75d j 314 <.L37> - -00000370 <.L38>: - 370: 007657b3 srl a5,a2,t2 - 374: 00e696b3 sll a3,a3,a4 - -00000378 <.LVL133>: - 378: 00d7e4b3 or s1,a5,a3 - -0000037c <.LVL134>: - 37c: 00e617b3 sll a5,a2,a4 - 380: 0075d433 srl s0,a1,t2 - -00000384 <.LVL135>: - 384: c23e sw a5,4(sp) - -00000386 <.LVL136>: - 386: 00e595b3 sll a1,a1,a4 - 38a: 007557b3 srl a5,a0,t2 - -0000038e <.LVL137>: - 38e: 8fcd or a5,a5,a1 - 390: c63e sw a5,12(sp) - -00000392 <.LVL138>: - 392: 00e517b3 sll a5,a0,a4 - -00000396 <.LVL139>: - 396: c43e sw a5,8(sp) - -00000398 <.LBB8>: - 398: 01049793 sll a5,s1,0x10 - -0000039c <.LVL141>: - 39c: 83c1 srl a5,a5,0x10 - 39e: 0104d593 srl a1,s1,0x10 - 3a2: 8522 mv a0,s0 - -000003a4 <.LBE8>: - 3a4: ce1e sw t2,28(sp) - 3a6: cc3a sw a4,24(sp) - -000003a8 <.LBB9>: - 3a8: c83e sw a5,16(sp) - -000003aa <.LVL143>: - 3aa: 00000097 auipc ra,0x0 - 3ae: 000080e7 jalr ra # 3aa <.LVL143> - -000003b2 <.LVL144>: - 3b2: 85aa mv a1,a0 - 3b4: ca2a sw a0,20(sp) - 3b6: 01049513 sll a0,s1,0x10 - -000003ba <.LVL145>: - 3ba: 8141 srl a0,a0,0x10 - 3bc: 00000097 auipc ra,0x0 - 3c0: 000080e7 jalr ra # 3bc <.LVL145+0x2> - -000003c4 <.LVL146>: - 3c4: c82a sw a0,16(sp) - -000003c6 <.LVL147>: - 3c6: 0104d593 srl a1,s1,0x10 - 3ca: 8522 mv a0,s0 - -000003cc <.LVL148>: - 3cc: 00000097 auipc ra,0x0 - 3d0: 000080e7 jalr ra # 3cc <.LVL148> - -000003d4 <.LVL149>: - 3d4: 47b2 lw a5,12(sp) - 3d6: 4652 lw a2,20(sp) - 3d8: 46c2 lw a3,16(sp) - 3da: 0107d413 srl s0,a5,0x10 - -000003de <.LVL150>: - 3de: 0542 sll a0,a0,0x10 - 3e0: 8c49 or s0,s0,a0 - -000003e2 <.LVL151>: - 3e2: 4762 lw a4,24(sp) - 3e4: 43f2 lw t2,28(sp) - 3e6: 87b2 mv a5,a2 - 3e8: 00d47c63 bgeu s0,a3,400 <.L45> - -000003ec <.LVL152>: - 3ec: 9426 add s0,s0,s1 - -000003ee <.LVL153>: - 3ee: fff60793 add a5,a2,-1 - -000003f2 <.LVL154>: - 3f2: 00946763 bltu s0,s1,400 <.L45> - 3f6: 00d47563 bgeu s0,a3,400 <.L45> - 3fa: ffe60793 add a5,a2,-2 - 3fe: 9426 add s0,s0,s1 - -00000400 <.L45>: - 400: d03e sw a5,32(sp) - 402: 40d407b3 sub a5,s0,a3 - -00000406 <.LVL157>: - 406: 853e mv a0,a5 - 408: 0104d593 srl a1,s1,0x10 - 40c: ce3a sw a4,28(sp) - 40e: cc1e sw t2,24(sp) - 410: c83e sw a5,16(sp) - -00000412 <.LVL158>: - 412: 00000097 auipc ra,0x0 - 416: 000080e7 jalr ra # 412 <.LVL158> - -0000041a <.LVL159>: - 41a: 85aa mv a1,a0 - 41c: ca2a sw a0,20(sp) - 41e: 01049513 sll a0,s1,0x10 - -00000422 <.LVL160>: - 422: 8141 srl a0,a0,0x10 - 424: 00000097 auipc ra,0x0 - 428: 000080e7 jalr ra # 424 <.LVL160+0x2> - -0000042c <.LVL161>: - 42c: 842a mv s0,a0 - -0000042e <.LVL162>: - 42e: 4542 lw a0,16(sp) - 430: 0104d593 srl a1,s1,0x10 - 434: 00000097 auipc ra,0x0 - 438: 000080e7 jalr ra # 434 <.LVL162+0x6> - -0000043c <.LVL163>: - 43c: 00c15583 lhu a1,12(sp) - 440: 4652 lw a2,20(sp) - 442: 0542 sll a0,a0,0x10 - 444: 8dc9 or a1,a1,a0 - -00000446 <.LVL164>: - 446: 43e2 lw t2,24(sp) - 448: 4772 lw a4,28(sp) - 44a: 5782 lw a5,32(sp) - 44c: 8532 mv a0,a2 - 44e: 0085fc63 bgeu a1,s0,466 <.L48> - -00000452 <.LVL165>: - 452: 95a6 add a1,a1,s1 - -00000454 <.LVL166>: - 454: fff60513 add a0,a2,-1 - -00000458 <.LVL167>: - 458: 0095e763 bltu a1,s1,466 <.L48> - 45c: 0085f563 bgeu a1,s0,466 <.L48> - 460: ffe60513 add a0,a2,-2 - 464: 95a6 add a1,a1,s1 - -00000466 <.L48>: - 466: 408586b3 sub a3,a1,s0 - -0000046a <.LBB10>: - 46a: 4592 lw a1,4(sp) - -0000046c <.LBB15>: - 46c: c636 sw a3,12(sp) - -0000046e <.LVL171>: - 46e: 07c2 sll a5,a5,0x10 - -00000470 <.LBB16>: - 470: 66c1 lui a3,0x10 - -00000472 <.LBB17>: - 472: 8fc9 or a5,a5,a0 - -00000474 <.LBB18>: - 474: fff68313 add t1,a3,-1 # ffff <.LLST46+0xf21d> - 478: 0067f433 and s0,a5,t1 - -0000047c <.LVL174>: - 47c: 0065f333 and t1,a1,t1 - -00000480 <.LVL175>: - 480: 0105d293 srl t0,a1,0x10 - -00000484 <.LBB11>: - 484: 8522 mv a0,s0 - -00000486 <.LVL176>: - 486: 859a mv a1,t1 - 488: 00000097 auipc ra,0x0 - 48c: 000080e7 jalr ra # 488 <.LVL176+0x2> - 490: c82a sw a0,16(sp) - -00000492 <.LBB12>: - 492: 8596 mv a1,t0 - 494: 8522 mv a0,s0 - -00000496 <.LVL178>: - 496: 00000097 auipc ra,0x0 - 49a: 000080e7 jalr ra # 496 <.LVL178> - 49e: 842a mv s0,a0 - -000004a0 <.LBB13>: - 4a0: 859a mv a1,t1 - 4a2: 0107d513 srl a0,a5,0x10 - -000004a6 <.LVL180>: - 4a6: 00000097 auipc ra,0x0 - 4aa: 000080e7 jalr ra # 4a6 <.LVL180> - -000004ae <.LVL181>: - 4ae: 832a mv t1,a0 - -000004b0 <.LBB14>: - 4b0: 8596 mv a1,t0 - 4b2: 0107d513 srl a0,a5,0x10 - -000004b6 <.LVL183>: - 4b6: 00000097 auipc ra,0x0 - 4ba: 000080e7 jalr ra # 4b6 <.LVL183> - -000004be <.LBE14>: - 4be: 45c2 lw a1,16(sp) - 4c0: 941a add s0,s0,t1 - -000004c2 <.LVL185>: - 4c2: 0105d693 srl a3,a1,0x10 - 4c6: 96a2 add a3,a3,s0 - -000004c8 <.LVL186>: - 4c8: 0066f463 bgeu a3,t1,4d0 <.L51> - 4cc: 6641 lui a2,0x10 - -000004ce <.LVL187>: - 4ce: 9532 add a0,a0,a2 - -000004d0 <.L51>: - 4d0: 0106d613 srl a2,a3,0x10 - 4d4: 45c2 lw a1,16(sp) - 4d6: 9532 add a0,a0,a2 - -000004d8 <.LVL189>: - 4d8: 6641 lui a2,0x10 - -000004da <.LVL190>: - 4da: 167d add a2,a2,-1 # ffff <.LLST46+0xf21d> - -000004dc <.LVL191>: - 4dc: 8ef1 and a3,a3,a2 - -000004de <.LVL192>: - 4de: 06c2 sll a3,a3,0x10 - 4e0: 8e6d and a2,a2,a1 - -000004e2 <.LVL193>: - 4e2: 96b2 add a3,a3,a2 - -000004e4 <.LBE18>: - 4e4: 4632 lw a2,12(sp) - 4e6: 00a66763 bltu a2,a0,4f4 <.L52> - 4ea: 00a61f63 bne a2,a0,508 <.L53> - 4ee: 4622 lw a2,8(sp) - 4f0: 00d67c63 bgeu a2,a3,508 <.L53> - -000004f4 <.L52>: - 4f4: 4612 lw a2,4(sp) - 4f6: 17fd add a5,a5,-1 # ffff <.LLST46+0xf21d> - -000004f8 <.LBB19>: - 4f8: 40c68633 sub a2,a3,a2 - 4fc: 00c6b5b3 sltu a1,a3,a2 - 500: 86b2 mv a3,a2 - -00000502 <.LVL196>: - 502: 00958633 add a2,a1,s1 - -00000506 <.LVL197>: - 506: 8d11 sub a0,a0,a2 - -00000508 <.L53>: - 508: 4602 lw a2,0(sp) - 50a: c60d beqz a2,534 <.L56> - -0000050c <.LBB20>: - 50c: 4622 lw a2,8(sp) - 50e: 40d606b3 sub a3,a2,a3 - -00000512 <.LVL199>: - 512: 4632 lw a2,12(sp) - 514: 40a604b3 sub s1,a2,a0 - -00000518 <.LVL200>: - 518: 4622 lw a2,8(sp) - 51a: 00d63633 sltu a2,a2,a3 - 51e: 8c91 sub s1,s1,a2 - -00000520 <.LBE20>: - 520: 00749633 sll a2,s1,t2 - 524: 00e6d6b3 srl a3,a3,a4 - -00000528 <.LVL202>: - 528: 00e4d4b3 srl s1,s1,a4 - -0000052c <.LVL203>: - 52c: 4702 lw a4,0(sp) - -0000052e <.LVL204>: - 52e: 8ed1 or a3,a3,a2 - 530: c314 sw a3,0(a4) - 532: c344 sw s1,4(a4) - -00000534 <.L56>: - 534: 4701 li a4,0 - 536: beed j 130 <.L31> - -_udiv_w_sdiv.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__udiv_w_sdiv>: - 0: 4501 li a0,0 - -00000002 <.LVL1>: - 2: 8082 ret - -adddf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__adddf3>: - 0: 00100737 lui a4,0x100 - 4: 177d add a4,a4,-1 # fffff <.LLST32+0xfef49> - -00000006 <.LBE2>: - 6: 1131 add sp,sp,-20 - -00000008 <.LBB3>: - 8: 00b777b3 and a5,a4,a1 - -0000000c <.LBB4>: - c: 0146d313 srl t1,a3,0x14 - 10: 8f75 and a4,a4,a3 - -00000012 <.LBE4>: - 12: c622 sw s0,12(sp) - 14: c426 sw s1,8(sp) - -00000016 <.LBB5>: - 16: 01f5d413 srl s0,a1,0x1f - 1a: 0145d493 srl s1,a1,0x14 - -0000001e <.LBE5>: - 1e: 00379593 sll a1,a5,0x3 - 22: 01d55793 srl a5,a0,0x1d - -00000026 <.LBB7>: - 26: 7ff4f493 and s1,s1,2047 - -0000002a <.LBE7>: - 2a: 8fcd or a5,a5,a1 - -0000002c <.LBB9>: - 2c: 7ff37313 and t1,t1,2047 - -00000030 <.LBE9>: - 30: 01d65593 srl a1,a2,0x1d - 34: 070e sll a4,a4,0x3 - 36: c806 sw ra,16(sp) - -00000038 <.LBB11>: - 38: 82fd srl a3,a3,0x1f - -0000003a <.LBE11>: - 3a: 050e sll a0,a0,0x3 - -0000003c <.LBB13>: - 3c: 8dd9 or a1,a1,a4 - -0000003e <.LVL6>: - 3e: 060e sll a2,a2,0x3 - -00000040 <.LVL7>: - 40: 406482b3 sub t0,s1,t1 - 44: 26d41963 bne s0,a3,2b6 <.L2> - -00000048 <.LBB15>: - 48: 12505263 blez t0,16c <.L3> - -0000004c <.LVL9>: - 4c: 06031e63 bnez t1,c8 <.L4> - 50: 00c5e733 or a4,a1,a2 - 54: 5a070c63 beqz a4,60c <.L107> - 58: fff28713 add a4,t0,-1 - -0000005c <.LVL10>: - 5c: ef39 bnez a4,ba <.L6> - -0000005e <.L160>: - 5e: 962a add a2,a2,a0 - -00000060 <.LVL12>: - 60: 00a63733 sltu a4,a2,a0 - -00000064 <.LVL13>: - 64: 95be add a1,a1,a5 - -00000066 <.LVL14>: - 66: 00e587b3 add a5,a1,a4 - -0000006a <.LBE16>: - 6a: 00800737 lui a4,0x800 - 6e: 8f7d and a4,a4,a5 - -00000070 <.LBB17>: - 70: 8532 mv a0,a2 - -00000072 <.LBE17>: - 72: 22071463 bnez a4,29a <.L98> - -00000076 <.L153>: - 76: 4485 li s1,1 - -00000078 <.L5>: - 78: 00757713 and a4,a0,7 - 7c: cf01 beqz a4,94 <.L87> - 7e: 00f57713 and a4,a0,15 - 82: 4691 li a3,4 - 84: 00d70863 beq a4,a3,94 <.L87> - -00000088 <.LBB57>: - 88: 00450713 add a4,a0,4 - 8c: 00a736b3 sltu a3,a4,a0 - 90: 97b6 add a5,a5,a3 - -00000092 <.LVL19>: - 92: 853a mv a0,a4 - -00000094 <.L87>: - 94: 00800737 lui a4,0x800 - 98: 8f7d and a4,a4,a5 - 9a: 56070f63 beqz a4,618 <.L90> - -0000009e <.LVL21>: - 9e: 0485 add s1,s1,1 - -000000a0 <.LVL22>: - a0: 7ff00713 li a4,2047 - a4: 08e48463 beq s1,a4,12c <.L124> - a8: ff800737 lui a4,0xff800 - ac: 177d add a4,a4,-1 # ff7fffff <.LLST32+0xff7fef49> - ae: 8ff9 and a5,a5,a4 - -000000b0 <.LVL23>: - b0: 810d srl a0,a0,0x3 - -000000b2 <.LVL24>: - b2: 01d79713 sll a4,a5,0x1d - b6: 8f49 or a4,a4,a0 - b8: ab11 j 5cc <.L157> - -000000ba <.L6>: - ba: 7ff00693 li a3,2047 - -000000be <.LVL26>: - be: 06d29963 bne t0,a3,130 <.L10> - -000000c2 <.L121>: - c2: 7ff00493 li s1,2047 - -000000c6 <.LVL28>: - c6: bf4d j 78 <.L5> - -000000c8 <.L4>: - c8: 7ff00713 li a4,2047 - cc: fae486e3 beq s1,a4,78 <.L5> - -000000d0 <.LVL30>: - d0: 03800713 li a4,56 - d4: 06574263 blt a4,t0,138 <.L95> - d8: 00800737 lui a4,0x800 - dc: 8dd9 or a1,a1,a4 - -000000de <.LVL31>: - de: 8716 mv a4,t0 - -000000e0 <.L12>: - e0: 46fd li a3,31 - e2: 04e6ce63 blt a3,a4,13e <.L13> - e6: 02000313 li t1,32 - -000000ea <.LVL33>: - ea: 40e30333 sub t1,t1,a4 - ee: 006596b3 sll a3,a1,t1 - f2: 00e652b3 srl t0,a2,a4 - f6: 00661333 sll t1,a2,t1 - fa: 0056e6b3 or a3,a3,t0 - fe: 00603333 snez t1,t1 - 102: 0066e6b3 or a3,a3,t1 - -00000106 <.LVL34>: - 106: 00e5d733 srl a4,a1,a4 - -0000010a <.L11>: - 10a: 9536 add a0,a0,a3 - -0000010c <.LVL36>: - 10c: 973e add a4,a4,a5 - -0000010e <.LVL37>: - 10e: 00d536b3 sltu a3,a0,a3 - -00000112 <.LVL38>: - 112: 00d707b3 add a5,a4,a3 - -00000116 <.L17>: - 116: 00800737 lui a4,0x800 - 11a: 8f7d and a4,a4,a5 - 11c: df31 beqz a4,78 <.L5> - -0000011e <.LVL40>: - 11e: 0485 add s1,s1,1 - -00000120 <.LVL41>: - 120: 7ff00713 li a4,2047 - 124: 16e49c63 bne s1,a4,29c <.L9> - -00000128 <.L35>: - 128: 7ff00493 li s1,2047 - -0000012c <.L124>: - 12c: 4781 li a5,0 - 12e: a299 j 274 <.L158> - -00000130 <.L10>: - 130: 03800693 li a3,56 - 134: fae6d6e3 bge a3,a4,e0 <.L12> - -00000138 <.L95>: - 138: 4701 li a4,0 - 13a: 4685 li a3,1 - 13c: b7f9 j 10a <.L11> - -0000013e <.L13>: - 13e: fe070693 add a3,a4,-32 # 7fffe0 <.LLST32+0x7fef2a> - 142: 02000293 li t0,32 - 146: 00d5d6b3 srl a3,a1,a3 - 14a: 4301 li t1,0 - -0000014c <.LVL46>: - 14c: 00570863 beq a4,t0,15c <.L14> - 150: 04000313 li t1,64 - 154: 40e30333 sub t1,t1,a4 - 158: 00659333 sll t1,a1,t1 - -0000015c <.L14>: - 15c: 00c36333 or t1,t1,a2 - 160: 00603333 snez t1,t1 - 164: 0066e6b3 or a3,a3,t1 - -00000168 <.LVL47>: - 168: 4701 li a4,0 - -0000016a <.LVL48>: - 16a: b745 j 10a <.L11> - -0000016c <.L3>: - 16c: 0a028c63 beqz t0,224 <.L18> - 170: 409306b3 sub a3,t1,s1 - -00000174 <.LVL50>: - 174: e085 bnez s1,194 <.L19> - 176: 00a7e733 or a4,a5,a0 - 17a: 48070263 beqz a4,5fe <.L97> - 17e: fff68713 add a4,a3,-1 - -00000182 <.LVL51>: - 182: ec070ee3 beqz a4,5e <.L160> - 186: 7ff00293 li t0,2047 - 18a: 04569f63 bne a3,t0,1e8 <.L146> - -0000018e <.L105>: - 18e: 87ae mv a5,a1 - -00000190 <.LVL53>: - 190: 8532 mv a0,a2 - -00000192 <.LVL54>: - 192: bf05 j c2 <.L121> - -00000194 <.L19>: - 194: 7ff00713 li a4,2047 - 198: fee30be3 beq t1,a4,18e <.L105> - -0000019c <.LVL56>: - 19c: 03800713 li a4,56 - 1a0: 04d74863 blt a4,a3,1f0 <.L102> - 1a4: 00800737 lui a4,0x800 - 1a8: 8fd9 or a5,a5,a4 - -000001aa <.LVL57>: - 1aa: 8736 mv a4,a3 - -000001ac <.L25>: - 1ac: 46fd li a3,31 - 1ae: 04e6c463 blt a3,a4,1f6 <.L26> - 1b2: 02000293 li t0,32 - 1b6: 40e282b3 sub t0,t0,a4 - 1ba: 005796b3 sll a3,a5,t0 - 1be: 00e553b3 srl t2,a0,a4 - 1c2: 005512b3 sll t0,a0,t0 - 1c6: 0076e6b3 or a3,a3,t2 - 1ca: 005032b3 snez t0,t0 - 1ce: 0056e6b3 or a3,a3,t0 - -000001d2 <.LVL59>: - 1d2: 00e7d733 srl a4,a5,a4 - -000001d6 <.L24>: - 1d6: 9636 add a2,a2,a3 - -000001d8 <.LVL61>: - 1d8: 972e add a4,a4,a1 - -000001da <.LVL62>: - 1da: 00d636b3 sltu a3,a2,a3 - -000001de <.LVL63>: - 1de: 8532 mv a0,a2 - -000001e0 <.LVL64>: - 1e0: 00d707b3 add a5,a4,a3 - -000001e4 <.LBB73>: - 1e4: 849a mv s1,t1 - -000001e6 <.LBB74>: - 1e6: bf05 j 116 <.L17> - -000001e8 <.L146>: - 1e8: 03800693 li a3,56 - 1ec: fce6d0e3 bge a3,a4,1ac <.L25> - -000001f0 <.L102>: - 1f0: 4701 li a4,0 - 1f2: 4685 li a3,1 - 1f4: b7cd j 1d6 <.L24> - -000001f6 <.L26>: - 1f6: fe070693 add a3,a4,-32 # 7fffe0 <.LLST32+0x7fef2a> - 1fa: 02000393 li t2,32 - 1fe: 00d7d6b3 srl a3,a5,a3 - 202: 4281 li t0,0 - 204: 00770863 beq a4,t2,214 <.L27> - 208: 04000293 li t0,64 - 20c: 40e282b3 sub t0,t0,a4 - 210: 005792b3 sll t0,a5,t0 - -00000214 <.L27>: - 214: 00a2e2b3 or t0,t0,a0 - 218: 005032b3 snez t0,t0 - 21c: 0056e6b3 or a3,a3,t0 - -00000220 <.LVL70>: - 220: 4701 li a4,0 - -00000222 <.LVL71>: - 222: bf55 j 1d6 <.L24> - -00000224 <.L18>: - 224: 00148713 add a4,s1,1 - 228: 7fe77693 and a3,a4,2046 - -0000022c <.LVL73>: - 22c: e6b1 bnez a3,278 <.L30> - 22e: 00a7e733 or a4,a5,a0 - 232: e885 bnez s1,262 <.L31> - -00000234 <.LVL74>: - 234: 3c070963 beqz a4,606 <.L104> - 238: 00c5e733 or a4,a1,a2 - 23c: e2070ee3 beqz a4,78 <.L5> - -00000240 <.LBB25>: - 240: 962a add a2,a2,a0 - -00000242 <.LVL75>: - 242: 00a63733 sltu a4,a2,a0 - 246: 95be add a1,a1,a5 - -00000248 <.LVL76>: - 248: 00e587b3 add a5,a1,a4 - -0000024c <.LBE25>: - 24c: 00800737 lui a4,0x800 - 250: 8f7d and a4,a4,a5 - -00000252 <.LBB26>: - 252: 8532 mv a0,a2 - -00000254 <.LBE26>: - 254: e20702e3 beqz a4,78 <.L5> - 258: ff800737 lui a4,0xff800 - 25c: 177d add a4,a4,-1 # ff7fffff <.LLST32+0xff7fef49> - 25e: 8ff9 and a5,a5,a4 - -00000260 <.LVL79>: - 260: bd19 j 76 <.L153> - -00000262 <.L31>: - 262: d715 beqz a4,18e <.L105> - 264: 8e4d or a2,a2,a1 - -00000266 <.LVL81>: - 266: e4060ee3 beqz a2,c2 <.L121> - -0000026a <.L156>: - 26a: 4401 li s0,0 - -0000026c <.LBB76>: - 26c: 7ff00493 li s1,2047 - -00000270 <.LBB77>: - 270: 000807b7 lui a5,0x80 - -00000274 <.L158>: - 274: 4701 li a4,0 - 276: aea1 j 5ce <.L34> - -00000278 <.L30>: - 278: 7ff00693 li a3,2047 - 27c: ead706e3 beq a4,a3,128 <.L35> - 280: 962a add a2,a2,a0 - -00000282 <.LBB29>: - 282: 00a63533 sltu a0,a2,a0 - -00000286 <.LVL88>: - 286: 95be add a1,a1,a5 - -00000288 <.LVL89>: - 288: 95aa add a1,a1,a0 - -0000028a <.LBE29>: - 28a: 01f59513 sll a0,a1,0x1f - 28e: 8205 srl a2,a2,0x1 - -00000290 <.LVL90>: - 290: 8d51 or a0,a0,a2 - 292: 0015d793 srl a5,a1,0x1 - -00000296 <.LVL91>: - 296: 84ba mv s1,a4 - -00000298 <.LVL92>: - 298: b3c5 j 78 <.L5> - -0000029a <.L98>: - 29a: 4489 li s1,2 - -0000029c <.L9>: - 29c: ff800737 lui a4,0xff800 - 2a0: 177d add a4,a4,-1 # ff7fffff <.LLST32+0xff7fef49> - 2a2: 8ff9 and a5,a5,a4 - -000002a4 <.LVL95>: - 2a4: 00155713 srl a4,a0,0x1 - 2a8: 8905 and a0,a0,1 - 2aa: 8f49 or a4,a4,a0 - 2ac: 01f79513 sll a0,a5,0x1f - 2b0: 8d59 or a0,a0,a4 - 2b2: 8385 srl a5,a5,0x1 - 2b4: b3d1 j 78 <.L5> - -000002b6 <.L2>: - 2b6: 0c505d63 blez t0,390 <.L38> - -000002ba <.LVL97>: - 2ba: 02031f63 bnez t1,2f8 <.L39> - 2be: 00c5e733 or a4,a1,a2 - 2c2: 34070563 beqz a4,60c <.L107> - 2c6: fff28713 add a4,t0,-1 - -000002ca <.LVL98>: - 2ca: ef01 bnez a4,2e2 <.L40> - -000002cc <.LBB33>: - 2cc: 40c50633 sub a2,a0,a2 - -000002d0 <.LVL99>: - 2d0: 00c53733 sltu a4,a0,a2 - -000002d4 <.LVL100>: - 2d4: 40b785b3 sub a1,a5,a1 - -000002d8 <.LVL101>: - 2d8: 8532 mv a0,a2 - -000002da <.LVL102>: - 2da: 40e587b3 sub a5,a1,a4 - -000002de <.L150>: - 2de: 4485 li s1,1 - -000002e0 <.LBB81>: - 2e0: a0b5 j 34c <.L43> - -000002e2 <.L40>: - 2e2: 7ff00693 li a3,2047 - -000002e6 <.LVL106>: - 2e6: dcd28ee3 beq t0,a3,c2 <.L121> - -000002ea <.L44>: - 2ea: 03800693 li a3,56 - 2ee: 02e6d163 bge a3,a4,310 <.L46> - -000002f2 <.L110>: - 2f2: 4701 li a4,0 - 2f4: 4685 li a3,1 - 2f6: a091 j 33a <.L45> - -000002f8 <.L39>: - 2f8: 7ff00713 li a4,2047 - 2fc: d6e48ee3 beq s1,a4,78 <.L5> - -00000300 <.LVL109>: - 300: 03800713 li a4,56 - 304: fe5747e3 blt a4,t0,2f2 <.L110> - 308: 00800737 lui a4,0x800 - 30c: 8dd9 or a1,a1,a4 - -0000030e <.LVL110>: - 30e: 8716 mv a4,t0 - -00000310 <.L46>: - 310: 46fd li a3,31 - 312: 04e6c863 blt a3,a4,362 <.L47> - 316: 02000313 li t1,32 - -0000031a <.LVL112>: - 31a: 40e30333 sub t1,t1,a4 - 31e: 006596b3 sll a3,a1,t1 - 322: 00e652b3 srl t0,a2,a4 - 326: 00661333 sll t1,a2,t1 - 32a: 0056e6b3 or a3,a3,t0 - 32e: 00603333 snez t1,t1 - 332: 0066e6b3 or a3,a3,t1 - -00000336 <.LVL113>: - 336: 00e5d733 srl a4,a1,a4 - -0000033a <.L45>: - 33a: 40d506b3 sub a3,a0,a3 - -0000033e <.LVL115>: - 33e: 00d53633 sltu a2,a0,a3 - 342: 40e78733 sub a4,a5,a4 - -00000346 <.LVL116>: - 346: 8536 mv a0,a3 - -00000348 <.LVL117>: - 348: 40c707b3 sub a5,a4,a2 - -0000034c <.L43>: - 34c: 00800337 lui t1,0x800 - 350: 0067f733 and a4,a5,t1 - 354: d20702e3 beqz a4,78 <.L5> - -00000358 <.LBB36>: - 358: 137d add t1,t1,-1 # 7fffff <.LLST32+0x7fef49> - 35a: 0067f333 and t1,a5,t1 - -0000035e <.LVL119>: - 35e: 82aa mv t0,a0 - 360: a24d j 502 <.L77> - -00000362 <.L47>: - 362: fe070693 add a3,a4,-32 # 7fffe0 <.LLST32+0x7fef2a> - 366: 02000293 li t0,32 - 36a: 00d5d6b3 srl a3,a1,a3 - 36e: 4301 li t1,0 - -00000370 <.LVL121>: - 370: 00570863 beq a4,t0,380 <.L48> - 374: 04000313 li t1,64 - 378: 40e30333 sub t1,t1,a4 - 37c: 00659333 sll t1,a1,t1 - -00000380 <.L48>: - 380: 00c36333 or t1,t1,a2 - 384: 00603333 snez t1,t1 - 388: 0066e6b3 or a3,a3,t1 - -0000038c <.LVL122>: - 38c: 4701 li a4,0 - -0000038e <.LVL123>: - 38e: b775 j 33a <.L45> - -00000390 <.L38>: - 390: 0c028863 beqz t0,460 <.L51> - 394: 409302b3 sub t0,t1,s1 - -00000398 <.LVL125>: - 398: e895 bnez s1,3cc <.L52> - 39a: 00a7e733 or a4,a5,a0 - 39e: 26070963 beqz a4,610 <.L112> - 3a2: fff28713 add a4,t0,-1 - -000003a6 <.LVL126>: - 3a6: eb11 bnez a4,3ba <.L53> - -000003a8 <.LBB43>: - 3a8: 40a60533 sub a0,a2,a0 - -000003ac <.LVL128>: - 3ac: 8d9d sub a1,a1,a5 - -000003ae <.LVL129>: - 3ae: 00a63633 sltu a2,a2,a0 - -000003b2 <.LVL130>: - 3b2: 40c587b3 sub a5,a1,a2 - -000003b6 <.LBE43>: - 3b6: 8436 mv s0,a3 - -000003b8 <.LVL132>: - 3b8: b71d j 2de <.L150> - -000003ba <.L53>: - 3ba: 7ff00393 li t2,2047 - 3be: 06729363 bne t0,t2,424 <.L148> - -000003c2 <.L114>: - 3c2: 87ae mv a5,a1 - -000003c4 <.LVL135>: - 3c4: 8532 mv a0,a2 - -000003c6 <.LBB83>: - 3c6: 7ff00493 li s1,2047 - -000003ca <.LVL137>: - 3ca: a855 j 47e <.L152> - -000003cc <.L52>: - 3cc: 7ff00713 li a4,2047 - 3d0: fee309e3 beq t1,a4,3c2 <.L114> - -000003d4 <.LVL139>: - 3d4: 03800713 li a4,56 - 3d8: 04574a63 blt a4,t0,42c <.L116> - 3dc: 00800737 lui a4,0x800 - 3e0: 8fd9 or a5,a5,a4 - -000003e2 <.LVL140>: - 3e2: 8716 mv a4,t0 - -000003e4 <.L58>: - 3e4: 42fd li t0,31 - 3e6: 04e2c663 blt t0,a4,432 <.L59> - 3ea: 02000393 li t2,32 - 3ee: 40e383b3 sub t2,t2,a4 - 3f2: 00e55433 srl s0,a0,a4 - -000003f6 <.LVL142>: - 3f6: 007792b3 sll t0,a5,t2 - 3fa: 007513b3 sll t2,a0,t2 - 3fe: 0082e2b3 or t0,t0,s0 - 402: 007033b3 snez t2,t2 - 406: 0072e533 or a0,t0,t2 - 40a: 00e7d733 srl a4,a5,a4 - -0000040e <.L57>: - 40e: 40a60533 sub a0,a2,a0 - -00000412 <.LVL145>: - 412: 40e58733 sub a4,a1,a4 - -00000416 <.LVL146>: - 416: 00a63633 sltu a2,a2,a0 - -0000041a <.LVL147>: - 41a: 40c707b3 sub a5,a4,a2 - -0000041e <.LBB84>: - 41e: 849a mv s1,t1 - -00000420 <.LBB85>: - 420: 8436 mv s0,a3 - 422: b72d j 34c <.L43> - -00000424 <.L148>: - 424: 03800293 li t0,56 - 428: fae2dee3 bge t0,a4,3e4 <.L58> - -0000042c <.L116>: - 42c: 4701 li a4,0 - 42e: 4505 li a0,1 - -00000430 <.LVL152>: - 430: bff9 j 40e <.L57> - -00000432 <.L59>: - 432: fe070293 add t0,a4,-32 # 7fffe0 <.LLST32+0x7fef2a> - 436: 02000413 li s0,32 - -0000043a <.LVL154>: - 43a: 0057d2b3 srl t0,a5,t0 - 43e: 4381 li t2,0 - 440: 00870863 beq a4,s0,450 <.L60> - 444: 04000393 li t2,64 - 448: 40e383b3 sub t2,t2,a4 - 44c: 007793b3 sll t2,a5,t2 - -00000450 <.L60>: - 450: 00a3e3b3 or t2,t2,a0 - 454: 007033b3 snez t2,t2 - 458: 0072e533 or a0,t0,t2 - -0000045c <.LVL155>: - 45c: 4701 li a4,0 - -0000045e <.LVL156>: - 45e: bf45 j 40e <.L57> - -00000460 <.L51>: - 460: 00148713 add a4,s1,1 - 464: 7fe77713 and a4,a4,2046 - 468: e72d bnez a4,4d2 <.L63> - -0000046a <.LBB86>: - 46a: 00a7e333 or t1,a5,a0 - -0000046e <.LVL158>: - 46e: 00c5e733 or a4,a1,a2 - -00000472 <.LBB87>: - 472: e4a9 bnez s1,4bc <.L64> - -00000474 <.LVL159>: - 474: 00031763 bnez t1,482 <.L65> - -00000478 <.LVL160>: - 478: c77d beqz a4,566 <.L161> - -0000047a <.LBE87>: - 47a: 87ae mv a5,a1 - -0000047c <.LVL161>: - 47c: 8532 mv a0,a2 - -0000047e <.L152>: - 47e: 8436 mv s0,a3 - -00000480 <.LVL163>: - 480: bee5 j 78 <.L5> - -00000482 <.L65>: - 482: be070be3 beqz a4,78 <.L5> - -00000486 <.LBB47>: - 486: 40c502b3 sub t0,a0,a2 - -0000048a <.LVL165>: - 48a: 00553733 sltu a4,a0,t0 - 48e: 40b78333 sub t1,a5,a1 - 492: 40e30333 sub t1,t1,a4 - -00000496 <.LBE47>: - 496: 00800737 lui a4,0x800 - 49a: 00e37733 and a4,t1,a4 - 49e: cb09 beqz a4,4b0 <.L68> - -000004a0 <.LBB48>: - 4a0: 40a60533 sub a0,a2,a0 - -000004a4 <.LVL168>: - 4a4: 8d9d sub a1,a1,a5 - -000004a6 <.LVL169>: - 4a6: 00a63633 sltu a2,a2,a0 - -000004aa <.LVL170>: - 4aa: 40c587b3 sub a5,a1,a2 - -000004ae <.LBE48>: - 4ae: bfc1 j 47e <.L152> - -000004b0 <.L68>: - 4b0: 0062e733 or a4,t0,t1 - 4b4: cb4d beqz a4,566 <.L161> - 4b6: 879a mv a5,t1 - -000004b8 <.LBB49>: - 4b8: 8516 mv a0,t0 - -000004ba <.LVL174>: - 4ba: be7d j 78 <.L5> - -000004bc <.L64>: - 4bc: 00031863 bnez t1,4cc <.L71> - 4c0: 16070c63 beqz a4,638 <.L120> - -000004c4 <.LBE89>: - 4c4: 87ae mv a5,a1 - -000004c6 <.LVL176>: - 4c6: 8532 mv a0,a2 - -000004c8 <.LBB91>: - 4c8: 8436 mv s0,a3 - -000004ca <.LVL178>: - 4ca: bee5 j c2 <.L121> - -000004cc <.L71>: - 4cc: be070be3 beqz a4,c2 <.L121> - 4d0: bb69 j 26a <.L156> - -000004d2 <.L63>: - 4d2: 40c50733 sub a4,a0,a2 - 4d6: 00e533b3 sltu t2,a0,a4 - 4da: 40b78333 sub t1,a5,a1 - -000004de <.LVL181>: - 4de: 40730333 sub t1,t1,t2 - -000004e2 <.LBE50>: - 4e2: 008003b7 lui t2,0x800 - 4e6: 007373b3 and t2,t1,t2 - -000004ea <.LBB51>: - 4ea: 82ba mv t0,a4 - -000004ec <.LBE51>: - 4ec: 06038963 beqz t2,55e <.L74> - -000004f0 <.LBB52>: - 4f0: 40a60533 sub a0,a2,a0 - -000004f4 <.LVL183>: - 4f4: 8d9d sub a1,a1,a5 - -000004f6 <.LVL184>: - 4f6: 00a63633 sltu a2,a2,a0 - -000004fa <.LVL185>: - 4fa: 82aa mv t0,a0 - -000004fc <.LVL186>: - 4fc: 40c58333 sub t1,a1,a2 - -00000500 <.LBE52>: - 500: 8436 mv s0,a3 - -00000502 <.L77>: - 502: 06030463 beqz t1,56a <.L78> - 506: 851a mv a0,t1 - 508: c216 sw t0,4(sp) - 50a: c01a sw t1,0(sp) - 50c: 00000097 auipc ra,0x0 - 510: 000080e7 jalr ra # 50c <.L77+0xa> - -00000514 <.LVL189>: - 514: 4302 lw t1,0(sp) - 516: 4292 lw t0,4(sp) - 518: ff850793 add a5,a0,-8 - -0000051c <.L79>: - 51c: 02000713 li a4,32 - 520: 8f1d sub a4,a4,a5 - 522: 00f31333 sll t1,t1,a5 - -00000526 <.LVL191>: - 526: 00e2d733 srl a4,t0,a4 - 52a: 00676733 or a4,a4,t1 - -0000052e <.LVL192>: - 52e: 00f29333 sll t1,t0,a5 - -00000532 <.LVL193>: - 532: 0a97cf63 blt a5,s1,5f0 <.L81> - 536: 8f85 sub a5,a5,s1 - -00000538 <.LVL194>: - 538: 00178613 add a2,a5,1 # 80001 <.LLST32+0x7ef4b> - -0000053c <.L82>: - 53c: 02000693 li a3,32 - 540: 8e91 sub a3,a3,a2 - 542: 00d71533 sll a0,a4,a3 - 546: 00c357b3 srl a5,t1,a2 - 54a: 00d316b3 sll a3,t1,a3 - 54e: 8d5d or a0,a0,a5 - 550: 00d036b3 snez a3,a3 - 554: 8d55 or a0,a0,a3 - -00000556 <.LVL196>: - 556: 00c757b3 srl a5,a4,a2 - -0000055a <.L154>: - 55a: 4481 li s1,0 - -0000055c <.LVL198>: - 55c: be31 j 78 <.L5> - -0000055e <.L74>: - 55e: 00676733 or a4,a4,t1 - 562: f345 bnez a4,502 <.L77> - 564: 4481 li s1,0 - -00000566 <.L161>: - 566: 4781 li a5,0 - -00000568 <.LVL201>: - 568: a0f1 j 634 <.L155> - -0000056a <.L78>: - 56a: 8516 mv a0,t0 - 56c: c21a sw t1,4(sp) - 56e: c016 sw t0,0(sp) - 570: 00000097 auipc ra,0x0 - 574: 000080e7 jalr ra # 570 <.L78+0x6> - -00000578 <.LVL203>: - 578: 01850793 add a5,a0,24 - -0000057c <.LVL204>: - 57c: 46fd li a3,31 - 57e: 4282 lw t0,0(sp) - 580: 4312 lw t1,4(sp) - 582: f8f6dde3 bge a3,a5,51c <.L79> - -00000586 <.LVL205>: - 586: 1561 add a0,a0,-8 - 588: 00a29733 sll a4,t0,a0 - -0000058c <.LVL206>: - 58c: 0297c963 blt a5,s1,5be <.L83> - 590: 8f85 sub a5,a5,s1 - -00000592 <.LVL207>: - 592: 00178613 add a2,a5,1 - -00000596 <.LVL208>: - 596: fac6d3e3 bge a3,a2,53c <.L82> - 59a: 1785 add a5,a5,-31 - 59c: 02000693 li a3,32 - 5a0: 00f757b3 srl a5,a4,a5 - 5a4: 4501 li a0,0 - 5a6: 00d60763 beq a2,a3,5b4 <.L85> - 5aa: 04000513 li a0,64 - 5ae: 8d11 sub a0,a0,a2 - 5b0: 00a71533 sll a0,a4,a0 - -000005b4 <.L85>: - 5b4: 00a03533 snez a0,a0 - 5b8: 8d5d or a0,a0,a5 - -000005ba <.LVL209>: - 5ba: 4781 li a5,0 - 5bc: bf79 j 55a <.L154> - -000005be <.L83>: - 5be: 8c9d sub s1,s1,a5 - 5c0: ff8007b7 lui a5,0xff800 - -000005c4 <.LVL212>: - 5c4: 17fd add a5,a5,-1 # ff7fffff <.LLST32+0xff7fef49> - 5c6: 8ff9 and a5,a5,a4 - -000005c8 <.LBB94>: - 5c8: 01d79713 sll a4,a5,0x1d - -000005cc <.L157>: - 5cc: 838d srl a5,a5,0x3 - -000005ce <.L34>: - 5ce: 04d2 sll s1,s1,0x14 - 5d0: 7ff006b7 lui a3,0x7ff00 - 5d4: 07b2 sll a5,a5,0xc - -000005d6 <.LVL216>: - 5d6: 83b1 srl a5,a5,0xc - 5d8: 8cf5 and s1,s1,a3 - 5da: 8cdd or s1,s1,a5 - 5dc: 047e sll s0,s0,0x1f - -000005de <.LVL217>: - 5de: 0084e7b3 or a5,s1,s0 - -000005e2 <.LBE95>: - 5e2: 40c2 lw ra,16(sp) - 5e4: 4432 lw s0,12(sp) - 5e6: 44a2 lw s1,8(sp) - 5e8: 853a mv a0,a4 - 5ea: 85be mv a1,a5 - 5ec: 0151 add sp,sp,20 - 5ee: 8082 ret - -000005f0 <.L81>: - 5f0: 8c9d sub s1,s1,a5 - 5f2: ff8007b7 lui a5,0xff800 - -000005f6 <.LVL221>: - 5f6: 17fd add a5,a5,-1 # ff7fffff <.LLST32+0xff7fef49> - 5f8: 8ff9 and a5,a5,a4 - -000005fa <.LVL222>: - 5fa: 851a mv a0,t1 - 5fc: bcb5 j 78 <.L5> - -000005fe <.L97>: - 5fe: 87ae mv a5,a1 - -00000600 <.LVL224>: - 600: 8532 mv a0,a2 - -00000602 <.LBB98>: - 602: 84b6 mv s1,a3 - -00000604 <.LVL226>: - 604: bc95 j 78 <.L5> - -00000606 <.L104>: - 606: 87ae mv a5,a1 - -00000608 <.LVL228>: - 608: 8532 mv a0,a2 - -0000060a <.LVL229>: - 60a: b4bd j 78 <.L5> - -0000060c <.L107>: - 60c: 8496 mv s1,t0 - -0000060e <.LVL231>: - 60e: b4ad j 78 <.L5> - -00000610 <.L112>: - 610: 87ae mv a5,a1 - -00000612 <.LVL233>: - 612: 8532 mv a0,a2 - -00000614 <.LBB102>: - 614: 8496 mv s1,t0 - -00000616 <.LVL235>: - 616: b5a5 j 47e <.L152> - -00000618 <.L90>: - 618: 01d79693 sll a3,a5,0x1d - 61c: 810d srl a0,a0,0x3 - -0000061e <.LVL237>: - 61e: 7ff00613 li a2,2047 - 622: 8ec9 or a3,a3,a0 - -00000624 <.LVL238>: - 624: 838d srl a5,a5,0x3 - 626: 00c49f63 bne s1,a2,644 <.L125> - -0000062a <.LVL240>: - 62a: 8edd or a3,a3,a5 - 62c: 000807b7 lui a5,0x80 - 630: ae068ce3 beqz a3,128 <.L35> - -00000634 <.L155>: - 634: 4401 li s0,0 - 636: bf61 j 5ce <.L34> - -00000638 <.L120>: - 638: 4401 li s0,0 - -0000063a <.LBB104>: - 63a: 7ff00493 li s1,2047 - -0000063e <.LBB105>: - 63e: 000807b7 lui a5,0x80 - -00000642 <.LVL244>: - 642: b771 j 5ce <.L34> - -00000644 <.L125>: - 644: 8736 mv a4,a3 - 646: b761 j 5ce <.L34> - -divdf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divdf3>: - 0: fc410113 add sp,sp,-60 - 4: d826 sw s1,48(sp) - 6: 84ae mv s1,a1 - -00000008 <.LBB3>: - 8: 00c59713 sll a4,a1,0xc - c: 01f4d793 srl a5,s1,0x1f - 10: 81d1 srl a1,a1,0x14 - -00000012 <.LBE3>: - 12: da22 sw s0,52(sp) - 14: 832a mv t1,a0 - 16: 842a mv s0,a0 - -00000018 <.LBB4>: - 18: dc06 sw ra,56(sp) - -0000001a <.LBB5>: - 1a: 7ff5f513 and a0,a1,2047 - -0000001e <.LVL2>: - 1e: c03e sw a5,0(sp) - 20: 8331 srl a4,a4,0xc - -00000022 <.LBE5>: - 22: c549 beqz a0,ac <.L2> - 24: 7ff00793 li a5,2047 - 28: 0ef50f63 beq a0,a5,126 <.L3> - -0000002c <.LVL4>: - 2c: 070e sll a4,a4,0x3 - -0000002e <.LVL5>: - 2e: 01d35793 srl a5,t1,0x1d - 32: 8fd9 or a5,a5,a4 - 34: 00800737 lui a4,0x800 - 38: 8fd9 or a5,a5,a4 - -0000003a <.LVL6>: - 3a: 00331413 sll s0,t1,0x3 - -0000003e <.LVL7>: - 3e: c0150593 add a1,a0,-1023 - -00000042 <.L103>: - 42: 4481 li s1,0 - -00000044 <.L4>: - 44: 00c69713 sll a4,a3,0xc - 48: 00c75393 srl t2,a4,0xc - -0000004c <.LVL10>: - 4c: 0146d713 srl a4,a3,0x14 - 50: 82fd srl a3,a3,0x1f - 52: 7ff77713 and a4,a4,2047 - -00000056 <.LVL11>: - 56: c236 sw a3,4(sp) - -00000058 <.LBE10>: - 58: cb65 beqz a4,148 <.L9> - 5a: 7ff00693 li a3,2047 - 5e: 16d70563 beq a4,a3,1c8 <.L10> - -00000062 <.LVL13>: - 62: 00339513 sll a0,t2,0x3 - 66: 01d65693 srl a3,a2,0x1d - 6a: 8ec9 or a3,a3,a0 - 6c: 00800537 lui a0,0x800 - 70: 00a6e3b3 or t2,a3,a0 - -00000074 <.LVL14>: - 74: 00361693 sll a3,a2,0x3 - -00000078 <.LVL15>: - 78: c0170613 add a2,a4,-1023 # 7ffc01 <.LLST25+0x7fec19> - -0000007c <.L104>: - 7c: 4501 li a0,0 - -0000007e <.L11>: - 7e: 4702 lw a4,0(sp) - 80: 4312 lw t1,4(sp) - 82: 00674733 xor a4,a4,t1 - 86: c63a sw a4,12(sp) - -00000088 <.LVL18>: - 88: 40c58733 sub a4,a1,a2 - -0000008c <.LVL19>: - 8c: c43a sw a4,8(sp) - -0000008e <.LVL20>: - 8e: 00249713 sll a4,s1,0x2 - -00000092 <.LVL21>: - 92: 8f49 or a4,a4,a0 - 94: 177d add a4,a4,-1 - 96: 4639 li a2,14 - -00000098 <.LVL22>: - 98: 16e66963 bltu a2,a4,20a <.L16> - 9c: 00000637 lui a2,0x0 - a0: 070a sll a4,a4,0x2 - a2: 00060613 mv a2,a2 - a6: 9732 add a4,a4,a2 - a8: 4318 lw a4,0(a4) - aa: 8702 jr a4 - -000000ac <.L2>: - ac: 006767b3 or a5,a4,t1 - b0: c3d9 beqz a5,136 <.L71> - -000000b2 <.LBB15>: - b2: c836 sw a3,16(sp) - b4: c632 sw a2,12(sp) - b6: c329 beqz a4,f8 <.L5> - b8: 853a mv a0,a4 - -000000ba <.LVL24>: - ba: c41a sw t1,8(sp) - bc: c23a sw a4,4(sp) - be: 00000097 auipc ra,0x0 - c2: 000080e7 jalr ra # be <.LVL24+0x4> - -000000c6 <.LVL25>: - c6: 4712 lw a4,4(sp) - c8: 4322 lw t1,8(sp) - ca: 4632 lw a2,12(sp) - cc: 46c2 lw a3,16(sp) - ce: 82aa mv t0,a0 - -000000d0 <.LVL26>: - d0: ff550393 add t2,a0,-11 # 7ffff5 <.LLST25+0x7ff00d> - -000000d4 <.L6>: - d4: 47f5 li a5,29 - d6: ff828593 add a1,t0,-8 - da: 407787b3 sub a5,a5,t2 - de: 00b71733 sll a4,a4,a1 - -000000e2 <.LVL28>: - e2: 00f357b3 srl a5,t1,a5 - e6: 8fd9 or a5,a5,a4 - -000000e8 <.LVL29>: - e8: 00b31733 sll a4,t1,a1 - -000000ec <.L8>: - ec: c0d00593 li a1,-1011 - f0: 405585b3 sub a1,a1,t0 - -000000f4 <.LVL31>: - f4: 843a mv s0,a4 - f6: b7b1 j 42 <.L103> - -000000f8 <.L5>: - f8: 851a mv a0,t1 - -000000fa <.LVL33>: - fa: c43a sw a4,8(sp) - fc: c21a sw t1,4(sp) - fe: 00000097 auipc ra,0x0 - 102: 000080e7 jalr ra # fe <.LVL33+0x4> - -00000106 <.LVL34>: - 106: 01550393 add t2,a0,21 - 10a: 47f1 li a5,28 - 10c: 4312 lw t1,4(sp) - 10e: 4722 lw a4,8(sp) - 110: 4632 lw a2,12(sp) - 112: 46c2 lw a3,16(sp) - 114: 02050293 add t0,a0,32 - -00000118 <.LVL35>: - 118: fa77dee3 bge a5,t2,d4 <.L6> - -0000011c <.LVL36>: - 11c: ff850793 add a5,a0,-8 - 120: 00f317b3 sll a5,t1,a5 - -00000124 <.LVL37>: - 124: b7e1 j ec <.L8> - -00000126 <.L3>: - 126: 006767b3 or a5,a4,t1 - 12a: cb91 beqz a5,13e <.L72> - -0000012c <.LBB16>: - 12c: 87ba mv a5,a4 - 12e: 7ff00593 li a1,2047 - -00000132 <.LBE16>: - 132: 448d li s1,3 - 134: bf01 j 44 <.L4> - -00000136 <.L71>: - 136: 4401 li s0,0 - 138: 4581 li a1,0 - -0000013a <.LBE17>: - 13a: 4485 li s1,1 - 13c: b721 j 44 <.L4> - -0000013e <.L72>: - 13e: 4401 li s0,0 - 140: 7ff00593 li a1,2047 - -00000144 <.LBE18>: - 144: 4489 li s1,2 - 146: bdfd j 44 <.L4> - -00000148 <.L9>: - 148: 00c3e6b3 or a3,t2,a2 - 14c: c6d1 beqz a3,1d8 <.L73> - -0000014e <.LBB19>: - 14e: 04038563 beqz t2,198 <.L12> - 152: 851e mv a0,t2 - 154: ca32 sw a2,20(sp) - 156: c82e sw a1,16(sp) - 158: c63e sw a5,12(sp) - 15a: c41e sw t2,8(sp) - 15c: 00000097 auipc ra,0x0 - 160: 000080e7 jalr ra # 15c <.LBB19+0xe> - -00000164 <.LVL40>: - 164: 43a2 lw t2,8(sp) - 166: 47b2 lw a5,12(sp) - 168: 45c2 lw a1,16(sp) - 16a: 4652 lw a2,20(sp) - 16c: 86aa mv a3,a0 - -0000016e <.LVL41>: - 16e: ff550293 add t0,a0,-11 - -00000172 <.L13>: - 172: 4775 li a4,29 - 174: ff868513 add a0,a3,-8 - 178: 40570733 sub a4,a4,t0 - 17c: 00a393b3 sll t2,t2,a0 - -00000180 <.LVL43>: - 180: 00e65733 srl a4,a2,a4 - 184: 00776733 or a4,a4,t2 - -00000188 <.LVL44>: - 188: 00a613b3 sll t2,a2,a0 - -0000018c <.L15>: - 18c: c0d00613 li a2,-1011 - 190: 8e15 sub a2,a2,a3 - -00000192 <.LVL46>: - 192: 869e mv a3,t2 - 194: 83ba mv t2,a4 - -00000196 <.LVL47>: - 196: b5dd j 7c <.L104> - -00000198 <.L12>: - 198: 8532 mv a0,a2 - 19a: ca1e sw t2,20(sp) - 19c: c82e sw a1,16(sp) - 19e: c63e sw a5,12(sp) - 1a0: c432 sw a2,8(sp) - 1a2: 00000097 auipc ra,0x0 - 1a6: 000080e7 jalr ra # 1a2 <.L12+0xa> - -000001aa <.LVL49>: - 1aa: 01550293 add t0,a0,21 - 1ae: 4771 li a4,28 - 1b0: 4622 lw a2,8(sp) - 1b2: 47b2 lw a5,12(sp) - 1b4: 45c2 lw a1,16(sp) - 1b6: 43d2 lw t2,20(sp) - 1b8: 02050693 add a3,a0,32 - -000001bc <.LVL50>: - 1bc: fa575be3 bge a4,t0,172 <.L13> - -000001c0 <.LVL51>: - 1c0: 1561 add a0,a0,-8 - 1c2: 00a61733 sll a4,a2,a0 - -000001c6 <.LVL52>: - 1c6: b7d9 j 18c <.L15> - -000001c8 <.L10>: - 1c8: 00c3e6b3 or a3,t2,a2 - 1cc: ca91 beqz a3,1e0 <.L74> - 1ce: 86b2 mv a3,a2 - 1d0: 450d li a0,3 - -000001d2 <.LBB20>: - 1d2: 7ff00613 li a2,2047 - -000001d6 <.LVL54>: - 1d6: b565 j 7e <.L11> - -000001d8 <.L73>: - 1d8: 4381 li t2,0 - -000001da <.LVL56>: - 1da: 4601 li a2,0 - -000001dc <.LBE20>: - 1dc: 4505 li a0,1 - 1de: b545 j 7e <.L11> - -000001e0 <.L74>: - 1e0: 4381 li t2,0 - -000001e2 <.LVL59>: - 1e2: 7ff00613 li a2,2047 - -000001e6 <.LBE21>: - 1e6: 4509 li a0,2 - 1e8: bd59 j 7e <.L11> - -000001ea <.L19>: - 1ea: 4702 lw a4,0(sp) - 1ec: 83be mv t2,a5 - -000001ee <.LVL62>: - 1ee: 86a2 mv a3,s0 - -000001f0 <.LVL63>: - 1f0: c63a sw a4,12(sp) - -000001f2 <.L23>: - 1f2: 4789 li a5,2 - 1f4: 46f48f63 beq s1,a5,672 <.L88> - 1f8: 478d li a5,3 - 1fa: 46f48563 beq s1,a5,664 <.L86> - 1fe: 4785 li a5,1 - 200: 34f49363 bne s1,a5,546 <.L44> - -00000204 <.L90>: - 204: 4381 li t2,0 - 206: 4681 li a3,0 - 208: a13d j 636 <.L105> - -0000020a <.L16>: - 20a: 00f3e663 bltu t2,a5,216 <.L24> - 20e: 3a779963 bne a5,t2,5c0 <.L25> - 212: 3ad46763 bltu s0,a3,5c0 <.L25> - -00000216 <.L24>: - 216: 01f79593 sll a1,a5,0x1f - -0000021a <.LVL68>: - 21a: 00145613 srl a2,s0,0x1 - -0000021e <.LVL69>: - 21e: 01f41713 sll a4,s0,0x1f - -00000222 <.LVL70>: - 222: 8385 srl a5,a5,0x1 - -00000224 <.LVL71>: - 224: 00c5e433 or s0,a1,a2 - -00000228 <.L26>: - 228: 00839613 sll a2,t2,0x8 - 22c: d03a sw a4,32(sp) - -0000022e <.LVL73>: - 22e: 00869713 sll a4,a3,0x8 - -00000232 <.LVL74>: - 232: c03a sw a4,0(sp) - -00000234 <.LBB31>: - 234: 01065713 srl a4,a2,0x10 - -00000238 <.LBE31>: - 238: 0186d593 srl a1,a3,0x18 - -0000023c <.LBB33>: - 23c: c23a sw a4,4(sp) - -0000023e <.LBE33>: - 23e: 00c5e333 or t1,a1,a2 - -00000242 <.LBB35>: - 242: 4592 lw a1,4(sp) - 244: 01031713 sll a4,t1,0x10 - -00000248 <.LVL78>: - 248: 8341 srl a4,a4,0x10 - 24a: 853e mv a0,a5 - -0000024c <.LVL79>: - 24c: ce1a sw t1,28(sp) - 24e: cc3a sw a4,24(sp) - -00000250 <.LVL80>: - 250: ca3e sw a5,20(sp) - 252: 00000097 auipc ra,0x0 - 256: 000080e7 jalr ra # 252 <.LVL80+0x2> - -0000025a <.LVL81>: - 25a: 85aa mv a1,a0 - 25c: c82a sw a0,16(sp) - 25e: 4562 lw a0,24(sp) - -00000260 <.LVL82>: - 260: 00000097 auipc ra,0x0 - 264: 000080e7 jalr ra # 260 <.LVL82> - -00000268 <.LVL83>: - 268: 47d2 lw a5,20(sp) - 26a: 4592 lw a1,4(sp) - 26c: 84aa mv s1,a0 - -0000026e <.LVL84>: - 26e: 853e mv a0,a5 - 270: 00000097 auipc ra,0x0 - 274: 000080e7 jalr ra # 270 <.LVL84+0x2> - -00000278 <.LVL85>: - 278: 46c2 lw a3,16(sp) - 27a: 0542 sll a0,a0,0x10 - 27c: 01045613 srl a2,s0,0x10 - 280: 8e49 or a2,a2,a0 - -00000282 <.LVL86>: - 282: 4372 lw t1,28(sp) - 284: 5702 lw a4,32(sp) - 286: 87b6 mv a5,a3 - 288: 00967c63 bgeu a2,s1,2a0 <.L27> - 28c: 961a add a2,a2,t1 - -0000028e <.LVL87>: - 28e: fff68793 add a5,a3,-1 - -00000292 <.LVL88>: - 292: 00666763 bltu a2,t1,2a0 <.L27> - 296: 00967563 bgeu a2,s1,2a0 <.L27> - 29a: ffe68793 add a5,a3,-2 - 29e: 961a add a2,a2,t1 - -000002a0 <.L27>: - 2a0: 4592 lw a1,4(sp) - 2a2: d03e sw a5,32(sp) - -000002a4 <.LVL91>: - 2a4: 409607b3 sub a5,a2,s1 - -000002a8 <.LVL92>: - 2a8: 853e mv a0,a5 - 2aa: d21a sw t1,36(sp) - 2ac: ce3a sw a4,28(sp) - -000002ae <.LVL93>: - 2ae: c83e sw a5,16(sp) - -000002b0 <.LVL94>: - 2b0: 00000097 auipc ra,0x0 - 2b4: 000080e7 jalr ra # 2b0 <.LVL94> - -000002b8 <.LVL95>: - 2b8: 85aa mv a1,a0 - 2ba: ca2a sw a0,20(sp) - -000002bc <.LVL96>: - 2bc: 4562 lw a0,24(sp) - -000002be <.LVL97>: - 2be: 0442 sll s0,s0,0x10 - -000002c0 <.LVL98>: - 2c0: 8041 srl s0,s0,0x10 - 2c2: 00000097 auipc ra,0x0 - 2c6: 000080e7 jalr ra # 2c2 <.LVL98+0x2> - -000002ca <.LVL99>: - 2ca: 4592 lw a1,4(sp) - 2cc: 84aa mv s1,a0 - 2ce: 4542 lw a0,16(sp) - 2d0: 00000097 auipc ra,0x0 - 2d4: 000080e7 jalr ra # 2d0 <.LVL99+0x6> - -000002d8 <.LVL101>: - 2d8: 4652 lw a2,20(sp) - 2da: 0542 sll a0,a0,0x10 - 2dc: 8c49 or s0,s0,a0 - -000002de <.LVL102>: - 2de: 4772 lw a4,28(sp) - 2e0: 5782 lw a5,32(sp) - 2e2: 5312 lw t1,36(sp) - 2e4: 85b2 mv a1,a2 - 2e6: 00947c63 bgeu s0,s1,2fe <.L30> - -000002ea <.LVL103>: - 2ea: 941a add s0,s0,t1 - -000002ec <.LVL104>: - 2ec: fff60593 add a1,a2,-1 # ffffffff <.LLST25+0xfffff017> - -000002f0 <.LVL105>: - 2f0: 00646763 bltu s0,t1,2fe <.L30> - 2f4: 00947563 bgeu s0,s1,2fe <.L30> - 2f8: ffe60593 add a1,a2,-2 - 2fc: 941a add s0,s0,t1 - -000002fe <.L30>: - 2fe: 07c2 sll a5,a5,0x10 - 300: 00b7e2b3 or t0,a5,a1 - -00000304 <.LBB36>: - 304: 4782 lw a5,0(sp) - 306: 4602 lw a2,0(sp) - 308: 63c1 lui t2,0x10 - 30a: fff38693 add a3,t2,-1 # ffff <.LLST25+0xf017> - 30e: 83c1 srl a5,a5,0x10 - 310: c83e sw a5,16(sp) - -00000312 <.LVL108>: - 312: 00d2f7b3 and a5,t0,a3 - 316: 8ef1 and a3,a3,a2 - -00000318 <.LBB41>: - 318: 8c05 sub s0,s0,s1 - -0000031a <.LBB37>: - 31a: 853e mv a0,a5 - 31c: ca36 sw a3,20(sp) - 31e: 85b6 mv a1,a3 - -00000320 <.LVL110>: - 320: 00000097 auipc ra,0x0 - 324: 000080e7 jalr ra # 320 <.LVL110> - 328: 84aa mv s1,a0 - -0000032a <.LBB38>: - 32a: 45c2 lw a1,16(sp) - 32c: 853e mv a0,a5 - 32e: 00000097 auipc ra,0x0 - 332: 000080e7 jalr ra # 32e <.LBB38+0x4> - 336: 87aa mv a5,a0 - -00000338 <.LBB39>: - 338: 45d2 lw a1,20(sp) - 33a: 0102d513 srl a0,t0,0x10 - -0000033e <.LVL113>: - 33e: 00000097 auipc ra,0x0 - 342: 000080e7 jalr ra # 33e <.LVL113> - 346: ce2a sw a0,28(sp) - -00000348 <.LBB40>: - 348: 45c2 lw a1,16(sp) - 34a: 0102d513 srl a0,t0,0x10 - -0000034e <.LVL115>: - 34e: 00000097 auipc ra,0x0 - 352: 000080e7 jalr ra # 34e <.LVL115> - -00000356 <.LBE40>: - 356: 4672 lw a2,28(sp) - 358: 0104d693 srl a3,s1,0x10 - 35c: 97b2 add a5,a5,a2 - -0000035e <.LVL117>: - 35e: 97b6 add a5,a5,a3 - -00000360 <.LVL118>: - 360: 00c7f363 bgeu a5,a2,366 <.L33> - 364: 951e add a0,a0,t2 - -00000366 <.L33>: - 366: 0107d693 srl a3,a5,0x10 - 36a: 9536 add a0,a0,a3 - -0000036c <.LVL120>: - 36c: 66c1 lui a3,0x10 - 36e: 16fd add a3,a3,-1 # ffff <.LLST25+0xf017> - 370: 8ff5 and a5,a5,a3 - -00000372 <.LVL121>: - 372: 07c2 sll a5,a5,0x10 - 374: 8cf5 and s1,s1,a3 - -00000376 <.LVL122>: - 376: 94be add s1,s1,a5 - -00000378 <.LBE42>: - 378: 00a46763 bltu s0,a0,386 <.L34> - -0000037c <.LBB43>: - 37c: 8396 mv t2,t0 - -0000037e <.LBE43>: - 37e: 04a41363 bne s0,a0,3c4 <.L35> - 382: 04977163 bgeu a4,s1,3c4 <.L35> - -00000386 <.L34>: - 386: 4782 lw a5,0(sp) - 388: fff28393 add t2,t0,-1 - -0000038c <.LBB44>: - 38c: 97ba add a5,a5,a4 - 38e: 00e7b6b3 sltu a3,a5,a4 - 392: 00668633 add a2,a3,t1 - 396: 9432 add s0,s0,a2 - -00000398 <.LVL125>: - 398: 873e mv a4,a5 - -0000039a <.LBE44>: - 39a: 00836563 bltu t1,s0,3a4 <.L38> - 39e: 02831363 bne t1,s0,3c4 <.L35> - 3a2: e28d bnez a3,3c4 <.L35> - -000003a4 <.L38>: - 3a4: 00a46663 bltu s0,a0,3b0 <.L39> - 3a8: 00851e63 bne a0,s0,3c4 <.L35> - 3ac: 0097fc63 bgeu a5,s1,3c4 <.L35> - -000003b0 <.L39>: - 3b0: 4702 lw a4,0(sp) - -000003b2 <.LVL127>: - 3b2: ffe28393 add t2,t0,-2 - -000003b6 <.LBB45>: - 3b6: 97ba add a5,a5,a4 - -000003b8 <.LVL129>: - 3b8: 873e mv a4,a5 - -000003ba <.LVL130>: - 3ba: 4782 lw a5,0(sp) - 3bc: 00f737b3 sltu a5,a4,a5 - 3c0: 979a add a5,a5,t1 - 3c2: 943e add s0,s0,a5 - -000003c4 <.L35>: - 3c4: 409704b3 sub s1,a4,s1 - -000003c8 <.LVL132>: - 3c8: 8c09 sub s0,s0,a0 - -000003ca <.LVL133>: - 3ca: 00973733 sltu a4,a4,s1 - -000003ce <.LVL134>: - 3ce: 8c19 sub s0,s0,a4 - -000003d0 <.LBE46>: - 3d0: d41a sw t1,40(sp) - 3d2: 56fd li a3,-1 - 3d4: 16830963 beq t1,s0,546 <.L44> - -000003d8 <.LBB47>: - 3d8: 4592 lw a1,4(sp) - 3da: 8522 mv a0,s0 - -000003dc <.LVL136>: - 3dc: d21e sw t2,36(sp) - -000003de <.LBB48>: - 3de: 00000097 auipc ra,0x0 - 3e2: 000080e7 jalr ra # 3de <.LBB48> - -000003e6 <.LVL138>: - 3e6: 85aa mv a1,a0 - 3e8: d02a sw a0,32(sp) - -000003ea <.LVL139>: - 3ea: 4562 lw a0,24(sp) - -000003ec <.LVL140>: - 3ec: 00000097 auipc ra,0x0 - 3f0: 000080e7 jalr ra # 3ec <.LVL140> - -000003f4 <.LVL141>: - 3f4: 4592 lw a1,4(sp) - 3f6: ce2a sw a0,28(sp) - -000003f8 <.LVL142>: - 3f8: 8522 mv a0,s0 - -000003fa <.LVL143>: - 3fa: 00000097 auipc ra,0x0 - 3fe: 000080e7 jalr ra # 3fa <.LVL143> - -00000402 <.LVL144>: - 402: 5682 lw a3,32(sp) - 404: 47f2 lw a5,28(sp) - 406: 0542 sll a0,a0,0x10 - 408: 0104d413 srl s0,s1,0x10 - -0000040c <.LVL145>: - 40c: 8c49 or s0,s0,a0 - -0000040e <.LVL146>: - 40e: 5392 lw t2,36(sp) - 410: 5322 lw t1,40(sp) - 412: 8736 mv a4,a3 - 414: 00f47c63 bgeu s0,a5,42c <.L45> - -00000418 <.LVL147>: - 418: 941a add s0,s0,t1 - -0000041a <.LVL148>: - 41a: fff68713 add a4,a3,-1 - -0000041e <.LVL149>: - 41e: 00646763 bltu s0,t1,42c <.L45> - 422: 00f47563 bgeu s0,a5,42c <.L45> - 426: ffe68713 add a4,a3,-2 - 42a: 941a add s0,s0,t1 - -0000042c <.L45>: - 42c: 4592 lw a1,4(sp) - 42e: 40f407b3 sub a5,s0,a5 - 432: 853e mv a0,a5 - 434: d61a sw t1,44(sp) - 436: d43a sw a4,40(sp) - 438: d21e sw t2,36(sp) - -0000043a <.LVL152>: - 43a: ce3e sw a5,28(sp) - -0000043c <.LVL153>: - 43c: 00000097 auipc ra,0x0 - 440: 000080e7 jalr ra # 43c <.LVL153> - -00000444 <.LVL154>: - 444: 85aa mv a1,a0 - 446: d02a sw a0,32(sp) - 448: 4562 lw a0,24(sp) - -0000044a <.LVL155>: - 44a: 00000097 auipc ra,0x0 - 44e: 000080e7 jalr ra # 44a <.LVL155> - -00000452 <.LVL156>: - 452: 4592 lw a1,4(sp) - 454: 842a mv s0,a0 - -00000456 <.LVL157>: - 456: 4572 lw a0,28(sp) - 458: 00000097 auipc ra,0x0 - 45c: 000080e7 jalr ra # 458 <.LVL157+0x2> - -00000460 <.LVL158>: - 460: 5602 lw a2,32(sp) - 462: 01049793 sll a5,s1,0x10 - 466: 0542 sll a0,a0,0x10 - 468: 83c1 srl a5,a5,0x10 - 46a: 8fc9 or a5,a5,a0 - -0000046c <.LVL159>: - 46c: 5392 lw t2,36(sp) - 46e: 5722 lw a4,40(sp) - 470: 5332 lw t1,44(sp) - 472: 85b2 mv a1,a2 - 474: 0087fc63 bgeu a5,s0,48c <.L48> - -00000478 <.LVL160>: - 478: 979a add a5,a5,t1 - -0000047a <.LVL161>: - 47a: fff60593 add a1,a2,-1 - -0000047e <.LVL162>: - 47e: 0067e763 bltu a5,t1,48c <.L48> - 482: 0087f563 bgeu a5,s0,48c <.L48> - 486: ffe60593 add a1,a2,-2 - 48a: 979a add a5,a5,t1 - -0000048c <.L48>: - 48c: 0742 sll a4,a4,0x10 - 48e: 8f4d or a4,a4,a1 - 490: 01071293 sll t0,a4,0x10 - 494: 0102d293 srl t0,t0,0x10 - -00000498 <.LBB49>: - 498: 45d2 lw a1,20(sp) - -0000049a <.LBB55>: - 49a: 8f81 sub a5,a5,s0 - -0000049c <.LBB51>: - 49c: 8516 mv a0,t0 - 49e: 00000097 auipc ra,0x0 - 4a2: 000080e7 jalr ra # 49e <.LBB51+0x2> - 4a6: 84aa mv s1,a0 - -000004a8 <.LBB52>: - 4a8: 45c2 lw a1,16(sp) - 4aa: 8516 mv a0,t0 - 4ac: 00000097 auipc ra,0x0 - 4b0: 000080e7 jalr ra # 4ac <.LBB52+0x4> - 4b4: 82aa mv t0,a0 - -000004b6 <.LBB53>: - 4b6: 45d2 lw a1,20(sp) - 4b8: 01075513 srl a0,a4,0x10 - 4bc: 00000097 auipc ra,0x0 - 4c0: 000080e7 jalr ra # 4bc <.LBB53+0x6> - 4c4: 842a mv s0,a0 - -000004c6 <.LBB54>: - 4c6: 45c2 lw a1,16(sp) - 4c8: 01075513 srl a0,a4,0x10 - 4cc: 00000097 auipc ra,0x0 - 4d0: 000080e7 jalr ra # 4cc <.LBB54+0x6> - -000004d4 <.LBE54>: - 4d4: 0104d613 srl a2,s1,0x10 - 4d8: 008286b3 add a3,t0,s0 - 4dc: 00d602b3 add t0,a2,a3 - -000004e0 <.LVL171>: - 4e0: 0082f463 bgeu t0,s0,4e8 <.L51> - 4e4: 66c1 lui a3,0x10 - 4e6: 9536 add a0,a0,a3 - -000004e8 <.L51>: - 4e8: 0102d693 srl a3,t0,0x10 - 4ec: 9536 add a0,a0,a3 - -000004ee <.LVL173>: - 4ee: 66c1 lui a3,0x10 - 4f0: 16fd add a3,a3,-1 # ffff <.LLST25+0xf017> - 4f2: 00d2f2b3 and t0,t0,a3 - -000004f6 <.LVL174>: - 4f6: 02c2 sll t0,t0,0x10 - 4f8: 8ee5 and a3,a3,s1 - 4fa: 92b6 add t0,t0,a3 - -000004fc <.LBE56>: - 4fc: 00a7e763 bltu a5,a0,50a <.L52> - -00000500 <.LBB57>: - 500: 86ba mv a3,a4 - -00000502 <.LBE57>: - 502: 04a79063 bne a5,a0,542 <.L53> - -00000506 <.LVL176>: - 506: 04028063 beqz t0,546 <.L44> - -0000050a <.L52>: - 50a: 979a add a5,a5,t1 - -0000050c <.LVL178>: - 50c: fff70693 add a3,a4,-1 - -00000510 <.LBB58>: - 510: 863e mv a2,a5 - -00000512 <.LBE58>: - 512: 0267e363 bltu a5,t1,538 <.L56> - 516: 00a7e763 bltu a5,a0,524 <.L57> - 51a: 02a79463 bne a5,a0,542 <.L53> - 51e: 4602 lw a2,0(sp) - -00000520 <.LVL181>: - 520: 00567e63 bgeu a2,t0,53c <.L58> - -00000524 <.L57>: - 524: ffe70693 add a3,a4,-2 - -00000528 <.LBB59>: - 528: 4702 lw a4,0(sp) - -0000052a <.LVL183>: - 52a: 4602 lw a2,0(sp) - 52c: 0706 sll a4,a4,0x1 - -0000052e <.LVL184>: - 52e: 00c73633 sltu a2,a4,a2 - 532: 961a add a2,a2,t1 - 534: 963e add a2,a2,a5 - -00000536 <.LVL185>: - 536: c03a sw a4,0(sp) - -00000538 <.L56>: - 538: 00a61563 bne a2,a0,542 <.L53> - -0000053c <.L58>: - 53c: 4782 lw a5,0(sp) - 53e: 00f28463 beq t0,a5,546 <.L44> - -00000542 <.L53>: - 542: 0016e693 or a3,a3,1 - -00000546 <.L44>: - 546: 47a2 lw a5,8(sp) - 548: 3ff78793 add a5,a5,1023 - -0000054c <.LVL190>: - 54c: 08f05363 blez a5,5d2 <.L59> - 550: 0076f713 and a4,a3,7 - 554: cf01 beqz a4,56c <.L60> - 556: 00f6f713 and a4,a3,15 - 55a: 4611 li a2,4 - 55c: 00c70863 beq a4,a2,56c <.L60> - -00000560 <.LBB60>: - 560: 00468713 add a4,a3,4 - 564: 00d73633 sltu a2,a4,a3 - 568: 93b2 add t2,t2,a2 - 56a: 86ba mv a3,a4 - -0000056c <.L60>: - 56c: 01000737 lui a4,0x1000 - 570: 00e3f733 and a4,t2,a4 - 574: cb09 beqz a4,586 <.L63> - 576: ff0007b7 lui a5,0xff000 - -0000057a <.LVL192>: - 57a: 17fd add a5,a5,-1 # feffffff <.LLST25+0xfefff017> - 57c: 00f3f3b3 and t2,t2,a5 - 580: 47a2 lw a5,8(sp) - 582: 40078793 add a5,a5,1024 - -00000586 <.L63>: - 586: 7fe00713 li a4,2046 - 58a: 0ef74463 blt a4,a5,672 <.L88> - 58e: 0036d713 srl a4,a3,0x3 - -00000592 <.LVL195>: - 592: 01d39693 sll a3,t2,0x1d - -00000596 <.LVL196>: - 596: 8ed9 or a3,a3,a4 - -00000598 <.LVL197>: - 598: 0033d393 srl t2,t2,0x3 - -0000059c <.L17>: - 59c: 4732 lw a4,12(sp) - 59e: 03b2 sll t2,t2,0xc - -000005a0 <.LBE63>: - 5a0: 50e2 lw ra,56(sp) - 5a2: 5452 lw s0,52(sp) - -000005a4 <.LBB64>: - 5a4: 07d2 sll a5,a5,0x14 - -000005a6 <.LVL200>: - 5a6: 00c3d393 srl t2,t2,0xc - 5aa: 0077e7b3 or a5,a5,t2 - 5ae: 077e sll a4,a4,0x1f - 5b0: 00e7e633 or a2,a5,a4 - -000005b4 <.LBE64>: - 5b4: 54c2 lw s1,48(sp) - 5b6: 8536 mv a0,a3 - 5b8: 85b2 mv a1,a2 - 5ba: 03c10113 add sp,sp,60 - -000005be <.LVL202>: - 5be: 8082 ret - -000005c0 <.L25>: - 5c0: 4722 lw a4,8(sp) - 5c2: 177d add a4,a4,-1 # ffffff <.LLST25+0xfff017> - 5c4: c43a sw a4,8(sp) - -000005c6 <.LVL204>: - 5c6: 4701 li a4,0 - -000005c8 <.LVL205>: - 5c8: b185 j 228 <.L26> - -000005ca <.L20>: - 5ca: 4792 lw a5,4(sp) - -000005cc <.LBE66>: - 5cc: 84aa mv s1,a0 - -000005ce <.LBB67>: - 5ce: c63e sw a5,12(sp) - -000005d0 <.LBE67>: - 5d0: b10d j 1f2 <.L23> - -000005d2 <.L59>: - 5d2: 4605 li a2,1 - 5d4: cb89 beqz a5,5e6 <.L64> - 5d6: 8e1d sub a2,a2,a5 - -000005d8 <.LVL211>: - 5d8: 03800713 li a4,56 - 5dc: c2c744e3 blt a4,a2,204 <.L90> - 5e0: 477d li a4,31 - 5e2: 04c74c63 blt a4,a2,63a <.L65> - -000005e6 <.L64>: - 5e6: 47a2 lw a5,8(sp) - 5e8: 41e78713 add a4,a5,1054 - 5ec: 00c6d7b3 srl a5,a3,a2 - 5f0: 00e696b3 sll a3,a3,a4 - 5f4: 00d036b3 snez a3,a3 - 5f8: 00e39733 sll a4,t2,a4 - 5fc: 8ed9 or a3,a3,a4 - 5fe: 8fd5 or a5,a5,a3 - -00000600 <.LVL213>: - 600: 00c3d3b3 srl t2,t2,a2 - -00000604 <.L66>: - 604: 0077f713 and a4,a5,7 - 608: cf01 beqz a4,620 <.L68> - 60a: 00f7f713 and a4,a5,15 - 60e: 4691 li a3,4 - 610: 00d70863 beq a4,a3,620 <.L68> - -00000614 <.LBB25>: - 614: 00478713 add a4,a5,4 - 618: 00f736b3 sltu a3,a4,a5 - 61c: 93b6 add t2,t2,a3 - -0000061e <.LVL215>: - 61e: 87ba mv a5,a4 - -00000620 <.L68>: - 620: 00800737 lui a4,0x800 - 624: 00e3f733 and a4,t2,a4 - 628: eb31 bnez a4,67c <.L92> - -0000062a <.LVL217>: - 62a: 01d39693 sll a3,t2,0x1d - 62e: 838d srl a5,a5,0x3 - -00000630 <.LVL218>: - 630: 8edd or a3,a3,a5 - -00000632 <.LVL219>: - 632: 0033d393 srl t2,t2,0x3 - -00000636 <.L105>: - 636: 4781 li a5,0 - 638: b795 j 59c <.L17> - -0000063a <.L65>: - 63a: 5705 li a4,-31 - 63c: 40f707b3 sub a5,a4,a5 - 640: 02000593 li a1,32 - 644: 00f3d7b3 srl a5,t2,a5 - 648: 4701 li a4,0 - 64a: 00b60763 beq a2,a1,658 <.L67> - 64e: 4722 lw a4,8(sp) - 650: 43e70713 add a4,a4,1086 # 80043e <.LLST25+0x7ff456> - 654: 00e39733 sll a4,t2,a4 - -00000658 <.L67>: - 658: 8f55 or a4,a4,a3 - 65a: 00e03733 snez a4,a4 - 65e: 8fd9 or a5,a5,a4 - -00000660 <.LVL222>: - 660: 4381 li t2,0 - 662: b74d j 604 <.L66> - -00000664 <.L86>: - 664: 000803b7 lui t2,0x80 - 668: 4681 li a3,0 - 66a: 7ff00793 li a5,2047 - 66e: c602 sw zero,12(sp) - -00000670 <.LVL224>: - 670: b735 j 59c <.L17> - -00000672 <.L88>: - 672: 4381 li t2,0 - 674: 4681 li a3,0 - 676: 7ff00793 li a5,2047 - 67a: b70d j 59c <.L17> - -0000067c <.L92>: - 67c: 4381 li t2,0 - -0000067e <.LVL227>: - 67e: 4681 li a3,0 - 680: 4785 li a5,1 - -00000682 <.LVL228>: - 682: bf29 j 59c <.L17> - -eqdf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__eqdf2>: - 0: 1151 add sp,sp,-12 - -00000002 <.LBB3>: - 2: 0145d713 srl a4,a1,0x14 - 6: 001007b7 lui a5,0x100 - a: 17fd add a5,a5,-1 # fffff <.LASF16+0xffe4a> - -0000000c <.LBB4>: - c: 0146d393 srl t2,a3,0x14 - -00000010 <.LBE4>: - 10: c422 sw s0,8(sp) - 12: c226 sw s1,4(sp) - -00000014 <.LBB5>: - 14: 7ff77713 and a4,a4,2047 - 18: c032 sw a2,0(sp) - -0000001a <.LBE5>: - 1a: 7ff00413 li s0,2047 - -0000001e <.LBB6>: - 1e: 00b7f333 and t1,a5,a1 - -00000022 <.LBE6>: - 22: 82aa mv t0,a0 - -00000024 <.LBB7>: - 24: 8ff5 and a5,a5,a3 - -00000026 <.LBB8>: - 26: 81fd srl a1,a1,0x1f - -00000028 <.LBB9>: - 28: 7ff3f393 and t2,t2,2047 - 2c: 82fd srl a3,a3,0x1f - -0000002e <.LBE9>: - 2e: 00870963 beq a4,s0,40 <.L2> - 32: 4505 li a0,1 - -00000034 <.LVL5>: - 34: 02839463 bne t2,s0,5c <.L13> - -00000038 <.L1>: - 38: 4422 lw s0,8(sp) - 3a: 4492 lw s1,4(sp) - 3c: 0131 add sp,sp,12 - 3e: 8082 ret - -00000040 <.L2>: - 40: 4505 li a0,1 - -00000042 <.LVL8>: - 42: fee39be3 bne t2,a4,38 <.L1> - 46: 00f367b3 or a5,t1,a5 - -0000004a <.LVL9>: - 4a: 8fd1 or a5,a5,a2 - 4c: 0057e7b3 or a5,a5,t0 - 50: f7e5 bnez a5,38 <.L1> - 52: 40d58533 sub a0,a1,a3 - 56: 00a03533 snez a0,a0 - 5a: bff9 j 38 <.L1> - -0000005c <.L13>: - 5c: 4505 li a0,1 - 5e: fc771de3 bne a4,t2,38 <.L1> - 62: fcf31be3 bne t1,a5,38 <.L1> - 66: 4782 lw a5,0(sp) - -00000068 <.LVL11>: - 68: fcf298e3 bne t0,a5,38 <.L1> - 6c: 00d58863 beq a1,a3,7c <.L11> - 70: f761 bnez a4,38 <.L1> - 72: 00536333 or t1,t1,t0 - -00000076 <.LVL12>: - 76: 00603533 snez a0,t1 - 7a: bf7d j 38 <.L1> - -0000007c <.L11>: - 7c: 4501 li a0,0 - 7e: bf6d j 38 <.L1> - -gedf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__gedf2>: - 0: 1161 add sp,sp,-8 - -00000002 <.LBB3>: - 2: 0145d293 srl t0,a1,0x14 - 6: 001007b7 lui a5,0x100 - a: 17fd add a5,a5,-1 # fffff <.LASF16+0xffe26> - -0000000c <.LBE3>: - c: c026 sw s1,0(sp) - e: 872a mv a4,a0 - 10: 83aa mv t2,a0 - -00000012 <.LBB4>: - 12: c222 sw s0,4(sp) - -00000014 <.LBB5>: - 14: 0146d513 srl a0,a3,0x14 - -00000018 <.LBB6>: - 18: 7ff2f293 and t0,t0,2047 - -0000001c <.LBE6>: - 1c: 7ff00493 li s1,2047 - -00000020 <.LBB7>: - 20: 00b7f333 and t1,a5,a1 - -00000024 <.LBB8>: - 24: 7ff57513 and a0,a0,2047 - 28: 8ff5 and a5,a5,a3 - -0000002a <.LBB9>: - 2a: 81fd srl a1,a1,0x1f - -0000002c <.LBB10>: - 2c: 82fd srl a3,a3,0x1f - -0000002e <.LBE10>: - 2e: 02929663 bne t0,s1,5a <.L2> - 32: 00e36333 or t1,t1,a4 - -00000036 <.LVL6>: - 36: 08031863 bnez t1,c6 <.L24> - 3a: 00550663 beq a0,t0,46 <.L4> - -0000003e <.L20>: - 3e: 4505 li a0,1 - 40: c989 beqz a1,52 <.L1> - 42: 557d li a0,-1 - 44: a039 j 52 <.L1> - -00000046 <.L4>: - 46: 8e5d or a2,a2,a5 - -00000048 <.LVL9>: - 48: 5579 li a0,-2 - -0000004a <.LVL10>: - 4a: e601 bnez a2,52 <.L1> - -0000004c <.LBB12>: - 4c: 4501 li a0,0 - 4e: fed598e3 bne a1,a3,3e <.L20> - -00000052 <.L1>: - 52: 4412 lw s0,4(sp) - 54: 4482 lw s1,0(sp) - 56: 0121 add sp,sp,8 - 58: 8082 ret - -0000005a <.L2>: - 5a: 02951563 bne a0,s1,84 <.L8> - 5e: 8e5d or a2,a2,a5 - -00000060 <.LVL12>: - 60: 5579 li a0,-2 - -00000062 <.LVL13>: - 62: fa65 bnez a2,52 <.L1> - -00000064 <.LBB13>: - 64: 00028863 beqz t0,74 <.L9> - -00000068 <.L61>: - 68: fcd59be3 bne a1,a3,3e <.L20> - -0000006c <.L21>: - 6c: 557d li a0,-1 - 6e: d1f5 beqz a1,52 <.L1> - 70: 852e mv a0,a1 - 72: b7c5 j 52 <.L1> - -00000074 <.L9>: - 74: 00e36333 or t1,t1,a4 - -00000078 <.LVL16>: - 78: fe0318e3 bnez t1,68 <.L61> - -0000007c <.L11>: - 7c: 557d li a0,-1 - 7e: daf1 beqz a3,52 <.L1> - 80: 8536 mv a0,a3 - 82: bfc1 j 52 <.L1> - -00000084 <.L8>: - 84: 8432 mv s0,a2 - 86: 02028363 beqz t0,ac <.L12> - -0000008a <.LVL18>: - 8a: d955 beqz a0,3e <.L20> - -0000008c <.LVL19>: - 8c: fad599e3 bne a1,a3,3e <.L20> - 90: fa5547e3 blt a0,t0,3e <.L20> - 94: fca2cce3 blt t0,a0,6c <.L21> - -00000098 <.L19>: - 98: fa67e3e3 bltu a5,t1,3e <.L20> - 9c: fcf318e3 bne t1,a5,6c <.L21> - a0: f8746fe3 bltu s0,t2,3e <.L20> - a4: 4501 li a0,0 - -000000a6 <.LVL21>: - a6: fa83f6e3 bgeu t2,s0,52 <.L1> - aa: b7c9 j 6c <.L21> - -000000ac <.L12>: - ac: 00e36733 or a4,t1,a4 - -000000b0 <.LVL23>: - b0: c119 beqz a0,b6 <.L14> - -000000b2 <.LVL24>: - b2: d769 beqz a4,7c <.L11> - b4: bf55 j 68 <.L61> - -000000b6 <.L14>: - b6: 8e5d or a2,a2,a5 - -000000b8 <.LVL26>: - b8: c609 beqz a2,c2 <.L15> - -000000ba <.LVL27>: - ba: d369 beqz a4,7c <.L11> - -000000bc <.LVL28>: - bc: fcd58ee3 beq a1,a3,98 <.L19> - c0: bfbd j 3e <.L20> - -000000c2 <.L15>: - c2: db41 beqz a4,52 <.L1> - c4: bfad j 3e <.L20> - -000000c6 <.L24>: - c6: 5579 li a0,-2 - -000000c8 <.LVL31>: - c8: b769 j 52 <.L1> - -ledf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__ledf2>: - 0: 1161 add sp,sp,-8 - -00000002 <.LBB3>: - 2: 0145d293 srl t0,a1,0x14 - 6: 001007b7 lui a5,0x100 - a: 17fd add a5,a5,-1 # fffff <.LASF16+0xffe26> - -0000000c <.LBE3>: - c: c026 sw s1,0(sp) - e: 872a mv a4,a0 - 10: 83aa mv t2,a0 - -00000012 <.LBB4>: - 12: c222 sw s0,4(sp) - -00000014 <.LBB5>: - 14: 0146d513 srl a0,a3,0x14 - -00000018 <.LBB6>: - 18: 7ff2f293 and t0,t0,2047 - -0000001c <.LBE6>: - 1c: 7ff00493 li s1,2047 - -00000020 <.LBB7>: - 20: 00b7f333 and t1,a5,a1 - -00000024 <.LBB8>: - 24: 7ff57513 and a0,a0,2047 - 28: 8ff5 and a5,a5,a3 - -0000002a <.LBB9>: - 2a: 81fd srl a1,a1,0x1f - -0000002c <.LBB10>: - 2c: 82fd srl a3,a3,0x1f - -0000002e <.LBE10>: - 2e: 02929663 bne t0,s1,5a <.L2> - 32: 00e36333 or t1,t1,a4 - -00000036 <.LVL6>: - 36: 08031863 bnez t1,c6 <.L24> - 3a: 00550663 beq a0,t0,46 <.L4> - -0000003e <.L20>: - 3e: 4505 li a0,1 - 40: c989 beqz a1,52 <.L1> - 42: 557d li a0,-1 - 44: a039 j 52 <.L1> - -00000046 <.L4>: - 46: 8e5d or a2,a2,a5 - -00000048 <.LVL9>: - 48: 4509 li a0,2 - -0000004a <.LVL10>: - 4a: e601 bnez a2,52 <.L1> - -0000004c <.LBB12>: - 4c: 4501 li a0,0 - 4e: fed598e3 bne a1,a3,3e <.L20> - -00000052 <.L1>: - 52: 4412 lw s0,4(sp) - 54: 4482 lw s1,0(sp) - 56: 0121 add sp,sp,8 - 58: 8082 ret - -0000005a <.L2>: - 5a: 02951563 bne a0,s1,84 <.L8> - 5e: 8e5d or a2,a2,a5 - -00000060 <.LVL12>: - 60: 4509 li a0,2 - -00000062 <.LVL13>: - 62: fa65 bnez a2,52 <.L1> - -00000064 <.LBB13>: - 64: 00028863 beqz t0,74 <.L9> - -00000068 <.L61>: - 68: fcd59be3 bne a1,a3,3e <.L20> - -0000006c <.L21>: - 6c: 557d li a0,-1 - 6e: d1f5 beqz a1,52 <.L1> - 70: 852e mv a0,a1 - 72: b7c5 j 52 <.L1> - -00000074 <.L9>: - 74: 00e36333 or t1,t1,a4 - -00000078 <.LVL16>: - 78: fe0318e3 bnez t1,68 <.L61> - -0000007c <.L11>: - 7c: 557d li a0,-1 - 7e: daf1 beqz a3,52 <.L1> - 80: 8536 mv a0,a3 - 82: bfc1 j 52 <.L1> - -00000084 <.L8>: - 84: 8432 mv s0,a2 - 86: 02028363 beqz t0,ac <.L12> - -0000008a <.LVL18>: - 8a: d955 beqz a0,3e <.L20> - -0000008c <.LVL19>: - 8c: fad599e3 bne a1,a3,3e <.L20> - 90: fa5547e3 blt a0,t0,3e <.L20> - 94: fca2cce3 blt t0,a0,6c <.L21> - -00000098 <.L19>: - 98: fa67e3e3 bltu a5,t1,3e <.L20> - 9c: fcf318e3 bne t1,a5,6c <.L21> - a0: f8746fe3 bltu s0,t2,3e <.L20> - a4: 4501 li a0,0 - -000000a6 <.LVL21>: - a6: fa83f6e3 bgeu t2,s0,52 <.L1> - aa: b7c9 j 6c <.L21> - -000000ac <.L12>: - ac: 00e36733 or a4,t1,a4 - -000000b0 <.LVL23>: - b0: c119 beqz a0,b6 <.L14> - -000000b2 <.LVL24>: - b2: d769 beqz a4,7c <.L11> - b4: bf55 j 68 <.L61> - -000000b6 <.L14>: - b6: 8e5d or a2,a2,a5 - -000000b8 <.LVL26>: - b8: c609 beqz a2,c2 <.L15> - -000000ba <.LVL27>: - ba: d369 beqz a4,7c <.L11> - -000000bc <.LVL28>: - bc: fcd58ee3 beq a1,a3,98 <.L19> - c0: bfbd j 3e <.L20> - -000000c2 <.L15>: - c2: db41 beqz a4,52 <.L1> - c4: bfad j 3e <.L20> - -000000c6 <.L24>: - c6: 4509 li a0,2 - -000000c8 <.LVL31>: - c8: b769 j 52 <.L1> - -muldf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__muldf3>: - 0: fc410113 add sp,sp,-60 - -00000004 <.LBB3>: - 4: 00c59793 sll a5,a1,0xc - -00000008 <.LBE3>: - 8: d826 sw s1,48(sp) - -0000000a <.LBB4>: - a: 0145d313 srl t1,a1,0x14 - e: 00c7d493 srl s1,a5,0xc - -00000012 <.LVL1>: - 12: 01f5d793 srl a5,a1,0x1f - -00000016 <.LBE4>: - 16: da22 sw s0,52(sp) - 18: dc06 sw ra,56(sp) - -0000001a <.LBB5>: - 1a: 7ff37313 and t1,t1,2047 - -0000001e <.LVL2>: - 1e: c43e sw a5,8(sp) - -00000020 <.LBE5>: - 20: 8436 mv s0,a3 - 22: 30030363 beqz t1,328 <.L2> - 26: 7ff00793 li a5,2047 - 2a: 36f30463 beq t1,a5,392 <.L3> - -0000002e <.LVL4>: - 2e: 00349693 sll a3,s1,0x3 - 32: 01d55793 srl a5,a0,0x1d - 36: 8fd5 or a5,a5,a3 - 38: 008006b7 lui a3,0x800 - 3c: 00d7e4b3 or s1,a5,a3 - -00000040 <.LVL5>: - 40: 00351593 sll a1,a0,0x3 - -00000044 <.LVL6>: - 44: c0130313 add t1,t1,-1023 - -00000048 <.L76>: - 48: 4281 li t0,0 - -0000004a <.L4>: - 4a: 01445713 srl a4,s0,0x14 - 4e: 00c41793 sll a5,s0,0xc - 52: 7ff77713 and a4,a4,2047 - 56: 83b1 srl a5,a5,0xc - -00000058 <.LVL9>: - 58: 807d srl s0,s0,0x1f - -0000005a <.LBE10>: - 5a: 34070d63 beqz a4,3b4 <.L9> - 5e: 7ff00693 li a3,2047 - 62: 3cd70a63 beq a4,a3,436 <.L10> - -00000066 <.LVL11>: - 66: 01d65693 srl a3,a2,0x1d - 6a: 078e sll a5,a5,0x3 - -0000006c <.LVL12>: - 6c: 8edd or a3,a3,a5 - 6e: 008007b7 lui a5,0x800 - 72: 8fd5 or a5,a5,a3 - -00000074 <.LVL13>: - 74: 00361693 sll a3,a2,0x3 - -00000078 <.LVL14>: - 78: c0170613 add a2,a4,-1023 - -0000007c <.L77>: - 7c: 4701 li a4,0 - -0000007e <.L11>: - 7e: 4522 lw a0,8(sp) - 80: 961a add a2,a2,t1 - -00000082 <.LVL17>: - 82: d232 sw a2,36(sp) - 84: 0605 add a2,a2,1 - 86: 8d21 xor a0,a0,s0 - 88: c232 sw a2,4(sp) - 8a: 00229613 sll a2,t0,0x2 - 8e: c02a sw a0,0(sp) - -00000090 <.LVL18>: - 90: 8e59 or a2,a2,a4 - 92: 4529 li a0,10 - -00000094 <.LVL19>: - 94: 3ec54d63 blt a0,a2,48e <.L16> - 98: 4509 li a0,2 - 9a: 3ac54f63 blt a0,a2,458 <.L17> - 9e: 167d add a2,a2,-1 - a0: 4505 li a0,1 - a2: 3cc57a63 bgeu a0,a2,476 <.L19> - -000000a6 <.L18>: - a6: 0105d713 srl a4,a1,0x10 - -000000aa <.LVL21>: - aa: c43a sw a4,8(sp) - -000000ac <.LVL22>: - ac: 62c1 lui t0,0x10 - -000000ae <.LVL23>: - ae: 0106d713 srl a4,a3,0x10 - b2: c63a sw a4,12(sp) - -000000b4 <.LBB18>: - b4: fff28713 add a4,t0,-1 # ffff <.LLST81+0xf1c4> - b8: 00e5f633 and a2,a1,a4 - bc: 8ef9 and a3,a3,a4 - -000000be <.LVL25>: - be: ca32 sw a2,20(sp) - c0: 8532 mv a0,a2 - c2: cc36 sw a3,24(sp) - c4: 85b6 mv a1,a3 - -000000c6 <.LVL26>: - c6: 00000097 auipc ra,0x0 - ca: 000080e7 jalr ra # c6 <.LVL26> - ce: 83aa mv t2,a0 - -000000d0 <.LBB19>: - d0: 45b2 lw a1,12(sp) - d2: 4552 lw a0,20(sp) - d4: 00000097 auipc ra,0x0 - d8: 000080e7 jalr ra # d4 <.LBB19+0x4> - dc: 832a mv t1,a0 - -000000de <.LBB20>: - de: 45e2 lw a1,24(sp) - e0: 4522 lw a0,8(sp) - e2: 00000097 auipc ra,0x0 - e6: 000080e7 jalr ra # e2 <.LBB20+0x4> - ea: 842a mv s0,a0 - -000000ec <.LBB21>: - ec: 45b2 lw a1,12(sp) - ee: 4522 lw a0,8(sp) - f0: 00000097 auipc ra,0x0 - f4: 000080e7 jalr ra # f0 <.LBB21+0x4> - -000000f8 <.LBE21>: - f8: 0103d693 srl a3,t2,0x10 - fc: 9322 add t1,t1,s0 - -000000fe <.LBB22>: - fe: d02a sw a0,32(sp) - -00000100 <.LBE22>: - 100: 9336 add t1,t1,a3 - -00000102 <.LVL32>: - 102: 00837563 bgeu t1,s0,10c <.L23> - 106: 005506b3 add a3,a0,t0 - 10a: d036 sw a3,32(sp) - -0000010c <.L23>: - 10c: 01035293 srl t0,t1,0x10 - -00000110 <.LVL34>: - 110: 00e37333 and t1,t1,a4 - -00000114 <.LVL35>: - 114: 0342 sll t1,t1,0x10 - 116: 00e3f6b3 and a3,t2,a4 - 11a: 969a add a3,a3,t1 - 11c: d436 sw a3,40(sp) - -0000011e <.LBB23>: - 11e: 0107d693 srl a3,a5,0x10 - -00000122 <.LVL37>: - 122: 8ff9 and a5,a5,a4 - -00000124 <.LBB24>: - 124: 4552 lw a0,20(sp) - -00000126 <.LBE24>: - 126: c836 sw a3,16(sp) - -00000128 <.LBB25>: - 128: ce3e sw a5,28(sp) - 12a: 85be mv a1,a5 - 12c: 00000097 auipc ra,0x0 - 130: 000080e7 jalr ra # 12c <.LBB25+0x4> - 134: 872a mv a4,a0 - -00000136 <.LBB26>: - 136: 45c2 lw a1,16(sp) - 138: 4552 lw a0,20(sp) - -0000013a <.LVL41>: - 13a: 00000097 auipc ra,0x0 - 13e: 000080e7 jalr ra # 13a <.LVL41> - 142: 87aa mv a5,a0 - -00000144 <.LBB27>: - 144: 45f2 lw a1,28(sp) - 146: 4522 lw a0,8(sp) - -00000148 <.LVL43>: - 148: 00000097 auipc ra,0x0 - 14c: 000080e7 jalr ra # 148 <.LVL43> - 150: 832a mv t1,a0 - -00000152 <.LBB28>: - 152: 45c2 lw a1,16(sp) - 154: 4522 lw a0,8(sp) - 156: 00000097 auipc ra,0x0 - 15a: 000080e7 jalr ra # 156 <.LBB28+0x4> - -0000015e <.LBE28>: - 15e: 01075693 srl a3,a4,0x10 - 162: 979a add a5,a5,t1 - -00000164 <.LVL46>: - 164: 96be add a3,a3,a5 - -00000166 <.LVL47>: - 166: 0066f463 bgeu a3,t1,16e <.L24> - 16a: 67c1 lui a5,0x10 - 16c: 953e add a0,a0,a5 - -0000016e <.L24>: - 16e: 0106d793 srl a5,a3,0x10 - 172: 97aa add a5,a5,a0 - 174: 6341 lui t1,0x10 - -00000176 <.LVL49>: - 176: d63e sw a5,44(sp) - -00000178 <.LVL50>: - 178: fff30793 add a5,t1,-1 # ffff <.LLST81+0xf1c4> - -0000017c <.LVL51>: - 17c: 8efd and a3,a3,a5 - -0000017e <.LVL52>: - 17e: 06c2 sll a3,a3,0x10 - 180: 8f7d and a4,a4,a5 - -00000182 <.LVL53>: - 182: 9736 add a4,a4,a3 - 184: ca3a sw a4,20(sp) - 186: 92ba add t0,t0,a4 - -00000188 <.LBB29>: - 188: 8fe5 and a5,a5,s1 - 18a: 0104d713 srl a4,s1,0x10 - -0000018e <.LBB30>: - 18e: 45e2 lw a1,24(sp) - -00000190 <.LBE30>: - 190: c43a sw a4,8(sp) - -00000192 <.LBB31>: - 192: 853e mv a0,a5 - -00000194 <.LVL57>: - 194: 00000097 auipc ra,0x0 - 198: 000080e7 jalr ra # 194 <.LVL57> - 19c: 872a mv a4,a0 - -0000019e <.LBB32>: - 19e: 45b2 lw a1,12(sp) - 1a0: 853e mv a0,a5 - -000001a2 <.LVL59>: - 1a2: 00000097 auipc ra,0x0 - 1a6: 000080e7 jalr ra # 1a2 <.LVL59> - 1aa: 83aa mv t2,a0 - -000001ac <.LBB33>: - 1ac: 45e2 lw a1,24(sp) - 1ae: 4522 lw a0,8(sp) - 1b0: 00000097 auipc ra,0x0 - 1b4: 000080e7 jalr ra # 1b0 <.LBB33+0x4> - 1b8: 842a mv s0,a0 - -000001ba <.LBB34>: - 1ba: 45b2 lw a1,12(sp) - 1bc: 4522 lw a0,8(sp) - 1be: 00000097 auipc ra,0x0 - 1c2: 000080e7 jalr ra # 1be <.LBB34+0x4> - -000001c6 <.LBE34>: - 1c6: 01075693 srl a3,a4,0x10 - 1ca: 93a2 add t2,t2,s0 - -000001cc <.LVL63>: - 1cc: 93b6 add t2,t2,a3 - -000001ce <.LVL64>: - 1ce: 0083f363 bgeu t2,s0,1d4 <.L25> - 1d2: 951a add a0,a0,t1 - -000001d4 <.L25>: - 1d4: 6441 lui s0,0x10 - -000001d6 <.LVL66>: - 1d6: fff40313 add t1,s0,-1 # ffff <.LLST81+0xf1c4> - 1da: 0103d693 srl a3,t2,0x10 - 1de: 0063f3b3 and t2,t2,t1 - -000001e2 <.LVL67>: - 1e2: 03c2 sll t2,t2,0x10 - 1e4: 00677733 and a4,a4,t1 - -000001e8 <.LVL68>: - 1e8: 971e add a4,a4,t2 - 1ea: 00a684b3 add s1,a3,a0 - -000001ee <.LBB35>: - 1ee: 45f2 lw a1,28(sp) - -000001f0 <.LBB41>: - 1f0: c63a sw a4,12(sp) - -000001f2 <.LBB37>: - 1f2: 853e mv a0,a5 - -000001f4 <.LVL71>: - 1f4: 00000097 auipc ra,0x0 - 1f8: 000080e7 jalr ra # 1f4 <.LVL71> - 1fc: 872a mv a4,a0 - -000001fe <.LBB38>: - 1fe: 45c2 lw a1,16(sp) - 200: 853e mv a0,a5 - -00000202 <.LVL73>: - 202: 00000097 auipc ra,0x0 - 206: 000080e7 jalr ra # 202 <.LVL73> - 20a: 87aa mv a5,a0 - -0000020c <.LBB39>: - 20c: 45f2 lw a1,28(sp) - 20e: 4522 lw a0,8(sp) - -00000210 <.LVL75>: - 210: 00000097 auipc ra,0x0 - 214: 000080e7 jalr ra # 210 <.LVL75> - 218: 83aa mv t2,a0 - -0000021a <.LBB40>: - 21a: 45c2 lw a1,16(sp) - 21c: 4522 lw a0,8(sp) - 21e: 00000097 auipc ra,0x0 - 222: 000080e7 jalr ra # 21e <.LBB40+0x4> - -00000226 <.LBE40>: - 226: 01075693 srl a3,a4,0x10 - 22a: 979e add a5,a5,t2 - -0000022c <.LVL78>: - 22c: 97b6 add a5,a5,a3 - -0000022e <.LVL79>: - 22e: 0077f363 bgeu a5,t2,234 <.L26> - 232: 9522 add a0,a0,s0 - -00000234 <.L26>: - 234: 0067f633 and a2,a5,t1 - 238: 0642 sll a2,a2,0x10 - 23a: 00677733 and a4,a4,t1 - -0000023e <.LBB45>: - 23e: 5682 lw a3,32(sp) - -00000240 <.LBB46>: - 240: 9732 add a4,a4,a2 - -00000242 <.LBB47>: - 242: 45d2 lw a1,20(sp) - 244: 5632 lw a2,44(sp) - 246: 9696 add a3,a3,t0 - -00000248 <.LVL82>: - 248: 00b6b5b3 sltu a1,a3,a1 - -0000024c <.LVL83>: - 24c: 963a add a2,a2,a4 - -0000024e <.LVL84>: - 24e: 95b2 add a1,a1,a2 - 250: 00e63733 sltu a4,a2,a4 - -00000254 <.LVL85>: - 254: 00c5b633 sltu a2,a1,a2 - 258: 8e59 or a2,a2,a4 - -0000025a <.LBB48>: - 25a: 83c1 srl a5,a5,0x10 - -0000025c <.LVL86>: - 25c: 963e add a2,a2,a5 - -0000025e <.LBB49>: - 25e: 47b2 lw a5,12(sp) - 260: 009582b3 add t0,a1,s1 - 264: 00f68733 add a4,a3,a5 - -00000268 <.LVL88>: - 268: 00d736b3 sltu a3,a4,a3 - -0000026c <.LVL89>: - 26c: 00d28333 add t1,t0,a3 - -00000270 <.LBB51>: - 270: 00b2b7b3 sltu a5,t0,a1 - -00000274 <.LVL91>: - 274: 005332b3 sltu t0,t1,t0 - -00000278 <.LVL92>: - 278: 0057e7b3 or a5,a5,t0 - -0000027c <.LVL93>: - 27c: 97b2 add a5,a5,a2 - 27e: 97aa add a5,a5,a0 - -00000280 <.LBB54>: - 280: 5622 lw a2,40(sp) - 282: 01735693 srl a3,t1,0x17 - -00000286 <.LVL94>: - 286: 07a6 sll a5,a5,0x9 - 288: 8fd5 or a5,a5,a3 - -0000028a <.LBB55>: - 28a: 00971693 sll a3,a4,0x9 - 28e: 8ed1 or a3,a3,a2 - -00000290 <.LVL96>: - 290: 835d srl a4,a4,0x17 - -00000292 <.LVL97>: - 292: 00d036b3 snez a3,a3 - -00000296 <.LBE55>: - 296: 8ed9 or a3,a3,a4 - -00000298 <.LBE15>: - 298: 01000737 lui a4,0x1000 - -0000029c <.LBB56>: - 29c: 0326 sll t1,t1,0x9 - -0000029e <.LBE56>: - 29e: 8f7d and a4,a4,a5 - -000002a0 <.LBB60>: - 2a0: 0066e6b3 or a3,a3,t1 - -000002a4 <.LBE60>: - 2a4: 20070163 beqz a4,4a6 <.L57> - 2a8: 0016d713 srl a4,a3,0x1 - 2ac: 8a85 and a3,a3,1 - -000002ae <.LVL100>: - 2ae: 8f55 or a4,a4,a3 - 2b0: 01f79693 sll a3,a5,0x1f - 2b4: 8ed9 or a3,a3,a4 - -000002b6 <.LVL101>: - 2b6: 8385 srl a5,a5,0x1 - -000002b8 <.L37>: - 2b8: 4712 lw a4,4(sp) - 2ba: 3ff70513 add a0,a4,1023 # 10003ff <.LLST81+0xfff5c4> - -000002be <.LVL103>: - 2be: 1ea05763 blez a0,4ac <.L38> - 2c2: 0076f713 and a4,a3,7 - 2c6: cf01 beqz a4,2de <.L39> - 2c8: 00f6f713 and a4,a3,15 - 2cc: 4611 li a2,4 - 2ce: 00c70863 beq a4,a2,2de <.L39> - -000002d2 <.LBB64>: - 2d2: 00468713 add a4,a3,4 # 800004 <.LLST81+0x7ff1c9> - 2d6: 00d73633 sltu a2,a4,a3 - 2da: 97b2 add a5,a5,a2 - 2dc: 86ba mv a3,a4 - -000002de <.L39>: - 2de: 01000737 lui a4,0x1000 - 2e2: 8f7d and a4,a4,a5 - 2e4: cb01 beqz a4,2f4 <.L42> - 2e6: ff000737 lui a4,0xff000 - 2ea: 177d add a4,a4,-1 # feffffff <.LLST81+0xfefff1c4> - 2ec: 8ff9 and a5,a5,a4 - 2ee: 4712 lw a4,4(sp) - 2f0: 40070513 add a0,a4,1024 - -000002f4 <.L42>: - 2f4: 7fe00713 li a4,2046 - 2f8: 24a74a63 blt a4,a0,54c <.L61> - 2fc: 01d79613 sll a2,a5,0x1d - -00000300 <.LVL107>: - 300: 828d srl a3,a3,0x3 - -00000302 <.LVL108>: - 302: 8e55 or a2,a2,a3 - -00000304 <.LVL109>: - 304: 838d srl a5,a5,0x3 - -00000306 <.L20>: - 306: 07b2 sll a5,a5,0xc - -00000308 <.LVL111>: - 308: 01451713 sll a4,a0,0x14 - 30c: 83b1 srl a5,a5,0xc - 30e: 8fd9 or a5,a5,a4 - 310: 4702 lw a4,0(sp) - -00000312 <.LBE67>: - 312: 50e2 lw ra,56(sp) - 314: 5452 lw s0,52(sp) - -00000316 <.LBB68>: - 316: 077e sll a4,a4,0x1f - 318: 00e7e6b3 or a3,a5,a4 - -0000031c <.LBE68>: - 31c: 54c2 lw s1,48(sp) - 31e: 8532 mv a0,a2 - -00000320 <.LVL113>: - 320: 85b6 mv a1,a3 - 322: 03c10113 add sp,sp,60 - -00000326 <.LVL114>: - 326: 8082 ret - -00000328 <.L2>: - 328: 00a4e5b3 or a1,s1,a0 - 32c: c9bd beqz a1,3a2 <.L50> - -0000032e <.LBB69>: - 32e: c232 sw a2,4(sp) - 330: cc95 beqz s1,36c <.L5> - 332: c02a sw a0,0(sp) - 334: 8526 mv a0,s1 - -00000336 <.LVL116>: - 336: 00000097 auipc ra,0x0 - 33a: 000080e7 jalr ra # 336 <.LVL116> - -0000033e <.LVL117>: - 33e: 4702 lw a4,0(sp) - 340: 4612 lw a2,4(sp) - 342: ff550593 add a1,a0,-11 - -00000346 <.L6>: - 346: 47f5 li a5,29 - 348: ff850693 add a3,a0,-8 - 34c: 8f8d sub a5,a5,a1 - 34e: 00d49333 sll t1,s1,a3 - 352: 00f757b3 srl a5,a4,a5 - 356: 0067e7b3 or a5,a5,t1 - -0000035a <.LVL119>: - 35a: 00d714b3 sll s1,a4,a3 - -0000035e <.L8>: - 35e: c0d00313 li t1,-1011 - 362: 85a6 mv a1,s1 - -00000364 <.LVL121>: - 364: 40a30333 sub t1,t1,a0 - -00000368 <.LVL122>: - 368: 84be mv s1,a5 - -0000036a <.LVL123>: - 36a: b9f9 j 48 <.L76> - -0000036c <.L5>: - 36c: c02a sw a0,0(sp) - 36e: 00000097 auipc ra,0x0 - 372: 000080e7 jalr ra # 36e <.L5+0x2> - -00000376 <.LVL125>: - 376: 87aa mv a5,a0 - -00000378 <.LVL126>: - 378: 01578593 add a1,a5,21 # 10015 <.LLST81+0xf1da> - 37c: 46f1 li a3,28 - 37e: 4702 lw a4,0(sp) - 380: 4612 lw a2,4(sp) - 382: 02050513 add a0,a0,32 - -00000386 <.LVL127>: - 386: fcb6d0e3 bge a3,a1,346 <.L6> - -0000038a <.LVL128>: - 38a: 17e1 add a5,a5,-8 - 38c: 00f717b3 sll a5,a4,a5 - -00000390 <.LVL129>: - 390: b7f9 j 35e <.L8> - -00000392 <.L3>: - 392: 00a4e5b3 or a1,s1,a0 - 396: c991 beqz a1,3aa <.L51> - 398: 85aa mv a1,a0 - -0000039a <.LBB70>: - 39a: 7ff00313 li t1,2047 - -0000039e <.LBE70>: - 39e: 428d li t0,3 - 3a0: b16d j 4a <.L4> - -000003a2 <.L50>: - 3a2: 4481 li s1,0 - -000003a4 <.LVL133>: - 3a4: 4301 li t1,0 - -000003a6 <.LBE71>: - 3a6: 4285 li t0,1 - 3a8: b14d j 4a <.L4> - -000003aa <.L51>: - 3aa: 4481 li s1,0 - -000003ac <.LVL136>: - 3ac: 7ff00313 li t1,2047 - -000003b0 <.LBE72>: - 3b0: 4289 li t0,2 - 3b2: b961 j 4a <.L4> - -000003b4 <.L9>: - 3b4: 00c7e6b3 or a3,a5,a2 - 3b8: c6d9 beqz a3,446 <.L52> - -000003ba <.LBB73>: - 3ba: c3b9 beqz a5,400 <.L12> - 3bc: 853e mv a0,a5 - 3be: ca32 sw a2,20(sp) - 3c0: c82e sw a1,16(sp) - 3c2: c61a sw t1,12(sp) - 3c4: c216 sw t0,4(sp) - 3c6: c03e sw a5,0(sp) - 3c8: 00000097 auipc ra,0x0 - 3cc: 000080e7 jalr ra # 3c8 <.LBB73+0xe> - -000003d0 <.LVL139>: - 3d0: 4782 lw a5,0(sp) - 3d2: 4292 lw t0,4(sp) - 3d4: 4332 lw t1,12(sp) - 3d6: 45c2 lw a1,16(sp) - 3d8: 4652 lw a2,20(sp) - 3da: ff550693 add a3,a0,-11 - -000003de <.L13>: - 3de: 4775 li a4,29 - 3e0: ff850393 add t2,a0,-8 - 3e4: 8f15 sub a4,a4,a3 - 3e6: 007797b3 sll a5,a5,t2 - -000003ea <.LVL141>: - 3ea: 00e65733 srl a4,a2,a4 - 3ee: 8f5d or a4,a4,a5 - -000003f0 <.LVL142>: - 3f0: 007617b3 sll a5,a2,t2 - -000003f4 <.L15>: - 3f4: c0d00613 li a2,-1011 - 3f8: 86be mv a3,a5 - -000003fa <.LVL144>: - 3fa: 8e09 sub a2,a2,a0 - -000003fc <.LVL145>: - 3fc: 87ba mv a5,a4 - -000003fe <.LVL146>: - 3fe: b9bd j 7c <.L77> - -00000400 <.L12>: - 400: 8532 mv a0,a2 - 402: ca3e sw a5,20(sp) - 404: c82e sw a1,16(sp) - 406: c61a sw t1,12(sp) - 408: c216 sw t0,4(sp) - 40a: c032 sw a2,0(sp) - 40c: 00000097 auipc ra,0x0 - 410: 000080e7 jalr ra # 40c <.L12+0xc> - -00000414 <.LVL148>: - 414: 872a mv a4,a0 - -00000416 <.LVL149>: - 416: 01570693 add a3,a4,21 - 41a: 43f1 li t2,28 - 41c: 4602 lw a2,0(sp) - 41e: 4292 lw t0,4(sp) - 420: 4332 lw t1,12(sp) - 422: 45c2 lw a1,16(sp) - 424: 47d2 lw a5,20(sp) - 426: 02050513 add a0,a0,32 - -0000042a <.LVL150>: - 42a: fad3dae3 bge t2,a3,3de <.L13> - -0000042e <.LVL151>: - 42e: 1761 add a4,a4,-8 - 430: 00e61733 sll a4,a2,a4 - -00000434 <.LVL152>: - 434: b7c1 j 3f4 <.L15> - -00000436 <.L10>: - 436: 00c7e6b3 or a3,a5,a2 - 43a: ca91 beqz a3,44e <.L53> - 43c: 86b2 mv a3,a2 - 43e: 470d li a4,3 - -00000440 <.LBB74>: - 440: 7ff00613 li a2,2047 - -00000444 <.LVL155>: - 444: b92d j 7e <.L11> - -00000446 <.L52>: - 446: 4781 li a5,0 - -00000448 <.LVL157>: - 448: 4601 li a2,0 - -0000044a <.LBE74>: - 44a: 4705 li a4,1 - -0000044c <.LVL159>: - 44c: b90d j 7e <.L11> - -0000044e <.L53>: - 44e: 4781 li a5,0 - -00000450 <.LVL161>: - 450: 7ff00613 li a2,2047 - -00000454 <.LBE75>: - 454: 4709 li a4,2 - -00000456 <.LVL163>: - 456: b125 j 7e <.L11> - -00000458 <.L17>: - 458: 4505 li a0,1 - 45a: 00c51533 sll a0,a0,a2 - 45e: 53057613 and a2,a0,1328 - 462: ee15 bnez a2,49e <.L54> - 464: 24057313 and t1,a0,576 - -00000468 <.LVL165>: - 468: 0c031863 bnez t1,538 <.L55> - 46c: 08857513 and a0,a0,136 - 470: c2050be3 beqz a0,a6 <.L18> - -00000474 <.L21>: - 474: c022 sw s0,0(sp) - -00000476 <.L19>: - 476: 4609 li a2,2 - 478: 0cc70a63 beq a4,a2,54c <.L61> - 47c: 460d li a2,3 - 47e: 0cc70363 beq a4,a2,544 <.L59> - 482: 4605 li a2,1 - 484: e2c71ae3 bne a4,a2,2b8 <.L37> - -00000488 <.L63>: - 488: 4781 li a5,0 - 48a: 4601 li a2,0 - 48c: a041 j 50c <.L79> - -0000048e <.L16>: - 48e: 453d li a0,15 - 490: 0aa60a63 beq a2,a0,544 <.L59> - 494: 452d li a0,11 - 496: fca60fe3 beq a2,a0,474 <.L21> - -0000049a <.LBB82>: - 49a: 47a2 lw a5,8(sp) - -0000049c <.LVL169>: - 49c: c03e sw a5,0(sp) - -0000049e <.L54>: - 49e: 87a6 mv a5,s1 - 4a0: 86ae mv a3,a1 - -000004a2 <.LVL171>: - 4a2: 8716 mv a4,t0 - -000004a4 <.LVL172>: - 4a4: bfc9 j 476 <.L19> - -000004a6 <.L57>: - 4a6: 5712 lw a4,36(sp) - 4a8: c23a sw a4,4(sp) - -000004aa <.LVL174>: - 4aa: b539 j 2b8 <.L37> - -000004ac <.L38>: - 4ac: 4585 li a1,1 - 4ae: c909 beqz a0,4c0 <.L43> - 4b0: 8d89 sub a1,a1,a0 - -000004b2 <.LVL176>: - 4b2: 03800713 li a4,56 - 4b6: fcb749e3 blt a4,a1,488 <.L63> - 4ba: 477d li a4,31 - 4bc: 04b74a63 blt a4,a1,510 <.L44> - -000004c0 <.L43>: - 4c0: 4712 lw a4,4(sp) - 4c2: 00b6d533 srl a0,a3,a1 - 4c6: 41e70613 add a2,a4,1054 - 4ca: 00c69733 sll a4,a3,a2 - 4ce: 00e03733 snez a4,a4 - 4d2: 00c79633 sll a2,a5,a2 - 4d6: 8f51 or a4,a4,a2 - 4d8: 8f49 or a4,a4,a0 - -000004da <.LVL178>: - 4da: 00b7d7b3 srl a5,a5,a1 - -000004de <.L45>: - 4de: 00777693 and a3,a4,7 - 4e2: ce81 beqz a3,4fa <.L47> - 4e4: 00f77693 and a3,a4,15 - 4e8: 4611 li a2,4 - 4ea: 00c68863 beq a3,a2,4fa <.L47> - -000004ee <.LBB79>: - 4ee: 00470693 add a3,a4,4 - 4f2: 00e6b633 sltu a2,a3,a4 - 4f6: 97b2 add a5,a5,a2 - -000004f8 <.LVL180>: - 4f8: 8736 mv a4,a3 - -000004fa <.L47>: - 4fa: 008006b7 lui a3,0x800 - 4fe: 8efd and a3,a3,a5 - 500: eab9 bnez a3,556 <.L65> - -00000502 <.LVL182>: - 502: 01d79613 sll a2,a5,0x1d - 506: 830d srl a4,a4,0x3 - -00000508 <.LVL183>: - 508: 8e59 or a2,a2,a4 - -0000050a <.LVL184>: - 50a: 838d srl a5,a5,0x3 - -0000050c <.L79>: - 50c: 4501 li a0,0 - 50e: bbe5 j 306 <.L20> - -00000510 <.L44>: - 510: 5705 li a4,-31 - 512: 8f09 sub a4,a4,a0 - 514: 02000513 li a0,32 - 518: 00e7d733 srl a4,a5,a4 - 51c: 4601 li a2,0 - 51e: 00a58763 beq a1,a0,52c <.L46> - 522: 4612 lw a2,4(sp) - 524: 43e60613 add a2,a2,1086 - 528: 00c79633 sll a2,a5,a2 - -0000052c <.L46>: - 52c: 8e55 or a2,a2,a3 - 52e: 00c03633 snez a2,a2 - 532: 8f51 or a4,a4,a2 - -00000534 <.LVL187>: - 534: 4781 li a5,0 - 536: b765 j 4de <.L45> - -00000538 <.L55>: - 538: 000807b7 lui a5,0x80 - -0000053c <.L78>: - 53c: 7ff00513 li a0,2047 - 540: c002 sw zero,0(sp) - -00000542 <.LVL190>: - 542: b3d1 j 306 <.L20> - -00000544 <.L59>: - 544: 000807b7 lui a5,0x80 - 548: 4601 li a2,0 - 54a: bfcd j 53c <.L78> - -0000054c <.L61>: - 54c: 4781 li a5,0 - 54e: 4601 li a2,0 - 550: 7ff00513 li a0,2047 - 554: bb4d j 306 <.L20> - -00000556 <.L65>: - 556: 4781 li a5,0 - -00000558 <.LVL194>: - 558: 4601 li a2,0 - 55a: 4505 li a0,1 - 55c: b36d j 306 <.L20> - -negdf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__negdf2>: - 0: 800007b7 lui a5,0x80000 - 4: 872a mv a4,a0 - 6: 8fad xor a5,a5,a1 - -00000008 <.LBE3>: - 8: 853a mv a0,a4 - -0000000a <.LVL2>: - a: 85be mv a1,a5 - c: 8082 ret - -subdf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__subdf3>: - 0: 00100337 lui t1,0x100 - 4: 137d add t1,t1,-1 # fffff <.LLST28+0xfed9c> - -00000006 <.LBE2>: - 6: 1131 add sp,sp,-20 - -00000008 <.LBB3>: - 8: 00b372b3 and t0,t1,a1 - -0000000c <.LVL1>: - c: 0145d713 srl a4,a1,0x14 - -00000010 <.LBE3>: - 10: 01d55793 srl a5,a0,0x1d - -00000014 <.LBB5>: - 14: 00d37333 and t1,t1,a3 - -00000018 <.LBE5>: - 18: c622 sw s0,12(sp) - 1a: c426 sw s1,8(sp) - -0000001c <.LBB6>: - 1c: 01f5d413 srl s0,a1,0x1f - 20: 7ff77493 and s1,a4,2047 - -00000024 <.LBB8>: - 24: 0146d593 srl a1,a3,0x14 - -00000028 <.LBE8>: - 28: 00329713 sll a4,t0,0x3 - 2c: 8fd9 or a5,a5,a4 - -0000002e <.LVL3>: - 2e: 030e sll t1,t1,0x3 - 30: 01d65713 srl a4,a2,0x1d - 34: c806 sw ra,16(sp) - -00000036 <.LBB11>: - 36: 7ff5f593 and a1,a1,2047 - -0000003a <.LBE11>: - 3a: 7ff00393 li t2,2047 - 3e: 050e sll a0,a0,0x3 - -00000040 <.LBB13>: - 40: 82fd srl a3,a3,0x1f - -00000042 <.LBE13>: - 42: 00676733 or a4,a4,t1 - -00000046 <.LVL6>: - 46: 060e sll a2,a2,0x3 - -00000048 <.LVL7>: - 48: 06759063 bne a1,t2,a8 <.L2> - 4c: 00c762b3 or t0,a4,a2 - -00000050 <.LBB15>: - 50: 80148313 add t1,s1,-2047 - -00000054 <.LBE15>: - 54: 00028c63 beqz t0,6c <.L3> - -00000058 <.LBB32>: - 58: 82b6 mv t0,a3 - -0000005a <.LBE32>: - 5a: 34d41b63 bne s0,a3,3b0 <.L174> - -0000005e <.LBB33>: - 5e: 1e030d63 beqz t1,258 <.L24> - -00000062 <.LVL8>: - 62: 5c049d63 bnez s1,63c <.L115> - -00000066 <.L106>: - 66: 7ff00493 li s1,2047 - -0000006a <.LVL10>: - 6a: aa59 j 200 <.L25> - -0000006c <.L3>: - 6c: 0016c293 xor t0,a3,1 - -00000070 <.LVL12>: - 70: 34541963 bne s0,t0,3c2 <.L175> - -00000074 <.LBB34>: - 74: 1e030263 beqz t1,258 <.L24> - -00000078 <.LVL13>: - 78: d4fd beqz s1,66 <.L106> - -0000007a <.LBE34>: - 7a: 4781 li a5,0 - -0000007c <.LVL14>: - 7c: 4501 li a0,0 - -0000007e <.LBB36>: - 7e: 7ff00493 li s1,2047 - -00000082 <.L95>: - 82: 008006b7 lui a3,0x800 - 86: 8efd and a3,a3,a5 - 88: 5a068f63 beqz a3,646 <.L98> - -0000008c <.LVL17>: - 8c: 0485 add s1,s1,1 - -0000008e <.LVL18>: - 8e: 7ff00713 li a4,2047 - 92: 0ce48b63 beq s1,a4,168 <.L135> - 96: ff800737 lui a4,0xff800 - 9a: 177d add a4,a4,-1 # ff7fffff <.LLST28+0xff7fed9c> - 9c: 8ff9 and a5,a5,a4 - -0000009e <.LVL19>: - 9e: 810d srl a0,a0,0x3 - -000000a0 <.LVL20>: - a0: 01d79693 sll a3,a5,0x1d - a4: 8ec9 or a3,a3,a0 - a6: a38d j 608 <.L190> - -000000a8 <.L2>: - a8: 0016c293 xor t0,a3,1 - -000000ac <.LBB48>: - ac: 40b48333 sub t1,s1,a1 - -000000b0 <.LBE48>: - b0: 22541b63 bne s0,t0,2e6 <.L8> - -000000b4 <.LBB49>: - b4: 0e605a63 blez t1,1a8 <.L9> - -000000b8 <.LVL24>: - b8: e9a1 bnez a1,108 <.L10> - ba: 00c766b3 or a3,a4,a2 - be: 58068263 beqz a3,642 <.L117> - c2: fff30693 add a3,t1,-1 - -000000c6 <.LVL25>: - c6: ee85 bnez a3,fe <.L12> - -000000c8 <.L193>: - c8: 962a add a2,a2,a0 - -000000ca <.LVL27>: - ca: 00a636b3 sltu a3,a2,a0 - -000000ce <.LVL28>: - ce: 97ba add a5,a5,a4 - -000000d0 <.LVL29>: - d0: 97b6 add a5,a5,a3 - -000000d2 <.LBE16>: - d2: 00800737 lui a4,0x800 - -000000d6 <.LVL30>: - d6: 8f7d and a4,a4,a5 - -000000d8 <.LBB17>: - d8: 8532 mv a0,a2 - -000000da <.LBE17>: - da: 1e071863 bnez a4,2ca <.L109> - -000000de <.L185>: - de: 4485 li s1,1 - -000000e0 <.L11>: - e0: 00757713 and a4,a0,7 - e4: df59 beqz a4,82 <.L95> - e6: 00f57713 and a4,a0,15 - ea: 4691 li a3,4 - ec: f8d70be3 beq a4,a3,82 <.L95> - -000000f0 <.LBB39>: - f0: 00450713 add a4,a0,4 - f4: 00a736b3 sltu a3,a4,a0 - f8: 97b6 add a5,a5,a3 - -000000fa <.LVL34>: - fa: 853a mv a0,a4 - -000000fc <.LVL35>: - fc: b759 j 82 <.L95> - -000000fe <.L12>: - fe: 06731763 bne t1,t2,16c <.L16> - -00000102 <.L132>: - 102: 7ff00493 li s1,2047 - -00000106 <.LVL38>: - 106: bfe9 j e0 <.L11> - -00000108 <.L10>: - 108: fc748ce3 beq s1,t2,e0 <.L11> - -0000010c <.LVL40>: - 10c: 03800693 li a3,56 - 110: 0666c263 blt a3,t1,174 <.L103> - 114: 008006b7 lui a3,0x800 - 118: 8f55 or a4,a4,a3 - -0000011a <.LVL41>: - 11a: 869a mv a3,t1 - -0000011c <.L18>: - 11c: 45fd li a1,31 - 11e: 04d5ce63 blt a1,a3,17a <.L19> - 122: 02000313 li t1,32 - 126: 40d30333 sub t1,t1,a3 - 12a: 00d652b3 srl t0,a2,a3 - -0000012e <.LVL43>: - 12e: 006715b3 sll a1,a4,t1 - 132: 00661333 sll t1,a2,t1 - 136: 0055e5b3 or a1,a1,t0 - 13a: 00603333 snez t1,t1 - 13e: 0065e633 or a2,a1,t1 - 142: 00d756b3 srl a3,a4,a3 - -00000146 <.L17>: - 146: 9532 add a0,a0,a2 - -00000148 <.LVL46>: - 148: 96be add a3,a3,a5 - -0000014a <.LVL47>: - 14a: 00c53633 sltu a2,a0,a2 - -0000014e <.LVL48>: - 14e: 00c687b3 add a5,a3,a2 - -00000152 <.L23>: - 152: 00800737 lui a4,0x800 - 156: 8f7d and a4,a4,a5 - 158: d741 beqz a4,e0 <.L11> - -0000015a <.LVL50>: - 15a: 0485 add s1,s1,1 - -0000015c <.LVL51>: - 15c: 7ff00713 li a4,2047 - 160: 16e49663 bne s1,a4,2cc <.L15> - -00000164 <.L42>: - 164: 7ff00493 li s1,2047 - -00000168 <.L135>: - 168: 4781 li a5,0 - 16a: aa35 j 2a6 <.L191> - -0000016c <.L16>: - 16c: 03800593 li a1,56 - -00000170 <.LVL54>: - 170: fad5d6e3 bge a1,a3,11c <.L18> - -00000174 <.L103>: - 174: 4681 li a3,0 - 176: 4605 li a2,1 - -00000178 <.LVL56>: - 178: b7f9 j 146 <.L17> - -0000017a <.L19>: - 17a: fe068593 add a1,a3,-32 # 7fffe0 <.LLST28+0x7fed7d> - 17e: 02000293 li t0,32 - -00000182 <.LVL58>: - 182: 00b755b3 srl a1,a4,a1 - 186: 4301 li t1,0 - 188: 00568863 beq a3,t0,198 <.L20> - 18c: 04000313 li t1,64 - 190: 40d30333 sub t1,t1,a3 - 194: 00671333 sll t1,a4,t1 - -00000198 <.L20>: - 198: 00c36333 or t1,t1,a2 - 19c: 00603333 snez t1,t1 - 1a0: 0065e633 or a2,a1,t1 - -000001a4 <.LVL59>: - 1a4: 4681 li a3,0 - 1a6: b745 j 146 <.L17> - -000001a8 <.L9>: - 1a8: 0a030863 beqz t1,258 <.L24> - 1ac: 409586b3 sub a3,a1,s1 - -000001b0 <.LVL61>: - 1b0: c4b9 beqz s1,1fe <.L105> - -000001b2 <.LVL62>: - 1b2: 03800313 li t1,56 - 1b6: 06d34763 blt t1,a3,224 <.L112> - 1ba: 00800337 lui t1,0x800 - 1be: 0067e7b3 or a5,a5,t1 - -000001c2 <.L32>: - 1c2: 437d li t1,31 - 1c4: 06d34363 blt t1,a3,22a <.L33> - 1c8: 02000293 li t0,32 - 1cc: 40d282b3 sub t0,t0,a3 - 1d0: 00579333 sll t1,a5,t0 - 1d4: 00d553b3 srl t2,a0,a3 - 1d8: 005512b3 sll t0,a0,t0 - 1dc: 00736333 or t1,t1,t2 - 1e0: 005032b3 snez t0,t0 - 1e4: 00536333 or t1,t1,t0 - -000001e8 <.LVL64>: - 1e8: 00d7d6b3 srl a3,a5,a3 - -000001ec <.L31>: - 1ec: 961a add a2,a2,t1 - -000001ee <.LVL66>: - 1ee: 96ba add a3,a3,a4 - -000001f0 <.LVL67>: - 1f0: 00663333 sltu t1,a2,t1 - -000001f4 <.LVL68>: - 1f4: 8532 mv a0,a2 - -000001f6 <.LVL69>: - 1f6: 006687b3 add a5,a3,t1 - -000001fa <.LBB82>: - 1fa: 84ae mv s1,a1 - -000001fc <.LBB83>: - 1fc: bf99 j 152 <.L23> - -000001fe <.L105>: - 1fe: 84b6 mv s1,a3 - -00000200 <.L25>: - 200: 00a7e6b3 or a3,a5,a0 - 204: ca89 beqz a3,216 <.L125> - 206: fff48693 add a3,s1,-1 - -0000020a <.LVL73>: - 20a: ea068fe3 beqz a3,c8 <.L193> - 20e: 7ff00313 li t1,2047 - 212: 00649563 bne s1,t1,21c <.L178> - -00000216 <.L125>: - 216: 87ba mv a5,a4 - -00000218 <.LVL75>: - 218: 8532 mv a0,a2 - -0000021a <.LVL76>: - 21a: b5d9 j e0 <.L11> - -0000021c <.L178>: - 21c: 03800313 li t1,56 - 220: fad351e3 bge t1,a3,1c2 <.L32> - -00000224 <.L112>: - 224: 4681 li a3,0 - -00000226 <.LVL79>: - 226: 4305 li t1,1 - 228: b7d1 j 1ec <.L31> - -0000022a <.L33>: - 22a: fe068313 add t1,a3,-32 - 22e: 02000393 li t2,32 - 232: 0067d333 srl t1,a5,t1 - 236: 4281 li t0,0 - 238: 00768863 beq a3,t2,248 <.L34> - 23c: 04000293 li t0,64 - 240: 40d282b3 sub t0,t0,a3 - 244: 005792b3 sll t0,a5,t0 - -00000248 <.L34>: - 248: 00a2e2b3 or t0,t0,a0 - 24c: 005032b3 snez t0,t0 - 250: 00536333 or t1,t1,t0 - -00000254 <.LVL81>: - 254: 4681 li a3,0 - -00000256 <.LVL82>: - 256: bf59 j 1ec <.L31> - -00000258 <.L24>: - 258: 00148693 add a3,s1,1 - 25c: 7fe6f593 and a1,a3,2046 - -00000260 <.LVL84>: - 260: e5a9 bnez a1,2aa <.L37> - 262: 00a7e6b3 or a3,a5,a0 - 266: e495 bnez s1,292 <.L38> - -00000268 <.LVL85>: - 268: d6dd beqz a3,216 <.L125> - 26a: 00c766b3 or a3,a4,a2 - 26e: e60689e3 beqz a3,e0 <.L11> - -00000272 <.LBB25>: - 272: 962a add a2,a2,a0 - -00000274 <.LVL86>: - 274: 00a636b3 sltu a3,a2,a0 - 278: 97ba add a5,a5,a4 - -0000027a <.LVL87>: - 27a: 97b6 add a5,a5,a3 - -0000027c <.LBE25>: - 27c: 00800737 lui a4,0x800 - -00000280 <.LVL88>: - 280: 8f7d and a4,a4,a5 - -00000282 <.LBB26>: - 282: 8532 mv a0,a2 - -00000284 <.LBE26>: - 284: e4070ee3 beqz a4,e0 <.L11> - 288: ff800737 lui a4,0xff800 - 28c: 177d add a4,a4,-1 # ff7fffff <.LLST28+0xff7fed9c> - 28e: 8ff9 and a5,a5,a4 - -00000290 <.LVL90>: - 290: b5b9 j de <.L185> - -00000292 <.L38>: - 292: 3a068563 beqz a3,63c <.L115> - 296: 8f51 or a4,a4,a2 - -00000298 <.LVL92>: - 298: e60705e3 beqz a4,102 <.L132> - -0000029c <.L189>: - 29c: 4401 li s0,0 - -0000029e <.LBB87>: - 29e: 7ff00493 li s1,2047 - -000002a2 <.LBB88>: - 2a2: 000807b7 lui a5,0x80 - -000002a6 <.L191>: - 2a6: 4681 li a3,0 - 2a8: a68d j 60a <.L41> - -000002aa <.L37>: - 2aa: 7ff00593 li a1,2047 - 2ae: eab68be3 beq a3,a1,164 <.L42> - 2b2: 962a add a2,a2,a0 - -000002b4 <.LBB29>: - 2b4: 00a63533 sltu a0,a2,a0 - -000002b8 <.LVL98>: - 2b8: 97ba add a5,a5,a4 - -000002ba <.LVL99>: - 2ba: 97aa add a5,a5,a0 - -000002bc <.LBE29>: - 2bc: 01f79513 sll a0,a5,0x1f - 2c0: 8205 srl a2,a2,0x1 - -000002c2 <.LVL100>: - 2c2: 8d51 or a0,a0,a2 - 2c4: 8385 srl a5,a5,0x1 - 2c6: 84b6 mv s1,a3 - -000002c8 <.LVL101>: - 2c8: bd21 j e0 <.L11> - -000002ca <.L109>: - 2ca: 4489 li s1,2 - -000002cc <.L15>: - 2cc: ff800737 lui a4,0xff800 - 2d0: 177d add a4,a4,-1 # ff7fffff <.LLST28+0xff7fed9c> - 2d2: 8ff9 and a5,a5,a4 - -000002d4 <.LVL104>: - 2d4: 00155713 srl a4,a0,0x1 - 2d8: 8905 and a0,a0,1 - 2da: 8f49 or a4,a4,a0 - 2dc: 01f79513 sll a0,a5,0x1f - 2e0: 8d59 or a0,a0,a4 - 2e2: 8385 srl a5,a5,0x1 - 2e4: bbf5 j e0 <.L11> - -000002e6 <.L8>: - 2e6: 0e605763 blez t1,3d4 <.L45> - -000002ea <.LVL106>: - 2ea: e995 bnez a1,31e <.L46> - 2ec: 00c766b3 or a3,a4,a2 - 2f0: 34068963 beqz a3,642 <.L117> - 2f4: fff30693 add a3,t1,-1 # 7fffff <.LLST28+0x7fed9c> - -000002f8 <.LVL107>: - 2f8: ea91 bnez a3,30c <.L47> - -000002fa <.LBB51>: - 2fa: 40c50633 sub a2,a0,a2 - -000002fe <.LVL108>: - 2fe: 00c536b3 sltu a3,a0,a2 - -00000302 <.LVL109>: - 302: 8f99 sub a5,a5,a4 - -00000304 <.LVL110>: - 304: 8532 mv a0,a2 - -00000306 <.LVL111>: - 306: 8f95 sub a5,a5,a3 - -00000308 <.L183>: - 308: 4485 li s1,1 - -0000030a <.LBB92>: - 30a: a095 j 36e <.L50> - -0000030c <.L47>: - 30c: de730be3 beq t1,t2,102 <.L132> - -00000310 <.L51>: - 310: 03800593 li a1,56 - -00000314 <.LVL114>: - 314: 00d5df63 bge a1,a3,332 <.L53> - -00000318 <.L120>: - 318: 4681 li a3,0 - 31a: 4605 li a2,1 - -0000031c <.LVL116>: - 31c: a081 j 35c <.L52> - -0000031e <.L46>: - 31e: dc7481e3 beq s1,t2,e0 <.L11> - -00000322 <.LVL118>: - 322: 03800693 li a3,56 - 326: fe66c9e3 blt a3,t1,318 <.L120> - 32a: 008006b7 lui a3,0x800 - 32e: 8f55 or a4,a4,a3 - -00000330 <.LVL119>: - 330: 869a mv a3,t1 - -00000332 <.L53>: - 332: 45fd li a1,31 - 334: 04d5c763 blt a1,a3,382 <.L54> - 338: 02000313 li t1,32 - 33c: 40d30333 sub t1,t1,a3 - 340: 00d652b3 srl t0,a2,a3 - -00000344 <.LVL121>: - 344: 006715b3 sll a1,a4,t1 - 348: 00661333 sll t1,a2,t1 - 34c: 0055e5b3 or a1,a1,t0 - 350: 00603333 snez t1,t1 - 354: 0065e633 or a2,a1,t1 - 358: 00d756b3 srl a3,a4,a3 - -0000035c <.L52>: - 35c: 40c50633 sub a2,a0,a2 - -00000360 <.LVL124>: - 360: 00c53733 sltu a4,a0,a2 - 364: 40d786b3 sub a3,a5,a3 - -00000368 <.LVL125>: - 368: 8532 mv a0,a2 - -0000036a <.LVL126>: - 36a: 40e687b3 sub a5,a3,a4 - -0000036e <.L50>: - 36e: 008005b7 lui a1,0x800 - 372: 00b7f733 and a4,a5,a1 - 376: d60705e3 beqz a4,e0 <.L11> - -0000037a <.LBB55>: - 37a: 15fd add a1,a1,-1 # 7fffff <.LLST28+0x7fed9c> - 37c: 8dfd and a1,a1,a5 - -0000037e <.LVL128>: - 37e: 832a mv t1,a0 - 380: a2d1 j 544 <.L85> - -00000382 <.L54>: - 382: fe068593 add a1,a3,-32 # 7fffe0 <.LLST28+0x7fed7d> - 386: 02000293 li t0,32 - -0000038a <.LVL130>: - 38a: 00b755b3 srl a1,a4,a1 - 38e: 4301 li t1,0 - 390: 00568863 beq a3,t0,3a0 <.L55> - 394: 04000313 li t1,64 - 398: 40d30333 sub t1,t1,a3 - 39c: 00671333 sll t1,a4,t1 - -000003a0 <.L55>: - 3a0: 00c36333 or t1,t1,a2 - 3a4: 00603333 snez t1,t1 - 3a8: 0065e633 or a2,a1,t1 - -000003ac <.LVL131>: - 3ac: 4681 li a3,0 - 3ae: b77d j 35c <.L52> - -000003b0 <.L174>: - 3b0: 0e030a63 beqz t1,4a4 <.L58> - -000003b4 <.LVL133>: - 3b4: c4b1 beqz s1,400 <.L122> - -000003b6 <.LBE92>: - 3b6: 87ba mv a5,a4 - -000003b8 <.LVL134>: - 3b8: 8532 mv a0,a2 - -000003ba <.LBB94>: - 3ba: 7ff00493 li s1,2047 - -000003be <.LVL136>: - 3be: 8436 mv s0,a3 - -000003c0 <.LVL137>: - 3c0: b305 j e0 <.L11> - -000003c2 <.L175>: - 3c2: 0e030163 beqz t1,4a4 <.L58> - -000003c6 <.LVL139>: - 3c6: c0a9 beqz s1,408 <.L123> - -000003c8 <.LBE94>: - 3c8: 4781 li a5,0 - -000003ca <.LVL140>: - 3ca: 4501 li a0,0 - -000003cc <.LBB96>: - 3cc: 7ff00493 li s1,2047 - -000003d0 <.LVL142>: - 3d0: 8416 mv s0,t0 - -000003d2 <.LVL143>: - 3d2: b945 j 82 <.L95> - -000003d4 <.L45>: - 3d4: 0c030863 beqz t1,4a4 <.L58> - 3d8: 409586b3 sub a3,a1,s1 - -000003dc <.LVL145>: - 3dc: e0b9 bnez s1,422 <.L60> - 3de: 8416 mv s0,t0 - -000003e0 <.LVL146>: - 3e0: 84b6 mv s1,a3 - -000003e2 <.L59>: - 3e2: 00a7e6b3 or a3,a5,a0 - 3e6: e20688e3 beqz a3,216 <.L125> - 3ea: fff48693 add a3,s1,-1 - -000003ee <.LVL148>: - 3ee: ee99 bnez a3,40c <.L61> - -000003f0 <.LBB62>: - 3f0: 40a60533 sub a0,a2,a0 - -000003f4 <.LVL150>: - 3f4: 40f707b3 sub a5,a4,a5 - -000003f8 <.LVL151>: - 3f8: 00a63633 sltu a2,a2,a0 - -000003fc <.LVL152>: - 3fc: 8f91 sub a5,a5,a2 - 3fe: b729 j 308 <.L183> - -00000400 <.L122>: - 400: 8436 mv s0,a3 - -00000402 <.L182>: - 402: 7ff00493 li s1,2047 - -00000406 <.LVL155>: - 406: bff1 j 3e2 <.L59> - -00000408 <.L123>: - 408: 8416 mv s0,t0 - -0000040a <.LVL157>: - 40a: bfe5 j 402 <.L182> - -0000040c <.L61>: - 40c: 7ff00313 li t1,2047 - 410: e06483e3 beq s1,t1,216 <.L125> - -00000414 <.L64>: - 414: 03800313 li t1,56 - 418: 00d35e63 bge t1,a3,434 <.L66> - -0000041c <.L127>: - 41c: 4681 li a3,0 - -0000041e <.LVL160>: - 41e: 4505 li a0,1 - -00000420 <.LVL161>: - 420: a83d j 45e <.L65> - -00000422 <.L60>: - 422: 03800313 li t1,56 - 426: 06d34d63 blt t1,a3,4a0 <.L126> - 42a: 00800337 lui t1,0x800 - 42e: 0067e7b3 or a5,a5,t1 - -00000432 <.LVL163>: - 432: 8416 mv s0,t0 - -00000434 <.L66>: - 434: 437d li t1,31 - 436: 02d34e63 blt t1,a3,472 <.L67> - 43a: 02000293 li t0,32 - -0000043e <.LVL165>: - 43e: 40d282b3 sub t0,t0,a3 - 442: 00d553b3 srl t2,a0,a3 - 446: 00579333 sll t1,a5,t0 - 44a: 005512b3 sll t0,a0,t0 - 44e: 00736333 or t1,t1,t2 - 452: 005032b3 snez t0,t0 - 456: 00536533 or a0,t1,t0 - 45a: 00d7d6b3 srl a3,a5,a3 - -0000045e <.L65>: - 45e: 40a60533 sub a0,a2,a0 - -00000462 <.LVL168>: - 462: 40d706b3 sub a3,a4,a3 - -00000466 <.LVL169>: - 466: 00a637b3 sltu a5,a2,a0 - 46a: 40f687b3 sub a5,a3,a5 - -0000046e <.LBB97>: - 46e: 84ae mv s1,a1 - -00000470 <.LBB98>: - 470: bdfd j 36e <.L50> - -00000472 <.L67>: - 472: fe068313 add t1,a3,-32 - 476: 02000393 li t2,32 - 47a: 0067d333 srl t1,a5,t1 - 47e: 4281 li t0,0 - -00000480 <.LVL172>: - 480: 00768863 beq a3,t2,490 <.L68> - 484: 04000293 li t0,64 - 488: 40d282b3 sub t0,t0,a3 - 48c: 005792b3 sll t0,a5,t0 - -00000490 <.L68>: - 490: 00a2e2b3 or t0,t0,a0 - 494: 005032b3 snez t0,t0 - 498: 00536533 or a0,t1,t0 - -0000049c <.LVL173>: - 49c: 4681 li a3,0 - -0000049e <.LVL174>: - 49e: b7c1 j 45e <.L65> - -000004a0 <.L126>: - 4a0: 8416 mv s0,t0 - -000004a2 <.LVL176>: - 4a2: bfad j 41c <.L127> - -000004a4 <.L58>: - 4a4: 00148693 add a3,s1,1 - 4a8: 7fe6f693 and a3,a3,2046 - 4ac: e2bd bnez a3,512 <.L71> - -000004ae <.LBE98>: - 4ae: 00c766b3 or a3,a4,a2 - -000004b2 <.LBB99>: - 4b2: 00a7e5b3 or a1,a5,a0 - -000004b6 <.LBB100>: - 4b6: e4a1 bnez s1,4fe <.L72> - -000004b8 <.LVL179>: - 4b8: e599 bnez a1,4c6 <.L73> - -000004ba <.LVL180>: - 4ba: 1a068663 beqz a3,666 <.L130> - -000004be <.LBE100>: - 4be: 87ba mv a5,a4 - -000004c0 <.LVL181>: - 4c0: 8532 mv a0,a2 - -000004c2 <.L187>: - 4c2: 8416 mv s0,t0 - -000004c4 <.LVL183>: - 4c4: b931 j e0 <.L11> - -000004c6 <.L73>: - 4c6: c0068de3 beqz a3,e0 <.L11> - -000004ca <.LBB67>: - 4ca: 40c50333 sub t1,a0,a2 - -000004ce <.LVL185>: - 4ce: 006536b3 sltu a3,a0,t1 - 4d2: 40e785b3 sub a1,a5,a4 - 4d6: 8d95 sub a1,a1,a3 - -000004d8 <.LBE67>: - 4d8: 008006b7 lui a3,0x800 - 4dc: 8eed and a3,a3,a1 - 4de: ca89 beqz a3,4f0 <.L76> - -000004e0 <.LBB68>: - 4e0: 40a60533 sub a0,a2,a0 - -000004e4 <.LVL188>: - 4e4: 40f707b3 sub a5,a4,a5 - -000004e8 <.LVL189>: - 4e8: 00a63633 sltu a2,a2,a0 - -000004ec <.LVL190>: - 4ec: 8f91 sub a5,a5,a2 - 4ee: bfd1 j 4c2 <.L187> - -000004f0 <.L76>: - 4f0: 00b366b3 or a3,t1,a1 - 4f4: 16068963 beqz a3,666 <.L130> - 4f8: 87ae mv a5,a1 - -000004fa <.LBB69>: - 4fa: 851a mv a0,t1 - -000004fc <.LVL193>: - 4fc: b6d5 j e0 <.L11> - -000004fe <.L72>: - 4fe: e599 bnez a1,50c <.L79> - 500: 16068563 beqz a3,66a <.L131> - -00000504 <.LBE102>: - 504: 87ba mv a5,a4 - -00000506 <.LVL195>: - 506: 8532 mv a0,a2 - -00000508 <.LBB104>: - 508: 8416 mv s0,t0 - -0000050a <.LVL197>: - 50a: bee5 j 102 <.L132> - -0000050c <.L79>: - 50c: be068be3 beqz a3,102 <.L132> - 510: b371 j 29c <.L189> - -00000512 <.L71>: - 512: 40c506b3 sub a3,a0,a2 - 516: 00d533b3 sltu t2,a0,a3 - 51a: 40e785b3 sub a1,a5,a4 - -0000051e <.LVL200>: - 51e: 407585b3 sub a1,a1,t2 - -00000522 <.LBE70>: - 522: 008003b7 lui t2,0x800 - 526: 0075f3b3 and t2,a1,t2 - -0000052a <.LBB71>: - 52a: 8336 mv t1,a3 - -0000052c <.LBE71>: - 52c: 06038863 beqz t2,59c <.L82> - -00000530 <.LBB72>: - 530: 40a60533 sub a0,a2,a0 - -00000534 <.LVL202>: - 534: 40f707b3 sub a5,a4,a5 - -00000538 <.LVL203>: - 538: 00a63633 sltu a2,a2,a0 - -0000053c <.LVL204>: - 53c: 832a mv t1,a0 - -0000053e <.LVL205>: - 53e: 40c785b3 sub a1,a5,a2 - -00000542 <.LBE72>: - 542: 8416 mv s0,t0 - -00000544 <.L85>: - 544: c1ad beqz a1,5a6 <.L86> - 546: 852e mv a0,a1 - 548: c21a sw t1,4(sp) - 54a: c02e sw a1,0(sp) - 54c: 00000097 auipc ra,0x0 - 550: 000080e7 jalr ra # 54c <.L85+0x8> - -00000554 <.LVL208>: - 554: 4582 lw a1,0(sp) - 556: 4312 lw t1,4(sp) - 558: ff850793 add a5,a0,-8 - -0000055c <.L87>: - 55c: 02000713 li a4,32 - 560: 8f1d sub a4,a4,a5 - 562: 00f595b3 sll a1,a1,a5 - -00000566 <.LVL210>: - 566: 00e35733 srl a4,t1,a4 - 56a: 8f4d or a4,a4,a1 - -0000056c <.LVL211>: - 56c: 00f315b3 sll a1,t1,a5 - -00000570 <.LVL212>: - 570: 0a97cf63 blt a5,s1,62e <.L89> - 574: 8f85 sub a5,a5,s1 - -00000576 <.LVL213>: - 576: 00178613 add a2,a5,1 # 80001 <.LLST28+0x7ed9e> - -0000057a <.L90>: - 57a: 02000693 li a3,32 - 57e: 8e91 sub a3,a3,a2 - 580: 00d71533 sll a0,a4,a3 - 584: 00c5d7b3 srl a5,a1,a2 - 588: 00d596b3 sll a3,a1,a3 - 58c: 8d5d or a0,a0,a5 - 58e: 00d036b3 snez a3,a3 - 592: 8d55 or a0,a0,a3 - -00000594 <.LVL215>: - 594: 00c757b3 srl a5,a4,a2 - -00000598 <.L186>: - 598: 4481 li s1,0 - -0000059a <.LVL217>: - 59a: b699 j e0 <.L11> - -0000059c <.L82>: - 59c: 8ecd or a3,a3,a1 - 59e: f2dd bnez a3,544 <.L85> - -000005a0 <.LBB105>: - 5a0: 4781 li a5,0 - -000005a2 <.LBB106>: - 5a2: 4481 li s1,0 - -000005a4 <.LVL220>: - 5a4: a87d j 662 <.L188> - -000005a6 <.L86>: - 5a6: 851a mv a0,t1 - 5a8: c22e sw a1,4(sp) - 5aa: c01a sw t1,0(sp) - 5ac: 00000097 auipc ra,0x0 - 5b0: 000080e7 jalr ra # 5ac <.L86+0x6> - -000005b4 <.LVL222>: - 5b4: 01850793 add a5,a0,24 - -000005b8 <.LVL223>: - 5b8: 46fd li a3,31 - 5ba: 4302 lw t1,0(sp) - 5bc: 4592 lw a1,4(sp) - 5be: f8f6dfe3 bge a3,a5,55c <.L87> - -000005c2 <.LVL224>: - 5c2: 1561 add a0,a0,-8 - 5c4: 00a31733 sll a4,t1,a0 - -000005c8 <.LVL225>: - 5c8: 0297c963 blt a5,s1,5fa <.L91> - 5cc: 8f85 sub a5,a5,s1 - -000005ce <.LVL226>: - 5ce: 00178613 add a2,a5,1 - -000005d2 <.LVL227>: - 5d2: fac6d4e3 bge a3,a2,57a <.L90> - 5d6: 1785 add a5,a5,-31 - 5d8: 02000693 li a3,32 - 5dc: 00f757b3 srl a5,a4,a5 - 5e0: 4501 li a0,0 - 5e2: 00d60763 beq a2,a3,5f0 <.L93> - 5e6: 04000513 li a0,64 - 5ea: 8d11 sub a0,a0,a2 - 5ec: 00a71533 sll a0,a4,a0 - -000005f0 <.L93>: - 5f0: 00a03533 snez a0,a0 - 5f4: 8d5d or a0,a0,a5 - -000005f6 <.LVL228>: - 5f6: 4781 li a5,0 - 5f8: b745 j 598 <.L186> - -000005fa <.L91>: - 5fa: 8c9d sub s1,s1,a5 - 5fc: ff8007b7 lui a5,0xff800 - -00000600 <.LVL231>: - 600: 17fd add a5,a5,-1 # ff7fffff <.LLST28+0xff7fed9c> - 602: 8ff9 and a5,a5,a4 - -00000604 <.LBB107>: - 604: 01d79693 sll a3,a5,0x1d - -00000608 <.L190>: - 608: 838d srl a5,a5,0x3 - -0000060a <.L41>: - 60a: 01449713 sll a4,s1,0x14 - 60e: 7ff00637 lui a2,0x7ff00 - 612: 07b2 sll a5,a5,0xc - -00000614 <.LVL235>: - 614: 8f71 and a4,a4,a2 - 616: 83b1 srl a5,a5,0xc - 618: 047e sll s0,s0,0x1f - -0000061a <.LVL236>: - 61a: 8fd9 or a5,a5,a4 - -0000061c <.LBE108>: - 61c: 40c2 lw ra,16(sp) - -0000061e <.LBB109>: - 61e: 0087e733 or a4,a5,s0 - -00000622 <.LBE109>: - 622: 4432 lw s0,12(sp) - 624: 44a2 lw s1,8(sp) - 626: 8536 mv a0,a3 - 628: 85ba mv a1,a4 - 62a: 0151 add sp,sp,20 - 62c: 8082 ret - -0000062e <.L89>: - 62e: 8c9d sub s1,s1,a5 - 630: ff8007b7 lui a5,0xff800 - -00000634 <.LVL240>: - 634: 17fd add a5,a5,-1 # ff7fffff <.LLST28+0xff7fed9c> - 636: 8ff9 and a5,a5,a4 - -00000638 <.LVL241>: - 638: 852e mv a0,a1 - 63a: b45d j e0 <.L11> - -0000063c <.L115>: - 63c: 87ba mv a5,a4 - -0000063e <.LVL243>: - 63e: 8532 mv a0,a2 - -00000640 <.LVL244>: - 640: b4c9 j 102 <.L132> - -00000642 <.L117>: - 642: 849a mv s1,t1 - -00000644 <.LVL246>: - 644: bc71 j e0 <.L11> - -00000646 <.L98>: - 646: 01d79713 sll a4,a5,0x1d - 64a: 810d srl a0,a0,0x3 - -0000064c <.LVL248>: - 64c: 7ff00613 li a2,2047 - 650: 8f49 or a4,a4,a0 - -00000652 <.LVL249>: - 652: 838d srl a5,a5,0x3 - 654: 02c49163 bne s1,a2,676 <.L136> - -00000658 <.LVL251>: - 658: 8f5d or a4,a4,a5 - 65a: 000807b7 lui a5,0x80 - 65e: b00703e3 beqz a4,164 <.L42> - -00000662 <.L188>: - 662: 4401 li s0,0 - 664: b75d j 60a <.L41> - -00000666 <.L130>: - 666: 4781 li a5,0 - -00000668 <.LVL253>: - 668: bfed j 662 <.L188> - -0000066a <.L131>: - 66a: 4401 li s0,0 - -0000066c <.LBB114>: - 66c: 7ff00493 li s1,2047 - -00000670 <.LBB115>: - 670: 000807b7 lui a5,0x80 - -00000674 <.LVL257>: - 674: bf59 j 60a <.L41> - -00000676 <.L136>: - 676: 86ba mv a3,a4 - 678: bf49 j 60a <.L41> - -unorddf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__unorddf2>: - 0: 001007b7 lui a5,0x100 - 4: 17fd add a5,a5,-1 # fffff <.LASF16+0xffe47> - 6: 00b7f733 and a4,a5,a1 - -0000000a <.LVL1>: - a: 81d1 srl a1,a1,0x14 - -0000000c <.LBB3>: - c: 8ff5 and a5,a5,a3 - -0000000e <.LBB4>: - e: 7ff5f593 and a1,a1,2047 - -00000012 <.LBB5>: - 12: 82d1 srl a3,a3,0x14 - -00000014 <.LBE5>: - 14: 7ff00313 li t1,2047 - -00000018 <.LBB6>: - 18: 7ff6f693 and a3,a3,2047 - -0000001c <.LBE6>: - 1c: 00659563 bne a1,t1,26 <.L2> - 20: 8f49 or a4,a4,a0 - -00000022 <.LVL6>: - 22: 4505 li a0,1 - -00000024 <.LVL7>: - 24: eb09 bnez a4,36 <.L1> - -00000026 <.L2>: - 26: 7ff00713 li a4,2047 - 2a: 4501 li a0,0 - 2c: 00e69563 bne a3,a4,36 <.L1> - 30: 8fd1 or a5,a5,a2 - -00000032 <.LVL8>: - 32: 00f03533 snez a0,a5 - -00000036 <.L1>: - 36: 8082 ret - -fixdfsi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixdfsi>: - 0: 0145d713 srl a4,a1,0x14 - 4: 00100637 lui a2,0x100 - -00000008 <.LBE2>: - 8: 86aa mv a3,a0 - -0000000a <.LBB3>: - a: fff60793 add a5,a2,-1 # fffff <.LASF13+0xffe50> - e: 7ff77713 and a4,a4,2047 - -00000012 <.LBE3>: - 12: 3fe00513 li a0,1022 - -00000016 <.LBB4>: - 16: 8fed and a5,a5,a1 - -00000018 <.LVL3>: - 18: 81fd srl a1,a1,0x1f - -0000001a <.LBE4>: - 1a: 04e55563 bge a0,a4,64 <.L6> - 1e: 41d00513 li a0,1053 - 22: 00e55863 bge a0,a4,32 <.L3> - -00000026 <.LVL5>: - 26: 80000537 lui a0,0x80000 - 2a: fff54513 not a0,a0 - 2e: 952e add a0,a0,a1 - -00000030 <.LVL6>: - 30: 8082 ret - -00000032 <.L3>: - 32: 8fd1 or a5,a5,a2 - 34: 43300613 li a2,1075 - 38: 8e19 sub a2,a2,a4 - 3a: 457d li a0,31 - 3c: 00c54d63 blt a0,a2,56 <.L4> - -00000040 <.LVL9>: - 40: bed70713 add a4,a4,-1043 - -00000044 <.LVL10>: - 44: 00e79533 sll a0,a5,a4 - 48: 00c6d6b3 srl a3,a3,a2 - 4c: 8d55 or a0,a0,a3 - -0000004e <.L5>: - 4e: cd81 beqz a1,66 <.L2> - 50: 40a00533 neg a0,a0 - -00000054 <.LVL12>: - 54: 8082 ret - -00000056 <.L4>: - 56: 41300693 li a3,1043 - 5a: 40e68733 sub a4,a3,a4 - -0000005e <.LVL14>: - 5e: 00e7d533 srl a0,a5,a4 - -00000062 <.LVL15>: - 62: b7f5 j 4e <.L5> - -00000064 <.L6>: - 64: 4501 li a0,0 - -00000066 <.L2>: - 66: 8082 ret - -fixunsdfsi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixunsdfsi>: - 0: 0145d713 srl a4,a1,0x14 - 4: 00100637 lui a2,0x100 - -00000008 <.LBE2>: - 8: 86aa mv a3,a0 - -0000000a <.LBB3>: - a: fff60793 add a5,a2,-1 # fffff <.LASF25+0xffe5b> - e: 7ff77713 and a4,a4,2047 - -00000012 <.LBE3>: - 12: 3fe00513 li a0,1022 - -00000016 <.LBB4>: - 16: 8fed and a5,a5,a1 - -00000018 <.LVL3>: - 18: 81fd srl a1,a1,0x1f - -0000001a <.LBE4>: - 1a: 02e55f63 bge a0,a4,58 <.L4> - 1e: 4501 li a0,0 - 20: ed8d bnez a1,5a <.L1> - 22: 41e00593 li a1,1054 - -00000026 <.LVL5>: - 26: 557d li a0,-1 - 28: 02e5c963 blt a1,a4,5a <.L1> - -0000002c <.LBB5>: - 2c: 8fd1 or a5,a5,a2 - 2e: 43300613 li a2,1075 - 32: 8e19 sub a2,a2,a4 - 34: 45fd li a1,31 - 36: 00c5ca63 blt a1,a2,4a <.L3> - -0000003a <.LVL8>: - 3a: bed70713 add a4,a4,-1043 - -0000003e <.LVL9>: - 3e: 00e79533 sll a0,a5,a4 - 42: 00c6d6b3 srl a3,a3,a2 - 46: 8d55 or a0,a0,a3 - -00000048 <.LVL10>: - 48: 8082 ret - -0000004a <.L3>: - 4a: 41300693 li a3,1043 - 4e: 40e68733 sub a4,a3,a4 - -00000052 <.LVL12>: - 52: 00e7d533 srl a0,a5,a4 - -00000056 <.LVL13>: - 56: 8082 ret - -00000058 <.L4>: - 58: 4501 li a0,0 - -0000005a <.L1>: - 5a: 8082 ret - -floatsidf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatsidf>: - 0: 1151 add sp,sp,-12 - 2: c406 sw ra,8(sp) - 4: c222 sw s0,4(sp) - 6: c026 sw s1,0(sp) - -00000008 <.LBB10>: - 8: cd39 beqz a0,66 <.L5> - -0000000a <.LBB3>: - a: 41f55793 sra a5,a0,0x1f - e: 00a7c433 xor s0,a5,a0 - 12: 8c1d sub s0,s0,a5 - 14: 01f55493 srl s1,a0,0x1f - -00000018 <.LBB4>: - 18: 8522 mv a0,s0 - -0000001a <.LVL3>: - 1a: 00000097 auipc ra,0x0 - 1e: 000080e7 jalr ra # 1a <.LVL3> - -00000022 <.LVL4>: - 22: 41e00693 li a3,1054 - -00000026 <.LBE4>: - 26: 47a9 li a5,10 - -00000028 <.LBB5>: - 28: 8e89 sub a3,a3,a0 - -0000002a <.LBE5>: - 2a: 02a7c863 blt a5,a0,5a <.L4> - 2e: 47ad li a5,11 - 30: 8f89 sub a5,a5,a0 - 32: 0555 add a0,a0,21 - -00000034 <.LVL6>: - 34: 00a41733 sll a4,s0,a0 - 38: 00f457b3 srl a5,s0,a5 - -0000003c <.LVL7>: - 3c: 8526 mv a0,s1 - -0000003e <.L2>: - 3e: 07b2 sll a5,a5,0xc - -00000040 <.LBE11>: - 40: 40a2 lw ra,8(sp) - 42: 4412 lw s0,4(sp) - -00000044 <.LBB12>: - 44: 83b1 srl a5,a5,0xc - 46: 06d2 sll a3,a3,0x14 - -00000048 <.LVL10>: - 48: 057e sll a0,a0,0x1f - -0000004a <.LVL11>: - 4a: 8edd or a3,a3,a5 - 4c: 00a6e7b3 or a5,a3,a0 - -00000050 <.LBE12>: - 50: 4482 lw s1,0(sp) - 52: 853a mv a0,a4 - 54: 85be mv a1,a5 - 56: 0131 add sp,sp,12 - 58: 8082 ret - -0000005a <.L4>: - 5a: 1555 add a0,a0,-11 - -0000005c <.LVL14>: - 5c: 00a417b3 sll a5,s0,a0 - -00000060 <.LVL15>: - 60: 8526 mv a0,s1 - -00000062 <.L7>: - 62: 4701 li a4,0 - 64: bfe9 j 3e <.L2> - -00000066 <.L5>: - 66: 4681 li a3,0 - 68: 4781 li a5,0 - 6a: bfe5 j 62 <.L7> - -floatunsidf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatunsidf>: - 0: 1151 add sp,sp,-12 - 2: c222 sw s0,4(sp) - 4: c406 sw ra,8(sp) - 6: 842a mv s0,a0 - -00000008 <.LBB10>: - 8: c131 beqz a0,4c <.L4> - -0000000a <.LBB3>: - a: 00000097 auipc ra,0x0 - e: 000080e7 jalr ra # a <.LBB3> - -00000012 <.LVL2>: - 12: 41e00713 li a4,1054 - -00000016 <.LBE4>: - 16: 47a9 li a5,10 - -00000018 <.LBB5>: - 18: 8f09 sub a4,a4,a0 - -0000001a <.LBE5>: - 1a: 02a7c463 blt a5,a0,42 <.L3> - 1e: 47ad li a5,11 - 20: 8f89 sub a5,a5,a0 - 22: 0555 add a0,a0,21 - -00000024 <.LVL4>: - 24: 00f457b3 srl a5,s0,a5 - -00000028 <.LVL5>: - 28: 00a41433 sll s0,s0,a0 - -0000002c <.L2>: - 2c: 40a2 lw ra,8(sp) - 2e: 8522 mv a0,s0 - -00000030 <.LBB12>: - 30: 07b2 sll a5,a5,0xc - -00000032 <.LBE12>: - 32: 4412 lw s0,4(sp) - -00000034 <.LBB13>: - 34: 0752 sll a4,a4,0x14 - -00000036 <.LVL9>: - 36: 83b1 srl a5,a5,0xc - 38: 00f766b3 or a3,a4,a5 - -0000003c <.LBE13>: - 3c: 85b6 mv a1,a3 - 3e: 0131 add sp,sp,12 - 40: 8082 ret - -00000042 <.L3>: - 42: 1555 add a0,a0,-11 - -00000044 <.LVL11>: - 44: 00a417b3 sll a5,s0,a0 - -00000048 <.LVL12>: - 48: 4401 li s0,0 - -0000004a <.LVL13>: - 4a: b7cd j 2c <.L2> - -0000004c <.L4>: - 4c: 4781 li a5,0 - 4e: 4701 li a4,0 - 50: bff1 j 2c <.L2> - -fixdfdi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixdfdi>: - 0: 00100737 lui a4,0x100 - 4: 0145d613 srl a2,a1,0x14 - 8: fff70793 add a5,a4,-1 # fffff <.LLST8+0xffe2b> - c: 7ff67613 and a2,a2,2047 - -00000010 <.LBE2>: - 10: 3fe00693 li a3,1022 - -00000014 <.LBB3>: - 14: 8fed and a5,a5,a1 - -00000016 <.LBE3>: - 16: 08c6d763 bge a3,a2,a4 <.L8> - 1a: 1151 add sp,sp,-12 - 1c: c222 sw s0,4(sp) - 1e: c406 sw ra,8(sp) - 20: 43d00693 li a3,1085 - 24: 01f5d413 srl s0,a1,0x1f - 28: 02c6d263 bge a3,a2,4c <.L3> - -0000002c <.LVL2>: - 2c: 4505 li a0,1 - -0000002e <.LVL3>: - 2e: 8d01 sub a0,a0,s0 - 30: 41f55713 sra a4,a0,0x1f - 34: 800005b7 lui a1,0x80000 - -00000038 <.LVL4>: - 38: 00a037b3 snez a5,a0 - -0000003c <.LVL5>: - 3c: 8d99 sub a1,a1,a4 - 3e: 40a00533 neg a0,a0 - 42: 8d9d sub a1,a1,a5 - -00000044 <.L2>: - 44: 40a2 lw ra,8(sp) - 46: 4412 lw s0,4(sp) - 48: 0131 add sp,sp,12 - 4a: 8082 ret - -0000004c <.L3>: - 4c: 00e7e5b3 or a1,a5,a4 - -00000050 <.LVL8>: - 50: 43200793 li a5,1074 - 54: 02c7d163 bge a5,a2,76 <.L4> - -00000058 <.LVL9>: - 58: bcd60613 add a2,a2,-1075 - -0000005c <.LVL10>: - 5c: 00000097 auipc ra,0x0 - 60: 000080e7 jalr ra # 5c <.LVL10> - -00000064 <.L5>: - 64: d065 beqz s0,44 <.L2> - 66: 00a037b3 snez a5,a0 - 6a: 40b005b3 neg a1,a1 - -0000006e <.LVL12>: - 6e: 8d9d sub a1,a1,a5 - 70: 40a00533 neg a0,a0 - 74: bfc1 j 44 <.L2> - -00000076 <.L4>: - 76: 43300713 li a4,1075 - 7a: 8f11 sub a4,a4,a2 - 7c: 47fd li a5,31 - 7e: 00e7cc63 blt a5,a4,96 <.L6> - -00000082 <.LVL15>: - 82: bed60793 add a5,a2,-1043 - 86: 00f597b3 sll a5,a1,a5 - 8a: 00e55533 srl a0,a0,a4 - -0000008e <.LVL16>: - 8e: 8d5d or a0,a0,a5 - -00000090 <.LVL17>: - 90: 00e5d5b3 srl a1,a1,a4 - 94: bfc1 j 64 <.L5> - -00000096 <.L6>: - 96: 41300513 li a0,1043 - -0000009a <.LVL20>: - 9a: 8d11 sub a0,a0,a2 - 9c: 00a5d533 srl a0,a1,a0 - -000000a0 <.LVL21>: - a0: 4581 li a1,0 - a2: b7c9 j 64 <.L5> - -000000a4 <.L8>: - a4: 4501 li a0,0 - -000000a6 <.LVL24>: - a6: 4581 li a1,0 - -000000a8 <.LVL25>: - a8: 8082 ret - -fixunsdfdi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixunsdfdi>: - 0: 001006b7 lui a3,0x100 - 4: 0145d613 srl a2,a1,0x14 - 8: fff68713 add a4,a3,-1 # fffff <.LASF12+0xffe4a> - c: 8f6d and a4,a4,a1 - -0000000e <.LVL1>: - e: 01f5d793 srl a5,a1,0x1f - 12: 7ff67613 and a2,a2,2047 - -00000016 <.LBE2>: - 16: 3fe00593 li a1,1022 - 1a: 04c5df63 bge a1,a2,78 <.L6> - 1e: efa9 bnez a5,78 <.L6> - 20: 43e00793 li a5,1086 - -00000024 <.LVL4>: - 24: 04c7cc63 blt a5,a2,7c <.L8> - -00000028 <.LBB3>: - 28: 43200793 li a5,1074 - 2c: 00d765b3 or a1,a4,a3 - -00000030 <.LVL6>: - 30: 00c7dd63 bge a5,a2,4a <.L3> - -00000034 <.LBE3>: - 34: 1151 add sp,sp,-12 - -00000036 <.LBB7>: - 36: bcd60613 add a2,a2,-1075 - -0000003a <.LBE7>: - 3a: c406 sw ra,8(sp) - -0000003c <.LBB8>: - 3c: 00000097 auipc ra,0x0 - 40: 000080e7 jalr ra # 3c <.LBB8> - -00000044 <.LBE8>: - 44: 40a2 lw ra,8(sp) - 46: 0131 add sp,sp,12 - 48: 8082 ret - -0000004a <.L3>: - 4a: 43300713 li a4,1075 - 4e: 8f11 sub a4,a4,a2 - 50: 47fd li a5,31 - 52: 00e7cc63 blt a5,a4,6a <.L4> - -00000056 <.LVL11>: - 56: bed60793 add a5,a2,-1043 - 5a: 00f597b3 sll a5,a1,a5 - 5e: 00e55533 srl a0,a0,a4 - -00000062 <.LVL12>: - 62: 8d5d or a0,a0,a5 - -00000064 <.LVL13>: - 64: 00e5d5b3 srl a1,a1,a4 - 68: 8082 ret - -0000006a <.L4>: - 6a: 41300513 li a0,1043 - -0000006e <.LVL16>: - 6e: 8d11 sub a0,a0,a2 - 70: 00a5d533 srl a0,a1,a0 - -00000074 <.L13>: - 74: 4581 li a1,0 - 76: 8082 ret - -00000078 <.L6>: - 78: 4501 li a0,0 - -0000007a <.LVL19>: - 7a: bfed j 74 <.L13> - -0000007c <.L8>: - 7c: 557d li a0,-1 - -0000007e <.LVL21>: - 7e: 55fd li a1,-1 - -00000080 <.LVL22>: - 80: 8082 ret - -floatdidf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatdidf>: - 0: 1101 add sp,sp,-32 - 2: ce06 sw ra,28(sp) - 4: cc22 sw s0,24(sp) - 6: ca26 sw s1,20(sp) - -00000008 <.LBB17>: - 8: 00b567b3 or a5,a0,a1 - c: 16078363 beqz a5,172 <.L17> - -00000010 <.LBB3>: - 10: 01f5d793 srl a5,a1,0x1f - 14: c03e sw a5,0(sp) - 16: 842a mv s0,a0 - 18: 832e mv t1,a1 - -0000001a <.LVL1>: - 1a: 0005da63 bgez a1,2e <.L4> - -0000001e <.LVL2>: - 1e: 00a037b3 snez a5,a0 - -00000022 <.LVL3>: - 22: 40b006b3 neg a3,a1 - 26: 40f68333 sub t1,a3,a5 - 2a: 40a00433 neg s0,a0 - -0000002e <.L4>: - 2e: c21a sw t1,4(sp) - 30: 849a mv s1,t1 - 32: 02030663 beqz t1,5e <.L6> - 36: 851a mv a0,t1 - -00000038 <.LVL5>: - 38: 00000097 auipc ra,0x0 - 3c: 000080e7 jalr ra # 38 <.LVL5> - -00000040 <.LVL6>: - 40: 43e00713 li a4,1086 - 44: 8f09 sub a4,a4,a0 - -00000046 <.LBE4>: - 46: 43300613 li a2,1075 - -0000004a <.LBB5>: - 4a: 86aa mv a3,a0 - -0000004c <.LBE5>: - 4c: 8326 mv t1,s1 - 4e: 06e64963 blt a2,a4,c0 <.L25> - 52: 45ad li a1,11 - 54: 8622 mv a2,s0 - -00000056 <.LVL8>: - 56: 12b50363 beq a0,a1,17c <.L18> - 5a: 1555 add a0,a0,-11 - -0000005c <.LVL9>: - 5c: a00d j 7e <.L10> - -0000005e <.L6>: - 5e: 8522 mv a0,s0 - -00000060 <.LVL11>: - 60: 00000097 auipc ra,0x0 - 64: 000080e7 jalr ra # 60 <.LVL11> - -00000068 <.LVL12>: - 68: 02050693 add a3,a0,32 - -0000006c <.LVL13>: - 6c: 43e00713 li a4,1086 - -00000070 <.LBE6>: - 70: 02a00793 li a5,42 - 74: 4312 lw t1,4(sp) - -00000076 <.LBB7>: - 76: 8f15 sub a4,a4,a3 - -00000078 <.LBE7>: - 78: 02d7cf63 blt a5,a3,b6 <.L9> - 7c: 0555 add a0,a0,21 - -0000007e <.L10>: - 7e: 02b00593 li a1,43 - 82: 8d95 sub a1,a1,a3 - 84: 00b455b3 srl a1,s0,a1 - 88: 00a316b3 sll a3,t1,a0 - -0000008c <.LVL16>: - 8c: 00d5e4b3 or s1,a1,a3 - -00000090 <.LVL17>: - 90: 00a41633 sll a2,s0,a0 - -00000094 <.L2>: - 94: 4782 lw a5,0(sp) - 96: 00c49593 sll a1,s1,0xc - -0000009a <.LBE18>: - 9a: 40f2 lw ra,28(sp) - 9c: 4462 lw s0,24(sp) - -0000009e <.LBB19>: - 9e: 81b1 srl a1,a1,0xc - a0: 0752 sll a4,a4,0x14 - -000000a2 <.LVL19>: - a2: 8f4d or a4,a4,a1 - a4: 01f79493 sll s1,a5,0x1f - -000000a8 <.LVL20>: - a8: 009767b3 or a5,a4,s1 - -000000ac <.LBE19>: - ac: 8532 mv a0,a2 - ae: 44d2 lw s1,20(sp) - b0: 85be mv a1,a5 - b2: 6105 add sp,sp,32 - -000000b4 <.LVL22>: - b4: 8082 ret - -000000b6 <.L9>: - b6: 1555 add a0,a0,-11 - -000000b8 <.LVL24>: - b8: 4601 li a2,0 - ba: 00a414b3 sll s1,s0,a0 - -000000be <.LVL25>: - be: bfd9 j 94 <.L2> - -000000c0 <.L25>: - c0: 43600613 li a2,1078 - c4: 08e65763 bge a2,a4,152 <.L11> - c8: 4621 li a2,8 - ca: 8e09 sub a2,a2,a0 - cc: c22a sw a0,4(sp) - ce: 85a6 mv a1,s1 - d0: 8522 mv a0,s0 - -000000d2 <.LVL27>: - d2: c83a sw a4,16(sp) - d4: 00000097 auipc ra,0x0 - d8: 000080e7 jalr ra # d4 <.LVL27+0x2> - -000000dc <.LVL28>: - dc: 4692 lw a3,4(sp) - de: c62a sw a0,12(sp) - e0: c42e sw a1,8(sp) - e2: 03868613 add a2,a3,56 - e6: 8522 mv a0,s0 - e8: 85a6 mv a1,s1 - ea: 00000097 auipc ra,0x0 - ee: 000080e7 jalr ra # ea <.LVL28+0xe> - -000000f2 <.LVL29>: - f2: 42b2 lw t0,12(sp) - f4: 4322 lw t1,8(sp) - f6: 00b56433 or s0,a0,a1 - fa: 4692 lw a3,4(sp) - fc: 4742 lw a4,16(sp) - fe: 00803433 snez s0,s0 - 102: 00546433 or s0,s0,t0 - -00000106 <.LVL30>: - 106: 849a mv s1,t1 - -00000108 <.L12>: - 108: ff800637 lui a2,0xff800 - 10c: 167d add a2,a2,-1 # ff7fffff <.LLST11+0xff7ffcfb> - 10e: 00c4f7b3 and a5,s1,a2 - -00000112 <.LBB10>: - 112: 00747613 and a2,s0,7 - 116: ce01 beqz a2,12e <.L13> - -00000118 <.LVL33>: - 118: 00f47613 and a2,s0,15 - 11c: 4591 li a1,4 - 11e: 00b60863 beq a2,a1,12e <.L13> - -00000122 <.LBB11>: - 122: 00440613 add a2,s0,4 - 126: 008635b3 sltu a1,a2,s0 - 12a: 97ae add a5,a5,a1 - -0000012c <.LVL34>: - 12c: 8432 mv s0,a2 - -0000012e <.L13>: - 12e: 00800637 lui a2,0x800 - 132: 8e7d and a2,a2,a5 - 134: ca01 beqz a2,144 <.L16> - 136: ff800737 lui a4,0xff800 - -0000013a <.LVL36>: - 13a: 177d add a4,a4,-1 # ff7fffff <.LLST11+0xff7ffcfb> - 13c: 8ff9 and a5,a5,a4 - 13e: 43f00713 li a4,1087 - 142: 8f15 sub a4,a4,a3 - -00000144 <.L16>: - 144: 800d srl s0,s0,0x3 - -00000146 <.LVL39>: - 146: 01d79613 sll a2,a5,0x1d - 14a: 8e41 or a2,a2,s0 - -0000014c <.LVL40>: - 14c: 0037d493 srl s1,a5,0x3 - -00000150 <.LVL41>: - 150: b791 j 94 <.L2> - -00000152 <.L11>: - 152: 4621 li a2,8 - 154: 1561 add a0,a0,-8 - -00000156 <.LVL43>: - 156: fac689e3 beq a3,a2,108 <.L12> - 15a: 02800613 li a2,40 - 15e: 8e15 sub a2,a2,a3 - 160: 00c45633 srl a2,s0,a2 - 164: 00a495b3 sll a1,s1,a0 - 168: 00b664b3 or s1,a2,a1 - -0000016c <.LVL44>: - 16c: 00a41433 sll s0,s0,a0 - 170: bf61 j 108 <.L12> - -00000172 <.L17>: - 172: 4481 li s1,0 - 174: 4601 li a2,0 - 176: 4701 li a4,0 - 178: c002 sw zero,0(sp) - 17a: bf29 j 94 <.L2> - -0000017c <.L18>: - 17c: 43300713 li a4,1075 - -00000180 <.LVL48>: - 180: bf11 j 94 <.L2> - -floatundidf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatundidf>: - 0: 1121 add sp,sp,-24 - 2: ca06 sw ra,20(sp) - 4: c822 sw s0,16(sp) - 6: c626 sw s1,12(sp) - -00000008 <.LBB18>: - 8: 00b567b3 or a5,a0,a1 - c: 12078b63 beqz a5,142 <.L15> - -00000010 <.LBB3>: - 10: c22e sw a1,4(sp) - 12: c02a sw a0,0(sp) - 14: 842e mv s0,a1 - 16: c595 beqz a1,42 <.L4> - 18: 852e mv a0,a1 - -0000001a <.LVL2>: - 1a: 00000097 auipc ra,0x0 - 1e: 000080e7 jalr ra # 1a <.LVL2> - -00000022 <.LVL3>: - 22: 43e00493 li s1,1086 - 26: 8c89 sub s1,s1,a0 - -00000028 <.LBE4>: - 28: 43300793 li a5,1075 - 2c: 4682 lw a3,0(sp) - -0000002e <.LBB5>: - 2e: 872a mv a4,a0 - -00000030 <.LBE5>: - 30: 85a2 mv a1,s0 - 32: 0697c363 blt a5,s1,98 <.L23> - 36: 462d li a2,11 - 38: 87b6 mv a5,a3 - -0000003a <.LVL5>: - 3a: 10c50863 beq a0,a2,14a <.L16> - 3e: 1555 add a0,a0,-11 - -00000040 <.LVL6>: - 40: a00d j 62 <.L8> - -00000042 <.L4>: - 42: 00000097 auipc ra,0x0 - 46: 000080e7 jalr ra # 42 <.L4> - -0000004a <.LVL8>: - 4a: 02050713 add a4,a0,32 - -0000004e <.LVL9>: - 4e: 43e00493 li s1,1086 - -00000052 <.LBE6>: - 52: 02a00793 li a5,42 - 56: 4682 lw a3,0(sp) - 58: 4592 lw a1,4(sp) - -0000005a <.LBB7>: - 5a: 8c99 sub s1,s1,a4 - -0000005c <.LBE7>: - 5c: 02e7c963 blt a5,a4,8e <.L7> - 60: 0555 add a0,a0,21 - -00000062 <.L8>: - 62: 02b00413 li s0,43 - -00000066 <.LVL12>: - 66: 8c19 sub s0,s0,a4 - 68: 0086d433 srl s0,a3,s0 - 6c: 00a595b3 sll a1,a1,a0 - 70: 8c4d or s0,s0,a1 - -00000072 <.LVL13>: - 72: 00a697b3 sll a5,a3,a0 - -00000076 <.L2>: - 76: 0432 sll s0,s0,0xc - -00000078 <.LVL15>: - 78: 04d2 sll s1,s1,0x14 - -0000007a <.LVL16>: - 7a: 8031 srl s0,s0,0xc - 7c: 0084e733 or a4,s1,s0 - -00000080 <.LBE19>: - 80: 40d2 lw ra,20(sp) - 82: 4442 lw s0,16(sp) - 84: 44b2 lw s1,12(sp) - 86: 853e mv a0,a5 - 88: 85ba mv a1,a4 - 8a: 0161 add sp,sp,24 - 8c: 8082 ret - -0000008e <.L7>: - 8e: 1555 add a0,a0,-11 - -00000090 <.LVL19>: - 90: 4781 li a5,0 - 92: 00a69433 sll s0,a3,a0 - -00000096 <.LVL20>: - 96: b7c5 j 76 <.L2> - -00000098 <.L23>: - 98: 43600793 li a5,1078 - 9c: 0897d263 bge a5,s1,120 <.L9> - a0: 03850613 add a2,a0,56 - a4: c02a sw a0,0(sp) - a6: 8536 mv a0,a3 - -000000a8 <.LVL22>: - a8: c436 sw a3,8(sp) - aa: 00000097 auipc ra,0x0 - ae: 000080e7 jalr ra # aa <.LVL22+0x2> - -000000b2 <.LVL23>: - b2: 4702 lw a4,0(sp) - b4: 46a2 lw a3,8(sp) - b6: 00b567b3 or a5,a0,a1 - ba: 4621 li a2,8 - bc: 00f037b3 snez a5,a5 - c0: 8e19 sub a2,a2,a4 - c2: 85a2 mv a1,s0 - c4: 8536 mv a0,a3 - c6: c23e sw a5,4(sp) - c8: 00000097 auipc ra,0x0 - cc: 000080e7 jalr ra # c8 <.LVL23+0x16> - -000000d0 <.LVL24>: - d0: 4792 lw a5,4(sp) - d2: 4702 lw a4,0(sp) - d4: 842e mv s0,a1 - -000000d6 <.LVL25>: - d6: 8fc9 or a5,a5,a0 - -000000d8 <.L10>: - d8: ff8006b7 lui a3,0xff800 - dc: 16fd add a3,a3,-1 # ff7fffff <.LLST12+0xff7ffc30> - -000000de <.LBB10>: - de: 0077f613 and a2,a5,7 - -000000e2 <.LBE10>: - e2: 8ee1 and a3,a3,s0 - -000000e4 <.LBB13>: - e4: ce01 beqz a2,fc <.L11> - -000000e6 <.LVL28>: - e6: 00f7f613 and a2,a5,15 - ea: 4591 li a1,4 - ec: 00b60863 beq a2,a1,fc <.L11> - -000000f0 <.LBB11>: - f0: 00478613 add a2,a5,4 - f4: 00f635b3 sltu a1,a2,a5 - f8: 96ae add a3,a3,a1 - -000000fa <.LVL29>: - fa: 87b2 mv a5,a2 - -000000fc <.L11>: - fc: 00800637 lui a2,0x800 - 100: 8e75 and a2,a2,a3 - 102: ca01 beqz a2,112 <.L14> - 104: ff800637 lui a2,0xff800 - 108: 167d add a2,a2,-1 # ff7fffff <.LLST12+0xff7ffc30> - 10a: 43f00493 li s1,1087 - -0000010e <.LVL31>: - 10e: 8ef1 and a3,a3,a2 - 110: 8c99 sub s1,s1,a4 - -00000112 <.L14>: - 112: 838d srl a5,a5,0x3 - -00000114 <.LVL34>: - 114: 01d69713 sll a4,a3,0x1d - -00000118 <.LVL35>: - 118: 8fd9 or a5,a5,a4 - -0000011a <.LVL36>: - 11a: 0036d413 srl s0,a3,0x3 - -0000011e <.LVL37>: - 11e: bfa1 j 76 <.L2> - -00000120 <.L9>: - 120: 87b6 mv a5,a3 - -00000122 <.LVL39>: - 122: 46a1 li a3,8 - -00000124 <.LVL40>: - 124: ff850613 add a2,a0,-8 - 128: fad508e3 beq a0,a3,d8 <.L10> - -0000012c <.LVL41>: - 12c: 02800693 li a3,40 - 130: 8e89 sub a3,a3,a0 - 132: 00d7d6b3 srl a3,a5,a3 - 136: 00c41433 sll s0,s0,a2 - -0000013a <.LVL42>: - 13a: 8c55 or s0,s0,a3 - -0000013c <.LVL43>: - 13c: 00c797b3 sll a5,a5,a2 - -00000140 <.LVL44>: - 140: bf61 j d8 <.L10> - -00000142 <.L15>: - 142: 4401 li s0,0 - 144: 4781 li a5,0 - 146: 4481 li s1,0 - 148: b73d j 76 <.L2> - -0000014a <.L16>: - 14a: 43300493 li s1,1075 - -0000014e <.LVL47>: - 14e: b725 j 76 <.L2> - -addtf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__addtf3>: - 0: 7119 add sp,sp,-128 - 2: 45dc lw a5,12(a1) - 4: 4598 lw a4,8(a1) - 6: 00062283 lw t0,0(a2) - a: 00462303 lw t1,4(a2) - e: 4654 lw a3,12(a2) - 10: cc2a sw a0,24(sp) - 12: 4608 lw a0,8(a2) - 14: 06710613 add a2,sp,103 - 18: 9a41 and a2,a2,-16 - 1a: dca2 sw s0,120(sp) - 1c: de86 sw ra,124(sp) - 1e: daa6 sw s1,116(sp) - 20: 0045a383 lw t2,4(a1) - 24: 4180 lw s0,0(a1) - -00000026 <.LBB3>: - 26: c618 sw a4,8(a2) - 28: d83a sw a4,48(sp) - 2a: 01079713 sll a4,a5,0x10 - 2e: 8341 srl a4,a4,0x10 - 30: da3a sw a4,52(sp) - 32: 00179713 sll a4,a5,0x1 - 36: 00762223 sw t2,4(a2) - 3a: c65c sw a5,12(a2) - -0000003c <.LBE3>: - 3c: c432 sw a2,8(sp) - -0000003e <.LBB4>: - 3e: 83fd srl a5,a5,0x1f - 40: c200 sw s0,0(a2) - 42: 8345 srl a4,a4,0x11 - 44: 1030 add a2,sp,40 - 46: d61e sw t2,44(sp) - 48: c63e sw a5,12(sp) - 4a: d422 sw s0,40(sp) - 4c: c23a sw a4,4(sp) - -0000004e <.LBB5>: - 4e: 01c10393 add t2,sp,28 - -00000052 <.LBB6>: - 52: 87b2 mv a5,a2 - -00000054 <.L2>: - 54: 47d8 lw a4,12(a5) - 56: 478c lw a1,8(a5) - 58: 17f1 add a5,a5,-4 - 5a: 070e sll a4,a4,0x3 - 5c: 81f5 srl a1,a1,0x1d - 5e: 8f4d or a4,a4,a1 - 60: cb98 sw a4,16(a5) - 62: fef399e3 bne t2,a5,54 <.L2> - -00000066 <.LBB8>: - 66: 4722 lw a4,8(sp) - -00000068 <.LBB9>: - 68: 57a2 lw a5,40(sp) - -0000006a <.LBB10>: - 6a: de1a sw t1,60(sp) - 6c: 00672223 sw t1,4(a4) - 70: c754 sw a3,12(a4) - 72: 00572023 sw t0,0(a4) - 76: c708 sw a0,8(a4) - 78: 01069713 sll a4,a3,0x10 - 7c: 8341 srl a4,a4,0x10 - 7e: c2ba sw a4,68(sp) - 80: 00169713 sll a4,a3,0x1 - 84: 8345 srl a4,a4,0x11 - 86: c83a sw a4,16(sp) - 88: 01f6d713 srl a4,a3,0x1f - -0000008c <.LBB11>: - 8c: 078e sll a5,a5,0x3 - -0000008e <.LBB12>: - 8e: ca3a sw a4,20(sp) - 90: 1838 add a4,sp,56 - -00000092 <.LBB13>: - 92: d43e sw a5,40(sp) - -00000094 <.LBB14>: - 94: dc16 sw t0,56(sp) - 96: c0aa sw a0,64(sp) - -00000098 <.LBB15>: - 98: 02c10313 add t1,sp,44 - -0000009c <.LBB16>: - 9c: 86ba mv a3,a4 - -0000009e <.L3>: - 9e: 46cc lw a1,12(a3) - a0: 4688 lw a0,8(a3) - a2: 16f1 add a3,a3,-4 - a4: 058e sll a1,a1,0x3 - a6: 8175 srl a0,a0,0x1d - a8: 8dc9 or a1,a1,a0 - aa: ca8c sw a1,16(a3) - ac: fed319e3 bne t1,a3,9e <.L3> - -000000b0 <.LVL7>: - b0: 56e2 lw a3,56(sp) - -000000b2 <.LBB18>: - b2: 45c2 lw a1,16(sp) - -000000b4 <.LBB53>: - b4: 00369493 sll s1,a3,0x3 - -000000b8 <.LBB54>: - b8: 4692 lw a3,4(sp) - -000000ba <.LBB55>: - ba: dc26 sw s1,56(sp) - -000000bc <.LBB56>: - bc: 40b68533 sub a0,a3,a1 - -000000c0 <.LBE56>: - c0: 46b2 lw a3,12(sp) - c2: 45d2 lw a1,20(sp) - c4: 5eb69b63 bne a3,a1,6ba <.L4> - -000000c8 <.LBB57>: - c8: 2ea05463 blez a0,3b0 <.L5> - -000000cc <.LVL9>: - cc: 56d2 lw a3,52(sp) - -000000ce <.LVL10>: - ce: 52b2 lw t0,44(sp) - d0: 53c2 lw t2,48(sp) - d2: c036 sw a3,0(sp) - d4: 46c2 lw a3,16(sp) - d6: e6bd bnez a3,144 <.L6> - d8: 55f2 lw a1,60(sp) - da: 4606 lw a2,64(sp) - dc: 4316 lw t1,68(sp) - de: 00c5e6b3 or a3,a1,a2 - e2: 0066e6b3 or a3,a3,t1 - e6: 8ec5 or a3,a3,s1 - e8: e299 bnez a3,ee <.L7> - -000000ea <.L362>: - ea: c4be sw a5,72(sp) - ec: a4fd j 3da <.L363> - -000000ee <.L7>: - ee: fff50693 add a3,a0,-1 - -000000f2 <.LVL13>: - f2: ee8d bnez a3,12c <.L9> - -000000f4 <.LBB19>: - f4: 00978733 add a4,a5,s1 - f8: 005586b3 add a3,a1,t0 - -000000fc <.LVL14>: - fc: c4ba sw a4,72(sp) - -000000fe <.LVL15>: - fe: 00f73733 sltu a4,a4,a5 - -00000102 <.LVL16>: - 102: 9736 add a4,a4,a3 - -00000104 <.LVL17>: - 104: c6ba sw a4,76(sp) - -00000106 <.LVL18>: - 106: 00b6b5b3 sltu a1,a3,a1 - -0000010a <.LVL19>: - 10a: 00d73733 sltu a4,a4,a3 - -0000010e <.LVL20>: - 10e: 007607b3 add a5,a2,t2 - -00000112 <.LVL21>: - 112: 8dd9 or a1,a1,a4 - -00000114 <.LVL22>: - 114: 95be add a1,a1,a5 - 116: c8ae sw a1,80(sp) - -00000118 <.LVL23>: - 118: 00c7b733 sltu a4,a5,a2 - -0000011c <.L351>: - 11c: 00f5b5b3 sltu a1,a1,a5 - 120: 4782 lw a5,0(sp) - 122: 8f4d or a4,a4,a1 - -00000124 <.LBB111>: - 124: 4505 li a0,1 - -00000126 <.LBB112>: - 126: 933e add t1,t1,a5 - 128: 971a add a4,a4,t1 - -0000012a <.LBE21>: - 12a: a411 j 32e <.L20> - -0000012c <.L9>: - 12c: 6621 lui a2,0x8 - 12e: 167d add a2,a2,-1 # 7fff <.LLST158+0x5687> - 130: 5ec51ce3 bne a0,a2,f28 <.L21> - -00000134 <.L361>: - 134: c4be sw a5,72(sp) - 136: a4e5 j 41e <.L356> - -00000138 <.L266>: - 138: 87a6 mv a5,s1 - 13a: bfed j 134 <.L361> - -0000013c <.L267>: - 13c: 82ba mv t0,a4 - 13e: 83b6 mv t2,a3 - 140: c032 sw a2,0(sp) - -00000142 <.LVL28>: - 142: bfcd j 134 <.L361> - -00000144 <.L6>: - 144: 4612 lw a2,4(sp) - 146: 66a1 lui a3,0x8 - 148: 16fd add a3,a3,-1 # 7fff <.LLST158+0x5687> - 14a: 0cd61e63 bne a2,a3,226 <.L22> - -0000014e <.LVL30>: - 14e: c4be sw a5,72(sp) - 150: 4782 lw a5,0(sp) - 152: c696 sw t0,76(sp) - 154: c89e sw t2,80(sp) - 156: cabe sw a5,84(sp) - -00000158 <.LBB115>: - 158: 8532 mv a0,a2 - -0000015a <.L8>: - 15a: 47a6 lw a5,72(sp) - 15c: 0077f713 and a4,a5,7 - 160: c71d beqz a4,18e <.L252> - 162: 00f7f713 and a4,a5,15 - 166: 4691 li a3,4 - 168: 02d70363 beq a4,a3,18e <.L252> - -0000016c <.LBB117>: - 16c: 4736 lw a4,76(sp) - 16e: 0791 add a5,a5,4 - 170: c4be sw a5,72(sp) - -00000172 <.LVL33>: - 172: 0047b793 sltiu a5,a5,4 - -00000176 <.LVL34>: - 176: 97ba add a5,a5,a4 - 178: c6be sw a5,76(sp) - -0000017a <.LVL35>: - 17a: 00e7b7b3 sltu a5,a5,a4 - -0000017e <.LVL36>: - 17e: 4746 lw a4,80(sp) - 180: 97ba add a5,a5,a4 - -00000182 <.LVL37>: - 182: c8be sw a5,80(sp) - -00000184 <.LVL38>: - 184: 00e7b7b3 sltu a5,a5,a4 - -00000188 <.LVL39>: - 188: 4756 lw a4,84(sp) - 18a: 97ba add a5,a5,a4 - -0000018c <.LVL40>: - 18c: cabe sw a5,84(sp) - -0000018e <.L252>: - 18e: 47d6 lw a5,84(sp) - 190: 00080737 lui a4,0x80 - 194: 8f7d and a4,a4,a5 - 196: cb19 beqz a4,1ac <.L257> - 198: 6721 lui a4,0x8 - 19a: 0505 add a0,a0,1 - -0000019c <.LVL42>: - 19c: 177d add a4,a4,-1 # 7fff <.LLST158+0x5687> - 19e: 56e50fe3 beq a0,a4,f1c <.L258> - 1a2: fff80737 lui a4,0xfff80 - 1a6: 177d add a4,a4,-1 # fff7ffff <.LLST158+0xfff7d687> - 1a8: 8ff9 and a5,a5,a4 - 1aa: cabe sw a5,84(sp) - -000001ac <.L257>: - 1ac: 00bc add a5,sp,72 - 1ae: 08d0 add a2,sp,84 - -000001b0 <.L260>: - 1b0: 4398 lw a4,0(a5) - 1b2: 43d4 lw a3,4(a5) - 1b4: 830d srl a4,a4,0x3 - 1b6: 06f6 sll a3,a3,0x1d - 1b8: 8f55 or a4,a4,a3 - 1ba: c398 sw a4,0(a5) - 1bc: 0791 add a5,a5,4 - 1be: fec799e3 bne a5,a2,1b0 <.L260> - -000001c2 <.LVL45>: - 1c2: 4756 lw a4,84(sp) - -000001c4 <.LBE118>: - 1c4: 66a1 lui a3,0x8 - 1c6: fff68793 add a5,a3,-1 # 7fff <.LLST158+0x5687> - -000001ca <.LBB119>: - 1ca: 830d srl a4,a4,0x3 - 1cc: caba sw a4,84(sp) - -000001ce <.LBE119>: - 1ce: 00f51e63 bne a0,a5,1ea <.L261> - 1d2: 4636 lw a2,76(sp) - 1d4: 47a6 lw a5,72(sp) - 1d6: 8fd1 or a5,a5,a2 - 1d8: 4646 lw a2,80(sp) - 1da: 8fd1 or a5,a5,a2 - 1dc: 8fd9 or a5,a5,a4 - 1de: c791 beqz a5,1ea <.L261> - 1e0: cab6 sw a3,84(sp) - 1e2: c882 sw zero,80(sp) - 1e4: c682 sw zero,76(sp) - 1e6: c482 sw zero,72(sp) - -000001e8 <.LVL46>: - 1e8: c602 sw zero,12(sp) - -000001ea <.L261>: - 1ea: 47a2 lw a5,8(sp) - 1ec: 4626 lw a2,72(sp) - 1ee: 46b6 lw a3,76(sp) - 1f0: 4746 lw a4,80(sp) - 1f2: 45a2 lw a1,8(sp) - 1f4: c390 sw a2,0(a5) - 1f6: c3d4 sw a3,4(a5) - 1f8: c798 sw a4,8(a5) - 1fa: 47d6 lw a5,84(sp) - 1fc: 0546 sll a0,a0,0x11 - -000001fe <.LVL48>: - 1fe: 8145 srl a0,a0,0x11 - 200: 00f59623 sh a5,12(a1) - 204: 47b2 lw a5,12(sp) - -00000206 <.LBE122>: - 206: 50f6 lw ra,124(sp) - 208: 5466 lw s0,120(sp) - -0000020a <.LBB123>: - 20a: 07be sll a5,a5,0xf - 20c: 8fc9 or a5,a5,a0 - 20e: 00f59723 sh a5,14(a1) - 212: 45dc lw a5,12(a1) - -00000214 <.LBE123>: - 214: 45e2 lw a1,24(sp) - 216: 54d6 lw s1,116(sp) - 218: c190 sw a2,0(a1) - 21a: c1d4 sw a3,4(a1) - 21c: c598 sw a4,8(a1) - 21e: c5dc sw a5,12(a1) - 220: 852e mv a0,a1 - 222: 6109 add sp,sp,128 - -00000224 <.LVL50>: - 224: 8082 ret - -00000226 <.L22>: - 226: 4696 lw a3,68(sp) - 228: 00080637 lui a2,0x80 - 22c: 8ed1 or a3,a3,a2 - 22e: c2b6 sw a3,68(sp) - -00000230 <.LDL1>: - 230: 07400693 li a3,116 - 234: 4ea6cee3 blt a3,a0,f30 <.L23> - 238: 86aa mv a3,a0 - -0000023a <.L262>: - 23a: 4056d513 sra a0,a3,0x5 - -0000023e <.LVL53>: - 23e: 85ba mv a1,a4 - 240: 8afd and a3,a3,31 - -00000242 <.LVL54>: - 242: 4481 li s1,0 - 244: 4601 li a2,0 - -00000246 <.L24>: - 246: 02a61463 bne a2,a0,26e <.L25> - 24a: 460d li a2,3 - -0000024c <.LVL56>: - 24c: 8e09 sub a2,a2,a0 - 24e: 00251593 sll a1,a0,0x2 - 252: e68d bnez a3,27c <.L26> - -00000254 <.L27>: - 254: 00b70333 add t1,a4,a1 - 258: 00032303 lw t1,0(t1) - 25c: 0685 add a3,a3,1 - -0000025e <.LVL58>: - 25e: 00672023 sw t1,0(a4) - -00000262 <.LVL59>: - 262: 0711 add a4,a4,4 - 264: fed658e3 bge a2,a3,254 <.L27> - 268: 4711 li a4,4 - 26a: 8f09 sub a4,a4,a0 - 26c: a899 j 2c2 <.L31> - -0000026e <.L25>: - 26e: 0005a303 lw t1,0(a1) - 272: 0605 add a2,a2,1 # 80001 <.LLST158+0x7d689> - -00000274 <.LVL61>: - 274: 0591 add a1,a1,4 - 276: 0064e4b3 or s1,s1,t1 - -0000027a <.LVL62>: - 27a: b7f1 j 246 <.L24> - -0000027c <.L26>: - 27c: 02000313 li t1,32 - 280: 40d30433 sub s0,t1,a3 - 284: ca22 sw s0,20(sp) - -00000286 <.LVL64>: - 286: 02810313 add t1,sp,40 - 28a: 04c58413 add s0,a1,76 - 28e: 9322 add t1,t1,s0 - 290: fc432303 lw t1,-60(t1) - 294: 4452 lw s0,20(sp) - 296: c802 sw zero,16(sp) - -00000298 <.LVL65>: - 298: 00831333 sll t1,t1,s0 - 29c: 1820 add s0,sp,56 - 29e: 0064e4b3 or s1,s1,t1 - -000002a2 <.LVL66>: - 2a2: 95a2 add a1,a1,s0 - -000002a4 <.L29>: - 2a4: 4442 lw s0,16(sp) - 2a6: 0cc44f63 blt s0,a2,384 <.L30> - 2aa: 060a sll a2,a2,0x2 - 2ac: 102c add a1,sp,40 - 2ae: 04c60613 add a2,a2,76 - 2b2: 962e add a2,a2,a1 - 2b4: 4596 lw a1,68(sp) - 2b6: 4711 li a4,4 - 2b8: 8f09 sub a4,a4,a0 - -000002ba <.LVL68>: - 2ba: 00d5d5b3 srl a1,a1,a3 - 2be: fcb62223 sw a1,-60(a2) - -000002c2 <.L31>: - 2c2: 4691 li a3,4 - 2c4: 8e99 sub a3,a3,a4 - 2c6: 1830 add a2,sp,56 - 2c8: 070a sll a4,a4,0x2 - 2ca: 9732 add a4,a4,a2 - 2cc: 068a sll a3,a3,0x2 - 2ce: 4621 li a2,8 - 2d0: 00c6e863 bltu a3,a2,2e0 <.L32> - 2d4: 00072023 sw zero,0(a4) - -000002d8 <.LVL70>: - 2d8: 00072223 sw zero,4(a4) - 2dc: 16e1 add a3,a3,-8 - 2de: 0721 add a4,a4,8 - -000002e0 <.L32>: - 2e0: 4611 li a2,4 - 2e2: 00c6e463 bltu a3,a2,2ea <.L33> - 2e6: 00072023 sw zero,0(a4) - -000002ea <.L33>: - 2ea: 5762 lw a4,56(sp) - -000002ec <.LBB24>: - 2ec: 009034b3 snez s1,s1 - -000002f0 <.LBE24>: - 2f0: 8cd9 or s1,s1,a4 - -000002f2 <.L34>: - 2f2: 56f2 lw a3,60(sp) - -000002f4 <.LBB26>: - 2f4: dc26 sw s1,56(sp) - -000002f6 <.LBB27>: - 2f6: 94be add s1,s1,a5 - 2f8: 00568633 add a2,a3,t0 - 2fc: 4706 lw a4,64(sp) - 2fe: c4a6 sw s1,72(sp) - -00000300 <.LVL74>: - 300: 00f4b4b3 sltu s1,s1,a5 - -00000304 <.LVL75>: - 304: 94b2 add s1,s1,a2 - -00000306 <.LVL76>: - 306: c6a6 sw s1,76(sp) - -00000308 <.LVL77>: - 308: 00d636b3 sltu a3,a2,a3 - -0000030c <.LVL78>: - 30c: 00c4b4b3 sltu s1,s1,a2 - -00000310 <.LVL79>: - 310: 007707b3 add a5,a4,t2 - -00000314 <.LVL80>: - 314: 8ec5 or a3,a3,s1 - -00000316 <.LVL81>: - 316: 96be add a3,a3,a5 - 318: 00e7b733 sltu a4,a5,a4 - -0000031c <.LVL82>: - 31c: c8b6 sw a3,80(sp) - -0000031e <.LVL83>: - 31e: 00f6b6b3 sltu a3,a3,a5 - -00000322 <.LVL84>: - 322: 8f55 or a4,a4,a3 - -00000324 <.LVL85>: - 324: 4796 lw a5,68(sp) - -00000326 <.LVL86>: - 326: 4682 lw a3,0(sp) - -00000328 <.LBB125>: - 328: 4512 lw a0,4(sp) - -0000032a <.LBB126>: - 32a: 97b6 add a5,a5,a3 - 32c: 973e add a4,a4,a5 - -0000032e <.L20>: - 32e: 000807b7 lui a5,0x80 - -00000332 <.LBB29>: - 332: caba sw a4,84(sp) - -00000334 <.LBE29>: - 334: 8ff9 and a5,a5,a4 - 336: e20782e3 beqz a5,15a <.L8> - 33a: fff807b7 lui a5,0xfff80 - 33e: 17fd add a5,a5,-1 # fff7ffff <.LLST158+0xfff7d687> - 340: 8f7d and a4,a4,a5 - 342: caba sw a4,84(sp) - -00000344 <.LBB30>: - 344: 4726 lw a4,72(sp) - -00000346 <.LBE30>: - 346: 0505 add a0,a0,1 - -00000348 <.LBB32>: - 348: 08cc add a1,sp,84 - 34a: 01f71693 sll a3,a4,0x1f - -0000034e <.LVL91>: - 34e: 00b8 add a4,sp,72 - -00000350 <.L117>: - 350: 431c lw a5,0(a4) - 352: 4350 lw a2,4(a4) - 354: 8385 srl a5,a5,0x1 - 356: 067e sll a2,a2,0x1f - 358: 8fd1 or a5,a5,a2 - 35a: c31c sw a5,0(a4) - 35c: 0711 add a4,a4,4 - 35e: fee599e3 bne a1,a4,350 <.L117> - -00000362 <.LVL93>: - 362: 47d6 lw a5,84(sp) - 364: 00d03733 snez a4,a3 - 368: 8385 srl a5,a5,0x1 - 36a: cabe sw a5,84(sp) - -0000036c <.LBE32>: - 36c: 47a6 lw a5,72(sp) - 36e: 8fd9 or a5,a5,a4 - 370: c4be sw a5,72(sp) - -00000372 <.LBE33>: - 372: 67a1 lui a5,0x8 - 374: 17fd add a5,a5,-1 # 7fff <.LLST158+0x5687> - 376: def512e3 bne a0,a5,15a <.L8> - -0000037a <.LVL95>: - 37a: ca82 sw zero,84(sp) - 37c: c882 sw zero,80(sp) - 37e: c682 sw zero,76(sp) - 380: c482 sw zero,72(sp) - -00000382 <.LBB127>: - 382: bbe1 j 15a <.L8> - -00000384 <.L30>: - 384: 0005a303 lw t1,0(a1) - 388: 0591 add a1,a1,4 - 38a: 00d35433 srl s0,t1,a3 - -0000038e <.LVL98>: - 38e: ce22 sw s0,28(sp) - 390: 0005a303 lw t1,0(a1) - 394: 4452 lw s0,20(sp) - 396: 00831333 sll t1,t1,s0 - 39a: 841a mv s0,t1 - 39c: 4372 lw t1,28(sp) - 39e: 00836333 or t1,t1,s0 - 3a2: 4442 lw s0,16(sp) - 3a4: 00672023 sw t1,0(a4) - -000003a8 <.LVL99>: - 3a8: 0711 add a4,a4,4 - 3aa: 0405 add s0,s0,1 - 3ac: c822 sw s0,16(sp) - -000003ae <.LVL100>: - 3ae: bddd j 2a4 <.L29> - -000003b0 <.L5>: - 3b0: 4716 lw a4,68(sp) - 3b2: 52f2 lw t0,60(sp) - 3b4: 4386 lw t2,64(sp) - 3b6: c03a sw a4,0(sp) - 3b8: 1c050563 beqz a0,582 <.L45> - 3bc: 4742 lw a4,16(sp) - 3be: 4692 lw a3,4(sp) - -000003c0 <.LVL102>: - 3c0: 40d70533 sub a0,a4,a3 - -000003c4 <.LVL103>: - 3c4: e6a5 bnez a3,42c <.L46> - 3c6: 55b2 lw a1,44(sp) - 3c8: 5742 lw a4,48(sp) - -000003ca <.LVL104>: - 3ca: 5352 lw t1,52(sp) - 3cc: 00e5e6b3 or a3,a1,a4 - 3d0: 0066e6b3 or a3,a3,t1 - 3d4: 8edd or a3,a3,a5 - 3d6: e699 bnez a3,3e4 <.L47> - -000003d8 <.LVL105>: - 3d8: c4a6 sw s1,72(sp) - -000003da <.L363>: - 3da: 4782 lw a5,0(sp) - 3dc: c696 sw t0,76(sp) - 3de: c89e sw t2,80(sp) - -000003e0 <.L355>: - 3e0: cabe sw a5,84(sp) - -000003e2 <.LBB131>: - 3e2: bba5 j 15a <.L8> - -000003e4 <.L47>: - 3e4: fff50693 add a3,a0,-1 - -000003e8 <.LVL110>: - 3e8: e695 bnez a3,414 <.L48> - -000003ea <.LBB35>: - 3ea: 009786b3 add a3,a5,s1 - -000003ee <.LVL111>: - 3ee: 00558633 add a2,a1,t0 - 3f2: c4b6 sw a3,72(sp) - -000003f4 <.LVL112>: - 3f4: 00f6b6b3 sltu a3,a3,a5 - -000003f8 <.LVL113>: - 3f8: 96b2 add a3,a3,a2 - -000003fa <.LVL114>: - 3fa: c6b6 sw a3,76(sp) - -000003fc <.LVL115>: - 3fc: 00b635b3 sltu a1,a2,a1 - -00000400 <.LVL116>: - 400: 00c6b6b3 sltu a3,a3,a2 - -00000404 <.LVL117>: - 404: 007707b3 add a5,a4,t2 - -00000408 <.LVL118>: - 408: 8dd5 or a1,a1,a3 - -0000040a <.LVL119>: - 40a: 95be add a1,a1,a5 - 40c: c8ae sw a1,80(sp) - -0000040e <.LVL120>: - 40e: 00e7b733 sltu a4,a5,a4 - -00000412 <.LVL121>: - 412: b329 j 11c <.L351> - -00000414 <.L48>: - 414: 67a1 lui a5,0x8 - 416: 17fd add a5,a5,-1 # 7fff <.LLST158+0x5687> - 418: 32f512e3 bne a0,a5,f3c <.L59> - -0000041c <.L60>: - 41c: c4a6 sw s1,72(sp) - -0000041e <.L356>: - 41e: 4782 lw a5,0(sp) - 420: c696 sw t0,76(sp) - 422: c89e sw t2,80(sp) - 424: cabe sw a5,84(sp) - -00000426 <.LBB134>: - 426: a479 j 6b4 <.L358> - -00000428 <.L268>: - 428: 84be mv s1,a5 - 42a: bfcd j 41c <.L60> - -0000042c <.L46>: - 42c: 4742 lw a4,16(sp) - -0000042e <.LVL127>: - 42e: 67a1 lui a5,0x8 - 430: 17fd add a5,a5,-1 # 7fff <.LLST158+0x5687> - 432: fef705e3 beq a4,a5,41c <.L60> - 436: 57d2 lw a5,52(sp) - 438: 00080737 lui a4,0x80 - 43c: 8fd9 or a5,a5,a4 - 43e: da3e sw a5,52(sp) - -00000440 <.LDL4>: - 440: 07400793 li a5,116 - 444: 30a7c0e3 blt a5,a0,f44 <.L61> - 448: 86aa mv a3,a0 - -0000044a <.L263>: - 44a: 41f6d793 sra a5,a3,0x1f - 44e: 8bfd and a5,a5,31 - 450: 97b6 add a5,a5,a3 - 452: 8795 sra a5,a5,0x5 - -00000454 <.LVL129>: - 454: 85b2 mv a1,a2 - 456: 4401 li s0,0 - 458: 4701 li a4,0 - -0000045a <.L62>: - 45a: 02f74563 blt a4,a5,484 <.L63> - 45e: 458d li a1,3 - 460: 01f6f713 and a4,a3,31 - -00000464 <.LVL131>: - 464: 40f580b3 sub ra,a1,a5 - 468: e31d bnez a4,48e <.L64> - 46a: 00279593 sll a1,a5,0x2 - -0000046e <.L65>: - 46e: 00b606b3 add a3,a2,a1 - 472: 4294 lw a3,0(a3) - 474: 0705 add a4,a4,1 # 80001 <.LLST158+0x7d689> - -00000476 <.LVL133>: - 476: c214 sw a3,0(a2) - -00000478 <.LVL134>: - 478: 0611 add a2,a2,4 - 47a: fee0dae3 bge ra,a4,46e <.L65> - 47e: 4511 li a0,4 - 480: 8d1d sub a0,a0,a5 - 482: a88d j 4f4 <.L71> - -00000484 <.L63>: - 484: 4188 lw a0,0(a1) - 486: 0705 add a4,a4,1 - -00000488 <.LVL136>: - 488: 0591 add a1,a1,4 - 48a: 8c49 or s0,s0,a0 - -0000048c <.LVL137>: - 48c: b7f9 j 45a <.L62> - -0000048e <.L64>: - 48e: 800005b7 lui a1,0x80000 - 492: 05fd add a1,a1,31 # 8000001f <.LLST158+0x7fffd6a7> - 494: 8eed and a3,a3,a1 - -00000496 <.LVL139>: - 496: 0006d663 bgez a3,4a2 <.L67> - 49a: 16fd add a3,a3,-1 - 49c: fe06e693 or a3,a3,-32 - 4a0: 0685 add a3,a3,1 - -000004a2 <.L67>: - 4a2: 02000513 li a0,32 - 4a6: 40d506b3 sub a3,a0,a3 - 4aa: c236 sw a3,4(sp) - -000004ac <.LVL140>: - 4ac: 86be mv a3,a5 - 4ae: 0007d363 bgez a5,4b4 <.L68> - -000004b2 <.LVL141>: - 4b2: 4681 li a3,0 - -000004b4 <.L68>: - 4b4: 068a sll a3,a3,0x2 - 4b6: 102c add a1,sp,40 - 4b8: 04c68693 add a3,a3,76 - 4bc: 96ae add a3,a3,a1 - 4be: fb46a683 lw a3,-76(a3) - 4c2: 4592 lw a1,4(sp) - 4c4: 4301 li t1,0 - 4c6: 00b696b3 sll a3,a3,a1 - 4ca: 8c55 or s0,s0,a3 - -000004cc <.LVL143>: - 4cc: 00279693 sll a3,a5,0x2 - 4d0: 02868693 add a3,a3,40 - 4d4: 968a add a3,a3,sp - -000004d6 <.L69>: - 4d6: 08134763 blt t1,ra,564 <.L70> - 4da: 4511 li a0,4 - 4dc: 8d1d sub a0,a0,a5 - -000004de <.LVL145>: - 4de: 00209793 sll a5,ra,0x2 - -000004e2 <.LVL146>: - 4e2: 04c78793 add a5,a5,76 - 4e6: 1034 add a3,sp,40 - 4e8: 96be add a3,a3,a5 - 4ea: 57d2 lw a5,52(sp) - 4ec: 00e7d7b3 srl a5,a5,a4 - 4f0: faf6aa23 sw a5,-76(a3) - -000004f4 <.L71>: - 4f4: 4791 li a5,4 - 4f6: 4601 li a2,0 - 4f8: 00a7c563 blt a5,a0,502 <.L73> - 4fc: 8f89 sub a5,a5,a0 - 4fe: 00279613 sll a2,a5,0x2 - -00000502 <.L73>: - 502: 050a sll a0,a0,0x2 - 504: 02850793 add a5,a0,40 - 508: 00278533 add a0,a5,sp - 50c: 4581 li a1,0 - 50e: ca1e sw t2,20(sp) - 510: c216 sw t0,4(sp) - 512: 00000097 auipc ra,0x0 - 516: 000080e7 jalr ra # 512 <.L73+0x10> - -0000051a <.LBE37>: - 51a: 57a2 lw a5,40(sp) - -0000051c <.LBE36>: - 51c: 4292 lw t0,4(sp) - 51e: 43d2 lw t2,20(sp) - -00000520 <.LBB38>: - 520: 00803433 snez s0,s0 - -00000524 <.LBE38>: - 524: 8c5d or s0,s0,a5 - -00000526 <.L74>: - 526: 57b2 lw a5,44(sp) - -00000528 <.LBB41>: - 528: d422 sw s0,40(sp) - -0000052a <.LBB42>: - 52a: 9426 add s0,s0,s1 - 52c: 005786b3 add a3,a5,t0 - 530: 5742 lw a4,48(sp) - 532: c4a2 sw s0,72(sp) - -00000534 <.LVL151>: - 534: 00943433 sltu s0,s0,s1 - -00000538 <.LVL152>: - 538: 9436 add s0,s0,a3 - -0000053a <.LVL153>: - 53a: 00f6b7b3 sltu a5,a3,a5 - -0000053e <.LVL154>: - 53e: c6a2 sw s0,76(sp) - -00000540 <.LVL155>: - 540: 00d43433 sltu s0,s0,a3 - -00000544 <.LVL156>: - 544: 00770633 add a2,a4,t2 - -00000548 <.LVL157>: - 548: 8fc1 or a5,a5,s0 - -0000054a <.LVL158>: - 54a: 97b2 add a5,a5,a2 - 54c: c8be sw a5,80(sp) - -0000054e <.LVL159>: - 54e: 00e63733 sltu a4,a2,a4 - -00000552 <.LVL160>: - 552: 00c7b7b3 sltu a5,a5,a2 - -00000556 <.LVL161>: - 556: 8f5d or a4,a4,a5 - -00000558 <.LVL162>: - 558: 4682 lw a3,0(sp) - -0000055a <.LVL163>: - 55a: 57d2 lw a5,52(sp) - -0000055c <.LBB137>: - 55c: 4542 lw a0,16(sp) - -0000055e <.LBB138>: - 55e: 97b6 add a5,a5,a3 - 560: 973e add a4,a4,a5 - -00000562 <.LBE43>: - 562: b3f1 j 32e <.L20> - -00000564 <.L70>: - 564: 428c lw a1,0(a3) - 566: 4512 lw a0,4(sp) - 568: 0305 add t1,t1,1 - -0000056a <.LVL166>: - 56a: 00e5d5b3 srl a1,a1,a4 - 56e: ca2e sw a1,20(sp) - 570: 42cc lw a1,4(a3) - 572: 0691 add a3,a3,4 - 574: 00a595b3 sll a1,a1,a0 - 578: 4552 lw a0,20(sp) - 57a: 8dc9 or a1,a1,a0 - 57c: c20c sw a1,0(a2) - -0000057e <.LVL167>: - 57e: 0611 add a2,a2,4 - 580: bf99 j 4d6 <.L69> - -00000582 <.L45>: - 582: 4712 lw a4,4(sp) - 584: 6321 lui t1,0x8 - 586: ffe30593 add a1,t1,-2 # 7ffe <.LLST158+0x5686> - 58a: 00170513 add a0,a4,1 - -0000058e <.LVL169>: - 58e: 8de9 and a1,a1,a0 - 590: 5732 lw a4,44(sp) - 592: 56c2 lw a3,48(sp) - -00000594 <.LVL170>: - 594: 5652 lw a2,52(sp) - 596: eddd bnez a1,654 <.L85> - 598: 4512 lw a0,4(sp) - 59a: 00d765b3 or a1,a4,a3 - 59e: 8dd1 or a1,a1,a2 - 5a0: 8ddd or a1,a1,a5 - 5a2: e93d bnez a0,618 <.L86> - -000005a4 <.LVL171>: - 5a4: e981 bnez a1,5b4 <.L87> - 5a6: 4782 lw a5,0(sp) - 5a8: c4a6 sw s1,72(sp) - 5aa: c696 sw t0,76(sp) - 5ac: c89e sw t2,80(sp) - -000005ae <.L350>: - 5ae: cabe sw a5,84(sp) - -000005b0 <.L354>: - 5b0: 4501 li a0,0 - 5b2: b665 j 15a <.L8> - -000005b4 <.L87>: - 5b4: 4502 lw a0,0(sp) - 5b6: 0072e5b3 or a1,t0,t2 - 5ba: 8dc9 or a1,a1,a0 - 5bc: 8dc5 or a1,a1,s1 - 5be: e591 bnez a1,5ca <.L88> - 5c0: c4be sw a5,72(sp) - 5c2: c6ba sw a4,76(sp) - 5c4: c8b6 sw a3,80(sp) - 5c6: cab2 sw a2,84(sp) - 5c8: b7e5 j 5b0 <.L354> - -000005ca <.L88>: - 5ca: 009785b3 add a1,a5,s1 - 5ce: 00570533 add a0,a4,t0 - 5d2: c4ae sw a1,72(sp) - -000005d4 <.LVL175>: - 5d4: 00f5b5b3 sltu a1,a1,a5 - -000005d8 <.LVL176>: - 5d8: 95aa add a1,a1,a0 - -000005da <.LVL177>: - 5da: c6ae sw a1,76(sp) - -000005dc <.LVL178>: - 5dc: 00e53733 sltu a4,a0,a4 - -000005e0 <.LVL179>: - 5e0: 00a5b5b3 sltu a1,a1,a0 - -000005e4 <.LVL180>: - 5e4: 007687b3 add a5,a3,t2 - -000005e8 <.LVL181>: - 5e8: 8f4d or a4,a4,a1 - -000005ea <.LVL182>: - 5ea: 973e add a4,a4,a5 - 5ec: 00d7b6b3 sltu a3,a5,a3 - -000005f0 <.LVL183>: - 5f0: c8ba sw a4,80(sp) - -000005f2 <.LVL184>: - 5f2: 00f73733 sltu a4,a4,a5 - -000005f6 <.LVL185>: - 5f6: 4782 lw a5,0(sp) - 5f8: 8ed9 or a3,a3,a4 - -000005fa <.LVL186>: - 5fa: 963e add a2,a2,a5 - 5fc: 96b2 add a3,a3,a2 - -000005fe <.LBE45>: - 5fe: 000807b7 lui a5,0x80 - 602: 8ff5 and a5,a5,a3 - 604: e399 bnez a5,60a <.L99> - -00000606 <.LBB46>: - 606: cab6 sw a3,84(sp) - 608: b765 j 5b0 <.L354> - -0000060a <.L99>: - 60a: fff807b7 lui a5,0xfff80 - 60e: 17fd add a5,a5,-1 # fff7ffff <.LLST158+0xfff7d687> - 610: 8efd and a3,a3,a5 - 612: cab6 sw a3,84(sp) - -00000614 <.LBB145>: - 614: 4505 li a0,1 - -00000616 <.LVL188>: - 616: b691 j 15a <.L8> - -00000618 <.L86>: - 618: b20580e3 beqz a1,138 <.L266> - 61c: 4502 lw a0,0(sp) - 61e: 0072e5b3 or a1,t0,t2 - 622: 8dc9 or a1,a1,a0 - 624: 8dc5 or a1,a1,s1 - 626: b0058be3 beqz a1,13c <.L267> - -0000062a <.LBB148>: - 62a: ca9a sw t1,84(sp) - 62c: c882 sw zero,80(sp) - 62e: c682 sw zero,76(sp) - 630: c482 sw zero,72(sp) - -00000632 <.LBB47>: - 632: 00bc add a5,sp,72 - 634: 1870 add a2,sp,60 - -00000636 <.L102>: - 636: 47d8 lw a4,12(a5) - 638: 4794 lw a3,8(a5) - 63a: 17f1 add a5,a5,-4 - 63c: 070e sll a4,a4,0x3 - 63e: 82f5 srl a3,a3,0x1d - 640: 8f55 or a4,a4,a3 - 642: cb98 sw a4,16(a5) - 644: fef619e3 bne a2,a5,636 <.L102> - -00000648 <.L352>: - 648: 47a6 lw a5,72(sp) - -0000064a <.LBE69>: - 64a: 6521 lui a0,0x8 - 64c: 157d add a0,a0,-1 # 7fff <.LLST158+0x5687> - -0000064e <.LBB70>: - 64e: 078e sll a5,a5,0x3 - -00000650 <.LBB150>: - 650: c4be sw a5,72(sp) - 652: ab59 j be8 <.L357> - -00000654 <.L85>: - 654: 009785b3 add a1,a5,s1 - 658: 00570333 add t1,a4,t0 - 65c: c4ae sw a1,72(sp) - -0000065e <.LVL195>: - 65e: 00f5b5b3 sltu a1,a1,a5 - -00000662 <.LVL196>: - 662: 959a add a1,a1,t1 - -00000664 <.LVL197>: - 664: c6ae sw a1,76(sp) - -00000666 <.LVL198>: - 666: 00e33733 sltu a4,t1,a4 - -0000066a <.LVL199>: - 66a: 0065b5b3 sltu a1,a1,t1 - -0000066e <.LVL200>: - 66e: 007687b3 add a5,a3,t2 - -00000672 <.LVL201>: - 672: 8f4d or a4,a4,a1 - -00000674 <.LVL202>: - 674: 973e add a4,a4,a5 - 676: 00d7b6b3 sltu a3,a5,a3 - -0000067a <.LVL203>: - 67a: c8ba sw a4,80(sp) - -0000067c <.LVL204>: - 67c: 00f73733 sltu a4,a4,a5 - -00000680 <.LVL205>: - 680: 4782 lw a5,0(sp) - 682: 8ed9 or a3,a3,a4 - -00000684 <.LVL206>: - 684: 963e add a2,a2,a5 - 686: 96b2 add a3,a3,a2 - 688: cab6 sw a3,84(sp) - -0000068a <.LBB49>: - 68a: 00bc add a5,sp,72 - -0000068c <.LVL208>: - 68c: 08d0 add a2,sp,84 - -0000068e <.L114>: - 68e: 4398 lw a4,0(a5) - 690: 43d4 lw a3,4(a5) - 692: 8305 srl a4,a4,0x1 - 694: 06fe sll a3,a3,0x1f - 696: 8f55 or a4,a4,a3 - 698: c398 sw a4,0(a5) - 69a: 0791 add a5,a5,4 - 69c: fef619e3 bne a2,a5,68e <.L114> - 6a0: 47d6 lw a5,84(sp) - -000006a2 <.LBE49>: - 6a2: 6721 lui a4,0x8 - 6a4: 177d add a4,a4,-1 # 7fff <.LLST158+0x5687> - -000006a6 <.LBB52>: - 6a6: 8385 srl a5,a5,0x1 - -000006a8 <.LBE52>: - 6a8: d2e51ce3 bne a0,a4,3e0 <.L355> - -000006ac <.LVL211>: - 6ac: ca82 sw zero,84(sp) - 6ae: c882 sw zero,80(sp) - 6b0: c682 sw zero,76(sp) - 6b2: c482 sw zero,72(sp) - -000006b4 <.L358>: - 6b4: 6521 lui a0,0x8 - 6b6: 157d add a0,a0,-1 # 7fff <.LLST158+0x5687> - 6b8: b44d j 15a <.L8> - -000006ba <.L4>: - 6ba: 20a05063 blez a0,8ba <.L120> - -000006be <.LBB156>: - 6be: 56d2 lw a3,52(sp) - 6c0: 52b2 lw t0,44(sp) - 6c2: 53c2 lw t2,48(sp) - 6c4: c036 sw a3,0(sp) - -000006c6 <.LBB157>: - 6c6: 46c2 lw a3,16(sp) - 6c8: e2d1 bnez a3,74c <.L121> - 6ca: 5472 lw s0,60(sp) - 6cc: 4306 lw t1,64(sp) - 6ce: 4696 lw a3,68(sp) - 6d0: 00646633 or a2,s0,t1 - 6d4: 8e55 or a2,a2,a3 - 6d6: 8e45 or a2,a2,s1 - 6d8: a00609e3 beqz a2,ea <.L362> - 6dc: fff50593 add a1,a0,-1 - -000006e0 <.LVL215>: - 6e0: e9a9 bnez a1,732 <.L123> - -000006e2 <.LBB72>: - 6e2: 40828633 sub a2,t0,s0 - 6e6: 00c2b533 sltu a0,t0,a2 - 6ea: 40978733 sub a4,a5,s1 - -000006ee <.LVL217>: - 6ee: c22a sw a0,4(sp) - -000006f0 <.LVL218>: - 6f0: 84aa mv s1,a0 - -000006f2 <.LVL219>: - 6f2: 00e7b533 sltu a0,a5,a4 - 6f6: 8e09 sub a2,a2,a0 - -000006f8 <.LVL220>: - 6f8: 40638533 sub a0,t2,t1 - 6fc: c82a sw a0,16(sp) - -000006fe <.LVL221>: - 6fe: 0063b533 sltu a0,t2,t1 - 702: 00e7fc63 bgeu a5,a4,71a <.L128> - 706: 00541a63 bne s0,t0,71a <.L128> - -0000070a <.LVL222>: - 70a: 406387b3 sub a5,t2,t1 - 70e: 17fd add a5,a5,-1 - -00000710 <.L129>: - 710: 40730333 sub t1,t1,t2 - 714: 00133593 seqz a1,t1 - -00000718 <.LVL224>: - 718: a031 j 724 <.L130> - -0000071a <.L128>: - 71a: 4412 lw s0,4(sp) - 71c: 406387b3 sub a5,t2,t1 - 720: 8f85 sub a5,a5,s1 - -00000722 <.LVL226>: - 722: f47d bnez s0,710 <.L129> - -00000724 <.L130>: - 724: 4402 lw s0,0(sp) - 726: 8d4d or a0,a0,a1 - -00000728 <.LVL228>: - 728: 40d406b3 sub a3,s0,a3 - 72c: 8e89 sub a3,a3,a0 - -0000072e <.L353>: - 72e: 4505 li a0,1 - -00000730 <.LBB159>: - 730: a281 j 870 <.L131> - -00000732 <.L123>: - 732: 66a1 lui a3,0x8 - 734: 16fd add a3,a3,-1 # 7fff <.LLST158+0x5687> - 736: 9ed50fe3 beq a0,a3,134 <.L361> - 73a: 07400693 li a3,116 - 73e: 02b6d663 bge a3,a1,76a <.L264> - -00000742 <.L133>: - 742: c282 sw zero,68(sp) - 744: c082 sw zero,64(sp) - 746: de02 sw zero,60(sp) - 748: 4705 li a4,1 - 74a: a8e1 j 822 <.L144> - -0000074c <.L121>: - 74c: 4612 lw a2,4(sp) - 74e: 66a1 lui a3,0x8 - -00000750 <.LVL233>: - 750: 16fd add a3,a3,-1 # 7fff <.LLST158+0x5687> - 752: ccd60be3 beq a2,a3,428 <.L268> - 756: 4696 lw a3,68(sp) - 758: 00080637 lui a2,0x80 - 75c: 8ed1 or a3,a3,a2 - 75e: c2b6 sw a3,68(sp) - -00000760 <.LDL5>: - 760: 07400693 li a3,116 - 764: fca6cfe3 blt a3,a0,742 <.L133> - 768: 85aa mv a1,a0 - -0000076a <.L264>: - 76a: 4055d513 sra a0,a1,0x5 - -0000076e <.LVL235>: - 76e: 863a mv a2,a4 - 770: 89fd and a1,a1,31 - -00000772 <.LVL236>: - 772: 4481 li s1,0 - 774: 4681 li a3,0 - -00000776 <.L134>: - 776: 02a69463 bne a3,a0,79e <.L135> - 77a: 468d li a3,3 - -0000077c <.LVL238>: - 77c: 8e89 sub a3,a3,a0 - 77e: 00251613 sll a2,a0,0x2 - 782: e58d bnez a1,7ac <.L136> - -00000784 <.L137>: - 784: 00c70333 add t1,a4,a2 - 788: 00032303 lw t1,0(t1) - 78c: 0585 add a1,a1,1 - -0000078e <.LVL240>: - 78e: 00672023 sw t1,0(a4) - -00000792 <.LVL241>: - 792: 0711 add a4,a4,4 - 794: feb6d8e3 bge a3,a1,784 <.L137> - 798: 4711 li a4,4 - 79a: 8f09 sub a4,a4,a0 - 79c: a899 j 7f2 <.L141> - -0000079e <.L135>: - 79e: 00062303 lw t1,0(a2) # 80000 <.LLST158+0x7d688> - 7a2: 0685 add a3,a3,1 - -000007a4 <.LVL243>: - 7a4: 0611 add a2,a2,4 - 7a6: 0064e4b3 or s1,s1,t1 - -000007aa <.LVL244>: - 7aa: b7f1 j 776 <.L134> - -000007ac <.L136>: - 7ac: 02000313 li t1,32 - 7b0: 40b30433 sub s0,t1,a1 - 7b4: ca22 sw s0,20(sp) - -000007b6 <.LVL246>: - 7b6: 02810313 add t1,sp,40 - 7ba: 04c60413 add s0,a2,76 - 7be: 9322 add t1,t1,s0 - 7c0: fc432303 lw t1,-60(t1) - 7c4: 4452 lw s0,20(sp) - 7c6: c802 sw zero,16(sp) - -000007c8 <.LVL247>: - 7c8: 00831333 sll t1,t1,s0 - 7cc: 1820 add s0,sp,56 - 7ce: 0064e4b3 or s1,s1,t1 - -000007d2 <.LVL248>: - 7d2: 9622 add a2,a2,s0 - -000007d4 <.L139>: - 7d4: 4442 lw s0,16(sp) - 7d6: 0ad44c63 blt s0,a3,88e <.L140> - 7da: 068a sll a3,a3,0x2 - 7dc: 1030 add a2,sp,40 - 7de: 04c68693 add a3,a3,76 - 7e2: 96b2 add a3,a3,a2 - 7e4: 4616 lw a2,68(sp) - 7e6: 4711 li a4,4 - 7e8: 8f09 sub a4,a4,a0 - -000007ea <.LVL250>: - 7ea: 00b65633 srl a2,a2,a1 - 7ee: fcc6a223 sw a2,-60(a3) - -000007f2 <.L141>: - 7f2: 4691 li a3,4 - 7f4: 8e99 sub a3,a3,a4 - 7f6: 1830 add a2,sp,56 - 7f8: 070a sll a4,a4,0x2 - 7fa: 9732 add a4,a4,a2 - 7fc: 068a sll a3,a3,0x2 - 7fe: 4621 li a2,8 - 800: 00c6e863 bltu a3,a2,810 <.L142> - 804: 00072023 sw zero,0(a4) - -00000808 <.LVL252>: - 808: 00072223 sw zero,4(a4) - 80c: 16e1 add a3,a3,-8 - 80e: 0721 add a4,a4,8 - -00000810 <.L142>: - 810: 4611 li a2,4 - 812: 00c6e463 bltu a3,a2,81a <.L143> - 816: 00072023 sw zero,0(a4) - -0000081a <.L143>: - 81a: 56e2 lw a3,56(sp) - -0000081c <.LBB75>: - 81c: 00903733 snez a4,s1 - -00000820 <.LBE75>: - 820: 8f55 or a4,a4,a3 - -00000822 <.L144>: - 822: 5572 lw a0,60(sp) - -00000824 <.LBB78>: - 824: dc3a sw a4,56(sp) - -00000826 <.LBB79>: - 826: 40e78733 sub a4,a5,a4 - -0000082a <.LVL256>: - 82a: 40a28633 sub a2,t0,a0 - 82e: 00e7b6b3 sltu a3,a5,a4 - 832: 00c2b433 sltu s0,t0,a2 - -00000836 <.LVL257>: - 836: 8e15 sub a2,a2,a3 - -00000838 <.LVL258>: - 838: 4686 lw a3,64(sp) - 83a: 84a2 mv s1,s0 - -0000083c <.LVL259>: - 83c: 40d385b3 sub a1,t2,a3 - 840: 00d3b333 sltu t1,t2,a3 - 844: 00e7f663 bgeu a5,a4,850 <.L149> - 848: fff58793 add a5,a1,-1 - 84c: 00550663 beq a0,t0,858 <.L150> - -00000850 <.L149>: - 850: 409587b3 sub a5,a1,s1 - -00000854 <.LVL261>: - 854: 4581 li a1,0 - 856: c409 beqz s0,860 <.L151> - -00000858 <.L150>: - 858: 407686b3 sub a3,a3,t2 - 85c: 0016b593 seqz a1,a3 - -00000860 <.L151>: - 860: 4502 lw a0,0(sp) - 862: 4696 lw a3,68(sp) - 864: 0065e5b3 or a1,a1,t1 - -00000868 <.LVL264>: - 868: 40d506b3 sub a3,a0,a3 - -0000086c <.LBB160>: - 86c: 4512 lw a0,4(sp) - -0000086e <.LBB161>: - 86e: 8e8d sub a3,a3,a1 - -00000870 <.L131>: - 870: c8be sw a5,80(sp) - -00000872 <.LBE81>: - 872: 000807b7 lui a5,0x80 - -00000876 <.LBB82>: - 876: c4ba sw a4,72(sp) - -00000878 <.LBB83>: - 878: cab6 sw a3,84(sp) - 87a: c6b2 sw a2,76(sp) - -0000087c <.LBE83>: - 87c: 00f6f733 and a4,a3,a5 - 880: 8c070de3 beqz a4,15a <.L8> - -00000884 <.LBB84>: - 884: 17fd add a5,a5,-1 # 7ffff <.LLST158+0x7d687> - 886: 8efd and a3,a3,a5 - 888: cab6 sw a3,84(sp) - 88a: c22a sw a0,4(sp) - 88c: a179 j d1a <.L227> - -0000088e <.L140>: - 88e: 00062303 lw t1,0(a2) - 892: 0611 add a2,a2,4 - 894: 00b35433 srl s0,t1,a1 - -00000898 <.LVL268>: - 898: ce22 sw s0,28(sp) - 89a: 00062303 lw t1,0(a2) - 89e: 4452 lw s0,20(sp) - 8a0: 00831333 sll t1,t1,s0 - 8a4: 841a mv s0,t1 - 8a6: 4372 lw t1,28(sp) - 8a8: 00836333 or t1,t1,s0 - 8ac: 4442 lw s0,16(sp) - 8ae: 00672023 sw t1,0(a4) - -000008b2 <.LVL269>: - 8b2: 0711 add a4,a4,4 - 8b4: 0405 add s0,s0,1 - 8b6: c822 sw s0,16(sp) - -000008b8 <.LVL270>: - 8b8: bf31 j 7d4 <.L139> - -000008ba <.L120>: - 8ba: 4716 lw a4,68(sp) - 8bc: 5472 lw s0,60(sp) - 8be: 4386 lw t2,64(sp) - 8c0: c03a sw a4,0(sp) - -000008c2 <.LBB163>: - 8c2: 20050363 beqz a0,ac8 <.L152> - 8c6: 4742 lw a4,16(sp) - 8c8: 4692 lw a3,4(sp) - 8ca: 40d70533 sub a0,a4,a3 - -000008ce <.LVL272>: - 8ce: e6c9 bnez a3,958 <.L153> - 8d0: 52b2 lw t0,44(sp) - 8d2: 5342 lw t1,48(sp) - 8d4: 56d2 lw a3,52(sp) - 8d6: 0062e733 or a4,t0,t1 - -000008da <.LVL273>: - 8da: 8f55 or a4,a4,a3 - 8dc: 8f5d or a4,a4,a5 - 8de: eb09 bnez a4,8f0 <.L154> - -000008e0 <.LVL274>: - 8e0: 4782 lw a5,0(sp) - 8e2: c4a6 sw s1,72(sp) - 8e4: c6a2 sw s0,76(sp) - 8e6: c89e sw t2,80(sp) - 8e8: cabe sw a5,84(sp) - -000008ea <.L359>: - 8ea: 47d2 lw a5,20(sp) - 8ec: c63e sw a5,12(sp) - -000008ee <.LVL276>: - 8ee: b0b5 j 15a <.L8> - -000008f0 <.L154>: - 8f0: fff50593 add a1,a0,-1 - -000008f4 <.LVL278>: - 8f4: e5b1 bnez a1,940 <.L155> - -000008f6 <.LBB86>: - 8f6: 40540633 sub a2,s0,t0 - 8fa: 40f48733 sub a4,s1,a5 - -000008fe <.LVL280>: - 8fe: 00c437b3 sltu a5,s0,a2 - 902: c23e sw a5,4(sp) - -00000904 <.LVL281>: - 904: c63e sw a5,12(sp) - -00000906 <.LVL282>: - 906: 00e4b7b3 sltu a5,s1,a4 - -0000090a <.LVL283>: - 90a: 8e1d sub a2,a2,a5 - -0000090c <.LVL284>: - 90c: 0063b533 sltu a0,t2,t1 - 910: 406387b3 sub a5,t2,t1 - 914: 00e4fa63 bgeu s1,a4,928 <.L160> - 918: 00829863 bne t0,s0,928 <.L160> - -0000091c <.LVL285>: - 91c: 17fd add a5,a5,-1 - -0000091e <.L161>: - 91e: 40730333 sub t1,t1,t2 - 922: 00133593 seqz a1,t1 - -00000926 <.LVL287>: - 926: a029 j 930 <.L162> - -00000928 <.L160>: - 928: 4432 lw s0,12(sp) - 92a: 8f81 sub a5,a5,s0 - -0000092c <.LVL289>: - 92c: 4412 lw s0,4(sp) - 92e: f865 bnez s0,91e <.L161> - -00000930 <.L162>: - 930: 4402 lw s0,0(sp) - 932: 8d4d or a0,a0,a1 - -00000934 <.LBE86>: - 934: 45d2 lw a1,20(sp) - -00000936 <.LBB87>: - 936: 40d406b3 sub a3,s0,a3 - 93a: 8e89 sub a3,a3,a0 - -0000093c <.LBE87>: - 93c: c62e sw a1,12(sp) - 93e: bbc5 j 72e <.L353> - -00000940 <.L155>: - 940: 67a1 lui a5,0x8 - 942: 17fd add a5,a5,-1 # 7fff <.LLST158+0x5687> - 944: 60f51663 bne a0,a5,f50 <.L163> - -00000948 <.L164>: - 948: 4782 lw a5,0(sp) - 94a: c4a6 sw s1,72(sp) - 94c: c6a2 sw s0,76(sp) - 94e: cabe sw a5,84(sp) - 950: 47d2 lw a5,20(sp) - 952: c89e sw t2,80(sp) - 954: c63e sw a5,12(sp) - -00000956 <.LVL294>: - 956: bbb9 j 6b4 <.L358> - -00000958 <.L153>: - 958: 4742 lw a4,16(sp) - -0000095a <.LVL296>: - 95a: 67a1 lui a5,0x8 - 95c: 17fd add a5,a5,-1 # 7fff <.LLST158+0x5687> - 95e: fef705e3 beq a4,a5,948 <.L164> - 962: 57d2 lw a5,52(sp) - 964: 00080737 lui a4,0x80 - 968: 8fd9 or a5,a5,a4 - 96a: da3e sw a5,52(sp) - -0000096c <.LDL6>: - 96c: 07400793 li a5,116 - 970: 5ea7c463 blt a5,a0,f58 <.L165> - 974: 85aa mv a1,a0 - -00000976 <.L265>: - 976: 41f5d793 sra a5,a1,0x1f - 97a: 8bfd and a5,a5,31 - 97c: 97ae add a5,a5,a1 - 97e: 8795 sra a5,a5,0x5 - -00000980 <.LVL298>: - 980: 86b2 mv a3,a2 - 982: 4281 li t0,0 - 984: 4701 li a4,0 - -00000986 <.L166>: - 986: 02f74563 blt a4,a5,9b0 <.L167> - 98a: 468d li a3,3 - 98c: 01f5f713 and a4,a1,31 - -00000990 <.LVL300>: - 990: 40f680b3 sub ra,a3,a5 - 994: e705 bnez a4,9bc <.L168> - 996: 00279593 sll a1,a5,0x2 - -0000099a <.L169>: - 99a: 00b606b3 add a3,a2,a1 - 99e: 4294 lw a3,0(a3) - 9a0: 0705 add a4,a4,1 # 80001 <.LLST158+0x7d689> - -000009a2 <.LVL302>: - 9a2: c214 sw a3,0(a2) - -000009a4 <.LVL303>: - 9a4: 0611 add a2,a2,4 - 9a6: fee0dae3 bge ra,a4,99a <.L169> - 9aa: 4511 li a0,4 - 9ac: 8d1d sub a0,a0,a5 - 9ae: a89d j a24 <.L175> - -000009b0 <.L167>: - 9b0: 4288 lw a0,0(a3) - 9b2: 0705 add a4,a4,1 - -000009b4 <.LVL305>: - 9b4: 0691 add a3,a3,4 - 9b6: 00a2e2b3 or t0,t0,a0 - -000009ba <.LVL306>: - 9ba: b7f1 j 986 <.L166> - -000009bc <.L168>: - 9bc: 800006b7 lui a3,0x80000 - 9c0: 06fd add a3,a3,31 # 8000001f <.LLST158+0x7fffd6a7> - 9c2: 8eed and a3,a3,a1 - 9c4: 0006d663 bgez a3,9d0 <.L171> - 9c8: 16fd add a3,a3,-1 - 9ca: fe06e693 or a3,a3,-32 - 9ce: 0685 add a3,a3,1 - -000009d0 <.L171>: - 9d0: 02000513 li a0,32 - 9d4: 40d506b3 sub a3,a0,a3 - 9d8: c236 sw a3,4(sp) - -000009da <.LVL308>: - 9da: 86be mv a3,a5 - 9dc: 0007d363 bgez a5,9e2 <.L172> - -000009e0 <.LVL309>: - 9e0: 4681 li a3,0 - -000009e2 <.L172>: - 9e2: 068a sll a3,a3,0x2 - 9e4: 102c add a1,sp,40 - -000009e6 <.LVL311>: - 9e6: 04c68693 add a3,a3,76 - 9ea: 96ae add a3,a3,a1 - 9ec: fb46a683 lw a3,-76(a3) - 9f0: 4592 lw a1,4(sp) - 9f2: 4301 li t1,0 - 9f4: 00b696b3 sll a3,a3,a1 - 9f8: 00d2e2b3 or t0,t0,a3 - -000009fc <.LVL312>: - 9fc: 00279693 sll a3,a5,0x2 - a00: 02868693 add a3,a3,40 - a04: 968a add a3,a3,sp - -00000a06 <.L173>: - a06: 08134363 blt t1,ra,a8c <.L174> - a0a: 4511 li a0,4 - a0c: 8d1d sub a0,a0,a5 - -00000a0e <.LVL314>: - a0e: 00209793 sll a5,ra,0x2 - -00000a12 <.LVL315>: - a12: 04c78793 add a5,a5,76 - a16: 1034 add a3,sp,40 - a18: 96be add a3,a3,a5 - a1a: 57d2 lw a5,52(sp) - a1c: 00e7d7b3 srl a5,a5,a4 - a20: faf6aa23 sw a5,-76(a3) - -00000a24 <.L175>: - a24: 4791 li a5,4 - a26: 4601 li a2,0 - a28: 00a7c563 blt a5,a0,a32 <.L177> - a2c: 8f89 sub a5,a5,a0 - a2e: 00279613 sll a2,a5,0x2 - -00000a32 <.L177>: - a32: 050a sll a0,a0,0x2 - a34: 02850793 add a5,a0,40 - a38: 00278533 add a0,a5,sp - a3c: 4581 li a1,0 - a3e: c61e sw t2,12(sp) - a40: c216 sw t0,4(sp) - a42: 00000097 auipc ra,0x0 - a46: 000080e7 jalr ra # a42 <.L177+0x10> - -00000a4a <.LBB90>: - a4a: 4292 lw t0,4(sp) - -00000a4c <.LBE90>: - a4c: 57a2 lw a5,40(sp) - -00000a4e <.LBE88>: - a4e: 43b2 lw t2,12(sp) - -00000a50 <.LBB91>: - a50: 00503733 snez a4,t0 - -00000a54 <.LBE91>: - a54: 8f5d or a4,a4,a5 - -00000a56 <.L178>: - a56: 55b2 lw a1,44(sp) - a58: 56c2 lw a3,48(sp) - -00000a5a <.LBB95>: - a5a: d43a sw a4,40(sp) - -00000a5c <.LBB96>: - a5c: 40b40633 sub a2,s0,a1 - a60: 40e48733 sub a4,s1,a4 - -00000a64 <.LVL320>: - a64: 00c43333 sltu t1,s0,a2 - -00000a68 <.LVL321>: - a68: 00e4b7b3 sltu a5,s1,a4 - a6c: 8e1d sub a2,a2,a5 - -00000a6e <.LVL322>: - a6e: 829a mv t0,t1 - -00000a70 <.LVL323>: - a70: 40d387b3 sub a5,t2,a3 - a74: 00d3b533 sltu a0,t2,a3 - a78: 02e4f963 bgeu s1,a4,aaa <.L183> - a7c: 02859763 bne a1,s0,aaa <.L183> - -00000a80 <.LVL324>: - a80: 17fd add a5,a5,-1 - -00000a82 <.L184>: - a82: 407686b3 sub a3,a3,t2 - a86: 0016b593 seqz a1,a3 - a8a: a02d j ab4 <.L185> - -00000a8c <.L174>: - a8c: 428c lw a1,0(a3) - a8e: 4512 lw a0,4(sp) - a90: 0305 add t1,t1,1 - -00000a92 <.LVL327>: - a92: 00e5d5b3 srl a1,a1,a4 - a96: c62e sw a1,12(sp) - a98: 42cc lw a1,4(a3) - a9a: 0691 add a3,a3,4 - a9c: 00a595b3 sll a1,a1,a0 - aa0: 4532 lw a0,12(sp) - aa2: 8dc9 or a1,a1,a0 - aa4: c20c sw a1,0(a2) - -00000aa6 <.LVL328>: - aa6: 0611 add a2,a2,4 - aa8: bfb9 j a06 <.L173> - -00000aaa <.L183>: - aaa: 405787b3 sub a5,a5,t0 - -00000aae <.LVL330>: - aae: 4581 li a1,0 - ab0: fc0319e3 bnez t1,a82 <.L184> - -00000ab4 <.L185>: - ab4: 56d2 lw a3,52(sp) - ab6: 4402 lw s0,0(sp) - ab8: 8dc9 or a1,a1,a0 - -00000aba <.LBB166>: - aba: 4542 lw a0,16(sp) - -00000abc <.LBB167>: - abc: 40d406b3 sub a3,s0,a3 - ac0: 8e8d sub a3,a3,a1 - -00000ac2 <.LBE99>: - ac2: 45d2 lw a1,20(sp) - -00000ac4 <.LVL333>: - ac4: c62e sw a1,12(sp) - ac6: b36d j 870 <.L131> - -00000ac8 <.L152>: - ac8: 5652 lw a2,52(sp) - -00000aca <.LBB169>: - aca: 6321 lui t1,0x8 - acc: ffe30593 add a1,t1,-2 # 7ffe <.LLST158+0x5686> - -00000ad0 <.LBB170>: - ad0: c832 sw a2,16(sp) - -00000ad2 <.LBB171>: - ad2: 4612 lw a2,4(sp) - -00000ad4 <.LBB172>: - ad4: 56b2 lw a3,44(sp) - ad6: 5742 lw a4,48(sp) - -00000ad8 <.LBB173>: - ad8: 0605 add a2,a2,1 - ada: 8e6d and a2,a2,a1 - adc: 16061d63 bnez a2,c56 <.L186> - ae0: 4642 lw a2,16(sp) - ae2: 4282 lw t0,0(sp) - ae4: 00e6e5b3 or a1,a3,a4 - ae8: 8dd1 or a1,a1,a2 - aea: 00746633 or a2,s0,t2 - aee: 00566633 or a2,a2,t0 - af2: 4292 lw t0,4(sp) - af4: 8ddd or a1,a1,a5 - af6: 8e45 or a2,a2,s1 - af8: 0e029b63 bnez t0,bee <.L187> - -00000afc <.LVL336>: - afc: e989 bnez a1,b0e <.L188> - afe: 4782 lw a5,0(sp) - b00: c4a6 sw s1,72(sp) - b02: c6a2 sw s0,76(sp) - b04: c89e sw t2,80(sp) - b06: cabe sw a5,84(sp) - b08: c265 beqz a2,be8 <.L357> - -00000b0a <.L206>: - b0a: 4501 li a0,0 - b0c: bbf9 j 8ea <.L359> - -00000b0e <.L188>: - b0e: e611 bnez a2,b1a <.L190> - b10: c4be sw a5,72(sp) - b12: c6b6 sw a3,76(sp) - b14: 47c2 lw a5,16(sp) - b16: c8ba sw a4,80(sp) - b18: bc59 j 5ae <.L350> - -00000b1a <.L190>: - b1a: 40978633 sub a2,a5,s1 - -00000b1e <.LVL339>: - b1e: 40868333 sub t1,a3,s0 - b22: 00c7b2b3 sltu t0,a5,a2 - b26: 0066b5b3 sltu a1,a3,t1 - b2a: 40530333 sub t1,t1,t0 - b2e: c21a sw t1,4(sp) - -00000b30 <.LVL340>: - b30: 00773333 sltu t1,a4,t2 - b34: d02e sw a1,32(sp) - -00000b36 <.LVL341>: - b36: ce1a sw t1,28(sp) - b38: 407702b3 sub t0,a4,t2 - b3c: 00c7fa63 bgeu a5,a2,b50 <.L195> - b40: 00869863 bne a3,s0,b50 <.L195> - -00000b44 <.LVL342>: - b44: fff28593 add a1,t0,-1 - -00000b48 <.L196>: - b48: 0012b313 seqz t1,t0 - b4c: ce1a sw t1,28(sp) - b4e: a039 j b5c <.L197> - -00000b50 <.L195>: - b50: 5302 lw t1,32(sp) - b52: ce02 sw zero,28(sp) - b54: 40b285b3 sub a1,t0,a1 - -00000b58 <.LVL345>: - b58: fe0318e3 bnez t1,b48 <.L196> - -00000b5c <.L197>: - b5c: 4282 lw t0,0(sp) - b5e: 4342 lw t1,16(sp) - b60: c8ae sw a1,80(sp) - b62: c4b2 sw a2,72(sp) - b64: 40530333 sub t1,t1,t0 - b68: 42f2 lw t0,28(sp) - b6a: d01a sw t1,32(sp) - b6c: 00773333 sltu t1,a4,t2 - b70: 0062e333 or t1,t0,t1 - b74: 5282 lw t0,32(sp) - b76: 406282b3 sub t0,t0,t1 - b7a: 4312 lw t1,4(sp) - b7c: ca96 sw t0,84(sp) - b7e: c69a sw t1,76(sp) - -00000b80 <.LBE100>: - b80: 00080337 lui t1,0x80 - b84: 0062f333 and t1,t0,t1 - b88: 04030963 beqz t1,bda <.L198> - -00000b8c <.LBB101>: - b8c: 40d40633 sub a2,s0,a3 - -00000b90 <.LVL348>: - b90: 40f487b3 sub a5,s1,a5 - -00000b94 <.LVL349>: - b94: 00c43333 sltu t1,s0,a2 - -00000b98 <.LVL350>: - b98: 00f4b5b3 sltu a1,s1,a5 - -00000b9c <.LVL351>: - b9c: 8e0d sub a2,a2,a1 - -00000b9e <.LVL352>: - b9e: 829a mv t0,t1 - -00000ba0 <.LVL353>: - ba0: 40e385b3 sub a1,t2,a4 - ba4: 00e3b533 sltu a0,t2,a4 - ba8: 00f4fa63 bgeu s1,a5,bbc <.L203> - bac: 00869863 bne a3,s0,bbc <.L203> - -00000bb0 <.LVL354>: - bb0: 15fd add a1,a1,-1 - -00000bb2 <.L204>: - bb2: 407706b3 sub a3,a4,t2 - bb6: 0016b693 seqz a3,a3 - bba: a031 j bc6 <.L205> - -00000bbc <.L203>: - bbc: 405585b3 sub a1,a1,t0 - -00000bc0 <.LVL357>: - bc0: 4681 li a3,0 - bc2: fe0318e3 bnez t1,bb2 <.L204> - -00000bc6 <.L205>: - bc6: 4702 lw a4,0(sp) - bc8: 4442 lw s0,16(sp) - bca: 8ec9 or a3,a3,a0 - -00000bcc <.LVL359>: - bcc: c8ae sw a1,80(sp) - -00000bce <.LVL360>: - bce: 8f01 sub a4,a4,s0 - bd0: 8f15 sub a4,a4,a3 - bd2: caba sw a4,84(sp) - bd4: c6b2 sw a2,76(sp) - bd6: c4be sw a5,72(sp) - -00000bd8 <.LBB174>: - bd8: bf0d j b0a <.L206> - -00000bda <.L198>: - bda: 4792 lw a5,4(sp) - bdc: 8e5d or a2,a2,a5 - -00000bde <.LVL363>: - bde: 8e4d or a2,a2,a1 - be0: 00566633 or a2,a2,t0 - be4: 9c0616e3 bnez a2,5b0 <.L354> - -00000be8 <.L357>: - be8: c602 sw zero,12(sp) - -00000bea <.LVL365>: - bea: d70ff06f j 15a <.L8> - -00000bee <.L187>: - bee: ed8d bnez a1,c28 <.L207> - bf0: e20d bnez a2,c12 <.L208> - -00000bf2 <.LVL367>: - bf2: ca9a sw t1,84(sp) - bf4: c882 sw zero,80(sp) - bf6: c682 sw zero,76(sp) - bf8: c482 sw zero,72(sp) - -00000bfa <.LBB102>: - bfa: 00bc add a5,sp,72 - bfc: 1870 add a2,sp,60 - -00000bfe <.L209>: - bfe: 47d8 lw a4,12(a5) - c00: 4794 lw a3,8(a5) - c02: 17f1 add a5,a5,-4 - c04: 070e sll a4,a4,0x3 - c06: 82f5 srl a3,a3,0x1d - c08: 8f55 or a4,a4,a3 - c0a: cb98 sw a4,16(a5) - c0c: fef619e3 bne a2,a5,bfe <.L209> - c10: bc25 j 648 <.L352> - -00000c12 <.L208>: - c12: 4782 lw a5,0(sp) - c14: c4a6 sw s1,72(sp) - c16: c6a2 sw s0,76(sp) - c18: cabe sw a5,84(sp) - -00000c1a <.LBB176>: - c1a: 47d2 lw a5,20(sp) - c1c: c89e sw t2,80(sp) - c1e: c63e sw a5,12(sp) - -00000c20 <.L360>: - c20: fff30513 add a0,t1,-1 # 7ffff <.LLST158+0x7d687> - c24: d36ff06f j 15a <.L8> - -00000c28 <.L207>: - c28: e619 bnez a2,c36 <.L210> - -00000c2a <.LVL373>: - c2a: c4be sw a5,72(sp) - c2c: 47c2 lw a5,16(sp) - c2e: c6b6 sw a3,76(sp) - c30: c8ba sw a4,80(sp) - c32: cabe sw a5,84(sp) - c34: b7f5 j c20 <.L360> - -00000c36 <.L210>: - c36: ca9a sw t1,84(sp) - c38: c882 sw zero,80(sp) - c3a: c682 sw zero,76(sp) - c3c: c482 sw zero,72(sp) - -00000c3e <.LBB103>: - c3e: 00bc add a5,sp,72 - c40: 1870 add a2,sp,60 - -00000c42 <.L211>: - c42: 47d8 lw a4,12(a5) - c44: 4794 lw a3,8(a5) - c46: 17f1 add a5,a5,-4 - c48: 070e sll a4,a4,0x3 - c4a: 82f5 srl a3,a3,0x1d - c4c: 8f55 or a4,a4,a3 - c4e: cb98 sw a4,16(a5) - c50: fef619e3 bne a2,a5,c42 <.L211> - c54: bad5 j 648 <.L352> - -00000c56 <.L186>: - c56: 40978633 sub a2,a5,s1 - -00000c5a <.LVL378>: - c5a: 40868333 sub t1,a3,s0 - c5e: 00c7b2b3 sltu t0,a5,a2 - c62: 0066b5b3 sltu a1,a3,t1 - c66: 40530333 sub t1,t1,t0 - c6a: ce1a sw t1,28(sp) - c6c: 00773333 sltu t1,a4,t2 - c70: d22e sw a1,36(sp) - -00000c72 <.LVL379>: - c72: d01a sw t1,32(sp) - c74: 407702b3 sub t0,a4,t2 - c78: 00c7fa63 bgeu a5,a2,c8c <.L216> - c7c: 00869863 bne a3,s0,c8c <.L216> - -00000c80 <.LVL380>: - c80: fff28593 add a1,t0,-1 - -00000c84 <.L217>: - c84: 0012b313 seqz t1,t0 - c88: d01a sw t1,32(sp) - c8a: a039 j c98 <.L218> - -00000c8c <.L216>: - c8c: 5312 lw t1,36(sp) - c8e: d002 sw zero,32(sp) - c90: 40b285b3 sub a1,t0,a1 - -00000c94 <.LVL383>: - c94: fe0318e3 bnez t1,c84 <.L217> - -00000c98 <.L218>: - c98: 4282 lw t0,0(sp) - c9a: 4342 lw t1,16(sp) - c9c: c8ae sw a1,80(sp) - c9e: c4b2 sw a2,72(sp) - ca0: 40530333 sub t1,t1,t0 - ca4: 5282 lw t0,32(sp) - ca6: d21a sw t1,36(sp) - ca8: 00773333 sltu t1,a4,t2 - cac: 0062e333 or t1,t0,t1 - cb0: 5292 lw t0,36(sp) - cb2: 406282b3 sub t0,t0,t1 - cb6: 4372 lw t1,28(sp) - cb8: ca96 sw t0,84(sp) - cba: c69a sw t1,76(sp) - -00000cbc <.LBE104>: - cbc: 00080337 lui t1,0x80 - cc0: 0062f333 and t1,t0,t1 - cc4: 12030463 beqz t1,dec <.L219> - -00000cc8 <.LBB105>: - cc8: 40d40633 sub a2,s0,a3 - -00000ccc <.LVL386>: - ccc: 40f487b3 sub a5,s1,a5 - -00000cd0 <.LVL387>: - cd0: 00c432b3 sltu t0,s0,a2 - -00000cd4 <.LVL388>: - cd4: 00f4b5b3 sltu a1,s1,a5 - -00000cd8 <.LVL389>: - cd8: 8e0d sub a2,a2,a1 - -00000cda <.LVL390>: - cda: 8096 mv ra,t0 - -00000cdc <.LVL391>: - cdc: 40e385b3 sub a1,t2,a4 - ce0: 00e3b333 sltu t1,t2,a4 - ce4: 00f4fa63 bgeu s1,a5,cf8 <.L224> - ce8: 00869863 bne a3,s0,cf8 <.L224> - -00000cec <.LVL392>: - cec: 15fd add a1,a1,-1 - -00000cee <.L225>: - cee: 40770733 sub a4,a4,t2 - cf2: 00173513 seqz a0,a4 - cf6: a029 j d00 <.L226> - -00000cf8 <.L224>: - cf8: 401585b3 sub a1,a1,ra - -00000cfc <.LVL395>: - cfc: fe0299e3 bnez t0,cee <.L225> - -00000d00 <.L226>: - d00: 4702 lw a4,0(sp) - d02: 46c2 lw a3,16(sp) - d04: c4be sw a5,72(sp) - -00000d06 <.LBE105>: - d06: 47d2 lw a5,20(sp) - -00000d08 <.LBB106>: - d08: 8f15 sub a4,a4,a3 - d0a: 00656333 or t1,a0,t1 - -00000d0e <.LVL399>: - d0e: 40670333 sub t1,a4,t1 - -00000d12 <.LVL400>: - d12: ca9a sw t1,84(sp) - d14: c8ae sw a1,80(sp) - -00000d16 <.LVL401>: - d16: c6b2 sw a2,76(sp) - -00000d18 <.LBE106>: - d18: c63e sw a5,12(sp) - -00000d1a <.L227>: - d1a: 4556 lw a0,84(sp) - d1c: c165 beqz a0,dfc <.L228> - d1e: 00000097 auipc ra,0x0 - d22: 000080e7 jalr ra # d1e <.L227+0x4> - -00000d26 <.L229>: - d26: 1551 add a0,a0,-12 - -00000d28 <.LBB60>: - d28: 41f55793 sra a5,a0,0x1f - d2c: 8bfd and a5,a5,31 - d2e: 97aa add a5,a5,a0 - d30: 8795 sra a5,a5,0x5 - -00000d32 <.LVL406>: - d32: 01f57593 and a1,a0,31 - d36: 40f00733 neg a4,a5 - d3a: c9fd beqz a1,e30 <.L232> - d3c: 800006b7 lui a3,0x80000 - d40: 06fd add a3,a3,31 # 8000001f <.LLST158+0x7fffd6a7> - d42: 8ee9 and a3,a3,a0 - d44: 0006d663 bgez a3,d50 <.L233> - d48: 16fd add a3,a3,-1 - d4a: fe06e693 or a3,a3,-32 - d4e: 0685 add a3,a3,1 - -00000d50 <.L233>: - d50: 070a sll a4,a4,0x2 - d52: 02000313 li t1,32 - d56: 40d30333 sub t1,t1,a3 - d5a: 04810393 add t2,sp,72 - d5e: 00c70693 add a3,a4,12 - d62: 969e add a3,a3,t2 - d64: 40e00733 neg a4,a4 - -00000d68 <.L234>: - d68: 0ed39263 bne t2,a3,e4c <.L237> - d6c: fff78713 add a4,a5,-1 - -00000d70 <.LVL407>: - d70: 078a sll a5,a5,0x2 - -00000d72 <.LVL408>: - d72: 1034 add a3,sp,40 - d74: 04c78793 add a5,a5,76 - d78: 97b6 add a5,a5,a3 - d7a: 46a6 lw a3,72(sp) - d7c: 00b696b3 sll a3,a3,a1 - d80: fcd7aa23 sw a3,-44(a5) - -00000d84 <.L238>: - d84: 0705 add a4,a4,1 - d86: 00b4 add a3,sp,72 - d88: 070a sll a4,a4,0x2 - d8a: 4621 li a2,8 - d8c: 87b6 mv a5,a3 - d8e: 00c76863 bltu a4,a2,d9e <.L239> - d92: 0006a023 sw zero,0(a3) - d96: 0006a223 sw zero,4(a3) - d9a: 1761 add a4,a4,-8 - d9c: 0894 add a3,sp,80 - -00000d9e <.L239>: - d9e: 4611 li a2,4 - da0: 00c76463 bltu a4,a2,da8 <.L240> - da4: 0006a023 sw zero,0(a3) - -00000da8 <.L240>: - da8: 4712 lw a4,4(sp) - daa: 14e54f63 blt a0,a4,f08 <.L241> - dae: 8d19 sub a0,a0,a4 - -00000db0 <.LVL410>: - db0: 0505 add a0,a0,1 - -00000db2 <.LBB61>: - db2: 40555313 sra t1,a0,0x5 - -00000db6 <.LVL412>: - db6: 85be mv a1,a5 - db8: 897d and a0,a0,31 - -00000dba <.LVL413>: - dba: 86be mv a3,a5 - dbc: 4601 li a2,0 - dbe: 4701 li a4,0 - -00000dc0 <.L242>: - dc0: 0a671463 bne a4,t1,e68 <.L243> - dc4: 470d li a4,3 - -00000dc6 <.LVL415>: - dc6: 40670733 sub a4,a4,t1 - dca: 00231693 sll a3,t1,0x2 - dce: e545 bnez a0,e76 <.L244> - -00000dd0 <.L245>: - dd0: 00d582b3 add t0,a1,a3 - dd4: 0002a283 lw t0,0(t0) - dd8: 0505 add a0,a0,1 - -00000dda <.LVL417>: - dda: 0055a023 sw t0,0(a1) - -00000dde <.LVL418>: - dde: 0591 add a1,a1,4 - de0: fea758e3 bge a4,a0,dd0 <.L245> - de4: 4691 li a3,4 - de6: 406686b3 sub a3,a3,t1 - dea: a0f1 j eb6 <.L249> - -00000dec <.L219>: - dec: 47f2 lw a5,28(sp) - dee: 8e5d or a2,a2,a5 - -00000df0 <.LVL420>: - df0: 8e4d or a2,a2,a1 - df2: 00566633 or a2,a2,t0 - df6: de0609e3 beqz a2,be8 <.L357> - dfa: b705 j d1a <.L227> - -00000dfc <.L228>: - dfc: 4546 lw a0,80(sp) - dfe: c901 beqz a0,e0e <.L230> - e00: 00000097 auipc ra,0x0 - e04: 000080e7 jalr ra # e00 <.L228+0x4> - -00000e08 <.LVL422>: - e08: 02050513 add a0,a0,32 - e0c: bf29 j d26 <.L229> - -00000e0e <.L230>: - e0e: 4536 lw a0,76(sp) - e10: c901 beqz a0,e20 <.L231> - e12: 00000097 auipc ra,0x0 - e16: 000080e7 jalr ra # e12 <.L230+0x4> - -00000e1a <.LVL425>: - e1a: 04050513 add a0,a0,64 - e1e: b721 j d26 <.L229> - -00000e20 <.L231>: - e20: 4526 lw a0,72(sp) - e22: 00000097 auipc ra,0x0 - e26: 000080e7 jalr ra # e22 <.L231+0x2> - -00000e2a <.LVL428>: - e2a: 06050513 add a0,a0,96 - e2e: bde5 j d26 <.L229> - -00000e30 <.L232>: - e30: 08d4 add a3,sp,84 - e32: 070a sll a4,a4,0x2 - -00000e34 <.LBB66>: - e34: 460d li a2,3 - -00000e36 <.L235>: - e36: 00e685b3 add a1,a3,a4 - e3a: 418c lw a1,0(a1) - e3c: 167d add a2,a2,-1 - -00000e3e <.LVL432>: - e3e: 16f1 add a3,a3,-4 - e40: c2cc sw a1,4(a3) - -00000e42 <.LVL433>: - e42: fef65ae3 bge a2,a5,e36 <.L235> - e46: fff78713 add a4,a5,-1 - e4a: bf2d j d84 <.L238> - -00000e4c <.L237>: - e4c: 4290 lw a2,0(a3) - e4e: ffc6a283 lw t0,-4(a3) - e52: 00e68433 add s0,a3,a4 - e56: 00b61633 sll a2,a2,a1 - e5a: 0062d2b3 srl t0,t0,t1 - e5e: 00566633 or a2,a2,t0 - e62: c010 sw a2,0(s0) - e64: 16f1 add a3,a3,-4 - e66: b709 j d68 <.L234> - -00000e68 <.L243>: - e68: 0006a283 lw t0,0(a3) - e6c: 0705 add a4,a4,1 - -00000e6e <.LVL436>: - e6e: 0691 add a3,a3,4 - e70: 00566633 or a2,a2,t0 - -00000e74 <.LVL437>: - e74: b7b1 j dc0 <.L242> - -00000e76 <.L244>: - e76: 04c68413 add s0,a3,76 - e7a: 1024 add s1,sp,40 - e7c: 009402b3 add t0,s0,s1 - e80: fd42a283 lw t0,-44(t0) - e84: 02000393 li t2,32 - e88: 40a383b3 sub t2,t2,a0 - e8c: 007292b3 sll t0,t0,t2 - e90: 00566633 or a2,a2,t0 - -00000e94 <.LVL439>: - e94: 96be add a3,a3,a5 - e96: 4401 li s0,0 - -00000e98 <.L247>: - e98: 04e44963 blt s0,a4,eea <.L248> - e9c: 070a sll a4,a4,0x2 - e9e: 102c add a1,sp,40 - ea0: 04c70713 add a4,a4,76 - ea4: 972e add a4,a4,a1 - ea6: 45d6 lw a1,84(sp) - ea8: 4691 li a3,4 - eaa: 406686b3 sub a3,a3,t1 - -00000eae <.LVL441>: - eae: 00a5d5b3 srl a1,a1,a0 - eb2: fcb72a23 sw a1,-44(a4) - -00000eb6 <.L249>: - eb6: 4711 li a4,4 - eb8: 8f15 sub a4,a4,a3 - eba: 068a sll a3,a3,0x2 - ebc: 97b6 add a5,a5,a3 - ebe: 070a sll a4,a4,0x2 - ec0: 46a1 li a3,8 - ec2: 00d76863 bltu a4,a3,ed2 <.L250> - ec6: 0007a023 sw zero,0(a5) - eca: 0007a223 sw zero,4(a5) - ece: 1761 add a4,a4,-8 - ed0: 07a1 add a5,a5,8 - -00000ed2 <.L250>: - ed2: 4691 li a3,4 - ed4: 00d76463 bltu a4,a3,edc <.L251> - ed8: 0007a023 sw zero,0(a5) - -00000edc <.L251>: - edc: 47a6 lw a5,72(sp) - -00000ede <.LBB64>: - ede: 00c03633 snez a2,a2 - -00000ee2 <.LBE64>: - ee2: 8fd1 or a5,a5,a2 - ee4: c4be sw a5,72(sp) - -00000ee6 <.LBB181>: - ee6: ecaff06f j 5b0 <.L354> - -00000eea <.L248>: - eea: 0006a283 lw t0,0(a3) - eee: 42c4 lw s1,4(a3) - ef0: 0405 add s0,s0,1 - -00000ef2 <.LVL447>: - ef2: 00a2d2b3 srl t0,t0,a0 - ef6: 007494b3 sll s1,s1,t2 - efa: 0092e2b3 or t0,t0,s1 - efe: 0055a023 sw t0,0(a1) - -00000f02 <.LVL448>: - f02: 0691 add a3,a3,4 - f04: 0591 add a1,a1,4 - f06: bf49 j e98 <.L247> - -00000f08 <.L241>: - f08: 4792 lw a5,4(sp) - f0a: fff80737 lui a4,0xfff80 - f0e: 177d add a4,a4,-1 # fff7ffff <.LLST158+0xfff7d687> - f10: 40a78533 sub a0,a5,a0 - -00000f14 <.LVL450>: - f14: 47d6 lw a5,84(sp) - f16: 8ff9 and a5,a5,a4 - f18: cc8ff06f j 3e0 <.L355> - -00000f1c <.L258>: - f1c: ca82 sw zero,84(sp) - f1e: c882 sw zero,80(sp) - f20: c682 sw zero,76(sp) - f22: c482 sw zero,72(sp) - f24: a88ff06f j 1ac <.L257> - -00000f28 <.L21>: - f28: 07400613 li a2,116 - f2c: b0d65763 bge a2,a3,23a <.L262> - -00000f30 <.L23>: - f30: c282 sw zero,68(sp) - f32: c082 sw zero,64(sp) - f34: de02 sw zero,60(sp) - f36: 4485 li s1,1 - f38: bbaff06f j 2f2 <.L34> - -00000f3c <.L59>: - f3c: 07400793 li a5,116 - f40: d0d7d563 bge a5,a3,44a <.L263> - -00000f44 <.L61>: - f44: da02 sw zero,52(sp) - f46: d802 sw zero,48(sp) - f48: d602 sw zero,44(sp) - f4a: 4405 li s0,1 - f4c: ddaff06f j 526 <.L74> - -00000f50 <.L163>: - f50: 07400793 li a5,116 - f54: a2b7d1e3 bge a5,a1,976 <.L265> - -00000f58 <.L165>: - f58: da02 sw zero,52(sp) - f5a: d802 sw zero,48(sp) - f5c: d602 sw zero,44(sp) - f5e: 4705 li a4,1 - f60: bcdd j a56 <.L178> - -divtf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divtf3>: - 0: 4218 lw a4,0(a2) - 2: f6410113 add sp,sp,-156 - 6: 41dc lw a5,4(a1) - 8: c43a sw a4,8(sp) - a: 4618 lw a4,8(a2) - c: 4594 lw a3,8(a1) - e: cc2a sw a0,24(sp) - 10: c23a sw a4,4(sp) - 12: 4658 lw a4,12(a2) - 14: 4188 lw a0,0(a1) - 16: 45cc lw a1,12(a1) - 18: c63a sw a4,12(sp) - 1a: 08310713 add a4,sp,131 - 1e: 9b41 and a4,a4,-16 - 20: cb22 sw s0,148(sp) - 22: c926 sw s1,144(sp) - 24: cd06 sw ra,152(sp) - -00000026 <.LBB3>: - 26: c74c sw a1,12(a4) - -00000028 <.LBE3>: - 28: 4244 lw s1,4(a2) - 2a: c03a sw a4,0(sp) - -0000002c <.LBB4>: - 2c: c308 sw a0,0(a4) - 2e: c35c sw a5,4(a4) - 30: c714 sw a3,8(a4) - 32: 6621 lui a2,0x8 - 34: 01059713 sll a4,a1,0x10 - 38: 0105d413 srl s0,a1,0x10 - 3c: 8341 srl a4,a4,0x10 - 3e: 167d add a2,a2,-1 # 7fff <.LLST129+0x67e9> - 40: 81fd srl a1,a1,0x1f - 42: da2a sw a0,52(sp) - 44: dc3e sw a5,56(sp) - 46: de36 sw a3,60(sp) - 48: c0ba sw a4,64(sp) - 4a: 8c71 and s0,s0,a2 - -0000004c <.LVL2>: - 4c: c82e sw a1,16(sp) - -0000004e <.LBE4>: - 4e: cc5d beqz s0,10c <.L2> - 50: 1ac40f63 beq s0,a2,20e <.L3> - 54: 67c1 lui a5,0x10 - 56: 8fd9 or a5,a5,a4 - 58: c0be sw a5,64(sp) - -0000005a <.LBB5>: - 5a: 1030 add a2,sp,40 - 5c: 185c add a5,sp,52 - -0000005e <.L4>: - 5e: 47d8 lw a4,12(a5) - 60: 4794 lw a3,8(a5) - 62: 17f1 add a5,a5,-4 # fffc <.LLST129+0xe7e6> - 64: 070e sll a4,a4,0x3 - 66: 82f5 srl a3,a3,0x1d - 68: 8f55 or a4,a4,a3 - 6a: cb98 sw a4,16(a5) - 6c: fef619e3 bne a2,a5,5e <.L4> - -00000070 <.LVL6>: - 70: 57d2 lw a5,52(sp) - 72: 078e sll a5,a5,0x3 - 74: da3e sw a5,52(sp) - -00000076 <.LBE5>: - 76: 77f1 lui a5,0xffffc - 78: 0785 add a5,a5,1 # ffffc001 <.LLST129+0xffffa7eb> - 7a: 943e add s0,s0,a5 - -0000007c <.L199>: - 7c: 4701 li a4,0 - -0000007e <.L5>: - 7e: 4782 lw a5,0(sp) - 80: 46a2 lw a3,8(sp) - 82: 4632 lw a2,12(sp) - 84: c3c4 sw s1,4(a5) - 86: c394 sw a3,0(a5) - 88: 4692 lw a3,4(sp) - 8a: 00c15503 lhu a0,12(sp) - 8e: 827d srl a2,a2,0x1f - 90: c794 sw a3,8(a5) - 92: 46b2 lw a3,12(sp) - 94: c4a6 sw s1,72(sp) - 96: c8aa sw a0,80(sp) - 98: c7d4 sw a3,12(a5) - 9a: 47a2 lw a5,8(sp) - 9c: c632 sw a2,12(sp) - 9e: c2be sw a5,68(sp) - a0: 4792 lw a5,4(sp) - a2: c6be sw a5,76(sp) - a4: 0106d793 srl a5,a3,0x10 - a8: 66a1 lui a3,0x8 - aa: 16fd add a3,a3,-1 # 7fff <.LLST129+0x67e9> - ac: 8ff5 and a5,a5,a3 - -000000ae <.LBE11>: - ae: 16078b63 beqz a5,224 <.L18> - b2: 28d78663 beq a5,a3,33e <.L19> - b6: 66c1 lui a3,0x10 - b8: 8ec9 or a3,a3,a0 - ba: c8b6 sw a3,80(sp) - -000000bc <.LBB12>: - bc: 1828 add a0,sp,56 - be: 00d4 add a3,sp,68 - -000000c0 <.L20>: - c0: 46d0 lw a2,12(a3) - c2: 468c lw a1,8(a3) - c4: 16f1 add a3,a3,-4 # fffc <.LLST129+0xe7e6> - c6: 060e sll a2,a2,0x3 - c8: 81f5 srl a1,a1,0x1d - ca: 8e4d or a2,a2,a1 - cc: ca90 sw a2,16(a3) - ce: fed519e3 bne a0,a3,c0 <.L20> - -000000d2 <.LVL12>: - d2: 4696 lw a3,68(sp) - d4: 068e sll a3,a3,0x3 - d6: c2b6 sw a3,68(sp) - -000000d8 <.LBE12>: - d8: 76f1 lui a3,0xffffc - da: 0685 add a3,a3,1 # ffffc001 <.LLST129+0xffffa7eb> - dc: 97b6 add a5,a5,a3 - -000000de <.L201>: - de: 4681 li a3,0 - -000000e0 <.L21>: - e0: 4642 lw a2,16(sp) - e2: 45b2 lw a1,12(sp) - e4: 40f407b3 sub a5,s0,a5 - -000000e8 <.LVL15>: - e8: d43e sw a5,40(sp) - ea: 00271793 sll a5,a4,0x2 - ee: 8e2d xor a2,a2,a1 - f0: 8fd5 or a5,a5,a3 - f2: ce32 sw a2,28(sp) - -000000f4 <.LVL16>: - f4: 17fd add a5,a5,-1 - f6: 4639 li a2,14 - -000000f8 <.LVL17>: - f8: 26f66063 bltu a2,a5,358 <.L34> - fc: 00000637 lui a2,0x0 - 100: 078a sll a5,a5,0x2 - 102: 00060613 mv a2,a2 - 106: 97b2 add a5,a5,a2 - 108: 439c lw a5,0(a5) - 10a: 8782 jr a5 - -0000010c <.L2>: - 10c: 00a7e633 or a2,a5,a0 - 110: 8e55 or a2,a2,a3 - 112: 8e59 or a2,a2,a4 - 114: 10060563 beqz a2,21e <.L153> - -00000118 <.LBB18>: - 118: c729 beqz a4,162 <.L6> - 11a: 853a mv a0,a4 - 11c: 00000097 auipc ra,0x0 - 120: 000080e7 jalr ra # 11c <.LBB18+0x4> - -00000124 <.LBB7>: - 124: ff450713 add a4,a0,-12 - -00000128 <.LVL20>: - 128: 02000613 li a2,32 - 12c: 8e19 sub a2,a2,a4 - -0000012e <.LVL21>: - 12e: 4781 li a5,0 - -00000130 <.L7>: - 130: 40f005b3 neg a1,a5 - 134: 058a sll a1,a1,0x2 - 136: 03410293 add t0,sp,52 - 13a: 00c58693 add a3,a1,12 - 13e: 9696 add a3,a3,t0 - 140: 40b00433 neg s0,a1 - -00000144 <.L12>: - 144: 0ad29663 bne t0,a3,1f0 <.L15> - 148: fff78693 add a3,a5,-1 - -0000014c <.LVL24>: - 14c: 078a sll a5,a5,0x2 - 14e: 1850 add a2,sp,52 - -00000150 <.LVL25>: - 150: 05c78793 add a5,a5,92 - 154: 97b2 add a5,a5,a2 - 156: 5652 lw a2,52(sp) - 158: 00e61733 sll a4,a2,a4 - -0000015c <.LVL26>: - 15c: fae7a223 sw a4,-92(a5) - 160: a095 j 1c4 <.L14> - -00000162 <.L6>: - 162: c295 beqz a3,186 <.L8> - 164: 8536 mv a0,a3 - 166: 00000097 auipc ra,0x0 - 16a: 000080e7 jalr ra # 166 <.L6+0x4> - -0000016e <.LVL28>: - 16e: 02050513 add a0,a0,32 - -00000172 <.L9>: - 172: ff450713 add a4,a0,-12 - 176: 40575793 sra a5,a4,0x5 - -0000017a <.LVL30>: - 17a: 8b7d and a4,a4,31 - -0000017c <.LVL31>: - 17c: c70d beqz a4,1a6 <.L11> - 17e: 02000613 li a2,32 - 182: 8e19 sub a2,a2,a4 - -00000184 <.LVL32>: - 184: b775 j 130 <.L7> - -00000186 <.L8>: - 186: cb89 beqz a5,198 <.L10> - 188: 853e mv a0,a5 - 18a: 00000097 auipc ra,0x0 - 18e: 000080e7 jalr ra # 18a <.L8+0x4> - -00000192 <.LVL34>: - 192: 04050513 add a0,a0,64 - 196: bff1 j 172 <.L9> - -00000198 <.L10>: - 198: 00000097 auipc ra,0x0 - 19c: 000080e7 jalr ra # 198 <.L10> - -000001a0 <.LVL37>: - 1a0: 06050513 add a0,a0,96 - 1a4: b7f9 j 172 <.L9> - -000001a6 <.L11>: - 1a6: 40f00633 neg a2,a5 - 1aa: 0098 add a4,sp,64 - -000001ac <.LVL40>: - 1ac: 060a sll a2,a2,0x2 - -000001ae <.LBB9>: - 1ae: 468d li a3,3 - -000001b0 <.L13>: - 1b0: 00c705b3 add a1,a4,a2 - 1b4: 418c lw a1,0(a1) - 1b6: 16fd add a3,a3,-1 - -000001b8 <.LVL42>: - 1b8: 1771 add a4,a4,-4 - 1ba: c34c sw a1,4(a4) - -000001bc <.LVL43>: - 1bc: fef6dae3 bge a3,a5,1b0 <.L13> - 1c0: fff78693 add a3,a5,-1 - -000001c4 <.L14>: - 1c4: 00168793 add a5,a3,1 - 1c8: 078a sll a5,a5,0x2 - 1ca: 46a1 li a3,8 - 1cc: 1858 add a4,sp,52 - 1ce: 00d7e863 bltu a5,a3,1de <.L16> - 1d2: 00072023 sw zero,0(a4) - 1d6: 00072223 sw zero,4(a4) - 1da: 17e1 add a5,a5,-8 - 1dc: 1878 add a4,sp,60 - -000001de <.L16>: - 1de: 4691 li a3,4 - 1e0: 00d7e463 bltu a5,a3,1e8 <.L17> - 1e4: 00072023 sw zero,0(a4) - -000001e8 <.L17>: - 1e8: 7471 lui s0,0xffffc - 1ea: 0445 add s0,s0,17 # ffffc011 <.LLST129+0xffffa7fb> - 1ec: 8c09 sub s0,s0,a0 - 1ee: b579 j 7c <.L199> - -000001f0 <.L15>: - 1f0: 428c lw a1,0(a3) - 1f2: ffc6a303 lw t1,-4(a3) - 1f6: 008683b3 add t2,a3,s0 - 1fa: 00e595b3 sll a1,a1,a4 - 1fe: 00c35333 srl t1,t1,a2 - 202: 0065e5b3 or a1,a1,t1 - 206: 00b3a023 sw a1,0(t2) - 20a: 16f1 add a3,a3,-4 - 20c: bf25 j 144 <.L12> - -0000020e <.L3>: - 20e: 8fc9 or a5,a5,a0 - 210: 8fd5 or a5,a5,a3 - 212: 8fd9 or a5,a5,a4 - 214: 4709 li a4,2 - 216: e60784e3 beqz a5,7e <.L5> - 21a: 470d li a4,3 - 21c: b58d j 7e <.L5> - -0000021e <.L153>: - 21e: 4401 li s0,0 - -00000220 <.LBE19>: - 220: 4705 li a4,1 - 222: bdb1 j 7e <.L5> - -00000224 <.L18>: - 224: 47a2 lw a5,8(sp) - -00000226 <.LVL49>: - 226: 4692 lw a3,4(sp) - -00000228 <.LVL50>: - 228: 8fc5 or a5,a5,s1 - 22a: 8fd5 or a5,a5,a3 - 22c: 8fc9 or a5,a5,a0 - 22e: 12078263 beqz a5,352 <.L155> - -00000232 <.LBB20>: - 232: c539 beqz a0,280 <.L22> - 234: c23a sw a4,4(sp) - 236: 00000097 auipc ra,0x0 - 23a: 000080e7 jalr ra # 236 <.LBB20+0x4> - -0000023e <.LBB14>: - 23e: 4712 lw a4,4(sp) - 240: ff450693 add a3,a0,-12 - -00000244 <.LVL52>: - 244: 02000593 li a1,32 - 248: 8d95 sub a1,a1,a3 - -0000024a <.LVL53>: - 24a: 4781 li a5,0 - -0000024c <.L23>: - 24c: 40f00333 neg t1,a5 - 250: 030a sll t1,t1,0x2 - 252: 04410393 add t2,sp,68 - 256: 00c30613 add a2,t1,12 - 25a: 406004b3 neg s1,t1 - 25e: 961e add a2,a2,t2 - 260: c226 sw s1,4(sp) - -00000262 <.L28>: - 262: 0ac39e63 bne t2,a2,31e <.L31> - 266: fff78613 add a2,a5,-1 - -0000026a <.LVL55>: - 26a: 078a sll a5,a5,0x2 - 26c: 184c add a1,sp,52 - -0000026e <.LVL56>: - 26e: 05c78793 add a5,a5,92 - 272: 97ae add a5,a5,a1 - 274: 4596 lw a1,68(sp) - 276: 00d596b3 sll a3,a1,a3 - -0000027a <.LVL57>: - 27a: fad7aa23 sw a3,-76(a5) - 27e: a895 j 2f2 <.L30> - -00000280 <.L22>: - 280: 4792 lw a5,4(sp) - 282: c785 beqz a5,2aa <.L24> - 284: 853e mv a0,a5 - 286: c43a sw a4,8(sp) - 288: 00000097 auipc ra,0x0 - 28c: 000080e7 jalr ra # 288 <.L22+0x8> - -00000290 <.LVL59>: - 290: 4722 lw a4,8(sp) - 292: 02050513 add a0,a0,32 - -00000296 <.L25>: - 296: ff450693 add a3,a0,-12 - 29a: 4056d793 sra a5,a3,0x5 - -0000029e <.LVL61>: - 29e: 8afd and a3,a3,31 - -000002a0 <.LVL62>: - 2a0: ca85 beqz a3,2d0 <.L27> - 2a2: 02000593 li a1,32 - 2a6: 8d95 sub a1,a1,a3 - -000002a8 <.LVL63>: - 2a8: b755 j 24c <.L23> - -000002aa <.L24>: - 2aa: c23a sw a4,4(sp) - 2ac: c891 beqz s1,2c0 <.L26> - 2ae: 8526 mv a0,s1 - 2b0: 00000097 auipc ra,0x0 - 2b4: 000080e7 jalr ra # 2b0 <.L24+0x6> - -000002b8 <.LVL65>: - 2b8: 04050513 add a0,a0,64 - -000002bc <.L200>: - 2bc: 4712 lw a4,4(sp) - -000002be <.LVL67>: - 2be: bfe1 j 296 <.L25> - -000002c0 <.L26>: - 2c0: 4522 lw a0,8(sp) - 2c2: 00000097 auipc ra,0x0 - 2c6: 000080e7 jalr ra # 2c2 <.L26+0x2> - -000002ca <.LVL69>: - 2ca: 06050513 add a0,a0,96 - -000002ce <.LVL70>: - 2ce: b7fd j 2bc <.L200> - -000002d0 <.L27>: - 2d0: 40f005b3 neg a1,a5 - 2d4: 0894 add a3,sp,80 - -000002d6 <.LVL72>: - 2d6: 058a sll a1,a1,0x2 - -000002d8 <.LBB16>: - 2d8: 460d li a2,3 - -000002da <.L29>: - 2da: 00b68333 add t1,a3,a1 - 2de: 00032303 lw t1,0(t1) - 2e2: 167d add a2,a2,-1 # ffffffff <.LLST129+0xffffe7e9> - -000002e4 <.LVL74>: - 2e4: 16f1 add a3,a3,-4 - 2e6: 0066a223 sw t1,4(a3) - -000002ea <.LVL75>: - 2ea: fef658e3 bge a2,a5,2da <.L29> - 2ee: fff78613 add a2,a5,-1 - -000002f2 <.L30>: - 2f2: 00160793 add a5,a2,1 - 2f6: 078a sll a5,a5,0x2 - 2f8: 4621 li a2,8 - 2fa: 00d4 add a3,sp,68 - 2fc: 00c7e863 bltu a5,a2,30c <.L32> - 300: 0006a023 sw zero,0(a3) - 304: 0006a223 sw zero,4(a3) - 308: 17e1 add a5,a5,-8 - 30a: 00f4 add a3,sp,76 - -0000030c <.L32>: - 30c: 4611 li a2,4 - 30e: 00c7e463 bltu a5,a2,316 <.L33> - 312: 0006a023 sw zero,0(a3) - -00000316 <.L33>: - 316: 77f1 lui a5,0xffffc - 318: 07c5 add a5,a5,17 # ffffc011 <.LLST129+0xffffa7fb> - 31a: 8f89 sub a5,a5,a0 - 31c: b3c9 j de <.L201> - -0000031e <.L31>: - 31e: 00062303 lw t1,0(a2) - 322: ffc62283 lw t0,-4(a2) - 326: 4492 lw s1,4(sp) - 328: 00d31333 sll t1,t1,a3 - 32c: 00b2d2b3 srl t0,t0,a1 - 330: 94b2 add s1,s1,a2 - 332: 00536333 or t1,t1,t0 - 336: 0064a023 sw t1,0(s1) - 33a: 1671 add a2,a2,-4 - 33c: b71d j 262 <.L28> - -0000033e <.L19>: - 33e: 46a2 lw a3,8(sp) - 340: 8cd5 or s1,s1,a3 - 342: 4692 lw a3,4(sp) - 344: 8cd5 or s1,s1,a3 - 346: 8cc9 or s1,s1,a0 - 348: 4689 li a3,2 - 34a: d8048be3 beqz s1,e0 <.L21> - 34e: 468d li a3,3 - 350: bb41 j e0 <.L21> - -00000352 <.L155>: - 352: 4781 li a5,0 - -00000354 <.LBE21>: - 354: 4685 li a3,1 - 356: b369 j e0 <.L21> - -00000358 <.L34>: - 358: 4686 lw a3,64(sp) - -0000035a <.LVL81>: - 35a: 4746 lw a4,80(sp) - 35c: d882 sw zero,112(sp) - 35e: d682 sw zero,108(sp) - 360: d482 sw zero,104(sp) - 362: d282 sw zero,100(sp) - 364: 47b6 lw a5,76(sp) - 366: 02d76363 bltu a4,a3,38c <.L41> - 36a: 0ae69f63 bne a3,a4,428 <.L42> - 36e: 5772 lw a4,60(sp) - 370: 00e7ee63 bltu a5,a4,38c <.L41> - 374: 0af71a63 bne a4,a5,428 <.L42> - 378: 5762 lw a4,56(sp) - 37a: 47a6 lw a5,72(sp) - 37c: 00e7e863 bltu a5,a4,38c <.L41> - 380: 0af71463 bne a4,a5,428 <.L42> - 384: 5752 lw a4,52(sp) - 386: 4796 lw a5,68(sp) - 388: 0af76063 bltu a4,a5,428 <.L42> - -0000038c <.L41>: - 38c: 57d2 lw a5,52(sp) - 38e: 0090 add a2,sp,64 - 390: 07fe sll a5,a5,0x1f - 392: d8be sw a5,112(sp) - -00000394 <.LBB23>: - 394: 185c add a5,sp,52 - -00000396 <.L43>: - 396: 4398 lw a4,0(a5) - 398: 43d4 lw a3,4(a5) - 39a: 8305 srl a4,a4,0x1 - 39c: 06fe sll a3,a3,0x1f - 39e: 8f55 or a4,a4,a3 - 3a0: c398 sw a4,0(a5) - 3a2: 0791 add a5,a5,4 - 3a4: fef619e3 bne a2,a5,396 <.L43> - -000003a8 <.LVL84>: - 3a8: 4786 lw a5,64(sp) - 3aa: 8385 srl a5,a5,0x1 - 3ac: c0be sw a5,64(sp) - -000003ae <.L44>: - 3ae: 00dc add a5,sp,68 - 3b0: 1830 add a2,sp,56 - -000003b2 <.L45>: - 3b2: 47d8 lw a4,12(a5) - 3b4: 4794 lw a3,8(a5) - 3b6: 17f1 add a5,a5,-4 - 3b8: 0732 sll a4,a4,0xc - 3ba: 82d1 srl a3,a3,0x14 - 3bc: 8f55 or a4,a4,a3 - 3be: cb98 sw a4,16(a5) - 3c0: fef619e3 bne a2,a5,3b2 <.L45> - -000003c4 <.LVL87>: - 3c4: 4796 lw a5,68(sp) - 3c6: 07b2 sll a5,a5,0xc - 3c8: c2be sw a5,68(sp) - 3ca: 08dc add a5,sp,84 - 3cc: c23e sw a5,4(sp) - 3ce: 10dc add a5,sp,100 - 3d0: d63e sw a5,44(sp) - -000003d2 <.LBE24>: - 3d2: 478d li a5,3 - 3d4: d23e sw a5,36(sp) - -000003d6 <.L120>: - 3d6: 4786 lw a5,64(sp) - 3d8: 44c6 lw s1,80(sp) - 3da: 10979f63 bne a5,s1,4f8 <.L46> - 3de: 4792 lw a5,4(sp) - 3e0: 577d li a4,-1 - 3e2: c7d8 sw a4,12(a5) - 3e4: 5792 lw a5,36(sp) - 3e6: 4c078363 beqz a5,8ac <.L121> - -000003ea <.LBB25>: - 3ea: 57b2 lw a5,44(sp) - 3ec: 4316 lw t1,68(sp) - 3ee: 5552 lw a0,52(sp) - 3f0: 47d8 lw a4,12(a5) - -000003f2 <.LVL89>: - 3f2: 4626 lw a2,72(sp) - 3f4: 40a303b3 sub t2,t1,a0 - 3f8: 00e037b3 snez a5,a4 - 3fc: c43e sw a5,8(sp) - -000003fe <.LVL90>: - 3fe: 57e2 lw a5,56(sp) - -00000400 <.LVL91>: - 400: 007335b3 sltu a1,t1,t2 - 404: c62e sw a1,12(sp) - -00000406 <.LVL92>: - 406: 40f602b3 sub t0,a2,a5 - 40a: 00b036b3 snez a3,a1 - -0000040e <.LVL93>: - 40e: 00563433 sltu s0,a2,t0 - 412: cf19 beqz a4,430 <.L52> - 414: 00a31e63 bne t1,a0,430 <.L52> - -00000418 <.LVL94>: - 418: 12fd add t0,t0,-1 - -0000041a <.L53>: - 41a: 40c786b3 sub a3,a5,a2 - 41e: 4585 li a1,1 - 420: 0016b693 seqz a3,a3 - 424: c62e sw a1,12(sp) - 426: a809 j 438 <.L54> - -00000428 <.L42>: - 428: 57a2 lw a5,40(sp) - 42a: 17fd add a5,a5,-1 - 42c: d43e sw a5,40(sp) - -0000042e <.LVL97>: - 42e: b741 j 3ae <.L44> - -00000430 <.L52>: - 430: 40d282b3 sub t0,t0,a3 - -00000434 <.LVL99>: - 434: 4681 li a3,0 - -00000436 <.LVL100>: - 436: f1f5 bnez a1,41a <.L53> - -00000438 <.L54>: - 438: 8ec1 or a3,a3,s0 - 43a: ca36 sw a3,20(sp) - -0000043c <.LVL102>: - 43c: 56f2 lw a3,60(sp) - -0000043e <.LVL103>: - 43e: 45b6 lw a1,76(sp) - -00000440 <.LBB27>: - 440: 4432 lw s0,12(sp) - -00000442 <.LBB28>: - 442: c836 sw a3,16(sp) - -00000444 <.LBB29>: - 444: 46a2 lw a3,8(sp) - 446: 9532 add a0,a0,a2 - 448: 97ae add a5,a5,a1 - 44a: 40650533 sub a0,a0,t1 - 44e: 8f91 sub a5,a5,a2 - 450: 9536 add a0,a0,a3 - 452: 97a2 add a5,a5,s0 - 454: 00a636b3 sltu a3,a2,a0 - 458: 971a add a4,a4,t1 - -0000045a <.LVL104>: - 45a: 00f5b433 sltu s0,a1,a5 - 45e: d036 sw a3,32(sp) - -00000460 <.LVL105>: - 460: c622 sw s0,12(sp) - 462: 00e336b3 sltu a3,t1,a4 - -00000466 <.LVL106>: - 466: 40d506b3 sub a3,a0,a3 - -0000046a <.LVL107>: - 46a: 00e37d63 bgeu t1,a4,484 <.L55> - -0000046e <.LBB30>: - 46e: 4422 lw s0,8(sp) - 470: 408383b3 sub t2,t2,s0 - -00000474 <.LBB31>: - 474: 00c39863 bne t2,a2,484 <.L55> - -00000478 <.LVL109>: - 478: 17fd add a5,a5,-1 - -0000047a <.L56>: - 47a: 405582b3 sub t0,a1,t0 - -0000047e <.LVL111>: - 47e: 0012b393 seqz t2,t0 - 482: a039 j 490 <.L57> - -00000484 <.L55>: - 484: 00a63433 sltu s0,a2,a0 - 488: 8f81 sub a5,a5,s0 - -0000048a <.LVL113>: - 48a: 4381 li t2,0 - 48c: fea667e3 bltu a2,a0,47a <.L56> - -00000490 <.L57>: - 490: 4542 lw a0,16(sp) - 492: 4452 lw s0,20(sp) - 494: de3e sw a5,60(sp) - 496: 9526 add a0,a0,s1 - 498: 8d0d sub a0,a0,a1 - 49a: 9522 add a0,a0,s0 - 49c: 4432 lw s0,12(sp) - 49e: dc36 sw a3,56(sp) - 4a0: da3a sw a4,52(sp) - -000004a2 <.LVL115>: - 4a2: 0083e3b3 or t2,t2,s0 - -000004a6 <.LVL116>: - 4a6: 407503b3 sub t2,a0,t2 - -000004aa <.LVL117>: - 4aa: c09e sw t2,64(sp) - -000004ac <.LBE31>: - 4ac: 0274fc63 bgeu s1,t2,4e4 <.L69> - 4b0: 971a add a4,a4,t1 - -000004b2 <.LVL118>: - 4b2: 9636 add a2,a2,a3 - -000004b4 <.LBB32>: - 4b4: da3a sw a4,52(sp) - -000004b6 <.LVL119>: - 4b6: 00673733 sltu a4,a4,t1 - 4ba: 9732 add a4,a4,a2 - 4bc: dc3a sw a4,56(sp) - 4be: 00d636b3 sltu a3,a2,a3 - -000004c2 <.LVL120>: - 4c2: 00c73733 sltu a4,a4,a2 - 4c6: 97ae add a5,a5,a1 - -000004c8 <.LVL121>: - 4c8: 8ed9 or a3,a3,a4 - 4ca: 96be add a3,a3,a5 - -000004cc <.LBE32>: - 4cc: 4412 lw s0,4(sp) - -000004ce <.LBB33>: - 4ce: de36 sw a3,60(sp) - -000004d0 <.LVL122>: - 4d0: 00b7b5b3 sltu a1,a5,a1 - 4d4: 00f6b6b3 sltu a3,a3,a5 - 4d8: 8dd5 or a1,a1,a3 - 4da: 93a6 add t2,t2,s1 - -000004dc <.LBE33>: - 4dc: 5579 li a0,-2 - -000004de <.LBB34>: - 4de: 959e add a1,a1,t2 - -000004e0 <.LBE34>: - 4e0: c448 sw a0,12(s0) - -000004e2 <.LBB35>: - 4e2: c0ae sw a1,64(sp) - -000004e4 <.L69>: - 4e4: 5792 lw a5,36(sp) - 4e6: 17fd add a5,a5,-1 - 4e8: d23e sw a5,36(sp) - -000004ea <.LVL125>: - 4ea: 4792 lw a5,4(sp) - -000004ec <.LVL126>: - 4ec: 17f1 add a5,a5,-4 - 4ee: c23e sw a5,4(sp) - 4f0: 57b2 lw a5,44(sp) - 4f2: 17f1 add a5,a5,-4 - 4f4: d63e sw a5,44(sp) - 4f6: b5c5 j 3d6 <.L120> - -000004f8 <.L46>: - 4f8: 6741 lui a4,0x10 - 4fa: 177d add a4,a4,-1 # ffff <.LLST129+0xe7e9> - 4fc: 8f65 and a4,a4,s1 - 4fe: 853e mv a0,a5 - 500: 0104d593 srl a1,s1,0x10 - 504: c43a sw a4,8(sp) - -00000506 <.LVL128>: - 506: c83e sw a5,16(sp) - 508: 00000097 auipc ra,0x0 - 50c: 000080e7 jalr ra # 508 <.LVL128+0x2> - -00000510 <.LVL129>: - 510: 85aa mv a1,a0 - 512: c62a sw a0,12(sp) - 514: 4522 lw a0,8(sp) - -00000516 <.LVL130>: - 516: 00000097 auipc ra,0x0 - 51a: 000080e7 jalr ra # 516 <.LVL130> - -0000051e <.LVL131>: - 51e: 47c2 lw a5,16(sp) - 520: 842a mv s0,a0 - -00000522 <.LVL132>: - 522: 0104d593 srl a1,s1,0x10 - 526: 853e mv a0,a5 - 528: 00000097 auipc ra,0x0 - 52c: 000080e7 jalr ra # 528 <.LVL132+0x6> - -00000530 <.LVL133>: - 530: 5772 lw a4,60(sp) - 532: 46b2 lw a3,12(sp) - 534: 0542 sll a0,a0,0x10 - 536: 01075613 srl a2,a4,0x10 - 53a: 8e49 or a2,a2,a0 - -0000053c <.LVL134>: - 53c: 87b6 mv a5,a3 - 53e: 00867c63 bgeu a2,s0,556 <.L70> - 542: 9626 add a2,a2,s1 - -00000544 <.LVL135>: - 544: fff68793 add a5,a3,-1 - -00000548 <.LVL136>: - 548: 00966763 bltu a2,s1,556 <.L70> - 54c: 00867563 bgeu a2,s0,556 <.L70> - 550: ffe68793 add a5,a3,-2 - 554: 9626 add a2,a2,s1 - -00000556 <.L70>: - 556: d03e sw a5,32(sp) - 558: 408607b3 sub a5,a2,s0 - -0000055c <.LVL139>: - 55c: 853e mv a0,a5 - 55e: 0104d593 srl a1,s1,0x10 - 562: ca3a sw a4,20(sp) - 564: c63e sw a5,12(sp) - -00000566 <.LVL140>: - 566: 00000097 auipc ra,0x0 - 56a: 000080e7 jalr ra # 566 <.LVL140> - -0000056e <.LVL141>: - 56e: 85aa mv a1,a0 - 570: c82a sw a0,16(sp) - 572: 4522 lw a0,8(sp) - -00000574 <.LVL142>: - 574: 00000097 auipc ra,0x0 - 578: 000080e7 jalr ra # 574 <.LVL142> - -0000057c <.LVL143>: - 57c: 842a mv s0,a0 - 57e: 4532 lw a0,12(sp) - 580: 0104d593 srl a1,s1,0x10 - 584: 00000097 auipc ra,0x0 - 588: 000080e7 jalr ra # 584 <.LVL143+0x8> - -0000058c <.LVL145>: - 58c: 4752 lw a4,20(sp) - 58e: 67c1 lui a5,0x10 - 590: 17fd add a5,a5,-1 # ffff <.LLST129+0xe7e9> - 592: 4642 lw a2,16(sp) - 594: 8f7d and a4,a4,a5 - 596: 0542 sll a0,a0,0x10 - 598: 8f49 or a4,a4,a0 - -0000059a <.LVL146>: - 59a: 5782 lw a5,32(sp) - 59c: 85b2 mv a1,a2 - 59e: 00877c63 bgeu a4,s0,5b6 <.L73> - 5a2: 9726 add a4,a4,s1 - -000005a4 <.LVL147>: - 5a4: fff60593 add a1,a2,-1 - -000005a8 <.LVL148>: - 5a8: 00976763 bltu a4,s1,5b6 <.L73> - 5ac: 00877563 bgeu a4,s0,5b6 <.L73> - 5b0: ffe60593 add a1,a2,-2 - 5b4: 9726 add a4,a4,s1 - -000005b6 <.L73>: - 5b6: 8f01 sub a4,a4,s0 - -000005b8 <.LVL151>: - 5b8: c0ba sw a4,64(sp) - -000005ba <.LBB37>: - 5ba: 4716 lw a4,68(sp) - -000005bc <.LBB70>: - 5bc: 4692 lw a3,4(sp) - 5be: 6441 lui s0,0x10 - -000005c0 <.LVL153>: - 5c0: 07c2 sll a5,a5,0x10 - 5c2: 8fcd or a5,a5,a1 - -000005c4 <.LBB43>: - 5c4: ca3a sw a4,20(sp) - 5c6: 01075313 srl t1,a4,0x10 - 5ca: fff40713 add a4,s0,-1 # ffff <.LLST129+0xe7e9> - -000005ce <.LBB72>: - 5ce: c6dc sw a5,12(a3) - -000005d0 <.LBB44>: - 5d0: 0107d293 srl t0,a5,0x10 - -000005d4 <.LBB39>: - 5d4: 8ff9 and a5,a5,a4 - -000005d6 <.LVL156>: - 5d6: 4752 lw a4,20(sp) - 5d8: fff40693 add a3,s0,-1 - -000005dc <.LVL157>: - 5dc: 853e mv a0,a5 - 5de: 00d773b3 and t2,a4,a3 - 5e2: 859e mv a1,t2 - -000005e4 <.LVL158>: - 5e4: 00000097 auipc ra,0x0 - 5e8: 000080e7 jalr ra # 5e4 <.LVL158> - 5ec: 872a mv a4,a0 - -000005ee <.LBB40>: - 5ee: 859a mv a1,t1 - 5f0: 853e mv a0,a5 - -000005f2 <.LVL160>: - 5f2: 00000097 auipc ra,0x0 - 5f6: 000080e7 jalr ra # 5f2 <.LVL160> - 5fa: 87aa mv a5,a0 - -000005fc <.LBB41>: - 5fc: 859e mv a1,t2 - 5fe: 8516 mv a0,t0 - -00000600 <.LVL162>: - 600: 00000097 auipc ra,0x0 - 604: 000080e7 jalr ra # 600 <.LVL162> - 608: 83aa mv t2,a0 - -0000060a <.LBB42>: - 60a: 859a mv a1,t1 - 60c: 8516 mv a0,t0 - 60e: 00000097 auipc ra,0x0 - 612: 000080e7 jalr ra # 60e <.LBB42+0x4> - -00000616 <.LBE42>: - 616: 01075693 srl a3,a4,0x10 - 61a: 979e add a5,a5,t2 - -0000061c <.LVL165>: - 61c: 96be add a3,a3,a5 - -0000061e <.LVL166>: - 61e: 0076f363 bgeu a3,t2,624 <.L76> - 622: 9522 add a0,a0,s0 - -00000624 <.L76>: - 624: 6641 lui a2,0x10 - 626: fff60593 add a1,a2,-1 # ffff <.LLST129+0xe7e9> - 62a: 0106d793 srl a5,a3,0x10 - 62e: 8eed and a3,a3,a1 - -00000630 <.LVL168>: - 630: 06c2 sll a3,a3,0x10 - 632: 8f6d and a4,a4,a1 - -00000634 <.LVL169>: - 634: 9736 add a4,a4,a3 - 636: d03a sw a4,32(sp) - -00000638 <.LBB45>: - 638: 4712 lw a4,4(sp) - -0000063a <.LBB50>: - 63a: 97aa add a5,a5,a0 - -0000063c <.LBB51>: - 63c: 4758 lw a4,12(a4) - 63e: c83a sw a4,16(sp) - -00000640 <.LVL172>: - 640: 01075413 srl s0,a4,0x10 - -00000644 <.LVL173>: - 644: 4726 lw a4,72(sp) - 646: 46c2 lw a3,16(sp) - 648: c63a sw a4,12(sp) - -0000064a <.LVL174>: - 64a: 00b6f2b3 and t0,a3,a1 - -0000064e <.LVL175>: - 64e: 46b2 lw a3,12(sp) - 650: 8341 srl a4,a4,0x10 - -00000652 <.LBB46>: - 652: 8516 mv a0,t0 - -00000654 <.LVL177>: - 654: 00b6f3b3 and t2,a3,a1 - -00000658 <.LVL178>: - 658: 859e mv a1,t2 - 65a: 00000097 auipc ra,0x0 - 65e: 000080e7 jalr ra # 65a <.LVL178+0x2> - 662: 832a mv t1,a0 - -00000664 <.LBB47>: - 664: 85ba mv a1,a4 - 666: 8516 mv a0,t0 - 668: 00000097 auipc ra,0x0 - 66c: 000080e7 jalr ra # 668 <.LBB47+0x4> - 670: 82aa mv t0,a0 - -00000672 <.LBB48>: - 672: 859e mv a1,t2 - 674: 8522 mv a0,s0 - 676: 00000097 auipc ra,0x0 - 67a: 000080e7 jalr ra # 676 <.LBB48+0x4> - 67e: 83aa mv t2,a0 - -00000680 <.LBB49>: - 680: 85ba mv a1,a4 - 682: 8522 mv a0,s0 - 684: 00000097 auipc ra,0x0 - 688: 000080e7 jalr ra # 684 <.LBB49+0x4> - -0000068c <.LBE49>: - 68c: 01035713 srl a4,t1,0x10 - -00000690 <.LVL183>: - 690: 929e add t0,t0,t2 - -00000692 <.LVL184>: - 692: 9716 add a4,a4,t0 - -00000694 <.LVL185>: - 694: 00777463 bgeu a4,t2,69c <.L77> - 698: 6641 lui a2,0x10 - 69a: 9532 add a0,a0,a2 - -0000069c <.L77>: - 69c: 6641 lui a2,0x10 - 69e: fff60693 add a3,a2,-1 # ffff <.LLST129+0xe7e9> - 6a2: fff60593 add a1,a2,-1 - 6a6: 8ef9 and a3,a3,a4 - 6a8: 06c2 sll a3,a3,0x10 - 6aa: 00b37333 and t1,t1,a1 - -000006ae <.LVL187>: - 6ae: 9336 add t1,t1,a3 - 6b0: 006786b3 add a3,a5,t1 - -000006b4 <.LBB54>: - 6b4: 00f6b7b3 sltu a5,a3,a5 - -000006b8 <.LBB55>: - 6b8: 8341 srl a4,a4,0x10 - -000006ba <.LBB56>: - 6ba: 4336 lw t1,76(sp) - -000006bc <.LBB61>: - 6bc: 973e add a4,a4,a5 - -000006be <.LBB62>: - 6be: 47c2 lw a5,16(sp) - 6c0: 00b373b3 and t2,t1,a1 - -000006c4 <.LBB63>: - 6c4: 972a add a4,a4,a0 - -000006c6 <.LBB64>: - 6c6: 0107d413 srl s0,a5,0x10 - -000006ca <.LBB57>: - 6ca: 8fed and a5,a5,a1 - 6cc: c436 sw a3,8(sp) - -000006ce <.LVL193>: - 6ce: 853e mv a0,a5 - -000006d0 <.LVL194>: - 6d0: 859e mv a1,t2 - -000006d2 <.LVL195>: - 6d2: 00000097 auipc ra,0x0 - 6d6: 000080e7 jalr ra # 6d2 <.LVL195> - -000006da <.LVL196>: - 6da: 82aa mv t0,a0 - -000006dc <.LBB58>: - 6dc: 01035593 srl a1,t1,0x10 - 6e0: 853e mv a0,a5 - 6e2: 00000097 auipc ra,0x0 - 6e6: 000080e7 jalr ra # 6e2 <.LBB58+0x6> - 6ea: 87aa mv a5,a0 - -000006ec <.LBB59>: - 6ec: 859e mv a1,t2 - 6ee: 8522 mv a0,s0 - -000006f0 <.LVL199>: - 6f0: 00000097 auipc ra,0x0 - 6f4: 000080e7 jalr ra # 6f0 <.LVL199> - 6f8: 83aa mv t2,a0 - -000006fa <.LBB60>: - 6fa: 01035593 srl a1,t1,0x10 - 6fe: 8522 mv a0,s0 - 700: 00000097 auipc ra,0x0 - 704: 000080e7 jalr ra # 700 <.LBB60+0x6> - -00000708 <.LBE60>: - 708: 0102d693 srl a3,t0,0x10 - 70c: 979e add a5,a5,t2 - -0000070e <.LVL202>: - 70e: 96be add a3,a3,a5 - -00000710 <.LVL203>: - 710: 0076f463 bgeu a3,t2,718 <.L80> - 714: 6641 lui a2,0x10 - -00000716 <.LVL204>: - 716: 9532 add a0,a0,a2 - -00000718 <.L80>: - 718: 6641 lui a2,0x10 - -0000071a <.LVL206>: - 71a: fff60793 add a5,a2,-1 # ffff <.LLST129+0xe7e9> - -0000071e <.LVL207>: - 71e: 8ff5 and a5,a5,a3 - -00000720 <.LVL208>: - 720: 167d add a2,a2,-1 - -00000722 <.LVL209>: - 722: 00c2f2b3 and t0,t0,a2 - -00000726 <.LVL210>: - 726: 07c2 sll a5,a5,0x10 - 728: 9796 add a5,a5,t0 - 72a: 97ba add a5,a5,a4 - -0000072c <.LBB67>: - 72c: 00e7b733 sltu a4,a5,a4 - -00000730 <.LBB68>: - 730: 82c1 srl a3,a3,0x10 - -00000732 <.LBB69>: - 732: 96ba add a3,a3,a4 - 734: 00a68433 add s0,a3,a0 - -00000738 <.LBE69>: - 738: 56b2 lw a3,44(sp) - 73a: 5562 lw a0,56(sp) - -0000073c <.LVL215>: - 73c: 5752 lw a4,52(sp) - 73e: 46d4 lw a3,12(a3) - 740: 4286 lw t0,64(sp) - 742: de2a sw a0,60(sp) - 744: dc3a sw a4,56(sp) - 746: da36 sw a3,52(sp) - 748: 0282e063 bltu t0,s0,768 <.L83> - 74c: 0e541263 bne s0,t0,830 <.L85> - 750: 00f56c63 bltu a0,a5,768 <.L83> - 754: 0cf51e63 bne a0,a5,830 <.L85> - 758: 4622 lw a2,8(sp) - -0000075a <.LVL216>: - 75a: 00c76763 bltu a4,a2,768 <.L83> - 75e: 0cc71963 bne a4,a2,830 <.L85> - 762: 5602 lw a2,32(sp) - 764: 0cc6f663 bgeu a3,a2,830 <.L85> - -00000768 <.L83>: - 768: 4642 lw a2,16(sp) - 76a: 4592 lw a1,4(sp) - -0000076c <.LBB74>: - 76c: 92a6 add t0,t0,s1 - -0000076e <.LBE74>: - 76e: 167d add a2,a2,-1 - 770: c5d0 sw a2,12(a1) - -00000772 <.LBB75>: - 772: 4652 lw a2,20(sp) - 774: 9636 add a2,a2,a3 - 776: 00d635b3 sltu a1,a2,a3 - 77a: d82e sw a1,48(sp) - 77c: 45b2 lw a1,12(sp) - 77e: 00d636b3 sltu a3,a2,a3 - 782: da32 sw a2,52(sp) - -00000784 <.LVL218>: - 784: 00b703b3 add t2,a4,a1 - -00000788 <.LVL219>: - 788: 969e add a3,a3,t2 - 78a: 00e3b733 sltu a4,t2,a4 - -0000078e <.LVL220>: - 78e: 0076b3b3 sltu t2,a3,t2 - 792: 006505b3 add a1,a0,t1 - 796: 00776733 or a4,a4,t2 - -0000079a <.LVL221>: - 79a: 972e add a4,a4,a1 - 79c: 00a5b533 sltu a0,a1,a0 - 7a0: 00b735b3 sltu a1,a4,a1 - 7a4: 8dc9 or a1,a1,a0 - 7a6: 9596 add a1,a1,t0 - 7a8: dc36 sw a3,56(sp) - -000007aa <.LVL222>: - 7aa: de3a sw a4,60(sp) - 7ac: c0ae sw a1,64(sp) - -000007ae <.LBE75>: - 7ae: 00b4ef63 bltu s1,a1,7cc <.L97> - 7b2: 06b49f63 bne s1,a1,830 <.L85> - 7b6: 00e36b63 bltu t1,a4,7cc <.L97> - 7ba: 06e31b63 bne t1,a4,830 <.L85> - 7be: 4532 lw a0,12(sp) - 7c0: 00d56663 bltu a0,a3,7cc <.L97> - 7c4: 06d51663 bne a0,a3,830 <.L85> - 7c8: 5542 lw a0,48(sp) - 7ca: e13d bnez a0,830 <.L85> - -000007cc <.L97>: - 7cc: 0285e063 bltu a1,s0,7ec <.L98> - 7d0: 06b41063 bne s0,a1,830 <.L85> - 7d4: 00f76c63 bltu a4,a5,7ec <.L98> - 7d8: 04f71c63 bne a4,a5,830 <.L85> - 7dc: 4522 lw a0,8(sp) - 7de: 00a6e763 bltu a3,a0,7ec <.L98> - 7e2: 04a69763 bne a3,a0,830 <.L85> - 7e6: 5502 lw a0,32(sp) - 7e8: 04a67463 bgeu a2,a0,830 <.L85> - -000007ec <.L98>: - 7ec: 4542 lw a0,16(sp) - 7ee: 4292 lw t0,4(sp) - 7f0: 971a add a4,a4,t1 - 7f2: 1579 add a0,a0,-2 - 7f4: 00a2a623 sw a0,12(t0) - -000007f8 <.LBB76>: - 7f8: 4552 lw a0,20(sp) - 7fa: 00673333 sltu t1,a4,t1 - -000007fe <.LVL224>: - 7fe: 962a add a2,a2,a0 - 800: 4532 lw a0,12(sp) - 802: da32 sw a2,52(sp) - -00000804 <.LVL225>: - 804: 96aa add a3,a3,a0 - -00000806 <.LVL226>: - 806: 4552 lw a0,20(sp) - -00000808 <.LVL227>: - 808: 00a63633 sltu a2,a2,a0 - -0000080c <.LVL228>: - 80c: 4532 lw a0,12(sp) - 80e: 9636 add a2,a2,a3 - -00000810 <.LVL229>: - 810: dc32 sw a2,56(sp) - -00000812 <.LVL230>: - 812: 00a6b533 sltu a0,a3,a0 - -00000816 <.LVL231>: - 816: 00d63633 sltu a2,a2,a3 - -0000081a <.LVL232>: - 81a: 8d51 or a0,a0,a2 - -0000081c <.LVL233>: - 81c: 953a add a0,a0,a4 - 81e: de2a sw a0,60(sp) - 820: 00e53533 sltu a0,a0,a4 - 824: 00a36533 or a0,t1,a0 - 828: 00b48733 add a4,s1,a1 - 82c: 953a add a0,a0,a4 - 82e: c0aa sw a0,64(sp) - -00000830 <.L85>: - 830: 52d2 lw t0,52(sp) - 832: 5702 lw a4,32(sp) - 834: 5362 lw t1,56(sp) - -00000836 <.LVL235>: - 836: 55f2 lw a1,60(sp) - -00000838 <.LVL236>: - 838: 40e28533 sub a0,t0,a4 - 83c: 4722 lw a4,8(sp) - 83e: 4686 lw a3,64(sp) - -00000840 <.LBB78>: - 840: 40e30633 sub a2,t1,a4 - 844: 00c334b3 sltu s1,t1,a2 - -00000848 <.LVL238>: - 848: 00a2b733 sltu a4,t0,a0 - 84c: 8e19 sub a2,a2,a4 - -0000084e <.LVL239>: - 84e: c626 sw s1,12(sp) - -00000850 <.LVL240>: - 850: 40f58733 sub a4,a1,a5 - 854: 00e5b3b3 sltu t2,a1,a4 - 858: 00a2fb63 bgeu t0,a0,86e <.L115> - 85c: 42a2 lw t0,8(sp) - 85e: 00629863 bne t0,t1,86e <.L115> - -00000862 <.LVL241>: - 862: 177d add a4,a4,-1 - -00000864 <.L116>: - 864: 40b785b3 sub a1,a5,a1 - -00000868 <.LVL243>: - 868: 0015b313 seqz t1,a1 - 86c: a031 j 878 <.L117> - -0000086e <.L115>: - 86e: 4332 lw t1,12(sp) - -00000870 <.LVL245>: - 870: 40670733 sub a4,a4,t1 - -00000874 <.LVL246>: - 874: 4301 li t1,0 - 876: f4fd bnez s1,864 <.L116> - -00000878 <.L117>: - 878: 8e81 sub a3,a3,s0 - -0000087a <.LVL248>: - 87a: 00736333 or t1,t1,t2 - -0000087e <.LBE77>: - 87e: 5592 lw a1,36(sp) - -00000880 <.LBB79>: - 880: 406686b3 sub a3,a3,t1 - 884: c0b6 sw a3,64(sp) - -00000886 <.LVL250>: - 886: de3a sw a4,60(sp) - -00000888 <.LVL251>: - 888: dc32 sw a2,56(sp) - -0000088a <.LVL252>: - 88a: da2a sw a0,52(sp) - -0000088c <.LBE79>: - 88c: c4059ce3 bnez a1,4e4 <.L69> - 890: 5582 lw a1,32(sp) - 892: 00a59963 bne a1,a0,8a4 <.L118> - 896: 45a2 lw a1,8(sp) - 898: 00b61663 bne a2,a1,8a4 <.L118> - 89c: 00e79463 bne a5,a4,8a4 <.L118> - 8a0: 00d40663 beq s0,a3,8ac <.L121> - -000008a4 <.L118>: - 8a4: 47d6 lw a5,84(sp) - -000008a6 <.LVL254>: - 8a6: 0017e793 or a5,a5,1 - 8aa: cabe sw a5,84(sp) - -000008ac <.L121>: - 8ac: 5722 lw a4,40(sp) - 8ae: 6791 lui a5,0x4 - 8b0: 17fd add a5,a5,-1 # 3fff <.LLST129+0x27e9> - 8b2: 97ba add a5,a5,a4 - -000008b4 <.LVL256>: - 8b4: 10f05363 blez a5,9ba <.L123> - 8b8: 4756 lw a4,84(sp) - 8ba: 00777693 and a3,a4,7 - 8be: c69d beqz a3,8ec <.L124> - 8c0: 00f77693 and a3,a4,15 - 8c4: 4611 li a2,4 - 8c6: 02c68363 beq a3,a2,8ec <.L124> - -000008ca <.LBB81>: - 8ca: 0711 add a4,a4,4 - 8cc: 00473693 sltiu a3,a4,4 - 8d0: caba sw a4,84(sp) - -000008d2 <.LVL257>: - 8d2: 4766 lw a4,88(sp) - -000008d4 <.LVL258>: - 8d4: 9736 add a4,a4,a3 - 8d6: ccba sw a4,88(sp) - -000008d8 <.LVL259>: - 8d8: 00d73733 sltu a4,a4,a3 - -000008dc <.LVL260>: - 8dc: 46f6 lw a3,92(sp) - 8de: 9736 add a4,a4,a3 - -000008e0 <.LVL261>: - 8e0: ceba sw a4,92(sp) - -000008e2 <.LVL262>: - 8e2: 00d73733 sltu a4,a4,a3 - -000008e6 <.LVL263>: - 8e6: 5686 lw a3,96(sp) - 8e8: 9736 add a4,a4,a3 - -000008ea <.LVL264>: - 8ea: d0ba sw a4,96(sp) - -000008ec <.L124>: - 8ec: 5706 lw a4,96(sp) - 8ee: 001006b7 lui a3,0x100 - 8f2: 8ef9 and a3,a3,a4 - 8f4: ca89 beqz a3,906 <.L129> - 8f6: fff007b7 lui a5,0xfff00 - -000008fa <.LVL266>: - 8fa: 17fd add a5,a5,-1 # ffefffff <.LLST129+0xffefe7e9> - 8fc: 8f7d and a4,a4,a5 - 8fe: d0ba sw a4,96(sp) - 900: 5722 lw a4,40(sp) - 902: 6791 lui a5,0x4 - -00000904 <.LVL267>: - 904: 97ba add a5,a5,a4 - -00000906 <.L129>: - 906: 08d8 add a4,sp,84 - 908: 108c add a1,sp,96 - -0000090a <.L130>: - 90a: 4314 lw a3,0(a4) - 90c: 4350 lw a2,4(a4) - 90e: 828d srl a3,a3,0x3 - 910: 0676 sll a2,a2,0x1d - 912: 8ed1 or a3,a3,a2 - 914: c314 sw a3,0(a4) - 916: 0711 add a4,a4,4 - 918: feb719e3 bne a4,a1,90a <.L130> - -0000091c <.LBE82>: - 91c: 66a1 lui a3,0x8 - 91e: ffe68613 add a2,a3,-2 # 7ffe <.LLST129+0x67e8> - -00000922 <.LBB83>: - 922: 5706 lw a4,96(sp) - -00000924 <.LBE83>: - 924: 08f64463 blt a2,a5,9ac <.L131> - -00000928 <.LBB84>: - 928: 830d srl a4,a4,0x3 - 92a: d0ba sw a4,96(sp) - -0000092c <.L132>: - 92c: 4702 lw a4,0(sp) - 92e: 45d6 lw a1,84(sp) - 930: 4666 lw a2,88(sp) - 932: 46f6 lw a3,92(sp) - 934: 4502 lw a0,0(sp) - 936: c30c sw a1,0(a4) - 938: c350 sw a2,4(a4) - 93a: c714 sw a3,8(a4) - 93c: 5706 lw a4,96(sp) - -0000093e <.LBE85>: - 93e: 40ea lw ra,152(sp) - 940: 445a lw s0,148(sp) - -00000942 <.LBB86>: - 942: 00e51623 sh a4,12(a0) - 946: 4772 lw a4,28(sp) - -00000948 <.LBE86>: - 948: 44ca lw s1,144(sp) - -0000094a <.LBB87>: - 94a: 073e sll a4,a4,0xf - 94c: 8fd9 or a5,a5,a4 - -0000094e <.LVL272>: - 94e: 00f51723 sh a5,14(a0) - -00000952 <.LBE87>: - 952: 4762 lw a4,24(sp) - -00000954 <.LBB88>: - 954: 455c lw a5,12(a0) - -00000956 <.LBE88>: - 956: c30c sw a1,0(a4) - 958: c350 sw a2,4(a4) - 95a: c714 sw a3,8(a4) - 95c: c75c sw a5,12(a4) - 95e: 853a mv a0,a4 - 960: 09c10113 add sp,sp,156 - -00000964 <.LVL274>: - 964: 8082 ret - -00000966 <.L37>: - 966: 47c2 lw a5,16(sp) - 968: ce3e sw a5,28(sp) - -0000096a <.LBE89>: - 96a: 57d2 lw a5,52(sp) - 96c: cabe sw a5,84(sp) - 96e: 57e2 lw a5,56(sp) - 970: ccbe sw a5,88(sp) - 972: 57f2 lw a5,60(sp) - 974: cebe sw a5,92(sp) - 976: 4786 lw a5,64(sp) - -00000978 <.L122>: - 978: d0be sw a5,96(sp) - -0000097a <.LVL278>: - 97a: 4785 li a5,1 - 97c: 18f70c63 beq a4,a5,b14 <.L202> - 980: d715 beqz a4,8ac <.L121> - 982: 4789 li a5,2 - 984: 18f71d63 bne a4,a5,b1e <.L35> - -00000988 <.L39>: - 988: 67a1 lui a5,0x8 - 98a: d082 sw zero,96(sp) - 98c: ce82 sw zero,92(sp) - 98e: cc82 sw zero,88(sp) - 990: ca82 sw zero,84(sp) - 992: 17fd add a5,a5,-1 # 7fff <.LLST129+0x67e9> - 994: bf61 j 92c <.L132> - -00000996 <.L38>: - 996: 47b2 lw a5,12(sp) - -00000998 <.LBE90>: - 998: 8736 mv a4,a3 - -0000099a <.LBB91>: - 99a: ce3e sw a5,28(sp) - -0000099c <.LBE91>: - 99c: 4796 lw a5,68(sp) - 99e: cabe sw a5,84(sp) - 9a0: 47a6 lw a5,72(sp) - 9a2: ccbe sw a5,88(sp) - 9a4: 47b6 lw a5,76(sp) - 9a6: cebe sw a5,92(sp) - 9a8: 47c6 lw a5,80(sp) - -000009aa <.LVL282>: - 9aa: b7f9 j 978 <.L122> - -000009ac <.L131>: - 9ac: d082 sw zero,96(sp) - 9ae: ce82 sw zero,92(sp) - 9b0: cc82 sw zero,88(sp) - 9b2: ca82 sw zero,84(sp) - 9b4: fff68793 add a5,a3,-1 - 9b8: bf95 j 92c <.L132> - -000009ba <.L123>: - 9ba: 4705 li a4,1 - 9bc: c791 beqz a5,9c8 <.L133> - 9be: 8f1d sub a4,a4,a5 - -000009c0 <.LVL285>: - 9c0: 07400793 li a5,116 - 9c4: 14e7c063 blt a5,a4,b04 <.L134> - -000009c8 <.L133>: - 9c8: 08d4 add a3,sp,84 - 9ca: 40575513 sra a0,a4,0x5 - -000009ce <.LVL287>: - 9ce: 85b6 mv a1,a3 - 9d0: 8b7d and a4,a4,31 - -000009d2 <.LVL288>: - 9d2: 4781 li a5,0 - 9d4: 4601 li a2,0 - -000009d6 <.L135>: - 9d6: 02a61563 bne a2,a0,a00 <.L136> - 9da: 460d li a2,3 - -000009dc <.LVL290>: - 9dc: 8e09 sub a2,a2,a0 - 9de: 00251313 sll t1,a0,0x2 - 9e2: e715 bnez a4,a0e <.L137> - 9e4: 85b6 mv a1,a3 - -000009e6 <.L138>: - 9e6: 006582b3 add t0,a1,t1 - 9ea: 0002a283 lw t0,0(t0) - 9ee: 0705 add a4,a4,1 - -000009f0 <.LVL292>: - 9f0: 0055a023 sw t0,0(a1) - -000009f4 <.LVL293>: - 9f4: 0591 add a1,a1,4 - 9f6: fee658e3 bge a2,a4,9e6 <.L138> - 9fa: 4591 li a1,4 - 9fc: 8d89 sub a1,a1,a0 - 9fe: a0b9 j a4c <.L142> - -00000a00 <.L136>: - a00: 0005a303 lw t1,0(a1) - a04: 0605 add a2,a2,1 - -00000a06 <.LVL295>: - a06: 0591 add a1,a1,4 - a08: 0067e7b3 or a5,a5,t1 - -00000a0c <.LVL296>: - a0c: b7e9 j 9d6 <.L135> - -00000a0e <.L137>: - a0e: 1840 add s0,sp,52 - a10: 05c30593 add a1,t1,92 - a14: 95a2 add a1,a1,s0 - a16: fc45a583 lw a1,-60(a1) - a1a: 02000293 li t0,32 - a1e: 40e282b3 sub t0,t0,a4 - a22: 005595b3 sll a1,a1,t0 - a26: 8fcd or a5,a5,a1 - -00000a28 <.LVL298>: - a28: 08cc add a1,sp,84 - a2a: 959a add a1,a1,t1 - a2c: 8436 mv s0,a3 - a2e: 4381 li t2,0 - -00000a30 <.L140>: - a30: 08c3cb63 blt t2,a2,ac6 <.L141> - a34: 4591 li a1,4 - a36: 060a sll a2,a2,0x2 - a38: 8d89 sub a1,a1,a0 - -00000a3a <.LVL300>: - a3a: 05c60613 add a2,a2,92 - a3e: 1848 add a0,sp,52 - -00000a40 <.LVL301>: - a40: 962a add a2,a2,a0 - a42: 5506 lw a0,96(sp) - a44: 00e55733 srl a4,a0,a4 - -00000a48 <.LVL302>: - a48: fce62223 sw a4,-60(a2) - -00000a4c <.L142>: - a4c: 4711 li a4,4 - a4e: 8f0d sub a4,a4,a1 - a50: 08d0 add a2,sp,84 - a52: 058a sll a1,a1,0x2 - a54: 95b2 add a1,a1,a2 - a56: 070a sll a4,a4,0x2 - a58: 4621 li a2,8 - a5a: 00c76863 bltu a4,a2,a6a <.L143> - a5e: 0005a023 sw zero,0(a1) - a62: 0005a223 sw zero,4(a1) - a66: 1761 add a4,a4,-8 - a68: 05a1 add a1,a1,8 - -00000a6a <.L143>: - a6a: 4611 li a2,4 - a6c: 00c76463 bltu a4,a2,a74 <.L144> - a70: 0005a023 sw zero,0(a1) - -00000a74 <.L144>: - a74: 4756 lw a4,84(sp) - -00000a76 <.LBB95>: - a76: 00f037b3 snez a5,a5 - -00000a7a <.LBE95>: - a7a: 8fd9 or a5,a5,a4 - a7c: cabe sw a5,84(sp) - -00000a7e <.LBE93>: - a7e: 0077f713 and a4,a5,7 - a82: c71d beqz a4,ab0 <.L145> - a84: 00f7f713 and a4,a5,15 - a88: 4611 li a2,4 - a8a: 02c70363 beq a4,a2,ab0 <.L145> - -00000a8e <.LBB97>: - a8e: 4766 lw a4,88(sp) - a90: 0791 add a5,a5,4 - a92: cabe sw a5,84(sp) - -00000a94 <.LVL305>: - a94: 0047b793 sltiu a5,a5,4 - -00000a98 <.LVL306>: - a98: 97ba add a5,a5,a4 - a9a: ccbe sw a5,88(sp) - -00000a9c <.LVL307>: - a9c: 00e7b7b3 sltu a5,a5,a4 - -00000aa0 <.LVL308>: - aa0: 4776 lw a4,92(sp) - aa2: 97ba add a5,a5,a4 - -00000aa4 <.LVL309>: - aa4: cebe sw a5,92(sp) - -00000aa6 <.LVL310>: - aa6: 00e7b7b3 sltu a5,a5,a4 - -00000aaa <.LVL311>: - aaa: 5706 lw a4,96(sp) - aac: 97ba add a5,a5,a4 - -00000aae <.LVL312>: - aae: d0be sw a5,96(sp) - -00000ab0 <.L145>: - ab0: 5706 lw a4,96(sp) - ab2: 000807b7 lui a5,0x80 - ab6: 8ff9 and a5,a5,a4 - ab8: c795 beqz a5,ae4 <.L150> - -00000aba <.LVL314>: - aba: d082 sw zero,96(sp) - abc: ce82 sw zero,92(sp) - abe: cc82 sw zero,88(sp) - ac0: ca82 sw zero,84(sp) - ac2: 4785 li a5,1 - ac4: b5a5 j 92c <.L132> - -00000ac6 <.L141>: - ac6: 0005a303 lw t1,0(a1) - aca: 41c4 lw s1,4(a1) - acc: 0385 add t2,t2,1 - -00000ace <.LVL316>: - ace: 00e35333 srl t1,t1,a4 - ad2: 005494b3 sll s1,s1,t0 - ad6: 00936333 or t1,t1,s1 - ada: 00642023 sw t1,0(s0) - -00000ade <.LVL317>: - ade: 0591 add a1,a1,4 - ae0: 0411 add s0,s0,4 - ae2: b7b9 j a30 <.L140> - -00000ae4 <.L150>: - ae4: 00c68613 add a2,a3,12 - -00000ae8 <.L151>: - ae8: 429c lw a5,0(a3) - aea: 42d8 lw a4,4(a3) - aec: 838d srl a5,a5,0x3 - aee: 0776 sll a4,a4,0x1d - af0: 8fd9 or a5,a5,a4 - af2: c29c sw a5,0(a3) - af4: 0691 add a3,a3,4 - af6: fed619e3 bne a2,a3,ae8 <.L151> - -00000afa <.LVL319>: - afa: 5786 lw a5,96(sp) - afc: 838d srl a5,a5,0x3 - afe: d0be sw a5,96(sp) - -00000b00 <.L152>: - b00: 4781 li a5,0 - b02: b52d j 92c <.L132> - -00000b04 <.L134>: - b04: 4766 lw a4,88(sp) - b06: 47d6 lw a5,84(sp) - b08: 8fd9 or a5,a5,a4 - b0a: 4776 lw a4,92(sp) - b0c: 8fd9 or a5,a5,a4 - b0e: 5706 lw a4,96(sp) - b10: 8fd9 or a5,a5,a4 - b12: d7fd beqz a5,b00 <.L152> - -00000b14 <.L202>: - b14: d082 sw zero,96(sp) - b16: ce82 sw zero,92(sp) - b18: cc82 sw zero,88(sp) - -00000b1a <.LBB100>: - b1a: ca82 sw zero,84(sp) - b1c: b7d5 j b00 <.L152> - -00000b1e <.L35>: - b1e: 67a1 lui a5,0x8 - b20: d0be sw a5,96(sp) - b22: ce82 sw zero,92(sp) - b24: cc82 sw zero,88(sp) - b26: ca82 sw zero,84(sp) - -00000b28 <.LVL325>: - b28: 17fd add a5,a5,-1 # 7fff <.LLST129+0x67e9> - b2a: ce02 sw zero,28(sp) - b2c: b501 j 92c <.L132> - -eqtf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__eqtf2>: - 0: 4514 lw a3,8(a0) - 2: 7179 add sp,sp,-48 - 4: 4550 lw a2,12(a0) - 6: c036 sw a3,0(sp) - 8: 45d4 lw a3,12(a1) - a: d622 sw s0,44(sp) - c: d426 sw s1,40(sp) - e: 4180 lw s0,0(a1) - 10: 0045a383 lw t2,4(a1) - 14: 0085a283 lw t0,8(a1) - -00000018 <.LBB3>: - 18: 01061493 sll s1,a2,0x10 - 1c: 01065313 srl t1,a2,0x10 - 20: 827d srl a2,a2,0x1f - -00000022 <.LBE3>: - 22: 4118 lw a4,0(a0) - -00000024 <.LBB4>: - 24: 415c lw a5,4(a0) - -00000026 <.LBB5>: - 26: 65a1 lui a1,0x8 - -00000028 <.LBE5>: - 28: 01b10513 add a0,sp,27 - -0000002c <.LBB6>: - 2c: c232 sw a2,4(sp) - -0000002e <.LBB7>: - 2e: 01069613 sll a2,a3,0x10 - -00000032 <.LBE7>: - 32: 9941 and a0,a0,-16 - -00000034 <.LBB8>: - 34: 15fd add a1,a1,-1 # 7fff <.LASF19+0x7e4d> - -00000036 <.LBB9>: - 36: 8241 srl a2,a2,0x10 - 38: c554 sw a3,12(a0) - 3a: c100 sw s0,0(a0) - 3c: 00752223 sw t2,4(a0) - 40: 00552423 sw t0,8(a0) - 44: c432 sw a2,8(sp) - -00000046 <.LBB10>: - 46: 00b37333 and t1,t1,a1 - -0000004a <.LBB11>: - 4a: 0106d613 srl a2,a3,0x10 - -0000004e <.LBB12>: - 4e: 80c1 srl s1,s1,0x10 - -00000050 <.LBB13>: - 50: 8e6d and a2,a2,a1 - 52: 82fd srl a3,a3,0x1f - -00000054 <.LBE13>: - 54: 4505 li a0,1 - 56: 00b30863 beq t1,a1,66 <.L2> - 5a: 02b61a63 bne a2,a1,8e <.L15> - -0000005e <.L1>: - 5e: 5432 lw s0,44(sp) - -00000060 <.LVL7>: - 60: 54a2 lw s1,40(sp) - -00000062 <.LVL8>: - 62: 6145 add sp,sp,48 - -00000064 <.LVL9>: - 64: 8082 ret - -00000066 <.L2>: - 66: fe661ce3 bne a2,t1,5e <.L1> - 6a: 8fd9 or a5,a5,a4 - -0000006c <.LVL11>: - 6c: 4702 lw a4,0(sp) - -0000006e <.LVL12>: - 6e: 8fd9 or a5,a5,a4 - 70: 8fc5 or a5,a5,s1 - 72: 4722 lw a4,8(sp) - 74: 8fc1 or a5,a5,s0 - 76: 0077e7b3 or a5,a5,t2 - 7a: 0057e7b3 or a5,a5,t0 - 7e: 8fd9 or a5,a5,a4 - 80: fff9 bnez a5,5e <.L1> - 82: 4792 lw a5,4(sp) - 84: 40d78533 sub a0,a5,a3 - 88: 00a03533 snez a0,a0 - 8c: bfc9 j 5e <.L1> - -0000008e <.L15>: - 8e: 4505 li a0,1 - 90: fc6617e3 bne a2,t1,5e <.L1> - 94: fc8715e3 bne a4,s0,5e <.L1> - 98: fc7793e3 bne a5,t2,5e <.L1> - 9c: 4582 lw a1,0(sp) - 9e: fc5590e3 bne a1,t0,5e <.L1> - a2: 45a2 lw a1,8(sp) - a4: fab49de3 bne s1,a1,5e <.L1> - a8: 4592 lw a1,4(sp) - aa: 00d58a63 beq a1,a3,be <.L13> - ae: fa45 bnez a2,5e <.L1> - b0: 8f5d or a4,a4,a5 - -000000b2 <.LVL14>: - b2: 4782 lw a5,0(sp) - -000000b4 <.LVL15>: - b4: 8f5d or a4,a4,a5 - b6: 8f45 or a4,a4,s1 - b8: 00e03533 snez a0,a4 - bc: b74d j 5e <.L1> - -000000be <.L13>: - be: 4501 li a0,0 - c0: bf79 j 5e <.L1> - -getf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__getf2>: - 0: 411c lw a5,0(a0) - 2: 7179 add sp,sp,-48 - -00000004 <.LBB3>: - 4: 4558 lw a4,12(a0) - 6: c03e sw a5,0(sp) - -00000008 <.LVL2>: - 8: 415c lw a5,4(a0) - a: 45d4 lw a3,12(a1) - c: 0045a303 lw t1,4(a1) - 10: c23e sw a5,4(sp) - -00000012 <.LVL3>: - 12: 451c lw a5,8(a0) - 14: 0085a283 lw t0,8(a1) - 18: 01b10513 add a0,sp,27 - 1c: c43e sw a5,8(sp) - -0000001e <.LVL4>: - 1e: 419c lw a5,0(a1) - -00000020 <.LBB4>: - 20: 6621 lui a2,0x8 - -00000022 <.LBE4>: - 22: d426 sw s1,40(sp) - 24: 9941 and a0,a0,-16 - 26: d622 sw s0,44(sp) - -00000028 <.LBB5>: - 28: 01075593 srl a1,a4,0x10 - 2c: 167d add a2,a2,-1 # 7fff <.LLST9+0x7ce7> - 2e: 01071493 sll s1,a4,0x10 - -00000032 <.LBB6>: - 32: c554 sw a3,12(a0) - 34: 01069393 sll t2,a3,0x10 - 38: c11c sw a5,0(a0) - 3a: 00652223 sw t1,4(a0) - 3e: 00552423 sw t0,8(a0) - -00000042 <.LBB7>: - 42: 8df1 and a1,a1,a2 - -00000044 <.LBB8>: - 44: 0106d513 srl a0,a3,0x10 - -00000048 <.LBB9>: - 48: 80c1 srl s1,s1,0x10 - -0000004a <.LVL5>: - 4a: 837d srl a4,a4,0x1f - -0000004c <.LBB10>: - 4c: 0103d393 srl t2,t2,0x10 - -00000050 <.LVL7>: - 50: 8d71 and a0,a0,a2 - -00000052 <.LVL8>: - 52: 82fd srl a3,a3,0x1f - -00000054 <.LBE10>: - 54: 02c59e63 bne a1,a2,90 <.L2> - 58: 4402 lw s0,0(sp) - 5a: 4612 lw a2,4(sp) - 5c: 8e41 or a2,a2,s0 - 5e: 4422 lw s0,8(sp) - 60: 8e41 or a2,a2,s0 - 62: 8e45 or a2,a2,s1 - 64: e279 bnez a2,12a <.L26> - 66: 00b50663 beq a0,a1,72 <.L4> - -0000006a <.L21>: - 6a: 4505 li a0,1 - 6c: cf11 beqz a4,88 <.L1> - 6e: 557d li a0,-1 - 70: a821 j 88 <.L1> - -00000072 <.L4>: - 72: 0067e7b3 or a5,a5,t1 - -00000076 <.LVL12>: - 76: 0057e7b3 or a5,a5,t0 - 7a: 0077e7b3 or a5,a5,t2 - 7e: 5579 li a0,-2 - -00000080 <.LVL13>: - 80: e781 bnez a5,88 <.L1> - -00000082 <.LBB12>: - 82: 4501 li a0,0 - 84: fee693e3 bne a3,a4,6a <.L21> - -00000088 <.L1>: - 88: 5432 lw s0,44(sp) - 8a: 54a2 lw s1,40(sp) - -0000008c <.LVL15>: - 8c: 6145 add sp,sp,48 - -0000008e <.LVL16>: - 8e: 8082 ret - -00000090 <.L2>: - 90: 02c51063 bne a0,a2,b0 <.L10> - 94: 0067e633 or a2,a5,t1 - 98: 00566633 or a2,a2,t0 - 9c: 00766633 or a2,a2,t2 - a0: e649 bnez a2,12a <.L26> - -000000a2 <.LBB13>: - a2: c185 beqz a1,c2 <.L11> - -000000a4 <.LVL18>: - a4: fce693e3 bne a3,a4,6a <.L21> - -000000a8 <.L22>: - a8: 557d li a0,-1 - aa: df79 beqz a4,88 <.L1> - ac: 853a mv a0,a4 - ae: bfe9 j 88 <.L1> - -000000b0 <.L10>: - b0: c585 beqz a1,d8 <.L13> - -000000b2 <.LVL21>: - b2: dd45 beqz a0,6a <.L21> - -000000b4 <.L14>: - b4: fae69be3 bne a3,a4,6a <.L21> - b8: fab549e3 blt a0,a1,6a <.L21> - bc: 02a5df63 bge a1,a0,fa <.L18> - c0: b7e5 j a8 <.L22> - -000000c2 <.L11>: - c2: 4402 lw s0,0(sp) - c4: 4612 lw a2,4(sp) - c6: 8e41 or a2,a2,s0 - c8: 4422 lw s0,8(sp) - ca: 8e41 or a2,a2,s0 - cc: 8e45 or a2,a2,s1 - -000000ce <.L15>: - ce: f27d bnez a2,b4 <.L14> - -000000d0 <.L17>: - d0: 557d li a0,-1 - -000000d2 <.LVL25>: - d2: dadd beqz a3,88 <.L1> - d4: 8536 mv a0,a3 - d6: bf4d j 88 <.L1> - -000000d8 <.L13>: - d8: 4402 lw s0,0(sp) - da: 4612 lw a2,4(sp) - dc: 8e41 or a2,a2,s0 - de: 4422 lw s0,8(sp) - e0: 8e41 or a2,a2,s0 - e2: 8e45 or a2,a2,s1 - -000000e4 <.LVL27>: - e4: f56d bnez a0,ce <.L15> - e6: 0067e5b3 or a1,a5,t1 - -000000ea <.LVL28>: - ea: 0055e5b3 or a1,a1,t0 - ee: 0075e5b3 or a1,a1,t2 - f2: c995 beqz a1,126 <.L16> - -000000f4 <.LVL29>: - f4: de71 beqz a2,d0 <.L17> - -000000f6 <.LVL30>: - f6: f6e69ae3 bne a3,a4,6a <.L21> - -000000fa <.L18>: - fa: f693e8e3 bltu t2,s1,6a <.L21> - fe: fa7495e3 bne s1,t2,a8 <.L22> - 102: 46a2 lw a3,8(sp) - -00000104 <.LVL31>: - 104: f6d2e3e3 bltu t0,a3,6a <.L21> - 108: fa5690e3 bne a3,t0,a8 <.L22> - 10c: 4692 lw a3,4(sp) - 10e: f4d36ee3 bltu t1,a3,6a <.L21> - 112: f8669be3 bne a3,t1,a8 <.L22> - 116: 4682 lw a3,0(sp) - 118: f4d7e9e3 bltu a5,a3,6a <.L21> - 11c: 4682 lw a3,0(sp) - 11e: 4501 li a0,0 - -00000120 <.LVL32>: - 120: f8f6e4e3 bltu a3,a5,a8 <.L22> - 124: b795 j 88 <.L1> - -00000126 <.L16>: - 126: d22d beqz a2,88 <.L1> - 128: b789 j 6a <.L21> - -0000012a <.L26>: - 12a: 5579 li a0,-2 - -0000012c <.LVL35>: - 12c: bfb1 j 88 <.L1> - -letf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__letf2>: - 0: 411c lw a5,0(a0) - 2: 7179 add sp,sp,-48 - -00000004 <.LBB3>: - 4: 4558 lw a4,12(a0) - 6: c03e sw a5,0(sp) - -00000008 <.LVL2>: - 8: 415c lw a5,4(a0) - a: 45d4 lw a3,12(a1) - c: 0045a303 lw t1,4(a1) - 10: c23e sw a5,4(sp) - -00000012 <.LVL3>: - 12: 451c lw a5,8(a0) - 14: 0085a283 lw t0,8(a1) - 18: 01b10513 add a0,sp,27 - 1c: c43e sw a5,8(sp) - -0000001e <.LVL4>: - 1e: 419c lw a5,0(a1) - -00000020 <.LBB4>: - 20: 6621 lui a2,0x8 - -00000022 <.LBE4>: - 22: d426 sw s1,40(sp) - 24: 9941 and a0,a0,-16 - 26: d622 sw s0,44(sp) - -00000028 <.LBB5>: - 28: 01075593 srl a1,a4,0x10 - 2c: 167d add a2,a2,-1 # 7fff <.LLST9+0x7ce7> - 2e: 01071493 sll s1,a4,0x10 - -00000032 <.LBB6>: - 32: c554 sw a3,12(a0) - 34: 01069393 sll t2,a3,0x10 - 38: c11c sw a5,0(a0) - 3a: 00652223 sw t1,4(a0) - 3e: 00552423 sw t0,8(a0) - -00000042 <.LBB7>: - 42: 8df1 and a1,a1,a2 - -00000044 <.LBB8>: - 44: 0106d513 srl a0,a3,0x10 - -00000048 <.LBB9>: - 48: 80c1 srl s1,s1,0x10 - -0000004a <.LVL5>: - 4a: 837d srl a4,a4,0x1f - -0000004c <.LBB10>: - 4c: 0103d393 srl t2,t2,0x10 - -00000050 <.LVL7>: - 50: 8d71 and a0,a0,a2 - -00000052 <.LVL8>: - 52: 82fd srl a3,a3,0x1f - -00000054 <.LBE10>: - 54: 02c59e63 bne a1,a2,90 <.L2> - 58: 4402 lw s0,0(sp) - 5a: 4612 lw a2,4(sp) - 5c: 8e41 or a2,a2,s0 - 5e: 4422 lw s0,8(sp) - 60: 8e41 or a2,a2,s0 - 62: 8e45 or a2,a2,s1 - 64: e279 bnez a2,12a <.L26> - 66: 00b50663 beq a0,a1,72 <.L4> - -0000006a <.L21>: - 6a: 4505 li a0,1 - 6c: cf11 beqz a4,88 <.L1> - 6e: 557d li a0,-1 - 70: a821 j 88 <.L1> - -00000072 <.L4>: - 72: 0067e7b3 or a5,a5,t1 - -00000076 <.LVL12>: - 76: 0057e7b3 or a5,a5,t0 - 7a: 0077e7b3 or a5,a5,t2 - 7e: 4509 li a0,2 - -00000080 <.LVL13>: - 80: e781 bnez a5,88 <.L1> - -00000082 <.LBB12>: - 82: 4501 li a0,0 - 84: fee693e3 bne a3,a4,6a <.L21> - -00000088 <.L1>: - 88: 5432 lw s0,44(sp) - 8a: 54a2 lw s1,40(sp) - -0000008c <.LVL15>: - 8c: 6145 add sp,sp,48 - -0000008e <.LVL16>: - 8e: 8082 ret - -00000090 <.L2>: - 90: 02c51063 bne a0,a2,b0 <.L10> - 94: 0067e633 or a2,a5,t1 - 98: 00566633 or a2,a2,t0 - 9c: 00766633 or a2,a2,t2 - a0: e649 bnez a2,12a <.L26> - -000000a2 <.LBB13>: - a2: c185 beqz a1,c2 <.L11> - -000000a4 <.LVL18>: - a4: fce693e3 bne a3,a4,6a <.L21> - -000000a8 <.L22>: - a8: 557d li a0,-1 - aa: df79 beqz a4,88 <.L1> - ac: 853a mv a0,a4 - ae: bfe9 j 88 <.L1> - -000000b0 <.L10>: - b0: c585 beqz a1,d8 <.L13> - -000000b2 <.LVL21>: - b2: dd45 beqz a0,6a <.L21> - -000000b4 <.L14>: - b4: fae69be3 bne a3,a4,6a <.L21> - b8: fab549e3 blt a0,a1,6a <.L21> - bc: 02a5df63 bge a1,a0,fa <.L18> - c0: b7e5 j a8 <.L22> - -000000c2 <.L11>: - c2: 4402 lw s0,0(sp) - c4: 4612 lw a2,4(sp) - c6: 8e41 or a2,a2,s0 - c8: 4422 lw s0,8(sp) - ca: 8e41 or a2,a2,s0 - cc: 8e45 or a2,a2,s1 - -000000ce <.L15>: - ce: f27d bnez a2,b4 <.L14> - -000000d0 <.L17>: - d0: 557d li a0,-1 - -000000d2 <.LVL25>: - d2: dadd beqz a3,88 <.L1> - d4: 8536 mv a0,a3 - d6: bf4d j 88 <.L1> - -000000d8 <.L13>: - d8: 4402 lw s0,0(sp) - da: 4612 lw a2,4(sp) - dc: 8e41 or a2,a2,s0 - de: 4422 lw s0,8(sp) - e0: 8e41 or a2,a2,s0 - e2: 8e45 or a2,a2,s1 - -000000e4 <.LVL27>: - e4: f56d bnez a0,ce <.L15> - e6: 0067e5b3 or a1,a5,t1 - -000000ea <.LVL28>: - ea: 0055e5b3 or a1,a1,t0 - ee: 0075e5b3 or a1,a1,t2 - f2: c995 beqz a1,126 <.L16> - -000000f4 <.LVL29>: - f4: de71 beqz a2,d0 <.L17> - -000000f6 <.LVL30>: - f6: f6e69ae3 bne a3,a4,6a <.L21> - -000000fa <.L18>: - fa: f693e8e3 bltu t2,s1,6a <.L21> - fe: fa7495e3 bne s1,t2,a8 <.L22> - 102: 46a2 lw a3,8(sp) - -00000104 <.LVL31>: - 104: f6d2e3e3 bltu t0,a3,6a <.L21> - 108: fa5690e3 bne a3,t0,a8 <.L22> - 10c: 4692 lw a3,4(sp) - 10e: f4d36ee3 bltu t1,a3,6a <.L21> - 112: f8669be3 bne a3,t1,a8 <.L22> - 116: 4682 lw a3,0(sp) - 118: f4d7e9e3 bltu a5,a3,6a <.L21> - 11c: 4682 lw a3,0(sp) - 11e: 4501 li a0,0 - -00000120 <.LVL32>: - 120: f8f6e4e3 bltu a3,a5,a8 <.L22> - 124: b795 j 88 <.L1> - -00000126 <.L16>: - 126: d22d beqz a2,88 <.L1> - 128: b789 j 6a <.L21> - -0000012a <.L26>: - 12a: 4509 li a0,2 - -0000012c <.LVL35>: - 12c: bfb1 j 88 <.L1> - -multf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__multf3>: - 0: 4218 lw a4,0(a2) - 2: f3c10113 add sp,sp,-196 - 6: 419c lw a5,0(a1) - 8: c43a sw a4,8(sp) - a: 4618 lw a4,8(a2) - c: 4594 lw a3,8(a1) - e: cc2a sw a0,24(sp) - 10: c23a sw a4,4(sp) - 12: 4658 lw a4,12(a2) - 14: 41c8 lw a0,4(a1) - 16: 45cc lw a1,12(a1) - 18: c63a sw a4,12(sp) - 1a: 0ab10713 add a4,sp,171 - 1e: 9b41 and a4,a4,-16 - 20: df22 sw s0,188(sp) - 22: dd26 sw s1,184(sp) - 24: c186 sw ra,192(sp) - -00000026 <.LBB3>: - 26: c74c sw a1,12(a4) - -00000028 <.LBE3>: - 28: 4244 lw s1,4(a2) - 2a: c03a sw a4,0(sp) - -0000002c <.LBB4>: - 2c: c31c sw a5,0(a4) - 2e: c348 sw a0,4(a4) - 30: c714 sw a3,8(a4) - 32: 6621 lui a2,0x8 - 34: 01059713 sll a4,a1,0x10 - 38: 0105d413 srl s0,a1,0x10 - 3c: 8341 srl a4,a4,0x10 - 3e: 167d add a2,a2,-1 # 7fff <.LLST246+0x5acb> - 40: 81fd srl a1,a1,0x1f - 42: c6be sw a5,76(sp) - 44: c8aa sw a0,80(sp) - 46: cab6 sw a3,84(sp) - 48: ccba sw a4,88(sp) - 4a: 8c71 and s0,s0,a2 - -0000004c <.LVL2>: - 4c: c82e sw a1,16(sp) - -0000004e <.LBE4>: - 4e: 28040de3 beqz s0,ae8 <.L2> - 52: 38c40de3 beq s0,a2,bec <.L3> - 56: 67c1 lui a5,0x10 - 58: 8fd9 or a5,a5,a4 - 5a: ccbe sw a5,88(sp) - -0000005c <.LBB5>: - 5c: 0090 add a2,sp,64 - 5e: 00fc add a5,sp,76 - -00000060 <.L4>: - 60: 47d8 lw a4,12(a5) - 62: 4794 lw a3,8(a5) - 64: 17f1 add a5,a5,-4 # fffc <.LLST246+0xdac8> - 66: 070e sll a4,a4,0x3 - 68: 82f5 srl a3,a3,0x1d - 6a: 8f55 or a4,a4,a3 - 6c: cb98 sw a4,16(a5) - 6e: fef619e3 bne a2,a5,60 <.L4> - -00000072 <.LVL6>: - 72: 47b6 lw a5,76(sp) - 74: 078e sll a5,a5,0x3 - 76: c6be sw a5,76(sp) - -00000078 <.LBE5>: - 78: 77f1 lui a5,0xffffc - 7a: 0785 add a5,a5,1 # ffffc001 <.LLST246+0xffff9acd> - 7c: 943e add s0,s0,a5 - -0000007e <.L205>: - 7e: 4701 li a4,0 - -00000080 <.L5>: - 80: 4782 lw a5,0(sp) - 82: 46a2 lw a3,8(sp) - 84: 4632 lw a2,12(sp) - 86: c3c4 sw s1,4(a5) - 88: c394 sw a3,0(a5) - 8a: 4692 lw a3,4(sp) - 8c: 00c15503 lhu a0,12(sp) - 90: 827d srl a2,a2,0x1f - 92: c794 sw a3,8(a5) - 94: 46b2 lw a3,12(sp) - 96: d0a6 sw s1,96(sp) - 98: d4aa sw a0,104(sp) - 9a: c7d4 sw a3,12(a5) - 9c: 47a2 lw a5,8(sp) - 9e: c632 sw a2,12(sp) - a0: cebe sw a5,92(sp) - a2: 4792 lw a5,4(sp) - a4: d2be sw a5,100(sp) - a6: 0106d793 srl a5,a3,0x10 - aa: 66a1 lui a3,0x8 - ac: 16fd add a3,a3,-1 # 7fff <.LLST246+0x5acb> - ae: 8ff5 and a5,a5,a3 - -000000b0 <.LBE11>: - b0: 34078be3 beqz a5,c06 <.L18> - b4: 46d787e3 beq a5,a3,d22 <.L19> - b8: 66c1 lui a3,0x10 - ba: 8ec9 or a3,a3,a0 - bc: d4b6 sw a3,104(sp) - -000000be <.LBB12>: - be: 0888 add a0,sp,80 - c0: 08f4 add a3,sp,92 - -000000c2 <.L20>: - c2: 46d0 lw a2,12(a3) - c4: 468c lw a1,8(a3) - c6: 16f1 add a3,a3,-4 # fffc <.LLST246+0xdac8> - c8: 060e sll a2,a2,0x3 - ca: 81f5 srl a1,a1,0x1d - cc: 8e4d or a2,a2,a1 - ce: ca90 sw a2,16(a3) - d0: fed519e3 bne a0,a3,c2 <.L20> - -000000d4 <.LVL12>: - d4: 46f6 lw a3,92(sp) - d6: 068e sll a3,a3,0x3 - d8: ceb6 sw a3,92(sp) - -000000da <.LBE12>: - da: 76f1 lui a3,0xffffc - dc: 0685 add a3,a3,1 # ffffc001 <.LLST246+0xffff9acd> - de: 97b6 add a5,a5,a3 - -000000e0 <.L207>: - e0: 4681 li a3,0 - -000000e2 <.L21>: - e2: 4642 lw a2,16(sp) - e4: 45b2 lw a1,12(sp) - e6: 97a2 add a5,a5,s0 - -000000e8 <.LVL15>: - e8: d43e sw a5,40(sp) - ea: 0785 add a5,a5,1 - ec: 8e2d xor a2,a2,a1 - ee: d23e sw a5,36(sp) - f0: 00271793 sll a5,a4,0x2 - f4: ce32 sw a2,28(sp) - -000000f6 <.LVL16>: - f6: 8fd5 or a5,a5,a3 - f8: 4629 li a2,10 - -000000fa <.LVL17>: - fa: 46f649e3 blt a2,a5,d6c <.L34> - fe: 4609 li a2,2 - 100: 44f641e3 blt a2,a5,d42 <.L35> - 104: 17fd add a5,a5,-1 - 106: 4705 li a4,1 - 108: 4af772e3 bgeu a4,a5,dac <.L37> - -0000010c <.L36>: - 10c: 47b6 lw a5,76(sp) - 10e: 44f6 lw s1,92(sp) - 110: 62c1 lui t0,0x10 - 112: fff28313 add t1,t0,-1 # ffff <.LLST246+0xdacb> - 116: c23e sw a5,4(sp) - -00000118 <.LVL19>: - 118: 0107d413 srl s0,a5,0x10 - -0000011c <.LVL20>: - 11c: 0067f7b3 and a5,a5,t1 - 120: 0064f333 and t1,s1,t1 - 124: 0104d393 srl t2,s1,0x10 - -00000128 <.LBB21>: - 128: 853e mv a0,a5 - 12a: 859a mv a1,t1 - 12c: 00000097 auipc ra,0x0 - 130: 000080e7 jalr ra # 12c <.LBB21+0x4> - -00000134 <.LVL22>: - 134: 872a mv a4,a0 - -00000136 <.LBB22>: - 136: 859e mv a1,t2 - 138: 853e mv a0,a5 - -0000013a <.LVL24>: - 13a: 00000097 auipc ra,0x0 - 13e: 000080e7 jalr ra # 13a <.LVL24> - 142: 87aa mv a5,a0 - -00000144 <.LBB23>: - 144: 859a mv a1,t1 - 146: 8522 mv a0,s0 - -00000148 <.LVL26>: - 148: 00000097 auipc ra,0x0 - 14c: 000080e7 jalr ra # 148 <.LVL26> - 150: 832a mv t1,a0 - -00000152 <.LBB24>: - 152: 859e mv a1,t2 - 154: 8522 mv a0,s0 - 156: 00000097 auipc ra,0x0 - 15a: 000080e7 jalr ra # 156 <.LBB24+0x4> - -0000015e <.LBE24>: - 15e: 01075693 srl a3,a4,0x10 - 162: 979a add a5,a5,t1 - -00000164 <.LVL29>: - 164: 96be add a3,a3,a5 - -00000166 <.LVL30>: - 166: 0066f363 bgeu a3,t1,16c <.L42> - 16a: 9516 add a0,a0,t0 - -0000016c <.L42>: - 16c: 0106d793 srl a5,a3,0x10 - 170: 97aa add a5,a5,a0 - 172: 6441 lui s0,0x10 - -00000174 <.LVL32>: - 174: c13e sw a5,128(sp) - 176: fff40793 add a5,s0,-1 # ffff <.LLST246+0xdacb> - 17a: 8efd and a3,a3,a5 - -0000017c <.LVL33>: - 17c: 8f7d and a4,a4,a5 - -0000017e <.LVL34>: - 17e: 06c2 sll a3,a3,0x10 - 180: 96ba add a3,a3,a4 - -00000182 <.LBB25>: - 182: 4712 lw a4,4(sp) - -00000184 <.LBB31>: - 184: deb6 sw a3,124(sp) - -00000186 <.LBB32>: - 186: 01075393 srl t2,a4,0x10 - -0000018a <.LVL36>: - 18a: 5706 lw a4,96(sp) - 18c: c43a sw a4,8(sp) - -0000018e <.LVL37>: - 18e: 8341 srl a4,a4,0x10 - 190: c63a sw a4,12(sp) - -00000192 <.LBB26>: - 192: 4712 lw a4,4(sp) - 194: 00f77333 and t1,a4,a5 - -00000198 <.LVL39>: - 198: 4722 lw a4,8(sp) - 19a: 851a mv a0,t1 - -0000019c <.LVL40>: - 19c: 00f772b3 and t0,a4,a5 - 1a0: 8596 mv a1,t0 - 1a2: 00000097 auipc ra,0x0 - 1a6: 000080e7 jalr ra # 1a2 <.LVL40+0x6> - 1aa: 872a mv a4,a0 - -000001ac <.LBB27>: - 1ac: 45b2 lw a1,12(sp) - 1ae: 851a mv a0,t1 - -000001b0 <.LVL42>: - 1b0: 00000097 auipc ra,0x0 - 1b4: 000080e7 jalr ra # 1b0 <.LVL42> - 1b8: 832a mv t1,a0 - -000001ba <.LBB28>: - 1ba: 8596 mv a1,t0 - 1bc: 851e mv a0,t2 - 1be: 00000097 auipc ra,0x0 - 1c2: 000080e7 jalr ra # 1be <.LBB28+0x4> - 1c6: 82aa mv t0,a0 - -000001c8 <.LBB29>: - 1c8: 45b2 lw a1,12(sp) - 1ca: 851e mv a0,t2 - 1cc: 00000097 auipc ra,0x0 - 1d0: 000080e7 jalr ra # 1cc <.LBB29+0x4> - -000001d4 <.LBE29>: - 1d4: 01075693 srl a3,a4,0x10 - 1d8: 9316 add t1,t1,t0 - -000001da <.LBB30>: - 1da: ca2a sw a0,20(sp) - -000001dc <.LBE30>: - 1dc: 9336 add t1,t1,a3 - -000001de <.LVL47>: - 1de: 00537563 bgeu t1,t0,1e8 <.L43> - 1e2: 008506b3 add a3,a0,s0 - 1e6: ca36 sw a3,20(sp) - -000001e8 <.L43>: - 1e8: 01035693 srl a3,t1,0x10 - 1ec: 00f37333 and t1,t1,a5 - -000001f0 <.LVL49>: - 1f0: 0342 sll t1,t1,0x10 - 1f2: 8f7d and a4,a4,a5 - -000001f4 <.LVL50>: - 1f4: 971a add a4,a4,t1 - 1f6: da3a sw a4,52(sp) - -000001f8 <.LBB33>: - 1f8: 4746 lw a4,80(sp) - -000001fa <.LBB38>: - 1fa: d836 sw a3,48(sp) - -000001fc <.LBB39>: - 1fc: c63a sw a4,12(sp) - -000001fe <.LVL52>: - 1fe: 46b2 lw a3,12(sp) - -00000200 <.LVL53>: - 200: 01075293 srl t0,a4,0x10 - -00000204 <.LVL54>: - 204: 0104d713 srl a4,s1,0x10 - -00000208 <.LBB34>: - 208: 00f6f3b3 and t2,a3,a5 - 20c: 8fe5 and a5,a5,s1 - 20e: 851e mv a0,t2 - 210: 85be mv a1,a5 - 212: 00000097 auipc ra,0x0 - 216: 000080e7 jalr ra # 212 <.LBB34+0xa> - 21a: 832a mv t1,a0 - -0000021c <.LBB35>: - 21c: 85ba mv a1,a4 - 21e: 851e mv a0,t2 - 220: 00000097 auipc ra,0x0 - 224: 000080e7 jalr ra # 220 <.LBB35+0x4> - 228: 83aa mv t2,a0 - -0000022a <.LBB36>: - 22a: 85be mv a1,a5 - 22c: 8516 mv a0,t0 - 22e: 00000097 auipc ra,0x0 - 232: 000080e7 jalr ra # 22e <.LBB36+0x4> - 236: 87aa mv a5,a0 - -00000238 <.LBB37>: - 238: 85ba mv a1,a4 - 23a: 8516 mv a0,t0 - -0000023c <.LVL58>: - 23c: 00000097 auipc ra,0x0 - 240: 000080e7 jalr ra # 23c <.LVL58> - -00000244 <.LBE37>: - 244: 01035713 srl a4,t1,0x10 - 248: 93be add t2,t2,a5 - -0000024a <.LVL60>: - 24a: 93ba add t2,t2,a4 - -0000024c <.LVL61>: - 24c: 00f3f463 bgeu t2,a5,254 <.L44> - 250: 67c1 lui a5,0x10 - -00000252 <.LVL62>: - 252: 953e add a0,a0,a5 - -00000254 <.L44>: - 254: 6441 lui s0,0x10 - 256: fff40713 add a4,s0,-1 # ffff <.LLST246+0xdacb> - 25a: 0103d793 srl a5,t2,0x10 - 25e: 00e3f3b3 and t2,t2,a4 - -00000262 <.LVL64>: - 262: 97aa add a5,a5,a0 - 264: 00e37333 and t1,t1,a4 - -00000268 <.LVL65>: - 268: 03c2 sll t2,t2,0x10 - 26a: dc3e sw a5,56(sp) - -0000026c <.LVL66>: - 26c: 006387b3 add a5,t2,t1 - -00000270 <.LVL67>: - 270: de3e sw a5,60(sp) - -00000272 <.LBB40>: - 272: 47b2 lw a5,12(sp) - -00000274 <.LVL69>: - 274: 46a2 lw a3,8(sp) - 276: 0107d393 srl t2,a5,0x10 - -0000027a <.LVL70>: - 27a: 47a2 lw a5,8(sp) - 27c: 0107d293 srl t0,a5,0x10 - -00000280 <.LBB41>: - 280: 47b2 lw a5,12(sp) - 282: 8ff9 and a5,a5,a4 - 284: 8f75 and a4,a4,a3 - 286: 853e mv a0,a5 - -00000288 <.LVL72>: - 288: 85ba mv a1,a4 - 28a: 00000097 auipc ra,0x0 - 28e: 000080e7 jalr ra # 28a <.LVL72+0x2> - 292: 832a mv t1,a0 - -00000294 <.LBB42>: - 294: 8596 mv a1,t0 - 296: 853e mv a0,a5 - 298: 00000097 auipc ra,0x0 - 29c: 000080e7 jalr ra # 298 <.LBB42+0x4> - 2a0: 87aa mv a5,a0 - -000002a2 <.LBB43>: - 2a2: 85ba mv a1,a4 - 2a4: 851e mv a0,t2 - -000002a6 <.LVL75>: - 2a6: 00000097 auipc ra,0x0 - 2aa: 000080e7 jalr ra # 2a6 <.LVL75> - 2ae: 872a mv a4,a0 - -000002b0 <.LBB44>: - 2b0: 8596 mv a1,t0 - 2b2: 851e mv a0,t2 - -000002b4 <.LVL77>: - 2b4: 00000097 auipc ra,0x0 - 2b8: 000080e7 jalr ra # 2b4 <.LVL77> - -000002bc <.LBE44>: - 2bc: 97ba add a5,a5,a4 - -000002be <.LVL79>: - 2be: 01035693 srl a3,t1,0x10 - 2c2: 96be add a3,a3,a5 - -000002c4 <.LVL80>: - 2c4: 00e6f363 bgeu a3,a4,2ca <.L45> - 2c8: 9522 add a0,a0,s0 - -000002ca <.L45>: - 2ca: 0106d793 srl a5,a3,0x10 - 2ce: 97aa add a5,a5,a0 - 2d0: 63c1 lui t2,0x10 - 2d2: c0be sw a5,64(sp) - -000002d4 <.LVL82>: - 2d4: fff38793 add a5,t2,-1 # ffff <.LLST246+0xdacb> - -000002d8 <.LVL83>: - 2d8: 8efd and a3,a3,a5 - -000002da <.LVL84>: - 2da: 00f37333 and t1,t1,a5 - -000002de <.LVL85>: - 2de: 06c2 sll a3,a3,0x10 - 2e0: 00668733 add a4,a3,t1 - -000002e4 <.LVL86>: - 2e4: c2ba sw a4,68(sp) - -000002e6 <.LBB45>: - 2e6: 4712 lw a4,4(sp) - -000002e8 <.LVL88>: - 2e8: 01075293 srl t0,a4,0x10 - 2ec: 5716 lw a4,100(sp) - 2ee: d03a sw a4,32(sp) - -000002f0 <.LVL89>: - 2f0: 01075413 srl s0,a4,0x10 - -000002f4 <.LBB46>: - 2f4: 4712 lw a4,4(sp) - 2f6: 00f77333 and t1,a4,a5 - 2fa: 5702 lw a4,32(sp) - 2fc: 851a mv a0,t1 - -000002fe <.LVL91>: - 2fe: 8ff9 and a5,a5,a4 - 300: 85be mv a1,a5 - 302: 00000097 auipc ra,0x0 - 306: 000080e7 jalr ra # 302 <.LVL91+0x4> - 30a: 872a mv a4,a0 - -0000030c <.LBB47>: - 30c: 85a2 mv a1,s0 - 30e: 851a mv a0,t1 - -00000310 <.LVL93>: - 310: 00000097 auipc ra,0x0 - 314: 000080e7 jalr ra # 310 <.LVL93> - 318: 832a mv t1,a0 - -0000031a <.LBB48>: - 31a: 85be mv a1,a5 - 31c: 8516 mv a0,t0 - 31e: 00000097 auipc ra,0x0 - 322: 000080e7 jalr ra # 31e <.LBB48+0x4> - 326: 87aa mv a5,a0 - -00000328 <.LBB49>: - 328: 85a2 mv a1,s0 - 32a: 8516 mv a0,t0 - -0000032c <.LVL96>: - 32c: 00000097 auipc ra,0x0 - 330: 000080e7 jalr ra # 32c <.LVL96> - -00000334 <.LBE49>: - 334: 01075693 srl a3,a4,0x10 - 338: 933e add t1,t1,a5 - -0000033a <.LVL98>: - 33a: 9336 add t1,t1,a3 - -0000033c <.LVL99>: - 33c: 00f37363 bgeu t1,a5,342 <.L46> - 340: 951e add a0,a0,t2 - -00000342 <.L46>: - 342: 01035793 srl a5,t1,0x10 - -00000346 <.LVL101>: - 346: 63c1 lui t2,0x10 - 348: 00a78433 add s0,a5,a0 - -0000034c <.LVL102>: - 34c: fff38793 add a5,t2,-1 # ffff <.LLST246+0xdacb> - 350: 00f37333 and t1,t1,a5 - -00000354 <.LVL103>: - 354: 0342 sll t1,t1,0x10 - 356: 8f7d and a4,a4,a5 - -00000358 <.LVL104>: - 358: 971a add a4,a4,t1 - 35a: c4ba sw a4,72(sp) - -0000035c <.LBB50>: - 35c: 4756 lw a4,84(sp) - -0000035e <.LVL106>: - 35e: 0104d293 srl t0,s1,0x10 - 362: c83a sw a4,16(sp) - -00000364 <.LVL107>: - 364: 8341 srl a4,a4,0x10 - 366: d63a sw a4,44(sp) - -00000368 <.LBB51>: - 368: 4742 lw a4,16(sp) - 36a: 00f77333 and t1,a4,a5 - 36e: 8fe5 and a5,a5,s1 - 370: 851a mv a0,t1 - -00000372 <.LVL109>: - 372: 85be mv a1,a5 - 374: 00000097 auipc ra,0x0 - 378: 000080e7 jalr ra # 374 <.LVL109+0x2> - 37c: 872a mv a4,a0 - -0000037e <.LBB52>: - 37e: 8596 mv a1,t0 - 380: 851a mv a0,t1 - -00000382 <.LVL111>: - 382: 00000097 auipc ra,0x0 - 386: 000080e7 jalr ra # 382 <.LVL111> - 38a: 832a mv t1,a0 - -0000038c <.LBB53>: - 38c: 85be mv a1,a5 - 38e: 5532 lw a0,44(sp) - 390: 00000097 auipc ra,0x0 - 394: 000080e7 jalr ra # 390 <.LBB53+0x4> - 398: 87aa mv a5,a0 - -0000039a <.LBB54>: - 39a: 8596 mv a1,t0 - 39c: 5532 lw a0,44(sp) - -0000039e <.LVL114>: - 39e: 00000097 auipc ra,0x0 - 3a2: 000080e7 jalr ra # 39e <.LVL114> - -000003a6 <.LBE54>: - 3a6: 01075693 srl a3,a4,0x10 - 3aa: 933e add t1,t1,a5 - -000003ac <.LVL116>: - 3ac: 9336 add t1,t1,a3 - -000003ae <.LVL117>: - 3ae: 00f37363 bgeu t1,a5,3b4 <.L47> - 3b2: 951e add a0,a0,t2 - -000003b4 <.L47>: - 3b4: 01035793 srl a5,t1,0x10 - -000003b8 <.LVL119>: - 3b8: 460a lw a2,128(sp) - 3ba: 953e add a0,a0,a5 - -000003bc <.LVL120>: - 3bc: 57d2 lw a5,52(sp) - 3be: 62c1 lui t0,0x10 - 3c0: fff28593 add a1,t0,-1 # ffff <.LLST246+0xdacb> - 3c4: 00f603b3 add t2,a2,a5 - -000003c8 <.LBB55>: - 3c8: 57c2 lw a5,48(sp) - 3ca: 00c3b633 sltu a2,t2,a2 - -000003ce <.LBB56>: - 3ce: 00b37333 and t1,t1,a1 - -000003d2 <.LBB57>: - 3d2: 00c786b3 add a3,a5,a2 - 3d6: 47d2 lw a5,20(sp) - -000003d8 <.LBB58>: - 3d8: 0342 sll t1,t1,0x10 - 3da: 8f6d and a4,a4,a1 - -000003dc <.LBB59>: - 3dc: 96be add a3,a3,a5 - 3de: 57f2 lw a5,60(sp) - -000003e0 <.LBB60>: - 3e0: 971a add a4,a4,t1 - -000003e2 <.LBB61>: - 3e2: 5362 lw t1,56(sp) - 3e4: 979e add a5,a5,t2 - 3e6: c13e sw a5,128(sp) - -000003e8 <.LVL124>: - 3e8: 9336 add t1,t1,a3 - -000003ea <.LVL125>: - 3ea: 0077b7b3 sltu a5,a5,t2 - -000003ee <.LVL126>: - 3ee: 979a add a5,a5,t1 - -000003f0 <.LVL127>: - 3f0: 00d333b3 sltu t2,t1,a3 - -000003f4 <.LVL128>: - 3f4: 0067b333 sltu t1,a5,t1 - -000003f8 <.LBB63>: - 3f8: 00c6b6b3 sltu a3,a3,a2 - -000003fc <.LBB64>: - 3fc: 0063e3b3 or t2,t2,t1 - -00000400 <.LVL131>: - 400: 93b6 add t2,t2,a3 - -00000402 <.LBB65>: - 402: 4696 lw a3,68(sp) - 404: 4326 lw t1,72(sp) - -00000406 <.LVL132>: - 406: 00d78633 add a2,a5,a3 - -0000040a <.LVL133>: - 40a: 4686 lw a3,64(sp) - 40c: 00f637b3 sltu a5,a2,a5 - -00000410 <.LVL134>: - 410: 9332 add t1,t1,a2 - 412: 969e add a3,a3,t2 - -00000414 <.LVL135>: - 414: 97b6 add a5,a5,a3 - -00000416 <.LBB66>: - 416: 943e add s0,s0,a5 - -00000418 <.LVL137>: - 418: 00c33633 sltu a2,t1,a2 - -0000041c <.LVL138>: - 41c: 9622 add a2,a2,s0 - -0000041e <.LVL139>: - 41e: 971a add a4,a4,t1 - -00000420 <.LVL140>: - 420: 9532 add a0,a0,a2 - -00000422 <.LBB67>: - 422: c33a sw a4,132(sp) - 424: 00673733 sltu a4,a4,t1 - -00000428 <.LBB68>: - 428: 0076b3b3 sltu t2,a3,t2 - -0000042c <.LVL142>: - 42c: 972a add a4,a4,a0 - 42e: 00d7b6b3 sltu a3,a5,a3 - -00000432 <.LBB69>: - 432: 00f437b3 sltu a5,s0,a5 - -00000436 <.LVL144>: - 436: 00863433 sltu s0,a2,s0 - -0000043a <.LBB70>: - 43a: 00d3e6b3 or a3,t2,a3 - -0000043e <.LBB71>: - 43e: 8fc1 or a5,a5,s0 - -00000440 <.LBB72>: - 440: c53a sw a4,136(sp) - 442: 00c53633 sltu a2,a0,a2 - 446: 00a73733 sltu a4,a4,a0 - -0000044a <.LBB73>: - 44a: 97b6 add a5,a5,a3 - -0000044c <.LBB74>: - 44c: 8e59 or a2,a2,a4 - 44e: 963e add a2,a2,a5 - -00000450 <.LBB75>: - 450: 4792 lw a5,4(sp) - -00000452 <.LBB80>: - 452: c732 sw a2,140(sp) - -00000454 <.LBB81>: - 454: 0107d313 srl t1,a5,0x10 - -00000458 <.LVL150>: - 458: 57a6 lw a5,104(sp) - 45a: ca3e sw a5,20(sp) - -0000045c <.LVL151>: - 45c: 0107d713 srl a4,a5,0x10 - -00000460 <.LBB76>: - 460: 4792 lw a5,4(sp) - 462: 00b7f3b3 and t2,a5,a1 - 466: 47d2 lw a5,20(sp) - 468: 851e mv a0,t2 - 46a: 00b7f433 and s0,a5,a1 - 46e: 85a2 mv a1,s0 - 470: 00000097 auipc ra,0x0 - 474: 000080e7 jalr ra # 470 <.LBB76+0x10> - 478: 87aa mv a5,a0 - -0000047a <.LBB77>: - 47a: 85ba mv a1,a4 - 47c: 851e mv a0,t2 - -0000047e <.LVL154>: - 47e: 00000097 auipc ra,0x0 - 482: 000080e7 jalr ra # 47e <.LVL154> - 486: 83aa mv t2,a0 - -00000488 <.LBB78>: - 488: 85a2 mv a1,s0 - 48a: 851a mv a0,t1 - 48c: 00000097 auipc ra,0x0 - 490: 000080e7 jalr ra # 48c <.LBB78+0x4> - 494: 842a mv s0,a0 - -00000496 <.LBB79>: - 496: 85ba mv a1,a4 - 498: 851a mv a0,t1 - 49a: 00000097 auipc ra,0x0 - 49e: 000080e7 jalr ra # 49a <.LBB79+0x4> - -000004a2 <.LBE79>: - 4a2: 0107d713 srl a4,a5,0x10 - -000004a6 <.LVL158>: - 4a6: 93a2 add t2,t2,s0 - -000004a8 <.LVL159>: - 4a8: 93ba add t2,t2,a4 - -000004aa <.LVL160>: - 4aa: 0083f363 bgeu t2,s0,4b0 <.L74> - 4ae: 9516 add a0,a0,t0 - -000004b0 <.L74>: - 4b0: 0103d713 srl a4,t2,0x10 - 4b4: 972a add a4,a4,a0 - 4b6: d63a sw a4,44(sp) - -000004b8 <.LVL162>: - 4b8: 6741 lui a4,0x10 - -000004ba <.LVL163>: - 4ba: fff70693 add a3,a4,-1 # ffff <.LLST246+0xdacb> - 4be: 00d3f3b3 and t2,t2,a3 - -000004c2 <.LVL164>: - 4c2: 03c2 sll t2,t2,0x10 - 4c4: 8ff5 and a5,a5,a3 - -000004c6 <.LVL165>: - 4c6: 979e add a5,a5,t2 - 4c8: d83e sw a5,48(sp) - -000004ca <.LBB82>: - 4ca: 47e6 lw a5,88(sp) - -000004cc <.LVL167>: - 4cc: 0104d313 srl t1,s1,0x10 - -000004d0 <.LVL168>: - 4d0: 00d7f3b3 and t2,a5,a3 - 4d4: c23e sw a5,4(sp) - -000004d6 <.LVL169>: - 4d6: 0107d293 srl t0,a5,0x10 - -000004da <.LBB83>: - 4da: 00d4f7b3 and a5,s1,a3 - 4de: 851e mv a0,t2 - -000004e0 <.LVL171>: - 4e0: 85be mv a1,a5 - 4e2: 00000097 auipc ra,0x0 - 4e6: 000080e7 jalr ra # 4e2 <.LVL171+0x2> - 4ea: 842a mv s0,a0 - -000004ec <.LBB84>: - 4ec: 859a mv a1,t1 - 4ee: 851e mv a0,t2 - 4f0: 00000097 auipc ra,0x0 - 4f4: 000080e7 jalr ra # 4f0 <.LBB84+0x4> - 4f8: 83aa mv t2,a0 - -000004fa <.LBB85>: - 4fa: 85be mv a1,a5 - 4fc: 8516 mv a0,t0 - 4fe: 00000097 auipc ra,0x0 - 502: 000080e7 jalr ra # 4fe <.LBB85+0x4> - 506: 87aa mv a5,a0 - -00000508 <.LBB86>: - 508: 859a mv a1,t1 - 50a: 8516 mv a0,t0 - -0000050c <.LVL175>: - 50c: 00000097 auipc ra,0x0 - 510: 000080e7 jalr ra # 50c <.LVL175> - -00000514 <.LBE86>: - 514: 01045693 srl a3,s0,0x10 - 518: 93be add t2,t2,a5 - -0000051a <.LVL177>: - 51a: 93b6 add t2,t2,a3 - -0000051c <.LVL178>: - 51c: 00f3f363 bgeu t2,a5,522 <.L75> - 520: 953a add a0,a0,a4 - -00000522 <.L75>: - 522: 6741 lui a4,0x10 - 524: fff70693 add a3,a4,-1 # ffff <.LLST246+0xdacb> - 528: 0103d793 srl a5,t2,0x10 - -0000052c <.LVL180>: - 52c: 00d3f3b3 and t2,t2,a3 - -00000530 <.LVL181>: - 530: 97aa add a5,a5,a0 - 532: 8c75 and s0,s0,a3 - -00000534 <.LVL182>: - 534: 03c2 sll t2,t2,0x10 - 536: 4632 lw a2,12(sp) - 538: da3e sw a5,52(sp) - -0000053a <.LVL183>: - 53a: 008387b3 add a5,t2,s0 - -0000053e <.LVL184>: - 53e: dc3e sw a5,56(sp) - -00000540 <.LBB87>: - 540: 47b2 lw a5,12(sp) - -00000542 <.LVL186>: - 542: 00d673b3 and t2,a2,a3 - 546: 5602 lw a2,32(sp) - 548: 0107d293 srl t0,a5,0x10 - -0000054c <.LVL187>: - 54c: 5782 lw a5,32(sp) - 54e: 00d67433 and s0,a2,a3 - -00000552 <.LBB88>: - 552: 851e mv a0,t2 - -00000554 <.LBE88>: - 554: 83c1 srl a5,a5,0x10 - -00000556 <.LBB89>: - 556: 85a2 mv a1,s0 - 558: 00000097 auipc ra,0x0 - 55c: 000080e7 jalr ra # 558 <.LBB89+0x2> - 560: 832a mv t1,a0 - -00000562 <.LBB90>: - 562: 85be mv a1,a5 - 564: 851e mv a0,t2 - 566: 00000097 auipc ra,0x0 - 56a: 000080e7 jalr ra # 566 <.LBB90+0x4> - 56e: 83aa mv t2,a0 - -00000570 <.LBB91>: - 570: 85a2 mv a1,s0 - 572: 8516 mv a0,t0 - 574: 00000097 auipc ra,0x0 - 578: 000080e7 jalr ra # 574 <.LBB91+0x4> - 57c: 842a mv s0,a0 - -0000057e <.LBB92>: - 57e: 85be mv a1,a5 - 580: 8516 mv a0,t0 - 582: 00000097 auipc ra,0x0 - 586: 000080e7 jalr ra # 582 <.LBB92+0x4> - -0000058a <.LBE92>: - 58a: 01035793 srl a5,t1,0x10 - -0000058e <.LVL194>: - 58e: 93a2 add t2,t2,s0 - -00000590 <.LVL195>: - 590: 979e add a5,a5,t2 - -00000592 <.LVL196>: - 592: 0087f363 bgeu a5,s0,598 <.L76> - 596: 953a add a0,a0,a4 - -00000598 <.L76>: - 598: 46c2 lw a3,16(sp) - -0000059a <.LBB98>: - 59a: 0107d713 srl a4,a5,0x10 - 59e: 972a add a4,a4,a0 - -000005a0 <.LBB99>: - 5a0: 0106d393 srl t2,a3,0x10 - 5a4: 46a2 lw a3,8(sp) - -000005a6 <.LBB100>: - 5a6: 6441 lui s0,0x10 - -000005a8 <.LVL198>: - 5a8: c63a sw a4,12(sp) - -000005aa <.LBB101>: - 5aa: 0106d493 srl s1,a3,0x10 - -000005ae <.LVL200>: - 5ae: 46c2 lw a3,16(sp) - -000005b0 <.LBB102>: - 5b0: fff40713 add a4,s0,-1 # ffff <.LLST246+0xdacb> - -000005b4 <.LVL201>: - 5b4: 8ff9 and a5,a5,a4 - -000005b6 <.LVL202>: - 5b6: 00e6f2b3 and t0,a3,a4 - -000005ba <.LVL203>: - 5ba: 46a2 lw a3,8(sp) - 5bc: 00e37333 and t1,t1,a4 - -000005c0 <.LVL204>: - 5c0: 07c2 sll a5,a5,0x10 - 5c2: 8f75 and a4,a4,a3 - 5c4: 979a add a5,a5,t1 - -000005c6 <.LBB103>: - 5c6: 8516 mv a0,t0 - -000005c8 <.LVL206>: - 5c8: 85ba mv a1,a4 - 5ca: 00000097 auipc ra,0x0 - 5ce: 000080e7 jalr ra # 5ca <.LVL206+0x2> - 5d2: 832a mv t1,a0 - -000005d4 <.LBB95>: - 5d4: 85a6 mv a1,s1 - 5d6: 8516 mv a0,t0 - 5d8: 00000097 auipc ra,0x0 - 5dc: 000080e7 jalr ra # 5d8 <.LBB95+0x4> - 5e0: 82aa mv t0,a0 - -000005e2 <.LBB96>: - 5e2: 85ba mv a1,a4 - 5e4: 851e mv a0,t2 - 5e6: 00000097 auipc ra,0x0 - 5ea: 000080e7 jalr ra # 5e6 <.LBB96+0x4> - 5ee: 872a mv a4,a0 - -000005f0 <.LBB97>: - 5f0: 85a6 mv a1,s1 - 5f2: 851e mv a0,t2 - -000005f4 <.LVL210>: - 5f4: 00000097 auipc ra,0x0 - 5f8: 000080e7 jalr ra # 5f4 <.LVL210> - -000005fc <.LBE97>: - 5fc: 01035693 srl a3,t1,0x10 - 600: 92ba add t0,t0,a4 - -00000602 <.LVL212>: - 602: 92b6 add t0,t0,a3 - -00000604 <.LVL213>: - 604: 00e2f363 bgeu t0,a4,60a <.L77> - 608: 9522 add a0,a0,s0 - -0000060a <.L77>: - 60a: 63c1 lui t2,0x10 - 60c: fff38593 add a1,t2,-1 # ffff <.LLST246+0xdacb> - 610: 44ba lw s1,140(sp) - -00000612 <.LVL215>: - 612: 56b2 lw a3,44(sp) - 614: 0102d713 srl a4,t0,0x10 - -00000618 <.LVL216>: - 618: 462a lw a2,136(sp) - 61a: 953a add a0,a0,a4 - -0000061c <.LVL217>: - 61c: 00b2f2b3 and t0,t0,a1 - -00000620 <.LVL218>: - 620: 5742 lw a4,48(sp) - 622: 02c2 sll t0,t0,0x10 - 624: 00b37333 and t1,t1,a1 - -00000628 <.LVL219>: - 628: 9316 add t1,t1,t0 - -0000062a <.LBB104>: - 62a: 00d482b3 add t0,s1,a3 - 62e: 56e2 lw a3,56(sp) - 630: 9732 add a4,a4,a2 - -00000632 <.LVL221>: - 632: 5452 lw s0,52(sp) - 634: 00c73633 sltu a2,a4,a2 - -00000638 <.LVL222>: - 638: 9616 add a2,a2,t0 - -0000063a <.LBB105>: - 63a: 96ba add a3,a3,a4 - -0000063c <.LVL224>: - 63c: 9432 add s0,s0,a2 - -0000063e <.LVL225>: - 63e: 00e6b733 sltu a4,a3,a4 - -00000642 <.LVL226>: - 642: 9722 add a4,a4,s0 - -00000644 <.LBB106>: - 644: 0092b4b3 sltu s1,t0,s1 - -00000648 <.LVL228>: - 648: 005632b3 sltu t0,a2,t0 - -0000064c <.LBB107>: - 64c: 00c43633 sltu a2,s0,a2 - -00000650 <.LVL230>: - 650: 00873433 sltu s0,a4,s0 - -00000654 <.LVL231>: - 654: 8e41 or a2,a2,s0 - -00000656 <.LVL232>: - 656: 4432 lw s0,12(sp) - -00000658 <.LVL233>: - 658: 97b6 add a5,a5,a3 - -0000065a <.LBB108>: - 65a: 0054e2b3 or t0,s1,t0 - -0000065e <.LBB109>: - 65e: 9616 add a2,a2,t0 - -00000660 <.LBB110>: - 660: 00d7b6b3 sltu a3,a5,a3 - -00000664 <.LVL237>: - 664: 008702b3 add t0,a4,s0 - -00000668 <.LVL238>: - 668: 9696 add a3,a3,t0 - -0000066a <.LVL239>: - 66a: 933e add t1,t1,a5 - -0000066c <.LVL240>: - 66c: 9536 add a0,a0,a3 - -0000066e <.LBB111>: - 66e: c51a sw t1,136(sp) - -00000670 <.LVL242>: - 670: 00f33333 sltu t1,t1,a5 - 674: 932a add t1,t1,a0 - -00000676 <.LBB112>: - 676: 00e2b733 sltu a4,t0,a4 - -0000067a <.LVL243>: - 67a: 0056b2b3 sltu t0,a3,t0 - -0000067e <.LVL244>: - 67e: 00576733 or a4,a4,t0 - -00000682 <.LBB113>: - 682: c71a sw t1,140(sp) - 684: 00d536b3 sltu a3,a0,a3 - 688: 00a33333 sltu t1,t1,a0 - -0000068c <.LBB114>: - 68c: 9732 add a4,a4,a2 - -0000068e <.LBB115>: - 68e: 0066e6b3 or a3,a3,t1 - 692: 96ba add a3,a3,a4 - -00000694 <.LBB116>: - 694: 5316 lw t1,100(sp) - 696: 4742 lw a4,16(sp) - 698: 47c2 lw a5,16(sp) - 69a: 00b374b3 and s1,t1,a1 - 69e: 00b77433 and s0,a4,a1 - 6a2: 0107d293 srl t0,a5,0x10 - -000006a6 <.LBB121>: - 6a6: c936 sw a3,144(sp) - -000006a8 <.LBB122>: - 6a8: 01035793 srl a5,t1,0x10 - -000006ac <.LBB117>: - 6ac: 8522 mv a0,s0 - 6ae: 85a6 mv a1,s1 - 6b0: 00000097 auipc ra,0x0 - 6b4: 000080e7 jalr ra # 6b0 <.LBB117+0x4> - 6b8: 872a mv a4,a0 - -000006ba <.LBB118>: - 6ba: 85be mv a1,a5 - 6bc: 8522 mv a0,s0 - -000006be <.LVL250>: - 6be: 00000097 auipc ra,0x0 - 6c2: 000080e7 jalr ra # 6be <.LVL250> - 6c6: 842a mv s0,a0 - -000006c8 <.LBB119>: - 6c8: 85a6 mv a1,s1 - 6ca: 8516 mv a0,t0 - 6cc: 00000097 auipc ra,0x0 - 6d0: 000080e7 jalr ra # 6cc <.LBB119+0x4> - 6d4: 84aa mv s1,a0 - -000006d6 <.LBB120>: - 6d6: 85be mv a1,a5 - 6d8: 8516 mv a0,t0 - 6da: 00000097 auipc ra,0x0 - 6de: 000080e7 jalr ra # 6da <.LBB120+0x4> - -000006e2 <.LBE120>: - 6e2: 01075793 srl a5,a4,0x10 - -000006e6 <.LVL254>: - 6e6: 9426 add s0,s0,s1 - -000006e8 <.LVL255>: - 6e8: 943e add s0,s0,a5 - -000006ea <.LVL256>: - 6ea: 00947363 bgeu s0,s1,6f0 <.L102> - 6ee: 951e add a0,a0,t2 - -000006f0 <.L102>: - 6f0: 01045793 srl a5,s0,0x10 - 6f4: 97aa add a5,a5,a0 - 6f6: 63c1 lui t2,0x10 - 6f8: c43e sw a5,8(sp) - -000006fa <.LVL258>: - 6fa: fff38793 add a5,t2,-1 # ffff <.LLST246+0xdacb> - -000006fe <.LVL259>: - 6fe: 8c7d and s0,s0,a5 - -00000700 <.LVL260>: - 700: 0442 sll s0,s0,0x10 - 702: 8f7d and a4,a4,a5 - -00000704 <.LVL261>: - 704: 9722 add a4,a4,s0 - -00000706 <.LBB123>: - 706: 42c6 lw t0,80(sp) - -00000708 <.LBB128>: - 708: c63a sw a4,12(sp) - -0000070a <.LBB129>: - 70a: 4752 lw a4,20(sp) - -0000070c <.LVL264>: - 70c: 0102d413 srl s0,t0,0x10 - -00000710 <.LVL265>: - 710: 00f2f2b3 and t0,t0,a5 - -00000714 <.LVL266>: - 714: 8ff9 and a5,a5,a4 - 716: 01075493 srl s1,a4,0x10 - -0000071a <.LBB124>: - 71a: 8516 mv a0,t0 - -0000071c <.LVL268>: - 71c: 85be mv a1,a5 - 71e: 00000097 auipc ra,0x0 - 722: 000080e7 jalr ra # 71e <.LVL268+0x2> - 726: 872a mv a4,a0 - -00000728 <.LBB125>: - 728: 85a6 mv a1,s1 - 72a: 8516 mv a0,t0 - -0000072c <.LVL270>: - 72c: 00000097 auipc ra,0x0 - 730: 000080e7 jalr ra # 72c <.LVL270> - 734: 82aa mv t0,a0 - -00000736 <.LBB126>: - 736: 85be mv a1,a5 - 738: 8522 mv a0,s0 - 73a: 00000097 auipc ra,0x0 - 73e: 000080e7 jalr ra # 73a <.LBB126+0x4> - 742: 87aa mv a5,a0 - -00000744 <.LBB127>: - 744: 85a6 mv a1,s1 - 746: 8522 mv a0,s0 - -00000748 <.LVL273>: - 748: 00000097 auipc ra,0x0 - 74c: 000080e7 jalr ra # 748 <.LVL273> - -00000750 <.LBE127>: - 750: 01075693 srl a3,a4,0x10 - 754: 92be add t0,t0,a5 - -00000756 <.LVL275>: - 756: 92b6 add t0,t0,a3 - -00000758 <.LVL276>: - 758: 00f2f363 bgeu t0,a5,75e <.L103> - 75c: 951e add a0,a0,t2 - -0000075e <.L103>: - 75e: 0102d793 srl a5,t0,0x10 - -00000762 <.LVL278>: - 762: 97aa add a5,a5,a0 - 764: 6441 lui s0,0x10 - -00000766 <.LVL279>: - 766: c83e sw a5,16(sp) - -00000768 <.LVL280>: - 768: fff40793 add a5,s0,-1 # ffff <.LLST246+0xdacb> - -0000076c <.LVL281>: - 76c: 00f2f2b3 and t0,t0,a5 - -00000770 <.LVL282>: - 770: 02c2 sll t0,t0,0x10 - 772: 8f7d and a4,a4,a5 - -00000774 <.LVL283>: - 774: 9716 add a4,a4,t0 - 776: d03a sw a4,32(sp) - -00000778 <.LBB130>: - 778: 5286 lw t0,96(sp) - 77a: 4712 lw a4,4(sp) - -0000077c <.LVL285>: - 77c: 0102d493 srl s1,t0,0x10 - 780: 01075393 srl t2,a4,0x10 - -00000784 <.LBB131>: - 784: 00f2f2b3 and t0,t0,a5 - -00000788 <.LVL287>: - 788: 8f7d and a4,a4,a5 - 78a: 853a mv a0,a4 - -0000078c <.LVL288>: - 78c: 8596 mv a1,t0 - 78e: 00000097 auipc ra,0x0 - 792: 000080e7 jalr ra # 78e <.LVL288+0x2> - 796: 87aa mv a5,a0 - -00000798 <.LBB132>: - 798: 85a6 mv a1,s1 - 79a: 853a mv a0,a4 - -0000079c <.LVL290>: - 79c: 00000097 auipc ra,0x0 - 7a0: 000080e7 jalr ra # 79c <.LVL290> - 7a4: 872a mv a4,a0 - -000007a6 <.LBB133>: - 7a6: 8596 mv a1,t0 - 7a8: 851e mv a0,t2 - -000007aa <.LVL292>: - 7aa: 00000097 auipc ra,0x0 - 7ae: 000080e7 jalr ra # 7aa <.LVL292> - 7b2: 82aa mv t0,a0 - -000007b4 <.LBB134>: - 7b4: 85a6 mv a1,s1 - 7b6: 851e mv a0,t2 - 7b8: 00000097 auipc ra,0x0 - 7bc: 000080e7 jalr ra # 7b8 <.LBB134+0x4> - -000007c0 <.LBE134>: - 7c0: 0107d693 srl a3,a5,0x10 - 7c4: 9716 add a4,a4,t0 - -000007c6 <.LVL295>: - 7c6: 9736 add a4,a4,a3 - -000007c8 <.LVL296>: - 7c8: 00577363 bgeu a4,t0,7ce <.L104> - 7cc: 9522 add a0,a0,s0 - -000007ce <.L104>: - 7ce: 62c1 lui t0,0x10 - -000007d0 <.LVL298>: - 7d0: fff28493 add s1,t0,-1 # ffff <.LLST246+0xdacb> - -000007d4 <.LVL299>: - 7d4: 01075693 srl a3,a4,0x10 - 7d8: 8f65 and a4,a4,s1 - -000007da <.LVL300>: - 7da: 0742 sll a4,a4,0x10 - 7dc: 8fe5 and a5,a5,s1 - -000007de <.LVL301>: - 7de: 97ba add a5,a5,a4 - 7e0: d83e sw a5,48(sp) - -000007e2 <.LBB135>: - 7e2: 4756 lw a4,84(sp) - 7e4: 47d2 lw a5,20(sp) - -000007e6 <.LBB140>: - 7e6: 96aa add a3,a3,a0 - -000007e8 <.LBB141>: - 7e8: 01075413 srl s0,a4,0x10 - 7ec: 8f65 and a4,a4,s1 - 7ee: 8cfd and s1,s1,a5 - -000007f0 <.LBB142>: - 7f0: d636 sw a3,44(sp) - -000007f2 <.LBB143>: - 7f2: 0107d393 srl t2,a5,0x10 - -000007f6 <.LBB136>: - 7f6: 853a mv a0,a4 - -000007f8 <.LVL304>: - 7f8: 85a6 mv a1,s1 - 7fa: 00000097 auipc ra,0x0 - 7fe: 000080e7 jalr ra # 7fa <.LVL304+0x2> - -00000802 <.LVL305>: - 802: 87aa mv a5,a0 - -00000804 <.LBB137>: - 804: 859e mv a1,t2 - 806: 853a mv a0,a4 - -00000808 <.LVL307>: - 808: 00000097 auipc ra,0x0 - 80c: 000080e7 jalr ra # 808 <.LVL307> - 810: 872a mv a4,a0 - -00000812 <.LBB138>: - 812: 85a6 mv a1,s1 - 814: 8522 mv a0,s0 - -00000816 <.LVL309>: - 816: 00000097 auipc ra,0x0 - 81a: 000080e7 jalr ra # 816 <.LVL309> - 81e: 84aa mv s1,a0 - -00000820 <.LBB139>: - 820: 859e mv a1,t2 - 822: 8522 mv a0,s0 - 824: 00000097 auipc ra,0x0 - 828: 000080e7 jalr ra # 824 <.LBB139+0x4> - -0000082c <.LBE139>: - 82c: 0107d693 srl a3,a5,0x10 - 830: 9726 add a4,a4,s1 - -00000832 <.LVL312>: - 832: 9736 add a4,a4,a3 - -00000834 <.LVL313>: - 834: 00977363 bgeu a4,s1,83a <.L105> - 838: 9516 add a0,a0,t0 - -0000083a <.L105>: - 83a: 01075693 srl a3,a4,0x10 - 83e: 96aa add a3,a3,a0 - 840: 63c1 lui t2,0x10 - -00000842 <.LVL315>: - 842: ca36 sw a3,20(sp) - -00000844 <.LVL316>: - 844: fff38693 add a3,t2,-1 # ffff <.LLST246+0xdacb> - -00000848 <.LVL317>: - 848: 8f75 and a4,a4,a3 - -0000084a <.LVL318>: - 84a: 8ff5 and a5,a5,a3 - -0000084c <.LVL319>: - 84c: 0742 sll a4,a4,0x10 - 84e: 973e add a4,a4,a5 - -00000850 <.LBB144>: - 850: 4792 lw a5,4(sp) - 852: 01035413 srl s0,t1,0x10 - -00000856 <.LVL321>: - 856: 00d37333 and t1,t1,a3 - -0000085a <.LVL322>: - 85a: 0107d493 srl s1,a5,0x10 - -0000085e <.LBB145>: - 85e: 8ff5 and a5,a5,a3 - 860: 853e mv a0,a5 - -00000862 <.LVL324>: - 862: 859a mv a1,t1 - 864: 00000097 auipc ra,0x0 - 868: 000080e7 jalr ra # 864 <.LVL324+0x2> - 86c: 82aa mv t0,a0 - -0000086e <.LBB146>: - 86e: 85a2 mv a1,s0 - 870: 853e mv a0,a5 - 872: 00000097 auipc ra,0x0 - 876: 000080e7 jalr ra # 872 <.LBB146+0x4> - 87a: 87aa mv a5,a0 - -0000087c <.LBB147>: - 87c: 859a mv a1,t1 - 87e: 8526 mv a0,s1 - -00000880 <.LVL327>: - 880: 00000097 auipc ra,0x0 - 884: 000080e7 jalr ra # 880 <.LVL327> - 888: 832a mv t1,a0 - -0000088a <.LBB148>: - 88a: 85a2 mv a1,s0 - 88c: 8526 mv a0,s1 - 88e: 00000097 auipc ra,0x0 - 892: 000080e7 jalr ra # 88e <.LBB148+0x4> - -00000896 <.LBE148>: - 896: 979a add a5,a5,t1 - -00000898 <.LVL330>: - 898: 0102d693 srl a3,t0,0x10 - 89c: 97b6 add a5,a5,a3 - -0000089e <.LVL331>: - 89e: 0067f363 bgeu a5,t1,8a4 <.L106> - 8a2: 951e add a0,a0,t2 - -000008a4 <.L106>: - 8a4: 63c1 lui t2,0x10 - 8a6: fff38313 add t1,t2,-1 # ffff <.LLST246+0xdacb> - -000008aa <.LVL333>: - 8aa: 0107d693 srl a3,a5,0x10 - 8ae: 0067f7b3 and a5,a5,t1 - -000008b2 <.LVL334>: - 8b2: 07c2 sll a5,a5,0x10 - 8b4: 0062f2b3 and t0,t0,t1 - -000008b8 <.LVL335>: - 8b8: 9536 add a0,a0,a3 - -000008ba <.LVL336>: - 8ba: 92be add t0,t0,a5 - -000008bc <.LBB149>: - 8bc: 46ba lw a3,140(sp) - 8be: 47b2 lw a5,12(sp) - 8c0: 5582 lw a1,32(sp) - 8c2: 444a lw s0,144(sp) - -000008c4 <.LVL338>: - 8c4: 4622 lw a2,8(sp) - 8c6: 97b6 add a5,a5,a3 - -000008c8 <.LVL339>: - 8c8: 00b784b3 add s1,a5,a1 - -000008cc <.LVL340>: - 8cc: 45c2 lw a1,16(sp) - 8ce: 9622 add a2,a2,s0 - -000008d0 <.LVL341>: - 8d0: 00d7b6b3 sltu a3,a5,a3 - -000008d4 <.LVL342>: - 8d4: 96b2 add a3,a3,a2 - -000008d6 <.LBB150>: - 8d6: 95b6 add a1,a1,a3 - -000008d8 <.LVL344>: - 8d8: 00f4b7b3 sltu a5,s1,a5 - -000008dc <.LVL345>: - 8dc: 97ae add a5,a5,a1 - -000008de <.LBB151>: - 8de: 00863433 sltu s0,a2,s0 - -000008e2 <.LVL347>: - 8e2: 00c6b633 sltu a2,a3,a2 - -000008e6 <.LBB152>: - 8e6: 00d5b6b3 sltu a3,a1,a3 - -000008ea <.LVL349>: - 8ea: 00b7b5b3 sltu a1,a5,a1 - -000008ee <.LBB153>: - 8ee: 8e41 or a2,a2,s0 - -000008f0 <.LBB154>: - 8f0: 8ecd or a3,a3,a1 - -000008f2 <.LVL352>: - 8f2: 96b2 add a3,a3,a2 - -000008f4 <.LBB155>: - 8f4: 5642 lw a2,48(sp) - 8f6: 55b2 lw a1,44(sp) - -000008f8 <.LVL353>: - 8f8: 9626 add a2,a2,s1 - 8fa: 95be add a1,a1,a5 - 8fc: c732 sw a2,140(sp) - -000008fe <.LVL354>: - 8fe: 00963633 sltu a2,a2,s1 - -00000902 <.LVL355>: - 902: 962e add a2,a2,a1 - -00000904 <.LVL356>: - 904: 00f5b7b3 sltu a5,a1,a5 - -00000908 <.LVL357>: - 908: 00b635b3 sltu a1,a2,a1 - -0000090c <.LVL358>: - 90c: 8fcd or a5,a5,a1 - -0000090e <.LVL359>: - 90e: 97b6 add a5,a5,a3 - -00000910 <.LBB156>: - 910: 46d2 lw a3,20(sp) - 912: 9732 add a4,a4,a2 - -00000914 <.LVL360>: - 914: 00c73633 sltu a2,a4,a2 - -00000918 <.LVL361>: - 918: 96be add a3,a3,a5 - -0000091a <.LVL362>: - 91a: 9636 add a2,a2,a3 - -0000091c <.LBB157>: - 91c: 92ba add t0,t0,a4 - -0000091e <.LVL364>: - 91e: 9532 add a0,a0,a2 - -00000920 <.LVL365>: - 920: c916 sw t0,144(sp) - -00000922 <.LVL366>: - 922: 00e2b2b3 sltu t0,t0,a4 - -00000926 <.LVL367>: - 926: 92aa add t0,t0,a0 - -00000928 <.LVL368>: - 928: cb16 sw t0,148(sp) - -0000092a <.LBB158>: - 92a: 00f6b7b3 sltu a5,a3,a5 - -0000092e <.LBB159>: - 92e: 00a2b2b3 sltu t0,t0,a0 - -00000932 <.LBB160>: - 932: 00d636b3 sltu a3,a2,a3 - -00000936 <.LBB161>: - 936: 00c53633 sltu a2,a0,a2 - -0000093a <.LBB162>: - 93a: 4766 lw a4,88(sp) - -0000093c <.LBB167>: - 93c: 00566633 or a2,a2,t0 - -00000940 <.LBB168>: - 940: 52a6 lw t0,104(sp) - -00000942 <.LBB169>: - 942: 8fd5 or a5,a5,a3 - -00000944 <.LBB170>: - 944: 97b2 add a5,a5,a2 - -00000946 <.LBB171>: - 946: 01075493 srl s1,a4,0x10 - -0000094a <.LVL377>: - 94a: 0102d413 srl s0,t0,0x10 - 94e: 00677733 and a4,a4,t1 - 952: 0062f2b3 and t0,t0,t1 - -00000956 <.LBB172>: - 956: cd3e sw a5,152(sp) - -00000958 <.LBB163>: - 958: 853a mv a0,a4 - 95a: 8596 mv a1,t0 - 95c: 00000097 auipc ra,0x0 - 960: 000080e7 jalr ra # 95c <.LBB163+0x4> - 964: 87aa mv a5,a0 - -00000966 <.LBB164>: - 966: 85a2 mv a1,s0 - 968: 853a mv a0,a4 - -0000096a <.LVL380>: - 96a: 00000097 auipc ra,0x0 - 96e: 000080e7 jalr ra # 96a <.LVL380> - 972: 872a mv a4,a0 - -00000974 <.LBB165>: - 974: 8596 mv a1,t0 - 976: 8526 mv a0,s1 - -00000978 <.LVL382>: - 978: 00000097 auipc ra,0x0 - 97c: 000080e7 jalr ra # 978 <.LVL382> - 980: 82aa mv t0,a0 - -00000982 <.LBB166>: - 982: 85a2 mv a1,s0 - 984: 8526 mv a0,s1 - 986: 00000097 auipc ra,0x0 - 98a: 000080e7 jalr ra # 986 <.LBB166+0x4> - -0000098e <.LBE166>: - 98e: 0107d693 srl a3,a5,0x10 - 992: 9716 add a4,a4,t0 - -00000994 <.LVL385>: - 994: 9736 add a4,a4,a3 - -00000996 <.LVL386>: - 996: 00577363 bgeu a4,t0,99c <.L137> - 99a: 951e add a0,a0,t2 - -0000099c <.L137>: - 99c: 006776b3 and a3,a4,t1 - 9a0: 465a lw a2,148(sp) - 9a2: 0067f7b3 and a5,a5,t1 - -000009a6 <.LVL388>: - 9a6: 06c2 sll a3,a3,0x10 - 9a8: 96be add a3,a3,a5 - 9aa: 01075793 srl a5,a4,0x10 - -000009ae <.LBB176>: - 9ae: 476a lw a4,152(sp) - -000009b0 <.LVL389>: - 9b0: 96b2 add a3,a3,a2 - -000009b2 <.LVL390>: - 9b2: 00c6b633 sltu a2,a3,a2 - 9b6: 97ba add a5,a5,a4 - 9b8: 97b2 add a5,a5,a2 - 9ba: 953e add a0,a0,a5 - -000009bc <.LBB178>: - 9bc: 470a lw a4,128(sp) - 9be: 57f6 lw a5,124(sp) - -000009c0 <.LBB177>: - 9c0: cd2a sw a0,152(sp) - 9c2: cb36 sw a3,148(sp) - -000009c4 <.LBB180>: - 9c4: 8f5d or a4,a4,a5 - -000009c6 <.LVL393>: - 9c6: 479a lw a5,132(sp) - 9c8: 0170 add a2,sp,140 - 9ca: 8f5d or a4,a4,a5 - -000009cc <.LVL394>: - 9cc: 47aa lw a5,136(sp) - 9ce: 07b6 sll a5,a5,0xd - 9d0: 8fd9 or a5,a5,a4 - -000009d2 <.LVL395>: - 9d2: 18f8 add a4,sp,124 - -000009d4 <.L140>: - 9d4: 4754 lw a3,12(a4) - 9d6: 4b0c lw a1,16(a4) - 9d8: 82cd srl a3,a3,0x13 - 9da: 05b6 sll a1,a1,0xd - 9dc: 8ecd or a3,a3,a1 - 9de: c314 sw a3,0(a4) - 9e0: 0711 add a4,a4,4 - 9e2: fee619e3 bne a2,a4,9d4 <.L140> - -000009e6 <.LBE180>: - 9e6: 469a lw a3,132(sp) - -000009e8 <.LBB181>: - 9e8: 5776 lw a4,124(sp) - 9ea: 00f037b3 snez a5,a5 - -000009ee <.LBE181>: - 9ee: dab6 sw a3,116(sp) - 9f0: 468a lw a3,128(sp) - -000009f2 <.LBB182>: - 9f2: 8fd9 or a5,a5,a4 - -000009f4 <.LBE182>: - 9f4: 472a lw a4,136(sp) - 9f6: d8b6 sw a3,112(sp) - -000009f8 <.LBE18>: - 9f8: 001006b7 lui a3,0x100 - -000009fc <.LBB183>: - 9fc: dcba sw a4,120(sp) - 9fe: d6be sw a5,108(sp) - -00000a00 <.LBE183>: - a00: 8f75 and a4,a4,a3 - a02: 3a070e63 beqz a4,dbe <.L180> - -00000a06 <.LBB184>: - a06: 07fe sll a5,a5,0x1f - -00000a08 <.LVL399>: - a08: 10f8 add a4,sp,108 - a0a: 18ac add a1,sp,120 - -00000a0c <.L142>: - a0c: 4314 lw a3,0(a4) - a0e: 4350 lw a2,4(a4) - a10: 8285 srl a3,a3,0x1 - a12: 067e sll a2,a2,0x1f - a14: 8ed1 or a3,a3,a2 - a16: c314 sw a3,0(a4) - a18: 0711 add a4,a4,4 - a1a: fee599e3 bne a1,a4,a0c <.L142> - -00000a1e <.LVL401>: - a1e: 5766 lw a4,120(sp) - a20: 8305 srl a4,a4,0x1 - a22: dcba sw a4,120(sp) - -00000a24 <.LBB186>: - a24: 00f03733 snez a4,a5 - -00000a28 <.LBE186>: - a28: 57b6 lw a5,108(sp) - -00000a2a <.LVL403>: - a2a: 8fd9 or a5,a5,a4 - a2c: d6be sw a5,108(sp) - -00000a2e <.L141>: - a2e: 5712 lw a4,36(sp) - a30: 6791 lui a5,0x4 - a32: 17fd add a5,a5,-1 # 3fff <.LLST246+0x1acb> - a34: 97ba add a5,a5,a4 - -00000a36 <.LVL405>: - a36: 38f05e63 blez a5,dd2 <.L146> - a3a: 5736 lw a4,108(sp) - a3c: 00777693 and a3,a4,7 - a40: c69d beqz a3,a6e <.L147> - a42: 00f77693 and a3,a4,15 - a46: 4611 li a2,4 - a48: 02c68363 beq a3,a2,a6e <.L147> - -00000a4c <.LBB187>: - a4c: 0711 add a4,a4,4 - a4e: 00473693 sltiu a3,a4,4 - a52: d6ba sw a4,108(sp) - -00000a54 <.LVL406>: - a54: 5746 lw a4,112(sp) - -00000a56 <.LVL407>: - a56: 9736 add a4,a4,a3 - a58: d8ba sw a4,112(sp) - -00000a5a <.LVL408>: - a5a: 00d73733 sltu a4,a4,a3 - -00000a5e <.LVL409>: - a5e: 56d6 lw a3,116(sp) - a60: 9736 add a4,a4,a3 - -00000a62 <.LVL410>: - a62: daba sw a4,116(sp) - -00000a64 <.LVL411>: - a64: 00d73733 sltu a4,a4,a3 - -00000a68 <.LVL412>: - a68: 56e6 lw a3,120(sp) - a6a: 9736 add a4,a4,a3 - -00000a6c <.LVL413>: - a6c: dcba sw a4,120(sp) - -00000a6e <.L147>: - a6e: 5766 lw a4,120(sp) - a70: 001006b7 lui a3,0x100 - a74: 8ef9 and a3,a3,a4 - a76: ca89 beqz a3,a88 <.L152> - a78: fff007b7 lui a5,0xfff00 - -00000a7c <.LVL415>: - a7c: 17fd add a5,a5,-1 # ffefffff <.LLST246+0xffefdacb> - a7e: 8f7d and a4,a4,a5 - a80: dcba sw a4,120(sp) - a82: 5712 lw a4,36(sp) - a84: 6791 lui a5,0x4 - -00000a86 <.LVL416>: - a86: 97ba add a5,a5,a4 - -00000a88 <.L152>: - a88: 10f8 add a4,sp,108 - a8a: 18ac add a1,sp,120 - -00000a8c <.L153>: - a8c: 4314 lw a3,0(a4) - a8e: 4350 lw a2,4(a4) - a90: 828d srl a3,a3,0x3 - a92: 0676 sll a2,a2,0x1d - a94: 8ed1 or a3,a3,a2 - a96: c314 sw a3,0(a4) - a98: 0711 add a4,a4,4 - a9a: feb719e3 bne a4,a1,a8c <.L153> - -00000a9e <.LBE188>: - a9e: 66a1 lui a3,0x8 - aa0: ffe68613 add a2,a3,-2 # 7ffe <.LLST246+0x5aca> - -00000aa4 <.LBB189>: - aa4: 5766 lw a4,120(sp) - -00000aa6 <.LBE189>: - aa6: 30f64f63 blt a2,a5,dc4 <.L154> - -00000aaa <.LBB190>: - aaa: 830d srl a4,a4,0x3 - aac: dcba sw a4,120(sp) - -00000aae <.L155>: - aae: 4702 lw a4,0(sp) - ab0: 55b6 lw a1,108(sp) - ab2: 5646 lw a2,112(sp) - ab4: 56d6 lw a3,116(sp) - ab6: 4502 lw a0,0(sp) - ab8: c30c sw a1,0(a4) - aba: c350 sw a2,4(a4) - abc: c714 sw a3,8(a4) - abe: 5766 lw a4,120(sp) - -00000ac0 <.LBE191>: - ac0: 408e lw ra,192(sp) - ac2: 547a lw s0,188(sp) - -00000ac4 <.LBB192>: - ac4: 00e51623 sh a4,12(a0) - ac8: 4772 lw a4,28(sp) - -00000aca <.LBE192>: - aca: 54ea lw s1,184(sp) - -00000acc <.LBB193>: - acc: 073e sll a4,a4,0xf - ace: 8fd9 or a5,a5,a4 - -00000ad0 <.LVL421>: - ad0: 00f51723 sh a5,14(a0) - -00000ad4 <.LBE193>: - ad4: 4762 lw a4,24(sp) - -00000ad6 <.LBB194>: - ad6: 455c lw a5,12(a0) - -00000ad8 <.LBE194>: - ad8: c30c sw a1,0(a4) - ada: c350 sw a2,4(a4) - adc: c714 sw a3,8(a4) - ade: c75c sw a5,12(a4) - ae0: 853a mv a0,a4 - ae2: 0c410113 add sp,sp,196 - -00000ae6 <.LVL423>: - ae6: 8082 ret - -00000ae8 <.L2>: - ae8: 00a7e633 or a2,a5,a0 - aec: 8e55 or a2,a2,a3 - aee: 8e59 or a2,a2,a4 - af0: 10060763 beqz a2,bfe <.L176> - -00000af4 <.LBB195>: - af4: c729 beqz a4,b3e <.L6> - af6: 853a mv a0,a4 - af8: 00000097 auipc ra,0x0 - afc: 000080e7 jalr ra # af8 <.LBB195+0x4> - -00000b00 <.LBB7>: - b00: ff450713 add a4,a0,-12 - -00000b04 <.LVL426>: - b04: 02000613 li a2,32 - b08: 8e19 sub a2,a2,a4 - -00000b0a <.LVL427>: - b0a: 4781 li a5,0 - -00000b0c <.L7>: - b0c: 40f005b3 neg a1,a5 - b10: 058a sll a1,a1,0x2 - b12: 04c10293 add t0,sp,76 - b16: 00c58693 add a3,a1,12 - b1a: 9696 add a3,a3,t0 - b1c: 40b00433 neg s0,a1 - -00000b20 <.L12>: - b20: 0ad29763 bne t0,a3,bce <.L15> - b24: fff78693 add a3,a5,-1 # 3fff <.LLST246+0x1acb> - -00000b28 <.LVL430>: - b28: 078a sll a5,a5,0x2 - b2a: 00f0 add a2,sp,76 - -00000b2c <.LVL431>: - b2c: 06c78793 add a5,a5,108 - b30: 97b2 add a5,a5,a2 - b32: 4636 lw a2,76(sp) - b34: 00e61733 sll a4,a2,a4 - -00000b38 <.LVL432>: - b38: f8e7aa23 sw a4,-108(a5) - b3c: a095 j ba0 <.L14> - -00000b3e <.L6>: - b3e: c295 beqz a3,b62 <.L8> - b40: 8536 mv a0,a3 - b42: 00000097 auipc ra,0x0 - b46: 000080e7 jalr ra # b42 <.L6+0x4> - -00000b4a <.LVL434>: - b4a: 02050513 add a0,a0,32 - -00000b4e <.L9>: - b4e: ff450713 add a4,a0,-12 - b52: 40575793 sra a5,a4,0x5 - -00000b56 <.LVL436>: - b56: 8b7d and a4,a4,31 - -00000b58 <.LVL437>: - b58: c70d beqz a4,b82 <.L11> - b5a: 02000613 li a2,32 - b5e: 8e19 sub a2,a2,a4 - -00000b60 <.LVL438>: - b60: b775 j b0c <.L7> - -00000b62 <.L8>: - b62: c901 beqz a0,b72 <.L10> - b64: 00000097 auipc ra,0x0 - b68: 000080e7 jalr ra # b64 <.L8+0x2> - -00000b6c <.LVL440>: - b6c: 04050513 add a0,a0,64 - b70: bff9 j b4e <.L9> - -00000b72 <.L10>: - b72: 853e mv a0,a5 - b74: 00000097 auipc ra,0x0 - b78: 000080e7 jalr ra # b74 <.L10+0x2> - -00000b7c <.LVL443>: - b7c: 06050513 add a0,a0,96 - b80: b7f9 j b4e <.L9> - -00000b82 <.L11>: - b82: 40f00633 neg a2,a5 - b86: 08b8 add a4,sp,88 - -00000b88 <.LVL446>: - b88: 060a sll a2,a2,0x2 - -00000b8a <.LBB9>: - b8a: 468d li a3,3 - -00000b8c <.L13>: - b8c: 00c705b3 add a1,a4,a2 - b90: 418c lw a1,0(a1) - b92: 16fd add a3,a3,-1 - -00000b94 <.LVL448>: - b94: 1771 add a4,a4,-4 - b96: c34c sw a1,4(a4) - -00000b98 <.LVL449>: - b98: fef6dae3 bge a3,a5,b8c <.L13> - b9c: fff78693 add a3,a5,-1 - -00000ba0 <.L14>: - ba0: 00168793 add a5,a3,1 - ba4: 078a sll a5,a5,0x2 - ba6: 46a1 li a3,8 - ba8: 00f8 add a4,sp,76 - baa: 00d7e863 bltu a5,a3,bba <.L16> - bae: 00072023 sw zero,0(a4) - bb2: 00072223 sw zero,4(a4) - bb6: 17e1 add a5,a5,-8 - bb8: 08d8 add a4,sp,84 - -00000bba <.L16>: - bba: 4691 li a3,4 - bbc: 00d7e463 bltu a5,a3,bc4 <.L17> - bc0: 00072023 sw zero,0(a4) - -00000bc4 <.L17>: - bc4: 7471 lui s0,0xffffc - bc6: 0445 add s0,s0,17 # ffffc011 <.LLST246+0xffff9add> - bc8: 8c09 sub s0,s0,a0 - bca: cb4ff06f j 7e <.L205> - -00000bce <.L15>: - bce: 428c lw a1,0(a3) - bd0: ffc6a303 lw t1,-4(a3) - bd4: 008683b3 add t2,a3,s0 - bd8: 00e595b3 sll a1,a1,a4 - bdc: 00c35333 srl t1,t1,a2 - be0: 0065e5b3 or a1,a1,t1 - be4: 00b3a023 sw a1,0(t2) - be8: 16f1 add a3,a3,-4 - bea: bf1d j b20 <.L12> - -00000bec <.L3>: - bec: 8fc9 or a5,a5,a0 - bee: 8fd5 or a5,a5,a3 - bf0: 8fd9 or a5,a5,a4 - bf2: 4709 li a4,2 - bf4: c8078663 beqz a5,80 <.L5> - bf8: 470d li a4,3 - bfa: c86ff06f j 80 <.L5> - -00000bfe <.L176>: - bfe: 4401 li s0,0 - -00000c00 <.LBE196>: - c00: 4705 li a4,1 - c02: c7eff06f j 80 <.L5> - -00000c06 <.L18>: - c06: 47a2 lw a5,8(sp) - -00000c08 <.LVL455>: - c08: 4692 lw a3,4(sp) - -00000c0a <.LVL456>: - c0a: 8fc5 or a5,a5,s1 - c0c: 8fd5 or a5,a5,a3 - c0e: 8fc9 or a5,a5,a0 - c10: 12078263 beqz a5,d34 <.L178> - -00000c14 <.LBB197>: - c14: c539 beqz a0,c62 <.L22> - c16: c23a sw a4,4(sp) - c18: 00000097 auipc ra,0x0 - c1c: 000080e7 jalr ra # c18 <.LBB197+0x4> - -00000c20 <.LBB14>: - c20: 4712 lw a4,4(sp) - c22: ff450693 add a3,a0,-12 - -00000c26 <.LVL458>: - c26: 02000593 li a1,32 - c2a: 8d95 sub a1,a1,a3 - -00000c2c <.LVL459>: - c2c: 4781 li a5,0 - -00000c2e <.L23>: - c2e: 40f00333 neg t1,a5 - c32: 030a sll t1,t1,0x2 - c34: 05c10393 add t2,sp,92 - c38: 00c30613 add a2,t1,12 - c3c: 406004b3 neg s1,t1 - c40: 961e add a2,a2,t2 - c42: c226 sw s1,4(sp) - -00000c44 <.L28>: - c44: 0ac39f63 bne t2,a2,d02 <.L31> - c48: fff78613 add a2,a5,-1 - -00000c4c <.LVL461>: - c4c: 078a sll a5,a5,0x2 - c4e: 00ec add a1,sp,76 - -00000c50 <.LVL462>: - c50: 06c78793 add a5,a5,108 - c54: 97ae add a5,a5,a1 - c56: 45f6 lw a1,92(sp) - c58: 00d596b3 sll a3,a1,a3 - -00000c5c <.LVL463>: - c5c: fad7a223 sw a3,-92(a5) - c60: a895 j cd4 <.L30> - -00000c62 <.L22>: - c62: 4792 lw a5,4(sp) - c64: c785 beqz a5,c8c <.L24> - c66: 853e mv a0,a5 - c68: c43a sw a4,8(sp) - c6a: 00000097 auipc ra,0x0 - c6e: 000080e7 jalr ra # c6a <.L22+0x8> - -00000c72 <.LVL465>: - c72: 4722 lw a4,8(sp) - c74: 02050513 add a0,a0,32 - -00000c78 <.L25>: - c78: ff450693 add a3,a0,-12 - c7c: 4056d793 sra a5,a3,0x5 - -00000c80 <.LVL467>: - c80: 8afd and a3,a3,31 - -00000c82 <.LVL468>: - c82: ca85 beqz a3,cb2 <.L27> - c84: 02000593 li a1,32 - c88: 8d95 sub a1,a1,a3 - -00000c8a <.LVL469>: - c8a: b755 j c2e <.L23> - -00000c8c <.L24>: - c8c: c23a sw a4,4(sp) - c8e: c891 beqz s1,ca2 <.L26> - c90: 8526 mv a0,s1 - c92: 00000097 auipc ra,0x0 - c96: 000080e7 jalr ra # c92 <.L24+0x6> - -00000c9a <.LVL471>: - c9a: 04050513 add a0,a0,64 - -00000c9e <.L206>: - c9e: 4712 lw a4,4(sp) - -00000ca0 <.LVL473>: - ca0: bfe1 j c78 <.L25> - -00000ca2 <.L26>: - ca2: 4522 lw a0,8(sp) - ca4: 00000097 auipc ra,0x0 - ca8: 000080e7 jalr ra # ca4 <.L26+0x2> - -00000cac <.LVL475>: - cac: 06050513 add a0,a0,96 - -00000cb0 <.LVL476>: - cb0: b7fd j c9e <.L206> - -00000cb2 <.L27>: - cb2: 40f005b3 neg a1,a5 - cb6: 10b4 add a3,sp,104 - -00000cb8 <.LVL478>: - cb8: 058a sll a1,a1,0x2 - -00000cba <.LBB16>: - cba: 460d li a2,3 - -00000cbc <.L29>: - cbc: 00b68333 add t1,a3,a1 - cc0: 00032303 lw t1,0(t1) - cc4: 167d add a2,a2,-1 - -00000cc6 <.LVL480>: - cc6: 16f1 add a3,a3,-4 - cc8: 0066a223 sw t1,4(a3) - -00000ccc <.LVL481>: - ccc: fef658e3 bge a2,a5,cbc <.L29> - cd0: fff78613 add a2,a5,-1 - -00000cd4 <.L30>: - cd4: 00160793 add a5,a2,1 - cd8: 078a sll a5,a5,0x2 - cda: 4621 li a2,8 - cdc: 08f4 add a3,sp,92 - cde: 00c7e863 bltu a5,a2,cee <.L32> - ce2: 0006a023 sw zero,0(a3) - ce6: 0006a223 sw zero,4(a3) - cea: 17e1 add a5,a5,-8 - cec: 10d4 add a3,sp,100 - -00000cee <.L32>: - cee: 4611 li a2,4 - cf0: 00c7e463 bltu a5,a2,cf8 <.L33> - cf4: 0006a023 sw zero,0(a3) - -00000cf8 <.L33>: - cf8: 77f1 lui a5,0xffffc - cfa: 07c5 add a5,a5,17 # ffffc011 <.LLST246+0xffff9add> - cfc: 8f89 sub a5,a5,a0 - cfe: be2ff06f j e0 <.L207> - -00000d02 <.L31>: - d02: 00062303 lw t1,0(a2) - d06: ffc62283 lw t0,-4(a2) - d0a: 4492 lw s1,4(sp) - d0c: 00d31333 sll t1,t1,a3 - d10: 00b2d2b3 srl t0,t0,a1 - d14: 94b2 add s1,s1,a2 - d16: 00536333 or t1,t1,t0 - d1a: 0064a023 sw t1,0(s1) - d1e: 1671 add a2,a2,-4 - d20: b715 j c44 <.L28> - -00000d22 <.L19>: - d22: 46a2 lw a3,8(sp) - d24: 4612 lw a2,4(sp) - d26: 8ec5 or a3,a3,s1 - d28: 8ed1 or a3,a3,a2 - d2a: 8ec9 or a3,a3,a0 - d2c: ea81 bnez a3,d3c <.L179> - d2e: 4689 li a3,2 - d30: bb2ff06f j e2 <.L21> - -00000d34 <.L178>: - d34: 4781 li a5,0 - -00000d36 <.LBE198>: - d36: 4685 li a3,1 - d38: baaff06f j e2 <.L21> - -00000d3c <.L179>: - d3c: 468d li a3,3 - d3e: ba4ff06f j e2 <.L21> - -00000d42 <.L35>: - d42: 4605 li a2,1 - d44: 00f617b3 sll a5,a2,a5 - d48: 5307f613 and a2,a5,1328 - d4c: ea05 bnez a2,d7c <.L38> - d4e: 0887f713 and a4,a5,136 - d52: eb39 bnez a4,da8 <.L39> - d54: 2407f793 and a5,a5,576 - d58: ba078a63 beqz a5,10c <.L36> - -00000d5c <.L40>: - d5c: 67a1 lui a5,0x8 - d5e: dcbe sw a5,120(sp) - d60: da82 sw zero,116(sp) - d62: d882 sw zero,112(sp) - d64: d682 sw zero,108(sp) - -00000d66 <.LVL489>: - d66: 17fd add a5,a5,-1 # 7fff <.LLST246+0x5acb> - d68: ce02 sw zero,28(sp) - d6a: b391 j aae <.L155> - -00000d6c <.L34>: - d6c: 463d li a2,15 - d6e: fec787e3 beq a5,a2,d5c <.L40> - d72: 462d li a2,11 - d74: 02c78a63 beq a5,a2,da8 <.L39> - -00000d78 <.LBB199>: - d78: 47c2 lw a5,16(sp) - d7a: ce3e sw a5,28(sp) - -00000d7c <.L38>: - d7c: 47b6 lw a5,76(sp) - d7e: d6be sw a5,108(sp) - d80: 47c6 lw a5,80(sp) - d82: d8be sw a5,112(sp) - d84: 47d6 lw a5,84(sp) - d86: dabe sw a5,116(sp) - d88: 47e6 lw a5,88(sp) - -00000d8a <.L143>: - d8a: dcbe sw a5,120(sp) - d8c: 4789 li a5,2 - d8e: 1af70063 beq a4,a5,f2e <.L144> - d92: 478d li a5,3 - d94: fcf704e3 beq a4,a5,d5c <.L40> - d98: 4785 li a5,1 - d9a: c8f71ae3 bne a4,a5,a2e <.L141> - -00000d9e <.L208>: - d9e: dc82 sw zero,120(sp) - da0: da82 sw zero,116(sp) - da2: d882 sw zero,112(sp) - -00000da4 <.LBB208>: - da4: d682 sw zero,108(sp) - da6: aa8d j f18 <.L175> - -00000da8 <.L39>: - da8: 47b2 lw a5,12(sp) - daa: ce3e sw a5,28(sp) - -00000dac <.L37>: - dac: 47f6 lw a5,92(sp) - dae: 8736 mv a4,a3 - db0: d6be sw a5,108(sp) - db2: 5786 lw a5,96(sp) - db4: d8be sw a5,112(sp) - db6: 5796 lw a5,100(sp) - db8: dabe sw a5,116(sp) - dba: 57a6 lw a5,104(sp) - -00000dbc <.LVL497>: - dbc: b7f9 j d8a <.L143> - -00000dbe <.L180>: - dbe: 57a2 lw a5,40(sp) - dc0: d23e sw a5,36(sp) - -00000dc2 <.LVL499>: - dc2: b1b5 j a2e <.L141> - -00000dc4 <.L154>: - dc4: dc82 sw zero,120(sp) - dc6: da82 sw zero,116(sp) - dc8: d882 sw zero,112(sp) - dca: d682 sw zero,108(sp) - dcc: fff68793 add a5,a3,-1 - dd0: b9f9 j aae <.L155> - -00000dd2 <.L146>: - dd2: 4705 li a4,1 - dd4: c791 beqz a5,de0 <.L156> - dd6: 8f1d sub a4,a4,a5 - -00000dd8 <.LVL502>: - dd8: 07400793 li a5,116 - ddc: 14e7c063 blt a5,a4,f1c <.L157> - -00000de0 <.L156>: - de0: 10f4 add a3,sp,108 - de2: 40575513 sra a0,a4,0x5 - -00000de6 <.LVL504>: - de6: 85b6 mv a1,a3 - de8: 8b7d and a4,a4,31 - -00000dea <.LVL505>: - dea: 4781 li a5,0 - dec: 4601 li a2,0 - -00000dee <.L158>: - dee: 02a61563 bne a2,a0,e18 <.L159> - df2: 460d li a2,3 - -00000df4 <.LVL507>: - df4: 8e09 sub a2,a2,a0 - df6: 00251313 sll t1,a0,0x2 - dfa: e715 bnez a4,e26 <.L160> - dfc: 85b6 mv a1,a3 - -00000dfe <.L161>: - dfe: 006582b3 add t0,a1,t1 - e02: 0002a283 lw t0,0(t0) - e06: 0705 add a4,a4,1 - -00000e08 <.LVL509>: - e08: 0055a023 sw t0,0(a1) - -00000e0c <.LVL510>: - e0c: 0591 add a1,a1,4 - e0e: fee658e3 bge a2,a4,dfe <.L161> - e12: 4591 li a1,4 - e14: 8d89 sub a1,a1,a0 - e16: a0b9 j e64 <.L165> - -00000e18 <.L159>: - e18: 0005a303 lw t1,0(a1) - e1c: 0605 add a2,a2,1 - -00000e1e <.LVL512>: - e1e: 0591 add a1,a1,4 - e20: 0067e7b3 or a5,a5,t1 - -00000e24 <.LVL513>: - e24: b7e9 j dee <.L158> - -00000e26 <.L160>: - e26: 00e0 add s0,sp,76 - e28: 06c30593 add a1,t1,108 - e2c: 95a2 add a1,a1,s0 - e2e: fb45a583 lw a1,-76(a1) - e32: 02000293 li t0,32 - e36: 40e282b3 sub t0,t0,a4 - e3a: 005595b3 sll a1,a1,t0 - e3e: 8fcd or a5,a5,a1 - -00000e40 <.LVL515>: - e40: 10ec add a1,sp,108 - e42: 959a add a1,a1,t1 - e44: 8436 mv s0,a3 - e46: 4381 li t2,0 - -00000e48 <.L163>: - e48: 08c3cb63 blt t2,a2,ede <.L164> - e4c: 4591 li a1,4 - e4e: 060a sll a2,a2,0x2 - e50: 8d89 sub a1,a1,a0 - -00000e52 <.LVL517>: - e52: 06c60613 add a2,a2,108 - e56: 00e8 add a0,sp,76 - -00000e58 <.LVL518>: - e58: 962a add a2,a2,a0 - e5a: 5566 lw a0,120(sp) - e5c: 00e55733 srl a4,a0,a4 - -00000e60 <.LVL519>: - e60: fae62a23 sw a4,-76(a2) - -00000e64 <.L165>: - e64: 4711 li a4,4 - e66: 8f0d sub a4,a4,a1 - e68: 10f0 add a2,sp,108 - e6a: 058a sll a1,a1,0x2 - e6c: 95b2 add a1,a1,a2 - e6e: 070a sll a4,a4,0x2 - e70: 4621 li a2,8 - e72: 00c76863 bltu a4,a2,e82 <.L166> - e76: 0005a023 sw zero,0(a1) - e7a: 0005a223 sw zero,4(a1) - e7e: 1761 add a4,a4,-8 - e80: 05a1 add a1,a1,8 - -00000e82 <.L166>: - e82: 4611 li a2,4 - e84: 00c76463 bltu a4,a2,e8c <.L167> - e88: 0005a023 sw zero,0(a1) - -00000e8c <.L167>: - e8c: 5736 lw a4,108(sp) - -00000e8e <.LBB203>: - e8e: 00f037b3 snez a5,a5 - -00000e92 <.LBE203>: - e92: 8fd9 or a5,a5,a4 - e94: d6be sw a5,108(sp) - -00000e96 <.LBE201>: - e96: 0077f713 and a4,a5,7 - e9a: c71d beqz a4,ec8 <.L168> - e9c: 00f7f713 and a4,a5,15 - ea0: 4611 li a2,4 - ea2: 02c70363 beq a4,a2,ec8 <.L168> - -00000ea6 <.LBB205>: - ea6: 5746 lw a4,112(sp) - ea8: 0791 add a5,a5,4 - eaa: d6be sw a5,108(sp) - -00000eac <.LVL522>: - eac: 0047b793 sltiu a5,a5,4 - -00000eb0 <.LVL523>: - eb0: 97ba add a5,a5,a4 - eb2: d8be sw a5,112(sp) - -00000eb4 <.LVL524>: - eb4: 00e7b7b3 sltu a5,a5,a4 - -00000eb8 <.LVL525>: - eb8: 5756 lw a4,116(sp) - eba: 97ba add a5,a5,a4 - -00000ebc <.LVL526>: - ebc: dabe sw a5,116(sp) - -00000ebe <.LVL527>: - ebe: 00e7b7b3 sltu a5,a5,a4 - -00000ec2 <.LVL528>: - ec2: 5766 lw a4,120(sp) - ec4: 97ba add a5,a5,a4 - -00000ec6 <.LVL529>: - ec6: dcbe sw a5,120(sp) - -00000ec8 <.L168>: - ec8: 5766 lw a4,120(sp) - eca: 000807b7 lui a5,0x80 - ece: 8ff9 and a5,a5,a4 - ed0: c795 beqz a5,efc <.L173> - -00000ed2 <.LVL531>: - ed2: dc82 sw zero,120(sp) - ed4: da82 sw zero,116(sp) - ed6: d882 sw zero,112(sp) - ed8: d682 sw zero,108(sp) - eda: 4785 li a5,1 - edc: bec9 j aae <.L155> - -00000ede <.L164>: - ede: 0005a303 lw t1,0(a1) - ee2: 41c4 lw s1,4(a1) - ee4: 0385 add t2,t2,1 - -00000ee6 <.LVL533>: - ee6: 00e35333 srl t1,t1,a4 - eea: 005494b3 sll s1,s1,t0 - eee: 00936333 or t1,t1,s1 - ef2: 00642023 sw t1,0(s0) - -00000ef6 <.LVL534>: - ef6: 0591 add a1,a1,4 - ef8: 0411 add s0,s0,4 - efa: b7b9 j e48 <.L163> - -00000efc <.L173>: - efc: 00c68613 add a2,a3,12 - -00000f00 <.L174>: - f00: 429c lw a5,0(a3) - f02: 42d8 lw a4,4(a3) - f04: 838d srl a5,a5,0x3 - f06: 0776 sll a4,a4,0x1d - f08: 8fd9 or a5,a5,a4 - f0a: c29c sw a5,0(a3) - f0c: 0691 add a3,a3,4 - f0e: fed619e3 bne a2,a3,f00 <.L174> - -00000f12 <.LVL536>: - f12: 57e6 lw a5,120(sp) - f14: 838d srl a5,a5,0x3 - f16: dcbe sw a5,120(sp) - -00000f18 <.L175>: - f18: 4781 li a5,0 - f1a: be51 j aae <.L155> - -00000f1c <.L157>: - f1c: 5746 lw a4,112(sp) - f1e: 57b6 lw a5,108(sp) - f20: 8fd9 or a5,a5,a4 - f22: 5756 lw a4,116(sp) - f24: 8fd9 or a5,a5,a4 - f26: 5766 lw a4,120(sp) - f28: 8fd9 or a5,a5,a4 - f2a: d7fd beqz a5,f18 <.L175> - f2c: bd8d j d9e <.L208> - -00000f2e <.L144>: - f2e: 67a1 lui a5,0x8 - f30: dc82 sw zero,120(sp) - f32: da82 sw zero,116(sp) - f34: d882 sw zero,112(sp) - f36: d682 sw zero,108(sp) - f38: 17fd add a5,a5,-1 # 7fff <.LLST246+0x5acb> - f3a: be95 j aae <.L155> - -negtf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__negtf2>: - 0: 0005a283 lw t0,0(a1) - 4: 0045a303 lw t1,4(a1) - 8: 4590 lw a2,8(a1) - a: 45cc lw a1,12(a1) - -0000000c <.LBB3>: - c: 1111 add sp,sp,-28 - e: 00f10793 add a5,sp,15 - -00000012 <.LBB4>: - 12: 0105d693 srl a3,a1,0x10 - 16: 63a1 lui t2,0x8 - -00000018 <.LBE4>: - 18: 9bc1 and a5,a5,-16 - -0000001a <.LBB5>: - 1a: 0076c6b3 xor a3,a3,t2 - -0000001e <.LBB6>: - 1e: 00b79623 sh a1,12(a5) - 22: 00d79723 sh a3,14(a5) - -00000026 <.LBB7>: - 26: 0057a023 sw t0,0(a5) - 2a: 0067a223 sw t1,4(a5) - 2e: c790 sw a2,8(a5) - -00000030 <.LBB8>: - 30: 47dc lw a5,12(a5) - -00000032 <.LBE8>: - 32: 00552023 sw t0,0(a0) - 36: 00652223 sw t1,4(a0) - 3a: c510 sw a2,8(a0) - 3c: c55c sw a5,12(a0) - 3e: 0171 add sp,sp,28 - 40: 8082 ret - -subtf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__subtf3>: - 0: f7c10113 add sp,sp,-132 - 4: 45dc lw a5,12(a1) - 6: 4598 lw a4,8(a1) - 8: 0005a383 lw t2,0(a1) - c: 0045a283 lw t0,4(a1) - 10: 00062303 lw t1,0(a2) - 14: 460c lw a1,8(a2) - 16: 4654 lw a3,12(a2) - 18: cc2a sw a0,24(sp) - 1a: 4248 lw a0,4(a2) - 1c: 06b10613 add a2,sp,107 - 20: dea2 sw s0,124(sp) - 22: 9a41 and a2,a2,-16 - 24: c106 sw ra,128(sp) - 26: dca6 sw s1,120(sp) - -00000028 <.LBB3>: - 28: c618 sw a4,8(a2) - 2a: da3a sw a4,52(sp) - 2c: 01079713 sll a4,a5,0x10 - 30: 00179413 sll s0,a5,0x1 - 34: 00762023 sw t2,0(a2) - 38: c65c sw a5,12(a2) - 3a: d61e sw t2,44(sp) - 3c: 83fd srl a5,a5,0x1f - 3e: 8341 srl a4,a4,0x10 - 40: 02c10393 add t2,sp,44 - 44: 00562223 sw t0,4(a2) - 48: d816 sw t0,48(sp) - 4a: c63e sw a5,12(sp) - -0000004c <.LBE3>: - 4c: c832 sw a2,16(sp) - -0000004e <.LBB4>: - 4e: dc3a sw a4,56(sp) - 50: 8045 srl s0,s0,0x11 - -00000052 <.LBB5>: - 52: 02010293 add t0,sp,32 - -00000056 <.LBB6>: - 56: 879e mv a5,t2 - -00000058 <.L2>: - 58: 47d8 lw a4,12(a5) - 5a: 4790 lw a2,8(a5) - 5c: 17f1 add a5,a5,-4 - 5e: 070e sll a4,a4,0x3 - 60: 8275 srl a2,a2,0x1d - 62: 8f51 or a4,a4,a2 - 64: cb98 sw a4,16(a5) - 66: fef299e3 bne t0,a5,58 <.L2> - -0000006a <.LBB8>: - 6a: 4742 lw a4,16(sp) - -0000006c <.LBB9>: - 6c: 57b2 lw a5,44(sp) - -0000006e <.LBB10>: - 6e: de1a sw t1,60(sp) - 70: 00672023 sw t1,0(a4) - 74: c754 sw a3,12(a4) - 76: c348 sw a0,4(a4) - 78: c70c sw a1,8(a4) - 7a: 01069713 sll a4,a3,0x10 - 7e: 8341 srl a4,a4,0x10 - 80: c4ba sw a4,72(sp) - 82: 00169713 sll a4,a3,0x1 - 86: 8345 srl a4,a4,0x11 - -00000088 <.LBB11>: - 88: 078e sll a5,a5,0x3 - -0000008a <.LBB12>: - 8a: ca3a sw a4,20(sp) - 8c: 1878 add a4,sp,60 - -0000008e <.LBB13>: - 8e: d63e sw a5,44(sp) - -00000090 <.LBB14>: - 90: c0aa sw a0,64(sp) - 92: c2ae sw a1,68(sp) - -00000094 <.LVL5>: - 94: 82fd srl a3,a3,0x1f - -00000096 <.LBB15>: - 96: 03010313 add t1,sp,48 - -0000009a <.LBB16>: - 9a: 863a mv a2,a4 - -0000009c <.L3>: - 9c: 464c lw a1,12(a2) - 9e: 4608 lw a0,8(a2) - a0: 1671 add a2,a2,-4 - a2: 058e sll a1,a1,0x3 - a4: 8175 srl a0,a0,0x1d - a6: 8dc9 or a1,a1,a0 - a8: ca0c sw a1,16(a2) - aa: fec319e3 bne t1,a2,9c <.L3> - -000000ae <.LVL8>: - ae: 5672 lw a2,60(sp) - -000000b0 <.LBE17>: - b0: 45d2 lw a1,20(sp) - b2: 6321 lui t1,0x8 - -000000b4 <.LBB18>: - b4: 00361493 sll s1,a2,0x3 - b8: 4652 lw a2,20(sp) - ba: de26 sw s1,60(sp) - -000000bc <.LBE18>: - bc: 137d add t1,t1,-1 # 7fff <.LLST157+0x5601> - be: 40c40633 sub a2,s0,a2 - c2: 06659363 bne a1,t1,128 <.L4> - c6: 4586 lw a1,64(sp) - c8: 4716 lw a4,68(sp) - -000000ca <.LBB19>: - ca: ce32 sw a2,28(sp) - -000000cc <.LBE19>: - cc: 8f4d or a4,a4,a1 - ce: 45a6 lw a1,72(sp) - d0: 8f4d or a4,a4,a1 - d2: 8f45 or a4,a4,s1 - d4: c721 beqz a4,11c <.L5> - d6: 4732 lw a4,12(sp) - -000000d8 <.LBB54>: - d8: c236 sw a3,4(sp) - -000000da <.L353>: - da: 02d719e3 bne a4,a3,90c <.L7> - -000000de <.L6>: - de: 4706 lw a4,64(sp) - e0: c03a sw a4,0(sp) - e2: 4716 lw a4,68(sp) - e4: c23a sw a4,4(sp) - e6: 4726 lw a4,72(sp) - e8: c43a sw a4,8(sp) - -000000ea <.LBB56>: - ea: 40060a63 beqz a2,4fe <.L48> - ee: 4752 lw a4,20(sp) - f0: 408705b3 sub a1,a4,s0 - -000000f4 <.LVL10>: - f4: 2a041f63 bnez s0,3b2 <.L49> - f8: 5642 lw a2,48(sp) - fa: 5752 lw a4,52(sp) - -000000fc <.LVL11>: - fc: 5562 lw a0,56(sp) - fe: 00e666b3 or a3,a2,a4 - 102: 8ec9 or a3,a3,a0 - 104: 8edd or a3,a3,a5 - 106: 24069a63 bnez a3,35a <.L50> - -0000010a <.LVL12>: - 10a: 4782 lw a5,0(sp) - 10c: c6a6 sw s1,76(sp) - 10e: c8be sw a5,80(sp) - 110: 4792 lw a5,4(sp) - 112: cabe sw a5,84(sp) - 114: 47a2 lw a5,8(sp) - -00000116 <.L362>: - 116: ccbe sw a5,88(sp) - -00000118 <.LBE20>: - 118: 842e mv s0,a1 - 11a: a905 j 54a <.L11> - -0000011c <.L5>: - 11c: 0016c713 xor a4,a3,1 - 120: c23a sw a4,4(sp) - -00000122 <.LVL15>: - 122: 4692 lw a3,4(sp) - 124: 4732 lw a4,12(sp) - -00000126 <.LVL16>: - 126: bf55 j da <.L353> - -00000128 <.L4>: - 128: 0016c693 xor a3,a3,1 - -0000012c <.LVL18>: - 12c: c236 sw a3,4(sp) - -0000012e <.LVL19>: - 12e: 4592 lw a1,4(sp) - 130: 46b2 lw a3,12(sp) - -00000132 <.LBB57>: - 132: ce32 sw a2,28(sp) - -00000134 <.LBE57>: - 134: 5cb69d63 bne a3,a1,70e <.L8> - -00000138 <.LBB58>: - 138: fac053e3 blez a2,de <.L6> - -0000013c <.LVL22>: - 13c: 56c2 lw a3,48(sp) - -0000013e <.LVL23>: - 13e: c036 sw a3,0(sp) - 140: 56d2 lw a3,52(sp) - 142: c236 sw a3,4(sp) - 144: 56e2 lw a3,56(sp) - 146: c436 sw a3,8(sp) - 148: 46d2 lw a3,20(sp) - 14a: eea5 bnez a3,1c2 <.L9> - 14c: 4506 lw a0,64(sp) - 14e: 4596 lw a1,68(sp) - -00000150 <.LVL24>: - 150: 42a6 lw t0,72(sp) - 152: 00b566b3 or a3,a0,a1 - 156: 0056e6b3 or a3,a3,t0 - 15a: 8ec5 or a3,a3,s1 - 15c: ea91 bnez a3,170 <.L10> - -0000015e <.L358>: - 15e: c6be sw a5,76(sp) - 160: 4782 lw a5,0(sp) - -00000162 <.LBB110>: - 162: 8432 mv s0,a2 - -00000164 <.LBB111>: - 164: c8be sw a5,80(sp) - 166: 4792 lw a5,4(sp) - 168: cabe sw a5,84(sp) - 16a: 47a2 lw a5,8(sp) - 16c: ccbe sw a5,88(sp) - -0000016e <.LBB112>: - 16e: aef1 j 54a <.L11> - -00000170 <.L10>: - 170: fff60693 add a3,a2,-1 - -00000174 <.LVL28>: - 174: ee8d bnez a3,1ae <.L12> - -00000176 <.LBB25>: - 176: 4682 lw a3,0(sp) - -00000178 <.LVL29>: - 178: 00978733 add a4,a5,s1 - 17c: c6ba sw a4,76(sp) - -0000017e <.LVL30>: - 17e: 96aa add a3,a3,a0 - -00000180 <.LVL31>: - 180: 00f73733 sltu a4,a4,a5 - -00000184 <.LVL32>: - 184: 4792 lw a5,4(sp) - 186: 9736 add a4,a4,a3 - -00000188 <.LVL33>: - 188: c8ba sw a4,80(sp) - -0000018a <.LVL34>: - 18a: 00a6b533 sltu a0,a3,a0 - -0000018e <.LVL35>: - 18e: 00d73733 sltu a4,a4,a3 - -00000192 <.LVL36>: - 192: 97ae add a5,a5,a1 - -00000194 <.LVL37>: - 194: 8d59 or a0,a0,a4 - -00000196 <.LVL38>: - 196: 953e add a0,a0,a5 - 198: 00b7b733 sltu a4,a5,a1 - -0000019c <.LVL39>: - 19c: caaa sw a0,84(sp) - -0000019e <.LVL40>: - 19e: 00f53533 sltu a0,a0,a5 - -000001a2 <.LVL41>: - 1a2: 47a2 lw a5,8(sp) - 1a4: 8f49 or a4,a4,a0 - -000001a6 <.LVL42>: - 1a6: 92be add t0,t0,a5 - 1a8: 9716 add a4,a4,t0 - -000001aa <.L354>: - 1aa: 4405 li s0,1 - -000001ac <.LBB118>: - 1ac: aa0d j 2de <.L23> - -000001ae <.L12>: - 1ae: 5a661ce3 bne a2,t1,f66 <.L24> - -000001b2 <.L365>: - 1b2: c6be sw a5,76(sp) - 1b4: a2f5 j 3a0 <.L364> - -000001b6 <.L268>: - 1b6: 87a6 mv a5,s1 - 1b8: bfed j 1b2 <.L365> - -000001ba <.L269>: - 1ba: c03a sw a4,0(sp) - 1bc: c236 sw a3,4(sp) - 1be: c432 sw a2,8(sp) - -000001c0 <.LVL48>: - 1c0: bfcd j 1b2 <.L365> - -000001c2 <.L9>: - 1c2: 00641a63 bne s0,t1,1d6 <.L25> - -000001c6 <.LVL50>: - 1c6: c6be sw a5,76(sp) - 1c8: 4782 lw a5,0(sp) - 1ca: c8be sw a5,80(sp) - 1cc: 4792 lw a5,4(sp) - 1ce: cabe sw a5,84(sp) - 1d0: 47a2 lw a5,8(sp) - -000001d2 <.L363>: - 1d2: ccbe sw a5,88(sp) - -000001d4 <.LBB122>: - 1d4: ae9d j 54a <.L11> - -000001d6 <.L25>: - 1d6: 46a6 lw a3,72(sp) - -000001d8 <.LVL53>: - 1d8: 000805b7 lui a1,0x80 - -000001dc <.LVL54>: - 1dc: 8ecd or a3,a3,a1 - 1de: c4b6 sw a3,72(sp) - -000001e0 <.LDL3>: - 1e0: 07400693 li a3,116 - 1e4: 58c6c5e3 blt a3,a2,f6e <.L26> - 1e8: 86b2 mv a3,a2 - -000001ea <.L264>: - 1ea: 4056d513 sra a0,a3,0x5 - -000001ee <.LVL56>: - 1ee: 85ba mv a1,a4 - 1f0: 8afd and a3,a3,31 - -000001f2 <.LVL57>: - 1f2: 4481 li s1,0 - 1f4: 4601 li a2,0 - -000001f6 <.L27>: - 1f6: 02a61463 bne a2,a0,21e <.L28> - 1fa: 460d li a2,3 - -000001fc <.LVL59>: - 1fc: 8e09 sub a2,a2,a0 - 1fe: 00251593 sll a1,a0,0x2 - 202: e68d bnez a3,22c <.L29> - -00000204 <.L30>: - 204: 00b70333 add t1,a4,a1 - 208: 00032303 lw t1,0(t1) - 20c: 0685 add a3,a3,1 - -0000020e <.LVL61>: - 20e: 00672023 sw t1,0(a4) - -00000212 <.LVL62>: - 212: 0711 add a4,a4,4 - 214: fed658e3 bge a2,a3,204 <.L30> - 218: 4711 li a4,4 - 21a: 8f09 sub a4,a4,a0 - 21c: a899 j 272 <.L34> - -0000021e <.L28>: - 21e: 0005a303 lw t1,0(a1) # 80000 <.LLST157+0x7d602> - 222: 0605 add a2,a2,1 - -00000224 <.LVL64>: - 224: 0591 add a1,a1,4 - 226: 0064e4b3 or s1,s1,t1 - -0000022a <.LVL65>: - 22a: b7f1 j 1f6 <.L27> - -0000022c <.L29>: - 22c: 02000293 li t0,32 - 230: 40d28333 sub t1,t0,a3 - 234: ca1a sw t1,20(sp) - -00000236 <.LVL67>: - 236: 02c10293 add t0,sp,44 - 23a: 04c58313 add t1,a1,76 - 23e: 9316 add t1,t1,t0 - 240: fc432303 lw t1,-60(t1) - 244: 42d2 lw t0,20(sp) - 246: 4381 li t2,0 - 248: 00531333 sll t1,t1,t0 - 24c: 0064e4b3 or s1,s1,t1 - -00000250 <.LVL68>: - 250: 03c10313 add t1,sp,60 - 254: 959a add a1,a1,t1 - -00000256 <.L32>: - 256: 0cc3cf63 blt t2,a2,334 <.L33> - 25a: 060a sll a2,a2,0x2 - 25c: 106c add a1,sp,44 - 25e: 04c60613 add a2,a2,76 - 262: 962e add a2,a2,a1 - 264: 45a6 lw a1,72(sp) - 266: 4711 li a4,4 - 268: 8f09 sub a4,a4,a0 - -0000026a <.LVL70>: - 26a: 00d5d5b3 srl a1,a1,a3 - 26e: fcb62223 sw a1,-60(a2) - -00000272 <.L34>: - 272: 4691 li a3,4 - 274: 8e99 sub a3,a3,a4 - 276: 1870 add a2,sp,60 - 278: 070a sll a4,a4,0x2 - 27a: 9732 add a4,a4,a2 - 27c: 068a sll a3,a3,0x2 - 27e: 4621 li a2,8 - 280: 00c6e863 bltu a3,a2,290 <.L35> - 284: 00072023 sw zero,0(a4) - -00000288 <.LVL72>: - 288: 00072223 sw zero,4(a4) - 28c: 16e1 add a3,a3,-8 - 28e: 0721 add a4,a4,8 - -00000290 <.L35>: - 290: 4611 li a2,4 - 292: 00c6e463 bltu a3,a2,29a <.L36> - 296: 00072023 sw zero,0(a4) - -0000029a <.L36>: - 29a: 56f2 lw a3,60(sp) - -0000029c <.LBB28>: - 29c: 00903733 snez a4,s1 - -000002a0 <.LBE28>: - 2a0: 8f55 or a4,a4,a3 - -000002a2 <.L37>: - 2a2: 4686 lw a3,64(sp) - 2a4: 4602 lw a2,0(sp) - -000002a6 <.LBB30>: - 2a6: de3a sw a4,60(sp) - -000002a8 <.LBB31>: - 2a8: 973e add a4,a4,a5 - 2aa: 9636 add a2,a2,a3 - 2ac: c6ba sw a4,76(sp) - -000002ae <.LVL75>: - 2ae: 00f73733 sltu a4,a4,a5 - -000002b2 <.LVL76>: - 2b2: 00e607b3 add a5,a2,a4 - 2b6: 4592 lw a1,4(sp) - 2b8: 4716 lw a4,68(sp) - -000002ba <.LVL77>: - 2ba: c8be sw a5,80(sp) - -000002bc <.LVL78>: - 2bc: 00d636b3 sltu a3,a2,a3 - -000002c0 <.LVL79>: - 2c0: 00c7b7b3 sltu a5,a5,a2 - -000002c4 <.LVL80>: - 2c4: 95ba add a1,a1,a4 - -000002c6 <.LVL81>: - 2c6: 8edd or a3,a3,a5 - -000002c8 <.LVL82>: - 2c8: 96ae add a3,a3,a1 - 2ca: cab6 sw a3,84(sp) - -000002cc <.LVL83>: - 2cc: 00e5b733 sltu a4,a1,a4 - -000002d0 <.LVL84>: - 2d0: 00b6b6b3 sltu a3,a3,a1 - -000002d4 <.LVL85>: - 2d4: 8f55 or a4,a4,a3 - -000002d6 <.LVL86>: - 2d6: 47a6 lw a5,72(sp) - -000002d8 <.LVL87>: - 2d8: 46a2 lw a3,8(sp) - -000002da <.LVL88>: - 2da: 97b6 add a5,a5,a3 - 2dc: 973e add a4,a4,a5 - -000002de <.L23>: - 2de: 000807b7 lui a5,0x80 - -000002e2 <.LBB32>: - 2e2: ccba sw a4,88(sp) - -000002e4 <.LBE32>: - 2e4: 8ff9 and a5,a5,a4 - 2e6: 26078263 beqz a5,54a <.L11> - 2ea: fff807b7 lui a5,0xfff80 - 2ee: 17fd add a5,a5,-1 # fff7ffff <.LLST157+0xfff7d601> - 2f0: 8f7d and a4,a4,a5 - 2f2: ccba sw a4,88(sp) - -000002f4 <.LBB33>: - 2f4: 4736 lw a4,76(sp) - -000002f6 <.LBE33>: - 2f6: 0405 add s0,s0,1 - -000002f8 <.LBB35>: - 2f8: 08ac add a1,sp,88 - 2fa: 01f71693 sll a3,a4,0x1f - -000002fe <.LVL92>: - 2fe: 00f8 add a4,sp,76 - -00000300 <.L120>: - 300: 431c lw a5,0(a4) - 302: 4350 lw a2,4(a4) - 304: 8385 srl a5,a5,0x1 - 306: 067e sll a2,a2,0x1f - 308: 8fd1 or a5,a5,a2 - 30a: c31c sw a5,0(a4) - 30c: 0711 add a4,a4,4 - 30e: fee599e3 bne a1,a4,300 <.L120> - -00000312 <.LVL94>: - 312: 47e6 lw a5,88(sp) - 314: 00d03733 snez a4,a3 - 318: 8385 srl a5,a5,0x1 - 31a: ccbe sw a5,88(sp) - -0000031c <.LBE35>: - 31c: 47b6 lw a5,76(sp) - 31e: 8fd9 or a5,a5,a4 - 320: c6be sw a5,76(sp) - -00000322 <.LBE36>: - 322: 67a1 lui a5,0x8 - 324: 17fd add a5,a5,-1 # 7fff <.LLST157+0x5601> - 326: 22f41263 bne s0,a5,54a <.L11> - -0000032a <.LVL96>: - 32a: cc82 sw zero,88(sp) - 32c: ca82 sw zero,84(sp) - 32e: c882 sw zero,80(sp) - 330: c682 sw zero,76(sp) - -00000332 <.LBB124>: - 332: ac21 j 54a <.L11> - -00000334 <.L33>: - 334: 0005a303 lw t1,0(a1) - 338: 42d2 lw t0,20(sp) - 33a: 0385 add t2,t2,1 - -0000033c <.LVL99>: - 33c: 00d35333 srl t1,t1,a3 - 340: ce1a sw t1,28(sp) - 342: 0045a303 lw t1,4(a1) - 346: 0591 add a1,a1,4 - 348: 00531333 sll t1,t1,t0 - 34c: 42f2 lw t0,28(sp) - 34e: 0062e333 or t1,t0,t1 - 352: 00672023 sw t1,0(a4) - -00000356 <.LVL100>: - 356: 0711 add a4,a4,4 - 358: bdfd j 256 <.L32> - -0000035a <.L50>: - 35a: fff58693 add a3,a1,-1 - -0000035e <.LVL102>: - 35e: ee85 bnez a3,396 <.L51> - -00000360 <.LBB38>: - 360: 4582 lw a1,0(sp) - 362: 009786b3 add a3,a5,s1 - -00000366 <.LVL103>: - 366: c6b6 sw a3,76(sp) - -00000368 <.LVL104>: - 368: 95b2 add a1,a1,a2 - -0000036a <.LVL105>: - 36a: 00f6b6b3 sltu a3,a3,a5 - -0000036e <.LVL106>: - 36e: 4792 lw a5,4(sp) - 370: 96ae add a3,a3,a1 - -00000372 <.LVL107>: - 372: c8b6 sw a3,80(sp) - -00000374 <.LVL108>: - 374: 00c5b633 sltu a2,a1,a2 - -00000378 <.LVL109>: - 378: 00b6b6b3 sltu a3,a3,a1 - -0000037c <.LVL110>: - 37c: 97ba add a5,a5,a4 - -0000037e <.LVL111>: - 37e: 8e55 or a2,a2,a3 - -00000380 <.LVL112>: - 380: 963e add a2,a2,a5 - 382: 00e7b733 sltu a4,a5,a4 - -00000386 <.LVL113>: - 386: cab2 sw a2,84(sp) - -00000388 <.LVL114>: - 388: 00f63633 sltu a2,a2,a5 - -0000038c <.LVL115>: - 38c: 47a2 lw a5,8(sp) - 38e: 8f51 or a4,a4,a2 - -00000390 <.LVL116>: - 390: 953e add a0,a0,a5 - 392: 972a add a4,a4,a0 - 394: bd19 j 1aa <.L354> - -00000396 <.L51>: - 396: 67a1 lui a5,0x8 - 398: 17fd add a5,a5,-1 # 7fff <.LLST157+0x5601> - 39a: 3ef590e3 bne a1,a5,f7a <.L62> - -0000039e <.L63>: - 39e: c6a6 sw s1,76(sp) - -000003a0 <.L364>: - 3a0: 4782 lw a5,0(sp) - 3a2: c8be sw a5,80(sp) - 3a4: 4792 lw a5,4(sp) - 3a6: cabe sw a5,84(sp) - 3a8: 47a2 lw a5,8(sp) - 3aa: ccbe sw a5,88(sp) - -000003ac <.LBB128>: - 3ac: aeb1 j 708 <.L360> - -000003ae <.L270>: - 3ae: 84be mv s1,a5 - 3b0: b7fd j 39e <.L63> - -000003b2 <.L49>: - 3b2: 4752 lw a4,20(sp) - -000003b4 <.LVL122>: - 3b4: 67a1 lui a5,0x8 - 3b6: 17fd add a5,a5,-1 # 7fff <.LLST157+0x5601> - 3b8: fef703e3 beq a4,a5,39e <.L63> - 3bc: 57e2 lw a5,56(sp) - 3be: 00080737 lui a4,0x80 - 3c2: 8fd9 or a5,a5,a4 - 3c4: dc3e sw a5,56(sp) - -000003c6 <.LDL4>: - 3c6: 07400793 li a5,116 - 3ca: 3ab7cce3 blt a5,a1,f82 <.L64> - 3ce: 86ae mv a3,a1 - -000003d0 <.L265>: - 3d0: 41f6d793 sra a5,a3,0x1f - 3d4: 8bfd and a5,a5,31 - 3d6: 97b6 add a5,a5,a3 - 3d8: 8795 sra a5,a5,0x5 - -000003da <.LVL124>: - 3da: 861e mv a2,t2 - 3dc: 4401 li s0,0 - -000003de <.LVL125>: - 3de: 4701 li a4,0 - -000003e0 <.L65>: - 3e0: 02f74663 blt a4,a5,40c <.L66> - 3e4: 460d li a2,3 - 3e6: 01f6f713 and a4,a3,31 - -000003ea <.LVL127>: - 3ea: 40f602b3 sub t0,a2,a5 - 3ee: e705 bnez a4,416 <.L67> - 3f0: 00279613 sll a2,a5,0x2 - -000003f4 <.L68>: - 3f4: 00c386b3 add a3,t2,a2 - 3f8: 4294 lw a3,0(a3) - 3fa: 0705 add a4,a4,1 # 80001 <.LLST157+0x7d603> - -000003fc <.LVL129>: - 3fc: 0391 add t2,t2,4 - 3fe: fed3ae23 sw a3,-4(t2) - -00000402 <.LVL130>: - 402: fee2d9e3 bge t0,a4,3f4 <.L68> - 406: 4511 li a0,4 - 408: 8d1d sub a0,a0,a5 - 40a: a0b5 j 476 <.L74> - -0000040c <.L66>: - 40c: 420c lw a1,0(a2) - 40e: 0705 add a4,a4,1 - -00000410 <.LVL132>: - 410: 0611 add a2,a2,4 - 412: 8c4d or s0,s0,a1 - -00000414 <.LVL133>: - 414: b7f1 j 3e0 <.L65> - -00000416 <.L67>: - 416: 80000637 lui a2,0x80000 - 41a: 067d add a2,a2,31 # 8000001f <.LLST157+0x7fffd621> - 41c: 8ef1 and a3,a3,a2 - -0000041e <.LVL135>: - 41e: 0006d663 bgez a3,42a <.L70> - 422: 16fd add a3,a3,-1 - 424: fe06e693 or a3,a3,-32 - 428: 0685 add a3,a3,1 - -0000042a <.L70>: - 42a: 02000593 li a1,32 - 42e: 8d95 sub a1,a1,a3 - 430: 86be mv a3,a5 - 432: 0007d363 bgez a5,438 <.L71> - -00000436 <.LVL136>: - 436: 4681 li a3,0 - -00000438 <.L71>: - 438: 068a sll a3,a3,0x2 - 43a: 04c68693 add a3,a3,76 - 43e: 1070 add a2,sp,44 - 440: 96b2 add a3,a3,a2 - 442: fb46a683 lw a3,-76(a3) - 446: 4501 li a0,0 - 448: 00b696b3 sll a3,a3,a1 - 44c: 8c55 or s0,s0,a3 - -0000044e <.LVL138>: - 44e: 00279693 sll a3,a5,0x2 - 452: 02c68693 add a3,a3,44 - 456: 968a add a3,a3,sp - -00000458 <.L72>: - 458: 08554463 blt a0,t0,4e0 <.L73> - 45c: 028a sll t0,t0,0x2 - 45e: 4511 li a0,4 - -00000460 <.LVL140>: - 460: 8d1d sub a0,a0,a5 - 462: 1074 add a3,sp,44 - 464: 04c28793 add a5,t0,76 - -00000468 <.LVL142>: - 468: 00d782b3 add t0,a5,a3 - 46c: 57e2 lw a5,56(sp) - 46e: 00e7d7b3 srl a5,a5,a4 - 472: faf2aa23 sw a5,-76(t0) - -00000476 <.L74>: - 476: 4791 li a5,4 - 478: 4601 li a2,0 - 47a: 00a7c563 blt a5,a0,484 <.L76> - 47e: 8f89 sub a5,a5,a0 - 480: 00279613 sll a2,a5,0x2 - -00000484 <.L76>: - 484: 050a sll a0,a0,0x2 - 486: 02c50793 add a5,a0,44 - 48a: 00278533 add a0,a5,sp - 48e: 4581 li a1,0 - 490: 00000097 auipc ra,0x0 - 494: 000080e7 jalr ra # 490 <.L76+0xc> - -00000498 <.LBE40>: - 498: 57b2 lw a5,44(sp) - -0000049a <.LBB41>: - 49a: 00803433 snez s0,s0 - -0000049e <.LBE41>: - 49e: 8c5d or s0,s0,a5 - -000004a0 <.L77>: - 4a0: 57c2 lw a5,48(sp) - 4a2: 4702 lw a4,0(sp) - -000004a4 <.LBB43>: - 4a4: d622 sw s0,44(sp) - -000004a6 <.LBB44>: - 4a6: 9426 add s0,s0,s1 - 4a8: 00e786b3 add a3,a5,a4 - 4ac: 4612 lw a2,4(sp) - 4ae: 5752 lw a4,52(sp) - 4b0: c6a2 sw s0,76(sp) - -000004b2 <.LVL146>: - 4b2: 00943433 sltu s0,s0,s1 - -000004b6 <.LVL147>: - 4b6: 9436 add s0,s0,a3 - -000004b8 <.LVL148>: - 4b8: 00f6b7b3 sltu a5,a3,a5 - -000004bc <.LVL149>: - 4bc: c8a2 sw s0,80(sp) - -000004be <.LVL150>: - 4be: 00d43433 sltu s0,s0,a3 - -000004c2 <.LVL151>: - 4c2: 963a add a2,a2,a4 - -000004c4 <.LVL152>: - 4c4: 8fc1 or a5,a5,s0 - -000004c6 <.LVL153>: - 4c6: 97b2 add a5,a5,a2 - 4c8: cabe sw a5,84(sp) - -000004ca <.LVL154>: - 4ca: 00e63733 sltu a4,a2,a4 - -000004ce <.LVL155>: - 4ce: 00c7b7b3 sltu a5,a5,a2 - -000004d2 <.LVL156>: - 4d2: 8f5d or a4,a4,a5 - -000004d4 <.LVL157>: - 4d4: 46a2 lw a3,8(sp) - -000004d6 <.LVL158>: - 4d6: 57e2 lw a5,56(sp) - -000004d8 <.LBB131>: - 4d8: 4452 lw s0,20(sp) - -000004da <.LBB132>: - 4da: 97b6 add a5,a5,a3 - 4dc: 973e add a4,a4,a5 - -000004de <.LBE45>: - 4de: b501 j 2de <.L23> - -000004e0 <.L73>: - 4e0: 4290 lw a2,0(a3) - 4e2: 0046a303 lw t1,4(a3) - 4e6: 0505 add a0,a0,1 - -000004e8 <.LVL162>: - 4e8: 00e65633 srl a2,a2,a4 - 4ec: 00b31333 sll t1,t1,a1 - 4f0: 00666633 or a2,a2,t1 - 4f4: 00c3a023 sw a2,0(t2) - -000004f8 <.LVL163>: - 4f8: 0691 add a3,a3,4 - 4fa: 0391 add t2,t2,4 - 4fc: bfb1 j 458 <.L72> - -000004fe <.L48>: - 4fe: 6321 lui t1,0x8 - 500: 00140593 add a1,s0,1 - 504: ffe30513 add a0,t1,-2 # 7ffe <.LLST157+0x5600> - 508: 8d6d and a0,a0,a1 - 50a: 5742 lw a4,48(sp) - 50c: 56d2 lw a3,52(sp) - 50e: 5662 lw a2,56(sp) - 510: 18051a63 bnez a0,6a4 <.L88> - 514: 00d765b3 or a1,a4,a3 - 518: 8dd1 or a1,a1,a2 - 51a: 8ddd or a1,a1,a5 - 51c: 14041563 bnez s0,666 <.L89> - -00000520 <.LVL165>: - 520: e991 bnez a1,534 <.L90> - 522: 4782 lw a5,0(sp) - 524: c6a6 sw s1,76(sp) - 526: c8be sw a5,80(sp) - 528: 4792 lw a5,4(sp) - 52a: cabe sw a5,84(sp) - 52c: 47a2 lw a5,8(sp) - 52e: ccbe sw a5,88(sp) - -00000530 <.L357>: - 530: 4401 li s0,0 - 532: a821 j 54a <.L11> - -00000534 <.L90>: - 534: 4512 lw a0,4(sp) - 536: 4582 lw a1,0(sp) - 538: 8dc9 or a1,a1,a0 - 53a: 4522 lw a0,8(sp) - 53c: 8dc9 or a1,a1,a0 - 53e: 8dc5 or a1,a1,s1 - 540: ede1 bnez a1,618 <.L91> - 542: c6be sw a5,76(sp) - 544: c8ba sw a4,80(sp) - 546: cab6 sw a3,84(sp) - 548: ccb2 sw a2,88(sp) - -0000054a <.L11>: - 54a: 47b6 lw a5,76(sp) - 54c: 0077f713 and a4,a5,7 - 550: c71d beqz a4,57e <.L254> - 552: 00f7f713 and a4,a5,15 - 556: 4691 li a3,4 - 558: 02d70363 beq a4,a3,57e <.L254> - -0000055c <.LBB113>: - 55c: 4746 lw a4,80(sp) - 55e: 0791 add a5,a5,4 - 560: c6be sw a5,76(sp) - -00000562 <.LVL169>: - 562: 0047b793 sltiu a5,a5,4 - -00000566 <.LVL170>: - 566: 97ba add a5,a5,a4 - 568: c8be sw a5,80(sp) - -0000056a <.LVL171>: - 56a: 00e7b7b3 sltu a5,a5,a4 - -0000056e <.LVL172>: - 56e: 4756 lw a4,84(sp) - 570: 97ba add a5,a5,a4 - -00000572 <.LVL173>: - 572: cabe sw a5,84(sp) - -00000574 <.LVL174>: - 574: 00e7b7b3 sltu a5,a5,a4 - -00000578 <.LVL175>: - 578: 4766 lw a4,88(sp) - 57a: 97ba add a5,a5,a4 - -0000057c <.LVL176>: - 57c: ccbe sw a5,88(sp) - -0000057e <.L254>: - 57e: 47e6 lw a5,88(sp) - 580: 00080737 lui a4,0x80 - 584: 8f7d and a4,a4,a5 - 586: cb19 beqz a4,59c <.L259> - 588: 6721 lui a4,0x8 - 58a: 0405 add s0,s0,1 - -0000058c <.LVL178>: - 58c: 177d add a4,a4,-1 # 7fff <.LLST157+0x5601> - 58e: 1ce406e3 beq s0,a4,f5a <.L260> - 592: fff80737 lui a4,0xfff80 - 596: 177d add a4,a4,-1 # fff7ffff <.LLST157+0xfff7d601> - 598: 8ff9 and a5,a5,a4 - 59a: ccbe sw a5,88(sp) - -0000059c <.L259>: - 59c: 00fc add a5,sp,76 - 59e: 08b0 add a2,sp,88 - -000005a0 <.L262>: - 5a0: 4398 lw a4,0(a5) - 5a2: 43d4 lw a3,4(a5) - 5a4: 830d srl a4,a4,0x3 - 5a6: 06f6 sll a3,a3,0x1d - 5a8: 8f55 or a4,a4,a3 - 5aa: c398 sw a4,0(a5) - 5ac: 0791 add a5,a5,4 - 5ae: fef619e3 bne a2,a5,5a0 <.L262> - -000005b2 <.LVL181>: - 5b2: 4766 lw a4,88(sp) - -000005b4 <.LBE114>: - 5b4: 66a1 lui a3,0x8 - 5b6: fff68793 add a5,a3,-1 # 7fff <.LLST157+0x5601> - -000005ba <.LBB115>: - 5ba: 830d srl a4,a4,0x3 - 5bc: ccba sw a4,88(sp) - -000005be <.LBE115>: - 5be: 00f41e63 bne s0,a5,5da <.L263> - 5c2: 4646 lw a2,80(sp) - 5c4: 47b6 lw a5,76(sp) - 5c6: 8fd1 or a5,a5,a2 - 5c8: 4656 lw a2,84(sp) - 5ca: 8fd1 or a5,a5,a2 - 5cc: 8fd9 or a5,a5,a4 - 5ce: c791 beqz a5,5da <.L263> - 5d0: ccb6 sw a3,88(sp) - 5d2: ca82 sw zero,84(sp) - 5d4: c882 sw zero,80(sp) - 5d6: c682 sw zero,76(sp) - -000005d8 <.LVL182>: - 5d8: c602 sw zero,12(sp) - -000005da <.L263>: - 5da: 47c2 lw a5,16(sp) - 5dc: 4636 lw a2,76(sp) - 5de: 46c6 lw a3,80(sp) - 5e0: 4756 lw a4,84(sp) - 5e2: 45c2 lw a1,16(sp) - 5e4: c390 sw a2,0(a5) - 5e6: c3d4 sw a3,4(a5) - 5e8: c798 sw a4,8(a5) - 5ea: 47e6 lw a5,88(sp) - 5ec: 0446 sll s0,s0,0x11 - -000005ee <.LVL184>: - 5ee: 8045 srl s0,s0,0x11 - 5f0: 00f59623 sh a5,12(a1) - 5f4: 47b2 lw a5,12(sp) - -000005f6 <.LBE141>: - 5f6: 408a lw ra,128(sp) - 5f8: 54e6 lw s1,120(sp) - -000005fa <.LBB142>: - 5fa: 07be sll a5,a5,0xf - 5fc: 8fc1 or a5,a5,s0 - 5fe: 00f59723 sh a5,14(a1) - 602: 45dc lw a5,12(a1) - -00000604 <.LBE142>: - 604: 45e2 lw a1,24(sp) - 606: 5476 lw s0,124(sp) - 608: c190 sw a2,0(a1) - 60a: c1d4 sw a3,4(a1) - 60c: c598 sw a4,8(a1) - 60e: c5dc sw a5,12(a1) - 610: 852e mv a0,a1 - 612: 08410113 add sp,sp,132 - -00000616 <.LVL186>: - 616: 8082 ret - -00000618 <.L91>: - 618: 4502 lw a0,0(sp) - 61a: 009785b3 add a1,a5,s1 - 61e: c6ae sw a1,76(sp) - -00000620 <.LVL188>: - 620: 953a add a0,a0,a4 - -00000622 <.LVL189>: - 622: 00f5b5b3 sltu a1,a1,a5 - -00000626 <.LVL190>: - 626: 4792 lw a5,4(sp) - 628: 95aa add a1,a1,a0 - -0000062a <.LVL191>: - 62a: c8ae sw a1,80(sp) - -0000062c <.LVL192>: - 62c: 00e53733 sltu a4,a0,a4 - -00000630 <.LVL193>: - 630: 00a5b5b3 sltu a1,a1,a0 - -00000634 <.LVL194>: - 634: 97b6 add a5,a5,a3 - -00000636 <.LVL195>: - 636: 8f4d or a4,a4,a1 - -00000638 <.LVL196>: - 638: 973e add a4,a4,a5 - 63a: 00d7b6b3 sltu a3,a5,a3 - -0000063e <.LVL197>: - 63e: caba sw a4,84(sp) - -00000640 <.LVL198>: - 640: 00f73733 sltu a4,a4,a5 - -00000644 <.LVL199>: - 644: 47a2 lw a5,8(sp) - 646: 8ed9 or a3,a3,a4 - -00000648 <.LVL200>: - 648: 963e add a2,a2,a5 - 64a: 96b2 add a3,a3,a2 - -0000064c <.LBE47>: - 64c: 000807b7 lui a5,0x80 - 650: 8ff5 and a5,a5,a3 - 652: e399 bnez a5,658 <.L102> - -00000654 <.LBB48>: - 654: ccb6 sw a3,88(sp) - 656: bde9 j 530 <.L357> - -00000658 <.L102>: - 658: fff807b7 lui a5,0xfff80 - 65c: 17fd add a5,a5,-1 # fff7ffff <.LLST157+0xfff7d601> - 65e: 8efd and a3,a3,a5 - 660: ccb6 sw a3,88(sp) - -00000662 <.LBB144>: - 662: 4405 li s0,1 - -00000664 <.LVL202>: - 664: b5dd j 54a <.L11> - -00000666 <.L89>: - 666: b40588e3 beqz a1,1b6 <.L268> - 66a: 4512 lw a0,4(sp) - 66c: 4582 lw a1,0(sp) - 66e: 8dc9 or a1,a1,a0 - 670: 4522 lw a0,8(sp) - 672: 8dc9 or a1,a1,a0 - 674: 8dc5 or a1,a1,s1 - 676: b40582e3 beqz a1,1ba <.L269> - -0000067a <.LBB147>: - 67a: cc9a sw t1,88(sp) - 67c: ca82 sw zero,84(sp) - 67e: c882 sw zero,80(sp) - 680: c682 sw zero,76(sp) - -00000682 <.LBB49>: - 682: 00fc add a5,sp,76 - 684: 0090 add a2,sp,64 - -00000686 <.L105>: - 686: 47d8 lw a4,12(a5) - 688: 4794 lw a3,8(a5) - 68a: 17f1 add a5,a5,-4 - 68c: 070e sll a4,a4,0x3 - 68e: 82f5 srl a3,a3,0x1d - 690: 8f55 or a4,a4,a3 - 692: cb98 sw a4,16(a5) - 694: fef619e3 bne a2,a5,686 <.L105> - -00000698 <.L355>: - 698: 47b6 lw a5,76(sp) - -0000069a <.LBE72>: - 69a: 6421 lui s0,0x8 - -0000069c <.LVL208>: - 69c: 147d add s0,s0,-1 # 7fff <.LLST157+0x5601> - -0000069e <.LBB73>: - 69e: 078e sll a5,a5,0x3 - -000006a0 <.LBB149>: - 6a0: c6be sw a5,76(sp) - 6a2: a965 j b5a <.L359> - -000006a4 <.L88>: - 6a4: 4402 lw s0,0(sp) - -000006a6 <.LVL210>: - 6a6: 00978533 add a0,a5,s1 - 6aa: c6aa sw a0,76(sp) - -000006ac <.LVL211>: - 6ac: 00870333 add t1,a4,s0 - -000006b0 <.LVL212>: - 6b0: 00f53533 sltu a0,a0,a5 - -000006b4 <.LVL213>: - 6b4: 4792 lw a5,4(sp) - 6b6: 951a add a0,a0,t1 - -000006b8 <.LVL214>: - 6b8: c8aa sw a0,80(sp) - -000006ba <.LVL215>: - 6ba: 00e33733 sltu a4,t1,a4 - -000006be <.LVL216>: - 6be: 00653533 sltu a0,a0,t1 - -000006c2 <.LVL217>: - 6c2: 97b6 add a5,a5,a3 - -000006c4 <.LVL218>: - 6c4: 8f49 or a4,a4,a0 - -000006c6 <.LVL219>: - 6c6: 973e add a4,a4,a5 - 6c8: 00d7b6b3 sltu a3,a5,a3 - -000006cc <.LVL220>: - 6cc: caba sw a4,84(sp) - -000006ce <.LVL221>: - 6ce: 00f73733 sltu a4,a4,a5 - -000006d2 <.LVL222>: - 6d2: 47a2 lw a5,8(sp) - 6d4: 8ed9 or a3,a3,a4 - -000006d6 <.LVL223>: - 6d6: 963e add a2,a2,a5 - 6d8: 96b2 add a3,a3,a2 - 6da: ccb6 sw a3,88(sp) - -000006dc <.LBB51>: - 6dc: 00fc add a5,sp,76 - -000006de <.LVL225>: - 6de: 08b0 add a2,sp,88 - -000006e0 <.L117>: - 6e0: 4398 lw a4,0(a5) - 6e2: 43d4 lw a3,4(a5) - 6e4: 8305 srl a4,a4,0x1 - 6e6: 06fe sll a3,a3,0x1f - 6e8: 8f55 or a4,a4,a3 - 6ea: c398 sw a4,0(a5) - 6ec: 0791 add a5,a5,4 - 6ee: fef619e3 bne a2,a5,6e0 <.L117> - -000006f2 <.LBE51>: - 6f2: 6721 lui a4,0x8 - 6f4: 177d add a4,a4,-1 # 7fff <.LLST157+0x5601> - -000006f6 <.LBB52>: - 6f6: 47e6 lw a5,88(sp) - -000006f8 <.LBE52>: - 6f8: 00e58463 beq a1,a4,700 <.L118> - -000006fc <.LBB53>: - 6fc: 8385 srl a5,a5,0x1 - 6fe: bc21 j 116 <.L362> - -00000700 <.L118>: - 700: cc82 sw zero,88(sp) - 702: ca82 sw zero,84(sp) - 704: c882 sw zero,80(sp) - 706: c682 sw zero,76(sp) - -00000708 <.L360>: - 708: 6421 lui s0,0x8 - 70a: 147d add s0,s0,-1 # 7fff <.LLST157+0x5601> - 70c: bd3d j 54a <.L11> - -0000070e <.L8>: - 70e: 1ec05f63 blez a2,90c <.L7> - -00000712 <.LBB155>: - 712: 56c2 lw a3,48(sp) - 714: c036 sw a3,0(sp) - 716: 56d2 lw a3,52(sp) - 718: c236 sw a3,4(sp) - 71a: 56e2 lw a3,56(sp) - 71c: c436 sw a3,8(sp) - -0000071e <.LBB156>: - 71e: 46d2 lw a3,20(sp) - 720: e2d1 bnez a3,7a4 <.L123> - 722: 4286 lw t0,64(sp) - 724: 4516 lw a0,68(sp) - 726: 46a6 lw a3,72(sp) - 728: 00a2e5b3 or a1,t0,a0 - -0000072c <.LVL232>: - 72c: 8dd5 or a1,a1,a3 - 72e: 8dc5 or a1,a1,s1 - 730: a20587e3 beqz a1,15e <.L358> - 734: fff60593 add a1,a2,-1 - -00000738 <.LVL233>: - 738: e9b9 bnez a1,78e <.L125> - -0000073a <.LBB75>: - 73a: 4602 lw a2,0(sp) - 73c: 4402 lw s0,0(sp) - -0000073e <.LVL235>: - 73e: 40978733 sub a4,a5,s1 - -00000742 <.LVL236>: - 742: 40560633 sub a2,a2,t0 - 746: 00e7b333 sltu t1,a5,a4 - 74a: 00c43433 sltu s0,s0,a2 - -0000074e <.LVL237>: - 74e: 40660633 sub a2,a2,t1 - -00000752 <.LVL238>: - 752: 4312 lw t1,4(sp) - 754: 84a2 mv s1,s0 - -00000756 <.LVL239>: - 756: 40a303b3 sub t2,t1,a0 - 75a: 00a33333 sltu t1,t1,a0 - 75e: 00e7fc63 bgeu a5,a4,776 <.L130> - 762: 4782 lw a5,0(sp) - 764: 00f29963 bne t0,a5,776 <.L130> - -00000768 <.LVL240>: - 768: fff38793 add a5,t2,-1 - -0000076c <.L131>: - 76c: 4592 lw a1,4(sp) - -0000076e <.LVL242>: - 76e: 8d0d sub a0,a0,a1 - 770: 00153593 seqz a1,a0 - 774: a021 j 77c <.L132> - -00000776 <.L130>: - 776: 409387b3 sub a5,t2,s1 - -0000077a <.LVL244>: - 77a: f86d bnez s0,76c <.L131> - -0000077c <.L132>: - 77c: 4522 lw a0,8(sp) - 77e: 0065e333 or t1,a1,t1 - -00000782 <.LVL246>: - 782: 40d506b3 sub a3,a0,a3 - 786: 406686b3 sub a3,a3,t1 - -0000078a <.L356>: - 78a: 4405 li s0,1 - -0000078c <.LBB158>: - 78c: a295 j 8f0 <.L133> - -0000078e <.L125>: - 78e: a26602e3 beq a2,t1,1b2 <.L365> - 792: 07400693 li a3,116 - 796: 02b6d363 bge a3,a1,7bc <.L266> - -0000079a <.L135>: - 79a: c482 sw zero,72(sp) - 79c: c282 sw zero,68(sp) - 79e: c082 sw zero,64(sp) - 7a0: 4705 li a4,1 - 7a2: a8c9 j 874 <.L146> - -000007a4 <.L123>: - 7a4: c06405e3 beq s0,t1,3ae <.L270> - 7a8: 46a6 lw a3,72(sp) - -000007aa <.LVL251>: - 7aa: 000805b7 lui a1,0x80 - -000007ae <.LVL252>: - 7ae: 8ecd or a3,a3,a1 - 7b0: c4b6 sw a3,72(sp) - -000007b2 <.LDL5>: - 7b2: 07400693 li a3,116 - 7b6: fec6c2e3 blt a3,a2,79a <.L135> - 7ba: 85b2 mv a1,a2 - -000007bc <.L266>: - 7bc: 4055d513 sra a0,a1,0x5 - -000007c0 <.LVL254>: - 7c0: 863a mv a2,a4 - 7c2: 89fd and a1,a1,31 - -000007c4 <.LVL255>: - 7c4: 4481 li s1,0 - 7c6: 4681 li a3,0 - -000007c8 <.L136>: - 7c8: 02a69463 bne a3,a0,7f0 <.L137> - 7cc: 468d li a3,3 - -000007ce <.LVL257>: - 7ce: 8e89 sub a3,a3,a0 - 7d0: 00251613 sll a2,a0,0x2 - 7d4: e58d bnez a1,7fe <.L138> - -000007d6 <.L139>: - 7d6: 00c70333 add t1,a4,a2 - 7da: 00032303 lw t1,0(t1) - 7de: 0585 add a1,a1,1 # 80001 <.LLST157+0x7d603> - -000007e0 <.LVL259>: - 7e0: 00672023 sw t1,0(a4) - -000007e4 <.LVL260>: - 7e4: 0711 add a4,a4,4 - 7e6: feb6d8e3 bge a3,a1,7d6 <.L139> - 7ea: 4711 li a4,4 - 7ec: 8f09 sub a4,a4,a0 - 7ee: a899 j 844 <.L143> - -000007f0 <.L137>: - 7f0: 00062303 lw t1,0(a2) - 7f4: 0685 add a3,a3,1 - -000007f6 <.LVL262>: - 7f6: 0611 add a2,a2,4 - 7f8: 0064e4b3 or s1,s1,t1 - -000007fc <.LVL263>: - 7fc: b7f1 j 7c8 <.L136> - -000007fe <.L138>: - 7fe: 02000293 li t0,32 - 802: 40b28333 sub t1,t0,a1 - 806: ca1a sw t1,20(sp) - -00000808 <.LVL265>: - 808: 02c10293 add t0,sp,44 - 80c: 04c60313 add t1,a2,76 - 810: 9316 add t1,t1,t0 - 812: fc432303 lw t1,-60(t1) - 816: 42d2 lw t0,20(sp) - 818: 4381 li t2,0 - 81a: 00531333 sll t1,t1,t0 - 81e: 0064e4b3 or s1,s1,t1 - -00000822 <.LVL266>: - 822: 03c10313 add t1,sp,60 - 826: 961a add a2,a2,t1 - -00000828 <.L141>: - 828: 08d3c563 blt t2,a3,8b2 <.L142> - 82c: 068a sll a3,a3,0x2 - 82e: 1070 add a2,sp,44 - 830: 04c68693 add a3,a3,76 - 834: 96b2 add a3,a3,a2 - 836: 4626 lw a2,72(sp) - 838: 4711 li a4,4 - 83a: 8f09 sub a4,a4,a0 - -0000083c <.LVL268>: - 83c: 00b65633 srl a2,a2,a1 - 840: fcc6a223 sw a2,-60(a3) - -00000844 <.L143>: - 844: 4691 li a3,4 - 846: 8e99 sub a3,a3,a4 - 848: 1870 add a2,sp,60 - 84a: 070a sll a4,a4,0x2 - 84c: 9732 add a4,a4,a2 - 84e: 068a sll a3,a3,0x2 - 850: 4621 li a2,8 - 852: 00c6e863 bltu a3,a2,862 <.L144> - 856: 00072023 sw zero,0(a4) - -0000085a <.LVL270>: - 85a: 00072223 sw zero,4(a4) - 85e: 16e1 add a3,a3,-8 - 860: 0721 add a4,a4,8 - -00000862 <.L144>: - 862: 4611 li a2,4 - 864: 00c6e463 bltu a3,a2,86c <.L145> - 868: 00072023 sw zero,0(a4) - -0000086c <.L145>: - 86c: 56f2 lw a3,60(sp) - -0000086e <.LBB78>: - 86e: 00903733 snez a4,s1 - -00000872 <.LBE78>: - 872: 8f55 or a4,a4,a3 - -00000874 <.L146>: - 874: 4682 lw a3,0(sp) - -00000876 <.LBB80>: - 876: 4506 lw a0,64(sp) - -00000878 <.LBB81>: - 878: de3a sw a4,60(sp) - -0000087a <.LBB82>: - 87a: 40e78733 sub a4,a5,a4 - -0000087e <.LVL274>: - 87e: 40a68633 sub a2,a3,a0 - 882: 00c6b2b3 sltu t0,a3,a2 - -00000886 <.LVL275>: - 886: 00e7b6b3 sltu a3,a5,a4 - 88a: 4592 lw a1,4(sp) - 88c: 4492 lw s1,4(sp) - 88e: 8e15 sub a2,a2,a3 - -00000890 <.LVL276>: - 890: 4696 lw a3,68(sp) - 892: 8396 mv t2,t0 - -00000894 <.LVL277>: - 894: 8d95 sub a1,a1,a3 - 896: 00d4b333 sltu t1,s1,a3 - 89a: 02e7ff63 bgeu a5,a4,8d8 <.L151> - 89e: 4782 lw a5,0(sp) - 8a0: 02f51c63 bne a0,a5,8d8 <.L151> - -000008a4 <.LVL278>: - 8a4: fff58793 add a5,a1,-1 - -000008a8 <.L152>: - 8a8: 4592 lw a1,4(sp) - 8aa: 8e8d sub a3,a3,a1 - 8ac: 0016b593 seqz a1,a3 - 8b0: a80d j 8e2 <.L153> - -000008b2 <.L142>: - 8b2: 00062303 lw t1,0(a2) - 8b6: 42d2 lw t0,20(sp) - 8b8: 0385 add t2,t2,1 - -000008ba <.LVL281>: - 8ba: 00b35333 srl t1,t1,a1 - 8be: ce1a sw t1,28(sp) - 8c0: 00462303 lw t1,4(a2) - 8c4: 0611 add a2,a2,4 - 8c6: 00531333 sll t1,t1,t0 - 8ca: 42f2 lw t0,28(sp) - 8cc: 0062e333 or t1,t0,t1 - 8d0: 00672023 sw t1,0(a4) - -000008d4 <.LVL282>: - 8d4: 0711 add a4,a4,4 - 8d6: bf89 j 828 <.L141> - -000008d8 <.L151>: - 8d8: 407587b3 sub a5,a1,t2 - -000008dc <.LVL284>: - 8dc: 4581 li a1,0 - 8de: fc0295e3 bnez t0,8a8 <.L152> - -000008e2 <.L153>: - 8e2: 46a6 lw a3,72(sp) - 8e4: 4522 lw a0,8(sp) - 8e6: 0065e5b3 or a1,a1,t1 - -000008ea <.LVL286>: - 8ea: 40d506b3 sub a3,a0,a3 - 8ee: 8e8d sub a3,a3,a1 - -000008f0 <.L133>: - 8f0: cabe sw a5,84(sp) - -000008f2 <.LBE85>: - 8f2: 000807b7 lui a5,0x80 - -000008f6 <.LBB86>: - 8f6: c6ba sw a4,76(sp) - -000008f8 <.LBB87>: - 8f8: ccb6 sw a3,88(sp) - 8fa: c8b2 sw a2,80(sp) - -000008fc <.LBE87>: - 8fc: 00f6f733 and a4,a3,a5 - 900: c40705e3 beqz a4,54a <.L11> - -00000904 <.LBB88>: - 904: 17fd add a5,a5,-1 # 7ffff <.LLST157+0x7d601> - 906: 8efd and a3,a3,a5 - 908: ccb6 sw a3,88(sp) - 90a: a991 j d5e <.L229> - -0000090c <.L7>: - 90c: 4716 lw a4,68(sp) - 90e: 4286 lw t0,64(sp) - 910: c03a sw a4,0(sp) - 912: 4726 lw a4,72(sp) - 914: c43a sw a4,8(sp) - -00000916 <.LBB159>: - 916: 20060163 beqz a2,b18 <.L154> - 91a: 4752 lw a4,20(sp) - 91c: 8f01 sub a4,a4,s0 - -0000091e <.LVL290>: - 91e: e851 bnez s0,9b2 <.L155> - 920: 5442 lw s0,48(sp) - -00000922 <.LVL291>: - 922: 5552 lw a0,52(sp) - 924: 56e2 lw a3,56(sp) - 926: 00a46633 or a2,s0,a0 - 92a: 8e55 or a2,a2,a3 - 92c: 8e5d or a2,a2,a5 - 92e: ea19 bnez a2,944 <.L156> - -00000930 <.LVL292>: - 930: 4782 lw a5,0(sp) - 932: c6a6 sw s1,76(sp) - 934: c896 sw t0,80(sp) - 936: cabe sw a5,84(sp) - 938: 47a2 lw a5,8(sp) - -0000093a <.LBB160>: - 93a: 843a mv s0,a4 - -0000093c <.LBB161>: - 93c: ccbe sw a5,88(sp) - -0000093e <.L208>: - 93e: 4792 lw a5,4(sp) - 940: c63e sw a5,12(sp) - 942: b121 j 54a <.L11> - -00000944 <.L156>: - 944: fff70593 add a1,a4,-1 - -00000948 <.LVL295>: - 948: e9a1 bnez a1,998 <.L157> - -0000094a <.LBB89>: - 94a: 40f48733 sub a4,s1,a5 - -0000094e <.LVL297>: - 94e: 40828633 sub a2,t0,s0 - 952: 00e4b7b3 sltu a5,s1,a4 - 956: 00c2b3b3 sltu t2,t0,a2 - -0000095a <.LVL298>: - 95a: 4302 lw t1,0(sp) - 95c: 8e1d sub a2,a2,a5 - -0000095e <.LVL299>: - 95e: 4782 lw a5,0(sp) - 960: c61e sw t2,12(sp) - -00000962 <.LVL300>: - 962: 00a33333 sltu t1,t1,a0 - 966: 8f89 sub a5,a5,a0 - 968: 00e4fa63 bgeu s1,a4,97c <.L162> - 96c: 00541863 bne s0,t0,97c <.L162> - -00000970 <.LVL301>: - 970: 17fd add a5,a5,-1 - -00000972 <.L163>: - 972: 4582 lw a1,0(sp) - -00000974 <.LVL303>: - 974: 8d0d sub a0,a0,a1 - 976: 00153593 seqz a1,a0 - 97a: a029 j 984 <.L164> - -0000097c <.L162>: - 97c: 4432 lw s0,12(sp) - 97e: 8f81 sub a5,a5,s0 - -00000980 <.LVL305>: - 980: fe0399e3 bnez t2,972 <.L163> - -00000984 <.L164>: - 984: 4522 lw a0,8(sp) - 986: 0065e333 or t1,a1,t1 - -0000098a <.LBE89>: - 98a: 4592 lw a1,4(sp) - -0000098c <.LBB90>: - 98c: 40d506b3 sub a3,a0,a3 - 990: 406686b3 sub a3,a3,t1 - -00000994 <.LBE90>: - 994: c62e sw a1,12(sp) - 996: bbd5 j 78a <.L356> - -00000998 <.L157>: - 998: 67a1 lui a5,0x8 - 99a: 17fd add a5,a5,-1 # 7fff <.LLST157+0x5601> - 99c: 5ef71963 bne a4,a5,f8e <.L165> - -000009a0 <.L166>: - 9a0: 4782 lw a5,0(sp) - 9a2: c6a6 sw s1,76(sp) - 9a4: c896 sw t0,80(sp) - 9a6: cabe sw a5,84(sp) - 9a8: 47a2 lw a5,8(sp) - 9aa: ccbe sw a5,88(sp) - 9ac: 4792 lw a5,4(sp) - 9ae: c63e sw a5,12(sp) - -000009b0 <.LVL310>: - 9b0: bba1 j 708 <.L360> - -000009b2 <.L155>: - 9b2: 46d2 lw a3,20(sp) - 9b4: 67a1 lui a5,0x8 - 9b6: 17fd add a5,a5,-1 # 7fff <.LLST157+0x5601> - 9b8: fef684e3 beq a3,a5,9a0 <.L166> - 9bc: 57e2 lw a5,56(sp) - 9be: 000806b7 lui a3,0x80 - 9c2: 8fd5 or a5,a5,a3 - 9c4: dc3e sw a5,56(sp) - -000009c6 <.LDL6>: - 9c6: 07400793 li a5,116 - 9ca: 5ce7c663 blt a5,a4,f96 <.L167> - 9ce: 85ba mv a1,a4 - -000009d0 <.L267>: - 9d0: 41f5d793 sra a5,a1,0x1f - 9d4: 8bfd and a5,a5,31 - 9d6: 97ae add a5,a5,a1 - 9d8: 8795 sra a5,a5,0x5 - -000009da <.LVL313>: - 9da: 869e mv a3,t2 - 9dc: 4401 li s0,0 - 9de: 4701 li a4,0 - -000009e0 <.L168>: - 9e0: 02f74663 blt a4,a5,a0c <.L169> - 9e4: 468d li a3,3 - 9e6: 01f5f713 and a4,a1,31 - -000009ea <.LVL315>: - 9ea: 40f680b3 sub ra,a3,a5 - 9ee: e705 bnez a4,a16 <.L170> - 9f0: 00279613 sll a2,a5,0x2 - -000009f4 <.L171>: - 9f4: 00c386b3 add a3,t2,a2 - 9f8: 4294 lw a3,0(a3) - 9fa: 0705 add a4,a4,1 - -000009fc <.LVL317>: - 9fc: 0391 add t2,t2,4 - 9fe: fed3ae23 sw a3,-4(t2) - -00000a02 <.LVL318>: - a02: fee0d9e3 bge ra,a4,9f4 <.L171> - a06: 4511 li a0,4 - a08: 8d1d sub a0,a0,a5 - a0a: a0b5 j a76 <.L177> - -00000a0c <.L169>: - a0c: 4290 lw a2,0(a3) - a0e: 0705 add a4,a4,1 - -00000a10 <.LVL319>: - a10: 0691 add a3,a3,4 # 80004 <.LLST157+0x7d606> - a12: 8c51 or s0,s0,a2 - -00000a14 <.LVL320>: - a14: b7f1 j 9e0 <.L168> - -00000a16 <.L170>: - a16: 800006b7 lui a3,0x80000 - a1a: 06fd add a3,a3,31 # 8000001f <.LLST157+0x7fffd621> - a1c: 8eed and a3,a3,a1 - a1e: 0006d663 bgez a3,a2a <.L173> - a22: 16fd add a3,a3,-1 - a24: fe06e693 or a3,a3,-32 - a28: 0685 add a3,a3,1 - -00000a2a <.L173>: - a2a: 02000593 li a1,32 - -00000a2e <.LVL322>: - a2e: 8d95 sub a1,a1,a3 - a30: 86be mv a3,a5 - a32: 0007d363 bgez a5,a38 <.L174> - -00000a36 <.LVL323>: - a36: 4681 li a3,0 - -00000a38 <.L174>: - a38: 068a sll a3,a3,0x2 - a3a: 04c68693 add a3,a3,76 - a3e: 1070 add a2,sp,44 - a40: 96b2 add a3,a3,a2 - a42: fb46a683 lw a3,-76(a3) - a46: 4501 li a0,0 - a48: 00b696b3 sll a3,a3,a1 - a4c: 8c55 or s0,s0,a3 - -00000a4e <.LVL325>: - a4e: 00279693 sll a3,a5,0x2 - a52: 02c68693 add a3,a3,44 - a56: 968a add a3,a3,sp - -00000a58 <.L175>: - a58: 08154263 blt a0,ra,adc <.L176> - a5c: 4511 li a0,4 - -00000a5e <.LVL327>: - a5e: 8d1d sub a0,a0,a5 - -00000a60 <.LVL328>: - a60: 00209793 sll a5,ra,0x2 - -00000a64 <.LVL329>: - a64: 04c78793 add a5,a5,76 - a68: 1074 add a3,sp,44 - a6a: 96be add a3,a3,a5 - a6c: 57e2 lw a5,56(sp) - a6e: 00e7d7b3 srl a5,a5,a4 - a72: faf6aa23 sw a5,-76(a3) - -00000a76 <.L177>: - a76: 4791 li a5,4 - a78: 4601 li a2,0 - a7a: 00a7c563 blt a5,a0,a84 <.L179> - a7e: 8f89 sub a5,a5,a0 - a80: 00279613 sll a2,a5,0x2 - -00000a84 <.L179>: - a84: 050a sll a0,a0,0x2 - a86: 02c50793 add a5,a0,44 - a8a: 00278533 add a0,a5,sp - a8e: 4581 li a1,0 - a90: c616 sw t0,12(sp) - -00000a92 <.LVL331>: - a92: 00000097 auipc ra,0x0 - a96: 000080e7 jalr ra # a92 <.LVL331> - -00000a9a <.LBE92>: - a9a: 57b2 lw a5,44(sp) - -00000a9c <.LBE91>: - a9c: 42b2 lw t0,12(sp) - -00000a9e <.LBB93>: - a9e: 00803733 snez a4,s0 - -00000aa2 <.LBE93>: - aa2: 8f5d or a4,a4,a5 - -00000aa4 <.L180>: - aa4: 55c2 lw a1,48(sp) - -00000aa6 <.LBB97>: - aa6: d63a sw a4,44(sp) - -00000aa8 <.LBB98>: - aa8: 40e48733 sub a4,s1,a4 - -00000aac <.LVL335>: - aac: 40b28633 sub a2,t0,a1 - ab0: 00e4b7b3 sltu a5,s1,a4 - ab4: 56d2 lw a3,52(sp) - ab6: 00c2b333 sltu t1,t0,a2 - -00000aba <.LVL336>: - aba: 4502 lw a0,0(sp) - abc: 8e1d sub a2,a2,a5 - -00000abe <.LVL337>: - abe: 4782 lw a5,0(sp) - ac0: 839a mv t2,t1 - -00000ac2 <.LVL338>: - ac2: 00d53533 sltu a0,a0,a3 - ac6: 8f95 sub a5,a5,a3 - ac8: 02e4f963 bgeu s1,a4,afa <.L185> - acc: 02559763 bne a1,t0,afa <.L185> - -00000ad0 <.LVL339>: - ad0: 17fd add a5,a5,-1 - -00000ad2 <.L186>: - ad2: 4582 lw a1,0(sp) - ad4: 8e8d sub a3,a3,a1 - ad6: 0016b593 seqz a1,a3 - ada: a02d j b04 <.L187> - -00000adc <.L176>: - adc: 4290 lw a2,0(a3) - ade: 0046a303 lw t1,4(a3) - ae2: 0505 add a0,a0,1 - -00000ae4 <.LVL342>: - ae4: 00e65633 srl a2,a2,a4 - ae8: 00b31333 sll t1,t1,a1 - aec: 00666633 or a2,a2,t1 - af0: 00c3a023 sw a2,0(t2) - -00000af4 <.LVL343>: - af4: 0691 add a3,a3,4 - af6: 0391 add t2,t2,4 - af8: b785 j a58 <.L175> - -00000afa <.L185>: - afa: 407787b3 sub a5,a5,t2 - -00000afe <.LVL345>: - afe: 4581 li a1,0 - b00: fc0319e3 bnez t1,ad2 <.L186> - -00000b04 <.L187>: - b04: 4422 lw s0,8(sp) - b06: 56e2 lw a3,56(sp) - b08: 8dc9 or a1,a1,a0 - -00000b0a <.LVL347>: - b0a: 40d406b3 sub a3,s0,a3 - b0e: 8e8d sub a3,a3,a1 - -00000b10 <.LBE100>: - b10: 4592 lw a1,4(sp) - -00000b12 <.LBB164>: - b12: 4452 lw s0,20(sp) - -00000b14 <.LBB165>: - b14: c62e sw a1,12(sp) - b16: bbe9 j 8f0 <.L133> - -00000b18 <.L154>: - b18: 6621 lui a2,0x8 - b1a: 00140593 add a1,s0,1 - b1e: ffe60513 add a0,a2,-2 # 7ffe <.LLST157+0x5600> - b22: 8de9 and a1,a1,a0 - -00000b24 <.LBB166>: - b24: 56c2 lw a3,48(sp) - b26: 5752 lw a4,52(sp) - b28: 53e2 lw t2,56(sp) - -00000b2a <.LBB167>: - b2a: 16059963 bnez a1,c9c <.L188> - b2e: 4582 lw a1,0(sp) - b30: 4522 lw a0,8(sp) - b32: 00b2e5b3 or a1,t0,a1 - b36: 8dc9 or a1,a1,a0 - b38: 00e6e533 or a0,a3,a4 - b3c: 00756533 or a0,a0,t2 - b40: 8dc5 or a1,a1,s1 - b42: 8d5d or a0,a0,a5 - b44: e86d bnez s0,c36 <.L189> - -00000b46 <.LVL350>: - b46: ed01 bnez a0,b5e <.L190> - b48: 4782 lw a5,0(sp) - b4a: c6a6 sw s1,76(sp) - b4c: c896 sw t0,80(sp) - b4e: cabe sw a5,84(sp) - b50: 47a2 lw a5,8(sp) - b52: ccbe sw a5,88(sp) - b54: de0595e3 bnez a1,93e <.L208> - -00000b58 <.L191>: - b58: 4401 li s0,0 - -00000b5a <.L359>: - b5a: c602 sw zero,12(sp) - -00000b5c <.LVL353>: - b5c: b2fd j 54a <.L11> - -00000b5e <.L190>: - b5e: e591 bnez a1,b6a <.L192> - b60: c6be sw a5,76(sp) - b62: c8b6 sw a3,80(sp) - b64: caba sw a4,84(sp) - b66: cc9e sw t2,88(sp) - -00000b68 <.LBB170>: - b68: b2e1 j 530 <.L357> - -00000b6a <.L192>: - b6a: 40978633 sub a2,a5,s1 - -00000b6e <.LVL357>: - b6e: 40568533 sub a0,a3,t0 - b72: 00c7b333 sltu t1,a5,a2 - b76: 00a6b5b3 sltu a1,a3,a0 - b7a: 40650533 sub a0,a0,t1 - b7e: ca2a sw a0,20(sp) - -00000b80 <.LVL358>: - b80: 4502 lw a0,0(sp) - b82: d02e sw a1,32(sp) - -00000b84 <.LVL359>: - b84: 40a70333 sub t1,a4,a0 - b88: 00a73533 sltu a0,a4,a0 - b8c: d22a sw a0,36(sp) - b8e: 00c7fa63 bgeu a5,a2,ba2 <.L197> - b92: 00569863 bne a3,t0,ba2 <.L197> - -00000b96 <.LVL360>: - b96: fff30593 add a1,t1,-1 - -00000b9a <.L198>: - b9a: 00133513 seqz a0,t1 - b9e: ce2a sw a0,28(sp) - ba0: a031 j bac <.L199> - -00000ba2 <.L197>: - ba2: 5502 lw a0,32(sp) - ba4: ce02 sw zero,28(sp) - ba6: 40b305b3 sub a1,t1,a1 - -00000baa <.LVL363>: - baa: f965 bnez a0,b9a <.L198> - -00000bac <.L199>: - bac: 4522 lw a0,8(sp) - bae: 4372 lw t1,28(sp) - bb0: caae sw a1,84(sp) - bb2: 40a38533 sub a0,t2,a0 - bb6: d02a sw a0,32(sp) - bb8: 5512 lw a0,36(sp) - bba: c6b2 sw a2,76(sp) - bbc: 00a36533 or a0,t1,a0 - -00000bc0 <.LVL365>: - bc0: 5302 lw t1,32(sp) - bc2: 40a30333 sub t1,t1,a0 - bc6: 4552 lw a0,20(sp) - -00000bc8 <.LVL366>: - bc8: cc9a sw t1,88(sp) - bca: c8aa sw a0,80(sp) - -00000bcc <.LBE101>: - bcc: 00080537 lui a0,0x80 - bd0: 00a37533 and a0,t1,a0 - bd4: c931 beqz a0,c28 <.L200> - -00000bd6 <.LBB102>: - bd6: 40f487b3 sub a5,s1,a5 - -00000bda <.LVL368>: - bda: 40d28633 sub a2,t0,a3 - -00000bde <.LVL369>: - bde: 00f4b5b3 sltu a1,s1,a5 - -00000be2 <.LVL370>: - be2: 00c2b333 sltu t1,t0,a2 - -00000be6 <.LVL371>: - be6: 4502 lw a0,0(sp) - be8: 8e0d sub a2,a2,a1 - -00000bea <.LVL372>: - bea: 4582 lw a1,0(sp) - bec: c61a sw t1,12(sp) - -00000bee <.LVL373>: - bee: 00e53533 sltu a0,a0,a4 - bf2: 8d99 sub a1,a1,a4 - bf4: 00f4fb63 bgeu s1,a5,c0a <.L205> - bf8: 00569963 bne a3,t0,c0a <.L205> - -00000bfc <.LVL374>: - bfc: 15fd add a1,a1,-1 - -00000bfe <.L206>: - bfe: 4682 lw a3,0(sp) - c00: 40d706b3 sub a3,a4,a3 - c04: 0016b693 seqz a3,a3 - c08: a031 j c14 <.L207> - -00000c0a <.L205>: - c0a: 46b2 lw a3,12(sp) - c0c: 8d95 sub a1,a1,a3 - -00000c0e <.LVL377>: - c0e: 4681 li a3,0 - c10: fe0317e3 bnez t1,bfe <.L206> - -00000c14 <.L207>: - c14: 4722 lw a4,8(sp) - c16: 8ec9 or a3,a3,a0 - -00000c18 <.LVL379>: - c18: caae sw a1,84(sp) - -00000c1a <.LVL380>: - c1a: 40770733 sub a4,a4,t2 - c1e: 8f15 sub a4,a4,a3 - c20: ccba sw a4,88(sp) - c22: c8b2 sw a2,80(sp) - c24: c6be sw a5,76(sp) - -00000c26 <.LBB172>: - c26: bb21 j 93e <.L208> - -00000c28 <.L200>: - c28: 47d2 lw a5,20(sp) - c2a: 8e5d or a2,a2,a5 - -00000c2c <.LVL383>: - c2c: 8e4d or a2,a2,a1 - c2e: 00666633 or a2,a2,t1 - c32: d21d beqz a2,b58 <.L191> - c34: b8f5 j 530 <.L357> - -00000c36 <.L189>: - c36: ed0d bnez a0,c70 <.L209> - c38: e18d bnez a1,c5a <.L210> - -00000c3a <.LVL385>: - c3a: ccb2 sw a2,88(sp) - c3c: ca82 sw zero,84(sp) - c3e: c882 sw zero,80(sp) - c40: c682 sw zero,76(sp) - -00000c42 <.LBB103>: - c42: 00fc add a5,sp,76 - c44: 0090 add a2,sp,64 - -00000c46 <.L211>: - c46: 47d8 lw a4,12(a5) - c48: 4794 lw a3,8(a5) - c4a: 17f1 add a5,a5,-4 - c4c: 070e sll a4,a4,0x3 - c4e: 82f5 srl a3,a3,0x1d - c50: 8f55 or a4,a4,a3 - c52: cb98 sw a4,16(a5) - c54: fef619e3 bne a2,a5,c46 <.L211> - c58: b481 j 698 <.L355> - -00000c5a <.L210>: - c5a: 4782 lw a5,0(sp) - c5c: c6a6 sw s1,76(sp) - c5e: c896 sw t0,80(sp) - c60: cabe sw a5,84(sp) - c62: 47a2 lw a5,8(sp) - c64: ccbe sw a5,88(sp) - -00000c66 <.LBB174>: - c66: 4792 lw a5,4(sp) - c68: c63e sw a5,12(sp) - -00000c6a <.L361>: - c6a: fff60413 add s0,a2,-1 - -00000c6e <.LVL390>: - c6e: b8f1 j 54a <.L11> - -00000c70 <.L209>: - c70: e591 bnez a1,c7c <.L212> - -00000c72 <.LVL392>: - c72: c6be sw a5,76(sp) - c74: c8b6 sw a3,80(sp) - c76: caba sw a4,84(sp) - c78: cc9e sw t2,88(sp) - c7a: bfc5 j c6a <.L361> - -00000c7c <.L212>: - c7c: ccb2 sw a2,88(sp) - c7e: ca82 sw zero,84(sp) - c80: c882 sw zero,80(sp) - c82: c682 sw zero,76(sp) - -00000c84 <.LBB104>: - c84: 00fc add a5,sp,76 - c86: 0090 add a2,sp,64 - -00000c88 <.L213>: - c88: 47d8 lw a4,12(a5) - c8a: 4794 lw a3,8(a5) - c8c: 17f1 add a5,a5,-4 - c8e: 070e sll a4,a4,0x3 - c90: 82f5 srl a3,a3,0x1d - c92: 8f55 or a4,a4,a3 - c94: cb98 sw a4,16(a5) - c96: fef619e3 bne a2,a5,c88 <.L213> - c9a: bafd j 698 <.L355> - -00000c9c <.L188>: - c9c: 40978633 sub a2,a5,s1 - -00000ca0 <.LVL397>: - ca0: 40568533 sub a0,a3,t0 - ca4: 00c7b333 sltu t1,a5,a2 - ca8: 00a6b5b3 sltu a1,a3,a0 - cac: 40650533 sub a0,a0,t1 - cb0: ca2a sw a0,20(sp) - -00000cb2 <.LVL398>: - cb2: 4502 lw a0,0(sp) - cb4: d22e sw a1,36(sp) - -00000cb6 <.LVL399>: - cb6: 40a70333 sub t1,a4,a0 - cba: 00a73533 sltu a0,a4,a0 - cbe: d42a sw a0,40(sp) - cc0: 00c7fa63 bgeu a5,a2,cd4 <.L218> - cc4: 00569863 bne a3,t0,cd4 <.L218> - -00000cc8 <.LVL400>: - cc8: fff30593 add a1,t1,-1 - -00000ccc <.L219>: - ccc: 00133513 seqz a0,t1 - cd0: d02a sw a0,32(sp) - cd2: a031 j cde <.L220> - -00000cd4 <.L218>: - cd4: 5512 lw a0,36(sp) - cd6: d002 sw zero,32(sp) - cd8: 40b305b3 sub a1,t1,a1 - -00000cdc <.LVL403>: - cdc: f965 bnez a0,ccc <.L219> - -00000cde <.L220>: - cde: 4522 lw a0,8(sp) - ce0: 5302 lw t1,32(sp) - ce2: caae sw a1,84(sp) - ce4: 40a38533 sub a0,t2,a0 - ce8: d22a sw a0,36(sp) - cea: 5522 lw a0,40(sp) - cec: c6b2 sw a2,76(sp) - cee: 00a36533 or a0,t1,a0 - -00000cf2 <.LVL405>: - cf2: 5312 lw t1,36(sp) - cf4: 40a30333 sub t1,t1,a0 - cf8: 4552 lw a0,20(sp) - -00000cfa <.LVL406>: - cfa: cc9a sw t1,88(sp) - cfc: c8aa sw a0,80(sp) - -00000cfe <.LBE105>: - cfe: 00080537 lui a0,0x80 - d02: 00a37533 and a0,t1,a0 - d06: 12050463 beqz a0,e2e <.L221> - -00000d0a <.LBB106>: - d0a: 40f487b3 sub a5,s1,a5 - -00000d0e <.LVL408>: - d0e: 40d28633 sub a2,t0,a3 - -00000d12 <.LVL409>: - d12: 00f4b5b3 sltu a1,s1,a5 - -00000d16 <.LVL410>: - d16: 00c2b333 sltu t1,t0,a2 - -00000d1a <.LVL411>: - d1a: 4502 lw a0,0(sp) - d1c: 8e0d sub a2,a2,a1 - -00000d1e <.LVL412>: - d1e: 4582 lw a1,0(sp) - d20: 809a mv ra,t1 - -00000d22 <.LVL413>: - d22: 00e53533 sltu a0,a0,a4 - d26: 8d99 sub a1,a1,a4 - d28: 00f4fb63 bgeu s1,a5,d3e <.L226> - d2c: 00569963 bne a3,t0,d3e <.L226> - -00000d30 <.LVL414>: - d30: 15fd add a1,a1,-1 - -00000d32 <.L227>: - d32: 4682 lw a3,0(sp) - d34: 8f15 sub a4,a4,a3 - d36: 00173713 seqz a4,a4 - d3a: ce3a sw a4,28(sp) - d3c: a029 j d46 <.L228> - -00000d3e <.L226>: - d3e: 401585b3 sub a1,a1,ra - -00000d42 <.LVL417>: - d42: fe0318e3 bnez t1,d32 <.L227> - -00000d46 <.L228>: - d46: 4722 lw a4,8(sp) - d48: 46f2 lw a3,28(sp) - d4a: c6be sw a5,76(sp) - -00000d4c <.LBE106>: - d4c: 4792 lw a5,4(sp) - -00000d4e <.LBB107>: - d4e: 40770733 sub a4,a4,t2 - d52: 8ec9 or a3,a3,a0 - -00000d54 <.LVL421>: - d54: 8f15 sub a4,a4,a3 - d56: ccba sw a4,88(sp) - d58: caae sw a1,84(sp) - -00000d5a <.LVL422>: - d5a: c8b2 sw a2,80(sp) - -00000d5c <.LBE107>: - d5c: c63e sw a5,12(sp) - -00000d5e <.L229>: - d5e: 4566 lw a0,88(sp) - d60: cd79 beqz a0,e3e <.L230> - d62: 00000097 auipc ra,0x0 - d66: 000080e7 jalr ra # d62 <.L229+0x4> - -00000d6a <.L231>: - d6a: 1551 add a0,a0,-12 # 7fff4 <.LLST157+0x7d5f6> - -00000d6c <.LBB66>: - d6c: 41f55793 sra a5,a0,0x1f - d70: 8bfd and a5,a5,31 - d72: 97aa add a5,a5,a0 - d74: 8795 sra a5,a5,0x5 - -00000d76 <.LVL427>: - d76: 01f57593 and a1,a0,31 - d7a: 40f00733 neg a4,a5 - d7e: c9f5 beqz a1,e72 <.L234> - d80: 800006b7 lui a3,0x80000 - d84: 06fd add a3,a3,31 # 8000001f <.LLST157+0x7fffd621> - d86: 8ee9 and a3,a3,a0 - d88: 0006d663 bgez a3,d94 <.L235> - d8c: 16fd add a3,a3,-1 - d8e: fe06e693 or a3,a3,-32 - d92: 0685 add a3,a3,1 - -00000d94 <.L235>: - d94: 070a sll a4,a4,0x2 - d96: 02000313 li t1,32 - d9a: 40d30333 sub t1,t1,a3 - d9e: 04c10393 add t2,sp,76 - da2: 00c70693 add a3,a4,12 - da6: 969e add a3,a3,t2 - da8: 40e00733 neg a4,a4 - -00000dac <.L236>: - dac: 0ed39163 bne t2,a3,e8e <.L239> - db0: fff78713 add a4,a5,-1 - -00000db4 <.LVL428>: - db4: 078a sll a5,a5,0x2 - -00000db6 <.LVL429>: - db6: 1074 add a3,sp,44 - db8: 04c78793 add a5,a5,76 - dbc: 97b6 add a5,a5,a3 - dbe: 46b6 lw a3,76(sp) - dc0: 00b696b3 sll a3,a3,a1 - dc4: fcd7aa23 sw a3,-44(a5) - -00000dc8 <.L240>: - dc8: 0705 add a4,a4,1 - dca: 00f4 add a3,sp,76 - dcc: 070a sll a4,a4,0x2 - dce: 4621 li a2,8 - dd0: 87b6 mv a5,a3 - dd2: 00c76863 bltu a4,a2,de2 <.L241> - dd6: 0006a023 sw zero,0(a3) - dda: 0006a223 sw zero,4(a3) - dde: 1761 add a4,a4,-8 - de0: 08d4 add a3,sp,84 - -00000de2 <.L241>: - de2: 4611 li a2,4 - de4: 00c76463 bltu a4,a2,dec <.L242> - de8: 0006a023 sw zero,0(a3) - -00000dec <.L242>: - dec: 14854f63 blt a0,s0,f4a <.L243> - df0: 8d01 sub a0,a0,s0 - -00000df2 <.LVL431>: - df2: 0505 add a0,a0,1 - -00000df4 <.LBB62>: - df4: 40555313 sra t1,a0,0x5 - -00000df8 <.LVL433>: - df8: 85be mv a1,a5 - dfa: 897d and a0,a0,31 - -00000dfc <.LVL434>: - dfc: 86be mv a3,a5 - dfe: 4601 li a2,0 - e00: 4701 li a4,0 - -00000e02 <.L244>: - e02: 0a671463 bne a4,t1,eaa <.L245> - e06: 470d li a4,3 - -00000e08 <.LVL436>: - e08: 40670733 sub a4,a4,t1 - e0c: 00231693 sll a3,t1,0x2 - e10: e545 bnez a0,eb8 <.L246> - -00000e12 <.L247>: - e12: 00d582b3 add t0,a1,a3 - e16: 0002a283 lw t0,0(t0) - e1a: 0505 add a0,a0,1 - -00000e1c <.LVL438>: - e1c: 0055a023 sw t0,0(a1) - -00000e20 <.LVL439>: - e20: 0591 add a1,a1,4 - e22: fea758e3 bge a4,a0,e12 <.L247> - e26: 4691 li a3,4 - e28: 406686b3 sub a3,a3,t1 - e2c: a0f1 j ef8 <.L251> - -00000e2e <.L221>: - e2e: 47d2 lw a5,20(sp) - e30: 8e5d or a2,a2,a5 - -00000e32 <.LVL441>: - e32: 8e4d or a2,a2,a1 - e34: 00666633 or a2,a2,t1 - e38: d20600e3 beqz a2,b58 <.L191> - e3c: b70d j d5e <.L229> - -00000e3e <.L230>: - e3e: 4556 lw a0,84(sp) - e40: c901 beqz a0,e50 <.L232> - e42: 00000097 auipc ra,0x0 - e46: 000080e7 jalr ra # e42 <.L230+0x4> - -00000e4a <.LVL443>: - e4a: 02050513 add a0,a0,32 - e4e: bf31 j d6a <.L231> - -00000e50 <.L232>: - e50: 4546 lw a0,80(sp) - e52: c901 beqz a0,e62 <.L233> - e54: 00000097 auipc ra,0x0 - e58: 000080e7 jalr ra # e54 <.L232+0x4> - -00000e5c <.LVL446>: - e5c: 04050513 add a0,a0,64 - e60: b729 j d6a <.L231> - -00000e62 <.L233>: - e62: 4536 lw a0,76(sp) - e64: 00000097 auipc ra,0x0 - e68: 000080e7 jalr ra # e64 <.L233+0x2> - -00000e6c <.LVL449>: - e6c: 06050513 add a0,a0,96 - e70: bded j d6a <.L231> - -00000e72 <.L234>: - e72: 08b4 add a3,sp,88 - e74: 070a sll a4,a4,0x2 - -00000e76 <.LBB68>: - e76: 460d li a2,3 - -00000e78 <.L237>: - e78: 00e685b3 add a1,a3,a4 - e7c: 418c lw a1,0(a1) - e7e: 167d add a2,a2,-1 - -00000e80 <.LVL453>: - e80: 16f1 add a3,a3,-4 - e82: c2cc sw a1,4(a3) - -00000e84 <.LVL454>: - e84: fef65ae3 bge a2,a5,e78 <.L237> - e88: fff78713 add a4,a5,-1 - e8c: bf35 j dc8 <.L240> - -00000e8e <.L239>: - e8e: 4290 lw a2,0(a3) - e90: ffc6a283 lw t0,-4(a3) - e94: 00e684b3 add s1,a3,a4 - e98: 00b61633 sll a2,a2,a1 - e9c: 0062d2b3 srl t0,t0,t1 - ea0: 00566633 or a2,a2,t0 - ea4: c090 sw a2,0(s1) - ea6: 16f1 add a3,a3,-4 - ea8: b711 j dac <.L236> - -00000eaa <.L245>: - eaa: 0006a283 lw t0,0(a3) - eae: 0705 add a4,a4,1 - -00000eb0 <.LVL457>: - eb0: 0691 add a3,a3,4 - eb2: 00566633 or a2,a2,t0 - -00000eb6 <.LVL458>: - eb6: b7b1 j e02 <.L244> - -00000eb8 <.L246>: - eb8: 04c68413 add s0,a3,76 - -00000ebc <.LVL460>: - ebc: 1064 add s1,sp,44 - ebe: 009402b3 add t0,s0,s1 - ec2: fd42a283 lw t0,-44(t0) - ec6: 02000393 li t2,32 - eca: 40a383b3 sub t2,t2,a0 - ece: 007292b3 sll t0,t0,t2 - ed2: 00566633 or a2,a2,t0 - -00000ed6 <.LVL461>: - ed6: 96be add a3,a3,a5 - ed8: 4401 li s0,0 - -00000eda <.L249>: - eda: 04e44963 blt s0,a4,f2c <.L250> - ede: 070a sll a4,a4,0x2 - ee0: 106c add a1,sp,44 - ee2: 04c70713 add a4,a4,76 - ee6: 972e add a4,a4,a1 - ee8: 45e6 lw a1,88(sp) - eea: 4691 li a3,4 - eec: 406686b3 sub a3,a3,t1 - -00000ef0 <.LVL463>: - ef0: 00a5d5b3 srl a1,a1,a0 - ef4: fcb72a23 sw a1,-44(a4) - -00000ef8 <.L251>: - ef8: 4711 li a4,4 - efa: 8f15 sub a4,a4,a3 - efc: 068a sll a3,a3,0x2 - efe: 97b6 add a5,a5,a3 - f00: 070a sll a4,a4,0x2 - f02: 46a1 li a3,8 - f04: 00d76863 bltu a4,a3,f14 <.L252> - f08: 0007a023 sw zero,0(a5) - f0c: 0007a223 sw zero,4(a5) - f10: 1761 add a4,a4,-8 - f12: 07a1 add a5,a5,8 - -00000f14 <.L252>: - f14: 4691 li a3,4 - f16: 00d76463 bltu a4,a3,f1e <.L253> - f1a: 0007a023 sw zero,0(a5) - -00000f1e <.L253>: - f1e: 47b6 lw a5,76(sp) - -00000f20 <.LBB64>: - f20: 00c03633 snez a2,a2 - -00000f24 <.LBE64>: - f24: 8fd1 or a5,a5,a2 - f26: c6be sw a5,76(sp) - f28: e08ff06f j 530 <.L357> - -00000f2c <.L250>: - f2c: 0006a283 lw t0,0(a3) - f30: 42c4 lw s1,4(a3) - f32: 0405 add s0,s0,1 - -00000f34 <.LVL468>: - f34: 00a2d2b3 srl t0,t0,a0 - f38: 007494b3 sll s1,s1,t2 - f3c: 0092e2b3 or t0,t0,s1 - f40: 0055a023 sw t0,0(a1) - -00000f44 <.LVL469>: - f44: 0691 add a3,a3,4 - f46: 0591 add a1,a1,4 - f48: bf49 j eda <.L249> - -00000f4a <.L243>: - f4a: 47e6 lw a5,88(sp) - f4c: fff80737 lui a4,0xfff80 - f50: 177d add a4,a4,-1 # fff7ffff <.LLST157+0xfff7d601> - f52: 8c09 sub s0,s0,a0 - f54: 8ff9 and a5,a5,a4 - f56: a7cff06f j 1d2 <.L363> - -00000f5a <.L260>: - f5a: cc82 sw zero,88(sp) - f5c: ca82 sw zero,84(sp) - f5e: c882 sw zero,80(sp) - f60: c682 sw zero,76(sp) - f62: e3aff06f j 59c <.L259> - -00000f66 <.L24>: - f66: 07400613 li a2,116 - f6a: a8d65063 bge a2,a3,1ea <.L264> - -00000f6e <.L26>: - f6e: c482 sw zero,72(sp) - f70: c282 sw zero,68(sp) - f72: c082 sw zero,64(sp) - f74: 4705 li a4,1 - f76: b2cff06f j 2a2 <.L37> - -00000f7a <.L62>: - f7a: 07400793 li a5,116 - f7e: c4d7d963 bge a5,a3,3d0 <.L265> - -00000f82 <.L64>: - f82: dc02 sw zero,56(sp) - f84: da02 sw zero,52(sp) - f86: d802 sw zero,48(sp) - f88: 4405 li s0,1 - -00000f8a <.LVL477>: - f8a: d16ff06f j 4a0 <.L77> - -00000f8e <.L165>: - f8e: 07400793 li a5,116 - f92: a2b7dfe3 bge a5,a1,9d0 <.L267> - -00000f96 <.L167>: - f96: dc02 sw zero,56(sp) - f98: da02 sw zero,52(sp) - f9a: d802 sw zero,48(sp) - f9c: 4705 li a4,1 - f9e: b619 j aa4 <.L180> - -unordtf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__unordtf2>: - 0: fdc10113 add sp,sp,-36 - 4: d022 sw s0,32(sp) - 6: 4118 lw a4,0(a0) - 8: 4140 lw s0,4(a0) - a: 00852383 lw t2,8(a0) - e: 4548 lw a0,12(a0) - 10: 45d4 lw a3,12(a1) - 12: 419c lw a5,0(a1) - 14: 0045a283 lw t0,4(a1) - 18: 0085a303 lw t1,8(a1) - -0000001c <.LBB2>: - 1c: 6621 lui a2,0x8 - -0000001e <.LBE2>: - 1e: 00f10593 add a1,sp,15 - 22: ce26 sw s1,28(sp) - 24: 99c1 and a1,a1,-16 - -00000026 <.LBB3>: - 26: 167d add a2,a2,-1 # 7fff <.LASF19+0x7e4a> - 28: 01055493 srl s1,a0,0x10 - -0000002c <.LBB4>: - 2c: c19c sw a5,0(a1) - 2e: 0055a223 sw t0,4(a1) - 32: 0065a423 sw t1,8(a1) - 36: c5d4 sw a3,12(a1) - -00000038 <.LBB5>: - 38: 8cf1 and s1,s1,a2 - -0000003a <.LBB6>: - 3a: 0106d593 srl a1,a3,0x10 - 3e: 8df1 and a1,a1,a2 - -00000040 <.LBE6>: - 40: 00c49a63 bne s1,a2,54 <.L2> - 44: 8f41 or a4,a4,s0 - -00000046 <.LBB7>: - 46: 0542 sll a0,a0,0x10 - 48: 8141 srl a0,a0,0x10 - -0000004a <.LBE7>: - 4a: 00776733 or a4,a4,t2 - 4e: 8f49 or a4,a4,a0 - 50: 4505 li a0,1 - 52: ef19 bnez a4,70 <.L1> - -00000054 <.L2>: - 54: 6721 lui a4,0x8 - 56: 177d add a4,a4,-1 # 7fff <.LASF19+0x7e4a> - 58: 4501 li a0,0 - 5a: 00e59b63 bne a1,a4,70 <.L1> - 5e: 0057e533 or a0,a5,t0 - -00000062 <.LBB8>: - 62: 06c2 sll a3,a3,0x10 - -00000064 <.LBE8>: - 64: 00656533 or a0,a0,t1 - -00000068 <.LBB9>: - 68: 82c1 srl a3,a3,0x10 - -0000006a <.LBE9>: - 6a: 8d55 or a0,a0,a3 - 6c: 00a03533 snez a0,a0 - -00000070 <.L1>: - 70: 5402 lw s0,32(sp) - 72: 44f2 lw s1,28(sp) - -00000074 <.LVL6>: - 74: 02410113 add sp,sp,36 - -00000078 <.LVL7>: - 78: 8082 ret - -fixtfsi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixtfsi>: - 0: 4114 lw a3,0(a0) - 2: 4150 lw a2,4(a0) - 4: 450c lw a1,8(a0) - 6: fd410113 add sp,sp,-44 - a: 4558 lw a4,12(a0) - c: 01f10793 add a5,sp,31 - 10: 9bc1 and a5,a5,-16 - -00000012 <.LBB3>: - 12: c3d0 sw a2,4(a5) - 14: c394 sw a3,0(a5) - 16: c78c sw a1,8(a5) - 18: c7d8 sw a4,12(a5) - 1a: 00171513 sll a0,a4,0x1 - -0000001e <.LBE3>: - 1e: 6791 lui a5,0x4 - -00000020 <.LBB4>: - 20: c036 sw a3,0(sp) - 22: c42e sw a1,8(sp) - 24: 8145 srl a0,a0,0x11 - -00000026 <.LBE4>: - 26: ffe78613 add a2,a5,-2 # 3ffe <.LLST11+0x3da5> - 2a: 08a65163 bge a2,a0,ac <.L8> - 2e: 01d78613 add a2,a5,29 - 32: 01f75693 srl a3,a4,0x1f - 36: 00a65a63 bge a2,a0,4a <.L3> - -0000003a <.LVL2>: - 3a: 80000537 lui a0,0x80000 - -0000003e <.LVL3>: - 3e: fff54513 not a0,a0 - 42: 9536 add a0,a0,a3 - -00000044 <.L2>: - 44: 02c10113 add sp,sp,44 - -00000048 <.LVL5>: - 48: 8082 ret - -0000004a <.L3>: - 4a: 0742 sll a4,a4,0x10 - -0000004c <.LVL7>: - 4c: 8341 srl a4,a4,0x10 - -0000004e <.LBB11>: - 4e: 6641 lui a2,0x10 - -00000050 <.LBB6>: - 50: 06f78793 add a5,a5,111 - 54: 8f89 sub a5,a5,a0 - -00000056 <.LBE6>: - 56: 8e59 or a2,a2,a4 - -00000058 <.LBB7>: - 58: 02000513 li a0,32 - -0000005c <.LVL8>: - 5c: 4057d713 sra a4,a5,0x5 - -00000060 <.LBE7>: - 60: c632 sw a2,12(sp) - -00000062 <.LBB8>: - 62: 8bfd and a5,a5,31 - -00000064 <.LVL10>: - 64: 8d1d sub a0,a0,a5 - -00000066 <.LVL11>: - 66: ef95 bnez a5,a2 <.L4> - -00000068 <.LVL12>: - 68: 070a sll a4,a4,0x2 - -0000006a <.LVL13>: - 6a: 02c70793 add a5,a4,44 - -0000006e <.LVL14>: - 6e: 00278733 add a4,a5,sp - 72: fd472783 lw a5,-44(a4) - 76: c03e sw a5,0(sp) - -00000078 <.L5>: - 78: 4502 lw a0,0(sp) - -0000007a <.LVL16>: - 7a: d6e9 beqz a3,44 <.L2> - 7c: 40a00533 neg a0,a0 - 80: b7d1 j 44 <.L2> - -00000082 <.L7>: - 82: 00f5d5b3 srl a1,a1,a5 - 86: 00a61533 sll a0,a2,a0 - -0000008a <.LVL19>: - 8a: 8dc9 or a1,a1,a0 - 8c: c02e sw a1,0(sp) - -0000008e <.LVL20>: - 8e: 4705 li a4,1 - -00000090 <.L6>: - 90: 070a sll a4,a4,0x2 - -00000092 <.LVL22>: - 92: 02c70713 add a4,a4,44 - 96: 970a add a4,a4,sp - 98: 00f65633 srl a2,a2,a5 - 9c: fcc72a23 sw a2,-44(a4) - a0: bfe1 j 78 <.L5> - -000000a2 <.L4>: - a2: 4309 li t1,2 - a4: fc670fe3 beq a4,t1,82 <.L7> - a8: 4701 li a4,0 - -000000aa <.LVL24>: - aa: b7dd j 90 <.L6> - -000000ac <.L8>: - ac: 4501 li a0,0 - -000000ae <.LVL26>: - ae: bf59 j 44 <.L2> - -fixunstfsi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixunstfsi>: - 0: 4114 lw a3,0(a0) - 2: 414c lw a1,4(a0) - 4: 4510 lw a2,8(a0) - 6: 4558 lw a4,12(a0) - 8: fd410113 add sp,sp,-44 - c: 01f10793 add a5,sp,31 - 10: 9bc1 and a5,a5,-16 - -00000012 <.LBB3>: - 12: c3cc sw a1,4(a5) - 14: c394 sw a3,0(a5) - 16: c790 sw a2,8(a5) - 18: c7d8 sw a4,12(a5) - 1a: 00171593 sll a1,a4,0x1 - -0000001e <.LBE3>: - 1e: 6791 lui a5,0x4 - -00000020 <.LBB4>: - 20: c036 sw a3,0(sp) - 22: c432 sw a2,8(sp) - 24: 81c5 srl a1,a1,0x11 - -00000026 <.LBE4>: - 26: ffe78513 add a0,a5,-2 # 3ffe <.LASF19+0x3dea> - 2a: 06b55b63 bge a0,a1,a0 <.L7> - 2e: 01f75693 srl a3,a4,0x1f - 32: 4501 li a0,0 - 34: ee95 bnez a3,70 <.L1> - 36: 01e78693 add a3,a5,30 - 3a: 557d li a0,-1 - 3c: 02b6ca63 blt a3,a1,70 <.L1> - -00000040 <.LBB10>: - 40: 0742 sll a4,a4,0x10 - -00000042 <.LVL3>: - 42: 8341 srl a4,a4,0x10 - -00000044 <.LBB11>: - 44: 66c1 lui a3,0x10 - -00000046 <.LBB6>: - 46: 06f78793 add a5,a5,111 - 4a: 8f8d sub a5,a5,a1 - -0000004c <.LBE6>: - 4c: 8ed9 or a3,a3,a4 - -0000004e <.LBB7>: - 4e: 02000593 li a1,32 - -00000052 <.LVL4>: - 52: 4057d713 sra a4,a5,0x5 - -00000056 <.LBE7>: - 56: c636 sw a3,12(sp) - -00000058 <.LBB8>: - 58: 8bfd and a5,a5,31 - -0000005a <.LVL6>: - 5a: 8d9d sub a1,a1,a5 - -0000005c <.LVL7>: - 5c: ef8d bnez a5,96 <.L3> - -0000005e <.LVL8>: - 5e: 070a sll a4,a4,0x2 - -00000060 <.LVL9>: - 60: 02c70793 add a5,a4,44 - -00000064 <.LVL10>: - 64: 00278733 add a4,a5,sp - 68: fd472783 lw a5,-44(a4) - 6c: c03e sw a5,0(sp) - -0000006e <.L4>: - 6e: 4502 lw a0,0(sp) - -00000070 <.L1>: - 70: 02c10113 add sp,sp,44 - -00000074 <.LVL13>: - 74: 8082 ret - -00000076 <.L6>: - 76: 00f65633 srl a2,a2,a5 - 7a: 00b695b3 sll a1,a3,a1 - -0000007e <.LVL15>: - 7e: 8e4d or a2,a2,a1 - 80: c032 sw a2,0(sp) - -00000082 <.LVL16>: - 82: 4705 li a4,1 - -00000084 <.L5>: - 84: 070a sll a4,a4,0x2 - -00000086 <.LVL18>: - 86: 02c70713 add a4,a4,44 - 8a: 970a add a4,a4,sp - 8c: 00f6d6b3 srl a3,a3,a5 - 90: fcd72a23 sw a3,-44(a4) - 94: bfe9 j 6e <.L4> - -00000096 <.L3>: - 96: 4509 li a0,2 - 98: fca70fe3 beq a4,a0,76 <.L6> - 9c: 4701 li a4,0 - -0000009e <.LVL20>: - 9e: b7dd j 84 <.L5> - -000000a0 <.L7>: - a0: 4501 li a0,0 - a2: b7f9 j 70 <.L1> - -floatsitf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatsitf>: - 0: 7139 add sp,sp,-64 - 2: da26 sw s1,52(sp) - 4: 02710693 add a3,sp,39 - 8: de06 sw ra,60(sp) - a: dc22 sw s0,56(sp) - c: 84aa mv s1,a0 - e: 9ac1 and a3,a3,-16 - -00000010 <.LBB13>: - 10: c5f9 beqz a1,de <.L2> - -00000012 <.LBB3>: - 12: 41f5d793 sra a5,a1,0x1f - 16: 00b7c433 xor s0,a5,a1 - 1a: 8c1d sub s0,s0,a5 - 1c: 01f5d313 srl t1,a1,0x1f - -00000020 <.LBB4>: - 20: 8522 mv a0,s0 - 22: c236 sw a3,4(sp) - -00000024 <.LBE4>: - 24: c01a sw t1,0(sp) - -00000026 <.LBB5>: - 26: 00000097 auipc ra,0x0 - 2a: 000080e7 jalr ra # 26 <.LBB5> - -0000002e <.LBE5>: - 2e: 05150793 add a5,a0,81 - -00000032 <.LBB6>: - 32: 6611 lui a2,0x4 - 34: 0679 add a2,a2,30 # 401e <.LASF30+0x3d46> - -00000036 <.LBB7>: - 36: 4057d713 sra a4,a5,0x5 - -0000003a <.LBE7>: - 3a: c422 sw s0,8(sp) - 3c: c602 sw zero,12(sp) - 3e: c802 sw zero,16(sp) - 40: ca02 sw zero,20(sp) - -00000042 <.LBB8>: - 42: 8bfd and a5,a5,31 - 44: 4302 lw t1,0(sp) - 46: 4692 lw a3,4(sp) - -00000048 <.LBB9>: - 48: 8e09 sub a2,a2,a0 - -0000004a <.LBB10>: - 4a: c795 beqz a5,76 <.L4> - -0000004c <.LVL6>: - 4c: 4589 li a1,2 - 4e: 08b71663 bne a4,a1,da <.L9> - 52: 02000593 li a1,32 - 56: 8d9d sub a1,a1,a5 - -00000058 <.LVL7>: - 58: 00b455b3 srl a1,s0,a1 - -0000005c <.LVL8>: - 5c: ca2e sw a1,20(sp) - -0000005e <.L5>: - 5e: fff70593 add a1,a4,-1 - -00000062 <.LVL10>: - 62: 070a sll a4,a4,0x2 - 64: 02c70713 add a4,a4,44 - 68: 0028 add a0,sp,8 - -0000006a <.LVL11>: - 6a: 972a add a4,a4,a0 - 6c: 00f41433 sll s0,s0,a5 - -00000070 <.LVL12>: - 70: fc872a23 sw s0,-44(a4) - 74: a00d j 96 <.L6> - -00000076 <.L4>: - 76: 478d li a5,3 - -00000078 <.LVL14>: - 78: 8f99 sub a5,a5,a4 - 7a: 078a sll a5,a5,0x2 - 7c: 002c add a1,sp,8 - 7e: 02c78793 add a5,a5,44 - 82: 97ae add a5,a5,a1 - 84: fd47a783 lw a5,-44(a5) - 88: 4589 li a1,2 - 8a: ca3e sw a5,20(sp) - -0000008c <.LVL15>: - 8c: 4789 li a5,2 - 8e: 00f71463 bne a4,a5,96 <.L6> - 92: c822 sw s0,16(sp) - -00000094 <.LVL16>: - 94: 4585 li a1,1 - -00000096 <.L6>: - 96: 058a sll a1,a1,0x2 - 98: c402 sw zero,8(sp) - -0000009a <.LVL18>: - 9a: c602 sw zero,12(sp) - 9c: 15f1 add a1,a1,-4 - 9e: 4791 li a5,4 - a0: 00f5e363 bltu a1,a5,a6 <.L7> - a4: c802 sw zero,16(sp) - -000000a6 <.L7>: - a6: 859a mv a1,t1 - -000000a8 <.L8>: - a8: 4352 lw t1,20(sp) - aa: 4522 lw a0,8(sp) - ac: 4732 lw a4,12(sp) - ae: 47c2 lw a5,16(sp) - b0: 00f59413 sll s0,a1,0xf - b4: 8c51 or s0,s0,a2 - b6: 00869723 sh s0,14(a3) - ba: 00669623 sh t1,12(a3) - be: c288 sw a0,0(a3) - c0: c2d8 sw a4,4(a3) - c2: c69c sw a5,8(a3) - c4: 46d4 lw a3,12(a3) - -000000c6 <.LBE14>: - c6: 50f2 lw ra,60(sp) - c8: 5462 lw s0,56(sp) - ca: c088 sw a0,0(s1) - cc: c0d8 sw a4,4(s1) - ce: c49c sw a5,8(s1) - d0: c4d4 sw a3,12(s1) - d2: 8526 mv a0,s1 - -000000d4 <.LVL21>: - d4: 54d2 lw s1,52(sp) - d6: 6121 add sp,sp,64 - -000000d8 <.LVL23>: - d8: 8082 ret - -000000da <.L9>: - da: 470d li a4,3 - -000000dc <.LVL25>: - dc: b749 j 5e <.L5> - -000000de <.L2>: - de: ca02 sw zero,20(sp) - e0: c802 sw zero,16(sp) - e2: c602 sw zero,12(sp) - e4: c402 sw zero,8(sp) - e6: 4601 li a2,0 - e8: b7c1 j a8 <.L8> - -floatunsitf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatunsitf>: - 0: fc410113 add sp,sp,-60 - 4: d826 sw s1,48(sp) - 6: dc06 sw ra,56(sp) - 8: 02310493 add s1,sp,35 - c: da22 sw s0,52(sp) - e: 86aa mv a3,a0 - 10: 98c1 and s1,s1,-16 - -00000012 <.LBB12>: - 12: cdc5 beqz a1,ca <.L2> - 14: c02a sw a0,0(sp) - -00000016 <.LBB3>: - 16: 852e mv a0,a1 - 18: 842e mv s0,a1 - 1a: 00000097 auipc ra,0x0 - 1e: 000080e7 jalr ra # 1a <.LBB3+0x4> - -00000022 <.LBE4>: - 22: 05150793 add a5,a0,81 - -00000026 <.LBB5>: - 26: 6591 lui a1,0x4 - 28: 05f9 add a1,a1,30 # 401e <.LASF29+0x3d4b> - -0000002a <.LBB6>: - 2a: 4057d713 sra a4,a5,0x5 - -0000002e <.LBE6>: - 2e: c222 sw s0,4(sp) - 30: c402 sw zero,8(sp) - 32: c602 sw zero,12(sp) - 34: c802 sw zero,16(sp) - -00000036 <.LBB7>: - 36: 8bfd and a5,a5,31 - 38: 4682 lw a3,0(sp) - -0000003a <.LBB8>: - 3a: 8d89 sub a1,a1,a0 - -0000003c <.LBB9>: - 3c: c795 beqz a5,68 <.L3> - -0000003e <.LVL5>: - 3e: 4609 li a2,2 - 40: 08c71363 bne a4,a2,c6 <.L8> - 44: 02000613 li a2,32 - 48: 8e1d sub a2,a2,a5 - -0000004a <.LVL6>: - 4a: 00c45633 srl a2,s0,a2 - -0000004e <.LVL7>: - 4e: c832 sw a2,16(sp) - -00000050 <.L4>: - 50: fff70613 add a2,a4,-1 - -00000054 <.LVL9>: - 54: 070a sll a4,a4,0x2 - 56: 02c70713 add a4,a4,44 - 5a: 0048 add a0,sp,4 - -0000005c <.LVL10>: - 5c: 972a add a4,a4,a0 - 5e: 00f41433 sll s0,s0,a5 - -00000062 <.LVL11>: - 62: fc872a23 sw s0,-44(a4) - 66: a00d j 88 <.L5> - -00000068 <.L3>: - 68: 478d li a5,3 - -0000006a <.LVL13>: - 6a: 8f99 sub a5,a5,a4 - 6c: 078a sll a5,a5,0x2 - 6e: 0050 add a2,sp,4 - 70: 02c78793 add a5,a5,44 - 74: 97b2 add a5,a5,a2 - 76: fd47a783 lw a5,-44(a5) - 7a: 4609 li a2,2 - 7c: c83e sw a5,16(sp) - -0000007e <.LVL14>: - 7e: 4789 li a5,2 - 80: 00f71463 bne a4,a5,88 <.L5> - 84: c622 sw s0,12(sp) - -00000086 <.LVL15>: - 86: 4605 li a2,1 - -00000088 <.L5>: - 88: 060a sll a2,a2,0x2 - 8a: c202 sw zero,4(sp) - -0000008c <.LVL17>: - 8c: c402 sw zero,8(sp) - 8e: 1671 add a2,a2,-4 - 90: 4791 li a5,4 - 92: 00f66363 bltu a2,a5,98 <.L7> - 96: c602 sw zero,12(sp) - -00000098 <.L7>: - 98: 4542 lw a0,16(sp) - 9a: 00b49723 sh a1,14(s1) - 9e: 4612 lw a2,4(sp) - a0: 00a49623 sh a0,12(s1) - a4: 4722 lw a4,8(sp) - a6: 47b2 lw a5,12(sp) - a8: 44cc lw a1,12(s1) - -000000aa <.LBE13>: - aa: 50e2 lw ra,56(sp) - ac: 5452 lw s0,52(sp) - -000000ae <.LBB14>: - ae: c090 sw a2,0(s1) - b0: c0d8 sw a4,4(s1) - b2: c49c sw a5,8(s1) - -000000b4 <.LBE14>: - b4: c290 sw a2,0(a3) - b6: c2d8 sw a4,4(a3) - b8: c69c sw a5,8(a3) - ba: c6cc sw a1,12(a3) - bc: 54c2 lw s1,48(sp) - be: 8536 mv a0,a3 - c0: 03c10113 add sp,sp,60 - c4: 8082 ret - -000000c6 <.L8>: - c6: 470d li a4,3 - -000000c8 <.LVL22>: - c8: b761 j 50 <.L4> - -000000ca <.L2>: - ca: c802 sw zero,16(sp) - cc: c602 sw zero,12(sp) - ce: c402 sw zero,8(sp) - d0: c202 sw zero,4(sp) - d2: 4581 li a1,0 - -000000d4 <.LVL24>: - d4: b7d1 j 98 <.L7> - -fixtfdi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixtfdi>: - 0: fcc10113 add sp,sp,-52 - 4: 4154 lw a3,4(a0) - 6: 4518 lw a4,8(a0) - 8: 4110 lw a2,0(a0) - a: 454c lw a1,12(a0) - c: 01f10793 add a5,sp,31 - 10: 9bc1 and a5,a5,-16 - 12: d822 sw s0,48(sp) - 14: d626 sw s1,44(sp) - -00000016 <.LBB3>: - 16: c3d4 sw a3,4(a5) - 18: c798 sw a4,8(a5) - 1a: c390 sw a2,0(a5) - 1c: c7cc sw a1,12(a5) - 1e: c43a sw a4,8(sp) - -00000020 <.LBE3>: - 20: 6791 lui a5,0x4 - -00000022 <.LBB4>: - 22: 00159713 sll a4,a1,0x1 - 26: c236 sw a3,4(sp) - 28: c032 sw a2,0(sp) - 2a: 8345 srl a4,a4,0x11 - -0000002c <.LBE4>: - 2c: ffe78693 add a3,a5,-2 # 3ffe <.LLST11+0x3d85> - 30: 0ee6db63 bge a3,a4,126 <.L11> - 34: 03d78693 add a3,a5,61 - 38: 01f5d613 srl a2,a1,0x1f - 3c: 02e6d363 bge a3,a4,62 <.L3> - -00000040 <.LVL2>: - 40: 4505 li a0,1 - 42: 8d11 sub a0,a0,a2 - 44: 41f55713 sra a4,a0,0x1f - -00000048 <.LVL3>: - 48: 800005b7 lui a1,0x80000 - -0000004c <.LVL4>: - 4c: 00a037b3 snez a5,a0 - 50: 8d99 sub a1,a1,a4 - 52: 40a00533 neg a0,a0 - 56: 8d9d sub a1,a1,a5 - -00000058 <.L2>: - 58: 5442 lw s0,48(sp) - 5a: 54b2 lw s1,44(sp) - 5c: 03410113 add sp,sp,52 - -00000060 <.LVL6>: - 60: 8082 ret - -00000062 <.L3>: - 62: 05c2 sll a1,a1,0x10 - -00000064 <.LBB11>: - 64: 66c1 lui a3,0x10 - -00000066 <.LBB12>: - 66: 81c1 srl a1,a1,0x10 - -00000068 <.LBB13>: - 68: 06f78793 add a5,a5,111 - -0000006c <.LBE6>: - 6c: 8dd5 or a1,a1,a3 - -0000006e <.LBB7>: - 6e: 8f99 sub a5,a5,a4 - 70: 4057d713 sra a4,a5,0x5 - -00000074 <.LVL9>: - 74: 468d li a3,3 - -00000076 <.LBE7>: - 76: c62e sw a1,12(sp) - -00000078 <.LBB8>: - 78: 8bfd and a5,a5,31 - -0000007a <.LVL11>: - 7a: 8e99 sub a3,a3,a4 - 7c: 00271513 sll a0,a4,0x2 - 80: c795 beqz a5,ac <.L4> - 82: 02000393 li t2,32 - 86: 40f383b3 sub t2,t2,a5 - -0000008a <.LVL12>: - 8a: 950a add a0,a0,sp - 8c: 840a mv s0,sp - 8e: 4281 li t0,0 - -00000090 <.L5>: - 90: 06d2cc63 blt t0,a3,108 <.L8> - 94: 068a sll a3,a3,0x2 - 96: 02c68693 add a3,a3,44 # 1002c <.LLST11+0xfdb3> - 9a: 4511 li a0,4 - 9c: 968a add a3,a3,sp - 9e: 00f5d5b3 srl a1,a1,a5 - a2: 40e50733 sub a4,a0,a4 - -000000a6 <.LVL14>: - a6: fcb6aa23 sw a1,-44(a3) - aa: a839 j c8 <.L7> - -000000ac <.L4>: - ac: 858a mv a1,sp - -000000ae <.L6>: - ae: 00a58333 add t1,a1,a0 - b2: 00032303 lw t1,0(t1) - b6: 0785 add a5,a5,1 - -000000b8 <.LVL17>: - b8: 0065a023 sw t1,0(a1) # 80000000 <.LLST11+0x7ffffd87> - -000000bc <.LVL18>: - bc: 0591 add a1,a1,4 - be: fef6d8e3 bge a3,a5,ae <.L6> - c2: 4791 li a5,4 - -000000c4 <.LVL19>: - c4: 40e78733 sub a4,a5,a4 - -000000c8 <.L7>: - c8: 4691 li a3,4 - ca: 8e99 sub a3,a3,a4 - cc: 070a sll a4,a4,0x2 - ce: 00e107b3 add a5,sp,a4 - d2: 00269713 sll a4,a3,0x2 - d6: 46a1 li a3,8 - d8: 00d76863 bltu a4,a3,e8 <.L9> - dc: 0007a023 sw zero,0(a5) - e0: 0007a223 sw zero,4(a5) - e4: 1761 add a4,a4,-8 - e6: 07a1 add a5,a5,8 - -000000e8 <.L9>: - e8: 4691 li a3,4 - ea: 00d76463 bltu a4,a3,f2 <.L10> - ee: 0007a023 sw zero,0(a5) - -000000f2 <.L10>: - f2: 4502 lw a0,0(sp) - f4: 4592 lw a1,4(sp) - -000000f6 <.LVL22>: - f6: d22d beqz a2,58 <.L2> - f8: 00a037b3 snez a5,a0 - fc: 40b005b3 neg a1,a1 - 100: 8d9d sub a1,a1,a5 - 102: 40a00533 neg a0,a0 - -00000106 <.LVL23>: - 106: bf89 j 58 <.L2> - -00000108 <.L8>: - 108: 00052303 lw t1,0(a0) - 10c: 4144 lw s1,4(a0) - 10e: 0285 add t0,t0,1 - -00000110 <.LVL25>: - 110: 00f35333 srl t1,t1,a5 - 114: 007494b3 sll s1,s1,t2 - 118: 00936333 or t1,t1,s1 - 11c: 00642023 sw t1,0(s0) - -00000120 <.LVL26>: - 120: 0511 add a0,a0,4 - 122: 0411 add s0,s0,4 - 124: b7b5 j 90 <.L5> - -00000126 <.L11>: - 126: 4501 li a0,0 - 128: 4581 li a1,0 - -0000012a <.LVL28>: - 12a: b73d j 58 <.L2> - -fixunstfdi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixunstfdi>: - 0: 7179 add sp,sp,-48 - 2: 410c lw a1,0(a0) - 4: 4514 lw a3,8(a0) - 6: 4150 lw a2,4(a0) - 8: 4558 lw a4,12(a0) - a: 01f10793 add a5,sp,31 - e: 9bc1 and a5,a5,-16 - 10: d622 sw s0,44(sp) - -00000012 <.LBB3>: - 12: c38c sw a1,0(a5) - 14: c794 sw a3,8(a5) - 16: c3d0 sw a2,4(a5) - 18: c7d8 sw a4,12(a5) - 1a: c436 sw a3,8(sp) - -0000001c <.LBE3>: - 1c: 6791 lui a5,0x4 - -0000001e <.LBB4>: - 1e: 00171693 sll a3,a4,0x1 - 22: c02e sw a1,0(sp) - 24: c232 sw a2,4(sp) - 26: 82c5 srl a3,a3,0x11 - -00000028 <.LBE4>: - 28: ffe78593 add a1,a5,-2 # 3ffe <.LASF19+0x3dea> - 2c: 0cd5d263 bge a1,a3,f0 <.L11> - 30: 01f75613 srl a2,a4,0x1f - 34: ee55 bnez a2,f0 <.L11> - 36: 03e78613 add a2,a5,62 - 3a: 0ad64e63 blt a2,a3,f6 <.L12> - -0000003e <.LBB10>: - 3e: 0742 sll a4,a4,0x10 - -00000040 <.LVL3>: - 40: 8341 srl a4,a4,0x10 - -00000042 <.LBB11>: - 42: 6641 lui a2,0x10 - -00000044 <.LBB6>: - 44: 06f78793 add a5,a5,111 - -00000048 <.LBE6>: - 48: 00c765b3 or a1,a4,a2 - -0000004c <.LBB7>: - 4c: 8f95 sub a5,a5,a3 - 4e: 4057d713 sra a4,a5,0x5 - 52: 468d li a3,3 - -00000054 <.LBE7>: - 54: c62e sw a1,12(sp) - -00000056 <.LBB8>: - 56: 8bfd and a5,a5,31 - -00000058 <.LVL6>: - 58: 8e99 sub a3,a3,a4 - 5a: 00271613 sll a2,a4,0x2 - 5e: c795 beqz a5,8a <.L3> - 60: 02000293 li t0,32 - 64: 40f282b3 sub t0,t0,a5 - -00000068 <.LVL7>: - 68: 960a add a2,a2,sp - 6a: 838a mv t2,sp - 6c: 4301 li t1,0 - -0000006e <.L4>: - 6e: 06d34463 blt t1,a3,d6 <.L7> - 72: 068a sll a3,a3,0x2 - 74: 02c68693 add a3,a3,44 - 78: 4611 li a2,4 - 7a: 968a add a3,a3,sp - 7c: 00f5d5b3 srl a1,a1,a5 - 80: 40e60733 sub a4,a2,a4 - -00000084 <.LVL9>: - 84: fcb6aa23 sw a1,-44(a3) - 88: a829 j a2 <.L6> - -0000008a <.L3>: - 8a: 858a mv a1,sp - -0000008c <.L5>: - 8c: 00c58533 add a0,a1,a2 - 90: 4108 lw a0,0(a0) - 92: 0785 add a5,a5,1 - -00000094 <.LVL12>: - 94: c188 sw a0,0(a1) - -00000096 <.LVL13>: - 96: 0591 add a1,a1,4 - 98: fef6dae3 bge a3,a5,8c <.L5> - 9c: 4791 li a5,4 - -0000009e <.LVL14>: - 9e: 40e78733 sub a4,a5,a4 - -000000a2 <.L6>: - a2: 4691 li a3,4 - a4: 8e99 sub a3,a3,a4 - a6: 070a sll a4,a4,0x2 - a8: 00e107b3 add a5,sp,a4 - ac: 00269713 sll a4,a3,0x2 - b0: 46a1 li a3,8 - b2: 00d76863 bltu a4,a3,c2 <.L8> - b6: 0007a023 sw zero,0(a5) - ba: 0007a223 sw zero,4(a5) - be: 1761 add a4,a4,-8 - c0: 07a1 add a5,a5,8 - -000000c2 <.L8>: - c2: 4691 li a3,4 - c4: 00d76463 bltu a4,a3,cc <.L9> - c8: 0007a023 sw zero,0(a5) - -000000cc <.L9>: - cc: 4502 lw a0,0(sp) - ce: 4592 lw a1,4(sp) - -000000d0 <.L1>: - d0: 5432 lw s0,44(sp) - d2: 6145 add sp,sp,48 - -000000d4 <.LVL18>: - d4: 8082 ret - -000000d6 <.L7>: - d6: 4208 lw a0,0(a2) - d8: 4240 lw s0,4(a2) - da: 0305 add t1,t1,1 - -000000dc <.LVL20>: - dc: 00f55533 srl a0,a0,a5 - e0: 00541433 sll s0,s0,t0 - e4: 8d41 or a0,a0,s0 - e6: 00a3a023 sw a0,0(t2) - -000000ea <.LVL21>: - ea: 0611 add a2,a2,4 # 10004 <.LASF19+0xfdf0> - ec: 0391 add t2,t2,4 - ee: b741 j 6e <.L4> - -000000f0 <.L11>: - f0: 4501 li a0,0 - f2: 4581 li a1,0 - f4: bff1 j d0 <.L1> - -000000f6 <.L12>: - f6: 557d li a0,-1 - f8: 55fd li a1,-1 - -000000fa <.LVL23>: - fa: bfd9 j d0 <.L1> - -floatditf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatditf>: - 0: fbc10113 add sp,sp,-68 - 4: 02b10693 add a3,sp,43 - 8: c086 sw ra,64(sp) - a: de22 sw s0,60(sp) - c: dc26 sw s1,56(sp) - e: c02a sw a0,0(sp) - -00000010 <.LBB11>: - 10: 00c5e7b3 or a5,a1,a2 - -00000014 <.LBE11>: - 14: 9ac1 and a3,a3,-16 - -00000016 <.LBB12>: - 16: 12078d63 beqz a5,150 <.L2> - 1a: 84ae mv s1,a1 - -0000001c <.LBB3>: - 1c: 01f65413 srl s0,a2,0x1f - -00000020 <.LVL2>: - 20: 00065963 bgez a2,32 <.L4> - 24: 00b037b3 snez a5,a1 - 28: 40c00633 neg a2,a2 - -0000002c <.LVL3>: - 2c: 8e1d sub a2,a2,a5 - 2e: 40b004b3 neg s1,a1 - -00000032 <.L4>: - 32: c635 beqz a2,9e <.L6> - 34: 8532 mv a0,a2 - 36: c436 sw a3,8(sp) - 38: c232 sw a2,4(sp) - 3a: 00000097 auipc ra,0x0 - 3e: 000080e7 jalr ra # 3a <.L4+0x8> - -00000042 <.LVL7>: - 42: 4612 lw a2,4(sp) - 44: 46a2 lw a3,8(sp) - -00000046 <.L7>: - 46: 6591 lui a1,0x4 - 48: 03e58593 add a1,a1,62 # 403e <.LASF30+0x3d66> - 4c: 8d89 sub a1,a1,a0 - -0000004e <.LBE4>: - 4e: 03150513 add a0,a0,49 - -00000052 <.LVL10>: - 52: c832 sw a2,16(sp) - -00000054 <.LBB5>: - 54: 40555713 sra a4,a0,0x5 - -00000058 <.LBE5>: - 58: c626 sw s1,12(sp) - 5a: ca02 sw zero,20(sp) - 5c: cc02 sw zero,24(sp) - -0000005e <.LBB6>: - 5e: 01f57793 and a5,a0,31 - -00000062 <.LVL12>: - 62: 40e00633 neg a2,a4 - -00000066 <.LVL13>: - 66: cba1 beqz a5,b6 <.L8> - 68: 02000513 li a0,32 - -0000006c <.LVL14>: - 6c: 8d1d sub a0,a0,a5 - -0000006e <.LVL15>: - 6e: c22a sw a0,4(sp) - 70: 00261513 sll a0,a2,0x2 - -00000074 <.LVL16>: - 74: 00c10393 add t2,sp,12 - 78: 00c50613 add a2,a0,12 - 7c: 961e add a2,a2,t2 - 7e: 40a00333 neg t1,a0 - -00000082 <.L9>: - 82: 0ac39563 bne t2,a2,12c <.L12> - 86: fff70613 add a2,a4,-1 - -0000008a <.LVL18>: - 8a: 070a sll a4,a4,0x2 - -0000008c <.LVL19>: - 8c: 02c70713 add a4,a4,44 - 90: 0068 add a0,sp,12 - 92: 972a add a4,a4,a0 - 94: 00f494b3 sll s1,s1,a5 - 98: fc972a23 sw s1,-44(a4) - 9c: a825 j d4 <.L11> - -0000009e <.L6>: - 9e: 8526 mv a0,s1 - a0: c432 sw a2,8(sp) - a2: c236 sw a3,4(sp) - a4: 00000097 auipc ra,0x0 - a8: 000080e7 jalr ra # a4 <.L6+0x6> - -000000ac <.LVL22>: - ac: 4622 lw a2,8(sp) - ae: 4692 lw a3,4(sp) - b0: 02050513 add a0,a0,32 - b4: bf49 j 46 <.L7> - -000000b6 <.L8>: - b6: 083c add a5,sp,24 - -000000b8 <.LVL25>: - b8: 060a sll a2,a2,0x2 - -000000ba <.LBB8>: - ba: 450d li a0,3 - -000000bc <.L10>: - bc: 00c782b3 add t0,a5,a2 - c0: 0002a283 lw t0,0(t0) - c4: 157d add a0,a0,-1 - -000000c6 <.LVL27>: - c6: 17f1 add a5,a5,-4 - c8: 0057a223 sw t0,4(a5) - -000000cc <.LVL28>: - cc: fee558e3 bge a0,a4,bc <.L10> - d0: fff70613 add a2,a4,-1 - -000000d4 <.L11>: - d4: 00160793 add a5,a2,1 - d8: 078a sll a5,a5,0x2 - da: 4621 li a2,8 - dc: 0078 add a4,sp,12 - de: 00c7e863 bltu a5,a2,ee <.L13> - e2: 00072023 sw zero,0(a4) - e6: 00072223 sw zero,4(a4) - ea: 17e1 add a5,a5,-8 - ec: 0858 add a4,sp,20 - -000000ee <.L13>: - ee: 4611 li a2,4 - f0: 00c7e463 bltu a5,a2,f8 <.L15> - f4: 00072023 sw zero,0(a4) - -000000f8 <.L15>: - f8: 4562 lw a0,24(sp) - fa: 4632 lw a2,12(sp) - fc: 4742 lw a4,16(sp) - fe: 47d2 lw a5,20(sp) - 100: 043e sll s0,s0,0xf - -00000102 <.LVL31>: - 102: 8c4d or s0,s0,a1 - 104: 00a69623 sh a0,12(a3) - 108: 00869723 sh s0,14(a3) - -0000010c <.LBE13>: - 10c: 4582 lw a1,0(sp) - -0000010e <.LBB14>: - 10e: c290 sw a2,0(a3) - 110: c2d8 sw a4,4(a3) - 112: c69c sw a5,8(a3) - 114: 46d4 lw a3,12(a3) - -00000116 <.LBE14>: - 116: 4086 lw ra,64(sp) - 118: 5472 lw s0,60(sp) - 11a: c190 sw a2,0(a1) - 11c: c1d8 sw a4,4(a1) - 11e: c59c sw a5,8(a1) - 120: c5d4 sw a3,12(a1) - 122: 54e2 lw s1,56(sp) - 124: 852e mv a0,a1 - 126: 04410113 add sp,sp,68 - 12a: 8082 ret - -0000012c <.L12>: - 12c: 4208 lw a0,0(a2) - 12e: ffc62283 lw t0,-4(a2) - 132: 00f51533 sll a0,a0,a5 - 136: c42a sw a0,8(sp) - 138: 4512 lw a0,4(sp) - 13a: 00a2d2b3 srl t0,t0,a0 - 13e: 4522 lw a0,8(sp) - 140: 00556533 or a0,a0,t0 - 144: 006602b3 add t0,a2,t1 - 148: 00a2a023 sw a0,0(t0) - 14c: 1671 add a2,a2,-4 - 14e: bf15 j 82 <.L9> - -00000150 <.L2>: - 150: cc02 sw zero,24(sp) - 152: ca02 sw zero,20(sp) - 154: c802 sw zero,16(sp) - 156: c602 sw zero,12(sp) - 158: 4581 li a1,0 - -0000015a <.LVL37>: - 15a: 4401 li s0,0 - 15c: bf71 j f8 <.L15> - -floatunditf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatunditf>: - 0: fbc10113 add sp,sp,-68 - 4: de22 sw s0,60(sp) - 6: c086 sw ra,64(sp) - 8: 02b10413 add s0,sp,43 - c: dc26 sw s1,56(sp) - e: c02a sw a0,0(sp) - -00000010 <.LBB11>: - 10: 00c5e7b3 or a5,a1,a2 - -00000014 <.LBE11>: - 14: 9841 and s0,s0,-16 - -00000016 <.LBB12>: - 16: 10078863 beqz a5,126 <.L2> - 1a: 84ae mv s1,a1 - -0000001c <.LBB3>: - 1c: c625 beqz a2,84 <.L4> - 1e: 8532 mv a0,a2 - 20: c232 sw a2,4(sp) - 22: 00000097 auipc ra,0x0 - 26: 000080e7 jalr ra # 22 <.LBB3+0x6> - -0000002a <.L16>: - 2a: 4612 lw a2,4(sp) - -0000002c <.LVL4>: - 2c: 6591 lui a1,0x4 - 2e: 03e58593 add a1,a1,62 # 403e <.LASF29+0x3d6b> - 32: 8d89 sub a1,a1,a0 - -00000034 <.LBE4>: - 34: 03150513 add a0,a0,49 - -00000038 <.LBB5>: - 38: 40555713 sra a4,a0,0x5 - -0000003c <.LBE5>: - 3c: c626 sw s1,12(sp) - 3e: c832 sw a2,16(sp) - 40: ca02 sw zero,20(sp) - 42: cc02 sw zero,24(sp) - -00000044 <.LBB6>: - 44: 01f57793 and a5,a0,31 - -00000048 <.LVL8>: - 48: 40e006b3 neg a3,a4 - 4c: c7a9 beqz a5,96 <.L6> - 4e: 02000613 li a2,32 - 52: 8e1d sub a2,a2,a5 - -00000054 <.LVL9>: - 54: c232 sw a2,4(sp) - -00000056 <.LVL10>: - 56: 00269613 sll a2,a3,0x2 - -0000005a <.LVL11>: - 5a: 00c10293 add t0,sp,12 - 5e: 00c60693 add a3,a2,12 - 62: 9696 add a3,a3,t0 - 64: 40c00333 neg t1,a2 - -00000068 <.L7>: - 68: 08d29e63 bne t0,a3,104 <.L10> - 6c: fff70693 add a3,a4,-1 - -00000070 <.LVL13>: - 70: 070a sll a4,a4,0x2 - -00000072 <.LVL14>: - 72: 02c70713 add a4,a4,44 - 76: 0070 add a2,sp,12 - 78: 9732 add a4,a4,a2 - 7a: 00f494b3 sll s1,s1,a5 - 7e: fc972a23 sw s1,-44(a4) - 82: a03d j b0 <.L9> - -00000084 <.L4>: - 84: 852e mv a0,a1 - 86: c232 sw a2,4(sp) - 88: 00000097 auipc ra,0x0 - 8c: 000080e7 jalr ra # 88 <.L4+0x4> - -00000090 <.LVL17>: - 90: 02050513 add a0,a0,32 - -00000094 <.LVL18>: - 94: bf59 j 2a <.L16> - -00000096 <.L6>: - 96: 083c add a5,sp,24 - -00000098 <.LVL20>: - 98: 068a sll a3,a3,0x2 - -0000009a <.LBB8>: - 9a: 460d li a2,3 - -0000009c <.L8>: - 9c: 00d78533 add a0,a5,a3 - a0: 4108 lw a0,0(a0) - a2: 167d add a2,a2,-1 - -000000a4 <.LVL22>: - a4: 17f1 add a5,a5,-4 - a6: c3c8 sw a0,4(a5) - -000000a8 <.LVL23>: - a8: fee65ae3 bge a2,a4,9c <.L8> - ac: fff70693 add a3,a4,-1 - -000000b0 <.L9>: - b0: 00168793 add a5,a3,1 - b4: 078a sll a5,a5,0x2 - b6: 46a1 li a3,8 - b8: 0078 add a4,sp,12 - ba: 00d7e863 bltu a5,a3,ca <.L11> - be: 00072023 sw zero,0(a4) - c2: 00072223 sw zero,4(a4) - c6: 17e1 add a5,a5,-8 - c8: 0858 add a4,sp,20 - -000000ca <.L11>: - ca: 4691 li a3,4 - cc: 00d7e463 bltu a5,a3,d4 <.L13> - d0: 00072023 sw zero,0(a4) - -000000d4 <.L13>: - d4: 4662 lw a2,24(sp) - d6: 46b2 lw a3,12(sp) - d8: 4742 lw a4,16(sp) - da: 47d2 lw a5,20(sp) - dc: 00b41723 sh a1,14(s0) - e0: 00c41623 sh a2,12(s0) - -000000e4 <.LBE13>: - e4: 4582 lw a1,0(sp) - -000000e6 <.LBB14>: - e6: 4450 lw a2,12(s0) - -000000e8 <.LBE14>: - e8: 4086 lw ra,64(sp) - -000000ea <.LBB15>: - ea: c014 sw a3,0(s0) - ec: c058 sw a4,4(s0) - ee: c41c sw a5,8(s0) - -000000f0 <.LBE15>: - f0: 5472 lw s0,60(sp) - f2: c194 sw a3,0(a1) - f4: c1d8 sw a4,4(a1) - f6: c59c sw a5,8(a1) - f8: c5d0 sw a2,12(a1) - fa: 54e2 lw s1,56(sp) - fc: 852e mv a0,a1 - fe: 04410113 add sp,sp,68 - 102: 8082 ret - -00000104 <.L10>: - 104: 4290 lw a2,0(a3) - 106: ffc6a503 lw a0,-4(a3) - 10a: 006683b3 add t2,a3,t1 - 10e: 00f61633 sll a2,a2,a5 - 112: c432 sw a2,8(sp) - 114: 4612 lw a2,4(sp) - 116: 16f1 add a3,a3,-4 - 118: 00c55533 srl a0,a0,a2 - 11c: 4622 lw a2,8(sp) - 11e: 8e49 or a2,a2,a0 - 120: 00c3a023 sw a2,0(t2) - 124: b791 j 68 <.L7> - -00000126 <.L2>: - 126: cc02 sw zero,24(sp) - 128: ca02 sw zero,20(sp) - 12a: c802 sw zero,16(sp) - 12c: c602 sw zero,12(sp) - 12e: 4581 li a1,0 - -00000130 <.LVL31>: - 130: b755 j d4 <.L13> - -addsf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__addsf3>: - 0: 00800737 lui a4,0x800 - -00000004 <.LBE2>: - 4: 1141 add sp,sp,-16 - -00000006 <.LBB3>: - 6: 177d add a4,a4,-1 # 7fffff <.LLST20+0x7ff6b8> - 8: 00a777b3 and a5,a4,a0 - -0000000c <.LBE3>: - c: c422 sw s0,8(sp) - -0000000e <.LBB4>: - e: 01f55693 srl a3,a0,0x1f - 12: 01755413 srl s0,a0,0x17 - -00000016 <.LBB5>: - 16: 0175d513 srl a0,a1,0x17 - -0000001a <.LVL2>: - 1a: 8f6d and a4,a4,a1 - -0000001c <.LBB6>: - 1c: 0ff47413 zext.b s0,s0 - -00000020 <.LBB7>: - 20: 0ff57513 zext.b a0,a0 - -00000024 <.LBE7>: - 24: c606 sw ra,12(sp) - 26: c226 sw s1,4(sp) - -00000028 <.LBB8>: - 28: 81fd srl a1,a1,0x1f - -0000002a <.LBE8>: - 2a: 078e sll a5,a5,0x3 - -0000002c <.LBB9>: - 2c: 070e sll a4,a4,0x3 - -0000002e <.LBB10>: - 2e: 40a40633 sub a2,s0,a0 - -00000032 <.LBE10>: - 32: 16b69c63 bne a3,a1,1aa <.L2> - -00000036 <.LBB11>: - 36: 0cc05a63 blez a2,10a <.L3> - -0000003a <.LVL8>: - 3a: e50d bnez a0,64 <.L4> - 3c: 16070563 beqz a4,1a6 <.L53> - 40: fff60593 add a1,a2,-1 - -00000044 <.LVL9>: - 44: e989 bnez a1,56 <.L6> - -00000046 <.L94>: - 46: 97ba add a5,a5,a4 - -00000048 <.LVL11>: - 48: 04000737 lui a4,0x4000 - -0000004c <.LVL12>: - 4c: 8f7d and a4,a4,a5 - 4e: 4409 li s0,2 - -00000050 <.LVL13>: - 50: e745 bnez a4,f8 <.L7> - -00000052 <.L91>: - 52: 4405 li s0,1 - 54: a025 j 7c <.L38> - -00000056 <.L6>: - 56: 0ff00513 li a0,255 - -0000005a <.LVL16>: - 5a: 00a61d63 bne a2,a0,74 <.L8> - -0000005e <.L63>: - 5e: 0ff00413 li s0,255 - -00000062 <.LVL18>: - 62: a829 j 7c <.L38> - -00000064 <.L4>: - 64: 0ff00593 li a1,255 - -00000068 <.LVL20>: - 68: 00b40a63 beq s0,a1,7c <.L38> - 6c: 040005b7 lui a1,0x4000 - 70: 8f4d or a4,a4,a1 - 72: 85b2 mv a1,a2 - -00000074 <.L8>: - 74: 466d li a2,27 - 76: 04b65c63 bge a2,a1,ce <.L9> - -0000007a <.LVL23>: - 7a: 0785 add a5,a5,1 - -0000007c <.L38>: - 7c: 0077f713 and a4,a5,7 - 80: c719 beqz a4,8e <.L39> - 82: 00f7f713 and a4,a5,15 - 86: 4611 li a2,4 - 88: 00c70363 beq a4,a2,8e <.L39> - 8c: 0791 add a5,a5,4 - -0000008e <.L39>: - 8e: 04000737 lui a4,0x4000 - 92: 8f7d and a4,a4,a5 - 94: 28070063 beqz a4,314 <.L40> - -00000098 <.LVL26>: - 98: 0405 add s0,s0,1 - -0000009a <.LVL27>: - 9a: 0ff00713 li a4,255 - 9e: 4481 li s1,0 - a0: 00e40863 beq s0,a4,b0 <.L18> - a4: 0037d493 srl s1,a5,0x3 - a8: 1f8007b7 lui a5,0x1f800 - -000000ac <.LVL28>: - ac: 17fd add a5,a5,-1 # 1f7fffff <.LLST20+0x1f7ff6b8> - ae: 8cfd and s1,s1,a5 - -000000b0 <.L18>: - b0: 045e sll s0,s0,0x17 - b2: 7f8007b7 lui a5,0x7f800 - b6: 04a6 sll s1,s1,0x9 - -000000b8 <.LVL30>: - b8: 80a5 srl s1,s1,0x9 - ba: 8c7d and s0,s0,a5 - bc: 8c45 or s0,s0,s1 - be: 01f69513 sll a0,a3,0x1f - -000000c2 <.LBE19>: - c2: 40b2 lw ra,12(sp) - c4: 8d41 or a0,a0,s0 - -000000c6 <.LVL32>: - c6: 4422 lw s0,8(sp) - c8: 4492 lw s1,4(sp) - ca: 0141 add sp,sp,16 - cc: 8082 ret - -000000ce <.L9>: - ce: 02000613 li a2,32 - d2: 8e0d sub a2,a2,a1 - d4: 00b75533 srl a0,a4,a1 - d8: 00c71733 sll a4,a4,a2 - -000000dc <.LVL34>: - dc: 00e03733 snez a4,a4 - -000000e0 <.LVL35>: - e0: 8f49 or a4,a4,a0 - -000000e2 <.LVL36>: - e2: 97ba add a5,a5,a4 - -000000e4 <.L10>: - e4: 04000737 lui a4,0x4000 - -000000e8 <.LVL38>: - e8: 8f7d and a4,a4,a5 - ea: db49 beqz a4,7c <.L38> - -000000ec <.LVL39>: - ec: 0405 add s0,s0,1 - -000000ee <.LVL40>: - ee: 0ff00713 li a4,255 - -000000f2 <.LBB21>: - f2: 4481 li s1,0 - -000000f4 <.LBB22>: - f4: fae40ee3 beq s0,a4,b0 <.L18> - -000000f8 <.L7>: - f8: 7e000737 lui a4,0x7e000 - fc: 0017f613 and a2,a5,1 - 100: 177d add a4,a4,-1 # 7dffffff <.LLST20+0x7dfff6b8> - 102: 8385 srl a5,a5,0x1 - 104: 8ff9 and a5,a5,a4 - 106: 8fd1 or a5,a5,a2 - 108: bf95 j 7c <.L38> - -0000010a <.L3>: - 10a: ce21 beqz a2,162 <.L11> - 10c: 40850633 sub a2,a0,s0 - -00000110 <.LVL43>: - 110: ec01 bnez s0,128 <.L12> - 112: 1e078963 beqz a5,304 <.L44> - 116: fff60593 add a1,a2,-1 - -0000011a <.LVL44>: - 11a: d595 beqz a1,46 <.L94> - 11c: 0ff00313 li t1,255 - 120: 00661c63 bne a2,t1,138 <.L14> - -00000124 <.L49>: - 124: 87ba mv a5,a4 - -00000126 <.LVL46>: - 126: bf25 j 5e <.L63> - -00000128 <.L12>: - 128: 0ff00593 li a1,255 - -0000012c <.LVL48>: - 12c: feb50ce3 beq a0,a1,124 <.L49> - 130: 040005b7 lui a1,0x4000 - 134: 8fcd or a5,a5,a1 - 136: 85b2 mv a1,a2 - -00000138 <.L14>: - 138: 466d li a2,27 - 13a: 00b65663 bge a2,a1,146 <.L15> - -0000013e <.LVL51>: - 13e: 00170793 add a5,a4,1 - -00000142 <.LBB24>: - 142: 842a mv s0,a0 - -00000144 <.LVL53>: - 144: bf25 j 7c <.L38> - -00000146 <.L15>: - 146: 02000613 li a2,32 - 14a: 8e0d sub a2,a2,a1 - 14c: 00b7d333 srl t1,a5,a1 - 150: 00c797b3 sll a5,a5,a2 - -00000154 <.LVL55>: - 154: 00f037b3 snez a5,a5 - -00000158 <.LVL56>: - 158: 00f367b3 or a5,t1,a5 - -0000015c <.LVL57>: - 15c: 97ba add a5,a5,a4 - -0000015e <.LBB26>: - 15e: 842a mv s0,a0 - -00000160 <.LBB27>: - 160: b751 j e4 <.L10> - -00000162 <.L11>: - 162: 00140613 add a2,s0,1 - -00000166 <.LVL61>: - 166: 0fe67593 and a1,a2,254 - -0000016a <.LVL62>: - 16a: e985 bnez a1,19a <.L16> - 16c: ec11 bnez s0,188 <.L17> - -0000016e <.LVL63>: - 16e: 18078d63 beqz a5,308 <.L48> - 172: d709 beqz a4,7c <.L38> - 174: 97ba add a5,a5,a4 - -00000176 <.LVL64>: - 176: 04000737 lui a4,0x4000 - -0000017a <.LVL65>: - 17a: 8f7d and a4,a4,a5 - 17c: d301 beqz a4,7c <.L38> - 17e: fc000737 lui a4,0xfc000 - 182: 177d add a4,a4,-1 # fbffffff <.LLST20+0xfbfff6b8> - 184: 8ff9 and a5,a5,a4 - -00000186 <.LVL66>: - 186: b5f1 j 52 <.L91> - -00000188 <.L17>: - 188: dfd1 beqz a5,124 <.L49> - -0000018a <.L34>: - 18a: ec070ae3 beqz a4,5e <.L63> - -0000018e <.L62>: - 18e: 4681 li a3,0 - -00000190 <.LBB30>: - 190: 0ff00413 li s0,255 - -00000194 <.LBB31>: - 194: 004004b7 lui s1,0x400 - 198: bf21 j b0 <.L18> - -0000019a <.L16>: - 19a: 0ff00593 li a1,255 - 19e: 18b60663 beq a2,a1,32a <.L51> - 1a2: 97ba add a5,a5,a4 - -000001a4 <.LVL72>: - 1a4: 8385 srl a5,a5,0x1 - -000001a6 <.L53>: - 1a6: 8432 mv s0,a2 - -000001a8 <.LVL74>: - 1a8: bdd1 j 7c <.L38> - -000001aa <.L2>: - 1aa: 06c05063 blez a2,20a <.L19> - -000001ae <.LVL76>: - 1ae: e529 bnez a0,1f8 <.L20> - 1b0: db7d beqz a4,1a6 <.L53> - 1b2: fff60593 add a1,a2,-1 - -000001b6 <.LVL77>: - 1b6: e581 bnez a1,1be <.L21> - 1b8: 8f99 sub a5,a5,a4 - -000001ba <.L88>: - 1ba: 4405 li s0,1 - -000001bc <.LBB36>: - 1bc: a02d j 1e6 <.L22> - -000001be <.L21>: - 1be: 0ff00513 li a0,255 - -000001c2 <.LVL81>: - 1c2: e8a60ee3 beq a2,a0,5e <.L63> - -000001c6 <.L23>: - 1c6: 456d li a0,27 - 1c8: 4605 li a2,1 - 1ca: 00b54d63 blt a0,a1,1e4 <.L24> - 1ce: 02000613 li a2,32 - 1d2: 8e0d sub a2,a2,a1 - 1d4: 00b75533 srl a0,a4,a1 - 1d8: 00c71733 sll a4,a4,a2 - -000001dc <.LVL83>: - 1dc: 00e03733 snez a4,a4 - 1e0: 00e56633 or a2,a0,a4 - -000001e4 <.L24>: - 1e4: 8f91 sub a5,a5,a2 - -000001e6 <.L22>: - 1e6: 040004b7 lui s1,0x4000 - 1ea: 0097f733 and a4,a5,s1 - 1ee: e80707e3 beqz a4,7c <.L38> - -000001f2 <.LBB13>: - 1f2: 14fd add s1,s1,-1 # 3ffffff <.LLST20+0x3fff6b8> - 1f4: 8cfd and s1,s1,a5 - -000001f6 <.LVL86>: - 1f6: a0e1 j 2be <.L36> - -000001f8 <.L20>: - 1f8: 0ff00593 li a1,255 - -000001fc <.LVL88>: - 1fc: e8b400e3 beq s0,a1,7c <.L38> - 200: 040005b7 lui a1,0x4000 - 204: 8f4d or a4,a4,a1 - 206: 85b2 mv a1,a2 - 208: bf7d j 1c6 <.L23> - -0000020a <.L19>: - 20a: c225 beqz a2,26a <.L25> - 20c: 408506b3 sub a3,a0,s0 - -00000210 <.LVL91>: - 210: e00d bnez s0,232 <.L26> - 212: cfed beqz a5,30c <.L56> - 214: fff68613 add a2,a3,-1 - -00000218 <.LVL92>: - 218: e609 bnez a2,222 <.L27> - 21a: 40f707b3 sub a5,a4,a5 - -0000021e <.LVL93>: - 21e: 86ae mv a3,a1 - 220: bf69 j 1ba <.L88> - -00000222 <.L27>: - 222: 0ff00313 li t1,255 - 226: 00669e63 bne a3,t1,242 <.L28> - -0000022a <.L58>: - 22a: 87ba mv a5,a4 - -0000022c <.LBB37>: - 22c: 0ff00413 li s0,255 - -00000230 <.LVL97>: - 230: a0c5 j 310 <.L90> - -00000232 <.L26>: - 232: 0ff00613 li a2,255 - 236: fec50ae3 beq a0,a2,22a <.L58> - 23a: 04000637 lui a2,0x4000 - 23e: 8fd1 or a5,a5,a2 - 240: 8636 mv a2,a3 - -00000242 <.L28>: - 242: 436d li t1,27 - 244: 4685 li a3,1 - 246: 00c34d63 blt t1,a2,260 <.L29> - 24a: 02000693 li a3,32 - 24e: 8e91 sub a3,a3,a2 - 250: 00c7d333 srl t1,a5,a2 - 254: 00d797b3 sll a5,a5,a3 - -00000258 <.LVL101>: - 258: 00f037b3 snez a5,a5 - 25c: 00f366b3 or a3,t1,a5 - -00000260 <.L29>: - 260: 40d707b3 sub a5,a4,a3 - -00000264 <.LBB38>: - 264: 842a mv s0,a0 - -00000266 <.LBB39>: - 266: 86ae mv a3,a1 - -00000268 <.LVL105>: - 268: bfbd j 1e6 <.L22> - -0000026a <.L25>: - 26a: 00140613 add a2,s0,1 - 26e: 0fe67613 and a2,a2,254 - 272: ee0d bnez a2,2ac <.L30> - 274: e40d bnez s0,29e <.L31> - -00000276 <.LVL107>: - 276: e789 bnez a5,280 <.L32> - -00000278 <.LVL108>: - 278: 87ba mv a5,a4 - -0000027a <.LVL109>: - 27a: eb59 bnez a4,310 <.L90> - -0000027c <.LBB40>: - 27c: 4481 li s1,0 - 27e: a831 j 29a <.L92> - -00000280 <.L32>: - 280: de070ee3 beqz a4,7c <.L38> - 284: 40e784b3 sub s1,a5,a4 - -00000288 <.LVL111>: - 288: 04000637 lui a2,0x4000 - 28c: 8e65 and a2,a2,s1 - 28e: 40f707b3 sub a5,a4,a5 - -00000292 <.LVL112>: - 292: ee3d bnez a2,310 <.L90> - 294: 87a6 mv a5,s1 - 296: de0493e3 bnez s1,7c <.L38> - -0000029a <.L92>: - 29a: 4681 li a3,0 - 29c: bd11 j b0 <.L18> - -0000029e <.L31>: - 29e: ee0796e3 bnez a5,18a <.L34> - 2a2: ee0706e3 beqz a4,18e <.L62> - 2a6: 87ba mv a5,a4 - -000002a8 <.LVL115>: - 2a8: 86ae mv a3,a1 - -000002aa <.LVL116>: - 2aa: bb55 j 5e <.L63> - -000002ac <.L30>: - 2ac: 40e784b3 sub s1,a5,a4 - -000002b0 <.LVL118>: - 2b0: 04000637 lui a2,0x4000 - 2b4: 8e65 and a2,a2,s1 - 2b6: ce15 beqz a2,2f2 <.L35> - 2b8: 40f704b3 sub s1,a4,a5 - -000002bc <.LVL119>: - 2bc: 86ae mv a3,a1 - -000002be <.L36>: - 2be: 8526 mv a0,s1 - 2c0: c036 sw a3,0(sp) - -000002c2 <.LVL121>: - 2c2: 00000097 auipc ra,0x0 - 2c6: 000080e7 jalr ra # 2c2 <.LVL121> - -000002ca <.LVL122>: - 2ca: 156d add a0,a0,-5 - 2cc: 4682 lw a3,0(sp) - 2ce: 00a494b3 sll s1,s1,a0 - 2d2: 02854363 blt a0,s0,2f8 <.L37> - 2d6: 8d01 sub a0,a0,s0 - -000002d8 <.LVL125>: - 2d8: 0505 add a0,a0,1 - -000002da <.LVL126>: - 2da: 02000713 li a4,32 - 2de: 8f09 sub a4,a4,a0 - 2e0: 00a4d7b3 srl a5,s1,a0 - 2e4: 00e494b3 sll s1,s1,a4 - -000002e8 <.LVL127>: - 2e8: 009034b3 snez s1,s1 - 2ec: 8fc5 or a5,a5,s1 - -000002ee <.LVL128>: - 2ee: 4401 li s0,0 - 2f0: b371 j 7c <.L38> - -000002f2 <.L35>: - 2f2: f4f1 bnez s1,2be <.L36> - 2f4: 4401 li s0,0 - -000002f6 <.LVL130>: - 2f6: b755 j 29a <.L92> - -000002f8 <.L37>: - 2f8: fc0007b7 lui a5,0xfc000 - 2fc: 17fd add a5,a5,-1 # fbffffff <.LLST20+0xfbfff6b8> - 2fe: 8c09 sub s0,s0,a0 - 300: 8fe5 and a5,a5,s1 - -00000302 <.LVL133>: - 302: bbad j 7c <.L38> - -00000304 <.L44>: - 304: 87ba mv a5,a4 - -00000306 <.LVL135>: - 306: b545 j 1a6 <.L53> - -00000308 <.L48>: - 308: 87ba mv a5,a4 - -0000030a <.LVL137>: - 30a: bb8d j 7c <.L38> - -0000030c <.L56>: - 30c: 87ba mv a5,a4 - -0000030e <.LBB42>: - 30e: 8436 mv s0,a3 - -00000310 <.L90>: - 310: 86ae mv a3,a1 - 312: b3ad j 7c <.L38> - -00000314 <.L40>: - 314: 0037d493 srl s1,a5,0x3 - -00000318 <.LVL142>: - 318: 0ff00793 li a5,255 - 31c: d8f41ae3 bne s0,a5,b0 <.L18> - 320: d80488e3 beqz s1,b0 <.L18> - 324: 004004b7 lui s1,0x400 - -00000328 <.LVL143>: - 328: bf8d j 29a <.L92> - -0000032a <.L51>: - 32a: 0ff00413 li s0,255 - -0000032e <.LBB46>: - 32e: 4481 li s1,0 - 330: b341 j b0 <.L18> - -divsf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divsf3>: - 0: fd810113 add sp,sp,-40 - 4: 01755693 srl a3,a0,0x17 - 8: ce26 sw s1,28(sp) - -0000000a <.LBB3>: - a: 00951793 sll a5,a0,0x9 - -0000000e <.LBE3>: - e: d206 sw ra,36(sp) - 10: d022 sw s0,32(sp) - 12: 0ff6f693 zext.b a3,a3 - -00000016 <.LBB4>: - 16: 83a5 srl a5,a5,0x9 - -00000018 <.LVL1>: - 18: 01f55493 srl s1,a0,0x1f - -0000001c <.LBE4>: - 1c: c2b5 beqz a3,80 <.L2> - 1e: 0ff00713 li a4,255 - 22: 08e68263 beq a3,a4,a6 <.L3> - -00000026 <.LVL3>: - 26: 078e sll a5,a5,0x3 - -00000028 <.LVL4>: - 28: 04000737 lui a4,0x4000 - 2c: 8fd9 or a5,a5,a4 - -0000002e <.LVL5>: - 2e: f8168693 add a3,a3,-127 - -00000032 <.LVL6>: - 32: 4301 li t1,0 - -00000034 <.L4>: - 34: 0175d613 srl a2,a1,0x17 - 38: 00959413 sll s0,a1,0x9 - 3c: 0ff67613 zext.b a2,a2 - 40: 8025 srl s0,s0,0x9 - -00000042 <.LVL8>: - 42: 81fd srl a1,a1,0x1f - -00000044 <.LBE5>: - 44: ca35 beqz a2,b8 <.L5> - 46: 0ff00713 li a4,255 - 4a: 08e60e63 beq a2,a4,e6 <.L6> - -0000004e <.LVL10>: - 4e: 040e sll s0,s0,0x3 - -00000050 <.LVL11>: - 50: 04000737 lui a4,0x4000 - 54: 8c59 or s0,s0,a4 - -00000056 <.LVL12>: - 56: f8160613 add a2,a2,-127 - -0000005a <.LVL13>: - 5a: 4501 li a0,0 - -0000005c <.L7>: - 5c: 8e91 sub a3,a3,a2 - -0000005e <.LVL15>: - 5e: 00231613 sll a2,t1,0x2 - -00000062 <.LVL16>: - 62: 8e49 or a2,a2,a0 - 64: 167d add a2,a2,-1 - 66: 42b9 li t0,14 - 68: 00b4c733 xor a4,s1,a1 - -0000006c <.LVL17>: - 6c: 0ac2e563 bltu t0,a2,116 <.L8> - 70: 000002b7 lui t0,0x0 - 74: 060a sll a2,a2,0x2 - 76: 00028293 mv t0,t0 - 7a: 9616 add a2,a2,t0 - 7c: 4210 lw a2,0(a2) - 7e: 8602 jr a2 - -00000080 <.L2>: - 80: cb8d beqz a5,b2 <.L30> - -00000082 <.LBB6>: - 82: 853e mv a0,a5 - -00000084 <.LVL19>: - 84: c22e sw a1,4(sp) - -00000086 <.LBB7>: - 86: c03e sw a5,0(sp) - 88: 00000097 auipc ra,0x0 - 8c: 000080e7 jalr ra # 88 <.LBB7+0x2> - -00000090 <.LVL20>: - 90: 4782 lw a5,0(sp) - 92: ffb50713 add a4,a0,-5 - 96: f8a00693 li a3,-118 - 9a: 4592 lw a1,4(sp) - 9c: 00e797b3 sll a5,a5,a4 - -000000a0 <.LVL21>: - a0: 8e89 sub a3,a3,a0 - -000000a2 <.LVL22>: - a2: 4301 li t1,0 - a4: bf41 j 34 <.L4> - -000000a6 <.L3>: - a6: 0ff00693 li a3,255 - -000000aa <.LBE8>: - aa: 430d li t1,3 - ac: f7c1 bnez a5,34 <.L4> - ae: 4309 li t1,2 - b0: b751 j 34 <.L4> - -000000b2 <.L30>: - b2: 4681 li a3,0 - -000000b4 <.LBE9>: - b4: 4305 li t1,1 - b6: bfbd j 34 <.L4> - -000000b8 <.L5>: - b8: cc0d beqz s0,f2 <.L32> - -000000ba <.LBB10>: - ba: 8522 mv a0,s0 - bc: c63e sw a5,12(sp) - be: c436 sw a3,8(sp) - c0: c21a sw t1,4(sp) - c2: c02e sw a1,0(sp) - -000000c4 <.LBB11>: - c4: 00000097 auipc ra,0x0 - c8: 000080e7 jalr ra # c4 <.LBB11> - -000000cc <.LVL28>: - cc: ffb50713 add a4,a0,-5 - d0: f8a00613 li a2,-118 - d4: 8e09 sub a2,a2,a0 - d6: 4582 lw a1,0(sp) - d8: 4312 lw t1,4(sp) - da: 46a2 lw a3,8(sp) - dc: 47b2 lw a5,12(sp) - de: 00e41433 sll s0,s0,a4 - -000000e2 <.LVL29>: - e2: 4501 li a0,0 - -000000e4 <.LVL30>: - e4: bfa5 j 5c <.L7> - -000000e6 <.L6>: - e6: 0ff00613 li a2,255 - -000000ea <.LBE12>: - ea: 450d li a0,3 - ec: f825 bnez s0,5c <.L7> - ee: 4509 li a0,2 - f0: b7b5 j 5c <.L7> - -000000f2 <.L32>: - f2: 4601 li a2,0 - -000000f4 <.LBE13>: - f4: 4505 li a0,1 - f6: b79d j 5c <.L7> - -000000f8 <.L11>: - f8: 8726 mv a4,s1 - -000000fa <.LVL36>: - fa: 843e mv s0,a5 - -000000fc <.LBE14>: - fc: 851a mv a0,t1 - -000000fe <.L15>: - fe: 4789 li a5,2 - -00000100 <.LVL39>: - 100: 1af50d63 beq a0,a5,2ba <.L40> - 104: 478d li a5,3 - 106: 1af50463 beq a0,a5,2ae <.L38> - 10a: 4785 li a5,1 - 10c: 0ef51e63 bne a0,a5,208 <.L24> - -00000110 <.L39>: - 110: 4781 li a5,0 - -00000112 <.L54>: - 112: 4501 li a0,0 - 114: a23d j 242 <.L9> - -00000116 <.L8>: - 116: 00541613 sll a2,s0,0x5 - -0000011a <.LVL43>: - 11a: 1487f063 bgeu a5,s0,25a <.L16> - 11e: 16fd add a3,a3,-1 - -00000120 <.LVL44>: - 120: 4381 li t2,0 - -00000122 <.L17>: - 122: c83a sw a4,16(sp) - -00000124 <.LBB16>: - 124: 01065713 srl a4,a2,0x10 - -00000128 <.LVL47>: - 128: c03a sw a4,0(sp) - -0000012a <.LVL48>: - 12a: 4582 lw a1,0(sp) - -0000012c <.LVL49>: - 12c: 6441 lui s0,0x10 - -0000012e <.LVL50>: - 12e: 147d add s0,s0,-1 # ffff <.LLST37+0xf84a> - 130: 00867733 and a4,a2,s0 - -00000134 <.LVL51>: - 134: 853e mv a0,a5 - -00000136 <.LVL52>: - 136: cc36 sw a3,24(sp) - -00000138 <.LVL53>: - 138: ca1e sw t2,20(sp) - -0000013a <.LVL54>: - 13a: c632 sw a2,12(sp) - 13c: c23a sw a4,4(sp) - -0000013e <.LVL55>: - 13e: c43e sw a5,8(sp) - 140: 00000097 auipc ra,0x0 - 144: 000080e7 jalr ra # 140 <.LVL55+0x2> - -00000148 <.LVL56>: - 148: 85aa mv a1,a0 - 14a: 842a mv s0,a0 - -0000014c <.LVL57>: - 14c: 4512 lw a0,4(sp) - 14e: 00000097 auipc ra,0x0 - 152: 000080e7 jalr ra # 14e <.LVL57+0x2> - -00000156 <.LVL58>: - 156: 47a2 lw a5,8(sp) - 158: 4582 lw a1,0(sp) - 15a: 84aa mv s1,a0 - -0000015c <.LVL59>: - 15c: 853e mv a0,a5 - 15e: 00000097 auipc ra,0x0 - 162: 000080e7 jalr ra # 15e <.LVL59+0x2> - -00000166 <.LVL60>: - 166: 43d2 lw t2,20(sp) - 168: 0542 sll a0,a0,0x10 - 16a: 4632 lw a2,12(sp) - 16c: 0103d593 srl a1,t2,0x10 - 170: 8dc9 or a1,a1,a0 - -00000172 <.LVL61>: - 172: 4742 lw a4,16(sp) - 174: 46e2 lw a3,24(sp) - 176: 87a2 mv a5,s0 - 178: 0095fc63 bgeu a1,s1,190 <.L18> - -0000017c <.LVL62>: - 17c: 95b2 add a1,a1,a2 - -0000017e <.LVL63>: - 17e: fff40793 add a5,s0,-1 - -00000182 <.LVL64>: - 182: 00c5e763 bltu a1,a2,190 <.L18> - 186: 0095f563 bgeu a1,s1,190 <.L18> - 18a: ffe40793 add a5,s0,-2 - 18e: 95b2 add a1,a1,a2 - -00000190 <.L18>: - 190: c83e sw a5,16(sp) - 192: 409587b3 sub a5,a1,s1 - -00000196 <.LVL67>: - 196: 4582 lw a1,0(sp) - -00000198 <.LVL68>: - 198: 853e mv a0,a5 - 19a: 843e mv s0,a5 - 19c: ca36 sw a3,20(sp) - 19e: c63a sw a4,12(sp) - -000001a0 <.LVL69>: - 1a0: cc32 sw a2,24(sp) - 1a2: 00000097 auipc ra,0x0 - 1a6: 000080e7 jalr ra # 1a2 <.LVL69+0x2> - -000001aa <.LVL70>: - 1aa: 85aa mv a1,a0 - 1ac: c42a sw a0,8(sp) - -000001ae <.LVL71>: - 1ae: 4512 lw a0,4(sp) - -000001b0 <.LVL72>: - 1b0: 00000097 auipc ra,0x0 - 1b4: 000080e7 jalr ra # 1b0 <.LVL72> - -000001b8 <.LVL73>: - 1b8: 4582 lw a1,0(sp) - 1ba: 84aa mv s1,a0 - 1bc: 8522 mv a0,s0 - 1be: 00000097 auipc ra,0x0 - 1c2: 000080e7 jalr ra # 1be <.LVL73+0x6> - -000001c6 <.LVL75>: - 1c6: 43a2 lw t2,8(sp) - 1c8: 01051313 sll t1,a0,0x10 - -000001cc <.LVL76>: - 1cc: 4732 lw a4,12(sp) - 1ce: 47c2 lw a5,16(sp) - 1d0: 46d2 lw a3,20(sp) - 1d2: 859e mv a1,t2 - 1d4: 02937163 bgeu t1,s1,1f6 <.L21> - -000001d8 <.LVL77>: - 1d8: 4662 lw a2,24(sp) - 1da: fff38593 add a1,t2,-1 - -000001de <.LVL78>: - 1de: 00c30533 add a0,t1,a2 - 1e2: 00653433 sltu s0,a0,t1 - -000001e6 <.LVL79>: - 1e6: 832a mv t1,a0 - 1e8: e419 bnez s0,1f6 <.L21> - -000001ea <.LVL81>: - 1ea: 00957663 bgeu a0,s1,1f6 <.L21> - 1ee: ffe38593 add a1,t2,-2 - 1f2: 00c50333 add t1,a0,a2 - -000001f6 <.L21>: - 1f6: 01079413 sll s0,a5,0x10 - -000001fa <.LBE17>: - 1fa: 40930333 sub t1,t1,s1 - -000001fe <.LBB18>: - 1fe: 8c4d or s0,s0,a1 - -00000200 <.LBE18>: - 200: 00603333 snez t1,t1 - -00000204 <.LVL86>: - 204: 00646433 or s0,s0,t1 - -00000208 <.L24>: - 208: 07f68513 add a0,a3,127 - -0000020c <.LVL88>: - 20c: 04a05d63 blez a0,266 <.L25> - 210: 00747793 and a5,s0,7 - 214: c799 beqz a5,222 <.L26> - 216: 00f47793 and a5,s0,15 - 21a: 4611 li a2,4 - 21c: 00c78363 beq a5,a2,222 <.L26> - 220: 0411 add s0,s0,4 - -00000222 <.L26>: - 222: 080007b7 lui a5,0x8000 - 226: 8fe1 and a5,a5,s0 - 228: c799 beqz a5,236 <.L27> - 22a: f80007b7 lui a5,0xf8000 - 22e: 17fd add a5,a5,-1 # f7ffffff <.LLST37+0xf7fff84a> - 230: 8c7d and s0,s0,a5 - 232: 08068513 add a0,a3,128 - -00000236 <.L27>: - 236: 0fe00793 li a5,254 - 23a: 08a7c063 blt a5,a0,2ba <.L40> - 23e: 00345793 srl a5,s0,0x3 - -00000242 <.L9>: - 242: 5092 lw ra,36(sp) - 244: 5402 lw s0,32(sp) - -00000246 <.LBB20>: - 246: 07a6 sll a5,a5,0x9 - -00000248 <.LVL93>: - 248: 055e sll a0,a0,0x17 - -0000024a <.LVL94>: - 24a: 83a5 srl a5,a5,0x9 - 24c: 8d5d or a0,a0,a5 - 24e: 077e sll a4,a4,0x1f - -00000250 <.LBE20>: - 250: 44f2 lw s1,28(sp) - 252: 8d59 or a0,a0,a4 - -00000254 <.LVL96>: - 254: 02810113 add sp,sp,40 - 258: 8082 ret - -0000025a <.L16>: - 25a: 01f79393 sll t2,a5,0x1f - -0000025e <.LVL98>: - 25e: 8385 srl a5,a5,0x1 - -00000260 <.LVL99>: - 260: b5c9 j 122 <.L17> - -00000262 <.L12>: - 262: 872e mv a4,a1 - -00000264 <.LBE22>: - 264: bd69 j fe <.L15> - -00000266 <.L25>: - 266: 4605 li a2,1 - 268: c519 beqz a0,276 <.L28> - 26a: 8e09 sub a2,a2,a0 - -0000026c <.LVL103>: - 26c: 45ed li a1,27 - 26e: 4781 li a5,0 - 270: 4501 li a0,0 - 272: fcc5c8e3 blt a1,a2,242 <.L9> - -00000276 <.L28>: - 276: 09e68693 add a3,a3,158 - 27a: 00c45633 srl a2,s0,a2 - 27e: 00d41433 sll s0,s0,a3 - -00000282 <.LVL105>: - 282: 00803433 snez s0,s0 - 286: 008667b3 or a5,a2,s0 - -0000028a <.LVL106>: - 28a: 0077f693 and a3,a5,7 - 28e: c699 beqz a3,29c <.L29> - 290: 00f7f693 and a3,a5,15 - 294: 4611 li a2,4 - 296: 00c68363 beq a3,a2,29c <.L29> - 29a: 0791 add a5,a5,4 - -0000029c <.L29>: - 29c: 040006b7 lui a3,0x4000 - 2a0: 8efd and a3,a3,a5 - 2a2: 838d srl a5,a5,0x3 - -000002a4 <.LVL108>: - 2a4: e60687e3 beqz a3,112 <.L54> - 2a8: 4781 li a5,0 - 2aa: 4505 li a0,1 - 2ac: bf59 j 242 <.L9> - -000002ae <.L38>: - 2ae: 004007b7 lui a5,0x400 - 2b2: 0ff00513 li a0,255 - 2b6: 4701 li a4,0 - -000002b8 <.LVL110>: - 2b8: b769 j 242 <.L9> - -000002ba <.L40>: - 2ba: 4781 li a5,0 - 2bc: 0ff00513 li a0,255 - 2c0: b749 j 242 <.L9> - -eqsf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__eqsf2>: - 0: 01755613 srl a2,a0,0x17 - 4: 008007b7 lui a5,0x800 - 8: 17fd add a5,a5,-1 # 7fffff <.LASF9+0x7ffe6f> - -0000000a <.LBB3>: - a: 0175d713 srl a4,a1,0x17 - -0000000e <.LBB4>: - e: 0ff67613 zext.b a2,a2 - -00000012 <.LBE4>: - 12: 0ff00293 li t0,255 - -00000016 <.LBB5>: - 16: 00a7f333 and t1,a5,a0 - 1a: 01f55693 srl a3,a0,0x1f - -0000001e <.LBB6>: - 1e: 8fed and a5,a5,a1 - -00000020 <.LVL3>: - 20: 0ff77713 zext.b a4,a4 - 24: 81fd srl a1,a1,0x1f - -00000026 <.LBE6>: - 26: 4505 li a0,1 - -00000028 <.LVL6>: - 28: 00560563 beq a2,t0,32 <.L2> - 2c: 00571b63 bne a4,t0,42 <.L12> - 30: 8082 ret - -00000032 <.L2>: - 32: 02c71463 bne a4,a2,5a <.L1> - 36: 00f367b3 or a5,t1,a5 - -0000003a <.LVL7>: - 3a: e385 bnez a5,5a <.L1> - 3c: 00b6c533 xor a0,a3,a1 - 40: 8082 ret - -00000042 <.L12>: - 42: 4505 li a0,1 - 44: 00e61b63 bne a2,a4,5a <.L1> - 48: 00f31963 bne t1,a5,5a <.L1> - 4c: 00b68663 beq a3,a1,58 <.L10> - 50: e609 bnez a2,5a <.L1> - 52: 00603533 snez a0,t1 - 56: 8082 ret - -00000058 <.L10>: - 58: 4501 li a0,0 - -0000005a <.L1>: - 5a: 8082 ret - -gesf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__gesf2>: - 0: 00800737 lui a4,0x800 - 4: 177d add a4,a4,-1 # 7fffff <.LASF19+0x7ffe4f> - 6: 01755693 srl a3,a0,0x17 - a: 00a77633 and a2,a4,a0 - e: 01f55793 srl a5,a0,0x1f - 12: 0ff6f693 zext.b a3,a3 - -00000016 <.LBB3>: - 16: 0175d513 srl a0,a1,0x17 - -0000001a <.LBE3>: - 1a: 0ff00313 li t1,255 - -0000001e <.LBB4>: - 1e: 8f6d and a4,a4,a1 - 20: 0ff57513 zext.b a0,a0 - -00000024 <.LVL5>: - 24: 81fd srl a1,a1,0x1f - -00000026 <.LBE4>: - 26: 00669f63 bne a3,t1,44 <.L2> - 2a: e225 bnez a2,8a <.L22> - 2c: 00d50663 beq a0,a3,38 <.L4> - -00000030 <.L62>: - 30: 4505 li a0,1 - 32: c7b1 beqz a5,7e <.L1> - 34: 557d li a0,-1 - 36: 8082 ret - -00000038 <.L4>: - 38: 5579 li a0,-2 - -0000003a <.LVL9>: - 3a: e331 bnez a4,7e <.L1> - -0000003c <.LBB6>: - 3c: feb79ae3 bne a5,a1,30 <.L62> - 40: 4501 li a0,0 - 42: 8082 ret - -00000044 <.L2>: - 44: 00651c63 bne a0,t1,5c <.L8> - 48: 5579 li a0,-2 - -0000004a <.LVL11>: - 4a: eb15 bnez a4,7e <.L1> - -0000004c <.LBB7>: - 4c: e291 bnez a3,50 <.L9> - -0000004e <.L60>: - 4e: ca15 beqz a2,82 <.L10> - -00000050 <.L9>: - 50: feb790e3 bne a5,a1,30 <.L62> - -00000054 <.L66>: - 54: 557d li a0,-1 - 56: c785 beqz a5,7e <.L1> - 58: 853e mv a0,a5 - 5a: 8082 ret - -0000005c <.L8>: - 5c: ce91 beqz a3,78 <.L12> - -0000005e <.LVL16>: - 5e: d969 beqz a0,30 <.L62> - -00000060 <.LVL17>: - 60: fcb798e3 bne a5,a1,30 <.L62> - 64: fcd546e3 blt a0,a3,30 <.L62> - 68: fea6c6e3 blt a3,a0,54 <.L66> - -0000006c <.L19>: - 6c: fcc762e3 bltu a4,a2,30 <.L62> - 70: 4501 li a0,0 - -00000072 <.LVL18>: - 72: 00e67663 bgeu a2,a4,7e <.L1> - 76: bff9 j 54 <.L66> - -00000078 <.L12>: - 78: f979 bnez a0,4e <.L60> - 7a: e319 bnez a4,80 <.L15> - -0000007c <.LVL20>: - 7c: fa55 bnez a2,30 <.L62> - -0000007e <.L1>: - 7e: 8082 ret - -00000080 <.L15>: - 80: e619 bnez a2,8e <.L16> - -00000082 <.L10>: - 82: 557d li a0,-1 - 84: dded beqz a1,7e <.L1> - 86: 852e mv a0,a1 - 88: 8082 ret - -0000008a <.L22>: - 8a: 5579 li a0,-2 - -0000008c <.LVL25>: - 8c: 8082 ret - -0000008e <.L16>: - 8e: fcb78fe3 beq a5,a1,6c <.L19> - 92: bf79 j 30 <.L62> - -lesf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__lesf2>: - 0: 00800737 lui a4,0x800 - 4: 177d add a4,a4,-1 # 7fffff <.LASF19+0x7ffe4f> - 6: 01755693 srl a3,a0,0x17 - a: 00a77633 and a2,a4,a0 - e: 01f55793 srl a5,a0,0x1f - 12: 0ff6f693 zext.b a3,a3 - -00000016 <.LBB3>: - 16: 0175d513 srl a0,a1,0x17 - -0000001a <.LBE3>: - 1a: 0ff00313 li t1,255 - -0000001e <.LBB4>: - 1e: 8f6d and a4,a4,a1 - 20: 0ff57513 zext.b a0,a0 - -00000024 <.LVL5>: - 24: 81fd srl a1,a1,0x1f - -00000026 <.LBE4>: - 26: 00669f63 bne a3,t1,44 <.L2> - 2a: e225 bnez a2,8a <.L22> - 2c: 00d50663 beq a0,a3,38 <.L4> - -00000030 <.L62>: - 30: 4505 li a0,1 - 32: c7b1 beqz a5,7e <.L1> - 34: 557d li a0,-1 - 36: 8082 ret - -00000038 <.L4>: - 38: 4509 li a0,2 - -0000003a <.LVL9>: - 3a: e331 bnez a4,7e <.L1> - -0000003c <.LBB6>: - 3c: feb79ae3 bne a5,a1,30 <.L62> - 40: 4501 li a0,0 - 42: 8082 ret - -00000044 <.L2>: - 44: 00651c63 bne a0,t1,5c <.L8> - 48: 4509 li a0,2 - -0000004a <.LVL11>: - 4a: eb15 bnez a4,7e <.L1> - -0000004c <.LBB7>: - 4c: e291 bnez a3,50 <.L9> - -0000004e <.L60>: - 4e: ca15 beqz a2,82 <.L10> - -00000050 <.L9>: - 50: feb790e3 bne a5,a1,30 <.L62> - -00000054 <.L66>: - 54: 557d li a0,-1 - 56: c785 beqz a5,7e <.L1> - 58: 853e mv a0,a5 - 5a: 8082 ret - -0000005c <.L8>: - 5c: ce91 beqz a3,78 <.L12> - -0000005e <.LVL16>: - 5e: d969 beqz a0,30 <.L62> - -00000060 <.LVL17>: - 60: fcb798e3 bne a5,a1,30 <.L62> - 64: fcd546e3 blt a0,a3,30 <.L62> - 68: fea6c6e3 blt a3,a0,54 <.L66> - -0000006c <.L19>: - 6c: fcc762e3 bltu a4,a2,30 <.L62> - 70: 4501 li a0,0 - -00000072 <.LVL18>: - 72: 00e67663 bgeu a2,a4,7e <.L1> - 76: bff9 j 54 <.L66> - -00000078 <.L12>: - 78: f979 bnez a0,4e <.L60> - 7a: e319 bnez a4,80 <.L15> - -0000007c <.LVL20>: - 7c: fa55 bnez a2,30 <.L62> - -0000007e <.L1>: - 7e: 8082 ret - -00000080 <.L15>: - 80: e619 bnez a2,8e <.L16> - -00000082 <.L10>: - 82: 557d li a0,-1 - 84: dded beqz a1,7e <.L1> - 86: 852e mv a0,a1 - 88: 8082 ret - -0000008a <.L22>: - 8a: 4509 li a0,2 - -0000008c <.LVL25>: - 8c: 8082 ret - -0000008e <.L16>: - 8e: fcb78fe3 beq a5,a1,6c <.L19> - 92: bf79 j 30 <.L62> - -mulsf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__mulsf3>: - 0: 1111 add sp,sp,-28 - 2: 01755293 srl t0,a0,0x17 - 6: ca22 sw s0,20(sp) - 8: c826 sw s1,16(sp) - -0000000a <.LBB3>: - a: 00951713 sll a4,a0,0x9 - -0000000e <.LBE3>: - e: cc06 sw ra,24(sp) - 10: 0ff2f293 zext.b t0,t0 - 14: 84ae mv s1,a1 - -00000016 <.LBB4>: - 16: 8325 srl a4,a4,0x9 - -00000018 <.LVL1>: - 18: 01f55413 srl s0,a0,0x1f - -0000001c <.LBE4>: - 1c: 14028763 beqz t0,16a <.L2> - 20: 0ff00793 li a5,255 - 24: 16f28463 beq t0,a5,18c <.L3> - -00000028 <.LVL3>: - 28: 070e sll a4,a4,0x3 - -0000002a <.LVL4>: - 2a: 040007b7 lui a5,0x4000 - 2e: 8f5d or a4,a4,a5 - -00000030 <.LVL5>: - 30: f8128293 add t0,t0,-127 - -00000034 <.L47>: - 34: 4601 li a2,0 - -00000036 <.L4>: - 36: 0174d693 srl a3,s1,0x17 - 3a: 00949793 sll a5,s1,0x9 - 3e: 0ff6f693 zext.b a3,a3 - 42: 83a5 srl a5,a5,0x9 - -00000044 <.LVL8>: - 44: 80fd srl s1,s1,0x1f - -00000046 <.LBE6>: - 46: 14068d63 beqz a3,1a0 <.L5> - 4a: 0ff00593 li a1,255 - 4e: 18b68063 beq a3,a1,1ce <.L6> - -00000052 <.LVL10>: - 52: 040005b7 lui a1,0x4000 - 56: 078e sll a5,a5,0x3 - -00000058 <.LVL11>: - 58: 8fcd or a5,a5,a1 - -0000005a <.LVL12>: - 5a: f8168693 add a3,a3,-127 - -0000005e <.LVL13>: - 5e: 4581 li a1,0 - -00000060 <.L7>: - 60: 9696 add a3,a3,t0 - -00000062 <.LVL15>: - 62: c036 sw a3,0(sp) - 64: 00168293 add t0,a3,1 - -00000068 <.LVL16>: - 68: 00261693 sll a3,a2,0x2 - 6c: 8ecd or a3,a3,a1 - 6e: 4529 li a0,10 - 70: 00944333 xor t1,s0,s1 - -00000074 <.LVL17>: - 74: 1ad54163 blt a0,a3,216 <.L8> - 78: 4509 li a0,2 - 7a: 16d54463 blt a0,a3,1e2 <.L9> - 7e: 16fd add a3,a3,-1 - 80: 4605 li a2,1 - -00000082 <.LVL18>: - 82: 16d67e63 bgeu a2,a3,1fe <.L11> - -00000086 <.L10>: - 86: 64c1 lui s1,0x10 - -00000088 <.LVL20>: - 88: 01075693 srl a3,a4,0x10 - 8c: fff48393 add t2,s1,-1 # ffff <.LLST34+0xf9c9> - 90: c236 sw a3,4(sp) - -00000092 <.LVL21>: - 92: 00777733 and a4,a4,t2 - -00000096 <.LVL22>: - 96: 0107d693 srl a3,a5,0x10 - 9a: 0077f7b3 and a5,a5,t2 - -0000009e <.LVL23>: - 9e: c436 sw a3,8(sp) - -000000a0 <.LBB9>: - a0: 853a mv a0,a4 - a2: 85be mv a1,a5 - -000000a4 <.LVL25>: - a4: 00000097 auipc ra,0x0 - a8: 000080e7 jalr ra # a4 <.LVL25> - ac: 842a mv s0,a0 - -000000ae <.LBB10>: - ae: 45a2 lw a1,8(sp) - b0: 853a mv a0,a4 - b2: 00000097 auipc ra,0x0 - b6: 000080e7 jalr ra # b2 <.LBB10+0x4> - ba: 872a mv a4,a0 - -000000bc <.LBB11>: - bc: 85be mv a1,a5 - be: 4512 lw a0,4(sp) - -000000c0 <.LVL28>: - c0: 00000097 auipc ra,0x0 - c4: 000080e7 jalr ra # c0 <.LVL28> - c8: 87aa mv a5,a0 - -000000ca <.LBB12>: - ca: 45a2 lw a1,8(sp) - cc: 4512 lw a0,4(sp) - -000000ce <.LVL30>: - ce: 00000097 auipc ra,0x0 - d2: 000080e7 jalr ra # ce <.LVL30> - -000000d6 <.LBE12>: - d6: 01045693 srl a3,s0,0x10 - da: 973e add a4,a4,a5 - -000000dc <.LVL32>: - dc: 9736 add a4,a4,a3 - -000000de <.LVL33>: - de: 00f77363 bgeu a4,a5,e4 <.L15> - e2: 9526 add a0,a0,s1 - -000000e4 <.L15>: - e4: 007777b3 and a5,a4,t2 - -000000e8 <.LVL35>: - e8: 007476b3 and a3,s0,t2 - ec: 07c2 sll a5,a5,0x10 - ee: 97b6 add a5,a5,a3 - -000000f0 <.LBE8>: - f0: 00679693 sll a3,a5,0x6 - f4: 00d036b3 snez a3,a3 - f8: 83e9 srl a5,a5,0x1a - -000000fa <.LVL37>: - fa: 8edd or a3,a3,a5 - -000000fc <.LBB14>: - fc: 01075793 srl a5,a4,0x10 - 100: 97aa add a5,a5,a0 - -00000102 <.LBE14>: - 102: 079a sll a5,a5,0x6 - -00000104 <.LVL39>: - 104: 8fd5 or a5,a5,a3 - -00000106 <.LBE7>: - 106: 08000737 lui a4,0x8000 - -0000010a <.LVL41>: - 10a: 8f7d and a4,a4,a5 - 10c: 10070f63 beqz a4,22a <.L29> - 110: 0017d713 srl a4,a5,0x1 - 114: 8b85 and a5,a5,1 - -00000116 <.LVL42>: - 116: 8fd9 or a5,a5,a4 - -00000118 <.L16>: - 118: 07f28513 add a0,t0,127 - -0000011c <.LVL44>: - 11c: 10a05963 blez a0,22e <.L17> - 120: 0077f713 and a4,a5,7 - 124: c719 beqz a4,132 <.L18> - 126: 00f7f713 and a4,a5,15 - 12a: 4691 li a3,4 - 12c: 00d70363 beq a4,a3,132 <.L18> - 130: 0791 add a5,a5,4 # 4000004 <.LLST34+0x3fff9ce> - -00000132 <.L18>: - 132: 08000737 lui a4,0x8000 - 136: 8f7d and a4,a4,a5 - 138: c719 beqz a4,146 <.L19> - 13a: f8000737 lui a4,0xf8000 - 13e: 177d add a4,a4,-1 # f7ffffff <.LLST34+0xf7fff9c9> - 140: 8ff9 and a5,a5,a4 - 142: 08028513 add a0,t0,128 - -00000146 <.L19>: - 146: 0fe00713 li a4,254 - 14a: 12a74b63 blt a4,a0,280 <.L33> - 14e: 0037d713 srl a4,a5,0x3 - -00000152 <.L12>: - 152: 40e2 lw ra,24(sp) - 154: 4452 lw s0,20(sp) - -00000156 <.LBB17>: - 156: 0726 sll a4,a4,0x9 - -00000158 <.LVL49>: - 158: 055e sll a0,a0,0x17 - -0000015a <.LVL50>: - 15a: 8325 srl a4,a4,0x9 - 15c: 8d59 or a0,a0,a4 - 15e: 037e sll t1,t1,0x1f - -00000160 <.LBE17>: - 160: 44c2 lw s1,16(sp) - 162: 00656533 or a0,a0,t1 - -00000166 <.LVL52>: - 166: 0171 add sp,sp,28 - 168: 8082 ret - -0000016a <.L2>: - 16a: cb05 beqz a4,19a <.L22> - -0000016c <.LBB18>: - 16c: 853a mv a0,a4 - -0000016e <.LVL54>: - 16e: c03a sw a4,0(sp) - 170: 00000097 auipc ra,0x0 - 174: 000080e7 jalr ra # 170 <.LVL54+0x2> - -00000178 <.LVL55>: - 178: 4702 lw a4,0(sp) - 17a: ffb50793 add a5,a0,-5 - 17e: f8a00293 li t0,-118 - 182: 00f71733 sll a4,a4,a5 - -00000186 <.LVL56>: - 186: 40a282b3 sub t0,t0,a0 - 18a: b56d j 34 <.L47> - -0000018c <.L3>: - 18c: 0ff00293 li t0,255 - -00000190 <.LBE19>: - 190: 460d li a2,3 - 192: ea0712e3 bnez a4,36 <.L4> - 196: 4609 li a2,2 - 198: bd79 j 36 <.L4> - -0000019a <.L22>: - 19a: 4281 li t0,0 - -0000019c <.LBE20>: - 19c: 4605 li a2,1 - 19e: bd61 j 36 <.L4> - -000001a0 <.L5>: - 1a0: cf95 beqz a5,1dc <.L24> - -000001a2 <.LBB21>: - 1a2: 853e mv a0,a5 - 1a4: c63a sw a4,12(sp) - 1a6: c416 sw t0,8(sp) - 1a8: c232 sw a2,4(sp) - -000001aa <.LBB22>: - 1aa: c03e sw a5,0(sp) - 1ac: 00000097 auipc ra,0x0 - 1b0: 000080e7 jalr ra # 1ac <.LBB22+0x2> - -000001b4 <.LVL62>: - 1b4: 4782 lw a5,0(sp) - 1b6: ffb50693 add a3,a0,-5 - 1ba: 4612 lw a2,4(sp) - 1bc: 00d797b3 sll a5,a5,a3 - -000001c0 <.LVL63>: - 1c0: f8a00693 li a3,-118 - 1c4: 42a2 lw t0,8(sp) - 1c6: 4732 lw a4,12(sp) - 1c8: 8e89 sub a3,a3,a0 - -000001ca <.LVL64>: - 1ca: 4581 li a1,0 - 1cc: bd51 j 60 <.L7> - -000001ce <.L6>: - 1ce: 0ff00693 li a3,255 - -000001d2 <.LBE23>: - 1d2: 458d li a1,3 - 1d4: e80796e3 bnez a5,60 <.L7> - 1d8: 4589 li a1,2 - 1da: b559 j 60 <.L7> - -000001dc <.L24>: - 1dc: 4681 li a3,0 - -000001de <.LBE24>: - 1de: 4585 li a1,1 - 1e0: b541 j 60 <.L7> - -000001e2 <.L9>: - 1e2: 4505 li a0,1 - 1e4: 00d516b3 sll a3,a0,a3 - 1e8: 5306f513 and a0,a3,1328 - 1ec: ed05 bnez a0,224 <.L26> - 1ee: 2406f613 and a2,a3,576 - -000001f2 <.LVL70>: - 1f2: e249 bnez a2,274 <.L31> - 1f4: 0886f693 and a3,a3,136 - 1f8: e80687e3 beqz a3,86 <.L10> - -000001fc <.L13>: - 1fc: 8326 mv t1,s1 - -000001fe <.L11>: - 1fe: 4709 li a4,2 - -00000200 <.LVL73>: - 200: 08e58063 beq a1,a4,280 <.L33> - 204: 470d li a4,3 - 206: 06e58763 beq a1,a4,274 <.L31> - 20a: 4705 li a4,1 - 20c: f0e596e3 bne a1,a4,118 <.L16> - 210: 4701 li a4,0 - -00000212 <.L48>: - 212: 4501 li a0,0 - 214: bf3d j 152 <.L12> - -00000216 <.L8>: - 216: 453d li a0,15 - 218: 04a68e63 beq a3,a0,274 <.L31> - 21c: 452d li a0,11 - -0000021e <.LBB26>: - 21e: 8322 mv t1,s0 - -00000220 <.LBE26>: - 220: fca68ee3 beq a3,a0,1fc <.L13> - -00000224 <.L26>: - 224: 87ba mv a5,a4 - -00000226 <.LVL77>: - 226: 85b2 mv a1,a2 - -00000228 <.LVL78>: - 228: bfd9 j 1fe <.L11> - -0000022a <.L29>: - 22a: 4282 lw t0,0(sp) - -0000022c <.LVL80>: - 22c: b5f5 j 118 <.L16> - -0000022e <.L17>: - 22e: 4685 li a3,1 - 230: c519 beqz a0,23e <.L20> - 232: 8e89 sub a3,a3,a0 - -00000234 <.LVL82>: - 234: 466d li a2,27 - 236: 4701 li a4,0 - 238: 4501 li a0,0 - 23a: f0d64ce3 blt a2,a3,152 <.L12> - -0000023e <.L20>: - 23e: 09e28293 add t0,t0,158 - 242: 00d7d6b3 srl a3,a5,a3 - 246: 005797b3 sll a5,a5,t0 - 24a: 00f037b3 snez a5,a5 - 24e: 00f6e733 or a4,a3,a5 - -00000252 <.LVL84>: - 252: 00777793 and a5,a4,7 - 256: c799 beqz a5,264 <.L21> - 258: 00f77793 and a5,a4,15 - 25c: 4691 li a3,4 - 25e: 00d78363 beq a5,a3,264 <.L21> - 262: 0711 add a4,a4,4 - -00000264 <.L21>: - 264: 040007b7 lui a5,0x4000 - 268: 8ff9 and a5,a5,a4 - 26a: 830d srl a4,a4,0x3 - -0000026c <.LVL86>: - 26c: d3dd beqz a5,212 <.L48> - 26e: 4701 li a4,0 - 270: 4505 li a0,1 - 272: b5c5 j 152 <.L12> - -00000274 <.L31>: - 274: 00400737 lui a4,0x400 - 278: 0ff00513 li a0,255 - 27c: 4301 li t1,0 - -0000027e <.LVL88>: - 27e: bdd1 j 152 <.L12> - -00000280 <.L33>: - 280: 4701 li a4,0 - 282: 0ff00513 li a0,255 - 286: b5f1 j 152 <.L12> - -negsf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__negsf2>: - 0: 00951713 sll a4,a0,0x9 - 4: 01f55793 srl a5,a0,0x1f - -00000008 <.LBB3>: - 8: 7f8006b7 lui a3,0x7f800 - -0000000c <.LBB4>: - c: 8325 srl a4,a4,0x9 - -0000000e <.LBB5>: - e: 8d75 and a0,a0,a3 - -00000010 <.LVL2>: - 10: 0017c793 xor a5,a5,1 - -00000014 <.LVL3>: - 14: 07fe sll a5,a5,0x1f - -00000016 <.LVL4>: - 16: 8d59 or a0,a0,a4 - -00000018 <.LBE5>: - 18: 8d5d or a0,a0,a5 - -0000001a <.LVL6>: - 1a: 8082 ret - -subsf3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__subsf3>: - 0: 008007b7 lui a5,0x800 - -00000004 <.LBE2>: - 4: 1141 add sp,sp,-16 - -00000006 <.LBB3>: - 6: 17fd add a5,a5,-1 # 7fffff <.LLST21+0x7ff59a> - 8: 00a7f633 and a2,a5,a0 - -0000000c <.LBE3>: - c: c422 sw s0,8(sp) - -0000000e <.LBB4>: - e: 01f55713 srl a4,a0,0x1f - 12: 01755413 srl s0,a0,0x17 - -00000016 <.LBB5>: - 16: 0175d513 srl a0,a1,0x17 - -0000001a <.LVL2>: - 1a: 8fed and a5,a5,a1 - -0000001c <.LBE5>: - 1c: c606 sw ra,12(sp) - 1e: c226 sw s1,4(sp) - -00000020 <.LBB6>: - 20: 0ff57513 zext.b a0,a0 - -00000024 <.LBE6>: - 24: 0ff00313 li t1,255 - -00000028 <.LBB7>: - 28: 0ff47413 zext.b s0,s0 - -0000002c <.LBE7>: - 2c: 060e sll a2,a2,0x3 - -0000002e <.LBB8>: - 2e: 81fd srl a1,a1,0x1f - -00000030 <.LBE8>: - 30: 078e sll a5,a5,0x3 - 32: 06651763 bne a0,t1,a0 <.L2> - -00000036 <.LBB9>: - 36: f0140693 add a3,s0,-255 - -0000003a <.LBE9>: - 3a: cb91 beqz a5,4e <.L3> - -0000003c <.LBB10>: - 3c: 82ae mv t0,a1 - -0000003e <.LBE10>: - 3e: 1eb71363 bne a4,a1,224 <.L118> - -00000042 <.LBB11>: - 42: 14068363 beqz a3,188 <.L17> - -00000046 <.LVL7>: - 46: e451 bnez s0,d2 <.L125> - -00000048 <.L54>: - 48: 0ff00413 li s0,255 - -0000004c <.LVL9>: - 4c: a211 j 150 <.L18> - -0000004e <.L3>: - 4e: 0015c293 xor t0,a1,1 - -00000052 <.LVL11>: - 52: 1c571f63 bne a4,t0,230 <.L119> - -00000056 <.LBB12>: - 56: 12068963 beqz a3,188 <.L17> - -0000005a <.LVL12>: - 5a: d47d beqz s0,48 <.L54> - 5c: 0ff00413 li s0,255 - -00000060 <.L47>: - 60: 040006b7 lui a3,0x4000 - 64: 8efd and a3,a3,a5 - 66: 2c068c63 beqz a3,33e <.L48> - -0000006a <.LVL14>: - 6a: 0405 add s0,s0,1 - -0000006c <.LVL15>: - 6c: 0ff00693 li a3,255 - 70: 4481 li s1,0 - 72: 00d40863 beq s0,a3,82 <.L25> - 76: 0037d493 srl s1,a5,0x3 - 7a: 1f8007b7 lui a5,0x1f800 - -0000007e <.LVL16>: - 7e: 17fd add a5,a5,-1 # 1f7fffff <.LLST21+0x1f7ff59a> - 80: 8cfd and s1,s1,a5 - -00000082 <.L25>: - 82: 045e sll s0,s0,0x17 - 84: 7f8007b7 lui a5,0x7f800 - 88: 04a6 sll s1,s1,0x9 - -0000008a <.LVL18>: - 8a: 80a5 srl s1,s1,0x9 - 8c: 8c7d and s0,s0,a5 - 8e: 8c45 or s0,s0,s1 - 90: 01f71513 sll a0,a4,0x1f - -00000094 <.LBE14>: - 94: 40b2 lw ra,12(sp) - 96: 8d41 or a0,a0,s0 - -00000098 <.LVL20>: - 98: 4422 lw s0,8(sp) - 9a: 4492 lw s1,4(sp) - 9c: 0141 add sp,sp,16 - 9e: 8082 ret - -000000a0 <.L2>: - a0: 0015c293 xor t0,a1,1 - -000000a4 <.LBB15>: - a4: 40a406b3 sub a3,s0,a0 - -000000a8 <.LBE15>: - a8: 10571f63 bne a4,t0,1c6 <.L8> - -000000ac <.LBB16>: - ac: 08d05963 blez a3,13e <.L9> - -000000b0 <.LVL24>: - b0: e505 bnez a0,d8 <.L10> - b2: 28078263 beqz a5,336 <.L62> - b6: fff68593 add a1,a3,-1 # 3ffffff <.LLST21+0x3fff59a> - -000000ba <.LVL25>: - ba: e989 bnez a1,cc <.L12> - -000000bc <.L131>: - bc: 97b2 add a5,a5,a2 - -000000be <.LVL27>: - be: 040006b7 lui a3,0x4000 - c2: 8efd and a3,a3,a5 - c4: 4409 li s0,2 - c6: e2bd bnez a3,12c <.L13> - -000000c8 <.L126>: - c8: 4405 li s0,1 - ca: a015 j ee <.L11> - -000000cc <.L12>: - cc: 00669c63 bne a3,t1,e4 <.L14> - -000000d0 <.L73>: - d0: 87b2 mv a5,a2 - -000000d2 <.L125>: - d2: 0ff00413 li s0,255 - -000000d6 <.LVL32>: - d6: a821 j ee <.L11> - -000000d8 <.L10>: - d8: 26640163 beq s0,t1,33a <.L70> - dc: 040005b7 lui a1,0x4000 - e0: 8fcd or a5,a5,a1 - e2: 85b6 mv a1,a3 - -000000e4 <.L14>: - e4: 46ed li a3,27 - e6: 00b6de63 bge a3,a1,102 <.L15> - -000000ea <.LVL36>: - ea: 00160793 add a5,a2,1 - -000000ee <.L11>: - ee: 0077f693 and a3,a5,7 - f2: d6bd beqz a3,60 <.L47> - f4: 00f7f693 and a3,a5,15 - f8: 4611 li a2,4 - fa: f6c683e3 beq a3,a2,60 <.L47> - fe: 0791 add a5,a5,4 # 7f800004 <.LLST21+0x7f7ff59f> - 100: b785 j 60 <.L47> - -00000102 <.L15>: - 102: 02000693 li a3,32 - 106: 8e8d sub a3,a3,a1 - 108: 00b7d533 srl a0,a5,a1 - -0000010c <.LVL40>: - 10c: 00d797b3 sll a5,a5,a3 - -00000110 <.LVL41>: - 110: 00f037b3 snez a5,a5 - -00000114 <.LVL42>: - 114: 8fc9 or a5,a5,a0 - -00000116 <.LVL43>: - 116: 97b2 add a5,a5,a2 - -00000118 <.L16>: - 118: 040006b7 lui a3,0x4000 - 11c: 8efd and a3,a3,a5 - 11e: dae1 beqz a3,ee <.L11> - -00000120 <.LVL45>: - 120: 0405 add s0,s0,1 - -00000122 <.LVL46>: - 122: 0ff00693 li a3,255 - -00000126 <.LBB25>: - 126: 4481 li s1,0 - -00000128 <.LBB26>: - 128: f4d40de3 beq s0,a3,82 <.L25> - -0000012c <.L13>: - 12c: 7e0006b7 lui a3,0x7e000 - 130: 0017f613 and a2,a5,1 - 134: 16fd add a3,a3,-1 # 7dffffff <.LLST21+0x7dfff59a> - 136: 8385 srl a5,a5,0x1 - 138: 8ff5 and a5,a5,a3 - 13a: 8fd1 or a5,a5,a2 - 13c: bf4d j ee <.L11> - -0000013e <.L9>: - 13e: c6a9 beqz a3,188 <.L17> - 140: 408505b3 sub a1,a0,s0 - -00000144 <.LVL49>: - 144: c409 beqz s0,14e <.L53> - 146: 040006b7 lui a3,0x4000 - 14a: 8e55 or a2,a2,a3 - 14c: a811 j 160 <.L21> - -0000014e <.L53>: - 14e: 842e mv s0,a1 - -00000150 <.L18>: - 150: de59 beqz a2,ee <.L11> - 152: fff40593 add a1,s0,-1 - -00000156 <.LVL52>: - 156: d1bd beqz a1,bc <.L131> - 158: 0ff00693 li a3,255 - 15c: f8d409e3 beq s0,a3,ee <.L11> - -00000160 <.L21>: - 160: 46ed li a3,27 - 162: 00b6d563 bge a3,a1,16c <.L22> - -00000166 <.LVL53>: - 166: 0785 add a5,a5,1 - -00000168 <.LBB27>: - 168: 842a mv s0,a0 - 16a: b751 j ee <.L11> - -0000016c <.L22>: - 16c: 02000693 li a3,32 - 170: 8e8d sub a3,a3,a1 - 172: 00d616b3 sll a3,a2,a3 - 176: 00b65333 srl t1,a2,a1 - 17a: 00d036b3 snez a3,a3 - -0000017e <.LVL56>: - 17e: 00d366b3 or a3,t1,a3 - -00000182 <.LVL57>: - 182: 97b6 add a5,a5,a3 - -00000184 <.LBB29>: - 184: 842a mv s0,a0 - -00000186 <.LBB30>: - 186: bf49 j 118 <.L16> - -00000188 <.L17>: - 188: 00140693 add a3,s0,1 - 18c: 0fe6f593 and a1,a3,254 - 190: e195 bnez a1,1b4 <.L23> - 192: ec11 bnez s0,1ae <.L24> - -00000194 <.LVL60>: - 194: de29 beqz a2,ee <.L11> - 196: 1a078263 beqz a5,33a <.L70> - 19a: 97b2 add a5,a5,a2 - -0000019c <.LVL61>: - 19c: 040006b7 lui a3,0x4000 - 1a0: 8efd and a3,a3,a5 - 1a2: d6b1 beqz a3,ee <.L11> - 1a4: fc0006b7 lui a3,0xfc000 - 1a8: 16fd add a3,a3,-1 # fbffffff <.LLST21+0xfbfff59a> - 1aa: 8ff5 and a5,a5,a3 - -000001ac <.LVL62>: - 1ac: bf31 j c8 <.L126> - -000001ae <.L24>: - 1ae: d215 beqz a2,d2 <.L125> - -000001b0 <.L42>: - 1b0: d385 beqz a5,d0 <.L73> - 1b2: a205 j 2d2 <.L72> - -000001b4 <.L23>: - 1b4: 0ff00593 li a1,255 - 1b8: 18b68e63 beq a3,a1,354 <.L60> - 1bc: 963e add a2,a2,a5 - -000001be <.LVL65>: - 1be: 00165793 srl a5,a2,0x1 - -000001c2 <.L127>: - 1c2: 8436 mv s0,a3 - -000001c4 <.LVL67>: - 1c4: b72d j ee <.L11> - -000001c6 <.L8>: - 1c6: 06d05b63 blez a3,23c <.L26> - -000001ca <.LVL69>: - 1ca: e531 bnez a0,216 <.L27> - 1cc: 16078563 beqz a5,336 <.L62> - 1d0: fff68593 add a1,a3,-1 - -000001d4 <.LVL70>: - 1d4: e589 bnez a1,1de <.L28> - 1d6: 40f607b3 sub a5,a2,a5 - -000001da <.L123>: - 1da: 4405 li s0,1 - -000001dc <.LBB36>: - 1dc: a025 j 204 <.L29> - -000001de <.L28>: - 1de: ee6689e3 beq a3,t1,d0 <.L73> - -000001e2 <.L30>: - 1e2: 456d li a0,27 - -000001e4 <.LVL74>: - 1e4: 4685 li a3,1 - 1e6: 00b54d63 blt a0,a1,200 <.L31> - 1ea: 02000693 li a3,32 - 1ee: 8e8d sub a3,a3,a1 - 1f0: 00b7d533 srl a0,a5,a1 - 1f4: 00d797b3 sll a5,a5,a3 - -000001f8 <.LVL75>: - 1f8: 00f037b3 snez a5,a5 - 1fc: 00f566b3 or a3,a0,a5 - -00000200 <.L31>: - 200: 40d607b3 sub a5,a2,a3 - -00000204 <.L29>: - 204: 040004b7 lui s1,0x4000 - 208: 0097f6b3 and a3,a5,s1 - 20c: ee0681e3 beqz a3,ee <.L11> - -00000210 <.LBB18>: - 210: 14fd add s1,s1,-1 # 3ffffff <.LLST21+0x3fff59a> - 212: 8cfd and s1,s1,a5 - -00000214 <.LVL78>: - 214: a8f1 j 2f0 <.L44> - -00000216 <.L27>: - 216: 12640263 beq s0,t1,33a <.L70> - 21a: 040005b7 lui a1,0x4000 - 21e: 8fcd or a5,a5,a1 - 220: 85b6 mv a1,a3 - 222: b7c1 j 1e2 <.L30> - -00000224 <.L118>: - 224: cab5 beqz a3,298 <.L32> - -00000226 <.LVL82>: - 226: c805 beqz s0,256 <.L66> - 228: 0ff00413 li s0,255 - -0000022c <.LVL83>: - 22c: 872e mv a4,a1 - -0000022e <.LVL84>: - 22e: b5c1 j ee <.L11> - -00000230 <.L119>: - 230: c6a5 beqz a3,298 <.L32> - -00000232 <.LVL86>: - 232: c415 beqz s0,25e <.L67> - 234: 0ff00413 li s0,255 - -00000238 <.LVL87>: - 238: 8716 mv a4,t0 - -0000023a <.LVL88>: - 23a: b51d j 60 <.L47> - -0000023c <.L26>: - 23c: ceb1 beqz a3,298 <.L32> - 23e: 408505b3 sub a1,a0,s0 - -00000242 <.LVL90>: - 242: e431 bnez s0,28e <.L34> - 244: 8716 mv a4,t0 - -00000246 <.LVL91>: - 246: 842e mv s0,a1 - -00000248 <.L33>: - 248: ea0603e3 beqz a2,ee <.L11> - 24c: fff40593 add a1,s0,-1 - -00000250 <.LVL93>: - 250: e989 bnez a1,262 <.L35> - 252: 8f91 sub a5,a5,a2 - -00000254 <.LVL94>: - 254: b759 j 1da <.L123> - -00000256 <.L66>: - 256: 872e mv a4,a1 - -00000258 <.L122>: - 258: 0ff00413 li s0,255 - -0000025c <.LVL97>: - 25c: b7f5 j 248 <.L33> - -0000025e <.L67>: - 25e: 8716 mv a4,t0 - -00000260 <.LVL99>: - 260: bfe5 j 258 <.L122> - -00000262 <.L35>: - 262: 0ff00693 li a3,255 - 266: e8d404e3 beq s0,a3,ee <.L11> - -0000026a <.L36>: - 26a: 436d li t1,27 - 26c: 4685 li a3,1 - 26e: 00b34d63 blt t1,a1,288 <.L37> - 272: 02000693 li a3,32 - 276: 8e8d sub a3,a3,a1 - 278: 00d616b3 sll a3,a2,a3 - 27c: 00b65333 srl t1,a2,a1 - 280: 00d036b3 snez a3,a3 - 284: 00d366b3 or a3,t1,a3 - -00000288 <.L37>: - 288: 8f95 sub a5,a5,a3 - -0000028a <.LBB37>: - 28a: 842a mv s0,a0 - -0000028c <.LBB38>: - 28c: bfa5 j 204 <.L29> - -0000028e <.L34>: - 28e: 04000737 lui a4,0x4000 - -00000292 <.LVL104>: - 292: 8e59 or a2,a2,a4 - 294: 8716 mv a4,t0 - 296: bfd1 j 26a <.L36> - -00000298 <.L32>: - 298: 00140693 add a3,s0,1 - 29c: 0fe6f693 and a3,a3,254 - 2a0: ee9d bnez a3,2de <.L38> - 2a2: e01d bnez s0,2c8 <.L39> - -000002a4 <.LVL107>: - 2a4: e601 bnez a2,2ac <.L40> - -000002a6 <.LVL108>: - 2a6: cbdd beqz a5,35c <.L69> - -000002a8 <.L128>: - 2a8: 8716 mv a4,t0 - -000002aa <.LVL110>: - 2aa: b591 j ee <.L11> - -000002ac <.L40>: - 2ac: c7d9 beqz a5,33a <.L70> - 2ae: 40f604b3 sub s1,a2,a5 - -000002b2 <.LVL112>: - 2b2: 040006b7 lui a3,0x4000 - 2b6: 8ee5 and a3,a3,s1 - 2b8: c299 beqz a3,2be <.L41> - 2ba: 8f91 sub a5,a5,a2 - -000002bc <.LVL113>: - 2bc: b7f5 j 2a8 <.L128> - -000002be <.L41>: - 2be: 87a6 mv a5,s1 - -000002c0 <.LVL115>: - 2c0: e20497e3 bnez s1,ee <.L11> - -000002c4 <.L129>: - 2c4: 4701 li a4,0 - 2c6: bb75 j 82 <.L25> - -000002c8 <.L39>: - 2c8: ee0614e3 bnez a2,1b0 <.L42> - 2cc: 8716 mv a4,t0 - -000002ce <.LVL118>: - 2ce: e00792e3 bnez a5,d2 <.L125> - -000002d2 <.L72>: - 2d2: 4701 li a4,0 - -000002d4 <.LBB40>: - 2d4: 0ff00413 li s0,255 - -000002d8 <.LBB41>: - 2d8: 004004b7 lui s1,0x400 - 2dc: b35d j 82 <.L25> - -000002de <.L38>: - 2de: 40f604b3 sub s1,a2,a5 - -000002e2 <.LVL121>: - 2e2: 040006b7 lui a3,0x4000 - 2e6: 8ee5 and a3,a3,s1 - 2e8: ce95 beqz a3,324 <.L43> - 2ea: 40c784b3 sub s1,a5,a2 - -000002ee <.LVL122>: - 2ee: 8716 mv a4,t0 - -000002f0 <.L44>: - 2f0: 8526 mv a0,s1 - 2f2: c03a sw a4,0(sp) - -000002f4 <.LVL124>: - 2f4: 00000097 auipc ra,0x0 - 2f8: 000080e7 jalr ra # 2f4 <.LVL124> - -000002fc <.LVL125>: - 2fc: 156d add a0,a0,-5 - 2fe: 4702 lw a4,0(sp) - 300: 00a494b3 sll s1,s1,a0 - 304: 02854363 blt a0,s0,32a <.L45> - 308: 8d01 sub a0,a0,s0 - -0000030a <.LVL128>: - 30a: 0505 add a0,a0,1 - -0000030c <.LVL129>: - 30c: 02000693 li a3,32 - 310: 8e89 sub a3,a3,a0 - 312: 00a4d7b3 srl a5,s1,a0 - 316: 00d494b3 sll s1,s1,a3 - -0000031a <.LVL130>: - 31a: 009034b3 snez s1,s1 - 31e: 8fc5 or a5,a5,s1 - -00000320 <.LVL131>: - 320: 4401 li s0,0 - 322: b3f1 j ee <.L11> - -00000324 <.L43>: - 324: f4f1 bnez s1,2f0 <.L44> - 326: 4401 li s0,0 - -00000328 <.LVL133>: - 328: bf71 j 2c4 <.L129> - -0000032a <.L45>: - 32a: fc0007b7 lui a5,0xfc000 - 32e: 17fd add a5,a5,-1 # fbffffff <.LLST21+0xfbfff59a> - 330: 8c09 sub s0,s0,a0 - 332: 8fe5 and a5,a5,s1 - -00000334 <.LVL136>: - 334: bb6d j ee <.L11> - -00000336 <.L62>: - 336: 87b2 mv a5,a2 - -00000338 <.LVL138>: - 338: b569 j 1c2 <.L127> - -0000033a <.L70>: - 33a: 87b2 mv a5,a2 - -0000033c <.LVL140>: - 33c: bb4d j ee <.L11> - -0000033e <.L48>: - 33e: 0037d493 srl s1,a5,0x3 - -00000342 <.LVL142>: - 342: 0ff00793 li a5,255 - 346: d2f41ee3 bne s0,a5,82 <.L25> - 34a: d2048ce3 beqz s1,82 <.L25> - 34e: 004004b7 lui s1,0x400 - -00000352 <.LVL143>: - 352: bf8d j 2c4 <.L129> - -00000354 <.L60>: - 354: 0ff00413 li s0,255 - -00000358 <.LBB46>: - 358: 4481 li s1,0 - 35a: b325 j 82 <.L25> - -0000035c <.L69>: - 35c: 4481 li s1,0 - 35e: b79d j 2c4 <.L129> - -unordsf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__unordsf2>: - 0: 008007b7 lui a5,0x800 - 4: 17fd add a5,a5,-1 # 7fffff <.LASF9+0x7ffe6c> - 6: 00a7f733 and a4,a5,a0 - -0000000a <.LBB3>: - a: 815d srl a0,a0,0x17 - -0000000c <.LBB4>: - c: 8fed and a5,a5,a1 - -0000000e <.LBE4>: - e: 0ff57513 zext.b a0,a0 - 12: 81dd srl a1,a1,0x17 - -00000014 <.LVL4>: - 14: 0ff00693 li a3,255 - 18: 0ff5f593 zext.b a1,a1 - -0000001c <.LBB5>: - 1c: 00d51463 bne a0,a3,24 <.L2> - 20: 4505 li a0,1 - 22: eb01 bnez a4,32 <.L1> - -00000024 <.L2>: - 24: 0ff00713 li a4,255 - -00000028 <.LVL6>: - 28: 4501 li a0,0 - 2a: 00e59463 bne a1,a4,32 <.L1> - 2e: 00f03533 snez a0,a5 - -00000032 <.L1>: - 32: 8082 ret - -fixsfsi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixsfsi>: - 0: 00800637 lui a2,0x800 - 4: 01755713 srl a4,a0,0x17 - 8: fff60793 add a5,a2,-1 # 7fffff <.LASF18+0x7ffe6f> - c: 0ff77713 zext.b a4,a4 - -00000010 <.LBE2>: - 10: 07e00593 li a1,126 - -00000014 <.LBB3>: - 14: 8fe9 and a5,a5,a0 - -00000016 <.LVL1>: - 16: 01f55693 srl a3,a0,0x1f - -0000001a <.LBE3>: - 1a: 04e5d063 bge a1,a4,5a <.L6> - 1e: 09d00593 li a1,157 - 22: 00e5d863 bge a1,a4,32 <.L3> - -00000026 <.LVL3>: - 26: 80000537 lui a0,0x80000 - -0000002a <.LVL4>: - 2a: fff54513 not a0,a0 - 2e: 9536 add a0,a0,a3 - -00000030 <.LVL5>: - 30: 8082 ret - -00000032 <.L3>: - 32: 00c7e533 or a0,a5,a2 - -00000036 <.LVL7>: - 36: 09500793 li a5,149 - 3a: 00e7da63 bge a5,a4,4e <.L4> - -0000003e <.LVL8>: - 3e: f6a70713 add a4,a4,-150 - -00000042 <.LVL9>: - 42: 00e51533 sll a0,a0,a4 - -00000046 <.L5>: - 46: ca99 beqz a3,5c <.L2> - 48: 40a00533 neg a0,a0 - 4c: 8082 ret - -0000004e <.L4>: - 4e: 09600793 li a5,150 - 52: 8f99 sub a5,a5,a4 - 54: 00f55533 srl a0,a0,a5 - -00000058 <.LVL13>: - 58: b7fd j 46 <.L5> - -0000005a <.L6>: - 5a: 4501 li a0,0 - -0000005c <.L2>: - 5c: 8082 ret - -fixunssfsi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixunssfsi>: - 0: 01755793 srl a5,a0,0x17 - 4: 00800637 lui a2,0x800 - 8: fff60693 add a3,a2,-1 # 7fffff <.LASF17+0x7ffe73> - c: 0ff7f793 zext.b a5,a5 - -00000010 <.LBE2>: - 10: 07e00593 li a1,126 - -00000014 <.LBB3>: - 14: 8ee9 and a3,a3,a0 - -00000016 <.LVL1>: - 16: 01f55713 srl a4,a0,0x1f - -0000001a <.LBE3>: - 1a: 4501 li a0,0 - -0000001c <.LVL3>: - 1c: 02f5da63 bge a1,a5,50 <.L1> - 20: eb05 bnez a4,50 <.L1> - 22: 09e00713 li a4,158 - -00000026 <.LVL4>: - 26: 557d li a0,-1 - 28: 02f74463 blt a4,a5,50 <.L1> - -0000002c <.LBB4>: - 2c: 09500713 li a4,149 - 30: 00c6e533 or a0,a3,a2 - -00000034 <.LVL6>: - 34: 00f75763 bge a4,a5,42 <.L3> - -00000038 <.LVL7>: - 38: f6a78793 add a5,a5,-150 - -0000003c <.LVL8>: - 3c: 00f51533 sll a0,a0,a5 - -00000040 <.LVL9>: - 40: 8082 ret - -00000042 <.L3>: - 42: 09600713 li a4,150 - 46: 40f707b3 sub a5,a4,a5 - -0000004a <.LVL11>: - 4a: 00f55533 srl a0,a0,a5 - -0000004e <.LVL12>: - 4e: 8082 ret - -00000050 <.L1>: - 50: 8082 ret - -floatsisf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatsisf>: - 0: 1151 add sp,sp,-12 - 2: c406 sw ra,8(sp) - 4: c222 sw s0,4(sp) - 6: c026 sw s1,0(sp) - -00000008 <.LBB10>: - 8: c945 beqz a0,b8 <.L9> - -0000000a <.LBB3>: - a: 41f55793 sra a5,a0,0x1f - e: 00a7c433 xor s0,a5,a0 - 12: 8c1d sub s0,s0,a5 - 14: 01f55493 srl s1,a0,0x1f - -00000018 <.LBB4>: - 18: 8522 mv a0,s0 - -0000001a <.LVL3>: - 1a: 00000097 auipc ra,0x0 - 1e: 000080e7 jalr ra # 1a <.LVL3> - -00000022 <.LVL4>: - 22: 87aa mv a5,a0 - -00000024 <.LVL5>: - 24: 09e00513 li a0,158 - -00000028 <.LVL6>: - 28: 8d1d sub a0,a0,a5 - -0000002a <.LBE4>: - 2a: 09600713 li a4,150 - 2e: 02a74363 blt a4,a0,54 <.L4> - -00000032 <.LVL8>: - 32: 4721 li a4,8 - 34: 08e78563 beq a5,a4,be <.L10> - 38: 17e1 add a5,a5,-8 - -0000003a <.LVL9>: - 3a: 00f41433 sll s0,s0,a5 - -0000003e <.L2>: - 3e: 0426 sll s0,s0,0x9 - -00000040 <.LVL11>: - 40: 8025 srl s0,s0,0x9 - 42: 055e sll a0,a0,0x17 - -00000044 <.LBE11>: - 44: 40a2 lw ra,8(sp) - -00000046 <.LBB12>: - 46: 8d41 or a0,a0,s0 - -00000048 <.LBE12>: - 48: 4412 lw s0,4(sp) - -0000004a <.LBB13>: - 4a: 04fe sll s1,s1,0x1f - -0000004c <.LBE13>: - 4c: 8d45 or a0,a0,s1 - -0000004e <.LVL14>: - 4e: 4482 lw s1,0(sp) - 50: 0131 add sp,sp,12 - 52: 8082 ret - -00000054 <.L4>: - 54: 09900713 li a4,153 - 58: 04a75863 bge a4,a0,a8 <.L5> - 5c: 4695 li a3,5 - 5e: 01b78713 add a4,a5,27 - 62: 00e41733 sll a4,s0,a4 - 66: 8e9d sub a3,a3,a5 - 68: 00d456b3 srl a3,s0,a3 - 6c: 00e03733 snez a4,a4 - 70: 00e6e433 or s0,a3,a4 - -00000074 <.L6>: - 74: fc000737 lui a4,0xfc000 - 78: 177d add a4,a4,-1 # fbffffff <.LASF14+0xfbfffdd1> - -0000007a <.LBB5>: - 7a: 00747693 and a3,s0,7 - -0000007e <.LBE5>: - 7e: 8f61 and a4,a4,s0 - -00000080 <.LBB6>: - 80: c691 beqz a3,8c <.L7> - -00000082 <.LVL18>: - 82: 883d and s0,s0,15 - 84: 4691 li a3,4 - 86: 00d40363 beq s0,a3,8c <.L7> - 8a: 0711 add a4,a4,4 - -0000008c <.L7>: - 8c: 040006b7 lui a3,0x4000 - 90: 8ef9 and a3,a3,a4 - 92: ca81 beqz a3,a2 <.L8> - 94: fc0006b7 lui a3,0xfc000 - 98: 16fd add a3,a3,-1 # fbffffff <.LASF14+0xfbfffdd1> - 9a: 09f00513 li a0,159 - -0000009e <.LVL20>: - 9e: 8f75 and a4,a4,a3 - a0: 8d1d sub a0,a0,a5 - -000000a2 <.L8>: - a2: 00375413 srl s0,a4,0x3 - -000000a6 <.LVL23>: - a6: bf61 j 3e <.L2> - -000000a8 <.L5>: - a8: 4695 li a3,5 - aa: ffb78713 add a4,a5,-5 - ae: fcd783e3 beq a5,a3,74 <.L6> - b2: 00e41433 sll s0,s0,a4 - -000000b6 <.LVL25>: - b6: bf7d j 74 <.L6> - -000000b8 <.L9>: - b8: 4481 li s1,0 - ba: 4401 li s0,0 - bc: b749 j 3e <.L2> - -000000be <.L10>: - be: 09600513 li a0,150 - -000000c2 <.LVL28>: - c2: bfb5 j 3e <.L2> - -floatunsisf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatunsisf>: - 0: 1151 add sp,sp,-12 - 2: c222 sw s0,4(sp) - 4: c406 sw ra,8(sp) - 6: 842a mv s0,a0 - -00000008 <.LBB9>: - 8: 4781 li a5,0 - a: c115 beqz a0,2e <.L2> - -0000000c <.LBB3>: - c: 00000097 auipc ra,0x0 - 10: 000080e7 jalr ra # c <.LBB3> - -00000014 <.LVL2>: - 14: 09e00793 li a5,158 - 18: 8f89 sub a5,a5,a0 - -0000001a <.LBE4>: - 1a: 09600713 li a4,150 - 1e: 02f74163 blt a4,a5,40 <.L3> - -00000022 <.LVL4>: - 22: 4721 li a4,8 - 24: 08e50063 beq a0,a4,a4 <.L9> - 28: 1561 add a0,a0,-8 - -0000002a <.LVL5>: - 2a: 00a41433 sll s0,s0,a0 - -0000002e <.L2>: - 2e: 0426 sll s0,s0,0x9 - -00000030 <.LVL7>: - 30: 8025 srl s0,s0,0x9 - 32: 01779513 sll a0,a5,0x17 - -00000036 <.LBE10>: - 36: 40a2 lw ra,8(sp) - 38: 8d41 or a0,a0,s0 - -0000003a <.LVL9>: - 3a: 4412 lw s0,4(sp) - 3c: 0131 add sp,sp,12 - 3e: 8082 ret - -00000040 <.L3>: - 40: 09900713 li a4,153 - 44: 04f75863 bge a4,a5,94 <.L4> - 48: 01b50693 add a3,a0,27 - 4c: 4715 li a4,5 - 4e: 00d416b3 sll a3,s0,a3 - 52: 8f09 sub a4,a4,a0 - 54: 00d036b3 snez a3,a3 - 58: 00e45733 srl a4,s0,a4 - 5c: 00e6e433 or s0,a3,a4 - -00000060 <.L5>: - 60: fc000737 lui a4,0xfc000 - 64: 177d add a4,a4,-1 # fbffffff <.LASF2+0xfbfffdd7> - -00000066 <.LBB5>: - 66: 00747693 and a3,s0,7 - -0000006a <.LBE5>: - 6a: 8f61 and a4,a4,s0 - -0000006c <.LBB6>: - 6c: c691 beqz a3,78 <.L6> - -0000006e <.LVL13>: - 6e: 883d and s0,s0,15 - 70: 4691 li a3,4 - 72: 00d40363 beq s0,a3,78 <.L6> - 76: 0711 add a4,a4,4 - -00000078 <.L6>: - 78: 040006b7 lui a3,0x4000 - 7c: 8ef9 and a3,a3,a4 - 7e: ca81 beqz a3,8e <.L7> - 80: fc0007b7 lui a5,0xfc000 - -00000084 <.LVL15>: - 84: 17fd add a5,a5,-1 # fbffffff <.LASF2+0xfbfffdd7> - 86: 8f7d and a4,a4,a5 - 88: 09f00793 li a5,159 - 8c: 8f89 sub a5,a5,a0 - -0000008e <.L7>: - 8e: 00375413 srl s0,a4,0x3 - -00000092 <.LVL18>: - 92: bf71 j 2e <.L2> - -00000094 <.L4>: - 94: 4695 li a3,5 - 96: ffb50713 add a4,a0,-5 - 9a: fcd503e3 beq a0,a3,60 <.L5> - 9e: 00e41433 sll s0,s0,a4 - -000000a2 <.LVL20>: - a2: bf7d j 60 <.L5> - -000000a4 <.L9>: - a4: 09600793 li a5,150 - -000000a8 <.LVL22>: - a8: b759 j 2e <.L2> - -fixsfdi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixsfdi>: - 0: 00800737 lui a4,0x800 - 4: 01755613 srl a2,a0,0x17 - 8: fff70793 add a5,a4,-1 # 7fffff <.LASF18+0x7ffe65> - c: 0ff67613 zext.b a2,a2 - -00000010 <.LBE2>: - 10: 07e00693 li a3,126 - -00000014 <.LBB3>: - 14: 8fe9 and a5,a5,a0 - -00000016 <.LBE3>: - 16: 06c6d863 bge a3,a2,86 <.L6> - 1a: 1151 add sp,sp,-12 - 1c: c222 sw s0,4(sp) - 1e: c406 sw ra,8(sp) - 20: 0bd00693 li a3,189 - 24: 01f55413 srl s0,a0,0x1f - 28: 02c6d263 bge a3,a2,4c <.L3> - -0000002c <.LVL2>: - 2c: 4505 li a0,1 - -0000002e <.LVL3>: - 2e: 8d01 sub a0,a0,s0 - 30: 41f55713 sra a4,a0,0x1f - 34: 800005b7 lui a1,0x80000 - 38: 00a037b3 snez a5,a0 - -0000003c <.LVL4>: - 3c: 8d99 sub a1,a1,a4 - 3e: 40a00533 neg a0,a0 - 42: 8d9d sub a1,a1,a5 - -00000044 <.L2>: - 44: 40a2 lw ra,8(sp) - 46: 4412 lw s0,4(sp) - 48: 0131 add sp,sp,12 - 4a: 8082 ret - -0000004c <.L3>: - 4c: 00e7e533 or a0,a5,a4 - -00000050 <.LVL7>: - 50: 09500793 li a5,149 - 54: 02c7d263 bge a5,a2,78 <.L4> - 58: f6a60613 add a2,a2,-150 - -0000005c <.LVL9>: - 5c: 4581 li a1,0 - 5e: 00000097 auipc ra,0x0 - 62: 000080e7 jalr ra # 5e <.LVL9+0x2> - -00000066 <.L5>: - 66: dc79 beqz s0,44 <.L2> - 68: 00a037b3 snez a5,a0 - 6c: 40b005b3 neg a1,a1 - -00000070 <.LVL11>: - 70: 8d9d sub a1,a1,a5 - 72: 40a00533 neg a0,a0 - 76: b7f9 j 44 <.L2> - -00000078 <.L4>: - 78: 09600793 li a5,150 - 7c: 8f91 sub a5,a5,a2 - 7e: 00f55533 srl a0,a0,a5 - -00000082 <.LVL14>: - 82: 4581 li a1,0 - 84: b7cd j 66 <.L5> - -00000086 <.L6>: - 86: 4501 li a0,0 - -00000088 <.LVL17>: - 88: 4581 li a1,0 - -0000008a <.LVL18>: - 8a: 8082 ret - -fixunssfdi.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__fixunssfdi>: - 0: 00800737 lui a4,0x800 - 4: 01755613 srl a2,a0,0x17 - 8: fff70793 add a5,a4,-1 # 7fffff <.LASF17+0x7ffe69> - c: 0ff67613 zext.b a2,a2 - -00000010 <.LBE2>: - 10: 07e00693 li a3,126 - -00000014 <.LBB3>: - 14: 8fe9 and a5,a5,a0 - -00000016 <.LBE3>: - 16: 04c6d163 bge a3,a2,58 <.L4> - 1a: 817d srl a0,a0,0x1f - -0000001c <.LVL2>: - 1c: ed15 bnez a0,58 <.L4> - 1e: 0be00693 li a3,190 - 22: 02c6cd63 blt a3,a2,5c <.L6> - -00000026 <.LBB4>: - 26: 00e7e533 or a0,a5,a4 - -0000002a <.LVL4>: - 2a: 09500793 li a5,149 - 2e: 00c7de63 bge a5,a2,4a <.L3> - -00000032 <.LBE4>: - 32: 1151 add sp,sp,-12 - -00000034 <.LBB5>: - 34: f6a60613 add a2,a2,-150 - -00000038 <.LVL6>: - 38: 4581 li a1,0 - -0000003a <.LBE5>: - 3a: c406 sw ra,8(sp) - -0000003c <.LBB6>: - 3c: 00000097 auipc ra,0x0 - 40: 000080e7 jalr ra # 3c <.LBB6> - -00000044 <.LBE6>: - 44: 40a2 lw ra,8(sp) - 46: 0131 add sp,sp,12 - 48: 8082 ret - -0000004a <.L3>: - 4a: 09600793 li a5,150 - 4e: 8f91 sub a5,a5,a2 - 50: 00f55533 srl a0,a0,a5 - -00000054 <.L11>: - 54: 4581 li a1,0 - 56: 8082 ret - -00000058 <.L4>: - 58: 4501 li a0,0 - 5a: bfed j 54 <.L11> - -0000005c <.L6>: - 5c: 557d li a0,-1 - -0000005e <.LVL12>: - 5e: 55fd li a1,-1 - -00000060 <.LVL13>: - 60: 8082 ret - -floatdisf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatdisf>: - 0: 1111 add sp,sp,-28 - 2: cc06 sw ra,24(sp) - 4: ca22 sw s0,20(sp) - 6: c826 sw s1,16(sp) - -00000008 <.LBB11>: - 8: 00b567b3 or a5,a0,a1 - c: 10078863 beqz a5,11c <.L13> - -00000010 <.LBB3>: - 10: 01f5d793 srl a5,a1,0x1f - 14: c03e sw a5,0(sp) - 16: 842a mv s0,a0 - 18: 86ae mv a3,a1 - -0000001a <.LVL1>: - 1a: 0005d963 bgez a1,2c <.L4> - -0000001e <.LVL2>: - 1e: 00a037b3 snez a5,a0 - -00000022 <.LVL3>: - 22: 40b006b3 neg a3,a1 - 26: 8e9d sub a3,a3,a5 - 28: 40a00433 neg s0,a0 - -0000002c <.L4>: - 2c: c2d9 beqz a3,b2 <.L6> - 2e: 8536 mv a0,a3 - -00000030 <.LVL4>: - 30: c236 sw a3,4(sp) - 32: 00000097 auipc ra,0x0 - 36: 000080e7 jalr ra # 32 <.LVL4+0x2> - -0000003a <.LVL5>: - 3a: 4692 lw a3,4(sp) - 3c: 0be00713 li a4,190 - 40: 84aa mv s1,a0 - -00000042 <.LVL6>: - 42: 8f09 sub a4,a4,a0 - -00000044 <.L7>: - 44: 02500613 li a2,37 - 48: 8e05 sub a2,a2,s1 - 4a: 85b6 mv a1,a3 - 4c: 8522 mv a0,s0 - 4e: c63a sw a4,12(sp) - 50: c436 sw a3,8(sp) - 52: 00000097 auipc ra,0x0 - 56: 000080e7 jalr ra # 52 <.L7+0xe> - -0000005a <.LVL8>: - 5a: 46a2 lw a3,8(sp) - 5c: c22a sw a0,4(sp) - 5e: 01b48613 add a2,s1,27 - 62: 8522 mv a0,s0 - 64: 85b6 mv a1,a3 - 66: 00000097 auipc ra,0x0 - 6a: 000080e7 jalr ra # 66 <.LVL8+0xc> - -0000006e <.LVL9>: - 6e: 4292 lw t0,4(sp) - 70: 00b567b3 or a5,a0,a1 - 74: 4732 lw a4,12(sp) - 76: 00f037b3 snez a5,a5 - 7a: 0057e7b3 or a5,a5,t0 - -0000007e <.L10>: - 7e: fc0006b7 lui a3,0xfc000 - 82: 16fd add a3,a3,-1 # fbffffff <.LASF25+0xfbfffdc1> - -00000084 <.LBB5>: - 84: 0077f613 and a2,a5,7 - -00000088 <.LBE5>: - 88: 8efd and a3,a3,a5 - -0000008a <.LBB6>: - 8a: c611 beqz a2,96 <.L11> - -0000008c <.LVL12>: - 8c: 8bbd and a5,a5,15 - 8e: 4611 li a2,4 - 90: 00c78363 beq a5,a2,96 <.L11> - 94: 0691 add a3,a3,4 - -00000096 <.L11>: - 96: 040007b7 lui a5,0x4000 - 9a: 8ff5 and a5,a5,a3 - 9c: cb81 beqz a5,ac <.L12> - 9e: fc0007b7 lui a5,0xfc000 - a2: 17fd add a5,a5,-1 # fbffffff <.LASF25+0xfbfffdc1> - a4: 0bf00713 li a4,191 - a8: 8efd and a3,a3,a5 - aa: 8f05 sub a4,a4,s1 - -000000ac <.L12>: - ac: 0036d793 srl a5,a3,0x3 - -000000b0 <.LVL16>: - b0: a815 j e4 <.L2> - -000000b2 <.L6>: - b2: 8522 mv a0,s0 - -000000b4 <.LVL18>: - b4: c436 sw a3,8(sp) - b6: c222 sw s0,4(sp) - b8: 00000097 auipc ra,0x0 - bc: 000080e7 jalr ra # b8 <.LVL18+0x4> - -000000c0 <.LVL19>: - c0: 02050493 add s1,a0,32 - -000000c4 <.LVL20>: - c4: 0be00713 li a4,190 - c8: 8f05 sub a4,a4,s1 - -000000ca <.LBE7>: - ca: 09600613 li a2,150 - ce: 46a2 lw a3,8(sp) - d0: 87a2 mv a5,s0 - d2: 02e64663 blt a2,a4,fe <.L8> - -000000d6 <.LVL22>: - d6: 02800693 li a3,40 - da: 04d48563 beq s1,a3,124 <.L14> - de: 1561 add a0,a0,-8 - e0: 00a417b3 sll a5,s0,a0 - -000000e4 <.L2>: - e4: 07a6 sll a5,a5,0x9 - -000000e6 <.LVL24>: - e6: 83a5 srl a5,a5,0x9 - e8: 075e sll a4,a4,0x17 - -000000ea <.LVL25>: - ea: 8f5d or a4,a4,a5 - ec: 4782 lw a5,0(sp) - -000000ee <.LBE12>: - ee: 40e2 lw ra,24(sp) - f0: 4452 lw s0,20(sp) - -000000f2 <.LBB13>: - f2: 01f79513 sll a0,a5,0x1f - -000000f6 <.LBE13>: - f6: 44c2 lw s1,16(sp) - f8: 8d59 or a0,a0,a4 - -000000fa <.LVL27>: - fa: 0171 add sp,sp,28 - -000000fc <.LVL28>: - fc: 8082 ret - -000000fe <.L8>: - fe: 09900613 li a2,153 - 102: f4e641e3 blt a2,a4,44 <.L7> - -00000106 <.LVL30>: - 106: 02500693 li a3,37 - 10a: 156d add a0,a0,-5 - 10c: 00d48563 beq s1,a3,116 <.L15> - 110: 00a417b3 sll a5,s0,a0 - -00000114 <.LVL31>: - 114: b7ad j 7e <.L10> - -00000116 <.L15>: - 116: 09900713 li a4,153 - -0000011a <.LVL33>: - 11a: b795 j 7e <.L10> - -0000011c <.L13>: - 11c: 4781 li a5,0 - 11e: 4701 li a4,0 - 120: c002 sw zero,0(sp) - 122: b7c9 j e4 <.L2> - -00000124 <.L14>: - 124: 09600713 li a4,150 - -00000128 <.LVL36>: - 128: bf75 j e4 <.L2> - -floatundisf.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__floatundisf>: - 0: 1121 add sp,sp,-24 - 2: ca06 sw ra,20(sp) - 4: c822 sw s0,16(sp) - 6: c626 sw s1,12(sp) - 8: c02e sw a1,0(sp) - -0000000a <.LBB11>: - a: 00b567b3 or a5,a0,a1 - e: cff9 beqz a5,ec <.L11> - 10: 84aa mv s1,a0 - -00000012 <.LBB3>: - 12: cdb5 beqz a1,8e <.L4> - 14: 852e mv a0,a1 - -00000016 <.LVL2>: - 16: 00000097 auipc ra,0x0 - 1a: 000080e7 jalr ra # 16 <.LVL2> - -0000001e <.LVL3>: - 1e: 0be00713 li a4,190 - 22: 842a mv s0,a0 - -00000024 <.LVL4>: - 24: 8f09 sub a4,a4,a0 - -00000026 <.L5>: - 26: 4582 lw a1,0(sp) - 28: 01b40613 add a2,s0,27 - 2c: 8526 mv a0,s1 - 2e: c43a sw a4,8(sp) - -00000030 <.LVL6>: - 30: 00000097 auipc ra,0x0 - 34: 000080e7 jalr ra # 30 <.LVL6> - -00000038 <.LVL7>: - 38: 00b567b3 or a5,a0,a1 - 3c: 4582 lw a1,0(sp) - 3e: 02500613 li a2,37 - 42: 00f037b3 snez a5,a5 - 46: 8e01 sub a2,a2,s0 - 48: 8526 mv a0,s1 - 4a: c23e sw a5,4(sp) - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <.LVL7+0x14> - -00000054 <.LVL8>: - 54: 4792 lw a5,4(sp) - 56: 4722 lw a4,8(sp) - 58: 8fc9 or a5,a5,a0 - -0000005a <.L8>: - 5a: fc0006b7 lui a3,0xfc000 - 5e: 16fd add a3,a3,-1 # fbffffff <.LASF3+0xfbfffdc3> - -00000060 <.LBB5>: - 60: 0077f613 and a2,a5,7 - -00000064 <.LBE5>: - 64: 8efd and a3,a3,a5 - -00000066 <.LBB6>: - 66: c611 beqz a2,72 <.L9> - -00000068 <.LVL11>: - 68: 8bbd and a5,a5,15 - 6a: 4611 li a2,4 - 6c: 00c78363 beq a5,a2,72 <.L9> - 70: 0691 add a3,a3,4 - -00000072 <.L9>: - 72: 040007b7 lui a5,0x4000 - 76: 8ff5 and a5,a5,a3 - 78: cb81 beqz a5,88 <.L10> - 7a: fc0007b7 lui a5,0xfc000 - 7e: 17fd add a5,a5,-1 # fbffffff <.LASF3+0xfbfffdc3> - 80: 0bf00713 li a4,191 - 84: 8efd and a3,a3,a5 - 86: 8f01 sub a4,a4,s0 - -00000088 <.L10>: - 88: 0036d793 srl a5,a3,0x3 - -0000008c <.LVL15>: - 8c: a03d j ba <.L2> - -0000008e <.L4>: - 8e: c22a sw a0,4(sp) - 90: 00000097 auipc ra,0x0 - 94: 000080e7 jalr ra # 90 <.L4+0x2> - -00000098 <.LVL17>: - 98: 02050413 add s0,a0,32 - -0000009c <.LVL18>: - 9c: 0be00713 li a4,190 - a0: 8f01 sub a4,a4,s0 - -000000a2 <.LBE7>: - a2: 09600693 li a3,150 - a6: 87a6 mv a5,s1 - a8: 02e6c363 blt a3,a4,ce <.L6> - -000000ac <.LVL20>: - ac: 02800693 li a3,40 - b0: 04d40163 beq s0,a3,f2 <.L12> - b4: 1561 add a0,a0,-8 - b6: 00a497b3 sll a5,s1,a0 - -000000ba <.L2>: - ba: 40d2 lw ra,20(sp) - bc: 4442 lw s0,16(sp) - -000000be <.LBB13>: - be: 07a6 sll a5,a5,0x9 - -000000c0 <.LVL22>: - c0: 01771513 sll a0,a4,0x17 - c4: 83a5 srl a5,a5,0x9 - -000000c6 <.LBE13>: - c6: 44b2 lw s1,12(sp) - c8: 8d5d or a0,a0,a5 - -000000ca <.LVL24>: - ca: 0161 add sp,sp,24 - cc: 8082 ret - -000000ce <.L6>: - ce: 09900693 li a3,153 - d2: f4e6cae3 blt a3,a4,26 <.L5> - -000000d6 <.LVL26>: - d6: 02500693 li a3,37 - da: 156d add a0,a0,-5 - dc: 00d40563 beq s0,a3,e6 <.L13> - e0: 00a497b3 sll a5,s1,a0 - -000000e4 <.LVL27>: - e4: bf9d j 5a <.L8> - -000000e6 <.L13>: - e6: 09900713 li a4,153 - -000000ea <.LVL29>: - ea: bf85 j 5a <.L8> - -000000ec <.L11>: - ec: 4781 li a5,0 - ee: 4701 li a4,0 - f0: b7e9 j ba <.L2> - -000000f2 <.L12>: - f2: 09600713 li a4,150 - -000000f6 <.LVL32>: - f6: b7d1 j ba <.L2> - -extendsfdf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__extendsfdf2>: - 0: 01755713 srl a4,a0,0x17 - 4: 0ff77713 zext.b a4,a4 - -00000008 <.LBE2>: - 8: 1151 add sp,sp,-12 - a: 00170793 add a5,a4,1 - e: c222 sw s0,4(sp) - 10: c026 sw s1,0(sp) - -00000012 <.LBB3>: - 12: 00951413 sll s0,a0,0x9 - -00000016 <.LBE3>: - 16: c406 sw ra,8(sp) - 18: 0fe7f793 and a5,a5,254 - -0000001c <.LBB4>: - 1c: 8025 srl s0,s0,0x9 - -0000001e <.LVL1>: - 1e: 01f55493 srl s1,a0,0x1f - -00000022 <.LBE4>: - 22: c785 beqz a5,4a <.L2> - 24: 00345793 srl a5,s0,0x3 - 28: 38070713 add a4,a4,896 - -0000002c <.LVL3>: - 2c: 0476 sll s0,s0,0x1d - -0000002e <.L3>: - 2e: 07b2 sll a5,a5,0xc - -00000030 <.LBE7>: - 30: 40a2 lw ra,8(sp) - -00000032 <.LBB8>: - 32: 83b1 srl a5,a5,0xc - -00000034 <.LBE8>: - 34: 8522 mv a0,s0 - -00000036 <.LBB9>: - 36: 0752 sll a4,a4,0x14 - -00000038 <.LBE9>: - 38: 4412 lw s0,4(sp) - -0000003a <.LBB10>: - 3a: 04fe sll s1,s1,0x1f - -0000003c <.LVL8>: - 3c: 8f5d or a4,a4,a5 - 3e: 009767b3 or a5,a4,s1 - -00000042 <.LBE10>: - 42: 85be mv a1,a5 - 44: 4482 lw s1,0(sp) - 46: 0131 add sp,sp,12 - 48: 8082 ret - -0000004a <.L2>: - 4a: ef0d bnez a4,84 <.L4> - 4c: 4781 li a5,0 - 4e: d065 beqz s0,2e <.L3> - -00000050 <.LBB11>: - 50: 8522 mv a0,s0 - -00000052 <.LVL10>: - 52: 00000097 auipc ra,0x0 - 56: 000080e7 jalr ra # 52 <.LVL10> - -0000005a <.LVL11>: - 5a: 47a9 li a5,10 - 5c: 00a7ce63 blt a5,a0,78 <.L5> - 60: 47ad li a5,11 - 62: 8f89 sub a5,a5,a0 - 64: 01550713 add a4,a0,21 - 68: 00f457b3 srl a5,s0,a5 - -0000006c <.LVL12>: - 6c: 00e41433 sll s0,s0,a4 - -00000070 <.L6>: - 70: 38900713 li a4,905 - 74: 8f09 sub a4,a4,a0 - -00000076 <.LVL14>: - 76: bf65 j 2e <.L3> - -00000078 <.L5>: - 78: ff550793 add a5,a0,-11 - 7c: 00f417b3 sll a5,s0,a5 - -00000080 <.LVL16>: - 80: 4401 li s0,0 - -00000082 <.LVL17>: - 82: b7fd j 70 <.L6> - -00000084 <.L4>: - 84: 4781 li a5,0 - 86: c419 beqz s0,94 <.L11> - -00000088 <.LVL19>: - 88: 00345793 srl a5,s0,0x3 - -0000008c <.LVL20>: - 8c: 00080737 lui a4,0x80 - -00000090 <.LVL21>: - 90: 0476 sll s0,s0,0x1d - -00000092 <.LVL22>: - 92: 8fd9 or a5,a5,a4 - -00000094 <.L11>: - 94: 7ff00713 li a4,2047 - 98: bf59 j 2e <.L3> - -extendsftf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__extendsftf2>: - 0: 7139 add sp,sp,-64 - -00000002 <.LBB3>: - 2: 0175d793 srl a5,a1,0x17 - -00000006 <.LBE3>: - 6: dc22 sw s0,56(sp) - -00000008 <.LBB4>: - 8: 0ff7f793 zext.b a5,a5 - c: 00959413 sll s0,a1,0x9 - 10: 8025 srl s0,s0,0x9 - -00000012 <.LBE4>: - 12: 00178613 add a2,a5,1 - 16: da26 sw s1,52(sp) - 18: 02710693 add a3,sp,39 - 1c: de06 sw ra,60(sp) - 1e: c422 sw s0,8(sp) - 20: ca02 sw zero,20(sp) - 22: c802 sw zero,16(sp) - 24: c602 sw zero,12(sp) - 26: 0fe67613 and a2,a2,254 - 2a: 872a mv a4,a0 - 2c: 9ac1 and a3,a3,-16 - -0000002e <.LBB5>: - 2e: 01f5d493 srl s1,a1,0x1f - -00000032 <.LBE5>: - 32: c239 beqz a2,78 <.L2> - 34: 6611 lui a2,0x4 - 36: f8060613 add a2,a2,-128 # 3f80 <.LLST22+0x3c65> - 3a: 97b2 add a5,a5,a2 - -0000003c <.LBB6>: - 3c: 00745613 srl a2,s0,0x7 - 40: 0466 sll s0,s0,0x19 - -00000042 <.LVL4>: - 42: ca32 sw a2,20(sp) - -00000044 <.LVL5>: - 44: c822 sw s0,16(sp) - -00000046 <.LVL6>: - 46: c402 sw zero,8(sp) - -00000048 <.L3>: - 48: 4352 lw t1,20(sp) - 4a: 04be sll s1,s1,0xf - -0000004c <.LVL8>: - 4c: 8cdd or s1,s1,a5 - 4e: 00969723 sh s1,14(a3) - 52: 00669623 sh t1,12(a3) - 56: 4522 lw a0,8(sp) - 58: 45b2 lw a1,12(sp) - 5a: 4642 lw a2,16(sp) - 5c: 46dc lw a5,12(a3) - -0000005e <.LBE7>: - 5e: 50f2 lw ra,60(sp) - 60: 5462 lw s0,56(sp) - -00000062 <.LBB8>: - 62: c288 sw a0,0(a3) - -00000064 <.LBE8>: - 64: c308 sw a0,0(a4) - -00000066 <.LBB9>: - 66: c2cc sw a1,4(a3) - 68: c690 sw a2,8(a3) - -0000006a <.LBE9>: - 6a: c34c sw a1,4(a4) - 6c: c710 sw a2,8(a4) - 6e: c75c sw a5,12(a4) - 70: 54d2 lw s1,52(sp) - 72: 853a mv a0,a4 - -00000074 <.LVL11>: - 74: 6121 add sp,sp,64 - -00000076 <.LVL12>: - 76: 8082 ret - -00000078 <.L2>: - 78: e7d1 bnez a5,104 <.L4> - 7a: d479 beqz s0,48 <.L3> - 7c: c22a sw a0,4(sp) - -0000007e <.LBB10>: - 7e: 8522 mv a0,s0 - 80: c036 sw a3,0(sp) - -00000082 <.LBB13>: - 82: 00000097 auipc ra,0x0 - 86: 000080e7 jalr ra # 82 <.LBB13> - -0000008a <.LBB11>: - 8a: 05150613 add a2,a0,81 - 8e: 40565793 sra a5,a2,0x5 - -00000092 <.LVL16>: - 92: 8a7d and a2,a2,31 - -00000094 <.LVL17>: - 94: 4682 lw a3,0(sp) - 96: 4712 lw a4,4(sp) - 98: c61d beqz a2,c6 <.L5> - -0000009a <.LVL18>: - 9a: 4589 li a1,2 - 9c: 06b79263 bne a5,a1,100 <.L10> - a0: 02000593 li a1,32 - a4: 8d91 sub a1,a1,a2 - -000000a6 <.LVL19>: - a6: 00b455b3 srl a1,s0,a1 - -000000aa <.LVL20>: - aa: ca2e sw a1,20(sp) - -000000ac <.L6>: - ac: fff78593 add a1,a5,-1 - -000000b0 <.LVL22>: - b0: 078a sll a5,a5,0x2 - b2: 02c78793 add a5,a5,44 - b6: 00810313 add t1,sp,8 - ba: 979a add a5,a5,t1 - bc: 00c41633 sll a2,s0,a2 - -000000c0 <.LVL23>: - c0: fcc7aa23 sw a2,-44(a5) - c4: a00d j e6 <.L7> - -000000c6 <.L5>: - c6: 460d li a2,3 - -000000c8 <.LVL25>: - c8: 8e1d sub a2,a2,a5 - ca: 060a sll a2,a2,0x2 - cc: 002c add a1,sp,8 - ce: 02c60613 add a2,a2,44 - d2: 962e add a2,a2,a1 - d4: fd462603 lw a2,-44(a2) - d8: 4589 li a1,2 - da: ca32 sw a2,20(sp) - -000000dc <.LVL26>: - dc: 4609 li a2,2 - de: 00c79463 bne a5,a2,e6 <.L7> - e2: c822 sw s0,16(sp) - -000000e4 <.LVL27>: - e4: 4585 li a1,1 - -000000e6 <.L7>: - e6: 058a sll a1,a1,0x2 - e8: c402 sw zero,8(sp) - ea: c602 sw zero,12(sp) - ec: 15f1 add a1,a1,-4 - ee: 4791 li a5,4 - f0: 00f5e363 bltu a1,a5,f6 <.L8> - f4: c802 sw zero,16(sp) - -000000f6 <.L8>: - f6: 6791 lui a5,0x4 - f8: f8978793 add a5,a5,-119 # 3f89 <.LLST22+0x3c6e> - fc: 8f89 sub a5,a5,a0 - -000000fe <.LVL29>: - fe: b7a9 j 48 <.L3> - -00000100 <.L10>: - 100: 478d li a5,3 - -00000102 <.LVL31>: - 102: b76d j ac <.L6> - -00000104 <.L4>: - 104: c809 beqz s0,116 <.L9> - -00000106 <.LBB14>: - 106: 01941793 sll a5,s0,0x19 - -0000010a <.LVL34>: - 10a: c83e sw a5,16(sp) - -0000010c <.LVL35>: - 10c: 801d srl s0,s0,0x7 - -0000010e <.LBE14>: - 10e: 67a1 lui a5,0x8 - 110: 8c5d or s0,s0,a5 - -00000112 <.LBB15>: - 112: c402 sw zero,8(sp) - -00000114 <.LBE15>: - 114: ca22 sw s0,20(sp) - -00000116 <.L9>: - 116: 67a1 lui a5,0x8 - 118: 17fd add a5,a5,-1 # 7fff <.LLST22+0x7ce4> - 11a: b73d j 48 <.L3> - -extenddftf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__extenddftf2>: - 0: fb810113 add sp,sp,-72 - -00000004 <.LBB3>: - 4: 01465793 srl a5,a2,0x14 - 8: 01f65713 srl a4,a2,0x1f - -0000000c <.LBE3>: - c: c02a sw a0,0(sp) - -0000000e <.LBB4>: - e: 7ff7f793 and a5,a5,2047 - 12: 00c61513 sll a0,a2,0xc - 16: 8131 srl a0,a0,0xc - -00000018 <.LVL2>: - 18: c23a sw a4,4(sp) - -0000001a <.LBE4>: - 1a: 00178713 add a4,a5,1 - 1e: c0a2 sw s0,64(sp) - 20: de26 sw s1,60(sp) - 22: c286 sw ra,68(sp) - 24: 02f10493 add s1,sp,47 - 28: c82e sw a1,16(sp) - 2a: ca2a sw a0,20(sp) - 2c: ce02 sw zero,28(sp) - 2e: cc02 sw zero,24(sp) - 30: 7fe77713 and a4,a4,2046 - 34: 842e mv s0,a1 - 36: 98c1 and s1,s1,-16 - 38: cf21 beqz a4,90 <.L2> - 3a: 6711 lui a4,0x4 - 3c: c0070713 add a4,a4,-1024 # 3c00 <.LLST22+0x38aa> - 40: 97ba add a5,a5,a4 - -00000042 <.LBB5>: - 42: 00455713 srl a4,a0,0x4 - 46: ce3a sw a4,28(sp) - -00000048 <.LVL5>: - 48: 0572 sll a0,a0,0x1c - -0000004a <.LVL6>: - 4a: 0045d713 srl a4,a1,0x4 - 4e: 8d59 or a0,a0,a4 - 50: 01c59413 sll s0,a1,0x1c - 54: cc2a sw a0,24(sp) - -00000056 <.LVL7>: - 56: ca22 sw s0,20(sp) - -00000058 <.LVL8>: - 58: c802 sw zero,16(sp) - -0000005a <.L3>: - 5a: 4772 lw a4,28(sp) - 5c: 45c2 lw a1,16(sp) - 5e: 4652 lw a2,20(sp) - 60: 00e49623 sh a4,12(s1) - 64: 4712 lw a4,4(sp) - 66: 46e2 lw a3,24(sp) - -00000068 <.LBE6>: - 68: 4096 lw ra,68(sp) - -0000006a <.LBB7>: - 6a: 073e sll a4,a4,0xf - 6c: 8fd9 or a5,a5,a4 - -0000006e <.LVL10>: - 6e: 00f49723 sh a5,14(s1) - -00000072 <.LBE7>: - 72: 4702 lw a4,0(sp) - -00000074 <.LBB8>: - 74: 44dc lw a5,12(s1) - -00000076 <.LBE8>: - 76: 4406 lw s0,64(sp) - -00000078 <.LBB9>: - 78: c08c sw a1,0(s1) - 7a: c0d0 sw a2,4(s1) - 7c: c494 sw a3,8(s1) - -0000007e <.LBE9>: - 7e: c30c sw a1,0(a4) - 80: c350 sw a2,4(a4) - 82: c714 sw a3,8(a4) - 84: c75c sw a5,12(a4) - 86: 54f2 lw s1,60(sp) - 88: 853a mv a0,a4 - 8a: 04810113 add sp,sp,72 - -0000008e <.LVL12>: - 8e: 8082 ret - -00000090 <.L2>: - 90: 00b56733 or a4,a0,a1 - 94: e7f9 bnez a5,162 <.L4> - 96: d371 beqz a4,5a <.L3> - -00000098 <.LBB10>: - 98: c921 beqz a0,e8 <.L5> - 9a: 00000097 auipc ra,0x0 - 9e: 000080e7 jalr ra # 9a <.LBB10+0x2> - -000000a2 <.L6>: - a2: 03150713 add a4,a0,49 - a6: 40575793 sra a5,a4,0x5 - -000000aa <.LVL15>: - aa: 8b7d and a4,a4,31 - -000000ac <.LVL16>: - ac: 40f006b3 neg a3,a5 - b0: c721 beqz a4,f8 <.L7> - b2: 02000613 li a2,32 - b6: 8e19 sub a2,a2,a4 - -000000b8 <.LVL17>: - b8: c432 sw a2,8(sp) - ba: 00269613 sll a2,a3,0x2 - -000000be <.LVL18>: - be: 01010293 add t0,sp,16 - c2: 00c60693 add a3,a2,12 - c6: 9696 add a3,a3,t0 - c8: 40c00333 neg t1,a2 - -000000cc <.L8>: - cc: 06d29a63 bne t0,a3,140 <.L11> - d0: fff78693 add a3,a5,-1 - -000000d4 <.LVL19>: - d4: 078a sll a5,a5,0x2 - -000000d6 <.LVL20>: - d6: 02c78793 add a5,a5,44 - da: 0810 add a2,sp,16 - dc: 97b2 add a5,a5,a2 - de: 00e41733 sll a4,s0,a4 - -000000e2 <.LVL21>: - e2: fce7aa23 sw a4,-44(a5) - e6: a035 j 112 <.L10> - -000000e8 <.L5>: - e8: 853a mv a0,a4 - -000000ea <.LVL23>: - ea: 00000097 auipc ra,0x0 - ee: 000080e7 jalr ra # ea <.LVL23> - -000000f2 <.LVL24>: - f2: 02050513 add a0,a0,32 - f6: b775 j a2 <.L6> - -000000f8 <.L7>: - f8: 0878 add a4,sp,28 - -000000fa <.LVL27>: - fa: 068a sll a3,a3,0x2 - -000000fc <.LBB12>: - fc: 460d li a2,3 - -000000fe <.L9>: - fe: 00d705b3 add a1,a4,a3 - 102: 418c lw a1,0(a1) - 104: 167d add a2,a2,-1 - -00000106 <.LVL29>: - 106: 1771 add a4,a4,-4 - 108: c34c sw a1,4(a4) - -0000010a <.LVL30>: - 10a: fef65ae3 bge a2,a5,fe <.L9> - 10e: fff78693 add a3,a5,-1 - -00000112 <.L10>: - 112: 00168793 add a5,a3,1 - 116: 078a sll a5,a5,0x2 - 118: 46a1 li a3,8 - 11a: 0818 add a4,sp,16 - 11c: 00d7e863 bltu a5,a3,12c <.L12> - 120: 00072023 sw zero,0(a4) - 124: 00072223 sw zero,4(a4) - 128: 17e1 add a5,a5,-8 - 12a: 0838 add a4,sp,24 - -0000012c <.L12>: - 12c: 4691 li a3,4 - 12e: 00d7e463 bltu a5,a3,136 <.L13> - 132: 00072023 sw zero,0(a4) - -00000136 <.L13>: - 136: 6791 lui a5,0x4 - 138: c0c78793 add a5,a5,-1012 # 3c0c <.LLST22+0x38b6> - 13c: 8f89 sub a5,a5,a0 - -0000013e <.LVL32>: - 13e: bf31 j 5a <.L3> - -00000140 <.L11>: - 140: 4290 lw a2,0(a3) - 142: ffc6a583 lw a1,-4(a3) - 146: 006683b3 add t2,a3,t1 - 14a: 00e61633 sll a2,a2,a4 - 14e: c632 sw a2,12(sp) - 150: 4622 lw a2,8(sp) - 152: 16f1 add a3,a3,-4 - 154: 00c5d5b3 srl a1,a1,a2 - 158: 4632 lw a2,12(sp) - 15a: 8e4d or a2,a2,a1 - 15c: 00c3a023 sw a2,0(t2) - 160: b7b5 j cc <.L8> - -00000162 <.L4>: - 162: cf19 beqz a4,180 <.L14> - -00000164 <.LBB14>: - 164: 01c51793 sll a5,a0,0x1c - -00000168 <.LVL36>: - 168: 0045d713 srl a4,a1,0x4 - 16c: 8fd9 or a5,a5,a4 - 16e: cc3e sw a5,24(sp) - -00000170 <.LVL37>: - 170: 8111 srl a0,a0,0x4 - -00000172 <.LBE14>: - 172: 67a1 lui a5,0x8 - -00000174 <.LBB15>: - 174: 01c59413 sll s0,a1,0x1c - -00000178 <.LBE15>: - 178: 8d5d or a0,a0,a5 - -0000017a <.LBB16>: - 17a: ca22 sw s0,20(sp) - -0000017c <.LVL40>: - 17c: c802 sw zero,16(sp) - -0000017e <.LBE16>: - 17e: ce2a sw a0,28(sp) - -00000180 <.L14>: - 180: 67a1 lui a5,0x8 - 182: 17fd add a5,a5,-1 # 7fff <.LLST22+0x7ca9> - 184: bdd9 j 5a <.L3> - -truncdfsf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__truncdfsf2>: - 0: 00c59713 sll a4,a1,0xc - -00000004 <.LVL1>: - 4: 0145d313 srl t1,a1,0x14 - -00000008 <.LBE2>: - 8: 8325 srl a4,a4,0x9 - -0000000a <.LBB4>: - a: 7ff37313 and t1,t1,2047 - -0000000e <.LBE4>: - e: 01d55793 srl a5,a0,0x1d - 12: 8fd9 or a5,a5,a4 - 14: 00130713 add a4,t1,1 - 18: 7fe77713 and a4,a4,2046 - -0000001c <.LBB6>: - 1c: 81fd srl a1,a1,0x1f - -0000001e <.LBE6>: - 1e: 00351613 sll a2,a0,0x3 - -00000022 <.LVL5>: - 22: c74d beqz a4,cc <.L2> - 24: c8030693 add a3,t1,-896 - -00000028 <.LVL6>: - 28: 0fe00713 li a4,254 - 2c: 0ed74b63 blt a4,a3,122 <.L15> - 30: 08d04063 bgtz a3,b0 <.L4> - 34: 5725 li a4,-23 - 36: 0ee6c963 blt a3,a4,128 <.L18> - 3a: 008002b7 lui t0,0x800 - 3e: 4779 li a4,30 - 40: 0057e2b3 or t0,a5,t0 - -00000044 <.LVL7>: - 44: 8f15 sub a4,a4,a3 - 46: 47fd li a5,31 - 48: 02e7ce63 blt a5,a4,84 <.L5> - 4c: c8230313 add t1,t1,-894 - -00000050 <.LVL8>: - 50: 00e65733 srl a4,a2,a4 - 54: 00661633 sll a2,a2,t1 - -00000058 <.LVL9>: - 58: 00c03633 snez a2,a2 - 5c: 00629333 sll t1,t0,t1 - -00000060 <.LVL10>: - 60: 00666633 or a2,a2,t1 - 64: 8f51 or a4,a4,a2 - -00000066 <.LBB9>: - 66: 00777793 and a5,a4,7 - 6a: efad bnez a5,e4 <.L6> - -0000006c <.L24>: - 6c: 00375793 srl a5,a4,0x3 - -00000070 <.L22>: - 70: 4681 li a3,0 - -00000072 <.L3>: - 72: 07a6 sll a5,a5,0x9 - -00000074 <.LVL15>: - 74: 01769513 sll a0,a3,0x17 - 78: 83a5 srl a5,a5,0x9 - 7a: 8fc9 or a5,a5,a0 - 7c: 01f59513 sll a0,a1,0x1f - -00000080 <.LBE11>: - 80: 8d5d or a0,a0,a5 - -00000082 <.LVL17>: - 82: 8082 ret - -00000084 <.L5>: - 84: 57f9 li a5,-2 - 86: 8f95 sub a5,a5,a3 - 88: 02000513 li a0,32 - -0000008c <.LVL19>: - 8c: 00f2d7b3 srl a5,t0,a5 - 90: 4681 li a3,0 - -00000092 <.LVL20>: - 92: 00a70663 beq a4,a0,9e <.L7> - 96: ca230693 add a3,t1,-862 - 9a: 00d296b3 sll a3,t0,a3 - -0000009e <.L7>: - 9e: 8ed1 or a3,a3,a2 - a0: 00d036b3 snez a3,a3 - a4: 8fd5 or a5,a5,a3 - -000000a6 <.LBB13>: - a6: 0077f713 and a4,a5,7 - aa: e721 bnez a4,f2 <.L8> - -000000ac <.L12>: - ac: 838d srl a5,a5,0x3 - -000000ae <.LVL23>: - ae: b7c9 j 70 <.L22> - -000000b0 <.L4>: - b0: 00651713 sll a4,a0,0x6 - b4: 078e sll a5,a5,0x3 - -000000b6 <.LVL25>: - b6: 00e03733 snez a4,a4 - ba: 8f5d or a4,a4,a5 - bc: 8275 srl a2,a2,0x1d - -000000be <.LVL26>: - be: 8f51 or a4,a4,a2 - -000000c0 <.LBB15>: - c0: 00777793 and a5,a4,7 - c4: ef95 bnez a5,100 <.L9> - c6: 00375793 srl a5,a4,0x3 - -000000ca <.LVL28>: - ca: b765 j 72 <.L3> - -000000cc <.L2>: - cc: 04030e63 beqz t1,128 <.L18> - -000000d0 <.LVL30>: - d0: 8fd1 or a5,a5,a2 - -000000d2 <.LVL31>: - d2: 0ff00693 li a3,255 - d6: dfd1 beqz a5,72 <.L3> - -000000d8 <.LBB16>: - d8: 4581 li a1,0 - -000000da <.LBE16>: - da: 0ff00693 li a3,255 - -000000de <.LBB17>: - de: 004007b7 lui a5,0x400 - e2: bf41 j 72 <.L3> - -000000e4 <.L6>: - e4: 00f77793 and a5,a4,15 - e8: 4691 li a3,4 - -000000ea <.LVL34>: - ea: f8d781e3 beq a5,a3,6c <.L24> - -000000ee <.LBE17>: - ee: 4681 li a3,0 - f0: a839 j 10e <.L11> - -000000f2 <.L8>: - f2: 00f7f713 and a4,a5,15 - f6: 4691 li a3,4 - f8: fad70ae3 beq a4,a3,ac <.L12> - fc: 0791 add a5,a5,4 # 400004 <.LLST9+0x3ffd20> - -000000fe <.LVL36>: - fe: b77d j ac <.L12> - -00000100 <.L9>: - 100: 00f77313 and t1,a4,15 - -00000104 <.LVL38>: - 104: 4291 li t0,4 - 106: 00375793 srl a5,a4,0x3 - 10a: f65304e3 beq t1,t0,72 <.L3> - -0000010e <.L11>: - 10e: 00470793 add a5,a4,4 - -00000112 <.LVL40>: - 112: 04000737 lui a4,0x4000 - 116: 8f7d and a4,a4,a5 - 118: 838d srl a5,a5,0x3 - -0000011a <.LVL41>: - 11a: df21 beqz a4,72 <.L3> - 11c: 0685 add a3,a3,1 - -0000011e <.L23>: - 11e: 4781 li a5,0 - 120: bf89 j 72 <.L3> - -00000122 <.L15>: - 122: 0ff00693 li a3,255 - -00000126 <.LVL44>: - 126: bfe5 j 11e <.L23> - -00000128 <.L18>: - 128: 4681 li a3,0 - 12a: bfd5 j 11e <.L23> - -trunctfsf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__trunctfsf2>: - 0: fd410113 add sp,sp,-44 - 4: 4558 lw a4,12(a0) - 6: 4514 lw a3,8(a0) - 8: 410c lw a1,0(a0) - a: 4150 lw a2,4(a0) - c: 01f10793 add a5,sp,31 - 10: 9bc1 and a5,a5,-16 - -00000012 <.LBB3>: - 12: c794 sw a3,8(a5) - 14: c7d8 sw a4,12(a5) - 16: c38c sw a1,0(a5) - 18: c3d0 sw a2,4(a5) - 1a: 01071793 sll a5,a4,0x10 - 1e: 83c1 srl a5,a5,0x10 - 20: c436 sw a3,8(sp) - 22: 850a mv a0,sp - 24: 00171693 sll a3,a4,0x1 - 28: c63e sw a5,12(sp) - 2a: c02e sw a1,0(sp) - 2c: c232 sw a2,4(sp) - 2e: 82c5 srl a3,a3,0x11 - -00000030 <.LVL1>: - 30: 837d srl a4,a4,0x1f - -00000032 <.LBB4>: - 32: ff410313 add t1,sp,-12 - -00000036 <.LBB5>: - 36: 87aa mv a5,a0 - -00000038 <.L2>: - 38: 47d0 lw a2,12(a5) - 3a: 478c lw a1,8(a5) - 3c: 17f1 add a5,a5,-4 - 3e: 060e sll a2,a2,0x3 - 40: 81f5 srl a1,a1,0x1d - 42: 8e4d or a2,a2,a1 - 44: cb90 sw a2,16(a5) - 46: fef319e3 bne t1,a5,38 <.L2> - -0000004a <.LVL4>: - 4a: 4582 lw a1,0(sp) - -0000004c <.LBE6>: - 4c: 6621 lui a2,0x8 - 4e: 00168793 add a5,a3,1 - -00000052 <.LBB7>: - 52: 058e sll a1,a1,0x3 - -00000054 <.LBE7>: - 54: 1679 add a2,a2,-2 # 7ffe <.LLST15+0x7ba3> - -00000056 <.LBB8>: - 56: c02e sw a1,0(sp) - -00000058 <.LBE8>: - 58: 8ff1 and a5,a5,a2 - 5a: 10078b63 beqz a5,170 <.L3> - 5e: 77f1 lui a5,0xffffc - 60: 08078793 add a5,a5,128 # ffffc080 <.LLST15+0xffffbc25> - 64: 96be add a3,a3,a5 - -00000066 <.LVL6>: - 66: 0fe00793 li a5,254 - 6a: 02d7d263 bge a5,a3,8e <.L4> - -0000006e <.L15>: - 6e: 0ff00693 li a3,255 - 72: 4601 li a2,0 - -00000074 <.L5>: - 74: 06de sll a3,a3,0x17 - 76: 7f8007b7 lui a5,0x7f800 - 7a: 0626 sll a2,a2,0x9 - -0000007c <.LVL9>: - 7c: 8efd and a3,a3,a5 - 7e: 8225 srl a2,a2,0x9 - 80: 8ed1 or a3,a3,a2 - 82: 01f71513 sll a0,a4,0x1f - -00000086 <.LBE10>: - 86: 8d55 or a0,a0,a3 - -00000088 <.LVL11>: - 88: 02c10113 add sp,sp,44 - -0000008c <.LVL12>: - 8c: 8082 ret - -0000008e <.L4>: - 8e: 04d05863 blez a3,de <.L6> - -00000092 <.LBB11>: - 92: 4522 lw a0,8(sp) - -00000094 <.LBB13>: - 94: 4612 lw a2,4(sp) - 96: 00751793 sll a5,a0,0x7 - -0000009a <.LVL16>: - 9a: 8fcd or a5,a5,a1 - -0000009c <.LVL17>: - 9c: 8fd1 or a5,a5,a2 - -0000009e <.LVL18>: - 9e: 4632 lw a2,12(sp) - a0: 8165 srl a0,a0,0x19 - -000000a2 <.LVL19>: - a2: 00f037b3 snez a5,a5 - -000000a6 <.LVL20>: - a6: 061e sll a2,a2,0x7 - a8: 8e49 or a2,a2,a0 - -000000aa <.LBE13>: - aa: 8fd1 or a5,a5,a2 - -000000ac <.L14>: - ac: 0077f613 and a2,a5,7 - b0: c619 beqz a2,be <.L16> - b2: 00f7f613 and a2,a5,15 - b6: 4591 li a1,4 - b8: 00b60363 beq a2,a1,be <.L16> - -000000bc <.LVL22>: - bc: 0791 add a5,a5,4 # 7f800004 <.LLST15+0x7f7ffba9> - -000000be <.L16>: - be: 04000637 lui a2,0x4000 - c2: 8e7d and a2,a2,a5 - c4: ce61 beqz a2,19c <.L8> - -000000c6 <.LVL24>: - c6: 0685 add a3,a3,1 - -000000c8 <.LVL25>: - c8: 0ff00593 li a1,255 - cc: 4601 li a2,0 - ce: fab683e3 beq a3,a1,74 <.L5> - d2: 1f800637 lui a2,0x1f800 - d6: 838d srl a5,a5,0x3 - -000000d8 <.LVL26>: - d8: 167d add a2,a2,-1 # 1f7fffff <.LLST15+0x1f7ffba4> - da: 8e7d and a2,a2,a5 - -000000dc <.LVL27>: - dc: bf61 j 74 <.L5> - -000000de <.L6>: - de: 57a5 li a5,-23 - e0: 0af6cc63 blt a3,a5,198 <.L17> - e4: 47b2 lw a5,12(sp) - e6: 00080637 lui a2,0x80 - -000000ea <.LBB17>: - ea: 4581 li a1,0 - -000000ec <.LBE17>: - ec: 8e5d or a2,a2,a5 - -000000ee <.LBB19>: - ee: 05a00793 li a5,90 - f2: 40d786b3 sub a3,a5,a3 - -000000f6 <.LVL29>: - f6: 4056d313 sra t1,a3,0x5 - -000000fa <.LBE19>: - fa: c632 sw a2,12(sp) - -000000fc <.LBB20>: - fc: 8afd and a3,a3,31 - -000000fe <.LVL31>: - fe: 4781 li a5,0 - -00000100 <.L9>: - 100: 00052283 lw t0,0(a0) - 104: 0585 add a1,a1,1 - -00000106 <.LVL33>: - 106: 0511 add a0,a0,4 - 108: 0057e7b3 or a5,a5,t0 - -0000010c <.LVL34>: - 10c: feb31ae3 bne t1,a1,100 <.L9> - 110: 00231593 sll a1,t1,0x2 - -00000114 <.LVL35>: - 114: ee91 bnez a3,130 <.L10> - -00000116 <.LVL36>: - 116: 02c58693 add a3,a1,44 - -0000011a <.LVL37>: - 11a: 002685b3 add a1,a3,sp - 11e: fd45a683 lw a3,-44(a1) - 122: c036 sw a3,0(sp) - -00000124 <.L12>: - 124: 4682 lw a3,0(sp) - -00000126 <.LBB21>: - 126: 00f037b3 snez a5,a5 - -0000012a <.LBE21>: - 12a: 8fd5 or a5,a5,a3 - -0000012c <.LBE24>: - 12c: 4681 li a3,0 - -0000012e <.LVL40>: - 12e: bfbd j ac <.L14> - -00000130 <.L10>: - 130: 02c58593 add a1,a1,44 - 134: 958a add a1,a1,sp - 136: fd45a583 lw a1,-44(a1) - 13a: 02000513 li a0,32 - 13e: 8d15 sub a0,a0,a3 - 140: 00a595b3 sll a1,a1,a0 - 144: 4289 li t0,2 - 146: 8fcd or a5,a5,a1 - -00000148 <.LVL42>: - 148: 4581 li a1,0 - 14a: 00531a63 bne t1,t0,15e <.L13> - 14e: 45a2 lw a1,8(sp) - 150: 00a61533 sll a0,a2,a0 - 154: 00d5d5b3 srl a1,a1,a3 - 158: 8d4d or a0,a0,a1 - 15a: c02a sw a0,0(sp) - -0000015c <.LVL43>: - 15c: 4585 li a1,1 - -0000015e <.L13>: - 15e: 058a sll a1,a1,0x2 - -00000160 <.LVL45>: - 160: 02c58593 add a1,a1,44 - 164: 958a add a1,a1,sp - 166: 00d65633 srl a2,a2,a3 - 16a: fcc5aa23 sw a2,-44(a1) - 16e: bf5d j 124 <.L12> - -00000170 <.L3>: - 170: 4601 li a2,0 - -00000172 <.LBE26>: - 172: d289 beqz a3,74 <.L5> - -00000174 <.LBB14>: - 174: 47a2 lw a5,8(sp) - -00000176 <.LBE14>: - 176: 4692 lw a3,4(sp) - -00000178 <.LBB15>: - 178: 4632 lw a2,12(sp) - -0000017a <.LBE15>: - 17a: 8edd or a3,a3,a5 - 17c: 8ed1 or a3,a3,a2 - 17e: 8ecd or a3,a3,a1 - 180: ee0687e3 beqz a3,6e <.L15> - -00000184 <.LBB29>: - 184: 83e5 srl a5,a5,0x19 - -00000186 <.LVL50>: - 186: 061e sll a2,a2,0x7 - -00000188 <.LVL51>: - 188: 8fd1 or a5,a5,a2 - -0000018a <.LBE30>: - 18a: 020006b7 lui a3,0x2000 - 18e: 9be1 and a5,a5,-8 - 190: 8fd5 or a5,a5,a3 - 192: 0ff00693 li a3,255 - 196: bf19 j ac <.L14> - -00000198 <.L17>: - 198: 4681 li a3,0 - -0000019a <.LBB31>: - 19a: 4795 li a5,5 - -0000019c <.L8>: - 19c: 0037d613 srl a2,a5,0x3 - -000001a0 <.LVL58>: - 1a0: 0ff00793 li a5,255 - 1a4: ecf698e3 bne a3,a5,74 <.L5> - 1a8: ec0603e3 beqz a2,6e <.L15> - 1ac: 00400637 lui a2,0x400 - -000001b0 <.LVL59>: - 1b0: 4701 li a4,0 - -000001b2 <.LVL60>: - 1b2: b5c9 j 74 <.L5> - -trunctfdf2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__trunctfdf2>: - 0: fc810113 add sp,sp,-56 - 4: 4554 lw a3,12(a0) - 6: 4518 lw a4,8(a0) - 8: 410c lw a1,0(a0) - a: 4150 lw a2,4(a0) - c: 02310793 add a5,sp,35 - 10: d826 sw s1,48(sp) - 12: 9bc1 and a5,a5,-16 - 14: da22 sw s0,52(sp) - -00000016 <.LBB3>: - 16: c798 sw a4,8(a5) - 18: c7d4 sw a3,12(a5) - 1a: c38c sw a1,0(a5) - 1c: c3d0 sw a2,4(a5) - 1e: 01069793 sll a5,a3,0x10 - 22: 83c1 srl a5,a5,0x10 - 24: c63a sw a4,12(sp) - 26: 01f6d493 srl s1,a3,0x1f - 2a: 00169713 sll a4,a3,0x1 - 2e: 0054 add a3,sp,4 - 30: c83e sw a5,16(sp) - 32: c22e sw a1,4(sp) - 34: c432 sw a2,8(sp) - 36: 8345 srl a4,a4,0x11 - -00000038 <.LBB4>: - 38: ff810513 add a0,sp,-8 - -0000003c <.LBB5>: - 3c: 87b6 mv a5,a3 - -0000003e <.L2>: - 3e: 47d0 lw a2,12(a5) - 40: 478c lw a1,8(a5) - 42: 17f1 add a5,a5,-4 - 44: 060e sll a2,a2,0x3 - 46: 81f5 srl a1,a1,0x1d - 48: 8e4d or a2,a2,a1 - 4a: cb90 sw a2,16(a5) - 4c: fea799e3 bne a5,a0,3e <.L2> - -00000050 <.LVL3>: - 50: 4592 lw a1,4(sp) - -00000052 <.LBE6>: - 52: 6621 lui a2,0x8 - 54: 00170793 add a5,a4,1 - -00000058 <.LBB7>: - 58: 058e sll a1,a1,0x3 - -0000005a <.LBE7>: - 5a: 1679 add a2,a2,-2 # 7ffe <.LLST14+0x7af8> - -0000005c <.LBB8>: - 5c: c22e sw a1,4(sp) - -0000005e <.LBE8>: - 5e: 8ff1 and a5,a5,a2 - 60: 18078c63 beqz a5,1f8 <.L3> - 64: 77f1 lui a5,0xffffc - 66: 40078793 add a5,a5,1024 # ffffc400 <.LLST14+0xffffbefa> - 6a: 973e add a4,a4,a5 - -0000006c <.LVL5>: - 6c: 7fe00793 li a5,2046 - 70: 1ee7c063 blt a5,a4,250 <.L21> - 74: 08e05a63 blez a4,108 <.L5> - -00000078 <.LBB10>: - 78: 4632 lw a2,12(sp) - 7a: 47c2 lw a5,16(sp) - 7c: 46a2 lw a3,8(sp) - -0000007e <.LVL7>: - 7e: 01c65513 srl a0,a2,0x1c - 82: 0792 sll a5,a5,0x4 - 84: 8fc9 or a5,a5,a0 - 86: c43e sw a5,8(sp) - -00000088 <.LBB11>: - 88: 00469793 sll a5,a3,0x4 - 8c: 8fcd or a5,a5,a1 - -0000008e <.LVL9>: - 8e: 82f1 srl a3,a3,0x1c - -00000090 <.LVL10>: - 90: 0612 sll a2,a2,0x4 - 92: 00f037b3 snez a5,a5 - -00000096 <.LVL11>: - 96: 8ed1 or a3,a3,a2 - -00000098 <.LBE11>: - 98: 8fd5 or a5,a5,a3 - -0000009a <.L6>: - 9a: 46a2 lw a3,8(sp) - -0000009c <.L17>: - 9c: 0077f613 and a2,a5,7 - a0: ce01 beqz a2,b8 <.L18> - -000000a2 <.LVL14>: - a2: 00f7f613 and a2,a5,15 - a6: 4591 li a1,4 - a8: 00b60863 beq a2,a1,b8 <.L18> - -000000ac <.LBB14>: - ac: 00478613 add a2,a5,4 - b0: 00f635b3 sltu a1,a2,a5 - b4: 96ae add a3,a3,a1 - b6: 87b2 mv a5,a2 - -000000b8 <.L18>: - b8: 00800637 lui a2,0x800 - bc: 8e75 and a2,a2,a3 - be: 16060763 beqz a2,22c <.L7> - c2: ff8005b7 lui a1,0xff800 - c6: 15fd add a1,a1,-1 # ff7fffff <.LLST14+0xff7ffaf9> - c8: 0705 add a4,a4,1 - ca: 7ff00513 li a0,2047 - ce: 8df5 and a1,a1,a3 - -000000d0 <.LVL16>: - d0: 4601 li a2,0 - d2: 4681 li a3,0 - d4: 00a70863 beq a4,a0,e4 <.L4> - d8: 838d srl a5,a5,0x3 - -000000da <.LVL17>: - da: 01d59613 sll a2,a1,0x1d - de: 8e5d or a2,a2,a5 - -000000e0 <.LVL18>: - e0: 0035d693 srl a3,a1,0x3 - -000000e4 <.L4>: - e4: 7ff007b7 lui a5,0x7ff00 - e8: 0752 sll a4,a4,0x14 - ea: 06b2 sll a3,a3,0xc - -000000ec <.LBE22>: - ec: 5452 lw s0,52(sp) - -000000ee <.LBB23>: - ee: 8f7d and a4,a4,a5 - f0: 82b1 srl a3,a3,0xc - f2: 01f49793 sll a5,s1,0x1f - f6: 8f55 or a4,a4,a3 - f8: 00f766b3 or a3,a4,a5 - -000000fc <.LBE23>: - fc: 54c2 lw s1,48(sp) - -000000fe <.LVL22>: - fe: 8532 mv a0,a2 - 100: 85b6 mv a1,a3 - 102: 03810113 add sp,sp,56 - -00000106 <.LVL23>: - 106: 8082 ret - -00000108 <.L5>: - 108: fcc00793 li a5,-52 - 10c: 10f74d63 blt a4,a5,226 <.L22> - 110: 47c2 lw a5,16(sp) - 112: 00080537 lui a0,0x80 - -00000116 <.LBB24>: - 116: 85b6 mv a1,a3 - -00000118 <.LBE24>: - 118: 8fc9 or a5,a5,a0 - 11a: c03e sw a5,0(sp) - 11c: c83e sw a5,16(sp) - -0000011e <.LBB26>: - 11e: 03d00793 li a5,61 - 122: 40e78733 sub a4,a5,a4 - -00000126 <.LVL25>: - 126: 40575313 sra t1,a4,0x5 - -0000012a <.LVL26>: - 12a: 4601 li a2,0 - 12c: 8b7d and a4,a4,31 - -0000012e <.LVL27>: - 12e: 4781 li a5,0 - -00000130 <.L8>: - 130: 0005a283 lw t0,0(a1) - 134: 0605 add a2,a2,1 # 800001 <.LLST14+0x7ffafb> - -00000136 <.LVL29>: - 136: 0591 add a1,a1,4 - 138: 0057e7b3 or a5,a5,t0 - -0000013c <.LVL30>: - 13c: fec31ae3 bne t1,a2,130 <.L8> - 140: 460d li a2,3 - -00000142 <.LVL31>: - 142: 40660633 sub a2,a2,t1 - 146: 00231593 sll a1,t1,0x2 - 14a: ef09 bnez a4,164 <.L9> - -0000014c <.L10>: - 14c: 00b68533 add a0,a3,a1 - 150: 4108 lw a0,0(a0) - 152: 0705 add a4,a4,1 - -00000154 <.LVL33>: - 154: c288 sw a0,0(a3) - -00000156 <.LVL34>: - 156: 0691 add a3,a3,4 - 158: fee65ae3 bge a2,a4,14c <.L10> - 15c: 4691 li a3,4 - 15e: 406686b3 sub a3,a3,t1 - 162: a089 j 1a4 <.L14> - -00000164 <.L9>: - 164: 02c58413 add s0,a1,44 - 168: 0048 add a0,sp,4 - 16a: 00a402b3 add t0,s0,a0 - 16e: fd42a283 lw t0,-44(t0) - 172: 02000393 li t2,32 - 176: 40e383b3 sub t2,t2,a4 - 17a: 007292b3 sll t0,t0,t2 - 17e: 0057e7b3 or a5,a5,t0 - -00000182 <.LVL36>: - 182: 95b6 add a1,a1,a3 - 184: 4401 li s0,0 - -00000186 <.L12>: - 186: 04c44963 blt s0,a2,1d8 <.L13> - 18a: 060a sll a2,a2,0x2 - 18c: 004c add a1,sp,4 - 18e: 02c60613 add a2,a2,44 - 192: 962e add a2,a2,a1 - 194: 4582 lw a1,0(sp) - 196: 4691 li a3,4 - 198: 406686b3 sub a3,a3,t1 - -0000019c <.LVL38>: - 19c: 00e5d533 srl a0,a1,a4 - 1a0: fca62a23 sw a0,-44(a2) - -000001a4 <.L14>: - 1a4: 4711 li a4,4 - 1a6: 8f15 sub a4,a4,a3 - 1a8: 068a sll a3,a3,0x2 - -000001aa <.LVL40>: - 1aa: 0691 add a3,a3,4 - 1ac: 070a sll a4,a4,0x2 - 1ae: 4621 li a2,8 - 1b0: 968a add a3,a3,sp - 1b2: 00c76863 bltu a4,a2,1c2 <.L15> - 1b6: 0006a023 sw zero,0(a3) - 1ba: 0006a223 sw zero,4(a3) - 1be: 1761 add a4,a4,-8 - 1c0: 06a1 add a3,a3,8 - -000001c2 <.L15>: - 1c2: 4611 li a2,4 - 1c4: 00c76463 bltu a4,a2,1cc <.L16> - 1c8: 0006a023 sw zero,0(a3) - -000001cc <.L16>: - 1cc: 4712 lw a4,4(sp) - -000001ce <.LBB27>: - 1ce: 00f037b3 snez a5,a5 - -000001d2 <.LBE27>: - 1d2: 8fd9 or a5,a5,a4 - -000001d4 <.LBE29>: - 1d4: 4701 li a4,0 - 1d6: b5d1 j 9a <.L6> - -000001d8 <.L13>: - 1d8: 0005a283 lw t0,0(a1) - 1dc: 0405 add s0,s0,1 - -000001de <.LVL44>: - 1de: 0591 add a1,a1,4 - 1e0: 00e2d533 srl a0,t0,a4 - 1e4: 0005a283 lw t0,0(a1) - 1e8: 007292b3 sll t0,t0,t2 - 1ec: 005562b3 or t0,a0,t0 - 1f0: 0056a023 sw t0,0(a3) - -000001f4 <.LVL45>: - 1f4: 0691 add a3,a3,4 - 1f6: bf41 j 186 <.L12> - -000001f8 <.L3>: - 1f8: cf31 beqz a4,254 <.L23> - -000001fa <.LBB12>: - 1fa: 47a2 lw a5,8(sp) - 1fc: 46b2 lw a3,12(sp) - 1fe: 4742 lw a4,16(sp) - -00000200 <.LBE12>: - 200: 00f6e633 or a2,a3,a5 - 204: 8e59 or a2,a2,a4 - 206: 8e4d or a2,a2,a1 - 208: ca29 beqz a2,25a <.L24> - -0000020a <.LBB32>: - 20a: 00469613 sll a2,a3,0x4 - 20e: 0712 sll a4,a4,0x4 - -00000210 <.LVL49>: - 210: 83f1 srl a5,a5,0x1c - -00000212 <.LVL50>: - 212: 82f1 srl a3,a3,0x1c - -00000214 <.LVL51>: - 214: 8ed9 or a3,a3,a4 - -00000216 <.LVL52>: - 216: 8fd1 or a5,a5,a2 - -00000218 <.LBE33>: - 218: 00400737 lui a4,0x400 - 21c: 8ed9 or a3,a3,a4 - -0000021e <.LVL54>: - 21e: 9be1 and a5,a5,-8 - -00000220 <.LVL55>: - 220: 7ff00713 li a4,2047 - 224: bda5 j 9c <.L17> - -00000226 <.L22>: - 226: 4701 li a4,0 - -00000228 <.LBB17>: - 228: 4795 li a5,5 - 22a: 4681 li a3,0 - -0000022c <.L7>: - 22c: 838d srl a5,a5,0x3 - -0000022e <.LVL59>: - 22e: 01d69613 sll a2,a3,0x1d - 232: 8e5d or a2,a2,a5 - -00000234 <.LVL60>: - 234: 7ff00793 li a5,2047 - 238: 828d srl a3,a3,0x3 - 23a: eaf715e3 bne a4,a5,e4 <.L4> - -0000023e <.LVL62>: - 23e: 8e55 or a2,a2,a3 - 240: 4681 li a3,0 - 242: ea0601e3 beqz a2,e4 <.L4> - 246: 000806b7 lui a3,0x80 - 24a: 4601 li a2,0 - 24c: 4481 li s1,0 - -0000024e <.LVL63>: - 24e: bd59 j e4 <.L4> - -00000250 <.L21>: - 250: 7ff00713 li a4,2047 - -00000254 <.L23>: - 254: 4681 li a3,0 - 256: 4601 li a2,0 - 258: b571 j e4 <.L4> - -0000025a <.L24>: - 25a: 4681 li a3,0 - -0000025c <.LBE35>: - 25c: 7ff00713 li a4,2047 - 260: b551 j e4 <.L4> - -save-restore.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__riscv_save_0>: - 0: 1151 add sp,sp,-12 - 2: c026 sw s1,0(sp) - 4: c222 sw s0,4(sp) - 6: c406 sw ra,8(sp) - 8: 8282 jr t0 - -0000000a <__riscv_restore_0>: - a: 4482 lw s1,0(sp) - c: 4412 lw s0,4(sp) - e: 40a2 lw ra,8(sp) - 10: 0131 add sp,sp,12 - 12: 8082 ret - -muldi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__mulsi3-0x2>: - 0: 0001 nop - -00000002 <__mulsi3>: - 2: 862a mv a2,a0 - 4: 4501 li a0,0 - -00000006 <.L1>: - 6: 0015f693 and a3,a1,1 - a: c291 beqz a3,e <.L2> - c: 9532 add a0,a0,a2 - -0000000e <.L2>: - e: 8185 srl a1,a1,0x1 - 10: 0606 sll a2,a2,0x1 - 12: f9f5 bnez a1,6 <.L1> - 14: 8082 ret - ... - -multi3.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__muldi3>: - 0: 1151 add sp,sp,-12 - 2: c222 sw s0,4(sp) - 4: 842a mv s0,a0 - 6: 83b6 mv t2,a3 - 8: c406 sw ra,8(sp) - a: c026 sw s1,0(sp) - c: 8532 mv a0,a2 - -0000000e <.LVL1>: - e: 82a2 mv t0,s0 - -00000010 <.LVL2>: - 10: 86b2 mv a3,a2 - 12: 4701 li a4,0 - 14: 4781 li a5,0 - 16: 4301 li t1,0 - -00000018 <.L5>: - 18: 0016f493 and s1,a3,1 - 1c: 00171613 sll a2,a4,0x1 - -00000020 <.LVL4>: - 20: c491 beqz s1,2c <.L2> - 22: 9316 add t1,t1,t0 - -00000024 <.LVL5>: - 24: 973e add a4,a4,a5 - -00000026 <.LVL6>: - 26: 005337b3 sltu a5,t1,t0 - -0000002a <.LVL7>: - 2a: 97ba add a5,a5,a4 - -0000002c <.L2>: - 2c: 01f2d713 srl a4,t0,0x1f - 30: 8285 srl a3,a3,0x1 - 32: 8f51 or a4,a4,a2 - 34: 0286 sll t0,t0,0x1 - -00000036 <.LVL10>: - 36: f2ed bnez a3,18 <.L5> - 38: c591 beqz a1,44 <.L6> - -0000003a <.LBB2>: - 3a: 00000097 auipc ra,0x0 - 3e: 000080e7 jalr ra # 3a <.LBB2> - -00000042 <.LBE2>: - 42: 97aa add a5,a5,a0 - -00000044 <.L6>: - 44: 00038963 beqz t2,56 <.L7> - -00000048 <.LBB3>: - 48: 8522 mv a0,s0 - 4a: 859e mv a1,t2 - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <.LBB3+0x4> - -00000054 <.LBE3>: - 54: 97aa add a5,a5,a0 - -00000056 <.L7>: - 56: 40a2 lw ra,8(sp) - 58: 4412 lw s0,4(sp) - 5a: 4482 lw s1,0(sp) - 5c: 851a mv a0,t1 - 5e: 85be mv a1,a5 - 60: 0131 add sp,sp,12 - 62: 8082 ret - -div.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__divsi3-0x2>: - 0: 0001 nop - -00000002 <__divsi3>: - 2: 02054e63 bltz a0,3e <.L10> - 6: 0405c363 bltz a1,4c <.L11> - -0000000a <__hidden___udivsi3>: - a: 862e mv a2,a1 - c: 85aa mv a1,a0 - e: 557d li a0,-1 - 10: c215 beqz a2,34 <.L5> - 12: 4685 li a3,1 - 14: 00b67863 bgeu a2,a1,24 <.L2> - -00000018 <.L1>: - 18: 00c05663 blez a2,24 <.L2> - 1c: 0606 sll a2,a2,0x1 - 1e: 0686 sll a3,a3,0x1 - 20: feb66ce3 bltu a2,a1,18 <.L1> - -00000024 <.L2>: - 24: 4501 li a0,0 - -00000026 <.L3>: - 26: 00c5e463 bltu a1,a2,2e <.L4> - 2a: 8d91 sub a1,a1,a2 - 2c: 8d55 or a0,a0,a3 - -0000002e <.L4>: - 2e: 8285 srl a3,a3,0x1 - 30: 8205 srl a2,a2,0x1 - 32: faf5 bnez a3,26 <.L3> - -00000034 <.L5>: - 34: 8082 ret - -00000036 <__umodsi3>: - 36: 8286 mv t0,ra - 38: 3fc9 jal a <__hidden___udivsi3> - 3a: 852e mv a0,a1 - 3c: 8282 jr t0 - -0000003e <.L10>: - 3e: 40a00533 neg a0,a0 - 42: 00b04763 bgtz a1,50 <.L12> - 46: 40b005b3 neg a1,a1 - 4a: b7c1 j a <__hidden___udivsi3> - -0000004c <.L11>: - 4c: 40b005b3 neg a1,a1 - -00000050 <.L12>: - 50: 8286 mv t0,ra - 52: 3f65 jal a <__hidden___udivsi3> - 54: 40a00533 neg a0,a0 - 58: 8282 jr t0 - -0000005a <__modsi3>: - 5a: 8286 mv t0,ra - 5c: 0005c763 bltz a1,6a <.L31> - 60: 00054963 bltz a0,72 <.L32> - -00000064 <.L30>: - 64: 375d jal a <__hidden___udivsi3> - 66: 852e mv a0,a1 - 68: 8282 jr t0 - -0000006a <.L31>: - 6a: 40b005b3 neg a1,a1 - 6e: fe055be3 bgez a0,64 <.L30> - -00000072 <.L32>: - 72: 40a00533 neg a0,a0 - 76: 3f51 jal a <__hidden___udivsi3> - 78: 40b00533 neg a0,a1 - 7c: 8282 jr t0 - ... - -atomic.o: file format elf32-littleriscv - - -enable-execute-stack.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__enable_execute_stack>: - 0: 8082 ret - -unwind-dw2.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 : - 0: 4701 li a4,0 - 2: 4681 li a3,0 - -00000004 <.L2>: - 4: 00054783 lbu a5,0(a0) - 8: 0505 add a0,a0,1 - -0000000a <.LVL2>: - a: 07f7f613 and a2,a5,127 - e: 07e2 sll a5,a5,0x18 - -00000010 <.LVL3>: - 10: 00d61633 sll a2,a2,a3 - 14: 87e1 sra a5,a5,0x18 - 16: 8f51 or a4,a4,a2 - 18: 069d add a3,a3,7 - 1a: fe07c5e3 bltz a5,4 <.L2> - 1e: c198 sw a4,0(a1) - -00000020 <.LVL6>: - 20: 8082 ret - -00000022 : - 22: 4781 li a5,0 - 24: 4701 li a4,0 - -00000026 <.L5>: - 26: 00054683 lbu a3,0(a0) - 2a: 0505 add a0,a0,1 - -0000002c <.LVL9>: - 2c: 07f6f613 and a2,a3,127 - 30: 00e61633 sll a2,a2,a4 - 34: 8fd1 or a5,a5,a2 - 36: 01869613 sll a2,a3,0x18 - 3a: 8661 sra a2,a2,0x18 - 3c: 071d add a4,a4,7 - 3e: fe0644e3 bltz a2,26 <.L5> - 42: 467d li a2,31 - 44: 00e66963 bltu a2,a4,56 <.L6> - 48: 0406f693 and a3,a3,64 - -0000004c <.LVL12>: - 4c: c689 beqz a3,56 <.L6> - 4e: 56fd li a3,-1 - 50: 00e69733 sll a4,a3,a4 - -00000054 <.LVL13>: - 54: 8fd9 or a5,a5,a4 - -00000056 <.L6>: - 56: c19c sw a5,0(a1) - -00000058 <.LVL15>: - 58: 8082 ret - -0000005a <_Unwind_GetGRPtr>: - 5a: 12452703 lw a4,292(a0) - 5e: 400007b7 lui a5,0x40000 - 62: 8ff9 and a5,a5,a4 - 64: 00259713 sll a4,a1,0x2 - -00000068 <.LBE126>: - 68: c799 beqz a5,76 <.L12> - 6a: 95aa add a1,a1,a0 - -0000006c <.LVL17>: - 6c: 1305c783 lbu a5,304(a1) - 70: c399 beqz a5,76 <.L12> - 72: 953a add a0,a0,a4 - -00000074 <.LVL18>: - 74: 8082 ret - -00000076 <.L12>: - 76: 953a add a0,a0,a4 - -00000078 <.LVL20>: - 78: 4108 lw a0,0(a0) - 7a: 8082 ret - -0000007c <_Unwind_SetGRPtr>: - 7c: 12452703 lw a4,292(a0) - 80: 400007b7 lui a5,0x40000 - 84: 8ff9 and a5,a5,a4 - -00000086 <.LBE128>: - 86: c789 beqz a5,90 <.L21> - 88: 00b507b3 add a5,a0,a1 - 8c: 12078823 sb zero,304(a5) # 40000130 <.LLST185+0x3fffda08> - -00000090 <.L21>: - 90: 058a sll a1,a1,0x2 - -00000092 <.LVL22>: - 92: 952e add a0,a0,a1 - -00000094 <.LVL23>: - 94: c110 sw a2,0(a0) - 96: 8082 ret - -00000098 <_Unwind_SetGRValue>: - 98: 04300793 li a5,67 - 9c: 00f59863 bne a1,a5,ac <.L26> - -000000a0 <.L27>: - a0: 1151 add sp,sp,-12 - a2: c406 sw ra,8(sp) - a4: 00000097 auipc ra,0x0 - a8: 000080e7 jalr ra # a4 <.L27+0x4> - -000000ac <.L26>: - ac: 000007b7 lui a5,0x0 - b0: 00078793 mv a5,a5 - b4: 97ae add a5,a5,a1 - b6: 0007c703 lbu a4,0(a5) # 0 - ba: 4791 li a5,4 - bc: fee7e2e3 bltu a5,a4,a0 <.L27> - c0: 00b507b3 add a5,a0,a1 - c4: 4705 li a4,1 - c6: 058a sll a1,a1,0x2 - -000000c8 <.LVL26>: - c8: 12e78823 sb a4,304(a5) - -000000cc <.LBB130>: - cc: 952e add a0,a0,a1 - -000000ce <.LVL28>: - ce: c110 sw a2,0(a0) - d0: 8082 ret - -000000d2 : - d2: 1111 add sp,sp,-28 - d4: cc06 sw ra,24(sp) - d6: ca22 sw s0,20(sp) - d8: c826 sw s1,16(sp) - da: c036 sw a3,0(sp) - -000000dc <.LBB155>: - dc: 0ff00793 li a5,255 - e0: 02f58363 beq a1,a5,106 <.L31> - e4: 0705f693 and a3,a1,112 - -000000e8 <.LVL30>: - e8: 03000793 li a5,48 - ec: 842e mv s0,a1 - ee: 84b2 mv s1,a2 - f0: 04f68b63 beq a3,a5,146 <.L32> - f4: 00d7ed63 bltu a5,a3,10e <.L33> - f8: 02000793 li a5,32 - fc: 04f68263 beq a3,a5,140 <.L34> - 100: 4601 li a2,0 - -00000102 <.LVL31>: - 102: 00d7ff63 bgeu a5,a3,120 <.L35> - -00000106 <.L31>: - 106: 00000097 auipc ra,0x0 - 10a: 000080e7 jalr ra # 106 <.L31> - -0000010e <.L33>: - 10e: 04000793 li a5,64 - 112: 02f68d63 beq a3,a5,14c <.L36> - 116: 05000793 li a5,80 - 11a: 4601 li a2,0 - 11c: fef695e3 bne a3,a5,106 <.L31> - -00000120 <.L35>: - 120: 05000793 li a5,80 - 124: 02f41763 bne s0,a5,152 <.L37> - -00000128 <.LBB158>: - 128: 00348513 add a0,s1,3 - -0000012c <.LVL36>: - 12c: 9971 and a0,a0,-4 - -0000012e <.LVL37>: - 12e: 411c lw a5,0(a0) - -00000130 <.LVL38>: - 130: 0511 add a0,a0,4 - -00000132 <.L38>: - 132: 4702 lw a4,0(sp) - -00000134 <.LBE156>: - 134: 40e2 lw ra,24(sp) - 136: 4452 lw s0,20(sp) - -00000138 <.LBB164>: - 138: c31c sw a5,0(a4) - -0000013a <.LBE164>: - 13a: 44c2 lw s1,16(sp) - -0000013c <.LVL41>: - 13c: 0171 add sp,sp,28 - -0000013e <.LVL42>: - 13e: 8082 ret - -00000140 <.L34>: - 140: 11852603 lw a2,280(a0) - -00000144 <.LBE147>: - 144: bff1 j 120 <.L35> - -00000146 <.L32>: - 146: 11c52603 lw a2,284(a0) - -0000014a <.LBE149>: - 14a: bfd9 j 120 <.L35> - -0000014c <.L36>: - 14c: 12052603 lw a2,288(a0) - -00000150 <.LBE151>: - 150: bfc1 j 120 <.L35> - -00000152 <.L37>: - 152: 00f47793 and a5,s0,15 - 156: 45b1 li a1,12 - -00000158 <.LVL50>: - 158: faf5e7e3 bltu a1,a5,106 <.L31> - 15c: 000005b7 lui a1,0x0 - 160: 078a sll a5,a5,0x2 - 162: 00058593 mv a1,a1 - 166: 97ae add a5,a5,a1 - 168: 439c lw a5,0(a5) - 16a: 8782 jr a5 - -0000016c <.L47>: - 16c: 006c add a1,sp,12 - 16e: 8526 mv a0,s1 - -00000170 <.LVL51>: - 170: c436 sw a3,8(sp) - 172: c232 sw a2,4(sp) - 174: 00000097 auipc ra,0x0 - 178: 000080e7 jalr ra # 174 <.LVL51+0x4> - -0000017c <.L56>: - 17c: 47b2 lw a5,12(sp) - -0000017e <.LBE160>: - 17e: 4612 lw a2,4(sp) - 180: 46a2 lw a3,8(sp) - -00000182 <.L49>: - 182: dbc5 beqz a5,132 <.L38> - 184: 45c1 li a1,16 - 186: 00b69363 bne a3,a1,18c <.L50> - 18a: 8626 mv a2,s1 - -0000018c <.L50>: - 18c: 01841713 sll a4,s0,0x18 - 190: 8761 sra a4,a4,0x18 - 192: 97b2 add a5,a5,a2 - 194: f8075fe3 bgez a4,132 <.L38> - 198: 439c lw a5,0(a5) - 19a: bf61 j 132 <.L38> - -0000019c <.L43>: - 19c: 006c add a1,sp,12 - 19e: 8526 mv a0,s1 - -000001a0 <.LVL58>: - 1a0: c436 sw a3,8(sp) - 1a2: c232 sw a2,4(sp) - 1a4: 00000097 auipc ra,0x0 - 1a8: 000080e7 jalr ra # 1a4 <.LVL58+0x4> - -000001ac <.LVL59>: - 1ac: bfc1 j 17c <.L56> - -000001ae <.L46>: - 1ae: 0014c783 lbu a5,1(s1) - 1b2: 0004c583 lbu a1,0(s1) - 1b6: 07a2 sll a5,a5,0x8 - 1b8: 8fcd or a5,a5,a1 - -000001ba <.L57>: - 1ba: 00248513 add a0,s1,2 - -000001be <.LVL62>: - 1be: b7d1 j 182 <.L49> - -000001c0 <.L42>: - 1c0: 0014c783 lbu a5,1(s1) - 1c4: 0004c583 lbu a1,0(s1) - 1c8: 07a2 sll a5,a5,0x8 - 1ca: 8fcd or a5,a5,a1 - 1cc: 07c2 sll a5,a5,0x10 - 1ce: 87c1 sra a5,a5,0x10 - 1d0: b7ed j 1ba <.L57> - -000001d2 <.L41>: - 1d2: 0014c783 lbu a5,1(s1) - 1d6: 0004c583 lbu a1,0(s1) - 1da: 00448513 add a0,s1,4 - -000001de <.LVL64>: - 1de: 07a2 sll a5,a5,0x8 - 1e0: 8fcd or a5,a5,a1 - 1e2: 0024c583 lbu a1,2(s1) - 1e6: 05c2 sll a1,a1,0x10 - 1e8: 8ddd or a1,a1,a5 - 1ea: 0034c783 lbu a5,3(s1) - 1ee: 07e2 sll a5,a5,0x18 - 1f0: 8fcd or a5,a5,a1 - -000001f2 <.LVL65>: - 1f2: bf41 j 182 <.L49> - -000001f4 <.L39>: - 1f4: 0014c783 lbu a5,1(s1) - 1f8: 0004c583 lbu a1,0(s1) - 1fc: 00848513 add a0,s1,8 - -00000200 <.LVL67>: - 200: 07a2 sll a5,a5,0x8 - 202: 8fcd or a5,a5,a1 - 204: 0024c583 lbu a1,2(s1) - 208: 05c2 sll a1,a1,0x10 - 20a: 8ddd or a1,a1,a5 - 20c: 0034c783 lbu a5,3(s1) - 210: 07e2 sll a5,a5,0x18 - 212: 8fcd or a5,a5,a1 - -00000214 <.LVL68>: - 214: b7bd j 182 <.L49> - -00000216 : - 216: fd410113 add sp,sp,-44 - 21a: d222 sw s0,36(sp) - 21c: d026 sw s1,32(sp) - 21e: d406 sw ra,40(sp) - 220: 1060 add s0,sp,44 - 222: 832a mv t1,a0 - 224: fcb42c23 sw a1,-40(s0) - 228: fcc42e23 sw a2,-36(s0) - 22c: 84b6 mv s1,a3 - 22e: 2006ac23 sw zero,536(a3) - 232: fe042223 sw zero,-28(s0) - -00000236 <.L59>: - 236: fd842783 lw a5,-40(s0) - 23a: 02f37263 bgeu t1,a5,25e <.L58> - 23e: 22c4a783 lw a5,556(s1) - 242: fef42023 sw a5,-32(s0) - -00000246 <.LBB167>: - 246: fdc42783 lw a5,-36(s0) - 24a: 1247a703 lw a4,292(a5) - -0000024e <.LBE167>: - 24e: 1107a783 lw a5,272(a5) - -00000252 <.LBB170>: - 252: 837d srl a4,a4,0x1f - -00000254 <.LBE170>: - 254: 97ba add a5,a5,a4 - 256: fe042703 lw a4,-32(s0) - 25a: 00f76a63 bltu a4,a5,26e <.L116> - -0000025e <.L58>: - 25e: fd440113 add sp,s0,-44 - 262: 50a2 lw ra,40(sp) - 264: 5412 lw s0,36(sp) - -00000266 <.LVL72>: - 266: 5482 lw s1,32(sp) - -00000268 <.LVL73>: - 268: 02c10113 add sp,sp,44 - 26c: 8082 ret - -0000026e <.L116>: - 26e: 00034703 lbu a4,0(t1) - 272: 04000613 li a2,64 - 276: 00130793 add a5,t1,1 - -0000027a <.LVL75>: - 27a: 0c077693 and a3,a4,192 - 27e: 02c69463 bne a3,a2,2a6 <.L60> - 282: 2384a583 lw a1,568(s1) - 286: fcf42a23 sw a5,-44(s0) - 28a: 03f77513 and a0,a4,63 - 28e: 00000097 auipc ra,0x0 - 292: 000080e7 jalr ra # 28e <.LVL75+0x14> - -00000296 <.LVL76>: - 296: fe042783 lw a5,-32(s0) - 29a: 953e add a0,a0,a5 - 29c: 22a4a623 sw a0,556(s1) - -000002a0 <.L120>: - 2a0: fd442783 lw a5,-44(s0) - 2a4: a859 j 33a <.L64> - -000002a6 <.L60>: - 2a6: 08000613 li a2,128 - 2aa: 04c69163 bne a3,a2,2ec <.L63> - 2ae: fec40593 add a1,s0,-20 - 2b2: 853e mv a0,a5 - 2b4: fce42a23 sw a4,-44(s0) - 2b8: 00000097 auipc ra,0x0 - 2bc: 000080e7 jalr ra # 2b8 <.L60+0x12> - -000002c0 <.LVL78>: - 2c0: fea42023 sw a0,-32(s0) - 2c4: fec42583 lw a1,-20(s0) - 2c8: 2344a503 lw a0,564(s1) - -000002cc <.LVL79>: - 2cc: 00000097 auipc ra,0x0 - 2d0: 000080e7 jalr ra # 2cc <.LVL79> - -000002d4 <.LVL80>: - 2d4: fd442703 lw a4,-44(s0) - 2d8: 4685 li a3,1 - 2da: 03f77713 and a4,a4,63 - 2de: 070e sll a4,a4,0x3 - 2e0: 9726 add a4,a4,s1 - 2e2: c354 sw a3,4(a4) - 2e4: c308 sw a0,0(a4) - -000002e6 <.L119>: - 2e6: fe042783 lw a5,-32(s0) - 2ea: a881 j 33a <.L64> - -000002ec <.L63>: - 2ec: 0c000613 li a2,192 - 2f0: 00c69963 bne a3,a2,302 <.L65> - 2f4: 03f77713 and a4,a4,63 - -000002f8 <.L124>: - 2f8: 070e sll a4,a4,0x3 - 2fa: 9726 add a4,a4,s1 - 2fc: 00072223 sw zero,4(a4) - 300: a82d j 33a <.L64> - -00000302 <.L65>: - 302: 02f00693 li a3,47 - 306: 44e6e863 bltu a3,a4,756 <.L66> - 30a: 000006b7 lui a3,0x0 - 30e: 070a sll a4,a4,0x2 - -00000310 <.LVL85>: - 310: 00068693 mv a3,a3 - 314: 9736 add a4,a4,a3 - 316: 4318 lw a4,0(a4) - 318: 8702 jr a4 - -0000031a <.L92>: - 31a: 2404c583 lbu a1,576(s1) - 31e: fdc42503 lw a0,-36(s0) - 322: 863e mv a2,a5 - 324: ff040693 add a3,s0,-16 - 328: 00000097 auipc ra,0x0 - 32c: 000080e7 jalr ra # 328 <.L92+0xe> - -00000330 <.LVL86>: - 330: ff042703 lw a4,-16(s0) - 334: 87aa mv a5,a0 - 336: 22e4a623 sw a4,556(s1) - -0000033a <.L64>: - 33a: 833e mv t1,a5 - 33c: bded j 236 <.L59> - -0000033e <.L91>: - 33e: 00134503 lbu a0,1(t1) - 342: 2384a583 lw a1,568(s1) - 346: fc642a23 sw t1,-44(s0) - 34a: 00000097 auipc ra,0x0 - 34e: 000080e7 jalr ra # 34a <.L91+0xc> - -00000352 <.LVL89>: - 352: fe042783 lw a5,-32(s0) - 356: fd442303 lw t1,-44(s0) - 35a: 953e add a0,a0,a5 - 35c: 22a4a623 sw a0,556(s1) - -00000360 <.LVL90>: - 360: 00230793 add a5,t1,2 - -00000364 <.LVL91>: - 364: bfd9 j 33a <.L64> - -00000366 <.L90>: - 366: 00234783 lbu a5,2(t1) - -0000036a <.LVL93>: - 36a: 00134503 lbu a0,1(t1) - -0000036e <.LBE175>: - 36e: 2384a583 lw a1,568(s1) - -00000372 <.LBB178>: - 372: 07a2 sll a5,a5,0x8 - 374: fc642a23 sw t1,-44(s0) - -00000378 <.LBE178>: - 378: 8d5d or a0,a0,a5 - 37a: 00000097 auipc ra,0x0 - 37e: 000080e7 jalr ra # 37a <.LBE178+0x2> - -00000382 <.LVL94>: - 382: fe042783 lw a5,-32(s0) - 386: fd442303 lw t1,-44(s0) - 38a: 953e add a0,a0,a5 - 38c: 22a4a623 sw a0,556(s1) - -00000390 <.LVL95>: - 390: 00330793 add a5,t1,3 - -00000394 <.LVL96>: - 394: b75d j 33a <.L64> - -00000396 <.L89>: - 396: 00234703 lbu a4,2(t1) - 39a: 00134783 lbu a5,1(t1) - -0000039e <.LVL98>: - 39e: 00434503 lbu a0,4(t1) - 3a2: 0722 sll a4,a4,0x8 - 3a4: 8f5d or a4,a4,a5 - 3a6: 00334783 lbu a5,3(t1) - -000003aa <.LBE179>: - 3aa: 2384a583 lw a1,568(s1) - -000003ae <.LBB182>: - 3ae: 0562 sll a0,a0,0x18 - 3b0: 07c2 sll a5,a5,0x10 - 3b2: 8fd9 or a5,a5,a4 - 3b4: fc642a23 sw t1,-44(s0) - -000003b8 <.LBE182>: - 3b8: 8d5d or a0,a0,a5 - 3ba: 00000097 auipc ra,0x0 - 3be: 000080e7 jalr ra # 3ba <.LBE182+0x2> - -000003c2 <.LVL99>: - 3c2: fe042783 lw a5,-32(s0) - 3c6: fd442303 lw t1,-44(s0) - 3ca: 953e add a0,a0,a5 - 3cc: 22a4a623 sw a0,556(s1) - -000003d0 <.LVL100>: - 3d0: 00530793 add a5,t1,5 - -000003d4 <.LVL101>: - 3d4: b79d j 33a <.L64> - -000003d6 <.L88>: - 3d6: fe840593 add a1,s0,-24 - 3da: 853e mv a0,a5 - 3dc: 00000097 auipc ra,0x0 - 3e0: 000080e7 jalr ra # 3dc <.L88+0x6> - -000003e4 <.LVL103>: - 3e4: fec40593 add a1,s0,-20 - 3e8: 00000097 auipc ra,0x0 - 3ec: 000080e7 jalr ra # 3e8 <.LVL103+0x4> - -000003f0 <.LVL104>: - 3f0: fec42583 lw a1,-20(s0) - 3f4: fea42023 sw a0,-32(s0) - -000003f8 <.L134>: - 3f8: 2344a503 lw a0,564(s1) - -000003fc <.LVL106>: - 3fc: 00000097 auipc ra,0x0 - 400: 000080e7 jalr ra # 3fc <.LVL106> - -00000404 <.LVL107>: - 404: fe842703 lw a4,-24(s0) - 408: 04200693 li a3,66 - 40c: fe042783 lw a5,-32(s0) - 410: f2e6e5e3 bltu a3,a4,33a <.L64> - 414: 070e sll a4,a4,0x3 - 416: 9726 add a4,a4,s1 - 418: 4685 li a3,1 - -0000041a <.L129>: - 41a: c354 sw a3,4(a4) - -0000041c <.L121>: - 41c: c308 sw a0,0(a4) - 41e: bf31 j 33a <.L64> - -00000420 <.L85>: - 420: 853e mv a0,a5 - 422: fe840593 add a1,s0,-24 - 426: 00000097 auipc ra,0x0 - 42a: 000080e7 jalr ra # 426 <.L85+0x6> - -0000042e <.LVL110>: - 42e: fe842703 lw a4,-24(s0) - 432: 04200693 li a3,66 - 436: 87aa mv a5,a0 - 438: ece6f0e3 bgeu a3,a4,2f8 <.L124> - 43c: bdfd j 33a <.L64> - -0000043e <.L86>: - 43e: 853e mv a0,a5 - 440: fe840593 add a1,s0,-24 - 444: 00000097 auipc ra,0x0 - 448: 000080e7 jalr ra # 444 <.L86+0x6> - -0000044c <.LVL112>: - 44c: fe842703 lw a4,-24(s0) - 450: 04200693 li a3,66 - 454: 87aa mv a5,a0 - 456: eee6e2e3 bltu a3,a4,33a <.L64> - 45a: 070e sll a4,a4,0x3 - 45c: 9726 add a4,a4,s1 - 45e: 4699 li a3,6 - 460: c354 sw a3,4(a4) - 462: bde1 j 33a <.L64> - -00000464 <.L84>: - 464: 853e mv a0,a5 - 466: fe840593 add a1,s0,-24 - 46a: 00000097 auipc ra,0x0 - 46e: 000080e7 jalr ra # 46a <.L84+0x6> - -00000472 <.LVL114>: - 472: ff040593 add a1,s0,-16 - 476: 00000097 auipc ra,0x0 - 47a: 000080e7 jalr ra # 476 <.LVL114+0x4> - -0000047e <.LVL115>: - 47e: fe842703 lw a4,-24(s0) - 482: 04200693 li a3,66 - 486: 87aa mv a5,a0 - -00000488 <.LVL116>: - 488: eae6e9e3 bltu a3,a4,33a <.L64> - 48c: 070e sll a4,a4,0x3 - 48e: 9726 add a4,a4,s1 - 490: 4689 li a3,2 - 492: c354 sw a3,4(a4) - 494: ff042683 lw a3,-16(s0) - 498: c314 sw a3,0(a4) - -0000049a <.LBE183>: - 49a: b545 j 33a <.L64> - -0000049c <.L83>: - 49c: fe442703 lw a4,-28(s0) - 4a0: c315 beqz a4,4c4 <.L102> - -000004a2 <.LVL118>: - 4a2: 21872683 lw a3,536(a4) - 4a6: fed42223 sw a3,-28(s0) - -000004aa <.L103>: - 4aa: 22c00613 li a2,556 - 4ae: 85a6 mv a1,s1 - 4b0: 853a mv a0,a4 - 4b2: fef42023 sw a5,-32(s0) - -000004b6 <.LVL120>: - 4b6: 00000097 auipc ra,0x0 - 4ba: 000080e7 jalr ra # 4b6 <.LVL120> - -000004be <.LVL121>: - 4be: 20a4ac23 sw a0,536(s1) - 4c2: b515 j 2e6 <.L119> - -000004c4 <.L102>: - 4c4: dc810113 add sp,sp,-568 - 4c8: 00f10713 add a4,sp,15 - 4cc: 9b41 and a4,a4,-16 - -000004ce <.LVL123>: - 4ce: bff1 j 4aa <.L103> - -000004d0 <.L82>: - 4d0: 2184a583 lw a1,536(s1) - 4d4: 22c00613 li a2,556 - 4d8: 8526 mv a0,s1 - 4da: fcf42a23 sw a5,-44(s0) - -000004de <.LVL125>: - 4de: feb42023 sw a1,-32(s0) - 4e2: 00000097 auipc ra,0x0 - 4e6: 000080e7 jalr ra # 4e2 <.LVL125+0x4> - -000004ea <.LVL126>: - 4ea: fe442783 lw a5,-28(s0) - 4ee: fe042583 lw a1,-32(s0) - 4f2: 20f5ac23 sw a5,536(a1) # 218 - -000004f6 <.LBE185>: - 4f6: feb42223 sw a1,-28(s0) - 4fa: b35d j 2a0 <.L120> - -000004fc <.L81>: - 4fc: fec40593 add a1,s0,-20 - 500: 853e mv a0,a5 - 502: 00000097 auipc ra,0x0 - 506: 000080e7 jalr ra # 502 <.L81+0x6> - -0000050a <.LVL129>: - 50a: fec42783 lw a5,-20(s0) - 50e: fec40593 add a1,s0,-20 - 512: 22f4a023 sw a5,544(s1) - 516: 00000097 auipc ra,0x0 - 51a: 000080e7 jalr ra # 516 <.LVL129+0xc> - -0000051e <.LVL130>: - 51e: fec42703 lw a4,-20(s0) - 522: 87aa mv a5,a0 - -00000524 <.LVL131>: - 524: 20e4ae23 sw a4,540(s1) - -00000528 <.L123>: - 528: 4705 li a4,1 - 52a: 22e4a423 sw a4,552(s1) - 52e: b531 j 33a <.L64> - -00000530 <.L80>: - 530: 853e mv a0,a5 - 532: fec40593 add a1,s0,-20 - 536: 00000097 auipc ra,0x0 - 53a: 000080e7 jalr ra # 536 <.L80+0x6> - -0000053e <.LVL133>: - 53e: fec42703 lw a4,-20(s0) - 542: 87aa mv a5,a0 - 544: 22e4a023 sw a4,544(s1) - 548: b7c5 j 528 <.L123> - -0000054a <.L79>: - 54a: 853e mv a0,a5 - 54c: fec40593 add a1,s0,-20 - 550: 00000097 auipc ra,0x0 - 554: 000080e7 jalr ra # 550 <.L79+0x6> - -00000558 <.LVL135>: - 558: fec42703 lw a4,-20(s0) - 55c: 87aa mv a5,a0 - 55e: 20e4ae23 sw a4,540(s1) - 562: bbe1 j 33a <.L64> - -00000564 <.L78>: - 564: 4709 li a4,2 - 566: 22f4a223 sw a5,548(s1) - -0000056a <.LVL137>: - 56a: 22e4a423 sw a4,552(s1) - 56e: fec40593 add a1,s0,-20 - 572: 853e mv a0,a5 - -00000574 <.L125>: - 574: 00000097 auipc ra,0x0 - 578: 000080e7 jalr ra # 574 <.L125> - -0000057c <.LVL139>: - 57c: fec42703 lw a4,-20(s0) - 580: 00e507b3 add a5,a0,a4 - -00000584 <.LVL140>: - 584: bb5d j 33a <.L64> - -00000586 <.L77>: - 586: 853e mv a0,a5 - 588: fe840593 add a1,s0,-24 - 58c: 00000097 auipc ra,0x0 - 590: 000080e7 jalr ra # 58c <.L77+0x6> - -00000594 <.LVL142>: - 594: fe842783 lw a5,-24(s0) - 598: 04200713 li a4,66 - 59c: 00f76763 bltu a4,a5,5aa <.L111> - 5a0: 078e sll a5,a5,0x3 - 5a2: 97a6 add a5,a5,s1 - 5a4: 470d li a4,3 - -000005a6 <.L127>: - 5a6: c3d8 sw a4,4(a5) - 5a8: c388 sw a0,0(a5) - -000005aa <.L111>: - 5aa: fec40593 add a1,s0,-20 - 5ae: b7d9 j 574 <.L125> - -000005b0 <.L76>: - 5b0: fe840593 add a1,s0,-24 - 5b4: 853e mv a0,a5 - 5b6: 00000097 auipc ra,0x0 - 5ba: 000080e7 jalr ra # 5b6 <.L76+0x6> - -000005be <.LVL144>: - 5be: ff040593 add a1,s0,-16 - 5c2: 00000097 auipc ra,0x0 - 5c6: 000080e7 jalr ra # 5c2 <.LVL144+0x4> - -000005ca <.LVL145>: - 5ca: ff042583 lw a1,-16(s0) - 5ce: fea42023 sw a0,-32(s0) - -000005d2 <.LVL146>: - 5d2: b51d j 3f8 <.L134> - -000005d4 <.L75>: - 5d4: fec40593 add a1,s0,-20 - 5d8: 853e mv a0,a5 - 5da: 00000097 auipc ra,0x0 - 5de: 000080e7 jalr ra # 5da <.L75+0x6> - -000005e2 <.LVL148>: - 5e2: fec42783 lw a5,-20(s0) - 5e6: 20048713 add a4,s1,512 - 5ea: ff040593 add a1,s0,-16 - 5ee: d31c sw a5,32(a4) - 5f0: fee42023 sw a4,-32(s0) - 5f4: 00000097 auipc ra,0x0 - 5f8: 000080e7 jalr ra # 5f4 <.LVL148+0x12> - -000005fc <.LVL149>: - 5fc: fe042703 lw a4,-32(s0) - 600: fca42a23 sw a0,-44(s0) - -00000604 <.LVL150>: - 604: ff042583 lw a1,-16(s0) - 608: 5b48 lw a0,52(a4) - -0000060a <.LVL151>: - 60a: 4685 li a3,1 - 60c: d714 sw a3,40(a4) - 60e: 00000097 auipc ra,0x0 - 612: 000080e7 jalr ra # 60e <.LVL151+0x4> - -00000616 <.LVL152>: - 616: fe042703 lw a4,-32(s0) - 61a: cf48 sw a0,28(a4) - 61c: b151 j 2a0 <.L120> - -0000061e <.L74>: - 61e: ff040593 add a1,s0,-16 - 622: 853e mv a0,a5 - 624: 00000097 auipc ra,0x0 - 628: 000080e7 jalr ra # 624 <.L74+0x6> - -0000062c <.LVL154>: - 62c: fea42023 sw a0,-32(s0) - 630: 2344a583 lw a1,564(s1) - 634: ff042503 lw a0,-16(s0) - -00000638 <.LVL155>: - 638: 00000097 auipc ra,0x0 - 63c: 000080e7 jalr ra # 638 <.LVL155> - -00000640 <.LVL156>: - 640: 20a4ae23 sw a0,540(s1) - 644: b14d j 2e6 <.L119> - -00000646 <.L73>: - 646: fe840593 add a1,s0,-24 - 64a: 853e mv a0,a5 - 64c: 00000097 auipc ra,0x0 - 650: 000080e7 jalr ra # 64c <.L73+0x6> - -00000654 <.LVL158>: - 654: fec40593 add a1,s0,-20 - 658: 00000097 auipc ra,0x0 - 65c: 000080e7 jalr ra # 658 <.LVL158+0x4> - -00000660 <.LVL159>: - 660: fec42583 lw a1,-20(s0) - 664: fea42023 sw a0,-32(s0) - -00000668 <.L131>: - 668: 2344a503 lw a0,564(s1) - -0000066c <.LVL161>: - 66c: 00000097 auipc ra,0x0 - 670: 000080e7 jalr ra # 66c <.LVL161> - -00000674 <.LVL162>: - 674: fe842703 lw a4,-24(s0) - 678: 04200693 li a3,66 - 67c: fe042783 lw a5,-32(s0) - 680: cae6ede3 bltu a3,a4,33a <.L64> - 684: 070e sll a4,a4,0x3 - 686: 9726 add a4,a4,s1 - 688: 4691 li a3,4 - 68a: bb41 j 41a <.L129> - -0000068c <.L72>: - 68c: fe840593 add a1,s0,-24 - 690: 853e mv a0,a5 - 692: 00000097 auipc ra,0x0 - 696: 000080e7 jalr ra # 692 <.L72+0x6> - -0000069a <.LVL164>: - 69a: ff040593 add a1,s0,-16 - 69e: 00000097 auipc ra,0x0 - 6a2: 000080e7 jalr ra # 69e <.LVL164+0x4> - -000006a6 <.LVL165>: - 6a6: ff042583 lw a1,-16(s0) - 6aa: fea42023 sw a0,-32(s0) - -000006ae <.LVL166>: - 6ae: bf6d j 668 <.L131> - -000006b0 <.L71>: - 6b0: 853e mv a0,a5 - 6b2: fe840593 add a1,s0,-24 - 6b6: 00000097 auipc ra,0x0 - 6ba: 000080e7 jalr ra # 6b6 <.L71+0x6> - -000006be <.LVL168>: - 6be: fe842783 lw a5,-24(s0) - 6c2: 04200713 li a4,66 - 6c6: eef762e3 bltu a4,a5,5aa <.L111> - 6ca: 078e sll a5,a5,0x3 - 6cc: 97a6 add a5,a5,s1 - 6ce: 4715 li a4,5 - 6d0: bdd9 j 5a6 <.L127> - -000006d2 <.L70>: - 6d2: 08048693 add a3,s1,128 - 6d6: 4701 li a4,0 - 6d8: 4585 li a1,1 - 6da: 04000613 li a2,64 - -000006de <.L112>: - 6de: c298 sw a4,0(a3) - 6e0: c2cc sw a1,4(a3) - 6e2: 0711 add a4,a4,4 - 6e4: 06a1 add a3,a3,8 # 8 <.L2+0x4> - 6e6: fec71ce3 bne a4,a2,6de <.L112> - 6ea: b981 j 33a <.L64> - -000006ec <.L69>: - 6ec: 853e mv a0,a5 - 6ee: fec40593 add a1,s0,-20 - 6f2: 00000097 auipc ra,0x0 - 6f6: 000080e7 jalr ra # 6f2 <.L69+0x6> - -000006fa <.LVL172>: - 6fa: fec42703 lw a4,-20(s0) - 6fe: fdc42683 lw a3,-36(s0) - 702: 87aa mv a5,a0 - 704: 12e6a623 sw a4,300(a3) - 708: b90d j 33a <.L64> - -0000070a <.L67>: - 70a: 853e mv a0,a5 - 70c: fe840593 add a1,s0,-24 - 710: 00000097 auipc ra,0x0 - 714: 000080e7 jalr ra # 710 <.L67+0x6> - -00000718 <.LVL174>: - 718: fec40593 add a1,s0,-20 - 71c: 00000097 auipc ra,0x0 - 720: 000080e7 jalr ra # 71c <.LVL174+0x4> - -00000724 <.LVL175>: - 724: fea42023 sw a0,-32(s0) - -00000728 <.LVL176>: - 728: fec42583 lw a1,-20(s0) - 72c: 2344a503 lw a0,564(s1) - -00000730 <.LVL177>: - 730: 00000097 auipc ra,0x0 - 734: 000080e7 jalr ra # 730 <.LVL177> - -00000738 <.LVL178>: - 738: fe842703 lw a4,-24(s0) - 73c: 04200693 li a3,66 - 740: fe042783 lw a5,-32(s0) - 744: bee6ebe3 bltu a3,a4,33a <.L64> - 748: 070e sll a4,a4,0x3 - 74a: 9726 add a4,a4,s1 - 74c: 4685 li a3,1 - 74e: c354 sw a3,4(a4) - 750: 40a00533 neg a0,a0 - -00000754 <.LVL179>: - 754: b1e1 j 41c <.L121> - -00000756 <.L66>: - 756: 00000097 auipc ra,0x0 - 75a: 000080e7 jalr ra # 756 <.L66> - -0000075e : - 75e: fd810113 add sp,sp,-40 - 762: d022 sw s0,32(sp) - 764: 842e mv s0,a1 - 766: ce26 sw s1,28(sp) - 768: 24800613 li a2,584 - 76c: 84aa mv s1,a0 - 76e: 4581 li a1,0 - -00000770 <.LVL183>: - 770: 8522 mv a0,s0 - -00000772 <.LVL184>: - 772: d206 sw ra,36(sp) - 774: 00000097 auipc ra,0x0 - 778: 000080e7 jalr ra # 774 <.LVL184+0x2> - -0000077c <.LVL185>: - 77c: 1104a503 lw a0,272(s1) - 780: 1204a623 sw zero,300(s1) - 784: 1004aa23 sw zero,276(s1) - 788: e901 bnez a0,798 <.L136> - -0000078a <.L138>: - 78a: 4515 li a0,5 - -0000078c <.L135>: - 78c: 5092 lw ra,36(sp) - 78e: 5402 lw s0,32(sp) - -00000790 <.LVL186>: - 790: 44f2 lw s1,28(sp) - -00000792 <.LVL187>: - 792: 02810113 add sp,sp,40 - 796: 8082 ret - -00000798 <.L136>: - 798: 1244a783 lw a5,292(s1) - -0000079c <.LBE203>: - 79c: 11848593 add a1,s1,280 - -000007a0 <.LBB206>: - 7a0: 83fd srl a5,a5,0x1f - -000007a2 <.LBE206>: - 7a2: 17fd add a5,a5,-1 - 7a4: 953e add a0,a0,a5 - 7a6: 00000097 auipc ra,0x0 - 7aa: 000080e7 jalr ra # 7a6 <.LBE206+0x4> - -000007ae <.LVL189>: - 7ae: c42a sw a0,8(sp) - -000007b0 <.LVL190>: - 7b0: dd69 beqz a0,78a <.L138> - 7b2: 1204a783 lw a5,288(s1) - -000007b6 <.LBB207>: - 7b6: 4158 lw a4,4(a0) - -000007b8 <.LBE207>: - 7b8: 22f42623 sw a5,556(s0) - -000007bc <.LBB210>: - 7bc: 00450793 add a5,a0,4 - 7c0: 8f99 sub a5,a5,a4 - 7c2: c03e sw a5,0(sp) - -000007c4 <.LBB211>: - 7c4: 07a5 add a5,a5,9 - -000007c6 <.LVL193>: - 7c6: 853e mv a0,a5 - -000007c8 <.LVL194>: - 7c8: c23e sw a5,4(sp) - -000007ca <.LVL195>: - 7ca: 00000097 auipc ra,0x0 - 7ce: 000080e7 jalr ra # 7ca <.LVL195> - -000007d2 <.LVL196>: - 7d2: 4792 lw a5,4(sp) - 7d4: 0505 add a0,a0,1 - 7d6: 953e add a0,a0,a5 - -000007d8 <.LVL197>: - 7d8: 4782 lw a5,0(sp) - 7da: 0097c703 lbu a4,9(a5) - 7de: 06500793 li a5,101 - 7e2: 02f71d63 bne a4,a5,81c <.L139> - 7e6: 4782 lw a5,0(sp) - 7e8: 00a7c703 lbu a4,10(a5) - 7ec: 06800793 li a5,104 - 7f0: 02f71663 bne a4,a5,81c <.L139> - -000007f4 <.LBB213>: - 7f4: 00154783 lbu a5,1(a0) - 7f8: 00054703 lbu a4,0(a0) - -000007fc <.LBE213>: - 7fc: 0511 add a0,a0,4 - -000007fe <.LBB216>: - 7fe: 07a2 sll a5,a5,0x8 - 800: 8fd9 or a5,a5,a4 - 802: ffe54703 lbu a4,-2(a0) - 806: 0742 sll a4,a4,0x10 - 808: 8f5d or a4,a4,a5 - 80a: fff54783 lbu a5,-1(a0) - 80e: 07e2 sll a5,a5,0x18 - 810: 8fd9 or a5,a5,a4 - -00000812 <.LBE216>: - 812: 24f42223 sw a5,580(s0) - -00000816 <.LVL200>: - 816: 4782 lw a5,0(sp) - 818: 07ad add a5,a5,11 - 81a: c23e sw a5,4(sp) - -0000081c <.L139>: - 81c: 4782 lw a5,0(sp) - 81e: 0087c703 lbu a4,8(a5) - 822: 478d li a5,3 - 824: 00e7fd63 bgeu a5,a4,83e <.L140> - 828: 00054683 lbu a3,0(a0) - 82c: 4791 li a5,4 - 82e: 00f68463 beq a3,a5,836 <.L141> - -00000832 <.L158>: - 832: 450d li a0,3 - 834: bfa1 j 78c <.L135> - -00000836 <.L141>: - 836: 00154783 lbu a5,1(a0) - 83a: ffe5 bnez a5,832 <.L158> - 83c: 0509 add a0,a0,2 - -0000083e <.L140>: - 83e: 080c add a1,sp,16 - 840: c63a sw a4,12(sp) - 842: 00000097 auipc ra,0x0 - 846: 000080e7 jalr ra # 842 <.L140+0x4> - -0000084a <.LVL205>: - 84a: 47c2 lw a5,16(sp) - 84c: 084c add a1,sp,20 - 84e: 22f42c23 sw a5,568(s0) - 852: 00000097 auipc ra,0x0 - 856: 000080e7 jalr ra # 852 <.LVL205+0x8> - -0000085a <.LVL206>: - 85a: 46d2 lw a3,20(sp) - 85c: 4732 lw a4,12(sp) - 85e: 87aa mv a5,a0 - -00000860 <.LVL207>: - 860: 22d42a23 sw a3,564(s0) - 864: 4685 li a3,1 - 866: 04d71863 bne a4,a3,8b6 <.L143> - 86a: 0007c783 lbu a5,0(a5) - 86e: 0505 add a0,a0,1 - -00000870 <.L144>: - 870: 22f42e23 sw a5,572(s0) - 874: 57fd li a5,-1 - 876: 24f400a3 sb a5,577(s0) - 87a: 4792 lw a5,4(sp) - 87c: 07a00713 li a4,122 - 880: 0007c683 lbu a3,0(a5) - 884: 4781 li a5,0 - 886: 00e69f63 bne a3,a4,8a4 <.L145> - 88a: 080c add a1,sp,16 - 88c: 00000097 auipc ra,0x0 - 890: 000080e7 jalr ra # 88c <.L144+0x1c> - -00000894 <.LVL209>: - 894: 4705 li a4,1 - 896: 24e40123 sb a4,578(s0) - 89a: 4712 lw a4,4(sp) - 89c: 47c2 lw a5,16(sp) - 89e: 0705 add a4,a4,1 - 8a0: 97aa add a5,a5,a0 - -000008a2 <.LVL210>: - 8a2: c23a sw a4,4(sp) - -000008a4 <.L145>: - 8a4: 4712 lw a4,4(sp) - 8a6: 00170313 add t1,a4,1 - -000008aa <.L155>: - 8aa: fff34703 lbu a4,-1(t1) - 8ae: eb19 bnez a4,8c4 <.L156> - 8b0: eb8d bnez a5,8e2 <.L154> - 8b2: 87aa mv a5,a0 - -000008b4 <.LVL213>: - 8b4: a035 j 8e0 <.L150> - -000008b6 <.L143>: - 8b6: 080c add a1,sp,16 - 8b8: 00000097 auipc ra,0x0 - 8bc: 000080e7 jalr ra # 8b8 <.L143+0x2> - -000008c0 <.LVL215>: - 8c0: 47c2 lw a5,16(sp) - 8c2: b77d j 870 <.L144> - -000008c4 <.L156>: - 8c4: 05000693 li a3,80 - 8c8: 08d70263 beq a4,a3,94c <.L146> - 8cc: 04e6e863 bltu a3,a4,91c <.L147> - 8d0: 04200693 li a3,66 - 8d4: 06d70563 beq a4,a3,93e <.L153> - 8d8: 04c00693 li a3,76 - 8dc: 04d70c63 beq a4,a3,934 <.L149> - -000008e0 <.L150>: - 8e0: dba9 beqz a5,832 <.L158> - -000008e2 <.L154>: - 8e2: 4702 lw a4,0(sp) - -000008e4 <.LBE227>: - 8e4: 853e mv a0,a5 - 8e6: 86a2 mv a3,s0 - -000008e8 <.LBB228>: - 8e8: 430c lw a1,0(a4) - -000008ea <.LBE228>: - 8ea: 8626 mv a2,s1 - -000008ec <.LBB229>: - 8ec: 0591 add a1,a1,4 - -000008ee <.LBE229>: - 8ee: 95ba add a1,a1,a4 - 8f0: 00000097 auipc ra,0x0 - 8f4: 000080e7 jalr ra # 8f0 <.LBE229+0x2> - -000008f8 <.LVL219>: - 8f8: 24044783 lbu a5,576(s0) - -000008fc <.LBB230>: - 8fc: 0ff00713 li a4,255 - 900: 08e78e63 beq a5,a4,99c <.L167> - 904: 8b9d and a5,a5,7 - -00000906 <.LVL221>: - 906: 4709 li a4,2 - 908: 08e78c63 beq a5,a4,9a0 <.L168> - 90c: 06f76263 bltu a4,a5,970 <.L160> - 910: 4511 li a0,4 - 912: c7b5 beqz a5,97e <.L159> - -00000914 <.L161>: - 914: 00000097 auipc ra,0x0 - 918: 000080e7 jalr ra # 914 <.L161> - -0000091c <.L147>: - 91c: 05200693 li a3,82 - 920: 02d70163 beq a4,a3,942 <.L151> - 924: 05300693 li a3,83 - 928: fad71ce3 bne a4,a3,8e0 <.L150> - -0000092c <.LBB234>: - 92c: 4705 li a4,1 - 92e: 24e401a3 sb a4,579(s0) - -00000932 <.LVL223>: - 932: a031 j 93e <.L153> - -00000934 <.L149>: - 934: 00054703 lbu a4,0(a0) - 938: 24e400a3 sb a4,577(s0) - -0000093c <.L184>: - 93c: 0505 add a0,a0,1 - -0000093e <.L153>: - 93e: 0305 add t1,t1,1 - 940: b7ad j 8aa <.L155> - -00000942 <.L151>: - 942: 00054703 lbu a4,0(a0) - 946: 24e40023 sb a4,576(s0) - 94a: bfcd j 93c <.L184> - -0000094c <.L146>: - 94c: 00054583 lbu a1,0(a0) - 950: 00150613 add a2,a0,1 - 954: 0834 add a3,sp,24 - 956: 8526 mv a0,s1 - -00000958 <.LVL229>: - 958: c61a sw t1,12(sp) - 95a: c23e sw a5,4(sp) - 95c: 00000097 auipc ra,0x0 - 960: 000080e7 jalr ra # 95c <.LVL229+0x4> - -00000964 <.LVL230>: - 964: 4762 lw a4,24(sp) - -00000966 <.LBE217>: - 966: 4792 lw a5,4(sp) - 968: 4332 lw t1,12(sp) - -0000096a <.LBB218>: - 96a: 22e42823 sw a4,560(s0) - -0000096e <.LBE218>: - 96e: bfc1 j 93e <.L153> - -00000970 <.L160>: - 970: 470d li a4,3 - 972: 02e78963 beq a5,a4,9a4 <.L170> - 976: 4711 li a4,4 - 978: 4521 li a0,8 - 97a: f8e79de3 bne a5,a4,914 <.L161> - -0000097e <.L159>: - 97e: 47a2 lw a5,8(sp) - 980: 0506 sll a0,a0,0x1 - 982: 0521 add a0,a0,8 - 984: 953e add a0,a0,a5 - -00000986 <.LVL234>: - 986: 24244783 lbu a5,578(s0) - 98a: ef99 bnez a5,9a8 <.L162> - 98c: 24144583 lbu a1,577(s0) - 990: 0ff00793 li a5,255 - 994: 04f58563 beq a1,a5,9de <.L164> - 998: 4701 li a4,0 - 99a: a025 j 9c2 <.L163> - -0000099c <.L167>: - 99c: 4501 li a0,0 - 99e: b7c5 j 97e <.L159> - -000009a0 <.L168>: - 9a0: 4509 li a0,2 - 9a2: bff1 j 97e <.L159> - -000009a4 <.L170>: - 9a4: 4511 li a0,4 - 9a6: bfe1 j 97e <.L159> - -000009a8 <.L162>: - 9a8: 082c add a1,sp,24 - 9aa: 00000097 auipc ra,0x0 - 9ae: 000080e7 jalr ra # 9aa <.L162+0x2> - -000009b2 <.LVL238>: - 9b2: 4762 lw a4,24(sp) - -000009b4 <.LBE237>: - 9b4: 24144583 lbu a1,577(s0) - 9b8: 0ff00793 li a5,255 - -000009bc <.LBB238>: - 9bc: 972a add a4,a4,a0 - -000009be <.LBE238>: - 9be: 00f58e63 beq a1,a5,9da <.L165> - -000009c2 <.L163>: - 9c2: 862a mv a2,a0 - 9c4: 0834 add a3,sp,24 - 9c6: 8526 mv a0,s1 - -000009c8 <.LVL241>: - 9c8: c03a sw a4,0(sp) - -000009ca <.LVL242>: - 9ca: 00000097 auipc ra,0x0 - 9ce: 000080e7 jalr ra # 9ca <.LVL242> - -000009d2 <.LVL243>: - 9d2: 47e2 lw a5,24(sp) - 9d4: 4702 lw a4,0(sp) - 9d6: 10f4aa23 sw a5,276(s1) - -000009da <.L165>: - 9da: c311 beqz a4,9de <.L164> - 9dc: 853a mv a0,a4 - -000009de <.L164>: - 9de: 47a2 lw a5,8(sp) - -000009e0 <.LBE244>: - 9e0: 86a2 mv a3,s0 - 9e2: 8626 mv a2,s1 - -000009e4 <.LBB245>: - 9e4: 438c lw a1,0(a5) - 9e6: 0591 add a1,a1,4 - -000009e8 <.LBE245>: - 9e8: 95be add a1,a1,a5 - 9ea: 00000097 auipc ra,0x0 - 9ee: 000080e7 jalr ra # 9ea <.LBE245+0x2> - -000009f2 <.LVL245>: - 9f2: 4501 li a0,0 - 9f4: bb61 j 78c <.L135> - -000009f6 <_Unwind_SetSpColumn>: - 9f6: 00000737 lui a4,0x0 - 9fa: 00274683 lbu a3,2(a4) # 2 - 9fe: 4711 li a4,4 - a00: 00e69863 bne a3,a4,a10 <.L186> - a04: c20c sw a1,0(a2) - -00000a06 <.LVL247>: - a06: 4589 li a1,2 - -00000a08 <.LVL248>: - a08: 00000317 auipc t1,0x0 - a0c: 00030067 jr t1 # a08 <.LVL248> - -00000a10 <.L186>: - a10: 1151 add sp,sp,-12 - a12: c406 sw ra,8(sp) - a14: 00000097 auipc ra,0x0 - a18: 000080e7 jalr ra # a14 <.L186+0x4> - -00000a1c <_Unwind_GetGR>: - a1c: 04200793 li a5,66 - a20: 00b7d863 bge a5,a1,a30 <.L190> - -00000a24 <.L193>: - a24: 1151 add sp,sp,-12 - a26: c406 sw ra,8(sp) - a28: 00000097 auipc ra,0x0 - a2c: 000080e7 jalr ra # a28 <.L193+0x4> - -00000a30 <.L190>: - a30: 12452683 lw a3,292(a0) - -00000a34 <.LBE246>: - a34: 00259793 sll a5,a1,0x2 - a38: 97aa add a5,a5,a0 - a3a: 4398 lw a4,0(a5) - -00000a3c <.LBB249>: - a3c: 400007b7 lui a5,0x40000 - a40: 8ff5 and a5,a5,a3 - -00000a42 <.LBE249>: - a42: cb81 beqz a5,a52 <.L191> - a44: 00b507b3 add a5,a0,a1 - a48: 1307c783 lbu a5,304(a5) # 40000130 <.LLST185+0x3fffda08> - a4c: c399 beqz a5,a52 <.L191> - -00000a4e <.LBB250>: - a4e: 853a mv a0,a4 - -00000a50 <.LBE250>: - a50: 8082 ret - -00000a52 <.L191>: - a52: 000007b7 lui a5,0x0 - a56: 00078793 mv a5,a5 - a5a: 97ae add a5,a5,a1 - a5c: 0007c683 lbu a3,0(a5) # 0 - a60: 4791 li a5,4 - a62: fcf691e3 bne a3,a5,a24 <.L193> - a66: 4308 lw a0,0(a4) - -00000a68 <.LVL257>: - a68: 8082 ret - -00000a6a : - a6a: 1111 add sp,sp,-28 - a6c: ca22 sw s0,20(sp) - a6e: 842e mv s0,a1 - a70: c826 sw s1,16(sp) - a72: 4589 li a1,2 - -00000a74 <.LVL259>: - a74: 84aa mv s1,a0 - a76: 8522 mv a0,s0 - -00000a78 <.LVL260>: - a78: cc06 sw ra,24(sp) - a7a: 00000097 auipc ra,0x0 - a7e: 000080e7 jalr ra # a7a <.LVL260+0x2> - -00000a82 <.LVL261>: - a82: e909 bnez a0,a94 <.L203> - a84: 10c42583 lw a1,268(s0) - a88: 0030 add a2,sp,8 - a8a: 8522 mv a0,s0 - a8c: 00000097 auipc ra,0x0 - a90: 000080e7 jalr ra # a8c <.LVL261+0xa> - -00000a94 <.L203>: - a94: 13000713 li a4,304 - a98: 4781 li a5,0 - -00000a9a <.L208>: - a9a: 00279693 sll a3,a5,0x2 - a9e: 00d48633 add a2,s1,a3 - aa2: 96a2 add a3,a3,s0 - aa4: 428c lw a1,0(a3) - aa6: 00e486b3 add a3,s1,a4 - aaa: 0006c683 lbu a3,0(a3) - aae: 4208 lw a0,0(a2) - -00000ab0 <.LVL264>: - ab0: c689 beqz a3,aba <.L204> - -00000ab2 <.L207>: - ab2: 00000097 auipc ra,0x0 - ab6: 000080e7 jalr ra # ab2 <.L207> - -00000aba <.L204>: - aba: 00e406b3 add a3,s0,a4 - abe: 0006c683 lbu a3,0(a3) - ac2: c6bd beqz a3,b30 <.L205> - ac4: c515 beqz a0,af0 <.L206> - ac6: c23a sw a4,4(sp) - -00000ac8 <.LBB253>: - ac8: 00000737 lui a4,0x0 - acc: 00070693 mv a3,a4 - ad0: 96be add a3,a3,a5 - ad2: 0006c603 lbu a2,0(a3) - ad6: c03e sw a5,0(sp) - ad8: 4691 li a3,4 - ada: fcd61ce3 bne a2,a3,ab2 <.L207> - ade: c62e sw a1,12(sp) - ae0: 4611 li a2,4 - ae2: 006c add a1,sp,12 - -00000ae4 <.LVL266>: - ae4: 00000097 auipc ra,0x0 - ae8: 000080e7 jalr ra # ae4 <.LVL266> - -00000aec <.LBE253>: - aec: 4782 lw a5,0(sp) - aee: 4712 lw a4,4(sp) - -00000af0 <.L206>: - af0: 0785 add a5,a5,1 - -00000af2 <.LVL269>: - af2: 04200693 li a3,66 - af6: 0705 add a4,a4,1 # 1 - af8: fad791e3 bne a5,a3,a9a <.L208> - afc: 4589 li a1,2 - afe: 8526 mv a0,s1 - b00: 00000097 auipc ra,0x0 - b04: 000080e7 jalr ra # b00 <.LVL269+0xe> - -00000b08 <.LVL270>: - b08: 87aa mv a5,a0 - b0a: 4501 li a0,0 - b0c: ef89 bnez a5,b26 <.L202> - -00000b0e <.LBB254>: - b0e: 4589 li a1,2 - b10: 8522 mv a0,s0 - b12: 00000097 auipc ra,0x0 - b16: 000080e7 jalr ra # b12 <.LBB254+0x4> - -00000b1a <.LBE255>: - b1a: 10c4a783 lw a5,268(s1) - b1e: 8d1d sub a0,a0,a5 - -00000b20 <.LVL273>: - b20: 12c42783 lw a5,300(s0) - b24: 953e add a0,a0,a5 - -00000b26 <.L202>: - b26: 40e2 lw ra,24(sp) - b28: 4452 lw s0,20(sp) - -00000b2a <.LVL275>: - b2a: 44c2 lw s1,16(sp) - -00000b2c <.LVL276>: - b2c: 0171 add sp,sp,28 - b2e: 8082 ret - -00000b30 <.L205>: - b30: d1e1 beqz a1,af0 <.L206> - b32: dd5d beqz a0,af0 <.L206> - b34: fab50ee3 beq a0,a1,af0 <.L206> - b38: c23a sw a4,4(sp) - b3a: 00000737 lui a4,0x0 - b3e: 00070693 mv a3,a4 - b42: 96be add a3,a3,a5 - b44: 0006c603 lbu a2,0(a3) - b48: c03e sw a5,0(sp) - b4a: 00000097 auipc ra,0x0 - b4e: 000080e7 jalr ra # b4a <.L205+0x1a> - -00000b52 <.LVL278>: - b52: 4712 lw a4,4(sp) - b54: 4782 lw a5,0(sp) - b56: bf69 j af0 <.L206> - -00000b58 : - b58: ed810113 add sp,sp,-296 - b5c: 10912e23 sw s1,284(sp) - b60: 12112223 sw ra,292(sp) - b64: 12812023 sw s0,288(sp) - b68: c22e sw a1,4(sp) - b6a: c032 sw a2,0(sp) - b6c: ce36 sw a3,28(sp) - -00000b6e <.LVL280>: - b6e: 4485 li s1,1 - -00000b70 <.L223>: - b70: 4792 lw a5,4(sp) - b72: 02f56563 bltu a0,a5,b9c <.L293> - b76: cc8d beqz s1,bb0 <.L226> - -00000b78 <.LVL282>: - b78: fff48713 add a4,s1,-1 - -00000b7c <.LVL283>: - b7c: 12412083 lw ra,292(sp) - b80: 12012403 lw s0,288(sp) - b84: 070a sll a4,a4,0x2 - -00000b86 <.LVL284>: - b86: 11070793 add a5,a4,272 # 110 <.L33+0x2> - b8a: 0078 add a4,sp,12 - b8c: 973e add a4,a4,a5 - b8e: f0072503 lw a0,-256(a4) - -00000b92 <.LVL285>: - b92: 11c12483 lw s1,284(sp) - -00000b96 <.LVL286>: - b96: 12810113 add sp,sp,296 - -00000b9a <.LVL287>: - b9a: 8082 ret - -00000b9c <.L293>: - b9c: 00054683 lbu a3,0(a0) - ba0: 47d9 li a5,22 - ba2: 00150413 add s0,a0,1 - -00000ba6 <.LVL289>: - ba6: 08d7eb63 bltu a5,a3,c3c <.L224> - baa: 4789 li a5,2 - bac: 06d7ea63 bltu a5,a3,c20 <.L225> - -00000bb0 <.L226>: - bb0: 00000097 auipc ra,0x0 - bb4: 000080e7 jalr ra # bb0 <.L226> - -00000bb8 <.L316>: - bb8: fe968593 add a1,a3,-23 - bbc: 4785 li a5,1 - bbe: 00b797b3 sll a5,a5,a1 - bc2: 6585 lui a1,0x1 - bc4: cf858513 add a0,a1,-776 # cf8 <.L248+0x24> - bc8: 8d7d and a0,a0,a5 - bca: e959 bnez a0,c60 <.L227> - bcc: 30458593 add a1,a1,772 - bd0: 8dfd and a1,a1,a5 - bd2: fff48513 add a0,s1,-1 - bd6: 32059863 bnez a1,f06 <.L228> - bda: 8b85 and a5,a5,1 - bdc: dbf1 beqz a5,bb0 <.L226> - -00000bde <.LBB270>: - bde: 4789 li a5,2 - be0: fc97d8e3 bge a5,s1,bb0 <.L226> - be4: 050a sll a0,a0,0x2 - be6: ffe48693 add a3,s1,-2 - -00000bea <.LVL292>: - bea: 0078 add a4,sp,12 - bec: 11050793 add a5,a0,272 - bf0: 068a sll a3,a3,0x2 - bf2: 00e78533 add a0,a5,a4 - bf6: 11068793 add a5,a3,272 - bfa: 00e786b3 add a3,a5,a4 - bfe: ffd48793 add a5,s1,-3 - c02: 078a sll a5,a5,0x2 - c04: 11078793 add a5,a5,272 - c08: f006a303 lw t1,-256(a3) - c0c: 97ba add a5,a5,a4 - c0e: f007a283 lw t0,-256(a5) - c12: f0052583 lw a1,-256(a0) - -00000c16 <.LVL293>: - c16: f0652023 sw t1,-256(a0) - c1a: f056a023 sw t0,-256(a3) - c1e: ac45 j ece <.L330> - -00000c20 <.L225>: - c20: 16f5 add a3,a3,-3 - -00000c22 <.LVL295>: - c22: 0ff6f693 zext.b a3,a3 - -00000c26 <.LVL296>: - c26: 47cd li a5,19 - c28: f8d7e4e3 bltu a5,a3,bb0 <.L226> - c2c: 000007b7 lui a5,0x0 - c30: 00078793 mv a5,a5 - c34: 068a sll a3,a3,0x2 - c36: 96be add a3,a3,a5 - c38: 429c lw a5,0(a3) - c3a: 8782 jr a5 - -00000c3c <.L224>: - c3c: 06f00793 li a5,111 - c40: 08d7ea63 bltu a5,a3,cd4 <.L248> - c44: 04f00793 li a5,79 - c48: 1cd7e063 bltu a5,a3,e08 <.L249> - c4c: 02800793 li a5,40 - c50: 3cf68463 beq a3,a5,1018 <.L250> - c54: 04d7ea63 bltu a5,a3,ca8 <.L251> - c58: 02300793 li a5,35 - c5c: f4d7fee3 bgeu a5,a3,bb8 <.L316> - -00000c60 <.L227>: - c60: 4785 li a5,1 - c62: f497d7e3 bge a5,s1,bb0 <.L226> - c66: ffe48313 add t1,s1,-2 - -00000c6a <.LVL298>: - c6a: 00231793 sll a5,t1,0x2 - c6e: 0078 add a4,sp,12 - c70: 11078793 add a5,a5,272 # 110 <.L33+0x2> - c74: 97ba add a5,a5,a4 - c76: fff48713 add a4,s1,-1 - c7a: 070a sll a4,a4,0x2 - c7c: f007a503 lw a0,-256(a5) - -00000c80 <.LVL299>: - c80: 1699 add a3,a3,-26 - -00000c82 <.LVL300>: - c82: 11070793 add a5,a4,272 - c86: 0078 add a4,sp,12 - c88: 973e add a4,a4,a5 - c8a: 0ff6f693 zext.b a3,a3 - -00000c8e <.LVL301>: - c8e: 47d1 li a5,20 - c90: f0072583 lw a1,-256(a4) - -00000c94 <.LVL302>: - c94: f0d7eee3 bltu a5,a3,bb0 <.L226> - c98: 000007b7 lui a5,0x0 - c9c: 00078793 mv a5,a5 - ca0: 068a sll a3,a3,0x2 - ca2: 96be add a3,a3,a5 - ca4: 429c lw a5,0(a3) - ca6: 8782 jr a5 - -00000ca8 <.L251>: - ca8: 02f00793 li a5,47 - cac: 34f68a63 beq a3,a5,1000 <.L253> - cb0: fad7f8e3 bgeu a5,a3,c60 <.L227> - cb4: fd068793 add a5,a3,-48 - -00000cb8 <.L254>: - cb8: 03f00693 li a3,63 - cbc: ee96cae3 blt a3,s1,bb0 <.L226> - -00000cc0 <.LVL305>: - cc0: 00249693 sll a3,s1,0x2 - cc4: 11068713 add a4,a3,272 - cc8: 0074 add a3,sp,12 - cca: 96ba add a3,a3,a4 - ccc: f0f6a023 sw a5,-256(a3) - cd0: 0485 add s1,s1,1 - -00000cd2 <.LVL306>: - cd2: a26d j e7c <.L264> - -00000cd4 <.L248>: - cd4: 09200793 li a5,146 - cd8: 16f68563 beq a3,a5,e42 <.L255> - cdc: 02d7e363 bltu a5,a3,d02 <.L256> - ce0: 08f00793 li a5,143 - ce4: 12d7fb63 bgeu a5,a3,e1a <.L257> - ce8: 09000793 li a5,144 - cec: ecf692e3 bne a3,a5,bb0 <.L226> - cf0: 006c add a1,sp,12 - cf2: 8522 mv a0,s0 - cf4: 00000097 auipc ra,0x0 - cf8: 000080e7 jalr ra # cf4 <.L248+0x20> - -00000cfc <.LVL308>: - cfc: 45b2 lw a1,12(sp) - cfe: 842a mv s0,a0 - d00: a231 j e0c <.L327> - -00000d02 <.L256>: - d02: 09600793 li a5,150 - d06: 16f68b63 beq a3,a5,e7c <.L264> - d0a: 0f100793 li a5,241 - d0e: 00250613 add a2,a0,2 - d12: 04f68463 beq a3,a5,d5a <.L260> - d16: 09400793 li a5,148 - d1a: e8f69be3 bne a3,a5,bb0 <.L226> - d1e: e80489e3 beqz s1,bb0 <.L226> - d22: 14fd add s1,s1,-1 - -00000d24 <.LBB272>: - d24: 00249793 sll a5,s1,0x2 - -00000d28 <.LBB273>: - d28: 00154683 lbu a3,1(a0) - -00000d2c <.LBE273>: - d2c: 11078793 add a5,a5,272 # 110 <.L33+0x2> - d30: 0078 add a4,sp,12 - d32: 97ba add a5,a5,a4 - -00000d34 <.LBB274>: - d34: 4591 li a1,4 - d36: f007a783 lw a5,-256(a5) - -00000d3a <.LVL312>: - d3a: 8432 mv s0,a2 - d3c: 1eb69f63 bne a3,a1,f3a <.L317> - -00000d40 <.L274>: - d40: 0017c583 lbu a1,1(a5) - d44: 0007c683 lbu a3,0(a5) - d48: 05a2 sll a1,a1,0x8 - d4a: 8dd5 or a1,a1,a3 - d4c: 0027c683 lbu a3,2(a5) - d50: 0037c783 lbu a5,3(a5) - -00000d54 <.LVL314>: - d54: 06c2 sll a3,a3,0x10 - d56: 8ecd or a3,a3,a1 - d58: a26d j f02 <.L325> - -00000d5a <.L260>: - d5a: 00154583 lbu a1,1(a0) - d5e: 4502 lw a0,0(sp) - d60: 0834 add a3,sp,24 - -00000d62 <.LVL316>: - d62: 00000097 auipc ra,0x0 - d66: 000080e7 jalr ra # d62 <.LVL316> - -00000d6a <.L321>: - d6a: 47e2 lw a5,24(sp) - d6c: 842a mv s0,a0 - -00000d6e <.LVL318>: - d6e: b7a9 j cb8 <.L254> - -00000d70 <.L245>: - d70: 00154783 lbu a5,1(a0) - -00000d74 <.L323>: - d74: 00250413 add s0,a0,2 - -00000d78 <.LVL321>: - d78: b781 j cb8 <.L254> - -00000d7a <.L244>: - d7a: 00150783 lb a5,1(a0) - d7e: bfdd j d74 <.L323> - -00000d80 <.L243>: - d80: 00254783 lbu a5,2(a0) - d84: 00154683 lbu a3,1(a0) - d88: 07a2 sll a5,a5,0x8 - -00000d8a <.LBE280>: - d8a: 8fd5 or a5,a5,a3 - -00000d8c <.L324>: - d8c: 00350413 add s0,a0,3 - -00000d90 <.LVL325>: - d90: b725 j cb8 <.L254> - -00000d92 <.L242>: - d92: 00254783 lbu a5,2(a0) - d96: 00154683 lbu a3,1(a0) - d9a: 07a2 sll a5,a5,0x8 - d9c: 8fd5 or a5,a5,a3 - -00000d9e <.LBE282>: - d9e: 07c2 sll a5,a5,0x10 - da0: 87c1 sra a5,a5,0x10 - da2: b7ed j d8c <.L324> - -00000da4 <.L240>: - da4: 00254783 lbu a5,2(a0) - da8: 00154683 lbu a3,1(a0) - -00000dac <.LBE284>: - dac: 00550413 add s0,a0,5 - -00000db0 <.LBB287>: - db0: 07a2 sll a5,a5,0x8 - db2: 8fd5 or a5,a5,a3 - db4: 00354683 lbu a3,3(a0) - db8: 06c2 sll a3,a3,0x10 - dba: 8edd or a3,a3,a5 - dbc: 00454783 lbu a5,4(a0) - dc0: 07e2 sll a5,a5,0x18 - dc2: 8fd5 or a5,a5,a3 - -00000dc4 <.LBE287>: - dc4: bdd5 j cb8 <.L254> - -00000dc6 <.L238>: - dc6: 00254783 lbu a5,2(a0) - dca: 00154683 lbu a3,1(a0) - -00000dce <.LBE288>: - dce: 00950413 add s0,a0,9 - -00000dd2 <.LBB291>: - dd2: 07a2 sll a5,a5,0x8 - dd4: 8fd5 or a5,a5,a3 - dd6: 00354683 lbu a3,3(a0) - dda: 06c2 sll a3,a3,0x10 - ddc: 8edd or a3,a3,a5 - dde: 00454783 lbu a5,4(a0) - de2: 07e2 sll a5,a5,0x18 - de4: 8fd5 or a5,a5,a3 - -00000de6 <.LBE291>: - de6: bdc9 j cb8 <.L254> - -00000de8 <.L237>: - de8: 8522 mv a0,s0 - -00000dea <.LVL334>: - dea: 080c add a1,sp,16 - dec: 00000097 auipc ra,0x0 - df0: 000080e7 jalr ra # dec <.LVL334+0x2> - -00000df4 <.LVL335>: - df4: 47c2 lw a5,16(sp) - df6: 842a mv s0,a0 - -00000df8 <.LVL336>: - df8: b5c1 j cb8 <.L254> - -00000dfa <.L236>: - dfa: 082c add a1,sp,24 - dfc: 8522 mv a0,s0 - -00000dfe <.LVL338>: - dfe: 00000097 auipc ra,0x0 - e02: 000080e7 jalr ra # dfe <.LVL338> - -00000e06 <.LVL339>: - e06: b795 j d6a <.L321> - -00000e08 <.L249>: - e08: fb068593 add a1,a3,-80 - -00000e0c <.L327>: - e0c: 4502 lw a0,0(sp) - e0e: 00000097 auipc ra,0x0 - e12: 000080e7 jalr ra # e0e <.L327+0x2> - -00000e16 <.LVL342>: - e16: 87aa mv a5,a0 - -00000e18 <.LVL343>: - e18: b545 j cb8 <.L254> - -00000e1a <.L257>: - e1a: 084c add a1,sp,20 - e1c: 8522 mv a0,s0 - e1e: c436 sw a3,8(sp) - e20: 00000097 auipc ra,0x0 - e24: 000080e7 jalr ra # e20 <.L257+0x6> - -00000e28 <.LVL345>: - e28: 46a2 lw a3,8(sp) - e2a: 842a mv s0,a0 - e2c: f9068593 add a1,a3,-112 - -00000e30 <.L328>: - e30: 4502 lw a0,0(sp) - e32: 00000097 auipc ra,0x0 - e36: 000080e7 jalr ra # e32 <.L328+0x2> - -00000e3a <.LVL347>: - e3a: 46d2 lw a3,20(sp) - e3c: 00d507b3 add a5,a0,a3 - -00000e40 <.LVL348>: - e40: bda5 j cb8 <.L254> - -00000e42 <.L255>: - e42: 006c add a1,sp,12 - e44: 8522 mv a0,s0 - e46: 00000097 auipc ra,0x0 - e4a: 000080e7 jalr ra # e46 <.L255+0x4> - -00000e4e <.LVL350>: - e4e: 084c add a1,sp,20 - e50: 00000097 auipc ra,0x0 - e54: 000080e7 jalr ra # e50 <.LVL350+0x2> - -00000e58 <.LVL351>: - e58: 45b2 lw a1,12(sp) - e5a: 842a mv s0,a0 - -00000e5c <.LVL352>: - e5c: bfd1 j e30 <.L328> - -00000e5e <.L235>: - e5e: d40489e3 beqz s1,bb0 <.L226> - e62: fff48793 add a5,s1,-1 - -00000e66 <.L329>: - e66: 078a sll a5,a5,0x2 - e68: 11078793 add a5,a5,272 - e6c: 0078 add a4,sp,12 - e6e: 97ba add a5,a5,a4 - e70: f007a783 lw a5,-256(a5) - -00000e74 <.LVL354>: - e74: b591 j cb8 <.L254> - -00000e76 <.L234>: - e76: d2048de3 beqz s1,bb0 <.L226> - e7a: 14fd add s1,s1,-1 - -00000e7c <.L264>: - e7c: 8522 mv a0,s0 - e7e: b9cd j b70 <.L223> - -00000e80 <.L232>: - e80: 00154683 lbu a3,1(a0) - e84: fff48793 add a5,s1,-1 - e88: 00250413 add s0,a0,2 - -00000e8c <.LVL358>: - e8c: d2f6d2e3 bge a3,a5,bb0 <.L226> - e90: 8f95 sub a5,a5,a3 - e92: bfd1 j e66 <.L329> - -00000e94 <.L233>: - e94: 4785 li a5,1 - e96: d097dde3 bge a5,s1,bb0 <.L226> - e9a: ffe48793 add a5,s1,-2 - e9e: b7e1 j e66 <.L329> - -00000ea0 <.L230>: - ea0: 4785 li a5,1 - ea2: d097d7e3 bge a5,s1,bb0 <.L226> - ea6: fff48693 add a3,s1,-1 - eaa: 068a sll a3,a3,0x2 - eac: 11068793 add a5,a3,272 - eb0: 0078 add a4,sp,12 - eb2: 00e786b3 add a3,a5,a4 - eb6: ffe48793 add a5,s1,-2 - eba: 078a sll a5,a5,0x2 - ebc: 11078793 add a5,a5,272 - ec0: 97ba add a5,a5,a4 - ec2: f007a503 lw a0,-256(a5) - -00000ec6 <.LVL359>: - ec6: f006a583 lw a1,-256(a3) - -00000eca <.LVL360>: - eca: f0a6a023 sw a0,-256(a3) - -00000ece <.L330>: - ece: f0b7a023 sw a1,-256(a5) - -00000ed2 <.LVL362>: - ed2: b76d j e7c <.L264> - -00000ed4 <.L246>: - ed4: cc048ee3 beqz s1,bb0 <.L226> - ed8: 14fd add s1,s1,-1 - -00000eda <.LBB294>: - eda: 00249793 sll a5,s1,0x2 - ede: 11078793 add a5,a5,272 - ee2: 0078 add a4,sp,12 - ee4: 97ba add a5,a5,a4 - -00000ee6 <.LBB299>: - ee6: f007a583 lw a1,-256(a5) - eea: 0015c783 lbu a5,1(a1) - eee: 0005c683 lbu a3,0(a1) - ef2: 07a2 sll a5,a5,0x8 - ef4: 8fd5 or a5,a5,a3 - ef6: 0025c683 lbu a3,2(a1) - efa: 06c2 sll a3,a3,0x10 - efc: 8edd or a3,a3,a5 - efe: 0035c783 lbu a5,3(a1) - -00000f02 <.L325>: - f02: 07e2 sll a5,a5,0x18 - f04: a889 j f56 <.L326> - -00000f06 <.L228>: - f06: ca0485e3 beqz s1,bb0 <.L226> - f0a: 00251793 sll a5,a0,0x2 - f0e: 11078793 add a5,a5,272 - f12: 0078 add a4,sp,12 - f14: 97ba add a5,a5,a4 - f16: 02000593 li a1,32 - f1a: f007a783 lw a5,-256(a5) - f1e: 84aa mv s1,a0 - -00000f20 <.LVL367>: - f20: 04b68963 beq a3,a1,f72 <.L267> - f24: 12d5e363 bltu a1,a3,104a <.L268> - f28: 45e5 li a1,25 - f2a: 02b68f63 beq a3,a1,f68 <.L269> - f2e: 45fd li a1,31 - f30: c8b690e3 bne a3,a1,bb0 <.L226> - f34: 40f007b3 neg a5,a5 - f38: b341 j cb8 <.L254> - -00000f3a <.L317>: - f3a: 4591 li a1,4 - f3c: 00d5ef63 bltu a1,a3,f5a <.L271> - f40: 4585 li a1,1 - f42: 02b68063 beq a3,a1,f62 <.L272> - f46: 4589 li a1,2 - f48: c6b694e3 bne a3,a1,bb0 <.L226> - -00000f4c <.LBB265>: - f4c: 0007c683 lbu a3,0(a5) - f50: 0017c783 lbu a5,1(a5) - -00000f54 <.LVL371>: - f54: 07a2 sll a5,a5,0x8 - -00000f56 <.L326>: - f56: 8fd5 or a5,a5,a3 - -00000f58 <.LBE267>: - f58: b385 j cb8 <.L254> - -00000f5a <.L271>: - f5a: 45a1 li a1,8 - f5c: deb682e3 beq a3,a1,d40 <.L274> - f60: b981 j bb0 <.L226> - -00000f62 <.L272>: - f62: 0007c783 lbu a5,0(a5) - -00000f66 <.LVL376>: - f66: bb89 j cb8 <.L254> - -00000f68 <.L269>: - f68: 41f7d693 sra a3,a5,0x1f - -00000f6c <.LVL378>: - f6c: 8fb5 xor a5,a5,a3 - -00000f6e <.LVL379>: - f6e: 8f95 sub a5,a5,a3 - f70: b3a1 j cb8 <.L254> - -00000f72 <.L267>: - f72: fff7c793 not a5,a5 - f76: b389 j cb8 <.L254> - -00000f78 <.L292>: - f78: 00b577b3 and a5,a0,a1 - -00000f7c <.L322>: - f7c: 849a mv s1,t1 - -00000f7e <.LVL384>: - f7e: bb2d j cb8 <.L254> - -00000f80 <.L291>: - f80: c41a sw t1,8(sp) - f82: 00000097 auipc ra,0x0 - f86: 000080e7 jalr ra # f82 <.L291+0x2> - -00000f8a <.L331>: - f8a: 4322 lw t1,8(sp) - f8c: 87aa mv a5,a0 - -00000f8e <.LVL387>: - f8e: b7fd j f7c <.L322> - -00000f90 <.L290>: - f90: 40b507b3 sub a5,a0,a1 - -00000f94 <.LVL389>: - f94: b7e5 j f7c <.L322> - -00000f96 <.L289>: - f96: c41a sw t1,8(sp) - f98: 00000097 auipc ra,0x0 - f9c: 000080e7 jalr ra # f98 <.L289+0x2> - -00000fa0 <.LVL391>: - fa0: b7ed j f8a <.L331> - -00000fa2 <.L288>: - fa2: c41a sw t1,8(sp) - fa4: 00000097 auipc ra,0x0 - fa8: 000080e7 jalr ra # fa4 <.L288+0x2> - -00000fac <.LVL393>: - fac: bff9 j f8a <.L331> - -00000fae <.L287>: - fae: 00b567b3 or a5,a0,a1 - -00000fb2 <.LVL395>: - fb2: b7e9 j f7c <.L322> - -00000fb4 <.L286>: - fb4: 00b507b3 add a5,a0,a1 - -00000fb8 <.LVL397>: - fb8: b7d1 j f7c <.L322> - -00000fba <.L285>: - fba: 00b517b3 sll a5,a0,a1 - -00000fbe <.LVL399>: - fbe: bf7d j f7c <.L322> - -00000fc0 <.L284>: - fc0: 00b557b3 srl a5,a0,a1 - -00000fc4 <.LVL401>: - fc4: bf65 j f7c <.L322> - -00000fc6 <.L283>: - fc6: 40b557b3 sra a5,a0,a1 - -00000fca <.LVL403>: - fca: bf4d j f7c <.L322> - -00000fcc <.L282>: - fcc: 00b547b3 xor a5,a0,a1 - -00000fd0 <.LVL405>: - fd0: b775 j f7c <.L322> - -00000fd2 <.L278>: - fd2: 00a5a7b3 slt a5,a1,a0 - -00000fd6 <.L332>: - fd6: 0017c793 xor a5,a5,1 - -00000fda <.LVL407>: - fda: b74d j f7c <.L322> - -00000fdc <.L280>: - fdc: 00b527b3 slt a5,a0,a1 - fe0: bfdd j fd6 <.L332> - -00000fe2 <.L281>: - fe2: 40b507b3 sub a5,a0,a1 - fe6: 0017b793 seqz a5,a5 - -00000fea <.LVL409>: - fea: bf49 j f7c <.L322> - -00000fec <.L277>: - fec: 00b527b3 slt a5,a0,a1 - -00000ff0 <.LVL411>: - ff0: b771 j f7c <.L322> - -00000ff2 <.L279>: - ff2: 00a5a7b3 slt a5,a1,a0 - -00000ff6 <.LVL413>: - ff6: b759 j f7c <.L322> - -00000ff8 <.L275>: - ff8: 8d0d sub a0,a0,a1 - -00000ffa <.LVL415>: - ffa: 00a037b3 snez a5,a0 - ffe: bfbd j f7c <.L322> - -00001000 <.L253>: - 1000: 00254603 lbu a2,2(a0) - 1004: 00154783 lbu a5,1(a0) - 1008: 0622 sll a2,a2,0x8 - 100a: 8e5d or a2,a2,a5 - -0000100c <.LBE306>: - 100c: 0642 sll a2,a2,0x10 - 100e: 8641 sra a2,a2,0x10 - 1010: 060d add a2,a2,3 - -00001012 <.LVL417>: - 1012: 00c50433 add s0,a0,a2 - -00001016 <.LVL418>: - 1016: b59d j e7c <.L264> - -00001018 <.L250>: - 1018: b8048ce3 beqz s1,bb0 <.L226> - 101c: 14fd add s1,s1,-1 - -0000101e <.LBB307>: - 101e: 00249793 sll a5,s1,0x2 - 1022: 11078793 add a5,a5,272 - 1026: 0078 add a4,sp,12 - 1028: 97ba add a5,a5,a4 - 102a: f007a783 lw a5,-256(a5) - 102e: 00350413 add s0,a0,3 - -00001032 <.LVL421>: - 1032: e40785e3 beqz a5,e7c <.L264> - -00001036 <.LBB310>: - 1036: 00254783 lbu a5,2(a0) - 103a: 00154683 lbu a3,1(a0) - -0000103e <.LVL422>: - 103e: 07a2 sll a5,a5,0x8 - 1040: 8fd5 or a5,a5,a3 - -00001042 <.LBE310>: - 1042: 07c2 sll a5,a5,0x10 - 1044: 87c1 sra a5,a5,0x10 - -00001046 <.LVL423>: - 1046: 943e add s0,s0,a5 - -00001048 <.LVL424>: - 1048: bd15 j e7c <.L264> - -0000104a <.L268>: - 104a: 02300593 li a1,35 - 104e: b6b691e3 bne a3,a1,bb0 <.L226> - 1052: 8522 mv a0,s0 - 1054: 080c add a1,sp,16 - 1056: c43e sw a5,8(sp) - 1058: 00000097 auipc ra,0x0 - 105c: 000080e7 jalr ra # 1058 <.L268+0xe> - -00001060 <.LVL426>: - 1060: 46c2 lw a3,16(sp) - 1062: 47a2 lw a5,8(sp) - 1064: 842a mv s0,a0 - 1066: 97b6 add a5,a5,a3 - -00001068 <.LVL427>: - 1068: b981 j cb8 <.L254> - -0000106a : - 106a: e6c10113 add sp,sp,-404 - 106e: 18912423 sw s1,392(sp) - 1072: c02a sw a0,0(sp) - 1074: 84ae mv s1,a1 - 1076: 17400613 li a2,372 - 107a: 85aa mv a1,a0 - -0000107c <.LVL429>: - 107c: 0848 add a0,sp,20 - -0000107e <.LVL430>: - 107e: 18112823 sw ra,400(sp) - 1082: 18812623 sw s0,396(sp) - 1086: 00000097 auipc ra,0x0 - 108a: 000080e7 jalr ra # 1086 <.LVL430+0x8> - -0000108e <.LVL431>: - 108e: 4589 li a1,2 - 1090: 0848 add a0,sp,20 - 1092: 00000097 auipc ra,0x0 - 1096: 000080e7 jalr ra # 1092 <.LVL431+0x4> - -0000109a <.LVL432>: - 109a: e911 bnez a0,10ae <.L334> - 109c: 4782 lw a5,0(sp) - 109e: 0070 add a2,sp,12 - 10a0: 0848 add a0,sp,20 - 10a2: 10c7a583 lw a1,268(a5) - 10a6: 00000097 auipc ra,0x0 - 10aa: 000080e7 jalr ra # 10a6 <.LVL432+0xc> - -000010ae <.L334>: - 10ae: 4502 lw a0,0(sp) - 10b0: 4601 li a2,0 - 10b2: 4589 li a1,2 - 10b4: 00000097 auipc ra,0x0 - 10b8: 000080e7 jalr ra # 10b4 <.L334+0x6> - -000010bc <.LVL434>: - 10bc: 2284a783 lw a5,552(s1) - 10c0: 4705 li a4,1 - 10c2: 4409 li s0,2 - 10c4: 00e78863 beq a5,a4,10d4 <.L335> - 10c8: 04878463 beq a5,s0,1110 <.L336> - 10cc: 00000097 auipc ra,0x0 - 10d0: 000080e7 jalr ra # 10cc <.LVL434+0x10> - -000010d4 <.L335>: - 10d4: 2204a583 lw a1,544(s1) - 10d8: 0848 add a0,sp,20 - -000010da <.LVL436>: - 10da: 00000097 auipc ra,0x0 - 10de: 000080e7 jalr ra # 10da <.LVL436> - -000010e2 <.LBE320>: - 10e2: 21c4a783 lw a5,540(s1) - 10e6: 97aa add a5,a5,a0 - 10e8: c43e sw a5,8(sp) - -000010ea <.L338>: - 10ea: 4782 lw a5,0(sp) - 10ec: 4722 lw a4,8(sp) - 10ee: 8426 mv s0,s1 - 10f0: c202 sw zero,4(sp) - 10f2: 10e7a623 sw a4,268(a5) - -000010f6 <.L347>: - 10f6: 4058 lw a4,4(s0) - 10f8: 4691 li a3,4 - 10fa: 177d add a4,a4,-1 - 10fc: 04e6e463 bltu a3,a4,1144 <.L339> - 1100: 000007b7 lui a5,0x0 - 1104: 070a sll a4,a4,0x2 - 1106: 00078693 mv a3,a5 - 110a: 9736 add a4,a4,a3 - 110c: 4318 lw a4,0(a4) - 110e: 8702 jr a4 - -00001110 <.L336>: - 1110: 2244a503 lw a0,548(s1) - 1114: 080c add a1,sp,16 - 1116: 00000097 auipc ra,0x0 - 111a: 000080e7 jalr ra # 1116 <.L336+0x6> - -0000111e <.LVL441>: - 111e: 45c2 lw a1,16(sp) - 1120: 4681 li a3,0 - 1122: 0850 add a2,sp,20 - 1124: 95aa add a1,a1,a0 - 1126: 00000097 auipc ra,0x0 - 112a: 000080e7 jalr ra # 1126 <.LVL441+0x8> - -0000112e <.LVL442>: - 112e: c42a sw a0,8(sp) - -00001130 <.LVL443>: - 1130: bf6d j 10ea <.L338> - -00001132 <.L345>: - 1132: 4010 lw a2,0(s0) - 1134: 47a2 lw a5,8(sp) - 1136: 963e add a2,a2,a5 - -00001138 <.L353>: - 1138: 4592 lw a1,4(sp) - 113a: 4502 lw a0,0(sp) - 113c: 00000097 auipc ra,0x0 - 1140: 000080e7 jalr ra # 113c <.L353+0x4> - -00001144 <.L339>: - 1144: 4792 lw a5,4(sp) - 1146: 04300713 li a4,67 - 114a: 0421 add s0,s0,8 - 114c: 0785 add a5,a5,1 # 1 - 114e: c23e sw a5,4(sp) - -00001150 <.LVL446>: - 1150: fae793e3 bne a5,a4,10f6 <.L347> - -00001154 <.LBB323>: - 1154: 4782 lw a5,0(sp) - -00001156 <.LVL448>: - 1156: 2434c703 lbu a4,579(s1) - -0000115a <.LVL449>: - 115a: 1247a783 lw a5,292(a5) - 115e: cf49 beqz a4,11f8 <.L348> - 1160: 80000737 lui a4,0x80000 - -00001164 <.LVL450>: - 1164: 8fd9 or a5,a5,a4 - -00001166 <.L349>: - 1166: 4702 lw a4,0(sp) - -00001168 <.LBE323>: - 1168: 19012083 lw ra,400(sp) - 116c: 18c12403 lw s0,396(sp) - 1170: 12f72223 sw a5,292(a4) # 80000124 <.LLST185+0x7fffd9fc> - -00001174 <.LVL451>: - 1174: 18812483 lw s1,392(sp) - -00001178 <.LVL452>: - 1178: 19410113 add sp,sp,404 - -0000117c <.LVL453>: - 117c: 8082 ret - -0000117e <.L344>: - 117e: 400c lw a1,0(s0) - -00001180 <.LBB326>: - 1180: 0078 add a4,sp,12 - -00001182 <.LBE326>: - 1182: 0848 add a0,sp,20 - -00001184 <.LBB329>: - 1184: 17c58793 add a5,a1,380 - 1188: 973e add a4,a4,a5 - -0000118a <.LBE329>: - 118a: fbc74703 lbu a4,-68(a4) - 118e: c719 beqz a4,119c <.L346> - 1190: 00000097 auipc ra,0x0 - 1194: 000080e7 jalr ra # 1190 <.LBE329+0x6> - -00001198 <.L356>: - 1198: 862a mv a2,a0 - 119a: a80d j 11cc <.L354> - -0000119c <.L346>: - 119c: 00000097 auipc ra,0x0 - 11a0: 000080e7 jalr ra # 119c <.L346> - -000011a4 <.L355>: - 11a4: 862a mv a2,a0 - 11a6: bf49 j 1138 <.L353> - -000011a8 <.L343>: - 11a8: 4008 lw a0,0(s0) - 11aa: 080c add a1,sp,16 - 11ac: 00000097 auipc ra,0x0 - 11b0: 000080e7 jalr ra # 11ac <.L343+0x4> - -000011b4 <.LVL459>: - 11b4: 45c2 lw a1,16(sp) - 11b6: 46a2 lw a3,8(sp) - 11b8: 0850 add a2,sp,20 - 11ba: 95aa add a1,a1,a0 - 11bc: 00000097 auipc ra,0x0 - 11c0: 000080e7 jalr ra # 11bc <.LVL459+0x8> - -000011c4 <.LVL460>: - 11c4: b7c5 j 11a4 <.L355> - -000011c6 <.L342>: - 11c6: 4010 lw a2,0(s0) - 11c8: 47a2 lw a5,8(sp) - 11ca: 963e add a2,a2,a5 - -000011cc <.L354>: - 11cc: 4592 lw a1,4(sp) - 11ce: 4502 lw a0,0(sp) - 11d0: 00000097 auipc ra,0x0 - 11d4: 000080e7 jalr ra # 11d0 <.L354+0x4> - -000011d8 <.LBE332>: - 11d8: b7b5 j 1144 <.L339> - -000011da <.L340>: - 11da: 4008 lw a0,0(s0) - 11dc: 080c add a1,sp,16 - 11de: 00000097 auipc ra,0x0 - 11e2: 000080e7 jalr ra # 11de <.L340+0x4> - -000011e6 <.LVL465>: - 11e6: 45c2 lw a1,16(sp) - 11e8: 46a2 lw a3,8(sp) - 11ea: 0850 add a2,sp,20 - 11ec: 95aa add a1,a1,a0 - 11ee: 00000097 auipc ra,0x0 - 11f2: 000080e7 jalr ra # 11ee <.LVL465+0x8> - -000011f6 <.LVL466>: - 11f6: b74d j 1198 <.L356> - -000011f8 <.L348>: - 11f8: 0786 sll a5,a5,0x1 - 11fa: 8385 srl a5,a5,0x1 - 11fc: b7ad j 1166 <.L349> - -000011fe : - 11fe: da010113 add sp,sp,-608 - -00001202 <.LVL469>: - 1202: 24912a23 sw s1,596(sp) - 1206: c02e sw a1,0(sp) - 1208: 84b2 mv s1,a2 - 120a: 4581 li a1,0 - -0000120c <.LVL470>: - 120c: 17400613 li a2,372 - -00001210 <.LVL471>: - 1210: 24812c23 sw s0,600(sp) - 1214: 24112e23 sw ra,604(sp) - 1218: 842a mv s0,a0 - 121a: c206 sw ra,4(sp) - -0000121c <.LVL472>: - 121c: 00000097 auipc ra,0x0 - 1220: 000080e7 jalr ra # 121c <.LVL472> - -00001224 <.LVL473>: - 1224: 4792 lw a5,4(sp) - 1226: 006c add a1,sp,12 - 1228: 8522 mv a0,s0 - 122a: 10f42823 sw a5,272(s0) - 122e: 400007b7 lui a5,0x40000 - 1232: 12f42223 sw a5,292(s0) - 1236: 00000097 auipc ra,0x0 - 123a: 000080e7 jalr ra # 1236 <.LVL473+0x12> - -0000123e <.LVL474>: - 123e: c509 beqz a0,1248 <.L358> - 1240: 00000097 auipc ra,0x0 - 1244: 000080e7 jalr ra # 1240 <.LVL474+0x2> - -00001248 <.L358>: - 1248: 000007b7 lui a5,0x0 - 124c: 00078793 mv a5,a5 - 1250: 0007c703 lbu a4,0(a5) # 0 - 1254: e761 bnez a4,131c <.L359> - -00001256 <.LBB337>: - 1256: 4711 li a4,4 - 1258: 00e78023 sb a4,0(a5) - 125c: 00e780a3 sb a4,1(a5) - 1260: 00e78123 sb a4,2(a5) - 1264: 00e781a3 sb a4,3(a5) - 1268: 00e78223 sb a4,4(a5) - 126c: 00e782a3 sb a4,5(a5) - 1270: 00e78323 sb a4,6(a5) - 1274: 00e783a3 sb a4,7(a5) - 1278: 00e78423 sb a4,8(a5) - 127c: 00e784a3 sb a4,9(a5) - 1280: 00e78523 sb a4,10(a5) - 1284: 00e785a3 sb a4,11(a5) - 1288: 00e78623 sb a4,12(a5) - 128c: 00e786a3 sb a4,13(a5) - 1290: 00e78723 sb a4,14(a5) - 1294: 00e787a3 sb a4,15(a5) - 1298: 02e78023 sb a4,32(a5) - 129c: 02e780a3 sb a4,33(a5) - 12a0: 02e78123 sb a4,34(a5) - 12a4: 02e781a3 sb a4,35(a5) - 12a8: 02e78223 sb a4,36(a5) - 12ac: 02e782a3 sb a4,37(a5) - 12b0: 02e78323 sb a4,38(a5) - 12b4: 02e783a3 sb a4,39(a5) - 12b8: 02e78423 sb a4,40(a5) - 12bc: 02e784a3 sb a4,41(a5) - 12c0: 02e78523 sb a4,42(a5) - 12c4: 02e785a3 sb a4,43(a5) - 12c8: 02e78623 sb a4,44(a5) - 12cc: 02e786a3 sb a4,45(a5) - 12d0: 02e78723 sb a4,46(a5) - 12d4: 02e787a3 sb a4,47(a5) - 12d8: 02e78823 sb a4,48(a5) - 12dc: 02e788a3 sb a4,49(a5) - 12e0: 02e78923 sb a4,50(a5) - 12e4: 02e789a3 sb a4,51(a5) - 12e8: 02e78a23 sb a4,52(a5) - 12ec: 02e78aa3 sb a4,53(a5) - 12f0: 02e78b23 sb a4,54(a5) - 12f4: 02e78ba3 sb a4,55(a5) - 12f8: 02e78c23 sb a4,56(a5) - 12fc: 02e78ca3 sb a4,57(a5) - 1300: 02e78d23 sb a4,58(a5) - 1304: 02e78da3 sb a4,59(a5) - 1308: 02e78e23 sb a4,60(a5) - 130c: 02e78ea3 sb a4,61(a5) - 1310: 02e78f23 sb a4,62(a5) - 1314: 02e78fa3 sb a4,63(a5) - 1318: 04e78023 sb a4,64(a5) - -0000131c <.L359>: - 131c: 4582 lw a1,0(sp) - 131e: 0030 add a2,sp,8 - 1320: 8522 mv a0,s0 - -00001322 <.LVL476>: - 1322: 00000097 auipc ra,0x0 - 1326: 000080e7 jalr ra # 1322 <.LVL476> - -0000132a <.LVL477>: - 132a: 4785 li a5,1 - 132c: 22f12a23 sw a5,564(sp) - 1330: 006c add a1,sp,12 - 1332: 4789 li a5,2 - 1334: 8522 mv a0,s0 - 1336: 22f12623 sw a5,556(sp) - 133a: 22012423 sw zero,552(sp) - 133e: 00000097 auipc ra,0x0 - 1342: 000080e7 jalr ra # 133e <.LVL477+0x14> - -00001346 <.LVL478>: - 1346: 25c12083 lw ra,604(sp) - 134a: 10942823 sw s1,272(s0) - 134e: 25812403 lw s0,600(sp) - -00001352 <.LVL479>: - 1352: 25412483 lw s1,596(sp) - -00001356 <.LVL480>: - 1356: 26010113 add sp,sp,608 - -0000135a <.LVL481>: - 135a: 8082 ret - -0000135c : - 135c: 1151 add sp,sp,-12 - 135e: c222 sw s0,4(sp) - 1360: c026 sw s1,0(sp) - 1362: 842e mv s0,a1 - 1364: 84aa mv s1,a0 - 1366: c406 sw ra,8(sp) - 1368: 00000097 auipc ra,0x0 - 136c: 000080e7 jalr ra # 1368 - -00001370 <.LVL483>: - 1370: 23c42583 lw a1,572(s0) - 1374: 4501 li a0,0 - 1376: 00359793 sll a5,a1,0x3 - 137a: 943e add s0,s0,a5 - -0000137c <.LVL484>: - 137c: 4058 lw a4,4(s0) - 137e: 4799 li a5,6 - 1380: 00f70763 beq a4,a5,138e <.L362> - -00001384 <.LBB339>: - 1384: 8526 mv a0,s1 - 1386: 00000097 auipc ra,0x0 - 138a: 000080e7 jalr ra # 1386 <.LBB339+0x2> - -0000138e <.L362>: - 138e: 40a2 lw ra,8(sp) - 1390: 4412 lw s0,4(sp) - 1392: 10a4a823 sw a0,272(s1) - 1396: 4482 lw s1,0(sp) - -00001398 <.LVL487>: - 1398: 0131 add sp,sp,12 - 139a: 8082 ret - -0000139c <_Unwind_RaiseException_Phase2>: - 139c: da010113 add sp,sp,-608 - 13a0: 24812c23 sw s0,600(sp) - 13a4: 24912a23 sw s1,596(sp) - 13a8: 24112e23 sw ra,604(sp) - 13ac: c02a sw a0,0(sp) - 13ae: 842e mv s0,a1 - 13b0: c232 sw a2,4(sp) - 13b2: 4485 li s1,1 - -000013b4 <.L373>: - 13b4: 006c add a1,sp,12 - 13b6: 8522 mv a0,s0 - 13b8: 00000097 auipc ra,0x0 - 13bc: 000080e7 jalr ra # 13b8 <.L373+0x4> - -000013c0 <.LBB343>: - 13c0: 12442683 lw a3,292(s0) - -000013c4 <.LBE347>: - 13c4: 10c42703 lw a4,268(s0) - -000013c8 <.LBE343>: - 13c8: 4782 lw a5,0(sp) - -000013ca <.LBB350>: - 13ca: 82fd srl a3,a3,0x1f - -000013cc <.LBE350>: - 13cc: 8f15 sub a4,a4,a3 - -000013ce <.LBE352>: - 13ce: 4b94 lw a3,16(a5) - 13d0: 00e69b63 bne a3,a4,13e6 <.L367> - -000013d4 <.LVL491>: - 13d4: e939 bnez a0,142a <.L368> - 13d6: 23c12383 lw t2,572(sp) - 13da: 02039463 bnez t2,1402 <.L375> - -000013de <.L372>: - 13de: 00000097 auipc ra,0x0 - 13e2: 000080e7 jalr ra # 13de <.L372> - -000013e6 <.L367>: - 13e6: e131 bnez a0,142a <.L368> - 13e8: 23c12383 lw t2,572(sp) - 13ec: 4301 li t1,0 - 13ee: 00039b63 bnez t2,1404 <.L369> - -000013f2 <.L370>: - 13f2: 006c add a1,sp,12 - 13f4: 8522 mv a0,s0 - -000013f6 <.LVL495>: - 13f6: 00000097 auipc ra,0x0 - 13fa: 000080e7 jalr ra # 13f6 <.LVL495> - -000013fe <.LVL496>: - 13fe: 0485 add s1,s1,1 - -00001400 <.LBE342>: - 1400: bf55 j 13b4 <.L373> - -00001402 <.L375>: - 1402: 4311 li t1,4 - -00001404 <.L369>: - 1404: 4702 lw a4,0(sp) - 1406: 87a2 mv a5,s0 - 1408: 00236593 or a1,t1,2 - 140c: 4310 lw a2,0(a4) - 140e: 4354 lw a3,4(a4) - 1410: 4505 li a0,1 - -00001412 <.LVL500>: - 1412: c41a sw t1,8(sp) - 1414: 9382 jalr t2 - -00001416 <.LVL501>: - 1416: 471d li a4,7 - 1418: 02e50363 beq a0,a4,143e <.L371> - 141c: 4721 li a4,8 - 141e: 00e51663 bne a0,a4,142a <.L368> - 1422: 4322 lw t1,8(sp) - 1424: fc0307e3 beqz t1,13f2 <.L370> - 1428: bf5d j 13de <.L372> - -0000142a <.L368>: - 142a: 4509 li a0,2 - -0000142c <.L366>: - 142c: 25c12083 lw ra,604(sp) - 1430: 25812403 lw s0,600(sp) - -00001434 <.LVL503>: - 1434: 25412483 lw s1,596(sp) - -00001438 <.LVL504>: - 1438: 26010113 add sp,sp,608 - -0000143c <.LVL505>: - 143c: 8082 ret - -0000143e <.L371>: - 143e: 4792 lw a5,4(sp) - 1440: c384 sw s1,0(a5) - 1442: b7ed j 142c <.L366> - -00001444 <_Unwind_ForcedUnwind_Phase2>: - 1444: 455c lw a5,12(a0) - 1446: d9410113 add sp,sp,-620 - 144a: 26812223 sw s0,612(sp) - 144e: c43e sw a5,8(sp) - -00001450 <.LVL508>: - 1450: 491c lw a5,16(a0) - -00001452 <.LVL509>: - 1452: 26912023 sw s1,608(sp) - 1456: 26112423 sw ra,616(sp) - 145a: 842a mv s0,a0 - 145c: c22e sw a1,4(sp) - 145e: c832 sw a2,16(sp) - 1460: c63e sw a5,12(sp) - -00001462 <.LVL510>: - 1462: 4485 li s1,1 - -00001464 <.L386>: - 1464: 4512 lw a0,4(sp) - 1466: 082c add a1,sp,24 - 1468: 00000097 auipc ra,0x0 - 146c: 000080e7 jalr ra # 1468 <.L386+0x4> - -00001470 <.LVL512>: - 1470: 832a mv t1,a0 - -00001472 <.LVL513>: - 1472: c131 beqz a0,14b6 <.L390> - 1474: ffc50793 add a5,a0,-4 - 1478: 4705 li a4,1 - 147a: 04f76e63 bltu a4,a5,14d6 <.L382> - 147e: 45e9 li a1,26 - -00001480 <.L381>: - 1480: 47b2 lw a5,12(sp) - 1482: ca1a sw t1,20(sp) - -00001484 <.LVL514>: - 1484: 4322 lw t1,8(sp) - -00001486 <.LVL515>: - 1486: c03e sw a5,0(sp) - 1488: 4010 lw a2,0(s0) - 148a: 4792 lw a5,4(sp) - 148c: 4054 lw a3,4(s0) - 148e: 8722 mv a4,s0 - 1490: 4505 li a0,1 - -00001492 <.LVL516>: - 1492: 9302 jalr t1 - -00001494 <.LVL517>: - 1494: e129 bnez a0,14d6 <.L382> - 1496: 4352 lw t1,20(sp) - 1498: 4795 li a5,5 - 149a: 04f30963 beq t1,a5,14ec <.L384> - 149e: 24812303 lw t1,584(sp) - 14a2: 00031c63 bnez t1,14ba <.L385> - -000014a6 <.L388>: - 14a6: 4512 lw a0,4(sp) - 14a8: 082c add a1,sp,24 - -000014aa <.LBE355>: - 14aa: 0485 add s1,s1,1 - -000014ac <.LBB358>: - 14ac: 00000097 auipc ra,0x0 - 14b0: 000080e7 jalr ra # 14ac <.LBB358> - -000014b4 <.LBE354>: - 14b4: bf45 j 1464 <.L386> - -000014b6 <.L390>: - 14b6: 45a9 li a1,10 - 14b8: b7e1 j 1480 <.L381> - -000014ba <.L385>: - 14ba: 4792 lw a5,4(sp) - 14bc: 4010 lw a2,0(s0) - 14be: 4054 lw a3,4(s0) - 14c0: 8722 mv a4,s0 - 14c2: 45a9 li a1,10 - 14c4: 4505 li a0,1 - -000014c6 <.LVL524>: - 14c6: 9302 jalr t1 - -000014c8 <.LVL525>: - 14c8: 479d li a5,7 - 14ca: 832a mv t1,a0 - -000014cc <.LVL526>: - 14cc: 02f50063 beq a0,a5,14ec <.L384> - 14d0: 47a1 li a5,8 - 14d2: fcf50ae3 beq a0,a5,14a6 <.L388> - -000014d6 <.L382>: - 14d6: 4309 li t1,2 - -000014d8 <.L380>: - 14d8: 26812083 lw ra,616(sp) - 14dc: 26412403 lw s0,612(sp) - -000014e0 <.LVL528>: - 14e0: 26012483 lw s1,608(sp) - -000014e4 <.LVL529>: - 14e4: 851a mv a0,t1 - 14e6: 26c10113 add sp,sp,620 - -000014ea <.LVL530>: - 14ea: 8082 ret - -000014ec <.L384>: - 14ec: 47c2 lw a5,16(sp) - 14ee: c384 sw s1,0(a5) - 14f0: b7e5 j 14d8 <.L380> - -000014f2 <_Unwind_GetCFA>: - 14f2: 10c52503 lw a0,268(a0) - -000014f6 <.LVL533>: - 14f6: 8082 ret - -000014f8 <_Unwind_SetGR>: - 14f8: 04200793 li a5,66 - 14fc: 00b7d863 bge a5,a1,150c <.L394> - -00001500 <.L397>: - 1500: 1151 add sp,sp,-12 - 1502: c406 sw ra,8(sp) - 1504: 00000097 auipc ra,0x0 - 1508: 000080e7 jalr ra # 1504 <.L397+0x4> - -0000150c <.L394>: - 150c: 000007b7 lui a5,0x0 - 1510: 00078793 mv a5,a5 - 1514: 97ae add a5,a5,a1 - 1516: 0007c683 lbu a3,0(a5) # 0 - -0000151a <.LBB360>: - 151a: 12452783 lw a5,292(a0) - 151e: 40000737 lui a4,0x40000 - 1522: 8f7d and a4,a4,a5 - 1524: 00259793 sll a5,a1,0x2 - -00001528 <.LBE360>: - 1528: cb01 beqz a4,1538 <.L395> - 152a: 95aa add a1,a1,a0 - -0000152c <.LVL538>: - 152c: 1305c703 lbu a4,304(a1) - 1530: c701 beqz a4,1538 <.L395> - -00001532 <.LBB362>: - 1532: 97aa add a5,a5,a0 - -00001534 <.L406>: - 1534: c390 sw a2,0(a5) - 1536: 8082 ret - -00001538 <.L395>: - 1538: 953e add a0,a0,a5 - -0000153a <.LVL542>: - 153a: 4711 li a4,4 - 153c: 411c lw a5,0(a0) - 153e: fee68be3 beq a3,a4,1534 <.L406> - 1542: bf7d j 1500 <.L397> - -00001544 <_Unwind_GetIP>: - 1544: 11052503 lw a0,272(a0) - -00001548 <.LVL545>: - 1548: 8082 ret - -0000154a <_Unwind_GetIPInfo>: - 154a: 12452783 lw a5,292(a0) - -0000154e <.LBE364>: - 154e: 11052503 lw a0,272(a0) - -00001552 <.LBB367>: - 1552: 83fd srl a5,a5,0x1f - -00001554 <.LBE367>: - 1554: c19c sw a5,0(a1) - 1556: 8082 ret - -00001558 <_Unwind_SetIP>: - 1558: 10b52823 sw a1,272(a0) - 155c: 8082 ret - -0000155e <_Unwind_GetLanguageSpecificData>: - 155e: 11452503 lw a0,276(a0) - -00001562 <.LVL550>: - 1562: 8082 ret - -00001564 <_Unwind_GetRegionStart>: - 1564: 12052503 lw a0,288(a0) - -00001568 <.LVL552>: - 1568: 8082 ret - -0000156a <_Unwind_FindEnclosingFunction>: - 156a: 1121 add sp,sp,-24 - 156c: 858a mv a1,sp - 156e: 157d add a0,a0,-1 - -00001570 <.LVL554>: - 1570: ca06 sw ra,20(sp) - 1572: 00000097 auipc ra,0x0 - 1576: 000080e7 jalr ra # 1572 <.LVL554+0x2> - -0000157a <.LVL555>: - 157a: c111 beqz a0,157e <.L412> - 157c: 4522 lw a0,8(sp) - -0000157e <.L412>: - 157e: 40d2 lw ra,20(sp) - 1580: 0161 add sp,sp,24 - 1582: 8082 ret - -00001584 <_Unwind_GetDataRelBase>: - 1584: 11c52503 lw a0,284(a0) - -00001588 <.LVL558>: - 1588: 8082 ret - -0000158a <_Unwind_GetTextRelBase>: - 158a: 11852503 lw a0,280(a0) - -0000158e <.LVL560>: - 158e: 8082 ret - -00001590 <__frame_state_for>: - 1590: c3810113 add sp,sp,-968 - 1594: 3c812023 sw s0,960(sp) - 1598: 3a912e23 sw s1,956(sp) - 159c: 842e mv s0,a1 - 159e: 84aa mv s1,a0 - 15a0: 4581 li a1,0 - -000015a2 <.LVL562>: - 15a2: 17400613 li a2,372 - 15a6: 850a mv a0,sp - -000015a8 <.LVL563>: - 15a8: 3c112223 sw ra,964(sp) - 15ac: 00000097 auipc ra,0x0 - 15b0: 000080e7 jalr ra # 15ac <.LVL563+0x4> - -000015b4 <.LVL564>: - 15b4: 400007b7 lui a5,0x40000 - 15b8: 0485 add s1,s1,1 - -000015ba <.LVL565>: - 15ba: 1acc add a1,sp,372 - 15bc: 850a mv a0,sp - 15be: 12f12223 sw a5,292(sp) - 15c2: 10912823 sw s1,272(sp) - 15c6: 00000097 auipc ra,0x0 - 15ca: 000080e7 jalr ra # 15c6 <.LVL565+0xc> - -000015ce <.LVL566>: - 15ce: e935 bnez a0,1642 <.L426> - 15d0: 39c12703 lw a4,924(sp) - 15d4: 4789 li a5,2 - 15d6: 06f70663 beq a4,a5,1642 <.L426> - 15da: 1adc add a5,sp,372 - 15dc: 12040693 add a3,s0,288 - 15e0: 01040713 add a4,s0,16 - 15e4: 11c40513 add a0,s0,284 - 15e8: 4305 li t1,1 - 15ea: 4289 li t0,2 - -000015ec <.L424>: - 15ec: 0047c583 lbu a1,4(a5) # 40000004 <.LLST185+0x3fffd8dc> - 15f0: 00b68023 sb a1,0(a3) - 15f4: 00658563 beq a1,t1,15fe <.L422> - 15f8: 4601 li a2,0 - 15fa: 00559363 bne a1,t0,1600 <.L423> - -000015fe <.L422>: - 15fe: 4390 lw a2,0(a5) - -00001600 <.L423>: - 1600: c310 sw a2,0(a4) - -00001602 <.LVL568>: - 1602: 0711 add a4,a4,4 # 40000004 <.LLST185+0x3fffd8dc> - 1604: 07a1 add a5,a5,8 - 1606: 0685 add a3,a3,1 - -00001608 <.LVL569>: - 1608: fea712e3 bne a4,a0,15ec <.L424> - 160c: 39012783 lw a5,912(sp) - 1610: c41c sw a5,8(s0) - 1612: 39412783 lw a5,916(sp) - 1616: 10f41e23 sh a5,284(s0) - 161a: 3b012783 lw a5,944(sp) - 161e: 10f41f23 sh a5,286(s0) - 1622: 12c12783 lw a5,300(sp) - 1626: c45c sw a5,12(s0) - 1628: 3b812783 lw a5,952(sp) - 162c: c05c sw a5,4(s0) - -0000162e <.L421>: - 162e: 3c412083 lw ra,964(sp) - 1632: 8522 mv a0,s0 - 1634: 3c012403 lw s0,960(sp) - 1638: 3bc12483 lw s1,956(sp) - -0000163c <.LVL571>: - 163c: 3c810113 add sp,sp,968 - 1640: 8082 ret - -00001642 <.L426>: - 1642: 4401 li s0,0 - -00001644 <.LVL573>: - 1644: b7ed j 162e <.L421> - -00001646 <_Unwind_DebugHook>: - 1646: 8082 ret - -00001648 <_Unwind_RaiseException>: - 1648: ab010113 add sp,sp,-1360 - 164c: 54812423 sw s0,1352(sp) - 1650: 54a12023 sw a0,1344(sp) - 1654: 52b12e23 sw a1,1340(sp) - 1658: 52c12c23 sw a2,1336(sp) - 165c: 55010593 add a1,sp,1360 - 1660: 8606 mv a2,ra - 1662: 842a mv s0,a0 - 1664: 0048 add a0,sp,4 - -00001666 <.LVL576>: - 1666: 54112623 sw ra,1356(sp) - 166a: 54912223 sw s1,1348(sp) - 166e: 52d12a23 sw a3,1332(sp) - 1672: 00000097 auipc ra,0x0 - 1676: 000080e7 jalr ra # 1672 <.LVL576+0xc> - -0000167a <.LVL577>: - 167a: 17400613 li a2,372 - 167e: 004c add a1,sp,4 - 1680: 1aa8 add a0,sp,376 - 1682: 00000097 auipc ra,0x0 - 1686: 000080e7 jalr ra # 1682 <.LVL577+0x8> - -0000168a <.L435>: - 168a: 15ec add a1,sp,748 - 168c: 1aa8 add a0,sp,376 - 168e: 00000097 auipc ra,0x0 - 1692: 000080e7 jalr ra # 168e <.L435+0x4> - -00001696 <.LVL579>: - 1696: 4795 li a5,5 - 1698: 00f50463 beq a0,a5,16a0 <.L431> - 169c: c919 beqz a0,16b2 <.L433> - -0000169e <.L437>: - 169e: 450d li a0,3 - -000016a0 <.L431>: - 16a0: 54c12083 lw ra,1356(sp) - 16a4: 54812403 lw s0,1352(sp) - -000016a8 <.LVL581>: - 16a8: 54412483 lw s1,1348(sp) - 16ac: 55010113 add sp,sp,1360 - 16b0: 8082 ret - -000016b2 <.L433>: - 16b2: 51c12303 lw t1,1308(sp) - 16b6: 00031963 bnez t1,16c8 <.L434> - -000016ba <.L438>: - 16ba: 15ec add a1,sp,748 - 16bc: 1aa8 add a0,sp,376 - -000016be <.LVL583>: - 16be: 00000097 auipc ra,0x0 - 16c2: 000080e7 jalr ra # 16be <.LVL583> - -000016c6 <.LBE369>: - 16c6: b7d1 j 168a <.L435> - -000016c8 <.L434>: - 16c8: 4010 lw a2,0(s0) - 16ca: 4054 lw a3,4(s0) - 16cc: 1abc add a5,sp,376 - 16ce: 8722 mv a4,s0 - 16d0: 4585 li a1,1 - 16d2: 4505 li a0,1 - -000016d4 <.LVL586>: - 16d4: 9302 jalr t1 - -000016d6 <.LVL587>: - 16d6: 4799 li a5,6 - 16d8: 00f50663 beq a0,a5,16e4 <.L436> - 16dc: 47a1 li a5,8 - 16de: fcf50ee3 beq a0,a5,16ba <.L438> - 16e2: bf75 j 169e <.L437> - -000016e4 <.L436>: - 16e4: 29c12703 lw a4,668(sp) - -000016e8 <.LBE373>: - 16e8: 28412783 lw a5,644(sp) - -000016ec <.LBE371>: - 16ec: 17400613 li a2,372 - -000016f0 <.LBB377>: - 16f0: 837d srl a4,a4,0x1f - -000016f2 <.LBE377>: - 16f2: 8f99 sub a5,a5,a4 - -000016f4 <.LBE383>: - 16f4: c81c sw a5,16(s0) - 16f6: 004c add a1,sp,4 - 16f8: 00042623 sw zero,12(s0) - -000016fc <.LBB378>: - 16fc: 1aa8 add a0,sp,376 - -000016fe <.LVL589>: - 16fe: 00000097 auipc ra,0x0 - 1702: 000080e7 jalr ra # 16fe <.LVL589> - -00001706 <.LVL590>: - 1706: 15f0 add a2,sp,748 - 1708: 1aac add a1,sp,376 - 170a: 8522 mv a0,s0 - 170c: 00000097 auipc ra,0x0 - 1710: 000080e7 jalr ra # 170c <.LVL590+0x6> - -00001714 <.LVL591>: - 1714: 479d li a5,7 - 1716: f8f515e3 bne a0,a5,16a0 <.L431> - -0000171a <.LBB385>: - 171a: 1aac add a1,sp,376 - 171c: 0048 add a0,sp,4 - -0000171e <.LVL592>: - 171e: 00000097 auipc ra,0x0 - 1722: 000080e7 jalr ra # 171e <.LVL592> - -00001726 <.LVL593>: - 1726: 28812403 lw s0,648(sp) - -0000172a <.LVL594>: - 172a: c02a sw a0,0(sp) - -0000172c <.LVL595>: - 172c: 28412503 lw a0,644(sp) - -00001730 <.LVL596>: - 1730: 85a2 mv a1,s0 - 1732: 00000097 auipc ra,0x0 - 1736: 000080e7 jalr ra # 1732 <.LVL596+0x2> - -0000173a <.LBE385>: - 173a: 54812623 sw s0,1356(sp) - 173e: 54812403 lw s0,1352(sp) - -00001742 <.LVL598>: - 1742: 4702 lw a4,0(sp) - 1744: 54c12083 lw ra,1356(sp) - 1748: 54412483 lw s1,1348(sp) - 174c: 54012503 lw a0,1344(sp) - 1750: 53c12583 lw a1,1340(sp) - 1754: 53812603 lw a2,1336(sp) - 1758: 53412683 lw a3,1332(sp) - 175c: 55010113 add sp,sp,1360 - -00001760 <.LVL599>: - 1760: 913a add sp,sp,a4 - -00001762 <.LVL600>: - 1762: 8082 ret - -00001764 <_Unwind_ForcedUnwind>: - 1764: cf410113 add sp,sp,-780 - 1768: 30812223 sw s0,772(sp) - 176c: 30912023 sw s1,768(sp) - 1770: 842a mv s0,a0 - 1772: 2ea12e23 sw a0,764(sp) - 1776: 2eb12c23 sw a1,760(sp) - 177a: 2ec12a23 sw a2,756(sp) - 177e: c02e sw a1,0(sp) - 1780: 84b2 mv s1,a2 - 1782: 066c add a1,sp,780 - -00001784 <.LVL602>: - 1784: 8606 mv a2,ra - -00001786 <.LVL603>: - 1786: 0028 add a0,sp,8 - -00001788 <.LVL604>: - 1788: 30112423 sw ra,776(sp) - 178c: 2ed12823 sw a3,752(sp) - 1790: 00000097 auipc ra,0x0 - 1794: 000080e7 jalr ra # 1790 <.LVL604+0x8> - -00001798 <.LVL605>: - 1798: 17400613 li a2,372 - 179c: 002c add a1,sp,8 - 179e: 1ae8 add a0,sp,380 - 17a0: 00000097 auipc ra,0x0 - 17a4: 000080e7 jalr ra # 17a0 <.LVL605+0x8> - -000017a8 <.LVL606>: - 17a8: 4782 lw a5,0(sp) - 17aa: c804 sw s1,16(s0) - 17ac: 0050 add a2,sp,4 - 17ae: c45c sw a5,12(s0) - 17b0: 1aec add a1,sp,380 - 17b2: 8522 mv a0,s0 - 17b4: 00000097 auipc ra,0x0 - 17b8: 000080e7 jalr ra # 17b4 <.LVL606+0xc> - -000017bc <.LVL607>: - 17bc: 479d li a5,7 - 17be: 04f51763 bne a0,a5,180c <.L446> - -000017c2 <.LBB386>: - 17c2: 1aec add a1,sp,380 - 17c4: 0028 add a0,sp,8 - -000017c6 <.LVL608>: - 17c6: 00000097 auipc ra,0x0 - 17ca: 000080e7 jalr ra # 17c6 <.LVL608> - -000017ce <.LVL609>: - 17ce: 28c12403 lw s0,652(sp) - -000017d2 <.LVL610>: - 17d2: c02a sw a0,0(sp) - -000017d4 <.LVL611>: - 17d4: 28812503 lw a0,648(sp) - -000017d8 <.LVL612>: - 17d8: 85a2 mv a1,s0 - 17da: 00000097 auipc ra,0x0 - 17de: 000080e7 jalr ra # 17da <.LVL612+0x2> - -000017e2 <.LBE386>: - 17e2: 30812423 sw s0,776(sp) - 17e6: 30412403 lw s0,772(sp) - -000017ea <.LVL614>: - 17ea: 4702 lw a4,0(sp) - 17ec: 30812083 lw ra,776(sp) - 17f0: 30012483 lw s1,768(sp) - -000017f4 <.LVL615>: - 17f4: 2fc12503 lw a0,764(sp) - 17f8: 2f812583 lw a1,760(sp) - 17fc: 2f412603 lw a2,756(sp) - 1800: 2f012683 lw a3,752(sp) - 1804: 30c10113 add sp,sp,780 - -00001808 <.LVL616>: - 1808: 913a add sp,sp,a4 - -0000180a <.LVL617>: - 180a: 8082 ret - -0000180c <.L446>: - 180c: 30812083 lw ra,776(sp) - 1810: 30412403 lw s0,772(sp) - -00001814 <.LVL619>: - 1814: 30012483 lw s1,768(sp) - -00001818 <.LVL620>: - 1818: 30c10113 add sp,sp,780 - -0000181c <.LVL621>: - 181c: 8082 ret - -0000181e <_Unwind_Resume>: - 181e: cf410113 add sp,sp,-780 - 1822: 30812223 sw s0,772(sp) - 1826: 2ea12e23 sw a0,764(sp) - 182a: 842a mv s0,a0 - 182c: 2eb12c23 sw a1,760(sp) - 1830: 2ec12a23 sw a2,756(sp) - 1834: 066c add a1,sp,780 - 1836: 8606 mv a2,ra - 1838: 0028 add a0,sp,8 - -0000183a <.LVL623>: - 183a: 30112423 sw ra,776(sp) - 183e: 2ed12823 sw a3,752(sp) - 1842: 30912023 sw s1,768(sp) - 1846: 00000097 auipc ra,0x0 - 184a: 000080e7 jalr ra # 1846 <.LVL623+0xc> - -0000184e <.LVL624>: - 184e: 17400613 li a2,372 - 1852: 002c add a1,sp,8 - 1854: 1ae8 add a0,sp,380 - 1856: 00000097 auipc ra,0x0 - 185a: 000080e7 jalr ra # 1856 <.LVL624+0x8> - -0000185e <.LVL625>: - 185e: 445c lw a5,12(s0) - 1860: 0050 add a2,sp,4 - 1862: 1aec add a1,sp,380 - 1864: 8522 mv a0,s0 - 1866: ef81 bnez a5,187e <.L448> - 1868: 00000097 auipc ra,0x0 - 186c: 000080e7 jalr ra # 1868 <.LVL625+0xa> - -00001870 <.L449>: - 1870: 479d li a5,7 - 1872: 00f50b63 beq a0,a5,1888 <.L450> - 1876: 00000097 auipc ra,0x0 - 187a: 000080e7 jalr ra # 1876 <.L449+0x6> - -0000187e <.L448>: - 187e: 00000097 auipc ra,0x0 - 1882: 000080e7 jalr ra # 187e <.L448> - -00001886 <.LVL628>: - 1886: b7ed j 1870 <.L449> - -00001888 <.L450>: - 1888: 1aec add a1,sp,380 - 188a: 0028 add a0,sp,8 - -0000188c <.LVL630>: - 188c: 00000097 auipc ra,0x0 - 1890: 000080e7 jalr ra # 188c <.LVL630> - -00001894 <.LVL631>: - 1894: 28c12403 lw s0,652(sp) - -00001898 <.LVL632>: - 1898: c02a sw a0,0(sp) - -0000189a <.LVL633>: - 189a: 28812503 lw a0,648(sp) - -0000189e <.LVL634>: - 189e: 85a2 mv a1,s0 - 18a0: 00000097 auipc ra,0x0 - 18a4: 000080e7 jalr ra # 18a0 <.LVL634+0x2> - -000018a8 <.LBE387>: - 18a8: 30812423 sw s0,776(sp) - 18ac: 30412403 lw s0,772(sp) - -000018b0 <.LVL636>: - 18b0: 4702 lw a4,0(sp) - 18b2: 30812083 lw ra,776(sp) - 18b6: 30012483 lw s1,768(sp) - 18ba: 2fc12503 lw a0,764(sp) - 18be: 2f812583 lw a1,760(sp) - 18c2: 2f412603 lw a2,756(sp) - 18c6: 2f012683 lw a3,752(sp) - 18ca: 30c10113 add sp,sp,780 - -000018ce <.LVL637>: - 18ce: 913a add sp,sp,a4 - -000018d0 <.LVL638>: - 18d0: 8082 ret - -000018d2 <_Unwind_Resume_or_Rethrow>: - 18d2: 455c lw a5,12(a0) - 18d4: cf410113 add sp,sp,-780 - 18d8: 30812223 sw s0,772(sp) - 18dc: 2ec12a23 sw a2,756(sp) - 18e0: 30112423 sw ra,776(sp) - 18e4: 30912023 sw s1,768(sp) - 18e8: 2ea12e23 sw a0,764(sp) - 18ec: 2eb12c23 sw a1,760(sp) - 18f0: 2ed12823 sw a3,752(sp) - 18f4: 8606 mv a2,ra - 18f6: 842a mv s0,a0 - 18f8: c3d1 beqz a5,197c <.L459> - 18fa: 066c add a1,sp,780 - 18fc: 0028 add a0,sp,8 - -000018fe <.LVL640>: - 18fe: 00000097 auipc ra,0x0 - 1902: 000080e7 jalr ra # 18fe <.LVL640> - -00001906 <.LVL641>: - 1906: 17400613 li a2,372 - 190a: 002c add a1,sp,8 - 190c: 1ae8 add a0,sp,380 - 190e: 00000097 auipc ra,0x0 - 1912: 000080e7 jalr ra # 190e <.LVL641+0x8> - -00001916 <.LVL642>: - 1916: 0050 add a2,sp,4 - 1918: 1aec add a1,sp,380 - 191a: 8522 mv a0,s0 - 191c: 00000097 auipc ra,0x0 - 1920: 000080e7 jalr ra # 191c <.LVL642+0x6> - -00001924 <.LVL643>: - 1924: 479d li a5,7 - 1926: 00f50663 beq a0,a5,1932 <.L455> - 192a: 00000097 auipc ra,0x0 - 192e: 000080e7 jalr ra # 192a <.LVL643+0x6> - -00001932 <.L455>: - 1932: 1aec add a1,sp,380 - 1934: 0028 add a0,sp,8 - -00001936 <.LVL645>: - 1936: 00000097 auipc ra,0x0 - 193a: 000080e7 jalr ra # 1936 <.LVL645> - -0000193e <.LVL646>: - 193e: 28c12403 lw s0,652(sp) - -00001942 <.LVL647>: - 1942: c02a sw a0,0(sp) - -00001944 <.LVL648>: - 1944: 28812503 lw a0,648(sp) - -00001948 <.LVL649>: - 1948: 85a2 mv a1,s0 - 194a: 00000097 auipc ra,0x0 - 194e: 000080e7 jalr ra # 194a <.LVL649+0x2> - -00001952 <.LBE388>: - 1952: 30812423 sw s0,776(sp) - 1956: 30412403 lw s0,772(sp) - -0000195a <.LVL651>: - 195a: 4702 lw a4,0(sp) - 195c: 30812083 lw ra,776(sp) - 1960: 30012483 lw s1,768(sp) - 1964: 2fc12503 lw a0,764(sp) - 1968: 2f812583 lw a1,760(sp) - 196c: 2f412603 lw a2,756(sp) - 1970: 2f012683 lw a3,752(sp) - 1974: 30c10113 add sp,sp,780 - -00001978 <.LVL652>: - 1978: 913a add sp,sp,a4 - -0000197a <.LVL653>: - 197a: 8082 ret - -0000197c <.L459>: - 197c: 00000097 auipc ra,0x0 - 1980: 000080e7 jalr ra # 197c <.L459> - -00001984 <.LVL655>: - 1984: 30812083 lw ra,776(sp) - 1988: 30412403 lw s0,772(sp) - -0000198c <.LVL656>: - 198c: 30012483 lw s1,768(sp) - 1990: 30c10113 add sp,sp,780 - 1994: 8082 ret - -00001996 <_Unwind_DeleteException>: - 1996: 451c lw a5,8(a0) - 1998: 85aa mv a1,a0 - 199a: c399 beqz a5,19a0 <.L460> - 199c: 4505 li a0,1 - -0000199e <.LVL658>: - 199e: 8782 jr a5 - -000019a0 <.L460>: - 19a0: 8082 ret - -000019a2 <_Unwind_Backtrace>: - 19a2: c3410113 add sp,sp,-972 - 19a6: 3c812223 sw s0,964(sp) - 19aa: c02e sw a1,0(sp) - 19ac: 842a mv s0,a0 - 19ae: 8606 mv a2,ra - 19b0: 07ec add a1,sp,972 - -000019b2 <.LVL661>: - 19b2: 0048 add a0,sp,4 - -000019b4 <.LVL662>: - 19b4: 3c112423 sw ra,968(sp) - 19b8: 3c912023 sw s1,960(sp) - 19bc: 00000097 auipc ra,0x0 - 19c0: 000080e7 jalr ra # 19bc <.LVL662+0x8> - -000019c4 <.L466>: - 19c4: 1aac add a1,sp,376 - 19c6: 0048 add a0,sp,4 - 19c8: 00000097 auipc ra,0x0 - 19cc: 000080e7 jalr ra # 19c8 <.L466+0x4> - -000019d0 <.LVL664>: - 19d0: 84aa mv s1,a0 - -000019d2 <.LVL665>: - 19d2: c511 beqz a0,19de <.L463> - 19d4: ffc50713 add a4,a0,-4 - 19d8: 4685 li a3,1 - 19da: 02e6e063 bltu a3,a4,19fa <.L464> - -000019de <.L463>: - 19de: 4582 lw a1,0(sp) - 19e0: 0048 add a0,sp,4 - 19e2: 9402 jalr s0 - -000019e4 <.LVL666>: - 19e4: e919 bnez a0,19fa <.L464> - 19e6: 4715 li a4,5 - 19e8: 00e48a63 beq s1,a4,19fc <.L462> - 19ec: 1aac add a1,sp,376 - 19ee: 0048 add a0,sp,4 - 19f0: 00000097 auipc ra,0x0 - 19f4: 000080e7 jalr ra # 19f0 <.LVL666+0xc> - -000019f8 <.LBE389>: - 19f8: b7f1 j 19c4 <.L466> - -000019fa <.L464>: - 19fa: 448d li s1,3 - -000019fc <.L462>: - 19fc: 3c812083 lw ra,968(sp) - 1a00: 3c412403 lw s0,964(sp) - -00001a04 <.LVL669>: - 1a04: 8526 mv a0,s1 - 1a06: 3c012483 lw s1,960(sp) - 1a0a: 3cc10113 add sp,sp,972 - -00001a0e <.LVL670>: - 1a0e: 8082 ret - -unwind-dw2-fde.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 : - 0: 4701 li a4,0 - 2: 4681 li a3,0 - -00000004 <.L2>: - 4: 00054783 lbu a5,0(a0) - 8: 0505 add a0,a0,1 - -0000000a <.LVL2>: - a: 07f7f613 and a2,a5,127 - e: 07e2 sll a5,a5,0x18 - -00000010 <.LVL3>: - 10: 00d61633 sll a2,a2,a3 - 14: 87e1 sra a5,a5,0x18 - 16: 8f51 or a4,a4,a2 - 18: 069d add a3,a3,7 - 1a: fe07c5e3 bltz a5,4 <.L2> - 1e: c198 sw a4,0(a1) - -00000020 <.LVL6>: - 20: 8082 ret - -00000022 : - 22: 4781 li a5,0 - 24: 4701 li a4,0 - -00000026 <.L5>: - 26: 00054683 lbu a3,0(a0) - 2a: 0505 add a0,a0,1 - -0000002c <.LVL9>: - 2c: 07f6f613 and a2,a3,127 - 30: 00e61633 sll a2,a2,a4 - 34: 8fd1 or a5,a5,a2 - 36: 01869613 sll a2,a3,0x18 - 3a: 8661 sra a2,a2,0x18 - 3c: 071d add a4,a4,7 - 3e: fe0644e3 bltz a2,26 <.L5> - 42: 467d li a2,31 - 44: 00e66963 bltu a2,a4,56 <.L6> - 48: 0406f693 and a3,a3,64 - -0000004c <.LVL12>: - 4c: c689 beqz a3,56 <.L6> - 4e: 56fd li a3,-1 - 50: 00e69733 sll a4,a3,a4 - -00000054 <.LVL13>: - 54: 8fd9 or a5,a5,a4 - -00000056 <.L6>: - 56: c19c sw a5,0(a1) - -00000058 <.LVL15>: - 58: 8082 ret - -0000005a : - 5a: 1101 add sp,sp,-32 - 5c: 00169793 sll a5,a3,0x1 - 60: cc22 sw s0,24(sp) - 62: ce06 sw ra,28(sp) - 64: ca26 sw s1,20(sp) - 66: c02a sw a0,0(sp) - 68: c22e sw a1,4(sp) - 6a: 8432 mv s0,a2 - 6c: c43a sw a4,8(sp) - 6e: 0785 add a5,a5,1 - -00000070 <.L12>: - 70: 4722 lw a4,8(sp) - 72: 00e7c763 blt a5,a4,80 <.L16> - -00000076 <.L11>: - 76: 40f2 lw ra,28(sp) - 78: 4462 lw s0,24(sp) - -0000007a <.LVL19>: - 7a: 44d2 lw s1,20(sp) - 7c: 6105 add sp,sp,32 - -0000007e <.LVL20>: - 7e: 8082 ret - -00000080 <.L16>: - 80: 4722 lw a4,8(sp) - 82: 00178493 add s1,a5,1 - 86: 02e4d063 bge s1,a4,a6 <.L13> - 8a: 00279593 sll a1,a5,0x2 - 8e: 95a2 add a1,a1,s0 - 90: 41d0 lw a2,4(a1) - 92: c63e sw a5,12(sp) - 94: 418c lw a1,0(a1) - 96: 4792 lw a5,4(sp) - -00000098 <.LVL22>: - 98: 4502 lw a0,0(sp) - 9a: c836 sw a3,16(sp) - 9c: 9782 jalr a5 - -0000009e <.LVL23>: - 9e: 47b2 lw a5,12(sp) - a0: 46c2 lw a3,16(sp) - a2: 00054363 bltz a0,a8 <.L14> - -000000a6 <.L13>: - a6: 84be mv s1,a5 - -000000a8 <.L14>: - a8: 068a sll a3,a3,0x2 - aa: 00249793 sll a5,s1,0x2 - ae: 97a2 add a5,a5,s0 - b0: 96a2 add a3,a3,s0 - b2: 4390 lw a2,0(a5) - b4: c83e sw a5,16(sp) - b6: 428c lw a1,0(a3) - b8: 4502 lw a0,0(sp) - ba: 4792 lw a5,4(sp) - bc: c636 sw a3,12(sp) - be: 9782 jalr a5 - -000000c0 <.LVL26>: - c0: fa055be3 bgez a0,76 <.L11> - -000000c4 <.LBB49>: - c4: 47c2 lw a5,16(sp) - c6: 46b2 lw a3,12(sp) - c8: 438c lw a1,0(a5) - ca: 4290 lw a2,0(a3) - cc: c28c sw a1,0(a3) - ce: c390 sw a2,0(a5) - -000000d0 <.LBE49>: - d0: 00149793 sll a5,s1,0x1 - d4: 0785 add a5,a5,1 - -000000d6 <.LVL29>: - d6: 86a6 mv a3,s1 - d8: bf61 j 70 <.L12> - -000000da : - da: 1111 add sp,sp,-28 - dc: ca22 sw s0,20(sp) - de: 4240 lw s0,4(a2) - e0: 00860793 add a5,a2,8 - e4: c826 sw s1,16(sp) - e6: cc06 sw ra,24(sp) - e8: c22a sw a0,4(sp) - ea: c42e sw a1,8(sp) - ec: 84b2 mv s1,a2 - ee: c03e sw a5,0(sp) - -000000f0 <.LVL31>: - f0: 00145693 srl a3,s0,0x1 - -000000f4 <.L25>: - f4: 16fd add a3,a3,-1 - -000000f6 <.LVL33>: - f6: 577d li a4,-1 - f8: 02e69063 bne a3,a4,118 <.L21> - fc: 00241793 sll a5,s0,0x2 - 100: fff40713 add a4,s0,-1 - -00000104 <.LVL34>: - 104: 00f48433 add s0,s1,a5 - -00000108 <.L22>: - 108: 1471 add s0,s0,-4 - 10a: 02e04263 bgtz a4,12e <.L23> - 10e: 40e2 lw ra,24(sp) - 110: 4452 lw s0,20(sp) - 112: 44c2 lw s1,16(sp) - -00000114 <.LVL36>: - 114: 0171 add sp,sp,28 - -00000116 <.LVL37>: - 116: 8082 ret - -00000118 <.L21>: - 118: 4602 lw a2,0(sp) - 11a: 45a2 lw a1,8(sp) - 11c: 4512 lw a0,4(sp) - 11e: 8722 mv a4,s0 - 120: c636 sw a3,12(sp) - 122: 00000097 auipc ra,0x0 - 126: 000080e7 jalr ra # 122 <.L21+0xa> - -0000012a <.LVL39>: - 12a: 46b2 lw a3,12(sp) - 12c: b7e1 j f4 <.L25> - -0000012e <.L23>: - 12e: 4410 lw a2,8(s0) - 130: 4494 lw a3,8(s1) - -00000132 <.LBE50>: - 132: 45a2 lw a1,8(sp) - -00000134 <.LBB51>: - 134: c490 sw a2,8(s1) - -00000136 <.LBE51>: - 136: 4512 lw a0,4(sp) - 138: 4602 lw a2,0(sp) - -0000013a <.LBB52>: - 13a: c414 sw a3,8(s0) - -0000013c <.LBE52>: - 13c: 4681 li a3,0 - -0000013e <.LVL42>: - 13e: c63a sw a4,12(sp) - 140: 00000097 auipc ra,0x0 - 144: 000080e7 jalr ra # 140 <.LVL42+0x2> - -00000148 <.LVL43>: - 148: 4732 lw a4,12(sp) - 14a: 177d add a4,a4,-1 - -0000014c <.LVL44>: - 14c: bf75 j 108 <.L22> - -0000014e : - 14e: 0ff00793 li a5,255 - 152: 02f50963 beq a0,a5,184 <.L30> - 156: 00757793 and a5,a0,7 - 15a: 4709 li a4,2 - 15c: 02e78663 beq a5,a4,188 <.L31> - 160: 00f76a63 bltu a4,a5,174 <.L28> - 164: 4511 li a0,4 - -00000166 <.LVL46>: - 166: cf91 beqz a5,182 <.L26> - -00000168 <.L29>: - 168: 1151 add sp,sp,-12 - 16a: c406 sw ra,8(sp) - 16c: 00000097 auipc ra,0x0 - 170: 000080e7 jalr ra # 16c <.L29+0x4> - -00000174 <.L28>: - 174: 470d li a4,3 - 176: 00e78b63 beq a5,a4,18c <.L33> - 17a: 4711 li a4,4 - 17c: 4521 li a0,8 - -0000017e <.LVL48>: - 17e: fee795e3 bne a5,a4,168 <.L29> - -00000182 <.L26>: - 182: 8082 ret - -00000184 <.L30>: - 184: 4501 li a0,0 - -00000186 <.LVL50>: - 186: 8082 ret - -00000188 <.L31>: - 188: 4509 li a0,2 - -0000018a <.LVL52>: - 18a: 8082 ret - -0000018c <.L33>: - 18c: 4511 li a0,4 - -0000018e <.LVL54>: - 18e: bfd5 j 182 <.L26> - -00000190 : - 190: 0ff00793 li a5,255 - 194: 02f50d63 beq a0,a5,1ce <.L44> - 198: 07057793 and a5,a0,112 - 19c: 02000713 li a4,32 - 1a0: 02e78363 beq a5,a4,1c6 <.L40> - 1a4: 02f77563 bgeu a4,a5,1ce <.L44> - 1a8: 03000713 li a4,48 - 1ac: 00e78f63 beq a5,a4,1ca <.L41> - 1b0: 05000713 li a4,80 - 1b4: 4501 li a0,0 - -000001b6 <.LVL56>: - 1b6: 00e78d63 beq a5,a4,1d0 <.L38> - 1ba: 1151 add sp,sp,-12 - 1bc: c406 sw ra,8(sp) - 1be: 00000097 auipc ra,0x0 - 1c2: 000080e7 jalr ra # 1be <.LVL56+0x8> - -000001c6 <.L40>: - 1c6: 41c8 lw a0,4(a1) - -000001c8 <.LVL58>: - 1c8: 8082 ret - -000001ca <.L41>: - 1ca: 4588 lw a0,8(a1) - -000001cc <.LVL60>: - 1cc: 8082 ret - -000001ce <.L44>: - 1ce: 4501 li a0,0 - -000001d0 <.L38>: - 1d0: 8082 ret - -000001d2 : - 1d2: 1121 add sp,sp,-24 - 1d4: ca06 sw ra,20(sp) - 1d6: c822 sw s0,16(sp) - 1d8: c626 sw s1,12(sp) - 1da: c036 sw a3,0(sp) - 1dc: 05000793 li a5,80 - 1e0: 00f51e63 bne a0,a5,1fc <.L51> - -000001e4 <.LBB53>: - 1e4: 00360513 add a0,a2,3 - -000001e8 <.LVL65>: - 1e8: 9971 and a0,a0,-4 - -000001ea <.LVL66>: - 1ea: 411c lw a5,0(a0) - -000001ec <.LVL67>: - 1ec: 0511 add a0,a0,4 - -000001ee <.L52>: - 1ee: 4702 lw a4,0(sp) - 1f0: 40d2 lw ra,20(sp) - 1f2: 4442 lw s0,16(sp) - 1f4: c31c sw a5,0(a4) - 1f6: 44b2 lw s1,12(sp) - 1f8: 0161 add sp,sp,24 - -000001fa <.LVL69>: - 1fa: 8082 ret - -000001fc <.L51>: - 1fc: 00f57793 and a5,a0,15 - 200: 46b1 li a3,12 - -00000202 <.LVL71>: - 202: 84aa mv s1,a0 - 204: 0af6ef63 bltu a3,a5,2c2 <.L53> - 208: 000006b7 lui a3,0x0 - 20c: 078a sll a5,a5,0x2 - 20e: 00068693 mv a3,a3 - 212: 97b6 add a5,a5,a3 - 214: 439c lw a5,0(a5) - 216: 842e mv s0,a1 - 218: 8782 jr a5 - -0000021a <.L62>: - 21a: 002c add a1,sp,8 - 21c: 8532 mv a0,a2 - -0000021e <.LVL73>: - 21e: c232 sw a2,4(sp) - 220: 00000097 auipc ra,0x0 - 224: 000080e7 jalr ra # 220 <.LVL73+0x2> - -00000228 <.L70>: - 228: 47a2 lw a5,8(sp) - -0000022a <.LBE55>: - 22a: 4612 lw a2,4(sp) - -0000022c <.L64>: - 22c: d3e9 beqz a5,1ee <.L52> - 22e: 0704f693 and a3,s1,112 - 232: 45c1 li a1,16 - 234: 00b69363 bne a3,a1,23a <.L65> - 238: 8432 mv s0,a2 - -0000023a <.L65>: - 23a: 01849713 sll a4,s1,0x18 - 23e: 8761 sra a4,a4,0x18 - 240: 97a2 add a5,a5,s0 - 242: fa0756e3 bgez a4,1ee <.L52> - 246: 439c lw a5,0(a5) - 248: b75d j 1ee <.L52> - -0000024a <.L58>: - 24a: 002c add a1,sp,8 - 24c: 8532 mv a0,a2 - -0000024e <.LVL81>: - 24e: c232 sw a2,4(sp) - 250: 00000097 auipc ra,0x0 - 254: 000080e7 jalr ra # 250 <.LVL81+0x2> - -00000258 <.LVL82>: - 258: bfc1 j 228 <.L70> - -0000025a <.L61>: - 25a: 00164783 lbu a5,1(a2) - 25e: 00064683 lbu a3,0(a2) - 262: 07a2 sll a5,a5,0x8 - 264: 8fd5 or a5,a5,a3 - -00000266 <.L71>: - 266: 00260513 add a0,a2,2 - -0000026a <.LVL85>: - 26a: b7c9 j 22c <.L64> - -0000026c <.L57>: - 26c: 00164783 lbu a5,1(a2) - 270: 00064683 lbu a3,0(a2) - 274: 07a2 sll a5,a5,0x8 - 276: 8fd5 or a5,a5,a3 - 278: 07c2 sll a5,a5,0x10 - 27a: 87c1 sra a5,a5,0x10 - 27c: b7ed j 266 <.L71> - -0000027e <.L56>: - 27e: 00164783 lbu a5,1(a2) - 282: 00064683 lbu a3,0(a2) - 286: 00460513 add a0,a2,4 - -0000028a <.LVL87>: - 28a: 07a2 sll a5,a5,0x8 - 28c: 8fd5 or a5,a5,a3 - 28e: 00264683 lbu a3,2(a2) - 292: 06c2 sll a3,a3,0x10 - 294: 8edd or a3,a3,a5 - 296: 00364783 lbu a5,3(a2) - 29a: 07e2 sll a5,a5,0x18 - 29c: 8fd5 or a5,a5,a3 - -0000029e <.LVL88>: - 29e: b779 j 22c <.L64> - -000002a0 <.L54>: - 2a0: 00164783 lbu a5,1(a2) - 2a4: 00064683 lbu a3,0(a2) - 2a8: 00860513 add a0,a2,8 - -000002ac <.LVL90>: - 2ac: 07a2 sll a5,a5,0x8 - 2ae: 8fd5 or a5,a5,a3 - 2b0: 00264683 lbu a3,2(a2) - 2b4: 06c2 sll a3,a3,0x10 - 2b6: 8edd or a3,a3,a5 - 2b8: 00364783 lbu a5,3(a2) - 2bc: 07e2 sll a5,a5,0x18 - 2be: 8fd5 or a5,a5,a3 - -000002c0 <.LVL91>: - 2c0: b7b5 j 22c <.L64> - -000002c2 <.L53>: - 2c2: 00000097 auipc ra,0x0 - 2c6: 000080e7 jalr ra # 2c2 <.L53> - -000002ca : - 2ca: 1121 add sp,sp,-24 - 2cc: c822 sw s0,16(sp) - 2ce: 4900 lw s0,16(a0) - 2d0: c02e sw a1,0(sp) - 2d2: 85aa mv a1,a0 - -000002d4 <.LVL95>: - 2d4: 800d srl s0,s0,0x3 - 2d6: 0ff47413 zext.b s0,s0 - 2da: 8522 mv a0,s0 - -000002dc <.LVL96>: - 2dc: ca06 sw ra,20(sp) - 2de: c626 sw s1,12(sp) - 2e0: 84b2 mv s1,a2 - 2e2: 00000097 auipc ra,0x0 - 2e6: 000080e7 jalr ra # 2e2 <.LVL96+0x6> - -000002ea <.LVL97>: - 2ea: 4782 lw a5,0(sp) - 2ec: 85aa mv a1,a0 - -000002ee <.LVL98>: - 2ee: 0054 add a3,sp,4 - 2f0: 00878613 add a2,a5,8 - 2f4: c02a sw a0,0(sp) - -000002f6 <.LVL99>: - 2f6: 8522 mv a0,s0 - -000002f8 <.LVL100>: - 2f8: 00000097 auipc ra,0x0 - 2fc: 000080e7 jalr ra # 2f8 <.LVL100> - -00000300 <.LVL101>: - 300: 4582 lw a1,0(sp) - 302: 0034 add a3,sp,8 - 304: 00848613 add a2,s1,8 - 308: 8522 mv a0,s0 - 30a: 00000097 auipc ra,0x0 - 30e: 000080e7 jalr ra # 30a <.LVL101+0xa> - -00000312 <.LVL102>: - 312: 4512 lw a0,4(sp) - 314: 47a2 lw a5,8(sp) - 316: 00a7eb63 bltu a5,a0,32c <.L74> - 31a: 00f53533 sltu a0,a0,a5 - 31e: 40a00533 neg a0,a0 - -00000322 <.L72>: - 322: 40d2 lw ra,20(sp) - 324: 4442 lw s0,16(sp) - 326: 44b2 lw s1,12(sp) - -00000328 <.LVL103>: - 328: 0161 add sp,sp,24 - -0000032a <.LVL104>: - 32a: 8082 ret - -0000032c <.L74>: - 32c: 4505 li a0,1 - 32e: bfd5 j 322 <.L72> - -00000330 : - 330: 1121 add sp,sp,-24 - 332: c626 sw s1,12(sp) - 334: 00950493 add s1,a0,9 - -00000338 <.LVL107>: - 338: c822 sw s0,16(sp) - 33a: 842a mv s0,a0 - 33c: 8526 mv a0,s1 - -0000033e <.LVL108>: - 33e: ca06 sw ra,20(sp) - 340: 00000097 auipc ra,0x0 - 344: 000080e7 jalr ra # 340 <.LVL108+0x2> - -00000348 <.LVL109>: - 348: 0505 add a0,a0,1 - 34a: 9526 add a0,a0,s1 - -0000034c <.LVL110>: - 34c: 00844483 lbu s1,8(s0) - -00000350 <.LVL111>: - 350: 478d li a5,3 - 352: 0097fd63 bgeu a5,s1,36c <.L77> - 356: 00054683 lbu a3,0(a0) - 35a: 4711 li a4,4 - 35c: 0ff00793 li a5,255 - 360: 00e69d63 bne a3,a4,37a <.L76> - 364: 00154703 lbu a4,1(a0) - 368: eb09 bnez a4,37a <.L76> - 36a: 0509 add a0,a0,2 - -0000036c <.L77>: - 36c: 00944703 lbu a4,9(s0) - 370: 07a00793 li a5,122 - 374: 00f70963 beq a4,a5,386 <.L79> - -00000378 <.L86>: - 378: 4781 li a5,0 - -0000037a <.L76>: - 37a: 40d2 lw ra,20(sp) - 37c: 4442 lw s0,16(sp) - 37e: 44b2 lw s1,12(sp) - 380: 853e mv a0,a5 - -00000382 <.LVL114>: - 382: 0161 add sp,sp,24 - 384: 8082 ret - -00000386 <.L79>: - 386: 004c add a1,sp,4 - 388: 00000097 auipc ra,0x0 - 38c: 000080e7 jalr ra # 388 <.L79+0x2> - -00000390 <.LVL116>: - 390: 002c add a1,sp,8 - 392: 00000097 auipc ra,0x0 - 396: 000080e7 jalr ra # 392 <.LVL116+0x2> - -0000039a <.LVL117>: - 39a: 4705 li a4,1 - 39c: 02e49263 bne s1,a4,3c0 <.L80> - 3a0: 0505 add a0,a0,1 - -000003a2 <.L81>: - 3a2: 004c add a1,sp,4 - 3a4: 0429 add s0,s0,10 - -000003a6 <.LVL119>: - 3a6: 00000097 auipc ra,0x0 - 3aa: 000080e7 jalr ra # 3a6 <.LVL119> - -000003ae <.L87>: - 3ae: 00044783 lbu a5,0(s0) - 3b2: 05200713 li a4,82 - 3b6: 00e79b63 bne a5,a4,3cc <.L82> - 3ba: 00054783 lbu a5,0(a0) - 3be: bf75 j 37a <.L76> - -000003c0 <.L80>: - 3c0: 004c add a1,sp,4 - 3c2: 00000097 auipc ra,0x0 - 3c6: 000080e7 jalr ra # 3c2 <.L80+0x2> - -000003ca <.LVL122>: - 3ca: bfe1 j 3a2 <.L81> - -000003cc <.L82>: - 3cc: 05000713 li a4,80 - 3d0: 02e79063 bne a5,a4,3f0 <.L83> - 3d4: 00054783 lbu a5,0(a0) - 3d8: 00150613 add a2,a0,1 - 3dc: 868a mv a3,sp - 3de: 4581 li a1,0 - 3e0: 07f7f513 and a0,a5,127 - -000003e4 <.LVL124>: - 3e4: 00000097 auipc ra,0x0 - 3e8: 000080e7 jalr ra # 3e4 <.LVL124> - -000003ec <.L84>: - 3ec: 0405 add s0,s0,1 - 3ee: b7c1 j 3ae <.L87> - -000003f0 <.L83>: - 3f0: 04c00713 li a4,76 - 3f4: 00e79463 bne a5,a4,3fc <.L85> - -000003f8 <.L91>: - 3f8: 0505 add a0,a0,1 - 3fa: bfcd j 3ec <.L84> - -000003fc <.L85>: - 3fc: 04200713 li a4,66 - 400: fee78ce3 beq a5,a4,3f8 <.L91> - 404: bf95 j 378 <.L86> - -00000406 : - 406: fd810113 add sp,sp,-40 - 40a: ce26 sw s1,28(sp) - 40c: d206 sw ra,36(sp) - 40e: 84ae mv s1,a1 - 410: d022 sw s0,32(sp) - 412: 832a mv t1,a0 - 414: 4581 li a1,0 - -00000416 <.LVL129>: - 416: 4281 li t0,0 - 418: c002 sw zero,0(sp) - 41a: 4781 li a5,0 - -0000041c <.L93>: - 41c: 4098 lw a4,0(s1) - 41e: c43a sw a4,8(sp) - -00000420 <.LBE57>: - 420: c70d beqz a4,44a <.L92> - -00000422 <.LBB59>: - 422: 40d4 lw a3,4(s1) - 424: c2f5 beqz a3,508 <.L94> - -00000426 <.LBB60>: - 426: 00448413 add s0,s1,4 - 42a: 8c15 sub s0,s0,a3 - -0000042c <.LBE60>: - 42c: 06878463 beq a5,s0,494 <.L95> - 430: 8522 mv a0,s0 - 432: c21a sw t1,4(sp) - -00000434 <.LVL134>: - 434: 00000097 auipc ra,0x0 - 438: 000080e7 jalr ra # 434 <.LVL134> - -0000043c <.LVL135>: - 43c: 0ff00793 li a5,255 - 440: 4312 lw t1,4(sp) - 442: 00f51b63 bne a0,a5,458 <.L96> - 446: 57fd li a5,-1 - 448: c03e sw a5,0(sp) - -0000044a <.L92>: - 44a: 5092 lw ra,36(sp) - 44c: 5402 lw s0,32(sp) - 44e: 4502 lw a0,0(sp) - 450: 44f2 lw s1,28(sp) - -00000452 <.LVL137>: - 452: 02810113 add sp,sp,40 - 456: 8082 ret - -00000458 <.L96>: - 458: 0ff57693 zext.b a3,a0 - 45c: 859a mv a1,t1 - 45e: c82a sw a0,16(sp) - 460: 8536 mv a0,a3 - -00000462 <.LVL139>: - 462: c61a sw t1,12(sp) - 464: c236 sw a3,4(sp) - 466: 00000097 auipc ra,0x0 - 46a: 000080e7 jalr ra # 466 <.LVL139+0x4> - -0000046e <.LVL140>: - 46e: 4332 lw t1,12(sp) - 470: 85aa mv a1,a0 - -00000472 <.LVL141>: - 472: 7f800613 li a2,2040 - 476: 01032783 lw a5,16(t1) - 47a: 4692 lw a3,4(sp) - 47c: 42c2 lw t0,16(sp) - 47e: 7f87f513 and a0,a5,2040 - -00000482 <.LVL142>: - 482: 06c51963 bne a0,a2,4f4 <.L98> - 486: 00369513 sll a0,a3,0x3 - 48a: 8077f793 and a5,a5,-2041 - 48e: 8fc9 or a5,a5,a0 - -00000490 <.L111>: - 490: 00f32823 sw a5,16(t1) - -00000494 <.L95>: - 494: 0ff2f793 zext.b a5,t0 - 498: 0834 add a3,sp,24 - 49a: 853e mv a0,a5 - 49c: 00848613 add a2,s1,8 - 4a0: ca1a sw t1,20(sp) - -000004a2 <.LVL144>: - 4a2: c816 sw t0,16(sp) - 4a4: c62e sw a1,12(sp) - 4a6: c23e sw a5,4(sp) - 4a8: 00000097 auipc ra,0x0 - 4ac: 000080e7 jalr ra # 4a8 <.LVL144+0x6> - -000004b0 <.LVL145>: - 4b0: 4512 lw a0,4(sp) - 4b2: 00000097 auipc ra,0x0 - 4b6: 000080e7 jalr ra # 4b2 <.LVL145+0x2> - -000004ba <.LVL146>: - 4ba: 468d li a3,3 - 4bc: 45b2 lw a1,12(sp) - 4be: 42c2 lw t0,16(sp) - 4c0: 4352 lw t1,20(sp) - 4c2: 57fd li a5,-1 - 4c4: 00a6e763 bltu a3,a0,4d2 <.L101> - 4c8: 050e sll a0,a0,0x3 - -000004ca <.LVL147>: - 4ca: 4785 li a5,1 - 4cc: 00a797b3 sll a5,a5,a0 - 4d0: 17fd add a5,a5,-1 - -000004d2 <.L101>: - 4d2: 46e2 lw a3,24(sp) - 4d4: 8ff5 and a5,a5,a3 - -000004d6 <.LVL149>: - 4d6: cb85 beqz a5,506 <.L106> - 4d8: 4782 lw a5,0(sp) - 4da: 0785 add a5,a5,1 - 4dc: c03e sw a5,0(sp) - -000004de <.LVL150>: - 4de: 00032783 lw a5,0(t1) - -000004e2 <.LVL151>: - 4e2: 00f6f463 bgeu a3,a5,4ea <.L103> - 4e6: 00d32023 sw a3,0(t1) - -000004ea <.L103>: - 4ea: 47a2 lw a5,8(sp) - 4ec: 0791 add a5,a5,4 - 4ee: 94be add s1,s1,a5 - -000004f0 <.LVL153>: - 4f0: 87a2 mv a5,s0 - 4f2: b72d j 41c <.L93> - -000004f4 <.L98>: - 4f4: 0037d693 srl a3,a5,0x3 - 4f8: 0ff6f693 zext.b a3,a3 - 4fc: f8568ce3 beq a3,t0,494 <.L95> - 500: 0047e793 or a5,a5,4 - 504: b771 j 490 <.L111> - -00000506 <.L106>: - 506: 87a2 mv a5,s0 - -00000508 <.L94>: - 508: 843e mv s0,a5 - 50a: b7c5 j 4ea <.L103> - -0000050c : - 50c: 491c lw a5,16(a0) - 50e: fd410113 add sp,sp,-44 - 512: d222 sw s0,36(sp) - 514: 838d srl a5,a5,0x3 - 516: 0ff7f793 zext.b a5,a5 - 51a: d026 sw s1,32(sp) - 51c: 842a mv s0,a0 - 51e: 84ae mv s1,a1 - 520: 85aa mv a1,a0 - -00000522 <.LVL158>: - 522: 853e mv a0,a5 - -00000524 <.LVL159>: - 524: c03e sw a5,0(sp) - -00000526 <.LVL160>: - 526: d406 sw ra,40(sp) - 528: c432 sw a2,8(sp) - 52a: 00000097 auipc ra,0x0 - 52e: 000080e7 jalr ra # 52a <.LVL160+0x4> - -00000532 <.LVL161>: - 532: 82aa mv t0,a0 - -00000534 <.LVL162>: - 534: 87a6 mv a5,s1 - 536: 4701 li a4,0 - -00000538 <.L113>: - 538: 4394 lw a3,0(a5) - 53a: c236 sw a3,4(sp) - -0000053c <.LBE66>: - 53c: e299 bnez a3,542 <.L122> - 53e: 4781 li a5,0 - -00000540 <.LVL165>: - 540: a8a9 j 59a <.L112> - -00000542 <.L122>: - 542: 43d0 lw a2,4(a5) - 544: ce4d beqz a2,5fe <.L123> - 546: 4814 lw a3,16(s0) - 548: 833a mv t1,a4 - 54a: 8a91 and a3,a3,4 - 54c: ca8d beqz a3,57e <.L115> - -0000054e <.LBB69>: - 54e: 00478313 add t1,a5,4 - 552: 40c30333 sub t1,t1,a2 - -00000556 <.LBE69>: - 556: 02670463 beq a4,t1,57e <.L115> - 55a: 851a mv a0,t1 - 55c: c83e sw a5,16(sp) - -0000055e <.LVL169>: - 55e: c61a sw t1,12(sp) - 560: 00000097 auipc ra,0x0 - 564: 000080e7 jalr ra # 560 <.LVL169+0x2> - -00000568 <.LVL170>: - 568: c02a sw a0,0(sp) - -0000056a <.LVL171>: - 56a: 00014503 lbu a0,0(sp) - -0000056e <.LVL172>: - 56e: 85a2 mv a1,s0 - 570: 00000097 auipc ra,0x0 - 574: 000080e7 jalr ra # 570 <.LVL172+0x2> - -00000578 <.LVL173>: - 578: 47c2 lw a5,16(sp) - 57a: 4332 lw t1,12(sp) - 57c: 82aa mv t0,a0 - -0000057e <.L115>: - 57e: 4702 lw a4,0(sp) - 580: e705 bnez a4,5a8 <.L116> - -00000582 <.LBB71>: - 582: 4798 lw a4,8(a5) - 584: 47d4 lw a3,12(a5) - 586: cc3a sw a4,24(sp) - 588: ce36 sw a3,28(sp) - -0000058a <.L134>: - 58a: cb3d beqz a4,600 <.L118> - -0000058c <.LBE71>: - 58c: 46a2 lw a3,8(sp) - 58e: 4762 lw a4,24(sp) - 590: 40e68733 sub a4,a3,a4 - 594: 46f2 lw a3,28(sp) - 596: 06d77563 bgeu a4,a3,600 <.L118> - -0000059a <.L112>: - 59a: 50a2 lw ra,40(sp) - 59c: 5412 lw s0,36(sp) - -0000059e <.LVL178>: - 59e: 5482 lw s1,32(sp) - 5a0: 853e mv a0,a5 - 5a2: 02c10113 add sp,sp,44 - -000005a6 <.LVL179>: - 5a6: 8082 ret - -000005a8 <.L116>: - 5a8: 00014483 lbu s1,0(sp) - 5ac: 00878613 add a2,a5,8 - 5b0: 8596 mv a1,t0 - 5b2: 0834 add a3,sp,24 - 5b4: 8526 mv a0,s1 - 5b6: ca1a sw t1,20(sp) - 5b8: c83e sw a5,16(sp) - 5ba: c616 sw t0,12(sp) - 5bc: 00000097 auipc ra,0x0 - 5c0: 000080e7 jalr ra # 5bc <.L116+0x14> - -000005c4 <.LVL181>: - 5c4: 862a mv a2,a0 - -000005c6 <.LVL182>: - 5c6: 0874 add a3,sp,28 - 5c8: 4581 li a1,0 - 5ca: 00f4f513 and a0,s1,15 - -000005ce <.LVL183>: - 5ce: 00000097 auipc ra,0x0 - 5d2: 000080e7 jalr ra # 5ce <.LVL183> - -000005d6 <.LVL184>: - 5d6: 8526 mv a0,s1 - 5d8: 00000097 auipc ra,0x0 - 5dc: 000080e7 jalr ra # 5d8 <.LVL184+0x2> - -000005e0 <.LVL185>: - 5e0: 468d li a3,3 - 5e2: 42b2 lw t0,12(sp) - 5e4: 47c2 lw a5,16(sp) - 5e6: 4352 lw t1,20(sp) - 5e8: 577d li a4,-1 - 5ea: 00a6e763 bltu a3,a0,5f8 <.L119> - 5ee: 050e sll a0,a0,0x3 - -000005f0 <.LVL186>: - 5f0: 4705 li a4,1 - 5f2: 00a71733 sll a4,a4,a0 - 5f6: 177d add a4,a4,-1 - -000005f8 <.L119>: - 5f8: 46e2 lw a3,24(sp) - 5fa: 8f75 and a4,a4,a3 - -000005fc <.LVL188>: - 5fc: b779 j 58a <.L134> - -000005fe <.L123>: - 5fe: 833a mv t1,a4 - -00000600 <.L118>: - 600: 4712 lw a4,4(sp) - 602: 0711 add a4,a4,4 - 604: 97ba add a5,a5,a4 - -00000606 <.LVL191>: - 606: 871a mv a4,t1 - 608: bf05 j 538 <.L113> - -0000060a : - 60a: 00450713 add a4,a0,4 - 60e: 4148 lw a0,4(a0) - -00000610 <.LBE76>: - 610: 40a70533 sub a0,a4,a0 - 614: 00000317 auipc t1,0x0 - 618: 00030067 jr t1 # 614 <.LBE76+0x4> - -0000061c : - 61c: 1111 add sp,sp,-28 - 61e: c22a sw a0,4(sp) - 620: 852e mv a0,a1 - -00000622 <.LVL196>: - 622: cc06 sw ra,24(sp) - 624: ca22 sw s0,20(sp) - 626: c826 sw s1,16(sp) - 628: 842e mv s0,a1 - 62a: 84b2 mv s1,a2 - 62c: 00000097 auipc ra,0x0 - 630: 000080e7 jalr ra # 62c <.LVL196+0xa> - -00000634 <.LVL197>: - 634: 4592 lw a1,4(sp) - 636: 0ff57793 zext.b a5,a0 - 63a: 853e mv a0,a5 - -0000063c <.LVL198>: - 63c: c03e sw a5,0(sp) - 63e: 00000097 auipc ra,0x0 - 642: 000080e7 jalr ra # 63e <.LVL198+0x2> - -00000646 <.LVL199>: - 646: 85aa mv a1,a0 - 648: 4502 lw a0,0(sp) - 64a: 00840613 add a2,s0,8 - 64e: 0034 add a3,sp,8 - 650: 00000097 auipc ra,0x0 - 654: 000080e7 jalr ra # 650 <.LVL199+0xa> - -00000658 <.LVL200>: - 658: 8526 mv a0,s1 - 65a: 00000097 auipc ra,0x0 - 65e: 000080e7 jalr ra # 65a <.LVL200+0x2> - -00000662 <.LVL201>: - 662: 4592 lw a1,4(sp) - 664: 0ff57413 zext.b s0,a0 - -00000668 <.LVL202>: - 668: 8522 mv a0,s0 - -0000066a <.LVL203>: - 66a: 00000097 auipc ra,0x0 - 66e: 000080e7 jalr ra # 66a <.LVL203> - -00000672 <.LVL204>: - 672: 85aa mv a1,a0 - 674: 0074 add a3,sp,12 - 676: 00848613 add a2,s1,8 - 67a: 8522 mv a0,s0 - 67c: 00000097 auipc ra,0x0 - 680: 000080e7 jalr ra # 67c <.LVL204+0xa> - -00000684 <.LVL205>: - 684: 4522 lw a0,8(sp) - 686: 47b2 lw a5,12(sp) - 688: 00a7eb63 bltu a5,a0,69e <.L138> - 68c: 00f53533 sltu a0,a0,a5 - 690: 40a00533 neg a0,a0 - -00000694 <.L136>: - 694: 40e2 lw ra,24(sp) - 696: 4452 lw s0,20(sp) - 698: 44c2 lw s1,16(sp) - -0000069a <.LVL206>: - 69a: 0171 add sp,sp,28 - -0000069c <.LVL207>: - 69c: 8082 ret - -0000069e <.L138>: - 69e: 4505 li a0,1 - 6a0: bfd5 j 694 <.L136> - -000006a2 : - 6a2: 1131 add sp,sp,-20 - 6a4: c622 sw s0,12(sp) - 6a6: 05a1 add a1,a1,8 - -000006a8 <.LVL210>: - 6a8: 8432 mv s0,a2 - 6aa: 850a mv a0,sp - -000006ac <.LVL211>: - 6ac: 4611 li a2,4 - -000006ae <.LVL212>: - 6ae: c806 sw ra,16(sp) - 6b0: 00000097 auipc ra,0x0 - 6b4: 000080e7 jalr ra # 6b0 <.LVL212+0x2> - -000006b8 <.LVL213>: - 6b8: 4611 li a2,4 - 6ba: 00840593 add a1,s0,8 - 6be: 0048 add a0,sp,4 - 6c0: 00000097 auipc ra,0x0 - 6c4: 000080e7 jalr ra # 6c0 <.LVL213+0x8> - -000006c8 <.LVL214>: - 6c8: 4782 lw a5,0(sp) - 6ca: 4712 lw a4,4(sp) - 6cc: 4505 li a0,1 - 6ce: 00f76663 bltu a4,a5,6da <.L140> - 6d2: 00e7b7b3 sltu a5,a5,a4 - 6d6: 40f00533 neg a0,a5 - -000006da <.L140>: - 6da: 40c2 lw ra,16(sp) - 6dc: 4432 lw s0,12(sp) - -000006de <.LVL215>: - 6de: 0151 add sp,sp,20 - 6e0: 8082 ret - -000006e2 : - 6e2: 4918 lw a4,16(a0) - 6e4: fd810113 add sp,sp,-40 - 6e8: c22a sw a0,4(sp) - 6ea: 830d srl a4,a4,0x3 - 6ec: 0ff77793 zext.b a5,a4 - 6f0: ca2e sw a1,20(sp) - 6f2: 85aa mv a1,a0 - -000006f4 <.LVL217>: - 6f4: 853e mv a0,a5 - -000006f6 <.LVL218>: - 6f6: ce26 sw s1,28(sp) - 6f8: d206 sw ra,36(sp) - 6fa: d022 sw s0,32(sp) - 6fc: 84b2 mv s1,a2 - 6fe: c03e sw a5,0(sp) - -00000700 <.LVL219>: - 700: 00000097 auipc ra,0x0 - 704: 000080e7 jalr ra # 700 <.LVL219> - -00000708 <.LVL220>: - 708: c62a sw a0,12(sp) - -0000070a <.LVL221>: - 70a: 4701 li a4,0 - -0000070c <.L146>: - 70c: 409c lw a5,0(s1) - 70e: c83e sw a5,16(sp) - -00000710 <.LBE89>: - 710: e799 bnez a5,71e <.L155> - 712: 5092 lw ra,36(sp) - 714: 5402 lw s0,32(sp) - 716: 44f2 lw s1,28(sp) - -00000718 <.LVL224>: - 718: 02810113 add sp,sp,40 - -0000071c <.LVL225>: - 71c: 8082 ret - -0000071e <.L155>: - 71e: 40d0 lw a2,4(s1) - 720: 843a mv s0,a4 - 722: ce31 beqz a2,77e <.L147> - -00000724 <.LVL227>: - 724: 4792 lw a5,4(sp) - 726: 4b94 lw a3,16(a5) - 728: 8a91 and a3,a3,4 - 72a: c685 beqz a3,752 <.L148> - -0000072c <.LBB92>: - 72c: 00448413 add s0,s1,4 - -00000730 <.LVL229>: - 730: 8c11 sub s0,s0,a2 - -00000732 <.LBE92>: - 732: 02870063 beq a4,s0,752 <.L148> - -00000736 <.LVL231>: - 736: 8522 mv a0,s0 - 738: 00000097 auipc ra,0x0 - 73c: 000080e7 jalr ra # 738 <.LVL231+0x2> - -00000740 <.LVL232>: - 740: c02a sw a0,0(sp) - -00000742 <.LVL233>: - 742: 4592 lw a1,4(sp) - 744: 00014503 lbu a0,0(sp) - -00000748 <.LVL234>: - 748: 00000097 auipc ra,0x0 - 74c: 000080e7 jalr ra # 748 <.LVL234> - -00000750 <.LVL235>: - 750: c62a sw a0,12(sp) - -00000752 <.L148>: - 752: 4782 lw a5,0(sp) - -00000754 <.LBB94>: - 754: 00848593 add a1,s1,8 - -00000758 <.LBE94>: - 758: eb8d bnez a5,78a <.L149> - -0000075a <.LBB95>: - 75a: 4611 li a2,4 - 75c: 0828 add a0,sp,24 - 75e: 00000097 auipc ra,0x0 - 762: 000080e7 jalr ra # 75e <.LBB95+0x4> - -00000766 <.LVL237>: - 766: 4762 lw a4,24(sp) - -00000768 <.L164>: - 768: cb19 beqz a4,77e <.L147> - -0000076a <.LBE96>: - 76a: 47d2 lw a5,20(sp) - 76c: 4398 lw a4,0(a5) - -0000076e <.LBB97>: - 76e: cb01 beqz a4,77e <.L147> - 770: 4354 lw a3,4(a4) - 772: 00168613 add a2,a3,1 # 1 - 776: 068a sll a3,a3,0x2 - 778: c350 sw a2,4(a4) - 77a: 9736 add a4,a4,a3 - 77c: c704 sw s1,8(a4) - -0000077e <.L147>: - 77e: 47c2 lw a5,16(sp) - 780: 00478713 add a4,a5,4 - 784: 94ba add s1,s1,a4 - -00000786 <.LVL240>: - 786: 8722 mv a4,s0 - 788: b751 j 70c <.L146> - -0000078a <.L149>: - 78a: 00014703 lbu a4,0(sp) - 78e: 862e mv a2,a1 - 790: 45b2 lw a1,12(sp) - 792: 0834 add a3,sp,24 - 794: 853a mv a0,a4 - 796: c43a sw a4,8(sp) - 798: 00000097 auipc ra,0x0 - 79c: 000080e7 jalr ra # 798 <.L149+0xe> - -000007a0 <.LVL242>: - 7a0: 4522 lw a0,8(sp) - 7a2: 00000097 auipc ra,0x0 - 7a6: 000080e7 jalr ra # 7a2 <.LVL242+0x2> - -000007aa <.LVL243>: - 7aa: 468d li a3,3 - 7ac: 577d li a4,-1 - 7ae: 00a6e763 bltu a3,a0,7bc <.L152> - 7b2: 050e sll a0,a0,0x3 - -000007b4 <.LVL244>: - 7b4: 4705 li a4,1 - 7b6: 00a71733 sll a4,a4,a0 - 7ba: 177d add a4,a4,-1 - -000007bc <.L152>: - 7bc: 46e2 lw a3,24(sp) - 7be: 8f75 and a4,a4,a3 - -000007c0 <.LVL246>: - 7c0: b765 j 768 <.L164> - -000007c2 : - 7c2: 491c lw a5,16(a0) - 7c4: 7139 add sp,sp,-64 - 7c6: dc22 sw s0,56(sp) - 7c8: 0017f713 and a4,a5,1 - 7cc: de06 sw ra,60(sp) - 7ce: da26 sw s1,52(sp) - 7d0: c22e sw a1,4(sp) - 7d2: c43a sw a4,8(sp) - 7d4: 842a mv s0,a0 - 7d6: c715 beqz a4,802 <.L166> - -000007d8 <.L203>: - 7d8: 445c lw a5,12(s0) - -000007da <.LBE130>: - 7da: 4804 lw s1,16(s0) - -000007dc <.LBB135>: - 7dc: c03e sw a5,0(sp) - -000007de <.LBE135>: - 7de: 0014f793 and a5,s1,1 - 7e2: 2c079663 bnez a5,aae <.L167> - 7e6: 8889 and s1,s1,2 - 7e8: 44049463 bnez s1,c30 <.L220> - 7ec: 8522 mv a0,s0 - 7ee: 5462 lw s0,56(sp) - -000007f0 <.LVL249>: - 7f0: 4612 lw a2,4(sp) - 7f2: 4582 lw a1,0(sp) - 7f4: 50f2 lw ra,60(sp) - 7f6: 54d2 lw s1,52(sp) - 7f8: 6121 add sp,sp,64 - 7fa: 00000317 auipc t1,0x0 - 7fe: 00030067 jr t1 # 7fa <.LVL249+0xa> - -00000802 <.L166>: - 802: 00b7d693 srl a3,a5,0xb - -00000806 <.LVL251>: - 806: eead bnez a3,880 <.L169> - 808: 8b89 and a5,a5,2 - -0000080a <.LBB138>: - 80a: 4544 lw s1,12(a0) - -0000080c <.LBE138>: - 80c: ebb1 bnez a5,860 <.L170> - 80e: 85a6 mv a1,s1 - -00000810 <.LVL252>: - 810: 00000097 auipc ra,0x0 - 814: 000080e7 jalr ra # 810 <.LVL252> - -00000818 <.LVL253>: - 818: 57fd li a5,-1 - 81a: 86aa mv a3,a0 - -0000081c <.LVL254>: - 81c: 04f51463 bne a0,a5,864 <.L175> - -00000820 <.LBB141>: - 820: a819 j 836 <.L176> - -00000822 <.L174>: - 822: 8522 mv a0,s0 - 824: c036 sw a3,0(sp) - 826: 00000097 auipc ra,0x0 - 82a: 000080e7 jalr ra # 826 <.L174+0x4> - -0000082e <.LVL256>: - 82e: 57fd li a5,-1 - 830: 4682 lw a3,0(sp) - 832: 02f51563 bne a0,a5,85c <.L172> - -00000836 <.L176>: - 836: 7f800793 li a5,2040 - 83a: c81c sw a5,16(s0) - 83c: 000007b7 lui a5,0x0 - 840: 00078793 mv a5,a5 - 844: c45c sw a5,12(s0) - -00000846 <.L202>: - 846: 401c lw a5,0(s0) - 848: 4712 lw a4,4(sp) - 84a: f8f777e3 bgeu a4,a5,7d8 <.L203> - -0000084e <.L210>: - 84e: 4481 li s1,0 - -00000850 <.L165>: - 850: 50f2 lw ra,60(sp) - 852: 5462 lw s0,56(sp) - 854: 8526 mv a0,s1 - 856: 54d2 lw s1,52(sp) - 858: 6121 add sp,sp,64 - 85a: 8082 ret - -0000085c <.L172>: - 85c: 96aa add a3,a3,a0 - -0000085e <.LBE140>: - 85e: 0491 add s1,s1,4 - -00000860 <.L170>: - 860: 408c lw a1,0(s1) - 862: f1e1 bnez a1,822 <.L174> - -00000864 <.L175>: - 864: 481c lw a5,16(s0) - 866: 00b69713 sll a4,a3,0xb - 86a: 7ff7f793 and a5,a5,2047 - 86e: 8fd9 or a5,a5,a4 - 870: c81c sw a5,16(s0) - -00000872 <.LVL264>: - 872: 00200737 lui a4,0x200 - 876: 06e6e463 bltu a3,a4,8de <.L177> - 87a: 7ff7f793 and a5,a5,2047 - 87e: c81c sw a5,16(s0) - -00000880 <.L169>: - 880: 00268493 add s1,a3,2 - 884: 00249793 sll a5,s1,0x2 - 888: 853e mv a0,a5 - 88a: c636 sw a3,12(sp) - 88c: c03e sw a5,0(sp) - -0000088e <.LVL266>: - 88e: 00000097 auipc ra,0x0 - 892: 000080e7 jalr ra # 88e <.LVL266> - -00000896 <.LVL267>: - 896: d62a sw a0,44(sp) - 898: 84aa mv s1,a0 - 89a: d555 beqz a0,846 <.L202> - 89c: 00052223 sw zero,4(a0) - 8a0: 4502 lw a0,0(sp) - 8a2: 00000097 auipc ra,0x0 - 8a6: 000080e7 jalr ra # 8a2 <.LVL267+0xc> - -000008aa <.LVL268>: - 8aa: d82a sw a0,48(sp) - 8ac: 46b2 lw a3,12(sp) - 8ae: 872a mv a4,a0 - 8b0: c119 beqz a0,8b6 <.L180> - 8b2: 00052223 sw zero,4(a0) - -000008b6 <.L180>: - 8b6: 481c lw a5,16(s0) - -000008b8 <.LBB148>: - 8b8: 00c42303 lw t1,12(s0) - -000008bc <.LBE148>: - 8bc: 0027f613 and a2,a5,2 - 8c0: e221 bnez a2,900 <.L181> - 8c2: 861a mv a2,t1 - 8c4: 106c add a1,sp,44 - 8c6: 8522 mv a0,s0 - 8c8: c83a sw a4,16(sp) - 8ca: c63e sw a5,12(sp) - 8cc: c036 sw a3,0(sp) - 8ce: 00000097 auipc ra,0x0 - 8d2: 000080e7 jalr ra # 8ce <.LBE148+0x12> - -000008d6 <.LVL270>: - 8d6: 4742 lw a4,16(sp) - 8d8: 47b2 lw a5,12(sp) - 8da: 4682 lw a3,0(sp) - 8dc: a02d j 906 <.L184> - -000008de <.L177>: - 8de: d6a5 beqz a3,846 <.L202> - 8e0: b745 j 880 <.L169> - -000008e2 <.L183>: - 8e2: 106c add a1,sp,44 - 8e4: 8522 mv a0,s0 - 8e6: ca3a sw a4,20(sp) - 8e8: c81a sw t1,16(sp) - 8ea: c63e sw a5,12(sp) - 8ec: c036 sw a3,0(sp) - 8ee: 00000097 auipc ra,0x0 - 8f2: 000080e7 jalr ra # 8ee <.L183+0xc> - -000008f6 <.LVL273>: - 8f6: 4342 lw t1,16(sp) - 8f8: 4752 lw a4,20(sp) - 8fa: 47b2 lw a5,12(sp) - 8fc: 4682 lw a3,0(sp) - 8fe: 0311 add t1,t1,4 - -00000900 <.L181>: - 900: 00032603 lw a2,0(t1) - 904: fe79 bnez a2,8e2 <.L183> - -00000906 <.L184>: - 906: 40d0 lw a2,4(s1) - 908: 00d60663 beq a2,a3,914 <.L185> - -0000090c <.L195>: - 90c: 00000097 auipc ra,0x0 - 910: 000080e7 jalr ra # 90c <.L195> - -00000914 <.L185>: - 914: 0047f613 and a2,a5,4 - 918: e21d bnez a2,93e <.L223> - 91a: 7f87f793 and a5,a5,2040 - 91e: e78d bnez a5,948 <.L224> - 920: 00000637 lui a2,0x0 - 924: 00060793 mv a5,a2 - -00000928 <.L252>: - 928: c03e sw a5,0(sp) - -0000092a <.LVL278>: - 92a: 14071663 bnez a4,a76 <.L225> - 92e: 4582 lw a1,0(sp) - 930: 8626 mv a2,s1 - 932: 8522 mv a0,s0 - 934: 00000097 auipc ra,0x0 - 938: 000080e7 jalr ra # 934 <.LVL278+0xa> - -0000093c <.LVL279>: - 93c: a22d j a66 <.L201> - -0000093e <.L223>: - 93e: 00000637 lui a2,0x0 - 942: 00060793 mv a5,a2 - 946: b7cd j 928 <.L252> - -00000948 <.L224>: - 948: 00000637 lui a2,0x0 - 94c: 00060793 mv a5,a2 - 950: bfe1 j 928 <.L252> - -00000952 <.L190>: - 952: 47c2 lw a5,16(sp) - 954: 40f30633 sub a2,t1,a5 - 958: 963a add a2,a2,a4 - 95a: 00862303 lw t1,8(a2) # 8 <.L2+0x4> - -0000095e <.LVL282>: - 95e: 00062423 sw zero,8(a2) - -00000962 <.L187>: - 962: 47b2 lw a5,12(sp) - 964: 02f30663 beq t1,a5,990 <.L189> - 968: 005485b3 add a1,s1,t0 - 96c: 00032603 lw a2,0(t1) - 970: 418c lw a1,0(a1) - 972: 4782 lw a5,0(sp) - 974: d21e sw t2,36(sp) - 976: d03a sw a4,32(sp) - 978: ce36 sw a3,28(sp) - 97a: cc16 sw t0,24(sp) - 97c: ca1a sw t1,20(sp) - 97e: 8522 mv a0,s0 - 980: 9782 jalr a5 - -00000982 <.LVL284>: - 982: 4352 lw t1,20(sp) - 984: 42e2 lw t0,24(sp) - 986: 46f2 lw a3,28(sp) - 988: 5702 lw a4,32(sp) - 98a: 5392 lw t2,36(sp) - 98c: fc0543e3 bltz a0,952 <.L190> - -00000990 <.L189>: - 990: 00570633 add a2,a4,t0 - 994: 00662023 sw t1,0(a2) - -00000998 <.LBE155>: - 998: 0385 add t2,t2,1 - -0000099a <.LBB156>: - 99a: 00548333 add t1,s1,t0 - -0000099e <.LBE156>: - 99e: 0291 add t0,t0,4 - 9a0: fc7691e3 bne a3,t2,962 <.L187> - 9a4: 4601 li a2,0 - 9a6: 4501 li a0,0 - 9a8: 45a1 li a1,8 - -000009aa <.L194>: - 9aa: 00b48333 add t1,s1,a1 - 9ae: 00032283 lw t0,0(t1) - 9b2: 00b70333 add t1,a4,a1 - 9b6: 00032303 lw t1,0(t1) - 9ba: 0c030b63 beqz t1,a90 <.L192> - -000009be <.LVL288>: - 9be: 47a2 lw a5,8(sp) - 9c0: 00279313 sll t1,a5,0x2 - 9c4: 9326 add t1,t1,s1 - 9c6: 0785 add a5,a5,1 # 1 - -000009c8 <.LVL289>: - 9c8: 00532423 sw t0,8(t1) - 9cc: c43e sw a5,8(sp) - -000009ce <.L193>: - 9ce: 0505 add a0,a0,1 - 9d0: 0591 add a1,a1,4 - 9d2: fca69ce3 bne a3,a0,9aa <.L194> - 9d6: 47a2 lw a5,8(sp) - 9d8: c350 sw a2,4(a4) - 9da: c0dc sw a5,4(s1) - -000009dc <.LBE153>: - 9dc: 963e add a2,a2,a5 - 9de: f2c697e3 bne a3,a2,90c <.L195> - 9e2: 4582 lw a1,0(sp) - 9e4: 863a mv a2,a4 - 9e6: 8522 mv a0,s0 - 9e8: c43a sw a4,8(sp) - 9ea: 00000097 auipc ra,0x0 - 9ee: 000080e7 jalr ra # 9ea <.LBE153+0xe> - -000009f2 <.LBB161>: - 9f2: 4722 lw a4,8(sp) - 9f4: 00472303 lw t1,4(a4) # 200004 <.LLST178+0x1fe607> - -000009f8 <.LVL294>: - 9f8: 06030263 beqz t1,a5c <.L196> - 9fc: 0044a283 lw t0,4(s1) - -00000a00 <.L200>: - a00: 137d add t1,t1,-1 - a02: 00231593 sll a1,t1,0x2 - a06: 00b706b3 add a3,a4,a1 - a0a: 4690 lw a2,8(a3) - -00000a0c <.LVL297>: - a0c: 00128693 add a3,t0,1 - a10: 068a sll a3,a3,0x2 - a12: 00458793 add a5,a1,4 - a16: 96a6 add a3,a3,s1 - a18: c43e sw a5,8(sp) - -00000a1a <.L197>: - a1a: 02028663 beqz t0,a46 <.L198> - a1e: 428c lw a1,0(a3) - a20: 4782 lw a5,0(sp) - a22: fff28393 add t2,t0,-1 - a26: d01a sw t1,32(sp) - a28: ce3a sw a4,28(sp) - a2a: cc16 sw t0,24(sp) - a2c: ca1e sw t2,20(sp) - a2e: c832 sw a2,16(sp) - a30: c636 sw a3,12(sp) - a32: 8522 mv a0,s0 - a34: 9782 jalr a5 - -00000a36 <.LVL299>: - a36: 46b2 lw a3,12(sp) - a38: 4642 lw a2,16(sp) - a3a: 43d2 lw t2,20(sp) - a3c: 42e2 lw t0,24(sp) - a3e: 4772 lw a4,28(sp) - a40: 5302 lw t1,32(sp) - a42: 04a04e63 bgtz a0,a9e <.L199> - -00000a46 <.L198>: - a46: 005306b3 add a3,t1,t0 - a4a: 068a sll a3,a3,0x2 - a4c: 96a6 add a3,a3,s1 - a4e: c690 sw a2,8(a3) - a50: fa0318e3 bnez t1,a00 <.L200> - a54: 40d4 lw a3,4(s1) - a56: 4350 lw a2,4(a4) - a58: 96b2 add a3,a3,a2 - a5a: c0d4 sw a3,4(s1) - -00000a5c <.L196>: - a5c: 853a mv a0,a4 - a5e: 00000097 auipc ra,0x0 - a62: 000080e7 jalr ra # a5e <.L196+0x2> - -00000a66 <.L201>: - a66: 4458 lw a4,12(s0) - a68: c444 sw s1,12(s0) - a6a: c098 sw a4,0(s1) - a6c: 481c lw a5,16(s0) - a6e: 0017e793 or a5,a5,1 - a72: c81c sw a5,16(s0) - a74: bbc9 j 846 <.L202> - -00000a76 <.L225>: - a76: 00000637 lui a2,0x0 - a7a: 00060793 mv a5,a2 - -00000a7e <.LVL304>: - a7e: c63e sw a5,12(sp) - -00000a80 <.LBB157>: - a80: 00848793 add a5,s1,8 - -00000a84 <.LBE157>: - a84: 4381 li t2,0 - -00000a86 <.LBE164>: - a86: 42a1 li t0,8 - -00000a88 <.LBB165>: - a88: 00060313 mv t1,a2 - -00000a8c <.LBB158>: - a8c: c83e sw a5,16(sp) - a8e: bdd1 j 962 <.L187> - -00000a90 <.L192>: - a90: 00261313 sll t1,a2,0x2 - a94: 933a add t1,t1,a4 - a96: 00532423 sw t0,8(t1) - a9a: 0605 add a2,a2,1 # 1 - -00000a9c <.LVL306>: - a9c: bf0d j 9ce <.L193> - -00000a9e <.L199>: - a9e: 47a2 lw a5,8(sp) - aa0: 4288 lw a0,0(a3) - aa2: 829e mv t0,t2 - aa4: 00f685b3 add a1,a3,a5 - aa8: c188 sw a0,0(a1) - -00000aaa <.LVL308>: - aaa: 16f1 add a3,a3,-4 - aac: b7bd j a1a <.L197> - -00000aae <.L167>: - aae: 0044f313 and t1,s1,4 - ab2: 08030563 beqz t1,b3c <.L205> - -00000ab6 <.LBB171>: - ab6: 4782 lw a5,0(sp) - ab8: 4381 li t2,0 - aba: 0047a283 lw t0,4(a5) - -00000abe <.L206>: - abe: d853f8e3 bgeu t2,t0,84e <.L210> - -00000ac2 <.LBB132>: - ac2: 00538333 add t1,t2,t0 - ac6: 4702 lw a4,0(sp) - ac8: 00135313 srl t1,t1,0x1 - -00000acc <.LVL312>: - acc: 00231793 sll a5,t1,0x2 - ad0: 97ba add a5,a5,a4 - ad2: 4784 lw s1,8(a5) - -00000ad4 <.LVL313>: - ad4: c81e sw t2,16(sp) - ad6: c61a sw t1,12(sp) - ad8: 8526 mv a0,s1 - ada: ca16 sw t0,20(sp) - adc: 00000097 auipc ra,0x0 - ae0: 000080e7 jalr ra # adc <.LVL313+0x8> - -00000ae4 <.LVL314>: - ae4: 0ff57793 zext.b a5,a0 - ae8: 853e mv a0,a5 - -00000aea <.LVL315>: - aea: 85a2 mv a1,s0 - aec: c43e sw a5,8(sp) - aee: 00000097 auipc ra,0x0 - af2: 000080e7 jalr ra # aee <.LVL315+0x4> - -00000af6 <.LVL316>: - af6: 85aa mv a1,a0 - af8: 4522 lw a0,8(sp) - afa: 1034 add a3,sp,40 - afc: 00848613 add a2,s1,8 - b00: 00000097 auipc ra,0x0 - b04: 000080e7 jalr ra # b00 <.LVL316+0xa> - -00000b08 <.LVL317>: - b08: 47a2 lw a5,8(sp) - b0a: 862a mv a2,a0 - -00000b0c <.LVL318>: - b0c: 1074 add a3,sp,44 - b0e: 00f7f513 and a0,a5,15 - -00000b12 <.LVL319>: - b12: 4581 li a1,0 - b14: 00000097 auipc ra,0x0 - b18: 000080e7 jalr ra # b14 <.LVL319+0x2> - -00000b1c <.LVL320>: - b1c: 56a2 lw a3,40(sp) - b1e: 4792 lw a5,4(sp) - b20: 4332 lw t1,12(sp) - b22: 43c2 lw t2,16(sp) - b24: 00d7ea63 bltu a5,a3,b38 <.L207> - b28: 5632 lw a2,44(sp) - b2a: 96b2 add a3,a3,a2 - b2c: d2d7e2e3 bltu a5,a3,850 <.L165> - b30: 42d2 lw t0,20(sp) - b32: 00130393 add t2,t1,1 - -00000b36 <.LVL321>: - b36: 8316 mv t1,t0 - -00000b38 <.L207>: - b38: 829a mv t0,t1 - b3a: b751 j abe <.L206> - -00000b3c <.L205>: - b3c: 7f84f693 and a3,s1,2040 - b40: eeb1 bnez a3,b9c <.L211> - -00000b42 <.LBB172>: - b42: 4782 lw a5,0(sp) - b44: 43d8 lw a4,4(a5) - -00000b46 <.L212>: - b46: d0e6f4e3 bgeu a3,a4,84e <.L210> - -00000b4a <.LBB174>: - b4a: 00e68433 add s0,a3,a4 - b4e: c63a sw a4,12(sp) - b50: 4702 lw a4,0(sp) - -00000b52 <.LVL326>: - b52: 8005 srl s0,s0,0x1 - -00000b54 <.LVL327>: - b54: 00241793 sll a5,s0,0x2 - b58: 97ba add a5,a5,a4 - b5a: 4784 lw s1,8(a5) - -00000b5c <.LVL328>: - b5c: 4611 li a2,4 - b5e: 1028 add a0,sp,40 - b60: 00848593 add a1,s1,8 - b64: c436 sw a3,8(sp) - b66: 00000097 auipc ra,0x0 - b6a: 000080e7 jalr ra # b66 <.LVL328+0xa> - -00000b6e <.LVL329>: - b6e: 4611 li a2,4 - b70: 00c48593 add a1,s1,12 - b74: 1068 add a0,sp,44 - b76: 00000097 auipc ra,0x0 - b7a: 000080e7 jalr ra # b76 <.LVL329+0x8> - -00000b7e <.LVL330>: - b7e: 5622 lw a2,40(sp) - b80: 4792 lw a5,4(sp) - b82: 46a2 lw a3,8(sp) - b84: 00c7ea63 bltu a5,a2,b98 <.L213> - b88: 56b2 lw a3,44(sp) - b8a: 9636 add a2,a2,a3 - b8c: ccc7e2e3 bltu a5,a2,850 <.L165> - b90: 4732 lw a4,12(sp) - b92: 00140693 add a3,s0,1 - -00000b96 <.LVL331>: - b96: 843a mv s0,a4 - -00000b98 <.L213>: - b98: 8722 mv a4,s0 - b9a: b775 j b46 <.L212> - -00000b9c <.L211>: - b9c: 808d srl s1,s1,0x3 - b9e: 0ff4f793 zext.b a5,s1 - ba2: 85a2 mv a1,s0 - ba4: 853e mv a0,a5 - ba6: c81a sw t1,16(sp) - -00000ba8 <.LBB179>: - ba8: c43e sw a5,8(sp) - -00000baa <.LVL335>: - baa: 00000097 auipc ra,0x0 - bae: 000080e7 jalr ra # baa <.LVL335> - -00000bb2 <.LVL336>: - bb2: 4782 lw a5,0(sp) - bb4: 4342 lw t1,16(sp) - bb6: c62a sw a0,12(sp) - -00000bb8 <.LVL337>: - bb8: 43c0 lw s0,4(a5) - -00000bba <.L216>: - bba: c8837ae3 bgeu t1,s0,84e <.L210> - -00000bbe <.LBB177>: - bbe: 008302b3 add t0,t1,s0 - bc2: 4702 lw a4,0(sp) - bc4: 0012d293 srl t0,t0,0x1 - -00000bc8 <.LVL339>: - bc8: 00229793 sll a5,t0,0x2 - bcc: 97ba add a5,a5,a4 - bce: 4784 lw s1,8(a5) - -00000bd0 <.LVL340>: - bd0: 45b2 lw a1,12(sp) - bd2: 4522 lw a0,8(sp) - bd4: 1034 add a3,sp,40 - bd6: 00848613 add a2,s1,8 - bda: ca1a sw t1,20(sp) - bdc: c816 sw t0,16(sp) - bde: 00000097 auipc ra,0x0 - be2: 000080e7 jalr ra # bde <.LVL340+0xe> - -00000be6 <.LVL341>: - be6: 47a2 lw a5,8(sp) - be8: 862a mv a2,a0 - -00000bea <.LVL342>: - bea: 1074 add a3,sp,44 - bec: 00f7f513 and a0,a5,15 - -00000bf0 <.LVL343>: - bf0: 4581 li a1,0 - bf2: 00000097 auipc ra,0x0 - bf6: 000080e7 jalr ra # bf2 <.LVL343+0x2> - -00000bfa <.LVL344>: - bfa: 56a2 lw a3,40(sp) - bfc: 4792 lw a5,4(sp) - bfe: 42c2 lw t0,16(sp) - c00: 4352 lw t1,20(sp) - c02: 00d7e963 bltu a5,a3,c14 <.L217> - c06: 5632 lw a2,44(sp) - c08: 96b2 add a3,a3,a2 - c0a: c4d7e3e3 bltu a5,a3,850 <.L165> - c0e: 00128313 add t1,t0,1 - -00000c12 <.LVL345>: - c12: 82a2 mv t0,s0 - -00000c14 <.L217>: - c14: 8416 mv s0,t0 - c16: b755 j bba <.L216> - -00000c18 <.L222>: - c18: 4612 lw a2,4(sp) - c1a: 8522 mv a0,s0 - c1c: 00000097 auipc ra,0x0 - c20: 000080e7 jalr ra # c1c <.L222+0x4> - -00000c24 <.LVL348>: - c24: 84aa mv s1,a0 - -00000c26 <.LVL349>: - c26: c20515e3 bnez a0,850 <.L165> - -00000c2a <.LBE181>: - c2a: 4782 lw a5,0(sp) - c2c: 0791 add a5,a5,4 - c2e: c03e sw a5,0(sp) - -00000c30 <.L220>: - c30: 4782 lw a5,0(sp) - c32: 438c lw a1,0(a5) - c34: f1f5 bnez a1,c18 <.L222> - c36: b921 j 84e <.L210> - -00000c38 <__register_frame_info_bases>: - c38: c115 beqz a0,c5c <.L253> - c3a: 411c lw a5,0(a0) - c3c: c385 beqz a5,c5c <.L253> - -00000c3e <.LBB184>: - c3e: 57fd li a5,-1 - c40: c19c sw a5,0(a1) - c42: 7f800793 li a5,2040 - c46: c99c sw a5,16(a1) - c48: 000007b7 lui a5,0x0 - c4c: 0007a703 lw a4,0(a5) # 0 - c50: c1d0 sw a2,4(a1) - c52: c594 sw a3,8(a1) - c54: c5c8 sw a0,12(a1) - c56: c9d8 sw a4,20(a1) - c58: 00b7a023 sw a1,0(a5) - -00000c5c <.L253>: - c5c: 8082 ret - -00000c5e <__register_frame_info>: - c5e: 4681 li a3,0 - c60: 4601 li a2,0 - c62: 00000317 auipc t1,0x0 - c66: 00030067 jr t1 # c62 <__register_frame_info+0x4> - -00000c6a <__register_frame>: - c6a: 411c lw a5,0(a0) - c6c: c39d beqz a5,c92 <.L262> - c6e: 1151 add sp,sp,-12 - c70: c222 sw s0,4(sp) - c72: 842a mv s0,a0 - c74: 4561 li a0,24 - -00000c76 <.LVL357>: - c76: c406 sw ra,8(sp) - c78: 00000097 auipc ra,0x0 - c7c: 000080e7 jalr ra # c78 <.LVL357+0x2> - -00000c80 <.LVL358>: - c80: 85aa mv a1,a0 - -00000c82 <.LVL359>: - c82: 8522 mv a0,s0 - -00000c84 <.LVL360>: - c84: 4412 lw s0,4(sp) - -00000c86 <.LVL361>: - c86: 40a2 lw ra,8(sp) - c88: 0131 add sp,sp,12 - c8a: 00000317 auipc t1,0x0 - c8e: 00030067 jr t1 # c8a <.LVL361+0x4> - -00000c92 <.L262>: - c92: 8082 ret - -00000c94 <__register_frame_info_table_bases>: - c94: 57fd li a5,-1 - c96: c19c sw a5,0(a1) - c98: 7fa00793 li a5,2042 - c9c: c99c sw a5,16(a1) - c9e: 000007b7 lui a5,0x0 - ca2: 0007a703 lw a4,0(a5) # 0 - ca6: c1d0 sw a2,4(a1) - ca8: c594 sw a3,8(a1) - caa: c5c8 sw a0,12(a1) - cac: c9d8 sw a4,20(a1) - cae: 00b7a023 sw a1,0(a5) - cb2: 8082 ret - -00000cb4 <__register_frame_info_table>: - cb4: 4681 li a3,0 - cb6: 4601 li a2,0 - cb8: 00000317 auipc t1,0x0 - cbc: 00030067 jr t1 # cb8 <__register_frame_info_table+0x4> - -00000cc0 <__register_frame_table>: - cc0: 1151 add sp,sp,-12 - cc2: c222 sw s0,4(sp) - cc4: 842a mv s0,a0 - cc6: 4561 li a0,24 - -00000cc8 <.LVL367>: - cc8: c406 sw ra,8(sp) - cca: 00000097 auipc ra,0x0 - cce: 000080e7 jalr ra # cca <.LVL367+0x2> - -00000cd2 <.LVL368>: - cd2: 85aa mv a1,a0 - -00000cd4 <.LVL369>: - cd4: 8522 mv a0,s0 - -00000cd6 <.LVL370>: - cd6: 4412 lw s0,4(sp) - -00000cd8 <.LVL371>: - cd8: 40a2 lw ra,8(sp) - cda: 0131 add sp,sp,12 - cdc: 00000317 auipc t1,0x0 - ce0: 00030067 jr t1 # cdc <.LVL371+0x4> - -00000ce4 <__deregister_frame_info_bases>: - ce4: 1151 add sp,sp,-12 - ce6: c406 sw ra,8(sp) - ce8: c222 sw s0,4(sp) - cea: c93d beqz a0,d60 <.L282> - cec: 4118 lw a4,0(a0) - cee: 87aa mv a5,a0 - cf0: cb25 beqz a4,d60 <.L282> - cf2: 00000737 lui a4,0x0 - cf6: 00072403 lw s0,0(a4) # 0 - cfa: 00070713 mv a4,a4 - -00000cfe <.L273>: - cfe: ec01 bnez s0,d16 <.L275> - -00000d00 <.LBB188>: - d00: 00000737 lui a4,0x0 - -00000d04 <.LVL375>: - d04: 00072403 lw s0,0(a4) # 0 - d08: 00070713 mv a4,a4 - -00000d0c <.L276>: - d0c: e01d bnez s0,d32 <.L279> - -00000d0e <.L280>: - d0e: 00000097 auipc ra,0x0 - d12: 000080e7 jalr ra # d0e <.L280> - -00000d16 <.L275>: - d16: 4450 lw a2,12(s0) - d18: 4854 lw a3,20(s0) - d1a: 00f61863 bne a2,a5,d2a <.L274> - -00000d1e <.LVL379>: - d1e: c314 sw a3,0(a4) - -00000d20 <.L271>: - d20: 40a2 lw ra,8(sp) - d22: 8522 mv a0,s0 - d24: 4412 lw s0,4(sp) - d26: 0131 add sp,sp,12 - d28: 8082 ret - -00000d2a <.L274>: - d2a: 01440713 add a4,s0,20 - d2e: 8436 mv s0,a3 - d30: b7f9 j cfe <.L273> - -00000d32 <.L279>: - d32: 4814 lw a3,16(s0) - d34: 4448 lw a0,12(s0) - d36: 8a85 and a3,a3,1 - d38: ca99 beqz a3,d4e <.L277> - d3a: 4114 lw a3,0(a0) - d3c: 00d79e63 bne a5,a3,d58 <.L278> - -00000d40 <.LVL384>: - d40: 485c lw a5,20(s0) - -00000d42 <.LVL385>: - d42: c31c sw a5,0(a4) - -00000d44 <.LVL386>: - d44: 00000097 auipc ra,0x0 - d48: 000080e7 jalr ra # d44 <.LVL386> - -00000d4c <.LVL387>: - d4c: bfd1 j d20 <.L271> - -00000d4e <.L277>: - d4e: 00f51563 bne a0,a5,d58 <.L278> - -00000d52 <.LVL389>: - d52: 485c lw a5,20(s0) - -00000d54 <.LVL390>: - d54: c31c sw a5,0(a4) - -00000d56 <.LVL391>: - d56: b7e9 j d20 <.L271> - -00000d58 <.L278>: - d58: 01440713 add a4,s0,20 - d5c: 4840 lw s0,20(s0) - d5e: b77d j d0c <.L276> - -00000d60 <.L282>: - d60: 4401 li s0,0 - d62: bf7d j d20 <.L271> - -00000d64 <__deregister_frame_info>: - d64: 00000317 auipc t1,0x0 - d68: 00030067 jr t1 # d64 <__deregister_frame_info> - -00000d6c <__deregister_frame>: - d6c: 411c lw a5,0(a0) - d6e: cf89 beqz a5,d88 <.L285> - -00000d70 <.LBB192>: - d70: 1151 add sp,sp,-12 - d72: c406 sw ra,8(sp) - -00000d74 <.LBB195>: - d74: 00000097 auipc ra,0x0 - d78: 000080e7 jalr ra # d74 <.LBB195> - -00000d7c <.LBE195>: - d7c: 40a2 lw ra,8(sp) - d7e: 0131 add sp,sp,12 - d80: 00000317 auipc t1,0x0 - d84: 00030067 jr t1 # d80 <.LBE195+0x4> - -00000d88 <.L285>: - d88: 8082 ret - -00000d8a <_Unwind_Find_FDE>: - d8a: 1121 add sp,sp,-24 - d8c: 00000637 lui a2,0x0 - d90: c822 sw s0,16(sp) - d92: 00062403 lw s0,0(a2) # 0 - -00000d96 <.LVL402>: - d96: ca06 sw ra,20(sp) - d98: c626 sw s1,12(sp) - d9a: c02a sw a0,0(sp) - d9c: c22e sw a1,4(sp) - -00000d9e <.L291>: - d9e: cc09 beqz s0,db8 <.L294> - da0: 4018 lw a4,0(s0) - da2: 4782 lw a5,0(sp) - da4: 02e7e563 bltu a5,a4,dce <.L292> - da8: 85be mv a1,a5 - -00000daa <.LVL403>: - daa: 8522 mv a0,s0 - -00000dac <.LVL404>: - dac: 00000097 auipc ra,0x0 - db0: 000080e7 jalr ra # dac <.LVL404> - -00000db4 <.LVL405>: - db4: 84aa mv s1,a0 - -00000db6 <.LVL406>: - db6: e521 bnez a0,dfe <.L293> - -00000db8 <.L294>: - db8: 00000337 lui t1,0x0 - -00000dbc <.L299>: - dbc: 00032403 lw s0,0(t1) # 0 - dc0: e809 bnez s0,dd2 <.L300> - -00000dc2 <.L290>: - dc2: 40d2 lw ra,20(sp) - dc4: 8522 mv a0,s0 - dc6: 4442 lw s0,16(sp) - dc8: 44b2 lw s1,12(sp) - dca: 0161 add sp,sp,24 - -00000dcc <.LVL411>: - dcc: 8082 ret - -00000dce <.L292>: - dce: 4840 lw s0,20(s0) - dd0: b7f9 j d9e <.L291> - -00000dd2 <.L300>: - dd2: 4858 lw a4,20(s0) - dd4: 4582 lw a1,0(sp) - dd6: 8522 mv a0,s0 - dd8: 00e32023 sw a4,0(t1) - ddc: 00000097 auipc ra,0x0 - de0: 000080e7 jalr ra # ddc <.L300+0xa> - -00000de4 <.LVL415>: - de4: 00000637 lui a2,0x0 - de8: 00062683 lw a3,0(a2) # 0 - dec: 84aa mv s1,a0 - -00000dee <.LVL416>: - dee: 00060593 mv a1,a2 - df2: 00000337 lui t1,0x0 - -00000df6 <.L296>: - df6: eea1 bnez a3,e4e <.L298> - -00000df8 <.L297>: - df8: c854 sw a3,20(s0) - dfa: c180 sw s0,0(a1) - dfc: d0e1 beqz s1,dbc <.L299> - -00000dfe <.L293>: - dfe: 4054 lw a3,4(s0) - e00: 4792 lw a5,4(sp) - e02: c394 sw a3,0(a5) - e04: 4414 lw a3,8(s0) - e06: c3d4 sw a3,4(a5) - e08: 4814 lw a3,16(s0) - e0a: 0036d513 srl a0,a3,0x3 - e0e: 8a91 and a3,a3,4 - e10: 0ff57513 zext.b a0,a0 - -00000e14 <.LVL419>: - e14: c691 beqz a3,e20 <.L303> - e16: 8526 mv a0,s1 - -00000e18 <.LVL420>: - e18: 00000097 auipc ra,0x0 - e1c: 000080e7 jalr ra # e18 <.LVL420> - -00000e20 <.L303>: - e20: 0ff57793 zext.b a5,a0 - e24: 85a2 mv a1,s0 - e26: 853e mv a0,a5 - -00000e28 <.LVL422>: - e28: c03e sw a5,0(sp) - -00000e2a <.LVL423>: - e2a: 00000097 auipc ra,0x0 - e2e: 000080e7 jalr ra # e2a <.LVL423> - -00000e32 <.LVL424>: - e32: 85aa mv a1,a0 - e34: 4502 lw a0,0(sp) - e36: 0034 add a3,sp,8 - e38: 00848613 add a2,s1,8 - e3c: 00000097 auipc ra,0x0 - e40: 000080e7 jalr ra # e3c <.LVL424+0xa> - -00000e44 <.LVL425>: - e44: 47a2 lw a5,8(sp) - e46: 4712 lw a4,4(sp) - e48: 8426 mv s0,s1 - -00000e4a <.LBB198>: - e4a: c71c sw a5,8(a4) - -00000e4c <.LBE198>: - e4c: bf9d j dc2 <.L290> - -00000e4e <.L298>: - e4e: 0006a283 lw t0,0(a3) - e52: 4008 lw a0,0(s0) - e54: faa2e2e3 bltu t0,a0,df8 <.L297> - e58: 01468593 add a1,a3,20 - e5c: 4ad4 lw a3,20(a3) - e5e: bf61 j df6 <.L296> - -unwind-sjlj.o: file format elf32-littleriscv - - -unwind-c.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 : - 0: 4701 li a4,0 - 2: 4681 li a3,0 - -00000004 <.L2>: - 4: 00054783 lbu a5,0(a0) - 8: 0505 add a0,a0,1 - -0000000a <.LVL2>: - a: 07f7f613 and a2,a5,127 - e: 07e2 sll a5,a5,0x18 - -00000010 <.LVL3>: - 10: 00d61633 sll a2,a2,a3 - 14: 87e1 sra a5,a5,0x18 - 16: 8f51 or a4,a4,a2 - 18: 069d add a3,a3,7 - 1a: fe07c5e3 bltz a5,4 <.L2> - 1e: c198 sw a4,0(a1) - -00000020 <.LVL6>: - 20: 8082 ret - -00000022 : - 22: 1111 add sp,sp,-28 - -00000024 <.LBB11>: - 24: cc06 sw ra,24(sp) - 26: ca22 sw s0,20(sp) - 28: c826 sw s1,16(sp) - 2a: c02e sw a1,0(sp) - -0000002c <.LVL9>: - 2c: c236 sw a3,4(sp) - -0000002e <.LBB15>: - 2e: 0ff00793 li a5,255 - 32: 02f58263 beq a1,a5,56 <.L5> - 36: 0705f413 and s0,a1,112 - 3a: 03000793 li a5,48 - 3e: 84b2 mv s1,a2 - 40: 04f40f63 beq s0,a5,9e <.L6> - 44: 0087ed63 bltu a5,s0,5e <.L7> - 48: 02000793 li a5,32 - 4c: 04f40363 beq s0,a5,92 <.L8> - 50: 4701 li a4,0 - 52: 0087ff63 bgeu a5,s0,70 <.L9> - -00000056 <.L5>: - 56: 00000097 auipc ra,0x0 - 5a: 000080e7 jalr ra # 56 <.L5> - -0000005e <.L7>: - 5e: 04000793 li a5,64 - 62: 04f40363 beq s0,a5,a8 <.L10> - 66: 05000793 li a5,80 - 6a: 4701 li a4,0 - 6c: fef415e3 bne s0,a5,56 <.L5> - -00000070 <.L9>: - 70: 4682 lw a3,0(sp) - 72: 05000793 li a5,80 - 76: 02f69e63 bne a3,a5,b2 <.L11> - -0000007a <.LBB18>: - 7a: 00348513 add a0,s1,3 - 7e: 9971 and a0,a0,-4 - -00000080 <.LVL14>: - 80: 411c lw a5,0(a0) - -00000082 <.LVL15>: - 82: 0511 add a0,a0,4 - -00000084 <.L12>: - 84: 4712 lw a4,4(sp) - -00000086 <.LBE16>: - 86: 40e2 lw ra,24(sp) - 88: 4452 lw s0,20(sp) - -0000008a <.LBB25>: - 8a: c31c sw a5,0(a4) - -0000008c <.LBE25>: - 8c: 44c2 lw s1,16(sp) - -0000008e <.LVL18>: - 8e: 0171 add sp,sp,28 - -00000090 <.LVL19>: - 90: 8082 ret - -00000092 <.L8>: - 92: 00000097 auipc ra,0x0 - 96: 000080e7 jalr ra # 92 <.L8> - -0000009a <.L36>: - 9a: 872a mv a4,a0 - 9c: bfd1 j 70 <.L9> - -0000009e <.L6>: - 9e: 00000097 auipc ra,0x0 - a2: 000080e7 jalr ra # 9e <.L6> - -000000a6 <.LVL23>: - a6: bfd5 j 9a <.L36> - -000000a8 <.L10>: - a8: 00000097 auipc ra,0x0 - ac: 000080e7 jalr ra # a8 <.L10> - -000000b0 <.LVL25>: - b0: b7ed j 9a <.L36> - -000000b2 <.L11>: - b2: 4782 lw a5,0(sp) - b4: 45b1 li a1,12 - b6: 8bbd and a5,a5,15 - b8: f8f5efe3 bltu a1,a5,56 <.L5> - bc: 000005b7 lui a1,0x0 - c0: 078a sll a5,a5,0x2 - c2: 00058593 mv a1,a1 - c6: 97ae add a5,a5,a1 - c8: 439c lw a5,0(a5) - ca: 8782 jr a5 - -000000cc <.L21>: - cc: 006c add a1,sp,12 - ce: 8526 mv a0,s1 - d0: c43a sw a4,8(sp) - d2: 00000097 auipc ra,0x0 - d6: 000080e7 jalr ra # d2 <.L21+0x6> - -000000da <.LVL27>: - da: 47b2 lw a5,12(sp) - -000000dc <.LBE19>: - dc: 4722 lw a4,8(sp) - -000000de <.L23>: - de: d3dd beqz a5,84 <.L12> - e0: a83d j 11e <.L24> - -000000e2 <.L27>: - e2: 8526 mv a0,s1 - e4: 4781 li a5,0 - e6: 4581 li a1,0 - -000000e8 <.L17>: - e8: 00054303 lbu t1,0(a0) - ec: 0505 add a0,a0,1 - -000000ee <.LVL32>: - ee: 07f37293 and t0,t1,127 - f2: 00b292b3 sll t0,t0,a1 - f6: 0057e7b3 or a5,a5,t0 - fa: 01831293 sll t0,t1,0x18 - fe: 4182d293 sra t0,t0,0x18 - 102: 059d add a1,a1,7 # 7 <.L2+0x3> - 104: fe02c2e3 bltz t0,e8 <.L17> - 108: 42fd li t0,31 - 10a: fcb2eae3 bltu t0,a1,de <.L23> - 10e: 04037313 and t1,t1,64 - -00000112 <.LVL35>: - 112: fc0306e3 beqz t1,de <.L23> - 116: 537d li t1,-1 - 118: 00b315b3 sll a1,t1,a1 - -0000011c <.LVL36>: - 11c: 8fcd or a5,a5,a1 - -0000011e <.L24>: - 11e: 45c1 li a1,16 - 120: 00b41363 bne s0,a1,126 <.L25> - 124: 8726 mv a4,s1 - -00000126 <.L25>: - 126: 00010403 lb s0,0(sp) - 12a: 97ba add a5,a5,a4 - 12c: f4045ce3 bgez s0,84 <.L12> - 130: 439c lw a5,0(a5) - 132: bf89 j 84 <.L12> - -00000134 <.L20>: - 134: 0014c783 lbu a5,1(s1) - 138: 0004c583 lbu a1,0(s1) - 13c: 07a2 sll a5,a5,0x8 - 13e: 8fcd or a5,a5,a1 - -00000140 <.L37>: - 140: 00248513 add a0,s1,2 - -00000144 <.LVL42>: - 144: bf69 j de <.L23> - -00000146 <.L16>: - 146: 0014c783 lbu a5,1(s1) - 14a: 0004c583 lbu a1,0(s1) - 14e: 07a2 sll a5,a5,0x8 - 150: 8fcd or a5,a5,a1 - 152: 07c2 sll a5,a5,0x10 - 154: 87c1 sra a5,a5,0x10 - 156: b7ed j 140 <.L37> - -00000158 <.L15>: - 158: 0014c783 lbu a5,1(s1) - 15c: 0004c583 lbu a1,0(s1) - 160: 00448513 add a0,s1,4 - 164: 07a2 sll a5,a5,0x8 - 166: 8fcd or a5,a5,a1 - 168: 0024c583 lbu a1,2(s1) - 16c: 05c2 sll a1,a1,0x10 - 16e: 8ddd or a1,a1,a5 - 170: 0034c783 lbu a5,3(s1) - 174: 07e2 sll a5,a5,0x18 - 176: 8fcd or a5,a5,a1 - -00000178 <.LVL44>: - 178: b79d j de <.L23> - -0000017a <.L13>: - 17a: 0014c783 lbu a5,1(s1) - 17e: 0004c583 lbu a1,0(s1) - 182: 00848513 add a0,s1,8 - 186: 07a2 sll a5,a5,0x8 - 188: 8fcd or a5,a5,a1 - 18a: 0024c583 lbu a1,2(s1) - 18e: 05c2 sll a1,a1,0x10 - 190: 8ddd or a1,a1,a5 - 192: 0034c783 lbu a5,3(s1) - 196: 07e2 sll a5,a5,0x18 - 198: 8fcd or a5,a5,a1 - -0000019a <.LVL46>: - 19a: b791 j de <.L23> - -0000019c <__gcc_personality_v0>: - 19c: fbc10113 add sp,sp,-68 - 1a0: de22 sw s0,60(sp) - 1a2: c086 sw ra,64(sp) - 1a4: 843e mv s0,a5 - 1a6: dc26 sw s1,56(sp) - 1a8: c23a sw a4,4(sp) - 1aa: c602 sw zero,12(sp) - 1ac: 4785 li a5,1 - -000001ae <.LVL48>: - 1ae: 14f51263 bne a0,a5,2f2 <.L53> - 1b2: 8989 and a1,a1,2 - -000001b4 <.LVL49>: - 1b4: c9f5 beqz a1,2a8 <.L41> - 1b6: 8522 mv a0,s0 - -000001b8 <.LVL50>: - 1b8: 00000097 auipc ra,0x0 - 1bc: 000080e7 jalr ra # 1b8 <.LVL50> - -000001c0 <.LVL51>: - 1c0: 84aa mv s1,a0 - -000001c2 <.LVL52>: - 1c2: c17d beqz a0,2a8 <.L41> - -000001c4 <.LBB31>: - 1c4: 4501 li a0,0 - 1c6: c411 beqz s0,1d2 <.L43> - 1c8: 8522 mv a0,s0 - 1ca: 00000097 auipc ra,0x0 - 1ce: 000080e7 jalr ra # 1ca <.LBB31+0x6> - -000001d2 <.L43>: - 1d2: 0004c583 lbu a1,0(s1) - 1d6: d02a sw a0,32(sp) - 1d8: 0ff00793 li a5,255 - 1dc: 00148613 add a2,s1,1 - -000001e0 <.LVL55>: - 1e0: 0cf58b63 beq a1,a5,2b6 <.L44> - 1e4: 1054 add a3,sp,36 - 1e6: 8522 mv a0,s0 - 1e8: 00000097 auipc ra,0x0 - 1ec: 000080e7 jalr ra # 1e8 <.LVL55+0x8> - -000001f0 <.LVL56>: - 1f0: 862a mv a2,a0 - -000001f2 <.L45>: - 1f2: 00064703 lbu a4,0(a2) - 1f6: 0ff00693 li a3,255 - 1fa: 00160513 add a0,a2,1 - -000001fe <.LVL58>: - 1fe: 02e10a23 sb a4,52(sp) - 202: 4781 li a5,0 - 204: 00d70963 beq a4,a3,216 <.L46> - 208: 086c add a1,sp,28 - 20a: 00000097 auipc ra,0x0 - 20e: 000080e7 jalr ra # 20a <.LVL58+0xc> - -00000212 <.LVL59>: - 212: 47f2 lw a5,28(sp) - 214: 97aa add a5,a5,a0 - -00000216 <.L46>: - 216: d63e sw a5,44(sp) - -00000218 <.LVL60>: - 218: 00054783 lbu a5,0(a0) - 21c: 086c add a1,sp,28 - 21e: 0505 add a0,a0,1 - -00000220 <.LVL61>: - 220: c03e sw a5,0(sp) - 222: 02f10aa3 sb a5,53(sp) - 226: 00000097 auipc ra,0x0 - 22a: 000080e7 jalr ra # 226 <.LVL61+0x6> - -0000022e <.LVL62>: - 22e: 4372 lw t1,28(sp) - 230: c42a sw a0,8(sp) - -00000232 <.LBE31>: - 232: 006c add a1,sp,12 - -00000234 <.LBB36>: - 234: 006504b3 add s1,a0,t1 - -00000238 <.LBE36>: - 238: 8522 mv a0,s0 - -0000023a <.LBB37>: - 23a: d826 sw s1,48(sp) - -0000023c <.LBE37>: - 23c: 00000097 auipc ra,0x0 - 240: 000080e7 jalr ra # 23c <.LBE37> - -00000244 <.LVL66>: - 244: 4732 lw a4,12(sp) - 246: 4622 lw a2,8(sp) - 248: 87aa mv a5,a0 - -0000024a <.LVL67>: - 24a: e319 bnez a4,250 <.L48> - 24c: fff50793 add a5,a0,-1 - -00000250 <.L48>: - 250: 04967c63 bgeu a2,s1,2a8 <.L41> - -00000254 <.LBB38>: - 254: 4582 lw a1,0(sp) - 256: 0814 add a3,sp,16 - 258: 4501 li a0,0 - 25a: c43e sw a5,8(sp) - 25c: 00000097 auipc ra,0x0 - 260: 000080e7 jalr ra # 25c <.LBB38+0x8> - -00000264 <.LVL69>: - 264: 4582 lw a1,0(sp) - 266: 862a mv a2,a0 - -00000268 <.LVL70>: - 268: 0854 add a3,sp,20 - 26a: 4501 li a0,0 - -0000026c <.LVL71>: - 26c: 00000097 auipc ra,0x0 - 270: 000080e7 jalr ra # 26c <.LVL71> - -00000274 <.LVL72>: - 274: 4582 lw a1,0(sp) - 276: 862a mv a2,a0 - -00000278 <.LVL73>: - 278: 0834 add a3,sp,24 - 27a: 4501 li a0,0 - -0000027c <.LVL74>: - 27c: 00000097 auipc ra,0x0 - 280: 000080e7 jalr ra # 27c <.LVL74> - -00000284 <.LVL75>: - 284: 086c add a1,sp,28 - 286: 00000097 auipc ra,0x0 - 28a: 000080e7 jalr ra # 286 <.LVL75+0x2> - -0000028e <.LVL76>: - 28e: 5702 lw a4,32(sp) - 290: 46c2 lw a3,16(sp) - 292: 47a2 lw a5,8(sp) - 294: 862a mv a2,a0 - -00000296 <.LVL77>: - 296: 9736 add a4,a4,a3 - 298: 04e7eb63 bltu a5,a4,2ee <.L56> - 29c: 46d2 lw a3,20(sp) - 29e: 9736 add a4,a4,a3 - 2a0: fae7f8e3 bgeu a5,a4,250 <.L48> - 2a4: 47e2 lw a5,24(sp) - 2a6: eb91 bnez a5,2ba <.L50> - -000002a8 <.L41>: - 2a8: 4521 li a0,8 - -000002aa <.L38>: - 2aa: 4086 lw ra,64(sp) - 2ac: 5472 lw s0,60(sp) - -000002ae <.LVL79>: - 2ae: 54e2 lw s1,56(sp) - 2b0: 04410113 add sp,sp,68 - -000002b4 <.LVL80>: - 2b4: 8082 ret - -000002b6 <.L44>: - 2b6: d22a sw a0,36(sp) - 2b8: bf2d j 1f2 <.L45> - -000002ba <.L50>: - 2ba: 5712 lw a4,36(sp) - 2bc: 00e784b3 add s1,a5,a4 - -000002c0 <.LBE40>: - 2c0: d4e5 beqz s1,2a8 <.L41> - 2c2: 4612 lw a2,4(sp) - 2c4: 45a9 li a1,10 - 2c6: 8522 mv a0,s0 - -000002c8 <.LVL84>: - 2c8: 00000097 auipc ra,0x0 - 2cc: 000080e7 jalr ra # 2c8 <.LVL84> - -000002d0 <.LVL85>: - 2d0: 4601 li a2,0 - 2d2: 45ad li a1,11 - 2d4: 8522 mv a0,s0 - 2d6: 00000097 auipc ra,0x0 - 2da: 000080e7 jalr ra # 2d6 <.LVL85+0x6> - -000002de <.LVL86>: - 2de: 8522 mv a0,s0 - 2e0: 85a6 mv a1,s1 - 2e2: 00000097 auipc ra,0x0 - 2e6: 000080e7 jalr ra # 2e2 <.LVL86+0x4> - -000002ea <.LVL87>: - 2ea: 451d li a0,7 - 2ec: bf7d j 2aa <.L38> - -000002ee <.L56>: - 2ee: 8626 mv a2,s1 - -000002f0 <.LVL89>: - 2f0: b785 j 250 <.L48> - -000002f2 <.L53>: - 2f2: 450d li a0,3 - -000002f4 <.LVL91>: - 2f4: bf5d j 2aa <.L38> - -emutls.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <__emutls_get_address>: - 0: 451c lw a5,8(a0) - 2: 1141 add sp,sp,-16 - 4: c422 sw s0,8(sp) - 6: c606 sw ra,12(sp) - 8: c226 sw s1,4(sp) - a: 842a mv s0,a0 - c: ef95 bnez a5,48 <.L2> - -0000000e <.LBB6>: - e: 4144 lw s1,4(a0) - 10: 4791 li a5,4 - 12: 4110 lw a2,0(a0) - 14: 0497e063 bltu a5,s1,54 <.L3> - 18: 00460513 add a0,a2,4 - -0000001c <.LVL2>: - 1c: c032 sw a2,0(sp) - 1e: 00000097 auipc ra,0x0 - 22: 000080e7 jalr ra # 1e <.LVL2+0x2> - -00000026 <.LVL3>: - 26: 4602 lw a2,0(sp) - 28: e509 bnez a0,32 <.L4> - -0000002a <.L6>: - 2a: 00000097 auipc ra,0x0 - 2e: 000080e7 jalr ra # 2a <.L6> - -00000032 <.L4>: - 32: c108 sw a0,0(a0) - 34: 00450793 add a5,a0,4 - -00000038 <.L5>: - 38: 444c lw a1,12(s0) - 3a: c1a1 beqz a1,7a <.L7> - 3c: 853e mv a0,a5 - -0000003e <.LVL6>: - 3e: 00000097 auipc ra,0x0 - 42: 000080e7 jalr ra # 3e <.LVL6> - -00000046 <.L13>: - 46: c408 sw a0,8(s0) - -00000048 <.L2>: - 48: 4408 lw a0,8(s0) - 4a: 40b2 lw ra,12(sp) - 4c: 4422 lw s0,8(sp) - -0000004e <.LVL8>: - 4e: 4492 lw s1,4(sp) - 50: 0141 add sp,sp,16 - 52: 8082 ret - -00000054 <.L3>: - 54: 00960533 add a0,a2,s1 - 58: 050d add a0,a0,3 - 5a: c032 sw a2,0(sp) - 5c: 00000097 auipc ra,0x0 - 60: 000080e7 jalr ra # 5c <.L3+0x8> - -00000064 <.LVL10>: - 64: d179 beqz a0,2a <.L6> - 66: 00348793 add a5,s1,3 - 6a: 97aa add a5,a5,a0 - 6c: 409004b3 neg s1,s1 - 70: 8fe5 and a5,a5,s1 - -00000072 <.LVL11>: - 72: 4602 lw a2,0(sp) - 74: fea7ae23 sw a0,-4(a5) - 78: b7c1 j 38 <.L5> - -0000007a <.L7>: - 7a: 4581 li a1,0 - 7c: 853e mv a0,a5 - -0000007e <.LVL12>: - 7e: 00000097 auipc ra,0x0 - 82: 000080e7 jalr ra # 7e <.LVL12> - -00000086 <.LVL13>: - 86: b7c1 j 46 <.L13> - -00000088 <__emutls_register_common>: - 88: 411c lw a5,0(a0) - 8a: 00b7f563 bgeu a5,a1,94 <.L15> - 8e: c10c sw a1,0(a0) - 90: 00052623 sw zero,12(a0) - -00000094 <.L15>: - 94: 415c lw a5,4(a0) - 96: 00c7f363 bgeu a5,a2,9c <.L16> - 9a: c150 sw a2,4(a0) - -0000009c <.L16>: - 9c: c689 beqz a3,a6 <.L14> - 9e: 411c lw a5,0(a0) - a0: 00b79363 bne a5,a1,a6 <.L14> - a4: c554 sw a3,12(a0) - -000000a6 <.L14>: - a6: 8082 ret diff --git a/inc/misc/install_xpack_gcc.ps1 b/inc/misc/install_xpack_gcc.ps1 new file mode 100644 index 0000000..cde131f --- /dev/null +++ b/inc/misc/install_xpack_gcc.ps1 @@ -0,0 +1,190 @@ +using namespace System.IO; +using namespace System.IO.Compression.FileSystem; + +[CmdletBinding(DefaultParameterSetName = 'DestPreset')] +param ( + # Uses one of the preset locations to install to + [Parameter(ParameterSetName = 'DestPreset', Position = 0)] + [ValidateSet('User', 'System')] + [string]$Destination = 'User', + + # If a preset location is not used, then the user must specify a path to install to + [Parameter(ParameterSetName = 'DestPath', Position = 0, Mandatory = $true)] + [string]$Path, + + # If enabled, will prevent modification of your PATH environment variable + [switch]$NoPath, + + # If enabled, will not install our make + [switch]$NoMake, + + # Skips all prompts and just installs, mainly intended for use if we need to re-run as admin. + [switch]$SkipPrompts +); + +$ErrorActionPreference = 'Stop'; + +[string] $XpackVersion = '14.2.0-3'; +[string] $XpackEdition = 'riscv-none-elf-gcc'; +[string] $XpackArch = 'win32-x64'; +[string] $XpackNameEd = "xpack-$XpackEdition"; +[string] $XpackNameEdVer = "$XpackNameEd-$XpackVersion"; +[string] $XpackNameEdVerArch = "$XpackNameEdVer-$XpackArch" +[string] $XpackDownloadFilename = "$XpackNameEdVerArch.zip"; +[string] $XpackDownloadURL = "https://github.com/xpack-dev-tools/$XpackEdition-xpack/releases/download/v$XpackVersion/$XpackDownloadFilename"; + +[string] $MakeVersion = '4.4.1'; +[string] $MakeEdition = 'without-guile'; +[string] $MakeArch = 'w32'; +[string] $MakeName = "make-$MakeVersion-$MakeEdition" +[string] $MakeNameFull = "$MakeName-$MakeArch"; +[string] $MakeDownloadFilename = "$MakeNameFull-bin.zip"; +[string] $MakeDownloadURL = "https://sourceforge.net/projects/ezwinports/files/$MakeDownloadFilename/download"; + +[EnvironmentVariableTarget] $PathScope = [EnvironmentVariableTarget]::User; +[string] $TempFolder = [Path]::GetTempPath(); +[bool] $NoClearTemp = $false; + +if ($PSCmdlet.ParameterSetName -EQ 'DestPreset') +{ + if ($Destination -EQ 'User') { $Path = Join-Path $ENV:LocalAppData $XpackNameEd; } + elseif ($Destination -EQ 'System') + { + $Path = Join-Path $ENV:ProgramFiles $XpackNameEd; + $PathScope = [EnvironmentVariableTarget]::Machine; + } + else { throw 'Unknown Preset Destination'; } +} +if ([string]::IsNullOrEmpty($Path)) { throw 'Destination path must be provided'; } + +[string] $TempFolder = Join-Path $TempFolder 'ch32fun'; +[string] $XpackDownloadFilePath = Join-Path $TempFolder $XpackDownloadFilename; +[string] $XpackPath = Join-Path $Path $XpackVersion; +[string] $XpackBinPath = Join-Path $XpackPath 'bin'; +[string] $MakeDownloadFilePath = Join-Path $TempFolder $MakeDownloadFilename; + +Write-Host "${XpackNameEdVer}:"; +Write-Host " will be downloaded from " -NoNewline -ForegroundColor 'DarkGray'; +Write-Host $XpackDownloadURL -ForegroundColor 'DarkGreen'; +Write-Host " to " -NoNewline -ForegroundColor 'DarkGray'; +Write-Host $XpackDownloadFilePath -ForegroundColor 'DarkGreen'; +Write-Host " then installed to " -NoNewline -ForegroundColor 'DarkGray'; +Write-Host $XpackPath -ForegroundColor 'DarkGreen'; +Write-Host; +if (-NOT $NoMake) +{ + Write-Host "${MakeName}:" + Write-Host " will be downloaded from " -NoNewline -ForegroundColor 'DarkGray'; + Write-Host $MakeDownloadURL -ForegroundColor 'DarkGreen'; + Write-Host " to " -NoNewline -ForegroundColor 'DarkGray'; + Write-Host $MakeDownloadFilePath -ForegroundColor 'DarkGreen'; + Write-Host " then installed to " -NoNewline -ForegroundColor 'DarkGray'; + Write-Host $XpackBinPath -ForegroundColor 'DarkGreen'; + Write-Host; +} +if ($NoPath) { Write-Host "Your environment variables will not be edited.`n"; } +else +{ + Write-Host "xpack will be added to your " -NoNewline; + Write-Host $PathScope.ToString().ToLower() -ForegroundColor 'DarkGreen' -NoNewline; + Write-Host " PATH environment variable.`n"; +} +if (-NOT $SkipPrompts) +{ + [string] $Answer = Read-Host -Prompt "Is this correct? (y/n)"; + if ($Answer -NE 'y') { Exit; } +} + +try +{ # Check if we need elevation + [bool] $IsAdmin = ([Security.Principal.WindowsPrincipal] [Security.Principal.WindowsIdentity]::GetCurrent()).IsInRole([Security.Principal.WindowsBuiltInRole] 'Administrator'); + if ((-NOT $NoPath) -AND ($PathScope -EQ [EnvironmentVariableTarget]::Machine) -AND (-NOT $IsAdmin)) { throw; } # If we want to set the system PATH variable, we need to elevate + if (-NOT (Test-Path $Path)) { New-Item -ItemType Directory -Path $Path -ErrorAction SilentlyContinue -ErrorVariable PermissionError | Out-Null; } + if ($PermissionError) { throw; } + [string] $TestFile = Join-Path $Path 'TestingFile.txt'; + Set-Content -Path $TestFile -Value 'Checking permissions.' -ErrorAction SilentlyContinue -ErrorVariable PermissionError; + if ($PermissionError) { throw; } + Remove-Item -Path $TestFile -ErrorAction SilentlyContinue -ErrorVariable PermissionError; + if ($PermissionError) { throw; } +} +catch +{ + Write-Host 'Administrator permissions are required, requesting elevation...'; + if (-NOT ([Security.Principal.WindowsPrincipal] [Security.Principal.WindowsIdentity]::GetCurrent()).IsInRole([Security.Principal.WindowsBuiltInRole] 'Administrator')) + { + if ([int](Get-CimInstance -Class Win32_OperatingSystem | Select-Object -ExpandProperty BuildNumber) -GE 6000) + { + $CommandLine = "-File `"$($MyInvocation.MyCommand.Path)`" -SkipPrompts"; + if ($PSCmdlet.ParameterSetName -EQ 'DestPreset') { $CommandLine += " -Destination `"$Destination`""; } + else { $CommandLine += " -Path `"$Path`""; } + if ($NoPath) { $CommandLine += ' -NoPath'; } + if ($NoMake) { $CommandLine += ' -NoMake'; } + try { Start-Process -FilePath 'PowerShell.exe' -Verb RunAs -ArgumentList $CommandLine; } + catch { Write-Error 'Failed to elevate to administrator.'; Exit; } + } + } + else { Write-Error 'Could not access folder, but am already administrator!'; Exit; } + if (-NOT $NoPath) { Write-Host 'You may need to restart your terminal before changes apply.'; } + Exit; +} + +[void](New-Item -Path $TempFolder -ItemType Directory -Force); +[void](New-Item -Path $Path -ItemType Directory -Force); + +if ($PSVersionTable.PSVersion.Major -LT 7) { $ProgressPreference = 'SilentlyContinue'; } # Showing progress makes it download very slowly on old PowerShell https://github.com/PowerShell/PowerShell/issues/2138 + +Write-Host "Downloading $XpackDownloadFilename" -NoNewline; +try { Write-Host $(' ({0:F2} MB)...' -F ([long]::Parse((Invoke-WebRequest -UseBasicParsing -Uri $XpackDownloadURL -Method Head).Headers['Content-Length']) / (1024.0 * 1024.0))); } +catch { Write-Host '...'; } +Invoke-WebRequest -UseBasicParsing -Uri $XpackDownloadURL -OutFile $XpackDownloadFilePath; + +if (-NOT $NoMake) +{ + Write-Host "Downloading $MakeDownloadFilename..."; + Invoke-WebRequest -UseBasicParsing -UserAgent 'Wget' -Uri $MakeDownloadURL -OutFile $MakeDownloadFilePath; +} + +Write-Host "Extracting $XpackDownloadFilename..."; +[string] $XpackTempPath = Join-Path $TempFolder 'xpath'; +if (Test-Path $XpackTempPath) { Remove-Item -Recurse -Force $XpackTempPath; } +Expand-Archive $XpackDownloadFilePath -DestinationPath $XpackTempPath; +if (-NOT (Test-Path $XpackPath)) { [void](New-Item -Path $XpackPath -ItemType Directory -Force); } +Copy-Item -Path $(Join-Path $(Join-Path $XpackTempPath $XpackNameEdVer) '*') -Destination $XpackPath -Recurse -Force; + +if (-NOT $NoMake) +{ + [string] $MakeTempPath = Join-Path $TempFolder 'make'; + Write-Host "Extracting $MakeDownloadFilename..."; + Expand-Archive -Force $MakeDownloadFilePath -DestinationPath $MakeTempPath; + Move-Item -Force -Path $(Join-Path $MakeTempPath 'bin/make.exe') -Destination $XpackBinPath; +} + +if (-NOT $NoClearTemp) +{ + Write-Host "Deleting $TempFolder..."; + Remove-Item $TempFolder -Force -Recurse; +} + +if (-NOT $NoPath) +{ + Write-Host "Adding to $PathScope PATH environment variable..."; + $CurrentPATH = [Environment]::GetEnvironmentVariable('PATH', $PathScope); + if ([string]::IsNullOrWhitespace($CurrentPATH)) { Write-Error 'Could not retrieve the current PATH, not editing'; Exit; } + + if ($CurrentPATH.Contains($XpackBinPath.TrimEnd(('\', '/')))) # If the install dir is on the path, regardless of trailing slash or not + { + Write-Host ' It looks like this xpack installation is already in your user PATH, so it will not be edited.'; + } + else { + $NewPATH = "$CurrentPATH;$XpackBinPath"; + [Environment]::SetEnvironmentVariable('PATH', $NewPATH, $PathScope); + Write-Host ' You may need to restart your terminal before you can use xpack gcc.'; + } + # Detect GitHub Actions runner and export for future steps + if ($env:GITHUB_ACTIONS -eq 'true') { + Write-Host "Detected GitHub Actions runner. Prepending xPack bin to PATH for workflow steps..." + Add-Content -Path $env:GITHUB_ENV -Value "PATH=$XpackBinPath`:$env:PATH" + } +} + +Write-Host 'Finished!'; \ No newline at end of file diff --git a/inc/misc/minichlink-live/README.md b/inc/misc/minichlink-live/README.md new file mode 100644 index 0000000..496b1b8 --- /dev/null +++ b/inc/misc/minichlink-live/README.md @@ -0,0 +1,37 @@ +# Minichlink live command server + +Minichlink now supports a command server on port 4444. +Currently, there are only two commands implemented: + - `-s` Set/Write command + - `-m` Read command + +The format of these commands is the same as the command line interface commands with the same name: +```sh +-s [debug register] [value] +-m [debug register] +``` +> [!WARNING] +> All values MUST be expressed in hexadecimal: +```sh +-s 0x20 0xc02a717d +``` + +Multiple commands can be chained together, the results of the read operations will be returned as a key value pair with the key being the register address: +```sh +04: 1234bees5 +04: f00cac1a +``` + +The QingKe V4 Processor manual describes how to build these commands, but there are also 4 example scripts that you can use: +```sh +./read.sh dma_count # reads contents of memory of `debug_count` symbol + +./write.sh dma_count 123 # writes the value 123 at `dma_count` symbol address + +./batch_read.sh dma_buffer # reads the contents of the symbol `dma_buffer` + # size is deduced automatically, but can also be specified with a second argument + +./plot.py dma_count # continuously read a value an plot it +``` +> [!WARNING] +> All of these scripts are examples, not tools, treat appropriately diff --git a/inc/misc/minichlink-live/batch_read.sh b/inc/misc/minichlink-live/batch_read.sh new file mode 100755 index 0000000..d750d83 --- /dev/null +++ b/inc/misc/minichlink-live/batch_read.sh @@ -0,0 +1,64 @@ +#!/usr/bin/env bash + +SYMBOL=$1 +COUNT=$2 +if [ -z "$SYMBOL" ]; then + echo "Usage: $0 []" + exit 1 +fi + +echo "Searching for symbol: '$SYMBOL'" + +ADDR="$(riscv64-unknown-elf-objdump -t *.elf | grep $SYMBOL | awk '{print "0x"$1}')" +if [ -z "$COUNT" ]; then + WORDS=$(riscv64-unknown-elf-objdump -t *.elf | grep $SYMBOL | awk '{print int(("0x"$5 + 3) / 4)}') +else + WORDS=$COUNT +fi + +if [ -z "$ADDR" ]; then + echo "Error: Symbol '$SYMBOL' not found in the object file." + exit 1 +fi + +if ! [[ $ADDR =~ ^0x[0-9a-fA-F]+$ ]]; then + echo "Error: Address must be in hexadecimal format (e.g., 0x20000000)." + exit 1 +fi + +echo "Reading $WORDS words from $SYMBOL@$ADDR" + +commands=" -s 0x10 0x80000001" # Make the debug module work properly. + +# Prelude +commands+=" -s 0x20 0xc02a717d" # add sp,sp,-16; sw a0,0(sp) +commands+=" -s 0x21 0x9002c22e" # sw a1,4(sp); ebreak +commands+=" -s 0x17 0x00270000" # Abstact cmd exec progbuf +# commands+=" -m 0x16" # Read ABSTRACTCS + +# Batch Read +commands+=" -s 0x20 0x05914188" # lw a0,0(a1); add a1,a1,4 +commands+=" -s 0x21 0x90029002" # ebreak + +commands+=" -s 0x04 $ADDR" # Write address 0x20000000 to DATA0 +commands+=" -s 0x17 0x0027100b" # Abstract cmd data0->x11 and exec progbuf +# commands+=" -m 0x16" # Read ABSTRACTCS + +for i in $(seq 0 $((WORDS - 2))); do + commands+=" -s 0x17 0x0026100a" # Abstract exec and x10->data0 + # commands+=" -m 0x16" # Read ABSTRACTCS + commands+=" -m 0x04" # Read DATA0 +done + +commands+=" -s 0x17 0x0022100a" # Abstract cmd x10->data0 +# commands+=" -m 0x16" # Read ABSTRACTCS +commands+=" -m 0x04" # Read DATA0 + +# Postlude +commands+=" -s 0x20 0x45924502" # lw a0,0(sp); lw a1,4(sp) +commands+=" -s 0x21 0x90026141" # add sp,sp,16; ebreak +# commands+=" -s 0x17 0x00270000" # Abstact cmd exec progbuf + +commands+=" -s 0x10 0x40000001" # Resume(1<<30) without reset(1<<0) + +echo $commands | nc localhost 4444 diff --git a/inc/misc/minichlink-live/plot.py b/inc/misc/minichlink-live/plot.py new file mode 100755 index 0000000..2244505 --- /dev/null +++ b/inc/misc/minichlink-live/plot.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python3 + +import matplotlib.pyplot as plt +from matplotlib.animation import FuncAnimation +import sys +import subprocess +import socket + + +PERIOD_MS = 1000 / 30 +SAMPLES = 200 +symbol = sys.argv[1] + +fig, ax = plt.subplots() +xdata, ydata = range(SAMPLES), [0] * SAMPLES +(ln,) = plt.plot([], []) + +# find elf in current directory +result = subprocess.run(["find", ".", "-name", "*.elf"], capture_output=True, text=True) +if result.returncode != 0: + print(f"Error: {result.stderr.strip()}") + sys.exit(1) + +elf = result.stdout.splitlines()[0] +print(f"Using ELF file: {elf}") + +result = subprocess.run( + ["riscv64-unknown-elf-objdump", "-t", elf], capture_output=True, text=True +) +if result.returncode != 0: + print(f"Error: {result.stderr.strip()}") + sys.exit(1) + +symbol_address = -1 +for line in result.stdout.splitlines()[4:]: + name = line.split()[-1] + if symbol == name: + symbol_address = int(line.split()[0], 16) + break + +if symbol_address == -1: + print(f"Error: Symbol '{symbol}' not found in ELF file.") + sys.exit(1) + +print(f"Symbol '{symbol}' found at address: {symbol_address:#x}") + +commands = " -s 0x10 0x80000001" # Make the debug module work properly. + +commands += " -s 0x20 0xc02a717d" # add sp,sp,-16; sw a0,0(sp) +commands += " -s 0x21 0xc432c22e" # sw a1,4(sp); sw a2,8(sp) +commands += " -s 0x22 0xe0000637" # lui a2,0xe0000 +commands += " -s 0x23 0x0f460613" # add a2,a2,244 # e00000f4 +commands += " -s 0x24 0x410c4208" # lw a0,0(a2); lw a1,0(a0) +commands += " -s 0x25 0x4502c20c" # sw a1,0(a2); lw a0,0(sp) +commands += " -s 0x26 0x46224592" # lw a1,4(sp); lw a2,8(sp) +commands += " -s 0x27 0x90026141" # add sp,sp,16; ebreak + +commands += f" -s 0x04 {symbol_address:#x}" # Write address 0x20000000 to DATA0 +commands += " -s 0x17 0x00270000" # Abstact cmd exec progbuf +commands += " -m 0x16" # Read ABSTRACTCS +commands += " -m 0x04" # Read DATA0 + +commands += " -s 0x10 0x40000001" # Resume(1<<30) without reset(1<<0) + +command = commands.encode() + + +def read_memory(): + s = socket.socket(socket.AF_INET, socket.SOCK_STREAM) + s.connect(("127.0.0.1", 4444)) + s.send(command) + + data = s.recv(1024).decode() + s.close() + + return data + + +def get_value(): + value = int(read_memory().splitlines()[-1].split()[-1], 16) + print(f"Received value: {value}") + return value + + +def init(): + ax.set_xlim(0, SAMPLES) + ax.set_ylim(0, 1024) + return (ln,) + + +def update(frame): + global ydata + value = get_value() + ydata = ydata[1:] + [value] + ln.set_data(xdata, ydata) + return (ln,) + + +ani = FuncAnimation( + fig, update, frames=SAMPLES, init_func=init, blit=True, interval=PERIOD_MS +) +plt.show() diff --git a/inc/misc/minichlink-live/read.sh b/inc/misc/minichlink-live/read.sh new file mode 100755 index 0000000..05fb674 --- /dev/null +++ b/inc/misc/minichlink-live/read.sh @@ -0,0 +1,43 @@ +#!/usr/bin/env bash + +SYMBOL=$1 +if [ -z "$SYMBOL" ]; then + echo "Usage: $0 " + exit 1 +fi + +echo "Searching for symbol: '$SYMBOL'" + +ADDR=$(riscv64-unknown-elf-objdump -t *.elf | grep $SYMBOL | awk '{print "0x"$1}') + +if [ -z "$ADDR" ]; then + echo "Error: Symbol '$SYMBOL' not found in the object file." + exit 1 +fi + +if ! [[ $ADDR =~ ^0x[0-9a-fA-F]+$ ]]; then + echo "Error: Address must be in hexadecimal format (e.g., 0x20000000)." + exit 1 +fi + +echo "Reading $SYMBOL@$ADDR" + +commands=" -s 0x10 0x80000001" # Make the debug module work properly. + +commands+=" -s 0x20 0xc02a717d" # add sp,sp,-16; sw a0,0(sp) +commands+=" -s 0x21 0xc432c22e" # sw a1,4(sp); sw a2,8(sp) +commands+=" -s 0x22 0xe0000637" # lui a2,0xe0000 +commands+=" -s 0x23 0x0f460613" # add a2,a2,244 # e00000f4 +commands+=" -s 0x24 0x410c4208" # lw a0,0(a2); lw a1,0(a0) +commands+=" -s 0x25 0x4502c20c" # sw a1,0(a2); lw a0,0(sp) +commands+=" -s 0x26 0x46224592" # lw a1,4(sp); lw a2,8(sp) +commands+=" -s 0x27 0x90026141" # add sp,sp,16; ebreak + +commands+=" -s 0x04 $ADDR" # Write address 0x20000000 to DATA0 +commands+=" -s 0x17 0x00270000" # Abstact cmd exec progbuf +commands+=" -m 0x16" # Read ABSTRACTCS +commands+=" -m 0x04" # Read DATA0 + +commands+=" -s 0x10 0x40000001" # Resume(1<<30) without reset(1<<0) + +echo $commands | nc localhost 4444 diff --git a/inc/misc/minichlink-live/write.sh b/inc/misc/minichlink-live/write.sh new file mode 100755 index 0000000..aba24c9 --- /dev/null +++ b/inc/misc/minichlink-live/write.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash + +SYMBOL=$1 +VAL=$2 +if [ -z "$SYMBOL" ] || [ -z "$VAL" ]; then + echo "Usage: $0 " + exit 1 +fi + +echo "Searching for symbol: '$SYMBOL'" + +ADDR="0x$(riscv64-unknown-elf-objdump -t *.elf | grep $SYMBOL | awk '{print $1}')" + +if [ -z "$ADDR" ]; then + echo "Error: Symbol '$SYMBOL' not found in the object file." + exit 1 +fi + +if ! [[ $ADDR =~ ^0x[0-9a-fA-F]+$ ]]; then + echo "Error: Address must be in hexadecimal format (e.g., 0x20000000)." + exit 1 +fi + +# Convert the value to hexadecimal format +if ! [[ $VAL =~ ^0x[0-9a-fA-F]+$ ]]; then + VAL="0x$(printf '%x' "$VAL")" +fi + +echo "Setting $SYMBOL@$ADDR -> $VAL" + +commands=" -s 0x10 0x80000001" # Make the debug module work properly. +commands+=" -s 0x20 0x0072a023" # Write wcode of sw x7,0(x5) +commands+=" -s 0x21 0x00100073" # Write wcode of ebreak +commands+=" -s 0x04 $ADDR" # Write address 0x20000000 to DATA0 +commands+=" -s 0x17 0x00271005" # Abstract cmd data0->x5 and exec progbuf +commands+=" -s 0x04 $VAL" # Write value to DATA0 +commands+=" -s 0x17 0x00271007" # Abstract cmd data0->x7 +commands+=" -m 0x16" # Read ABSTRACTCS +commands+=" -s 0x10 0x40000001" # Resume(1<<30) without reset(1<<0) + +echo $commands | nc localhost 4444 diff --git a/inc/misc/tests/Makefile b/inc/misc/tests/Makefile new file mode 100644 index 0000000..fa10eda --- /dev/null +++ b/inc/misc/tests/Makefile @@ -0,0 +1,23 @@ +all : ci + +EXAMPLES := $(wildcard ../../examples/*/.) $(wildcard ../../examples_v10x/*/.) $(wildcard ../../examples_v20x/*/.) $(wildcard ../../examples_v30x/*/.) $(wildcard ../../examples_x035/*/.) + +.PHONY: ci tests all $(EXAMPLES) clean + +results : + mkdir -p results + +$(EXAMPLES) : results + echo $(shell basename $(realpath $(lastword $@))) + ($(MAKE) -C $@ build > results/$(subst .,,$(subst /,_,$@)).txt 2> results/$(subst .,,$(subst /,_,$@)).warning && echo "success" > results/$(subst .,,$(subst /,_,$@)).result) || echo "failure" > results/$(subst .,,$(subst /,_,$@)).result + echo $(shell basename $(realpath $(lastword $@))).bin > results/$(subst .,,$(subst /,_,$@)).stat + sha1sum $@/$(shell basename $(realpath $(lastword $@))).bin | cut -d' ' -f 1 >> results/$(subst .,,$(subst /,_,$@)).stat + wc --bytes $@/$(shell basename $(realpath $(lastword $@))).bin | cut -d' ' -f 1 >> results/$(subst .,,$(subst /,_,$@)).stat + +tests : $(EXAMPLES) + +ci : install tests + +clean : + rm -rf results + diff --git a/src/ch32fun.c b/src/ch32fun.c index 6f986e0..f4d93a7 100644 --- a/src/ch32fun.c +++ b/src/ch32fun.c @@ -32,7 +32,7 @@ void *memmove(void *dest, const void *src, size_t n) void *memchr(const void *src, int c, size_t n) int puts(const char *s) int mini_itoa(long value, unsigned int radix, int uppercase, int unsig, - char *buffer) + char *buffer) int mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va) int mini_vpprintf(int (*puts)(char* s, int len, void* buf), void* buf, const char *fmt, va_list va) int mini_snprintf(char* buffer, unsigned int buffer_len, const char *fmt, ...) @@ -64,8 +64,8 @@ void WaitForDebuggerToAttach() #endif #if (defined( FUNCONF_USE_DEBUGPRINTF ) && !FUNCONF_USE_DEBUGPRINTF) && \ - (defined( FUNCONF_USE_UARTPRINTF ) && !FUNCONF_USE_UARTPRINTF) && \ - (defined( FUNCONF_NULL_PRINTF ) && FUNCONF_NULL_PRINTF) + (defined( FUNCONF_USE_UARTPRINTF ) && !FUNCONF_USE_UARTPRINTF) && \ + (defined( FUNCONF_NULL_PRINTF ) && FUNCONF_NULL_PRINTF) int _write(int fd, const char *buf, int size) int putchar(int c) @@ -85,56 +85,73 @@ void __libc_init_array(void) #define _SSP_STRING_H_ #define _SSP_STDIO_H_ -// #include "ch32fun.h" -#include -#include -#include -#include #include #include +#include +#include +#include +#include -#define WEAK __attribute__((weak)) - -WEAK int errno; - -static int __puts_uart(char *s, int len, void *buf) +#if defined(CH32H41x) +volatile v5f_main v5f_start_function = NULL; +static int start_v5f(void) { - (void)buf; + if (v5f_start_function == NULL) + { + asm volatile ( + "li a1, 1\n\ + sw a1, (a0)\n" // deep sleepy time for V5F + "li a0, 0xE000ED10\n\ + li a1, 0x80000000\n\ + sw a1, (a0)\n" // self-SYSRST when we are not supposed to be running + ); + return -1; + } - _write(0, s, len); - return len; + return v5f_start_function(); +} +#endif + +WEAK int errno; + +static int __puts_uart( char *s, int len, void *buf ) +{ + (void)buf; + + _write( 0, s, len ); + return len; } -WEAK int printf(const char *format, ...) +WEAK int printf( const char* format, ... ) { - va_list args; - va_start(args, format); - int ret_status = mini_vpprintf(__puts_uart, 0, format, args); - va_end(args); - return ret_status; + va_list args; + va_start( args, format ); + int ret_status = mini_vpprintf(__puts_uart, 0, format, args); + va_end( args ); + return ret_status; } -WEAK int vprintf(const char *format, va_list args) +WEAK int vprintf(const char* format, va_list args) { - return mini_vpprintf(__puts_uart, 0, format, args); + return mini_vpprintf(__puts_uart, 0, format, args); } -WEAK int snprintf(char *buffer, unsigned int buffer_len, const char *format, ...) +WEAK int snprintf( char * buffer, unsigned int buffer_len, const char* format, ... ) { - va_list args; - va_start(args, format); - int ret = mini_vsnprintf(buffer, buffer_len, format, args); - va_end(args); - return ret; + va_list args; + va_start( args, format ); + int ret = mini_vsnprintf( buffer, buffer_len, format, args ); + va_end( args ); + return ret; } -WEAK int sprintf(char *buffer, const char *format, ...) +WEAK int sprintf( char * buffer, const char * format, ... ) { - va_list args; - va_start(args, format); - int ret = mini_vsnprintf(buffer, INT_MAX, format, args); - va_end(args); - return ret; + va_list args; + va_start( args, format ); + int ret = mini_vsnprintf( buffer, INT_MAX, format, args ); + va_end( args ); + return ret; } /* Some stuff from MUSL @@ -174,382 +191,311 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define IS_CODEUNIT(c) ((unsigned)(c)-0xdf80 < 0x80) #define MB_CUR_MAX (CURRENT_UTF8 ? 4 : 1) -typedef void *mbstate_t; +typedef void * mbstate_t; #ifdef UNICODE WEAK size_t wcrtomb(char *restrict s, wchar_t wc, mbstate_t *restrict st) { - if (!s) return 1; - if ((unsigned)wc < 0x80) - { - *s = wc; - return 1; - } - else if (MB_CUR_MAX == 1) - { - if (!IS_CODEUNIT(wc)) - { - errno = 0x02; // EILSEQ - return -1; - } - *s = wc; - return 1; - } - else if ((unsigned)wc < 0x800) - { - *s++ = 0xc0 | (wc >> 6); - *s = 0x80 | (wc & 0x3f); - return 2; - } - else if ((unsigned)wc < 0xd800 || (unsigned)wc - 0xe000 < 0x2000) - { - *s++ = 0xe0 | (wc >> 12); - *s++ = 0x80 | ((wc >> 6) & 0x3f); - *s = 0x80 | (wc & 0x3f); - return 3; - } - else if ((unsigned)wc - 0x10000 < 0x100000) - { - *s++ = 0xf0 | (wc >> 18); - *s++ = 0x80 | ((wc >> 12) & 0x3f); - *s++ = 0x80 | ((wc >> 6) & 0x3f); - *s = 0x80 | (wc & 0x3f); - return 4; - } - errno = 0x02; // EILSEQ; - return -1; + if (!s) return 1; + if ((unsigned)wc < 0x80) { + *s = wc; + return 1; + } else if (MB_CUR_MAX == 1) { + if (!IS_CODEUNIT(wc)) { + errno = 0x02; // EILSEQ + return -1; + } + *s = wc; + return 1; + } else if ((unsigned)wc < 0x800) { + *s++ = 0xc0 | (wc>>6); + *s = 0x80 | (wc&0x3f); + return 2; + } else if ((unsigned)wc < 0xd800 || (unsigned)wc-0xe000 < 0x2000) { + *s++ = 0xe0 | (wc>>12); + *s++ = 0x80 | ((wc>>6)&0x3f); + *s = 0x80 | (wc&0x3f); + return 3; + } else if ((unsigned)wc-0x10000 < 0x100000) { + *s++ = 0xf0 | (wc>>18); + *s++ = 0x80 | ((wc>>12)&0x3f); + *s++ = 0x80 | ((wc>>6)&0x3f); + *s = 0x80 | (wc&0x3f); + return 4; + } + errno = 0x02;//EILSEQ; + return -1; } WEAK int wctomb(char *s, wchar_t wc) { - if (!s) return 0; - return wcrtomb(s, wc, 0); + if (!s) return 0; + return wcrtomb(s, wc, 0); } #endif WEAK size_t strlen(const char *s) { - const char *a = s; - for (; *s; s++) - ; - return s - a; -} -WEAK size_t strnlen(const char *s, size_t n) -{ - const char *p = memchr(s, 0, n); - return p ? (size_t)(p - s) : n; -} -WEAK void *memset(void *dest, int c, size_t n) -{ - unsigned char *s = dest; - for (; n; n--, s++) - *s = c; - return dest; + const char *a = s; + for (; *s; s++); + return s-a; } +WEAK size_t strnlen(const char *s, size_t n) { const char *p = memchr(s, 0, n); return p ? (size_t)(p-s) : n;} +WEAK void *memset(void *dest, int c, size_t n) { unsigned char *s = dest; for (; n; n--, s++) *s = c; return dest; } WEAK char *strcpy(char *d, const char *s) { - char *d0 = d; - for (; (*d = *s); s++, d++) - ; - return d0; + char *d0=d; + for (; (*d=*s); s++, d++); + return d0; } WEAK char *strncpy(char *d, const char *s, size_t n) { - char *d0 = d; - for (; n && (*d = *s); n--, s++, d++) - ; - return d0; + char *d0=d; + for (; n && (*d=*s); n--, s++, d++); + return d0; } WEAK int strcmp(const char *l, const char *r) { - for (; *l == *r && *l; l++, r++) - ; - return *(unsigned char *)l - *(unsigned char *)r; + for (; *l==*r && *l; l++, r++); + return *(unsigned char *)l - *(unsigned char *)r; } WEAK int strncmp(const char *_l, const char *_r, size_t n) { - const unsigned char *l = (void *)_l, *r = (void *)_r; - if (!n--) return 0; - for (; *l && *r && n && *l == *r; l++, r++, n--) - ; - return *l - *r; + const unsigned char *l=(void *)_l, *r=(void *)_r; + if (!n--) return 0; + for (; *l && *r && n && *l == *r ; l++, r++, n--); + return *l - *r; } static char *twobyte_strstr(const unsigned char *h, const unsigned char *n) { - uint16_t nw = n[0] << 8 | n[1], hw = h[0] << 8 | h[1]; - for (h++; *h && hw != nw; hw = hw << 8 | *++h) - ; - return *h ? (char *)h - 1 : 0; + uint16_t nw = n[0]<<8 | n[1], hw = h[0]<<8 | h[1]; + for (h++; *h && hw != nw; hw = hw<<8 | *++h); + return *h ? (char *)h-1 : 0; } static char *threebyte_strstr(const unsigned char *h, const unsigned char *n) { - uint32_t nw = (uint32_t)n[0] << 24 | n[1] << 16 | n[2] << 8; - uint32_t hw = (uint32_t)h[0] << 24 | h[1] << 16 | h[2] << 8; - for (h += 2; *h && hw != nw; hw = (hw | *++h) << 8) - ; - return *h ? (char *)h - 2 : 0; + uint32_t nw = (uint32_t)n[0]<<24 | n[1]<<16 | n[2]<<8; + uint32_t hw = (uint32_t)h[0]<<24 | h[1]<<16 | h[2]<<8; + for (h+=2; *h && hw != nw; hw = (hw|*++h)<<8); + return *h ? (char *)h-2 : 0; } static char *fourbyte_strstr(const unsigned char *h, const unsigned char *n) { - uint32_t nw = (uint32_t)n[0] << 24 | n[1] << 16 | n[2] << 8 | n[3]; - uint32_t hw = (uint32_t)h[0] << 24 | h[1] << 16 | h[2] << 8 | h[3]; - for (h += 3; *h && hw != nw; hw = hw << 8 | *++h) - ; - return *h ? (char *)h - 3 : 0; + uint32_t nw = (uint32_t)n[0]<<24 | n[1]<<16 | n[2]<<8 | n[3]; + uint32_t hw = (uint32_t)h[0]<<24 | h[1]<<16 | h[2]<<8 | h[3]; + for (h+=3; *h && hw != nw; hw = hw<<8 | *++h); + return *h ? (char *)h-3 : 0; } -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a,b) ((a)>(b)?(a):(b)) +#define MIN(a,b) ((a)<(b)?(a):(b)) -#define BITOP(a, b, op) \ - ((a)[(size_t)(b) / (8 * sizeof *(a))] op(size_t) 1 << ((size_t)(b) % (8 * sizeof *(a)))) +#define BITOP(a,b,op) \ + ((a)[(size_t)(b)/(8*sizeof *(a))] op (size_t)1<<((size_t)(b)%(8*sizeof *(a)))) static char *twoway_strstr(const unsigned char *h, const unsigned char *n) { - const unsigned char *z; - size_t l, ip, jp, k, p, ms, p0, mem, mem0; - size_t byteset[32 / sizeof(size_t)] = {0}; - size_t shift[256]; + const unsigned char *z; + size_t l, ip, jp, k, p, ms, p0, mem, mem0; + size_t byteset[32 / sizeof(size_t)] = { 0 }; + size_t shift[256]; - /* Computing length of needle and fill shift table */ - for (l = 0; n[l] && h[l]; l++) - BITOP(byteset, n[l], |=), shift[n[l]] = l + 1; - if (n[l]) return 0; /* hit the end of h */ + /* Computing length of needle and fill shift table */ + for (l=0; n[l] && h[l]; l++) + BITOP(byteset, n[l], |=), shift[n[l]] = l+1; + if (n[l]) return 0; /* hit the end of h */ - /* Compute maximal suffix */ - ip = -1; - jp = 0; - k = p = 1; - while (jp + k < l) - { - if (n[ip + k] == n[jp + k]) - { - if (k == p) - { - jp += p; - k = 1; - } - else - k++; - } - else if (n[ip + k] > n[jp + k]) - { - jp += k; - k = 1; - p = jp - ip; - } - else - { - ip = jp++; - k = p = 1; - } - } - ms = ip; - p0 = p; + /* Compute maximal suffix */ + ip = -1; jp = 0; k = p = 1; + while (jp+k n[jp+k]) { + jp += k; + k = 1; + p = jp - ip; + } else { + ip = jp++; + k = p = 1; + } + } + ms = ip; + p0 = p; - /* And with the opposite comparison */ - ip = -1; - jp = 0; - k = p = 1; - while (jp + k < l) - { - if (n[ip + k] == n[jp + k]) - { - if (k == p) - { - jp += p; - k = 1; - } - else - k++; - } - else if (n[ip + k] < n[jp + k]) - { - jp += k; - k = 1; - p = jp - ip; - } - else - { - ip = jp++; - k = p = 1; - } - } - if (ip + 1 > ms + 1) - ms = ip; - else - p = p0; + /* And with the opposite comparison */ + ip = -1; jp = 0; k = p = 1; + while (jp+k ms+1) ms = ip; + else p = p0; - /* Periodic needle? */ - if (memcmp(n, n + p, ms + 1)) - { - mem0 = 0; - p = MAX(ms, l - ms - 1) + 1; - } - else - mem0 = l - p; - mem = 0; + /* Periodic needle? */ + if (memcmp(n, n+p, ms+1)) { + mem0 = 0; + p = MAX(ms, l-ms-1) + 1; + } else mem0 = l-p; + mem = 0; - /* Initialize incremental end-of-haystack pointer */ - z = h; + /* Initialize incremental end-of-haystack pointer */ + z = h; - /* Search loop */ - for (;;) - { - /* Update incremental end-of-haystack pointer */ - if ((size_t)(z - h) < l) - { - /* Fast estimate for MAX(l,63) */ - size_t grow = l | 63; - const unsigned char *z2 = memchr(z, 0, grow); - if (z2) - { - z = z2; - if ((size_t)(z - h) < l) return 0; - } - else - z += grow; - } + /* Search loop */ + for (;;) { + /* Update incremental end-of-haystack pointer */ + if ((size_t)(z-h) < l) { + /* Fast estimate for MAX(l,63) */ + size_t grow = l | 63; + const unsigned char *z2 = memchr(z, 0, grow); + if (z2) { + z = z2; + if ((size_t)(z-h) < l) return 0; + } else z += grow; + } - /* Check last byte first; advance by shift on mismatch */ - if (BITOP(byteset, h[l - 1], &)) - { - k = l - shift[h[l - 1]]; - if (k) - { - if (k < mem) k = mem; - h += k; - mem = 0; - continue; - } - } - else - { - h += l; - mem = 0; - continue; - } + /* Check last byte first; advance by shift on mismatch */ + if (BITOP(byteset, h[l-1], &)) { + k = l-shift[h[l-1]]; + if (k) { + if (k < mem) k = mem; + h += k; + mem = 0; + continue; + } + } else { + h += l; + mem = 0; + continue; + } - /* Compare right half */ - for (k = MAX(ms + 1, mem); n[k] && n[k] == h[k]; k++) - ; - if (n[k]) - { - h += k - ms; - mem = 0; - continue; - } - /* Compare left half */ - for (k = ms + 1; k > mem && n[k - 1] == h[k - 1]; k--) - ; - if (k <= mem) return (char *)h; - h += p; - mem = mem0; - } + /* Compare right half */ + for (k=MAX(ms+1,mem); n[k] && n[k] == h[k]; k++); + if (n[k]) { + h += k-ms; + mem = 0; + continue; + } + /* Compare left half */ + for (k=ms+1; k>mem && n[k-1] == h[k-1]; k--); + if (k <= mem) return (char *)h; + h += p; + mem = mem0; + } } WEAK char *strchr(const char *s, int c) { - c = (unsigned char)c; - if (!c) return (char *)s + strlen(s); - for (; *s && *(unsigned char *)s != c; s++) - ; - return (char *)s; + c = (unsigned char)c; + do + { + char ts = *s; + if( ts == c ) return (char*)s; + if( !ts ) return 0; + s++; + } while(1); } WEAK char *strstr(const char *h, const char *n) { - /* Return immediately on empty needle */ - if (!n[0]) return (char *)h; + /* Return immediately on empty needle */ + if (!n[0]) return (char *)h; - /* Use faster algorithms for short needles */ - h = strchr(h, *n); - if (!h || !n[1]) return (char *)h; - if (!h[1]) return 0; - if (!n[2]) return twobyte_strstr((void *)h, (void *)n); - if (!h[2]) return 0; - if (!n[3]) return threebyte_strstr((void *)h, (void *)n); - if (!h[3]) return 0; - if (!n[4]) return fourbyte_strstr((void *)h, (void *)n); + /* Use faster algorithms for short needles */ + h = strchr(h, *n); + if (!h || !n[1]) return (char *)h; + if (!h[1]) return 0; + if (!n[2]) return twobyte_strstr((void *)h, (void *)n); + if (!h[2]) return 0; + if (!n[3]) return threebyte_strstr((void *)h, (void *)n); + if (!h[3]) return 0; + if (!n[4]) return fourbyte_strstr((void *)h, (void *)n); - return twoway_strstr((void *)h, (void *)n); + return twoway_strstr((void *)h, (void *)n); } + WEAK void *__memrchr(const void *m, int c, size_t n) { - const unsigned char *s = m; - c = (unsigned char)c; - while (n--) - if (s[n] == c) return (void *)(s + n); - return 0; + const unsigned char *s = m; + c = (unsigned char)c; + while (n--) if (s[n]==c) return (void *)(s+n); + return 0; } WEAK char *strrchr(const char *s, int c) { - return __memrchr(s, c, strlen(s) + 1); + return __memrchr(s, c, strlen(s) + 1); } WEAK void *memcpy(void *dest, const void *src, size_t n) { - unsigned char *d = dest; - const unsigned char *s = src; - for (; n; n--) - *d++ = *s++; - return dest; + unsigned char *d = dest; + const unsigned char *s = src; + for (; n; n--) *d++ = *s++; + return dest; } WEAK int memcmp(const void *vl, const void *vr, size_t n) { - const unsigned char *l = vl, *r = vr; - for (; n && *l == *r; n--, l++, r++) - ; - return n ? *l - *r : 0; + const unsigned char *l=vl, *r=vr; + for (; n && *l == *r; n--, l++, r++); + return n ? *l-*r : 0; } + WEAK void *memmove(void *dest, const void *src, size_t n) { - char *d = dest; - const char *s = src; + char *d = dest; + const char *s = src; - if (d == s) return d; - if ((uintptr_t)s - (uintptr_t)d - n <= -2 * n) return memcpy(d, s, n); + if (d==s) return d; + if ((uintptr_t)s-(uintptr_t)d-n <= -2*n) return memcpy(d, s, n); - if (d < s) - { - for (; n; n--) - *d++ = *s++; - } - else - { - while (n) - n--, d[n] = s[n]; - } + if (d - * + * * Permission granted on 2024-07-13 for optional relicense under MIT license. * https://github.com/mludvig/mini-printf/issues/16 * @@ -570,300 +516,267 @@ WEAK int puts(const char *s) #define mini_strlen strlen -static int -mini_itoa(long value, unsigned int radix, int uppercase, int unsig, - char *buffer) +int mini_itoa(long value, unsigned int radix, int uppercase, int unsig, char *buffer) { - char *pbuffer = buffer; - int negative = 0; - int i, len; + char *pbuffer = buffer; + int negative = 0; + int i, len; - /* No support for unusual radixes. */ - if (radix > 16) - return 0; + /* No support for unusual radixes. */ + if (radix > 16) + return 0; - if (value < 0 && !unsig) - { - negative = 1; - value = -value; - } + if (value < 0 && !unsig) { + negative = 1; + value = -value; + } - /* This builds the string back to front ... */ - do - { - int digit = value % radix; - *(pbuffer++) = (digit < 10 ? '0' + digit : (uppercase ? 'A' : 'a') + digit - 10); - value /= radix; - } while (value > 0); + /* This builds the string back to front ... */ + do { + int digit = value % radix; + *(pbuffer++) = (digit < 10 ? '0' + digit : (uppercase ? 'A' : 'a') + digit - 10); + value /= radix; + } while (value > 0); - if (negative) - *(pbuffer++) = '-'; + if (negative) + *(pbuffer++) = '-'; - *(pbuffer) = '\0'; + *(pbuffer) = '\0'; - /* ... now we reverse it (could do it recursively but will - * conserve the stack space) */ - len = (pbuffer - buffer); - for (i = 0; i < len / 2; i++) - { - char j = buffer[i]; - buffer[i] = buffer[len - i - 1]; - buffer[len - i - 1] = j; - } + /* ... now we reverse it (could do it recursively but will + * conserve the stack space) */ + len = (pbuffer - buffer); + for (i = 0; i < len / 2; i++) { + char j = buffer[i]; + buffer[i] = buffer[len-i-1]; + buffer[len-i-1] = j; + } - return len; + return len; } static int -mini_pad(char *ptr, int len, char pad_char, int pad_to, char *buffer) +mini_pad(char* ptr, int len, char pad_char, int pad_to, char *buffer) { - int i; - int overflow = 0; - char *pbuffer = buffer; - if (pad_to == 0) pad_to = len; - if (len > pad_to) - { - len = pad_to; - overflow = 1; - } - for (i = pad_to - len; i > 0; i--) - { - *(pbuffer++) = pad_char; - } - for (i = len; i > 0; i--) - { - *(pbuffer++) = *(ptr++); - } - len = pbuffer - buffer; - if (overflow) - { - for (i = 0; i < 3 && pbuffer > buffer; i++) - { - *(pbuffer-- - 1) = '*'; - } - } - return len; + int i; + int overflow = 0; + char * pbuffer = buffer; + if(pad_to == 0) pad_to = len; + if(len > pad_to) { + len = pad_to; + overflow = 1; + } + for(i = pad_to - len; i > 0; i --) { + *(pbuffer++) = pad_char; + } + for(i = len; i > 0; i --) { + *(pbuffer++) = *(ptr++); + } + len = pbuffer - buffer; + if(overflow) { + for (i = 0; i < 3 && pbuffer > buffer; i ++) { + *(pbuffer-- - 1) = '*'; + } + } + return len; } -struct mini_buff -{ - char *buffer, *pbuffer; - unsigned int buffer_len; +struct mini_buff { + char *buffer, *pbuffer; + unsigned int buffer_len; }; static int _puts(char *s, int len, void *buf) { - if (!buf) return len; - struct mini_buff *b = buf; - char *p0 = b->buffer; - int i; - /* Copy to buffer */ - for (i = 0; i < len; i++) - { - if (b->pbuffer == b->buffer + b->buffer_len - 1) - { - break; - } - *(b->pbuffer++) = s[i]; - } - *(b->pbuffer) = 0; - return b->pbuffer - p0; + if(!buf) return len; + struct mini_buff *b = buf; + char * p0 = b->buffer; + int i; + /* Copy to buffer */ + for (i = 0; i < len; i++) { + if(b->pbuffer == b->buffer + b->buffer_len - 1) { + break; + } + *(b->pbuffer ++) = s[i]; + } + *(b->pbuffer) = 0; + return b->pbuffer - p0; } #ifdef MINI_PRINTF_ENABLE_OBJECTS -static int (*mini_handler)(void *data, void *obj, int ch, int lhint, char **bf) = 0; -static void (*mini_handler_freeor)(void *data, void *) = 0; -static void *mini_handler_data = 0; +static int (*mini_handler) (void* data, void* obj, int ch, int lhint, char** bf) = 0; +static void (*mini_handler_freeor)(void* data, void*) = 0; +static void * mini_handler_data = 0; -void mini_printf_set_handler( - void *data, - int (*handler)(void *data, void *obj, int ch, int len_hint, char **buf), - void (*freeor)(void *data, void *buf)) +void mini_printf_set_handler( + void* data, + int (*handler)(void* data, void* obj, int ch, int len_hint, char** buf), + void (*freeor)(void* data, void* buf)) { - mini_handler = handler; - mini_handler_freeor = freeor; - mini_handler_data = data; + mini_handler = handler; + mini_handler_freeor = freeor; + mini_handler_data = data; } #endif -int mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va) +int +mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va) { - struct mini_buff b; - b.buffer = buffer; - b.pbuffer = buffer; - b.buffer_len = buffer_len; - if (buffer_len == 0) buffer = (void *)0; - int n = mini_vpprintf(_puts, (buffer != (void *)0) ? &b : (void *)0, fmt, va); - if (buffer == (void *)0) - { - return n; - } - return b.pbuffer - b.buffer; + struct mini_buff b; + b.buffer = buffer; + b.pbuffer = buffer; + b.buffer_len = buffer_len; + if(buffer_len == 0) buffer = (void*) 0; + int n = mini_vpprintf(_puts, (buffer != (void*)0)?&b:(void*)0, fmt, va); + if(buffer == (void*) 0) { + return n; + } + return b.pbuffer - b.buffer; } -int mini_vpprintf(int (*puts)(char *s, int len, void *buf), void *buf, const char *fmt, va_list va) +int +mini_vpprintf(int (*puts)(char* s, int len, void* buf), void* buf, const char *fmt, va_list va) { - char bf[24]; - char bf2[24]; - char ch; + char bf[24]; + char bf2[24]; + char ch; #ifdef MINI_PRINTF_ENABLE_OBJECTS - void *obj; + void* obj; #endif - if (puts == (void *)0) - { - /* run puts in counting mode. */ - puts = _puts; - buf = (void *)0; - } - int n = 0; - while ((ch = *(fmt++))) - { - int len; - if (ch != '%') - { - len = 1; - len = puts(&ch, len, buf); - } - else - { - char pad_char = ' '; - int pad_to = 0; - char l = 0; - char *ptr; + if(puts == (void*)0) { + /* run puts in counting mode. */ + puts = _puts; buf = (void*)0; + } + int n = 0; + while ((ch=*(fmt++))) { + int len; + if (ch!='%') { + len = 1; + len = puts(&ch, len, buf); + } else { + char pad_char = ' '; + int pad_to = 0; + char l = 0; + char *ptr; - ch = *(fmt++); + ch=*(fmt++); - /* Zero padding requested */ - if (ch == '0') pad_char = '0'; - while (ch >= '0' && ch <= '9') - { - pad_to = pad_to * 10 + (ch - '0'); - ch = *(fmt++); - } - if (pad_to > (signed int)sizeof(bf)) - { - pad_to = sizeof(bf); - } - if (ch == 'l') - { - l = 1; - ch = *(fmt++); - } + /* Zero padding requested */ + if (ch == '0') pad_char = '0'; + while (ch >= '0' && ch <= '9') { + pad_to = pad_to * 10 + (ch - '0'); + ch=*(fmt++); + } + if(pad_to > (signed int) sizeof(bf)) { + pad_to = sizeof(bf); + } + if (ch == 'l') { + l = 1; + ch=*(fmt++); + } - switch (ch) - { - case 0: - goto end; - case 'u': - case 'd': - if (l) - { - len = mini_itoa(va_arg(va, unsigned long), 10, 0, (ch == 'u'), bf2); - } - else - { - if (ch == 'u') - { - len = mini_itoa((unsigned long)va_arg(va, unsigned int), 10, 0, 1, bf2); - } - else - { - len = mini_itoa((long)va_arg(va, int), 10, 0, 0, bf2); - } - } - len = mini_pad(bf2, len, pad_char, pad_to, bf); - len = puts(bf, len, buf); - break; + switch (ch) { + case 0: + goto end; + case 'u': + case 'd': + if(l) { + len = mini_itoa(va_arg(va, unsigned long), 10, 0, (ch=='u'), bf2); + } else { + if(ch == 'u') { + len = mini_itoa((unsigned long) va_arg(va, unsigned int), 10, 0, 1, bf2); + } else { + len = mini_itoa((long) va_arg(va, int), 10, 0, 0, bf2); + } + } + len = mini_pad(bf2, len, pad_char, pad_to, bf); + len = puts(bf, len, buf); + break; - case 'x': - case 'X': - if (l) - { - len = mini_itoa(va_arg(va, unsigned long), 16, (ch == 'X'), 1, bf2); - } - else - { - len = mini_itoa((unsigned long)va_arg(va, unsigned int), 16, (ch == 'X'), 1, bf2); - } - len = mini_pad(bf2, len, pad_char, pad_to, bf); - len = puts(bf, len, buf); - break; + case 'x': + case 'X': + if(l) { + len = mini_itoa(va_arg(va, unsigned long), 16, (ch=='X'), 1, bf2); + } else { + len = mini_itoa((unsigned long) va_arg(va, unsigned int), 16, (ch=='X'), 1, bf2); + } + len = mini_pad(bf2, len, pad_char, pad_to, bf); + len = puts(bf, len, buf); + break; - case 'c': - ch = (char)(va_arg(va, int)); - len = mini_pad(&ch, 1, pad_char, pad_to, bf); - len = puts(bf, len, buf); - break; + case 'c' : + ch = (char)(va_arg(va, int)); + len = mini_pad(&ch, 1, pad_char, pad_to, bf); + len = puts(bf, len, buf); + break; - case 's': - ptr = va_arg(va, char *); - len = mini_strlen(ptr); - if (pad_to > 0) - { - len = mini_pad(ptr, len, pad_char, pad_to, bf); - len = puts(bf, len, buf); - } - else - { - len = puts(ptr, len, buf); - } - break; + case 's' : + ptr = va_arg(va, char*); + len = mini_strlen(ptr); + if (pad_to > 0) { + len = mini_pad(ptr, len, pad_char, pad_to, bf); + len = puts(bf, len, buf); + } else { + len = puts(ptr, len, buf); + } + break; #ifdef MINI_PRINTF_ENABLE_OBJECTS - case 'O': /* Object by content (e.g. str) */ - case 'R': /* Object by representation (e.g. repr)*/ - obj = va_arg(va, void *); - len = mini_handler(mini_handler_data, obj, ch, pad_to, &ptr); - if (pad_to > 0) - { - len = mini_pad(ptr, len, pad_char, pad_to, bf); - len = puts(bf, len, buf); - } - else - { - len = puts(ptr, len, buf); - } - mini_handler_freeor(mini_handler_data, ptr); - break; + case 'O' : /* Object by content (e.g. str) */ + case 'R' : /* Object by representation (e.g. repr)*/ + obj = va_arg(va, void*); + len = mini_handler(mini_handler_data, obj, ch, pad_to, &ptr); + if (pad_to > 0) { + len = mini_pad(ptr, len, pad_char, pad_to, bf); + len = puts(bf, len, buf); + } else { + len = puts(ptr, len, buf); + } + mini_handler_freeor(mini_handler_data, ptr); + break; #endif - default: - len = 1; - len = puts(&ch, len, buf); - break; - } - } - n = n + len; - } + default: + len = 1; + len = puts(&ch, len, buf); + break; + } + } + n = n + len; + } end: - return n; + return n; } -int mini_snprintf(char *buffer, unsigned int buffer_len, const char *fmt, ...) + +int +mini_snprintf(char* buffer, unsigned int buffer_len, const char *fmt, ...) { - int ret; - va_list va; - va_start(va, fmt); - ret = mini_vsnprintf(buffer, buffer_len, fmt, va); - va_end(va); + int ret; + va_list va; + va_start(va, fmt); + ret = mini_vsnprintf(buffer, buffer_len, fmt, va); + va_end(va); - return ret; + return ret; } -int mini_pprintf(int (*puts)(char *s, int len, void *buf), void *buf, const char *fmt, ...) +int +mini_pprintf(int (*puts)(char*s, int len, void* buf), void* buf, const char *fmt, ...) { - int ret; - va_list va; - va_start(va, fmt); - ret = mini_vpprintf(puts, buf, fmt, va); - va_end(va); + int ret; + va_list va; + va_start(va, fmt); + ret = mini_vpprintf(puts, buf, fmt, va); + va_end(va); - return ret; + return ret; } + /* - C version of CH32V003 Startup .s file from WCH - This file is public domain where possible or the following where not: - Copyright 2023 Charles Lohr, under the MIT-x11 or NewBSD licenses, you choose. + C version of CH32V003 Startup .s file from WCH + This file is public domain where possible or the following where not: + Copyright 2023 Charles Lohr, under the MIT-x11 or NewBSD licenses, you choose. */ #ifdef CPLUSPLUS @@ -871,74 +784,70 @@ int mini_pprintf(int (*puts)(char *s, int len, void *buf), void *buf, const char void __libc_init_array(void); #endif -int main() __attribute__((used)); -void SystemInit(void) __attribute__((used)); +int main() __attribute__((used)); +void SystemInit( void ) __attribute__((used)); -extern uint32_t *_sbss; -extern uint32_t *_ebss; -extern uint32_t *_data_lma; -extern uint32_t *_data_vma; -extern uint32_t *_edata; +extern uint32_t * _sbss; +extern uint32_t * _ebss; +extern uint32_t * _data_lma; +extern uint32_t * _data_vma; +extern uint32_t * _edata; #if FUNCONF_DEBUG_HARDFAULT #if FUNCONF_USE_DEBUGPRINTF -static void PrintN(uint32_t n) +void PrintHex( uint32_t n ) { - while ((*DMDATA0) & 0x80) - ; - // Write out character. - *DMDATA0 = 0x78302088; //" 0x" - int shift; - for (shift = 28; shift >= 0; shift -= 4) - { - while ((*DMDATA0) & 0x80) - ; - int s = (n >> shift) & 0xf; - s += (s < 10) ? '0' : ('a' - 10); - *DMDATA0 = 0x85 | (s << 8); //" 0x" - } + while( (*DMDATA0) & 0x80 ); + // Write out character. + *DMDATA0 = 0x78302088; //" 0x" + int shift; + for( shift = 28; shift >= 0; shift -= 4 ) + { + while( (*DMDATA0) & 0x80 ); + int s = (n>>shift) & 0xf; + s += ( s < 10 ) ? '0' : ('a' - 10); + *DMDATA0 = 0x85 | (s<<8); //" 0x" + } } #elif FUNCONF_USE_UARTPRINTF -static void PrintN(uint32_t n) +void PrintHex( uint32_t n ) { - putchar(' '); - putchar('0'); - putchar('x'); - int shift; - for (shift = 28; shift >= 0; shift -= 4) - { - int s = (n >> shift) & 0xf; - s += (s < 10) ? '0' : ('a' - 10); - putchar(s); - } + putchar( ' ' ); + putchar( '0' ); + putchar( 'x' ); + int shift; + for( shift = 28; shift >= 0; shift -= 4 ) + { + int s = (n>>shift) & 0xf; + s += ( s < 10 ) ? '0' : ('a' - 10); + putchar( s ); + } } #endif #endif // If you don't override a specific handler, it will just spin forever. -void DefaultIRQHandler(void) +void DefaultIRQHandler( void ) { -#if FUNCONF_DEBUG_HARDFAULT && (FUNCONF_USE_DEBUGPRINTF || FUNCONF_USE_UARTPRINTF) - // This is kind of like a crash handler. - // printf( "DEAD MSTATUS:%08x MTVAL:%08x MCAUSE:%08x MEPC:%08x\n", (int)__get_MSTATUS(), (int)__get_MTVAL(), (int)__get_MCAUSE(), (int)__get_MEPC() ); - PrintN(__get_MEPC()); // "addr2line -e debugprintfdemo.elf 0x000007e6" ---> debugprintfdemo.c:45 - PrintN(__get_MSTATUS()); - PrintN(__get_MTVAL()); - PrintN(__get_MCAUSE()); +#if FUNCONF_DEBUG_HARDFAULT && ( FUNCONF_USE_DEBUGPRINTF || FUNCONF_USE_UARTPRINTF || FUNCONF_USE_USBPRINTF ) + //This is kind of like a crash handler. + //printf( "DEAD MSTATUS:%08x MTVAL:%08x MCAUSE:%08x MEPC:%08x\n", (int)__get_MSTATUS(), (int)__get_MTVAL(), (int)__get_MCAUSE(), (int)__get_MEPC() ); + PrintHex( __get_MEPC() ); // "addr2line -e debugprintfdemo.elf 0x000007e6" ---> debugprintfdemo.c:45 + PrintHex( __get_MSTATUS() ); + PrintHex( __get_MTVAL() ); + PrintHex( __get_MCAUSE() ); #if FUNCONF_USE_DEBUGPRINTF - while ((*DMDATA0) & 0x80) - ; - *DMDATA0 = 0x0a85; - while ((*DMDATA0) & 0x80) - ; - *DMDATA0 = 0xaaaaaa83; + while( (*DMDATA0) & 0x80 ); + *DMDATA0 = 0x0a85; + while( (*DMDATA0) & 0x80 ); + *DMDATA0 = 0xaaaaaa83; #elif FUNCONF_USE_UARTPRINTF - putchar('\n'); + putchar( '\n' ); #endif #endif - // printf( "DEAD MSTATUS:%08x MTVAL:%08x MCAUSE:%08x MEPC:%08x\n", (int)__get_MSTATUS(), (int)__get_MTVAL(), (int)__get_MCAUSE(), (int)__get_MEPC() ); - // Infinite Loop - asm volatile("1: j 1b"); + //printf( "DEAD MSTATUS:%08x MTVAL:%08x MCAUSE:%08x MEPC:%08x\n", (int)__get_MSTATUS(), (int)__get_MTVAL(), (int)__get_MCAUSE(), (int)__get_MEPC() ); + // Infinite Loop + asm volatile( "1: j 1b" ); } // This makes it so that all of the interrupt handlers just alias to @@ -952,184 +861,292 @@ void DefaultIRQHandler(void) * The sys clock is switched to HSI. * Clears the CSSF flag in RCC->INTR */ -void NMI_RCC_CSS_IRQHandler(void) +void NMI_RCC_CSS_IRQHandler( void ) { - RCC->INTR |= RCC_CSSC; // clear the clock security int flag + RCC->INTR |= RCC_CSSC; // clear the clock security int flag } -void NMI_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("NMI_RCC_CSS_IRQHandler"))) __attribute__((used)); +void NMI_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("NMI_RCC_CSS_IRQHandler"))) __attribute__((used)); #else -void NMI_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); +void NMI_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); #endif -void HardFault_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void Ecall_M_Mode_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void Ecall_U_Mode_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void Break_Point_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void SysTick_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void SW_Handler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void WWDG_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void PVD_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TAMPER_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void RTC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void FLASH_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void RCC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI7_0_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void AWU_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI0_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI3_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI4_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel3_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel4_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel5_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel6_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel7_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void ADC1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void ADC1_2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBFS_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBFSWakeUp_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USB_HP_CAN1_TX_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USB_LP_CAN1_RX0_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void CAN1_RX1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void CAN1_SCE_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI9_5_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM1_BRK_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM1_UP_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM1_TRG_COM_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM1_CC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM3_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM4_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void I2C1_EV_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void I2C1_ER_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void SPI1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void I2C2_EV_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void I2C2_ER_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void SPI2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USART1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USART2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USART3_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI15_10_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void RTCAlarm_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBWakeUp_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void ETH_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void ETHWakeUp_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void OSC32KCal_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void OSCWakeUp_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA1_Channel8_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void BB_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void LLE_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); +void HardFault_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void Ecall_M_Mode_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void Ecall_U_Mode_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void Break_Point_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SysTick_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SW_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void WWDG_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void PVD_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TAMPER_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void RTC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void FLASH_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void RCC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI7_0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void AWU_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel5_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel6_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel7_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void ADC1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void ADC1_2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBFS_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBFSWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USB_HP_CAN1_TX_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USB_LP_CAN1_RX0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN1_RX1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN1_SCE_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI9_5_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM1_BRK_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM1_UP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM1_TRG_COM_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM1_CC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C1_EV_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C1_ER_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SPI1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C2_EV_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C2_ER_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SPI2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI15_10_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void RTCAlarm_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void ETH_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void ETHWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void OSC32KCal_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void OSCWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA1_Channel8_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void BB_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LLE_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); // This appears to be masked to USBHD -void TIM8_BRK_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM8_UP_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM8_TRG_COM_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM8_CC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void RNG_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void FSMC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void SDIO_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM5_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void SPI3_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void UART4_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void UART5_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM6_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM7_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel2_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel3_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel4_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel5_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void OTG_FS_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBHSWakeUp_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBHS_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DVP_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void UART6_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void UART7_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void UART8_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM9_BRK_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM9_UP_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM9_TRG_COM_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM9_CC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM10_BRK_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM10_UP_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM10_TRG_COM_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM10_CC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel6_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel7_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel8_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel9_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel10_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void DMA2_Channel11_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void CAN2_TX_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void CAN2_RX0_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void CAN2_RX1_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void CAN2_SCE_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI15_8_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void EXTI25_16_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USART4_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBFS_WakeUp_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void PIOC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void OPA_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBPD_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void USBPD_WKUP_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM2_CC_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM2_TRG_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); -void TIM2_BRK_IRQHandler(void) __attribute__((section(".text.vector_handler"))) __attribute((weak, alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM8_BRK_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM8_UP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM8_TRG_COM_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM8_CC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void RNG_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void FSMC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SDIO_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM5_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SPI3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART5_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM6_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM7_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel5_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void OTG_FS_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBHSWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBHS_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DVP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART6_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART7_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART8_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM9_BRK_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM9_UP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM9_TRG_COM_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM9_CC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM10_BRK_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM10_UP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM10_TRG_COM_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM10_CC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel6_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel7_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel8_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel9_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel10_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DMA2_Channel11_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN2_TX_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN2_RX0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN2_RX1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN2_SCE_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI15_8_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void EXTI25_16_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBFS_WakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void PIOC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void OPA_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBPD_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBPD_WKUP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM2_CC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM2_TRG_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM2_BRK_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LPTIMWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LPTIM_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CMPWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +// CH5xx +void TMR0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void GPIOA_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void GPIOB_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SPI0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USB_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USB2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TMR1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TMR2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void ADC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void PWMX_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TMR3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UART3_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void WDOG_BAT_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void NFC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USB2_DEVICE_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USB2_HOST_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LED_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +// CH32H41x +void IPC_CH0_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void IPC_CH1_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void IPC_CH2_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void IPC_CH3_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void HSEM_Handler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SPI4_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBPDWakeUp_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN1_TX_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN1_RX0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBSS_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBSS_LINK_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBHSWakeup_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USBSSWakeup_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C3_EV_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C3_ER_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C4_EV_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I2C4_ER_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void QSPI1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SERDES_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM9_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM10_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM11_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void TIM12_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void FMC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SDMMC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LPTIM1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LPTIM2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART5_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART6_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART7_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART8_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I3C_EV_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I3C_ER_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void ECDC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SAI_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LTDC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void GPHA_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DFSDM0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void DFSDM1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SWPMI_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void QSPI2_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void SWPMI_WKUP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN3_SCE_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN3_TX_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN3_RX0_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void CAN3_RX1_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LPTIM2_WKUP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void LPTIM1_WKUP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void I3C_WKUP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void HSADC_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void UHSIF_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); +void USART_WKUP_IRQHandler( void ) __attribute__((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used)); -void InterruptVector() __attribute__((naked)) __attribute((section(".init"))) __attribute((weak, alias("InterruptVectorDefault"))) __attribute((naked)); -void InterruptVectorDefault() __attribute__((naked)) __attribute((section(".init"))) __attribute((naked)); -void handle_reset(void) __attribute__((section(".text.handle_reset"))); +void handle_reset( void ) __attribute__((section(".text.handle_reset"))); -void InterruptVectorDefault(void) -{ -#if !defined(FUNCONF_TINYVECTOR) || !FUNCONF_TINYVECTOR - asm volatile(DEFAULT_INTERRUPT_VECTOR_CONTENTS); +#if FUNCONF_ISR_IN_RAM + void Init() __attribute__((naked)) __attribute((section(".init"))) __attribute((weak,alias("InitDefault"))) __attribute((naked)); + void InitDefault() __attribute__((naked)) __attribute((section(".init"))) __attribute((naked)); + void InitDefault( void ) + { + asm volatile( "\n\ + .align 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .option pop;\n" ); + } + + void InterruptVector() __attribute__((naked)) __attribute((section(VECTOR_HANDLER_SECTION))) __attribute((weak,alias("InterruptVectorDefault"))) __attribute((naked)); + void InterruptVectorDefault() __attribute__((naked)) __attribute((section(VECTOR_HANDLER_SECTION))) __attribute((naked)); + void InterruptVectorDefault( void ) + { + asm volatile( DEFAULT_INTERRUPT_VECTOR_CONTENTS ); + } #else - asm volatile("\n\ - .align 2\n\ - .option push;\n\ - .option norvc;\n\ - j handle_reset\n\ - .option pop;\n"); + void InterruptVector() __attribute__((naked)) __attribute((section(".init"))) __attribute((weak,alias("InterruptVectorDefault"))) __attribute((naked)); + void InterruptVectorDefault() __attribute__((naked)) __attribute((section(".init"))) __attribute((naked)); + void InterruptVectorDefault( void ) + { + #if !defined(FUNCONF_TINYVECTOR) || !FUNCONF_TINYVECTOR + asm volatile( DEFAULT_INTERRUPT_VECTOR_CONTENTS ); + #else + asm volatile( "\n\ + .align 2\n\ + .option push;\n\ + .option norvc;\n\ + j handle_reset\n\ + .option pop;\n" ); + #endif + } #endif -} -#if defined(CH32V003) || defined(CH32X03x) -void handle_reset(void) +#if FUNCONF_ISR_IN_RAM + #define VECTOR_HANDLER_SECTION ".data.vector_handler" +#else + #define VECTOR_HANDLER_SECTION ".text.vector_handler" +#endif + + + +#if defined( CH32V003 ) || defined( CH32X03x ) || defined(CH32V00x) + +void handle_reset( void ) { - asm volatile("\n\ + asm volatile( "\n\ .option push\n\ .option norelax\n\ la gp, __global_pointer$\n\ .option pop\n\ la sp, _eusrstack\n" #if __GNUC__ > 10 - ".option arch, +zicsr\n" +".option arch, +zicsr\n" #endif - // Setup the interrupt vector, processor status and INTSYSCR. + // Setup the interrupt vector, processor status and INTSYSCR. -#if FUNCONF_ENABLE_HPE // Enabled nested and hardware (HPE) stack, since it's really good on the x035. - " li t0, 0x88\n\ +#if FUNCONF_ENABLE_HPE // Enabled nested and hardware (HPE) stack, since it's really good on the x035. +" li t0, 0x1888\n\ csrs mstatus, t0\n" - " li t0, 0x0b\n\ +" li t0, 0x0b\n\ csrw 0x804, t0\n" #else - " li a0, 0x80\n\ +" li a0, 0x1880\n\ csrw mstatus, a0\n" #endif - " li a3, 0x3\n\ +" li a3, 0x3\n\ la a0, InterruptVector\n\ or a0, a0, a3\n\ - csrw mtvec, a0\n" - : : : "a0", "a3", "memory"); + csrw mtvec, a0\n" + : : : "a0", "a3", "memory"); - // Careful: Use registers to prevent overwriting of self-data. - // This clears out BSS. - asm volatile( - " la a0, _sbss\n\ + // Careful: Use registers to prevent overwriting of self-data. + // This clears out BSS. +asm volatile( +" la a0, _sbss\n\ la a1, _ebss\n\ li a2, 0\n\ bge a0, a1, 2f\n\ @@ -1137,8 +1154,8 @@ void handle_reset(void) addi a0, a0, 4\n\ blt a0, a1, 1b\n\ 2:" - // This loads DATA from FLASH to RAM. - " la a0, _data_lma\n\ + // This loads DATA from FLASH to RAM. +" la a0, _data_lma\n\ la a1, _data_vma\n\ la a2, _edata\n\ 1: beq a1, a2, 2f\n\ @@ -1149,54 +1166,67 @@ void handle_reset(void) bne a1, a2, 1b\n\ 2:\n" #ifdef CPLUSPLUS - // Call __libc_init_array function - " call %0 \n\t" - : : "i"(__libc_init_array) - : "a0", "a1", "a2", "a3", "a4", "a5", "t0", "t1", "t2", "memory" + // Call __libc_init_array function +" call %0 \n\t" +: : "i" (__libc_init_array) +: "a0", "a1", "a2", "a3", "a4", "a5", "t0", "t1", "t2", "memory" #else - : : : "a0", "a1", "a2", "a3", "memory" +: : : "a0", "a1", "a2", "a3", "memory" #endif - ); +); -#if defined(FUNCONF_SYSTICK_USE_HCLK) && FUNCONF_SYSTICK_USE_HCLK - SysTick->CTLR = 5; +#if defined( FUNCONF_SYSTICK_USE_HCLK ) && FUNCONF_SYSTICK_USE_HCLK + SysTick->CTLR = 5; #else - SysTick->CTLR = 1; + SysTick->CTLR = 1; #endif - // set mepc to be main as the root app. - asm volatile( - " csrw mepc, %[main]\n" - " mret\n" : : [main] "r"(main)); + // set mepc to be main as the root app. +asm volatile( +" csrw mepc, %[main]\n" +" mret\n" : : [main]"r"(main) ); } -#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) +#elif defined(CH32V10x) || defined(CH32V20x) || defined(CH32V30x) || defined(CH32L103) || defined(CH5xx) -void handle_reset(void) +void handle_reset( void ) { - asm volatile("\n\ + asm volatile( "\n\ .option push\n\ .option norelax\n\ la gp, __global_pointer$\n\ .option pop\n\ la sp, _eusrstack\n" #if __GNUC__ > 10 - ".option arch, +zicsr\n" + ".option arch, +zicsr\n" #endif - ); + ); - // Careful: Use registers to prevent overwriting of self-data. - // This clears out BSS. - asm volatile( - " la a0, _sbss\n\ + // Careful: Use registers to prevent overwriting of self-data. + // This clears out BSS. + asm volatile( +" la a0, _sbss\n\ la a1, _ebss\n\ bgeu a0, a1, 2f\n\ 1: sw zero, 0(a0)\n\ addi a0, a0, 4\n\ bltu a0, a1, 1b\n\ -2:" - // This loads DATA from FLASH to RAM. - " la a0, _data_lma\n\ +2:\n" +#ifdef CH5xx + /* Load highcode code section from FLASH to HIGHRAM */ +" la a0, _highcode_lma\n\ + la a1, _highcode_vma_start\n\ + la a2, _highcode_vma_end\n\ + bgeu a1, a2, 2f\n\ +1: lw t0, (a0)\n\ + sw t0, (a1)\n\ + addi a0, a0, 4\n\ + addi a1, a1, 4\n\ + bltu a1, a2, 1b\n\ +2:\n" +#endif + // This loads DATA from FLASH to RAM. +" la a0, _data_lma\n\ la a1, _data_vma\n\ la a2, _edata\n\ beq a1, a2, 2f\n\ @@ -1207,231 +1237,458 @@ void handle_reset(void) bltu a1, a2, 1b\n\ 2:\n" #ifdef CPLUSPLUS - // Call __libc_init_array function - " call %0 \n\t" - : : "i"(__libc_init_array) + // Call __libc_init_array function +" call %0 \n\t" +: : "i" (__libc_init_array) #else - : : +: : #endif - : "a0", "a1", "a2", "a3", "memory"); +: "a0", "a1", "a2", "a3", "memory" +); - // Setup the interrupt vector, processor status and INTSYSCR. - asm volatile( - " li t0, 0x1f\n\ + // Setup the interrupt vector, processor status and INTSYSCR. + asm volatile( +" li t0, 0x1f\n\ csrw 0xbc0, t0\n" -#if defined(CH32V30x) && !defined(DISABLED_FLOAT) - " li t0, 0x6088\n\ +#if defined(CH32V30x) && !defined( DISABLED_FLOAT ) +" li t0, 0x7888\n\ csrs mstatus, t0\n" #else - " li t0, 0x88\n\ +" li t0, 0x1888\n\ csrs mstatus, t0\n" #endif -#if FUNCONF_ENABLE_HPE // Enabled nested and hardware (HPE) stack, since it's really good on the x035. - " li t0, 0x0b\n\ +#if FUNCONF_ENABLE_HPE // Enabled nested and hardware (HPE) stack, since it's really good on the x035. +" li t0, 0x0b\n\ csrw 0x804, t0\n" #endif - " la t0, InterruptVector\n\ +" la t0, InterruptVector\n\ ori t0, t0, 3\n\ csrw mtvec, t0\n" - : : [InterruptVector] "r"(InterruptVector) : "t0", "memory"); + : : [InterruptVector]"r"(InterruptVector) : "t0", "memory" + ); -#if defined(FUNCONF_SYSTICK_USE_HCLK) && FUNCONF_SYSTICK_USE_HCLK && !defined(CH32V10x) - SysTick->CTLR = 5; +#if defined( FUNCONF_SYSTICK_USE_HCLK ) && FUNCONF_SYSTICK_USE_HCLK && !defined(CH32V10x) + SysTick->CTLR = 5; #else - SysTick->CTLR = 1; + SysTick->CTLR = 1; #endif - // set mepc to be main as the root app. - asm volatile( - " csrw mepc, %[main]\n" - " mret\n" : : [main] "r"(main)); + // set mepc to be main as the root app. + asm volatile( +" csrw mepc, %[main]\n" +" mret\n" : : [main]"r"(main) ); } +#elif defined(CH32H41x) + +void __ITCM setup_cache( void ) { + asm volatile( +" beqz a7, 3f\n" + "li a0, 0x1000003\n\ + csrw 0xbc2, a0\n" + "li a0, 0x0\n\ + csrw 0xBD0, a0\n" // supposed to clear cache, clearly not doing it + "li a0, 0x1000001\n\ + csrw 0xbc2, a0\n" +"3:" + ); +} + +void handle_reset( void ) +{ + asm volatile( "\n\ +.option push\n\ +.option norelax\n\ + la gp, __global_pointer$\n\ +.option pop\n\ + csrr a7, mhartid\n\ + bnez a7, 5f\n\ + la sp, _v3f_stack\n\ + j 3f\n\ +5: la sp, _v5f_stack\n" +"3:\n" + ); + + asm volatile( +#if __GNUC__ > 10 +" .option arch, +zicsr\n" +#endif + ); + + // Careful: Use registers to prevent overwriting of self-data. + // This clears out BSS. + asm volatile( + /* v3f already cleared BSS */ +" bnez a7, 5f\n\ + la a0, _sbss\n\ + la a1, _ebss\n\ + bgeu a0, a1, 2f\n\ +1: sw zero, 0(a0)\n\ + addi a0, a0, 4\n\ + bltu a0, a1, 1b\n\ +2:\n" + + // Load ITCM code from FLASH to ITCM. +" la a0, _itcm_lma\n\ + la a1, _itcm_vma_start\n\ + la a2, _itcm_vma_end\n\ + bgeu a1, a2, 2f\n\ +1: lw t0, (a0)\n\ + sw t0, (a1)\n\ + addi a0, a0, 4\n\ + addi a1, a1, 4\n\ + bltu a1, a2, 1b\n\ +2:\n" + // Load DTCM code from FLASH to DTCM. +" la a0, _dtcm_lma\n\ + la a1, _dtcm_vma_start\n\ + la a2, _dtcm_vma_end\n\ + bgeu a1, a2, 2f\n\ +1: lw t0, (a0)\n\ + sw t0, (a1)\n\ + addi a0, a0, 4\n\ + addi a1, a1, 4\n\ + bltu a1, a2, 1b\n\ +2:\n" + // This loads DATA from FLASH to RAM. +" la a0, _data_lma\n\ + la a1, _data_vma\n\ + la a2, _edata\n\ + beq a1, a2, 2f\n\ +1: lw t0, 0(a0)\n\ + sw t0, 0(a1)\n\ + addi a0, a0, 4\n\ + addi a1, a1, 4\n\ + bltu a1, a2, 1b\n\ +2:5:\n" +#ifdef CPLUSPLUS + // Call __libc_init_array function +" call %0 \n\t" +: : "i" (__libc_init_array) +#else +: : +#endif +: "a0", "a1", "a2", "a3", "memory" +); + + // Setup the interrupt vector, processor status and INTSYSCR. + asm volatile( +" bnez a7, 5f\n\ + la t0, 0x12370303\n\ + csrw 0xbc0, t0\n\ + j 3f\n\ +5: la t0, 0x12378400\n\ + csrw 0xbc0, t0\n\ +3:\n" + +#if !defined( DISABLED_FLOAT ) +" li t0, 0x7888\n\ + csrs mstatus, t0\n" +#else +" li t0, 0x1888\n\ + csrs mstatus, t0\n" #endif -#if defined(__riscv_float_abi_double) -#define FLOAD(src, offset, dst) \ - " fld " #src ", " #offset "*8(" #dst ")\n" -#define FSTORE(dst, offset, src) \ - " fsd " #dst ", " #offset "*8(" #src ")\n" -#elif defined(__riscv_float_abi_single) -#define FLOAD(src, offset, dst) \ - " flw " #src ", " #offset "*4(" #dst ")\n" -#define FSTORE(dst, offset, src) \ - " fsw " #dst ", " #offset "*4(" #src ")\n" +#if FUNCONF_ENABLE_HPE +" bnez a7, 5f\n\ + li t0, 0x01\n\ + csrw 0xBC1, t0\n\ + li t0, 0x0b\n\ + csrw 0x804, t0\n\ + j 3f\n\ +5: li t0, 0x07\n\ + csrw 0xBC1, t0\n\ + li t0, 0x0b\n\ + csrw 0x804, t0\n\ +3:\n" +#endif +" la t0, InterruptVector\n\ + ori t0, t0, 3\n\ + csrw mtvec, t0\n" + : : [InterruptVector]"r"(InterruptVector) : "t0", "memory" + ); + +#if defined( FUNCONF_SYSTICK_USE_HCLK ) && FUNCONF_SYSTICK_USE_HCLK + SysTick->CTLR = 5; +#else + SysTick->CTLR = 1; +#endif + + + +#if defined(FUNCONF_ICACHE_EN) && FUNCONF_ICACHE_EN + setup_cache(); +#endif + + asm volatile( +" bnez a7, 5f\n\ + csrw mepc, %[main]\n\ + mret\n\ +5: csrw mepc, %[start_v5f]\n\ + mret\n" + : : [main]"r"(main), [start_v5f]"r"(start_v5f) ); +} +#endif + +#if defined( __riscv_float_abi_double ) +#define FLOAD( src, offset, dst ) \ +" fld " #src ", " #offset "*8(" #dst ")\n" +#define FSTORE( dst, offset, src ) \ +" fsd " #dst ", " #offset "*8(" #src ")\n" +#elif defined( __riscv_float_abi_single ) +#define FLOAD( src, offset, dst ) \ +" flw " #src ", " #offset "*4(" #dst ")\n" +#define FSTORE( dst, offset, src ) \ +" fsw " #dst ", " #offset "*4(" #src ")\n" #else // Soft float #endif -__attribute__((naked)) int setjmp(jmp_buf env) +__attribute__ ((naked)) int setjmp( jmp_buf env ) { - asm volatile( - // Common registers - " sw ra, 0*4(a0)\n" - " sw s0, 1*4(a0)\n" - " sw s1, 2*4(a0)\n" - " sw sp, 3*4(a0)\n" + asm volatile( + // Common registers +" sw ra, 0*4(a0)\n" +" sw s0, 1*4(a0)\n" +" sw s1, 2*4(a0)\n" +" sw sp, 3*4(a0)\n" - // RV32I only registers -#if !defined(__riscv_abi_rve) - " sw s2, 4*4(a0)\n" - " sw s3, 5*4(a0)\n" - " sw s4, 6*4(a0)\n" - " sw s5, 7*4(a0)\n" - " sw s6, 8*4(a0)\n" - " sw s7, 9*4(a0)\n" - " sw s8, 10*4(a0)\n" - " sw s9, 11*4(a0)\n" - " sw s10, 12*4(a0)\n" - " sw s11, 13*4(a0)\n" + // RV32I only registers +#if !defined( __riscv_abi_rve ) +" sw s2, 4*4(a0)\n" +" sw s3, 5*4(a0)\n" +" sw s4, 6*4(a0)\n" +" sw s5, 7*4(a0)\n" +" sw s6, 8*4(a0)\n" +" sw s7, 9*4(a0)\n" +" sw s8, 10*4(a0)\n" +" sw s9, 11*4(a0)\n" +" sw s10, 12*4(a0)\n" +" sw s11, 13*4(a0)\n" #endif - // FPU registers -#if defined(FSTORE) - FSTORE(fs2, 14, a0) - FSTORE(fs3, 15, a0) - FSTORE(fs4, 16, a0) - FSTORE(fs5, 17, a0) - FSTORE(fs6, 18, a0) - FSTORE(fs7, 19, a0) - FSTORE(fs8, 20, a0) - FSTORE(fs9, 21, a0) - FSTORE(fs10, 22, a0) - FSTORE(fs11, 23, a0) + // FPU registers +#if defined( FSTORE ) + FSTORE(fs2, 14, a0) + FSTORE(fs3, 15, a0) + FSTORE(fs4, 16, a0) + FSTORE(fs5, 17, a0) + FSTORE(fs6, 18, a0) + FSTORE(fs7, 19, a0) + FSTORE(fs8, 20, a0) + FSTORE(fs9, 21, a0) + FSTORE(fs10, 22, a0) + FSTORE(fs11, 23, a0) #endif - " li a0, 0\n" - " ret\n"); +" li a0, 0\n" +" ret\n" + ); } -__attribute__((naked)) void longjmp(jmp_buf env, int val) +__attribute__ ((naked)) void longjmp( jmp_buf env, int val ) { - asm volatile( - // Common registers - " lw ra, 0*4(a0)\n" - " lw s0, 1*4(a0)\n" - " lw s1, 2*4(a0)\n" - " lw sp, 3*4(a0)\n" + asm volatile( + // Common registers +" lw ra, 0*4(a0)\n" +" lw s0, 1*4(a0)\n" +" lw s1, 2*4(a0)\n" +" lw sp, 3*4(a0)\n" - // RV32I only registers -#if !defined(__riscv_abi_rve) - " lw s2, 4*4(a0)\n" - " lw s3, 5*4(a0)\n" - " lw s4, 6*4(a0)\n" - " lw s5, 7*4(a0)\n" - " lw s6, 8*4(a0)\n" - " lw s7, 9*4(a0)\n" - " lw s8, 10*4(a0)\n" - " lw s9, 11*4(a0)\n" - " lw s10, 12*4(a0)\n" - " lw s11, 13*4(a0)\n" + // RV32I only registers +#if !defined( __riscv_abi_rve ) +" lw s2, 4*4(a0)\n" +" lw s3, 5*4(a0)\n" +" lw s4, 6*4(a0)\n" +" lw s5, 7*4(a0)\n" +" lw s6, 8*4(a0)\n" +" lw s7, 9*4(a0)\n" +" lw s8, 10*4(a0)\n" +" lw s9, 11*4(a0)\n" +" lw s10, 12*4(a0)\n" +" lw s11, 13*4(a0)\n" #endif - // FPU registers -#if defined(FLOAD) - FLOAD(fs2, 14, a0) - FLOAD(fs3, 15, a0) - FLOAD(fs4, 16, a0) - FLOAD(fs5, 17, a0) - FLOAD(fs6, 18, a0) - FLOAD(fs7, 19, a0) - FLOAD(fs8, 20, a0) - FLOAD(fs9, 21, a0) - FLOAD(fs10, 22, a0) - FLOAD(fs11, 23, a0) + // FPU registers +#if defined( FLOAD ) + FLOAD(fs2, 14, a0) + FLOAD(fs3, 15, a0) + FLOAD(fs4, 16, a0) + FLOAD(fs5, 17, a0) + FLOAD(fs6, 18, a0) + FLOAD(fs7, 19, a0) + FLOAD(fs8, 20, a0) + FLOAD(fs9, 21, a0) + FLOAD(fs10, 22, a0) + FLOAD(fs11, 23, a0) #endif - " seqz a0, a1\n" // a0 = (a1 == 0) ? 1 : 0 - " add a0, a0, a1\n" - " ret\n"); - __builtin_unreachable(); // Disable warning about no return. +" seqz a0, a1\n" // a0 = (a1 == 0) ? 1 : 0 +" add a0, a0, a1\n" +" ret\n" + ); + __builtin_unreachable(); // Disable warning about no return. } -#if defined(FUNCONF_USE_UARTPRINTF) && FUNCONF_USE_UARTPRINTF -void SetupUART(int uartBRR) +#if defined( FUNCONF_USE_UARTPRINTF ) && FUNCONF_USE_UARTPRINTF +void SetupUART( int uartBRR ) { #ifdef CH32V003 - // Enable GPIOD and UART. - RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1; + // Enable GPIOD and UART. + RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1; - // Push-Pull, 10MHz Output, GPIO D5, with AutoFunction - GPIOD->CFGLR &= ~(0xf << (4 * 5)); - GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5); + // Push-Pull, 10MHz Output, GPIO D5, with AutoFunction + GPIOD->CFGLR &= ~(0xf<<(4*5)); + GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*5); #elif defined(CH32X03x) - RCC->APB2PCENR |= RCC_APB2Periph_GPIOB | RCC_APB2Periph_USART1; + RCC->APB2PCENR |= RCC_APB2Periph_GPIOB | RCC_APB2Periph_USART1; - // Push-Pull, 10MHz Output, GPIO A9, with AutoFunction - GPIOB->CFGHR &= ~(0xf << (4 * 2)); - GPIOB->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 2); + // Push-Pull, 10MHz Output, GPIO A9, with AutoFunction + GPIOB->CFGHR &= ~(0xf<<(4*2)); + GPIOB->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*2); +#elif defined(CH5xx) + // rx,tx:PA8,PA9 on uart1 +#ifdef CH570_CH572 + funPinMode( PA2, GPIO_CFGLR_IN_PU ); + funPinMode( PA3, GPIO_CFGLR_OUT_2Mhz_PP ); #else - RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_USART1; + funPinMode( PA8, GPIO_CFGLR_IN_PU ); + funPinMode( PA9, GPIO_CFGLR_OUT_2Mhz_PP ); +#endif + R16_UART1_DL = ((10 * FUNCONF_SYSTEM_CORE_CLOCK / 8 / uartBRR) +5) /10; + R8_UART1_FCR = (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + R8_UART1_LCR = RB_LCR_WORD_SZ; + R8_UART1_IER = RB_IER_TXD_EN; + R8_UART1_DIV = 1; +#elif defined(CH32H41x) + RCC->HB2PCENR |= RCC_HB2Periph_GPIOA | RCC_HB2Periph_USART1 | RCC_HB2Periph_AFIO; + RCC->HB1PCENR |= RCC_HB1Periph_USART6; + /* out pin USART1 */ + funPinAF( PA9, 7); + funPinMode( PA9, GPIO_Mode_AF_PP, GPIO_Speed_180MHz ); + /* out pin USART6 */ + funPinAF( PA12, 6); + funPinMode( PA12, GPIO_Mode_AF_PP, GPIO_Speed_180MHz ); - // Push-Pull, 10MHz Output, GPIO A9, with AutoFunction - GPIOA->CFGHR &= ~(0xf << (4 * 1)); - GPIOA->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF) << (4 * 1); + USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx; + USART1->CTLR2 = USART_StopBits_1; + USART1->CTLR3 = USART_HardwareFlowControl_None; + USART1->BRR = uartBRR; + USART1->CTLR1 |= CTLR1_UE_Set; + USART6->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx; + USART6->CTLR2 = USART_StopBits_1; + USART6->CTLR3 = USART_HardwareFlowControl_None; + USART6->BRR = uartBRR; + USART6->CTLR1 |= CTLR1_UE_Set; +#else + RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_USART1; + + // Push-Pull, 10MHz Output, GPIO A9, with AutoFunction + GPIOA->CFGHR &= ~(0xf<<(4*1)); + GPIOA->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*1); #endif - // 115200, 8n1. Note if you don't specify a mode, UART remains off even when UE_Set. - USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx; - USART1->CTLR2 = USART_StopBits_1; - USART1->CTLR3 = USART_HardwareFlowControl_None; +#ifndef CH5xx + // 115200, 8n1. Note if you don't specify a mode, UART remains off even when UE_Set. + USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx; + USART1->CTLR2 = USART_StopBits_1; + USART1->CTLR3 = USART_HardwareFlowControl_None; - USART1->BRR = uartBRR; - USART1->CTLR1 |= CTLR1_UE_Set; + USART1->BRR = uartBRR; + USART1->CTLR1 |= CTLR1_UE_Set; +#endif } // For debug writing to the UART. WEAK int _write(int fd, const char *buf, int size) { - for (int i = 0; i < size; i++) - { - while (!(USART1->STATR & USART_FLAG_TC)) - ; - USART1->DATAR = *buf++; - } - return size; + for(int i = 0; i < size; i++){ +#ifdef CH5xx + while(!(R8_UART1_LSR & RB_LSR_TX_ALL_EMP)); + R8_UART1_THR = buf[i]; +#elif defined(CH32H41x) + if (__get_MHARTID()) { + while( !(USART6->STATR & USART_FLAG_TC)); + USART6->DATAR = *buf++; + } + else { + while( !(USART1->STATR & USART_FLAG_TC)); + USART1->DATAR = *buf++; + } +#else + while( !(USART1->STATR & USART_FLAG_TC)); + USART1->DATAR = *buf++; +#endif + } + return size; } // single char to UART WEAK int putchar(int c) { - while (!(USART1->STATR & USART_FLAG_TC)) - ; - USART1->DATAR = (const char)c; - return 1; +#ifdef CH5xx + while(!(R8_UART1_LSR & RB_LSR_TX_ALL_EMP)); + R8_UART1_THR = c; +#elif defined(CH32H41x) + if (__get_MHARTID()) { + while( !(USART6->STATR & USART_FLAG_TC)); + USART6->DATAR = (const char)c; + } + else { + while( !(USART1->STATR & USART_FLAG_TC)); + USART1->DATAR = (const char)c; + } +#else + while( !(USART1->STATR & USART_FLAG_TC)); + USART1->DATAR = (const char)c; +#endif + return 1; } #endif -#if defined(FUNCONF_USE_DEBUGPRINTF) && FUNCONF_USE_DEBUGPRINTF - -void handle_debug_input(int numbytes, uint8_t *data) __attribute__((weak)); -void handle_debug_input(int numbytes, uint8_t *data) +#if defined( FUNCONF_USE_USBPRINTF ) && FUNCONF_USE_USBPRINTF +extern int USBFS_SendEndpointNEW( int endp, uint8_t* data, int len, int copy); +WEAK int _write(int fd, const char *buf, int size) { - (void)numbytes; - (void)data; + while(USBFS_SendEndpointNEW(3, (uint8_t*)buf, size, 1) == -1); // -1 == busy + return size; } -static void internal_handle_input(volatile uint32_t *dmdata0) +WEAK int putchar(int c) { - uint32_t dmd0 = *dmdata0; - int bytes = (dmd0 & 0x3f) - 4; - if (bytes > 0 && bytes < 16) - { - handle_debug_input(bytes, ((uint8_t *)dmdata0) + 1); - } + uint8_t single = c; + while(USBFS_SendEndpointNEW(3, &single, 1, 1) == -1); // -1 == busy + return 1; +} +#endif + +#if defined( FUNCONF_USE_DEBUGPRINTF ) && FUNCONF_USE_DEBUGPRINTF +void handle_debug_input( int numbytes, uint8_t * data ) __attribute__((weak)); +void handle_debug_input( int numbytes, uint8_t * data ) { (void)numbytes; (void)data; } + +static void internal_handle_input( volatile uint32_t * dmdata0 ) +{ + uint32_t dmd0 = *dmdata0; + int bytes = (dmd0 & 0x3f) - 4; + if( bytes > 0 && bytes < 16 ) + { + handle_debug_input( bytes, ((uint8_t*)dmdata0) + 1 ); + } } -void poll_input(void) + +void poll_input( void ) { - volatile uint32_t *dmdata0 = (volatile uint32_t *)DMDATA0; - if (((*dmdata0) & 0x80) == 0) - { - internal_handle_input(dmdata0); - *dmdata0 = 0x84; - } + volatile uint32_t * dmdata0 = (volatile uint32_t *)DMDATA0; + if( ((*dmdata0) & 0x80) == 0 ) + { + internal_handle_input( dmdata0 ); + *dmdata0 = 0x84; + } } + // MSB .... LSB // DMDATA0: char3 char2 char1 [status word] // where [status word] is: @@ -1445,115 +1702,125 @@ void poll_input(void) // declare as weak to allow overriding. WEAK int _write(int fd, const char *buf, int size) { - (void)fd; - if ((*DMDATA0 & 0xc0) == 0xc0) return 0; + (void)fd; + if( ( *DMDATA0 & 0xc0 ) == 0xc0 ) return 0; - char buffer[4] = {0}; - int place = 0; - uint32_t lastdmd; - uint32_t timeout = FUNCONF_DEBUGPRINTF_TIMEOUT; // Give up after ~120ms + char buffer[4] = { 0 }; + int place = 0; + uint32_t lastdmd; + uint32_t timeout = FUNCONF_DEBUGPRINTF_TIMEOUT; // Give up after ~120ms - if (size == 0) - { - lastdmd = (*DMDATA0); - if (lastdmd && !(lastdmd & 0x80)) internal_handle_input((uint32_t *)DMDATA0); - } - while (place < size) - { - int tosend = size - place; - if (tosend > 7) tosend = 7; + if( size == 0 ) + { + lastdmd = (*DMDATA0); + if( lastdmd && !(lastdmd&0x80) ) internal_handle_input( (uint32_t*)DMDATA0 ); + } + while( place < size ) + { + int tosend = size - place; + if( tosend > 7 ) tosend = 7; - while ((lastdmd = (*DMDATA0)) & 0x80) - { - if (timeout-- == 0) - { - *DMDATA0 |= 0xc0; - return 0; - } - } + while( ( lastdmd = (*DMDATA0) ) & 0x80 ) + { + if( timeout-- == 0 ) + { + *DMDATA0 |= 0xc0; + return 0; + } + } - if (lastdmd) internal_handle_input((uint32_t *)DMDATA0); + if( lastdmd ) internal_handle_input( (uint32_t*)DMDATA0 ); - timeout = FUNCONF_DEBUGPRINTF_TIMEOUT; + timeout = FUNCONF_DEBUGPRINTF_TIMEOUT; - int t = 3; - while (t < tosend) - { - buffer[t - 3] = buf[t + place]; - t++; - } - *DMDATA1 = *(uint32_t *)&(buffer[0]); - t = 0; - while (t < tosend && t < 3) - { - buffer[t + 1] = buf[t + place]; - t++; - } - buffer[0] = 0x80 | (tosend + 4); - *DMDATA0 = *(uint32_t *)&(buffer[0]); + int t = 3; + while( t < tosend ) + { + buffer[t-3] = buf[t+place]; + t++; + } + *DMDATA1 = *(uint32_t*)&(buffer[0]); + t = 0; + while( t < tosend && t < 3 ) + { + buffer[t+1] = buf[t+place]; + t++; + } + buffer[0] = 0x80 | (tosend + 4); + *DMDATA0 = *(uint32_t*)&(buffer[0]); - // buf += tosend; - place += tosend; - } - return size; + //buf += tosend; + place += tosend; + } + return size; } // single to debug intf WEAK int putchar(int c) { - if ((*DMDATA0 & 0xc0) == 0xc0) return 0; + if( ( *DMDATA0 & 0xc0 ) == 0xc0 ) return 0; - int timeout = FUNCONF_DEBUGPRINTF_TIMEOUT; - uint32_t lastdmd = 0; + int timeout = FUNCONF_DEBUGPRINTF_TIMEOUT; + uint32_t lastdmd = 0; - while ((lastdmd = (*DMDATA0)) & 0x80) - { - if (timeout-- == 0) - { - *DMDATA0 |= 0xc0; - return 0; - } - } + while( ( lastdmd = (*DMDATA0) ) & 0x80 ) + { + if( timeout-- == 0 ) + { + *DMDATA0 |= 0xc0; + return 0; + } + } - // Simply seeking input. - if (lastdmd) internal_handle_input((uint32_t *)DMDATA0); + // Simply seeking input. + if( lastdmd ) internal_handle_input( (uint32_t*)DMDATA0 ); - // Write out character. - *DMDATA0 = 0x85 | ((const char)c << 8); - return 1; + // Write out character. + *DMDATA0 = 0x85 | ((const char)c<<8); + return 1; } -void SetupDebugPrintf(void) +void SetupDebugPrintf( void ) { - // Clear out the sending flag. - *DMDATA1 = 0x00; - *DMDATA0 = 0x80; + // Clear out the sending flag. + *DMDATA1 = 0x00; + *DMDATA0 = 0x80; } -int WaitForDebuggerToAttach(int timeout_ms) +void CallConstructors( void ) { -#if defined(CH32V20x) || defined(CH32V30x) -#define systickcnt_t uint64_t -#define SYSTICKCNT SysTick->CNT -#elif defined(CH32V10x) || defined(CH32X03x) -#define systickcnt_t uint32_t -#define SYSTICKCNT SysTick->CNTL + extern void (*__init_array_start[])(void); + extern void (*__init_array_end[])(void); + + for (void (**ctor)(void) = __init_array_start; ctor < __init_array_end; ++ctor) { + (*ctor)(); + } +} + +int WaitForDebuggerToAttach( int timeout_ms ) +{ + +#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) || defined(CH32L103) || defined(CH571_CH573) || defined(CH582_CH583) || defined(CH591_CH592) + #define systickcnt_t uint64_t + #define SYSTICKCNT SysTick->CNT +#elif defined(CH32V10x) || defined(CH570_CH572) || defined(CH584_CH585) + #define systickcnt_t uint32_t + #define SYSTICKCNT SysTick->CNTL #else -#define systickcnt_t uint32_t -#define SYSTICKCNT SysTick->CNT + #define systickcnt_t uint32_t + #define SYSTICKCNT SysTick->CNT #endif - const systickcnt_t start = SYSTICKCNT; - const systickcnt_t ticks_per_ms = (FUNCONF_SYSTEM_CORE_CLOCK / 1000); - const systickcnt_t timeout = timeout_ms * ticks_per_ms; + const systickcnt_t start = SYSTICKCNT; + const systickcnt_t ticks_per_ms = (FUNCONF_SYSTEM_CORE_CLOCK / 1000); + const systickcnt_t timeout = timeout_ms * ticks_per_ms; - // Wait for the sentinel to become zero. - while (!DidDebuggerAttach()) - { - if (timeout_ms && (SYSTICKCNT - start) > timeout) return 1; - } + // Wait for the sentinel to become zero. + while( !DidDebuggerAttach() ) { + if( timeout_ms && (SYSTICKCNT - start) > timeout ) return 1; + } - return 0; + return 0; #undef systickcnt_t #undef SYSTICKCNT @@ -1561,245 +1828,377 @@ int WaitForDebuggerToAttach(int timeout_ms) #endif -#if (defined(FUNCONF_USE_DEBUGPRINTF) && !FUNCONF_USE_DEBUGPRINTF) && \ - (defined(FUNCONF_USE_UARTPRINTF) && !FUNCONF_USE_UARTPRINTF) && \ - (defined(FUNCONF_NULL_PRINTF) && FUNCONF_NULL_PRINTF) +#if (defined( FUNCONF_USE_DEBUGPRINTF ) && !FUNCONF_USE_DEBUGPRINTF) && \ + (defined( FUNCONF_USE_UARTPRINTF ) && !FUNCONF_USE_UARTPRINTF) && \ + (defined( FUNCONF_USE_USBPRINTF ) && !FUNCONF_USE_USBPRINTF) && \ + (defined( FUNCONF_NULL_PRINTF ) && FUNCONF_NULL_PRINTF) WEAK int _write(int fd, const char *buf, int size) { - return size; + return size; } // single to debug intf WEAK int putchar(int c) { - return 1; + return 1; } #endif -void DelaySysTick(uint32_t n) +void DelaySysTick( uint32_t n ) { -#ifdef CH32V003 - uint32_t targend = SysTick->CNT + n; - while (((int32_t)(SysTick->CNT - targend)) < 0) - ; -#elif defined(CH32V20x) || defined(CH32V30x) - uint64_t targend = SysTick->CNT + n; - while (((int64_t)(SysTick->CNT - targend)) < 0) - ; -#elif defined(CH32V10x) || defined(CH32X03x) - uint32_t targend = SysTick->CNTL + n; - while (((int32_t)(SysTick->CNTL - targend)) < 0) - ; +#if defined(CH32V003) || defined(CH32V00x) + uint32_t targend = SysTick->CNT + n; + while( ((int32_t)( SysTick->CNT - targend )) < 0 ); +#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32X03x) || defined(CH32L103) || defined(CH582_CH583) || defined(CH591_CH592) || defined(CH32H41x) + uint64_t targend = SysTick->CNT + n; + while( ((int64_t)( SysTick->CNT - targend )) < 0 ); +#elif defined(CH32V10x) || defined(CH570_CH572) || defined(CH584_CH585) + uint32_t targend = SysTick->CNTL + n; + while( ((int32_t)( SysTick->CNTL - targend )) < 0 ); +#elif defined(CH571_CH573) + // ch573 insisted on being special, it's counting down + uint64_t targend = SysTick->CNT - n; + while( ((int64_t)( SysTick->CNT - targend )) > 0 ); #else -#error DelaySysTick not defined. + #error DelaySysTick not defined. #endif } -void SystemInit(void) +#if defined(CH32H41x) +void StartV5F(v5f_main function) +{ + volatile uint32_t addr = (uint32_t)handle_reset; + + v5f_start_function = function; + + NVIC->WAKEIP[1] = addr & ~(0x1); + NVIC->SCTLR |= (1<<5); +} +#endif + +void SystemInit( void ) { #if defined(CH32V30x) && defined(TARGET_MCU_MEMORY_SPLIT) - FLASH->OBR = TARGET_MCU_MEMORY_SPLIT << 8; + FLASH->OBR = TARGET_MCU_MEMORY_SPLIT<<8; #endif #if FUNCONF_HSE_BYPASS -#define HSEBYP (1 << 18) + #define HSEBYP (1<<18) #else -#define HSEBYP 0 + #define HSEBYP 0 #endif #if defined(FUNCONF_USE_CLK_SEC) && FUNCONF_USE_CLK_SEC -#define RCC_CSS RCC_CSSON // Enable clock security system +#define RCC_CSS RCC_CSSON // Enable clock security system #else #define RCC_CSS 0 #endif #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL -#if defined(CH32V003) -#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2 // HCLK = SYSCLK = APB1 And, enable PLL -#elif defined(CH32V20x_D8W) -#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV1 | PLL_MULTIPLICATION + #if defined(CH32V003) || defined(CH32V00x) + #define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2 // HCLK = SYSCLK = APB1 And, enable PLL + #elif defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV1 | PLL_MULTIPLICATION + #elif defined(CH32H41x) + #define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV2 | RCC_PPRE2_DIV2 | RCC_FPRE_DIV4 | RCC_CFGR0_MCO_SYSCLK + #else + #define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2 | PLL_MULTIPLICATION + #endif #else -#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2 | PLL_MULTIPLICATION -#endif -#else -#if defined(CH32V003) || defined(CH32X03x) -#define BASE_CFGR0 RCC_HPRE_DIV1 // HCLK = SYSCLK = APB1 And, no pll. -#else -#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV1 -#endif + #if defined(CH32V003) || defined(CH32X03x) || defined(CH32V00x) + #define BASE_CFGR0 RCC_HPRE_DIV1 // HCLK = SYSCLK = APB1 And, no pll. + #elif defined(CH32H41x) + #define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV0 | RCC_PPRE2_DIV0 | RCC_CFGR0_MCO_SYSCLK + #else + #define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV1 + #endif #endif // HSI always ON - needed for the Debug subsystem -#define BASE_CTLR (((FUNCONF_HSITRIM) << 3) | RCC_HSION | HSEBYP | RCC_CSS) - // #define BASE_CTLR (((FUNCONF_HSITRIM) << 3) | HSEBYP | RCC_CSS) // disable HSI in HSE modes +#define BASE_CTLR (((FUNCONF_HSITRIM) << 3) | RCC_HSION | HSEBYP | RCC_CSS) +//#define BASE_CTLR (((FUNCONF_HSITRIM) << 3) | HSEBYP | RCC_CSS) // disable HSI in HSE modes - // Flash latency settings. -#if defined(CH32V00x) -// Per TRM -#if FUNCONF_SYSTEM_CORE_CLOCK > 25000000 - FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; -#elif FUNCONF_SYSTEM_CORE_CLOCK > 15000000 - FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; -#else - FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; -#endif + // Flash latency settings. +#if defined(CH32V003) + #if FUNCONF_SYSTEM_CORE_CLOCK > 25000000 + FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // +1 Cycle Latency + #else + FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; // +0 Cycle Latency + #endif +#elif defined(CH32V00x) + // Per TRM + #if FUNCONF_SYSTEM_CORE_CLOCK > 25000000 + FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; + #elif FUNCONF_SYSTEM_CORE_CLOCK > 15000000 + FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; + #else + FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; + #endif #elif defined(CH32X03x) - FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; // +2 Cycle Latency (Recommended per TRM) -#elif defined(CH32V003) -#if FUNCONF_SYSTEM_CORE_CLOCK > 25000000 - FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // +1 Cycle Latency -#else - FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; // +0 Cycle Latency -#endif + FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; // +2 Cycle Latency (Recommended per TRM) +#elif defined(CH32H41x) + FLASH->ACTLR |= FLASH_ACTLR_EHMOD; #endif -#if defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI -#if defined(CH32V30x) || defined(CH32V20x) || defined(CH32V10x) - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; +#if defined(CH32H41x) + #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL + #if defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI + RCC->PLLCFGR = PLL_MULTIPLICATION | RCC_PLLSource_HSI; + #elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE + RCC->PLLCFGR = PLL_MULTIPLICATION | RCC_PLLSource_HSE; + #endif + #endif #endif -#if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL - RCC->CFGR0 = BASE_CFGR0; - RCC->CTLR = BASE_CTLR | RCC_HSION | RCC_PLLON; // Use HSI, enable PLL. -#else - RCC->CFGR0 = RCC_HPRE_DIV1; // PLLCLK = HCLK = SYSCLK = APB1 - RCC->CTLR = BASE_CTLR | RCC_HSION; // Use HSI, Only. + +#ifdef CH5xx // has no HSI except ch584/5 +#ifndef CLK_SOURCE_CH5XX + #define CLK_SOURCE_CH5XX CLK_SOURCE_PLL_60MHz #endif +#if (defined(CH570_CH572) || defined(CH584_CH585)) + SYS_CLKTypeDef sc = CLK_SOURCE_CH5XX; + + if(sc == RB_CLK_SYS_MOD) // LSI + { + SYS_SAFE_ACCESS( + R8_CLK_SYS_CFG |= RB_CLK_SYS_MOD; + ); + } + else + { + if((sc & RB_CLK_SYS_MOD) == 0x40) // PLL div + { + SYS_SAFE_ACCESS( + R8_HFCK_PWR_CTRL |= RB_CLK_PLL_PON; + R8_FLASH_CFG = 0x01; + R8_FLASH_SCK |= 1<<4; + ); + } + else + { + SYS_SAFE_ACCESS( + R8_FLASH_CFG = (sc & 0x1F) ? 0x02 : 0x07; + ); + } + SYS_SAFE_ACCESS( +#ifdef CH570_CH572 + R8_CLK_SYS_CFG = sc; +#else // CH584_585 + R16_CLK_SYS_CFG = sc; +#endif + ); + } +#else // ch5xx EXCEPT ch570/2 ch584/5 + SYS_CLKTypeDef sc = CLK_SOURCE_CH5XX; + SYS_SAFE_ACCESS( + R8_PLL_CONFIG &= ~(1 << 5); + ); + if(sc & 0x20) // HSE div + { + SYS_SAFE_ACCESS( + R32_CLK_SYS_CFG = (0 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN; + ); + ADD_N_NOPS(4); + SYS_SAFE_ACCESS( + R8_FLASH_CFG = 0x51; + ); + } + else if(sc & 0x40) // PLL div + { + SYS_SAFE_ACCESS( + R32_CLK_SYS_CFG = (1 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN; + ); + ADD_N_NOPS(4); + SYS_SAFE_ACCESS( + R8_FLASH_CFG = 0x52; + ); + } + else + { + SYS_SAFE_ACCESS( + R32_CLK_SYS_CFG |= RB_CLK_SYS_MOD; + ); + } + + SYS_SAFE_ACCESS( + R8_PLL_CONFIG |= 1 << 7; + ); +#endif // switch between ch570/2 and other ch5xx +#elif defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI + #if defined(CH32V30x) || defined(CH32V20x) || defined(CH32L103) || defined(CH32V10x) + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + #endif + #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL + RCC->CFGR0 = BASE_CFGR0; + RCC->CTLR = BASE_CTLR | RCC_HSION | RCC_PLLON; // Use HSI, enable PLL. + #else + RCC->CFGR0 = RCC_HPRE_DIV1; // PLLCLK = HCLK = SYSCLK = APB1 + RCC->CTLR = BASE_CTLR | RCC_HSION; // Use HSI, Only. + #endif #elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE -#if defined(CH32V003) - RCC->CTLR = BASE_CTLR | RCC_HSION | RCC_HSEON; // Keep HSI on while turning on HSE -#else - RCC->CTLR = RCC_HSEON; // Only turn on HSE. + #if defined(CH32V003) || defined(CH32V00x) + RCC->CTLR = BASE_CTLR | RCC_HSION | RCC_HSEON ; // Keep HSI on while turning on HSE + #else + RCC->CTLR = RCC_HSEON; // Only turn on HSE. + #endif + + // Values lifted from the EVT. There is little to no documentation on what this does. + while(!(RCC->CTLR&RCC_HSERDY)) {}; + + #if defined(CH32V003) || defined(CH32V00x) + RCC->CFGR0 = RCC_PLLSRC_HSE_Mul2 | RCC_SW_HSE; + #elif defined(CH32H41x) + RCC->CFGR0 = BASE_CFGR0 | RCC_SW_HSE; + #else + RCC->CFGR0 = BASE_CFGR0 | RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE; + #endif + + #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL + RCC->CTLR = BASE_CTLR | RCC_HSEON | RCC_PLLON; // Turn off HSI. + #else + RCC->CTLR = RCC_HSEON | HSEBYP; // Turn off PLL and HSI. + #endif #endif - // Values lifted from the EVT. There is little to no documentation on what this does. - while (!(RCC->CTLR & RCC_HSERDY)) {}; - -#if defined(CH32V003) - RCC->CFGR0 = RCC_PLLSRC_HSE_Mul2 | RCC_SW_HSE; -#else - RCC->CFGR0 = BASE_CFGR0 | RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE; -#endif - -#if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL - RCC->CTLR = BASE_CTLR | RCC_HSEON | RCC_PLLON; // Turn off HSI. -#else - RCC->CTLR = RCC_HSEON | HSEBYP; // Turn off PLL and HSI. -#endif -#endif - - // CH32V10x flash prefetch buffer + // CH32V10x flash prefetch buffer #if defined(CH32V10x) - // Enable Prefetch Buffer - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + // Enable Prefetch Buffer + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; #endif - // CH32V10x flash latency + // CH32V10x flash latency #if defined(CH32V10x) -#if defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE -#if !defined(FUNCONF_USE_PLL) || !FUNCONF_USE_PLL - FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; // +0 Cycle Latency -#else -#if FUNCONF_SYSTEM_CORE_CLOCK < 56000000 - FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // +1 Cycle Latency -#else - FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; // +2 Cycle Latency -#endif -#endif -#else - FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // +1 Cycle Latency -#endif + #if defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE + #if !defined(FUNCONF_USE_PLL) || !FUNCONF_USE_PLL + FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; // +0 Cycle Latency + #else + #if FUNCONF_SYSTEM_CORE_CLOCK < 56000000 + FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // +1 Cycle Latency + #else + FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; // +2 Cycle Latency + #endif + #endif + #else + FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // +1 Cycle Latency + #endif #endif - RCC->INTR = 0x009F0000; // Clear PLL, CSSC, HSE, HSI and LSI ready flags. - -#if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL - while ((RCC->CTLR & RCC_PLLRDY) == 0) - ; // Wait till PLL is ready - uint32_t tmp32 = RCC->CFGR0 & ~(0x03); // clr the SW - RCC->CFGR0 = tmp32 | RCC_SW_PLL; // Select PLL as system clock source - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - ; // Wait till PLL is used as system clock source +#if defined(CH32L103) + // Per TRM + #if FUNCONF_SYSTEM_CORE_CLOCK > 72000000 + FLASH->ACTLR = FLASH_ACTLR_LATENCY_2; + #elif FUNCONF_SYSTEM_CORE_CLOCK > 40000000 + FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; + #else + FLASH->ACTLR = FLASH_ACTLR_LATENCY_0; + #endif #endif -#if defined(FUNCONF_USE_UARTPRINTF) && FUNCONF_USE_UARTPRINTF - SetupUART(UART_BRR); +#ifndef CH5xx + RCC->INTR = 0x009F0000; // Clear PLL, CSSC, HSE, HSI and LSI ready flags. #endif -#if defined(FUNCONF_USE_DEBUGPRINTF) && FUNCONF_USE_DEBUGPRINTF - SetupDebugPrintf(); + +#if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL && !defined(CH5xx) + while((RCC->CTLR & RCC_PLLRDY) == 0) {}; // Wait till PLL is ready + #if defined(CH32H41x) + RCC->PLLCFGR |= RCC_SYSPLL_GATE; + #endif + uint32_t tmp32 = RCC->CFGR0 & ~(0x03); // clr the SW + RCC->CFGR0 = tmp32 | RCC_SW_PLL; // Select PLL as system clock source + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08); // Wait till PLL is used as system clock source +#endif + +#if defined( FUNCONF_USE_UARTPRINTF ) && FUNCONF_USE_UARTPRINTF + SetupUART( UART_BRR ); +#endif +#if defined( FUNCONF_USE_DEBUGPRINTF ) && FUNCONF_USE_DEBUGPRINTF + SetupDebugPrintf(); +#endif +#if defined(FUNCONF_SUPPORT_CONSTRUCTORS) && FUNCONF_SUPPORT_CONSTRUCTORS + CallConstructors(); #endif } -void funAnalogInit(void) +#ifndef CH5xx // no-op on ch5xx +void funAnalogInit( void ) { - // RCC->CFGR0 &= ~(0x1F<<11); // Assume ADCPRE = 0 - RCC->APB2PCENR |= RCC_APB2Periph_ADC1; + // Please remember that ADC clock should not exceed 14Mhz! + // To ensure that, you may need to adjust RCC depending on your clock speed in the following way: + // RCC->CFGR0 |= RCC_ADCPRE_DIV6 // ADC prediv + // RCC->CFGR0 |= RCC_PPRE2_DIV2; // Divide HCLK by 2 in PPRE2 because ADCPRE is not enough at high speeds + #if defined(CH32H41x) + RCC->HB2PCENR |= RCC_HB2Periph_ADC1; + // Reset ADC. + RCC->HB2PRSTR |= RCC_HB2Periph_ADC1; + RCC->HB2PRSTR &= ~RCC_HB2Periph_ADC1; + #else + RCC->APB2PCENR |= RCC_APB2Periph_ADC1; + // Reset ADC. + RCC->APB2PRSTR |= RCC_APB2Periph_ADC1; + RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1; + #endif - // Reset ADC. - RCC->APB2PRSTR |= RCC_APB2Periph_ADC1; - RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1; + // set sampling time for all channels to 15 (A good middleground) ADC_SMP0_1. + ADC1->SAMPTR2 = (ADC_SMP0_1<<(3*0)) | (ADC_SMP0_1<<(3*1)) | (ADC_SMP0_1<<(3*2)) | (ADC_SMP0_1<<(3*3)) | (ADC_SMP0_1<<(3*4)) | (ADC_SMP0_1<<(3*5)) | (ADC_SMP0_1<<(3*6)) | (ADC_SMP0_1<<(3*7)) | (ADC_SMP0_1<<(3*8)) | (ADC_SMP0_1<<(3*9)); + ADC1->SAMPTR1 = (ADC_SMP0_1<<(3*0)) | (ADC_SMP0_1<<(3*1)) | (ADC_SMP0_1<<(3*2)) | (ADC_SMP0_1<<(3*3)) | (ADC_SMP0_1<<(3*4)) | (ADC_SMP0_1<<(3*5)); - // set sampling time for all channels to 15 (A good middleground) ADC_SMP0_1. - ADC1->SAMPTR2 = (ADC_SMP0_1 << (3 * 0)) | (ADC_SMP0_1 << (3 * 1)) | (ADC_SMP0_1 << (3 * 2)) | (ADC_SMP0_1 << (3 * 3)) | (ADC_SMP0_1 << (3 * 4)) | (ADC_SMP0_1 << (3 * 5)) | (ADC_SMP0_1 << (3 * 6)) | (ADC_SMP0_1 << (3 * 7)) | (ADC_SMP0_1 << (3 * 8)) | (ADC_SMP0_1 << (3 * 9)); - ADC1->SAMPTR1 = (ADC_SMP0_1 << (3 * 0)) | (ADC_SMP0_1 << (3 * 1)) | (ADC_SMP0_1 << (3 * 2)) | (ADC_SMP0_1 << (3 * 3)) | (ADC_SMP0_1 << (3 * 4)) | (ADC_SMP0_1 << (3 * 5)); + // turn on ADC and set rule group to sw trig + #if defined(CH32V20x) + ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL | ADC_EXTTRIG; + #else + ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL; + #endif - ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL; // turn on ADC and set rule group to sw trig + // Reset calibration + ADC1->CTLR2 |= CTLR2_RSTCAL_Set; + while(ADC1->CTLR2 & CTLR2_RSTCAL_Set); + + // Calibrate + ADC1->CTLR2 |= CTLR2_CAL_Set; + while(ADC1->CTLR2 & CTLR2_CAL_Set); - // Reset calibration - ADC1->CTLR2 |= ADC_RSTCAL; - while (ADC1->CTLR2 & ADC_RSTCAL) - ; - - // Calibrate - ADC1->CTLR2 |= ADC_CAL; - while (ADC1->CTLR2 & ADC_CAL) - ; } -int funAnalogRead(int nAnalogNumber) +int funAnalogRead( int nAnalogNumber ) { - ADC1->RSQR3 = nAnalogNumber; + ADC1->RSQR3 = nAnalogNumber; - // start sw conversion (auto clears) - ADC1->CTLR2 |= ADC_SWSTART; - - // wait for conversion complete - while (!(ADC1->STATR & ADC_EOC)) - ; - - // get result - return ADC1->RDATAR; + // start sw conversion (auto clears) + ADC1->CTLR2 |= ADC_SWSTART; + + // wait for conversion complete + while(!(ADC1->STATR & ADC_EOC)); + + // get result + return ADC1->RDATAR; } +#endif // C++ Support #ifdef CPLUSPLUS // This is required to allow pure virtual functions to be defined. -extern void __cxa_pure_virtual() -{ - while (1) - ; -} +extern void __cxa_pure_virtual() { while (1); } // These magic symbols are provided by the linker. -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); +extern void (*__preinit_array_start[]) (void) __attribute__((weak)); +extern void (*__preinit_array_end[]) (void) __attribute__((weak)); +extern void (*__init_array_start[]) (void) __attribute__((weak)); +extern void (*__init_array_end[]) (void) __attribute__((weak)); void __libc_init_array(void) { - size_t count; - size_t i; + size_t count; + size_t i; - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) - __preinit_array_start[i](); + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) + __preinit_array_start[i](); - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) - __init_array_start[i](); + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) + __init_array_start[i](); } #endif