#ifndef TODO_HARDWARE_H #define TODO_HARDWARE_H #include "ch32fun.h" #ifndef __ASSEMBLER__ // Things before this can be used in assembly. #ifdef __cplusplus extern "C" { #endif /* Interrupt Number Definition, according to the selected device */ typedef enum IRQn { /****** RISC-V Processor Exceptions Numbers *******************************************************/ NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ EXC_IRQn = 3, /* 3 Exception Interrupt */ Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ SysTick0_IRQn = 12, /* 12 System timer Interrupt */ SysTick1_IRQn = 13, /* 13 System timer Interrupt */ Software_IRQn = 14, /* 14 software Interrupt */ IPC_CH0_IRQn = 16, /* 16 IPC CH0 Interrupt */ IPC_CH1_IRQn = 17, /* 17 IPC CH1 Interrupt */ IPC_CH2_IRQn = 18, /* 18 IPC CH2 Interrupt */ IPC_CH3_IRQn = 19, /* 19 IPC CH3 Interrupt */ HSEM_IRQn = 28, /* 28 HSEM Interrupt */ /****** RISC-V specific Interrupt Numbers *********************************************************/ WWDG_IRQn = 32, /* Window WatchDog Interrupt */ EXTI15_8_IRQn = 33, /* External Line[15:8] Interrupts */ FLASH_IRQn = 34, /* FLASH global Interrupt */ RCC_IRQn = 35, /* RCC global Interrupt */ EXTI7_0_IRQn = 36, /* External Line[7:0] Interrupts */ SPI1_IRQn = 37, /* SPI1 global Interrupt */ DMA1_Channel2_IRQn = 38, /* DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 39, /* DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 40, /* DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 41, /* DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 42, /* DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 43, /* DMA1 Channel 7 global Interrupt */ DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ USART2_IRQn = 45, /* USART2 global Interrupt */ I2C1_EV_IRQn = 46, /* I2C1 Event Interrupt */ I2C1_ER_IRQn = 47, /* I2C1 Error Interrupt */ USART1_IRQn = 48, /* USART1 global Interrupt */ SPI2_IRQn = 49, /* SPI2 global Interrupt */ SPI3_IRQn = 50, /* SPI3 global Interrupt */ SPI4_IRQn = 51, /* SPI4 global Interrupt */ I2C2_EV_IRQn = 52, /* I2C2 Event Interrupt */ I2C2_ER_IRQn = 53, /* I2C2 Error Interrupt */ USBPD_IRQn = 54, /* USBPD Interrupt */ USBPDWakeUp_IRQn = 55, /* USBPD WakeUp Interrupt */ USBHS_IRQn = 56, /* USBHS global Interrupt */ DMA1_Channel1_IRQn = 57, /* DMA1 Channel 1 global Interrupt */ CAN1_SCE_IRQn = 58, /* CAN1 SCE Interrupt */ CAN1_TX_IRQn = 59, /* CAN1 TX Interrupts */ CAN1_RX0_IRQn = 60, /* CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 61, /* CAN1 RX1 Interrupts */ USBSS_IRQn = 62, /* USBSS Interrupt */ USBSS_LINK_IRQn = 63, /* USBSS LINK Interrupt */ USBHSWakeup_IRQn = 64, /* USBHS WakeUp Interrupt */ USBSSWakeup_IRQn = 65, /* USBSS WakeUp Interrupt */ RTCAlarm_IRQn = 66, /* RTC Alarm through EXTI Line Interrupt */ USBFS_IRQn = 67, /* USBFS global Interrupt */ USBFSWakeUp_IRQn = 68, /* USBFS WakeUp Interrupt */ ADC1_2_IRQn = 69, /* ADC1 and ADC2 global Interrupt */ TIM1_BRK_IRQn = 70, /* TIM1 Break Interrupt */ TIM1_UP_IRQn = 71, /* TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 72, /* TIM1 Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 73, /* TIM1 Capture Compare Interrupt */ TIM2_IRQn = 74, /* TIM2 global Interrupt */ TIM3_IRQn = 75, /* TIM3 global Interrupt */ TIM4_IRQn = 76, /* TIM4 global Interrupt */ TIM5_IRQn = 77, /* TIM5 global Interrupt */ I2C3_EV_IRQn = 78, /* I2C3 Event Interrupt */ I2C3_ER_IRQn = 79, /* I2C3 Error Interrupt */ I2C4_EV_IRQn = 80, /* I2C4 Event Interrupt */ I2C4_ER_IRQn = 81, /* I2C4 Error Interrupt */ QSPI1_IRQn = 82, /* QSPI1 Interrupt */ SERDES_IRQn = 83, /* SERDES Interrupt */ USART3_IRQn = 84, /* USART3 global Interrupt */ USART4_IRQn = 85, /* USART4 global Interrupt */ TIM8_BRK_IRQn = 86, /* TIM8 Break Interrupt */ TIM8_UP_IRQn = 87, /* TIM8 Update Interrupt */ TIM8_TRG_COM_IRQn = 88, /* TIM8 Trigger and Commutation Interrupt */ TIM8_CC_IRQn = 89, /* TIM8 Capture Compare Interrupt */ TIM9_IRQn = 90, /* TIM9 global Interrupt */ TIM10_IRQn = 91, /* TIM10 global Interrupt */ TIM11_IRQn = 92, /* TIM11 global Interrupt */ TIM12_IRQn = 93, /* TIM12 global Interrupt */ FMC_IRQn = 94, /* FMC global Interrupt */ SDMMC_IRQn = 95, /* SDMMC global Interrupt */ LPTIM1_IRQn = 96, /* LPTIM1 global Interrupt */ LPTIM2_IRQn = 97, /* LPTIM2 global Interrupt */ USART5_IRQn = 98, /* USART5 global Interrupt */ USART6_IRQn = 99, /* USART6 global Interrupt */ TIM6_IRQn = 100, /* TIM6 global Interrupt */ TIM7_IRQn = 101, /* TIM7 global Interrupt */ DMA2_Channel1_IRQn = 102, /* DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 103, /* DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 104, /* DMA2 Channel 3 global Interrupt */ DMA2_Channel4_IRQn = 105, /* DMA2 Channel 4 global Interrupt */ DMA2_Channel5_IRQn = 106, /* DMA2 Channel 5 global Interrupt */ DMA2_Channel6_IRQn = 107, /* DMA2 Channel 6 global Interrupt */ DMA2_Channel7_IRQn = 108, /* DMA2 Channel 7 global Interrupt */ DMA2_Channel8_IRQn = 109, /* DMA2 Channel 8 global Interrupt */ ETH_IRQn = 110, /* ETH global Interrupt */ ETH_WKUP_IRQn = 111, /* ETH WakeUp Interrupt */ CAN2_SCE_IRQn = 112, /* CAN2 SCE Interrupt */ CAN2_TX_IRQn = 113, /* CAN2 TX Interrupts */ CAN2_RX0_IRQn = 114, /* CAN2 RX0 Interrupts */ CAN2_RX1_IRQn = 115, /* CAN2 RX1 Interrupts */ USART7_IRQn = 116, /* USART7 global Interrupt */ USART8_IRQn = 117, /* USART8 global Interrupt */ I3C_EV_IRQn = 118, /* I3C Event Interrupt */ I3C_ER_IRQn = 119, /* I3C Error Interrupt */ DVP_IRQn = 120, /* DVP global Interrupt */ ECDC_IRQn = 121, /* ECDC global Interrupt */ PIOC_IRQn = 122, /* PIOC global Interrupt */ SAI_IRQn = 123, /* SAI global Interrupt */ LTDC_IRQn = 124, /* LTDC global Interrupt */ GPHA_IRQn = 125, /* GPHA global Interrupt */ DFSDM0_IRQn = 127, /* DFSDM0 global Interrupt */ DFSDM1_IRQn = 128, /* DFSDM1 global Interrupt */ SWPMI_IRQn = 131, /* SWPMI global Interrupt */ QSPI2_IRQn = 134, /* QSPI2 Interrupt */ SWPMI_WKUP_IRQn = 135, /* SWPMI WakeUp Interrupt */ CAN3_SCE_IRQn = 136, /* CAN3 SCE Interrupt */ CAN3_TX_IRQn = 137, /* CAN3 TX Interrupts */ CAN3_RX0_IRQn = 138, /* CAN3 RX0 Interrupts */ CAN3_RX1_IRQn = 139, /* CAN3 RX1 Interrupts */ LPTIM2_WKUP_IRQn = 140, /* LPTIM2 WakeUp Interrupt */ LPTIM1_WKUP_IRQn = 141, /* LPTIM1 WakeUp Interrupt */ I3C_WKUP_IRQn = 142, /* I3C WakeUp Interrupt */ RTC_IRQn = 143, /* RTC global Interrupt */ HSADC_IRQn = 144, /* HSADC global Interrupt */ UHSIF_IRQn = 145, /* UHSIF global Interrupt */ RNG_IRQn = 146, /* RNG global Interrupt */ SDIO_IRQn = 147, /* SDIO global Interrupt */ USART_WKUP_IRQn = 148, /* USART wakeup Interrupt */ } IRQn_Type; #define BASE_VECTOR "\n\ .balign 2\n\ .option push;\n\ .option norvc;\n\ j handle_reset\n\ .word 0 \n\ .word NMI_Handler /* NMI */ \n\ .word HardFault_Handler /* Hard Fault */ \n\ .word 0 \n\ .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\ .word 0 \n\ .word 0 \n\ .word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\ .word Break_Point_Handler /* Break Point */ \n\ .word 0 \n\ .word 0 \n\ .word SysTick_Handler /* SysTick */ \n \ .word SysTick_Handler /* SysTick */ \n \ .word SW_Handler /* SW */ \n \ .word 0 \n \ .word IPC_CH0_Handler \n \ .word IPC_CH1_Handler \n \ .word IPC_CH2_Handler \n \ .word IPC_CH3_Handler \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ .word HSEM_Handler \n \ .word 0 \n \ .word 0 \n \ .word 0 \n \ /* External Interrupts */ \n \ .word WWDG_IRQHandler /* Window Watchdog */ \n \ .word EXTI15_8_IRQHandler \n \ .word FLASH_IRQHandler /* Flash */ \n \ .word RCC_IRQHandler /* RCC */ \n \ .word EXTI7_0_IRQHandler \n \ .word SPI1_IRQHandler /* SPI1 */ \n \ .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n \ .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n \ .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n \ .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n \ .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n \ .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n \ .word DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */ \n \ .word USART2_IRQHandler /* USART2 */ \n \ .word I2C1_EV_IRQHandler /* I2C1 Event */ \n \ .word I2C1_ER_IRQHandler /* I2C1 Error */ \n \ .word USART1_IRQHandler /* USART1 */ \n \ .word SPI2_IRQHandler /* SPI2 */ \n \ .word SPI3_IRQHandler /* SPI3 */ \n \ .word SPI4_IRQHandler /* SPI4 */ \n \ .word I2C2_EV_IRQHandler /* I2C2 Event */ \n \ .word I2C2_ER_IRQHandler /* I2C2 Error */ \n \ .word USBPD_IRQHandler \n \ .word USBPDWakeUp_IRQHandler \n \ .word USBHS_IRQHandler /* USBHS */ \n \ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n \ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n \ .word CAN1_TX_IRQHandler /* CAN1 TX */ \n \ .word CAN1_RX0_IRQHandler /* CAN1 RX1 */ \n \ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \n \ .word USBSS_IRQHandler \n \ .word USBSS_LINK_IRQHandler \n \ .word USBHSWakeup_IRQHandler \n \ .word USBSSWakeup_IRQHandler \n \ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n \ .word USBFS_IRQHandler /* USBFS */ \n \ .word USBFSWakeUp_IRQHandler /* USBFS Wakeup */ \n \ .word ADC1_2_IRQHandler /* ADC1_2 */ \n \ .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n \ .word TIM1_UP_IRQHandler /* TIM1 Update */ \n \ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n \ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n \ .word TIM2_IRQHandler /* TIM2 */ \n \ .word TIM3_IRQHandler /* TIM3 */ \n \ .word TIM4_IRQHandler /* TIM4 */ \n \ .word TIM5_IRQHandler /* TIM5 */ \n \ .word I2C3_EV_IRQHandler /* I2C3 Event */ \n \ .word I2C3_ER_IRQHandler /* I2C3 Error */ \n \ .word I2C4_EV_IRQHandler /* I2C4 Event */ \n \ .word I2C4_ER_IRQHandler /* I2C4 Error */ \n \ .word QSPI1_IRQHandler \n \ .word SERDES_IRQHandler \n \ .word USART3_IRQHandler /* USART3 */ \n \ .word USART4_IRQHandler /* USART4 */ \n \ .word TIM8_BRK_IRQHandler /* TIM8 Break */ \n \ .word TIM8_UP_IRQHandler /* TIM8 Update */ \n \ .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ \n \ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ \n \ .word TIM9_IRQHandler /* TIM9 */ \n \ .word TIM10_IRQHandler /* TIM10 */ \n \ .word TIM11_IRQHandler /* TIM11 */ \n \ .word TIM12_IRQHandler /* TIM12 */ \n \ .word FMC_IRQHandler \n \ .word SDMMC_IRQHandler \n \ .word LPTIM1_IRQHandler \n \ .word LPTIM2_IRQHandler \n \ .word USART5_IRQHandler /* USART5 */ \n \ .word USART6_IRQHandler /* USART6 */ \n \ .word TIM6_IRQHandler /* TIM6 */ \n \ .word TIM7_IRQHandler /* TIM7 */ \n \ .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ \n \ .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ \n \ .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ \n \ .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ \n \ .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ \n \ .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ \n \ .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ \n \ .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ \n \ .word ETH_IRQHandler /* ETH */ \n \ .word ETHWakeUp_IRQHandler /* ETH WakeUp */ \n \ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ \n \ .word CAN2_TX_IRQHandler /* CAN2 TX */ \n \ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ \n \ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ \n \ .word USART7_IRQHandler /* USART7 */ \n \ .word USART8_IRQHandler /* USART8 */ \n \ .word I3C_EV_IRQHandler /* I3C Event */ \n \ .word I3C_ER_IRQHandler /* I3C Error */ \n \ .word DVP_IRQHandler /* DVP */ \n \ .word ECDC_IRQHandler \n \ .word PIOC_IRQHandler \n \ .word SAI_IRQHandler \n \ .word LTDC_IRQHandler \n \ .word GPHA_IRQHandler \n \ .word 0 \n \ .word DFSDM0_IRQHandler \n \ .word DFSDM1_IRQHandler \n \ .word 0 \n \ .word 0 \n \ .word SWPMI_IRQHandler \n \ .word 0 \n \ .word 0 \n \ .word QSPI2_IRQHandler \n \ .word SWPMI_WKUP_IRQHandler \n \ .word CAN3_SCE_IRQHandler /* CAN3 SCE */ \n \ .word CAN3_TX_IRQHandler /* CAN3 TX */ \n \ .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ \n \ .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ \n \ .word LPTIM2_WKUP_IRQHandler \n \ .word LPTIM1_WKUP_IRQHandler \n \ .word I3C_WKUP_IRQHandler \n \ .word RTC_IRQHandler /* RTC */ \n \ .word HSADC_IRQHandler \n \ .word UHSIF_IRQHandler \n \ .word RNG_IRQHandler /* RNG */ \n \ .word SDIO_IRQHandler /* SDIO */ \n \ .word USART_WKUP_IRQHandler \n " #define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR "\n.option pop;\n" /* memory mapped structure for SysTick */ typedef struct { __IO uint32_t CTLR; __IO uint32_t SR; __IO uint64_t CNT; uint32_t RESERVED0; __IO uint64_t CMP; } SysTick_Type; #endif /* __ASSEMBLER__*/ #define HardFault_IRQn EXC_IRQn #define ADC1_2_IRQn ADC_IRQn /* Standard Peripheral Library old definitions (maintained for legacy purpose) */ #define HSI_Value HSI_VALUE #define HSE_Value HSE_VALUE #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT #ifndef __ASSEMBLER__ /* Analog to Digital Converter */ typedef struct { __IO uint32_t STATR; __IO uint32_t CTLR1; __IO uint32_t CTLR2; __IO uint32_t SAMPTR1; __IO uint32_t SAMPTR2; __IO uint32_t IOFR1; __IO uint32_t IOFR2; __IO uint32_t IOFR3; __IO uint32_t IOFR4; __IO uint32_t WDHTR; __IO uint32_t WDLTR; __IO uint32_t RSQR1; __IO uint32_t RSQR2; __IO uint32_t RSQR3; __IO uint32_t ISQR; __IO uint32_t IDATAR1; __IO uint32_t IDATAR2; __IO uint32_t IDATAR3; __IO uint32_t IDATAR4; __IO uint32_t RDATAR; uint32_t RESERVED0; __IO uint32_t AUX; __IO uint32_t DRV; } ADC_TypeDef; /* Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TXMIR; __IO uint32_t TXMDTR; __IO uint32_t TXMDLR; __IO uint32_t TXMDHR; } CAN_TxMailBox_TypeDef; /* Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RXMIR; __IO uint32_t RXMDTR; __IO uint32_t RXMDLR; __IO uint32_t RXMDHR; } CAN_FIFOMailBox_TypeDef; /* Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; /* Controller Area Network */ typedef struct { __IO uint32_t CTLR; __IO uint32_t STATR; __IO uint32_t TSTATR; __IO uint32_t RFIFO0; __IO uint32_t RFIFO1; __IO uint32_t INTENR; __IO uint32_t ERRSR; __IO uint32_t BTIMR; __IO uint32_t TTCTLR; __IO uint32_t TTCNT; __IO uint32_t TERR_CNT; uint32_t RESERVED0[85]; CAN_TxMailBox_TypeDef sTxMailBox[3]; CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FCTLR; __IO uint32_t FMCFGR; __IO uint32_t FMCFGR_CAN3; __IO uint32_t FSCFGR; __IO uint32_t FSCFGR_CAN3; __IO uint32_t FAFIFOR; __IO uint32_t FAFIFOR_CAN3; __IO uint32_t FWR; __IO uint32_t FWR_CAN3; uint32_t RESERVED2[7]; CAN_FilterRegister_TypeDef sFilterRegister[42]; } CAN_TypeDef; /* CRC Calculation Unit */ typedef struct { __IO uint32_t DATAR; __IO uint8_t IDATAR; uint8_t RESERVED0; uint16_t RESERVED1; __IO uint32_t CTLR; } CRC_TypeDef; /* Digital to Analog Converter */ typedef struct { __IO uint32_t CTLR; __IO uint32_t SWTR; __IO uint32_t R12BDHR1; __IO uint32_t L12BDHR1; __IO uint32_t R8BDHR1; __IO uint32_t R12BDHR2; __IO uint32_t L12BDHR2; __IO uint32_t R8BDHR2; __IO uint32_t RD12BDHR; __IO uint32_t LD12BDHR; __IO uint32_t RD8BDHR; __IO uint32_t DOR1; __IO uint32_t DOR2; } DAC_TypeDef; /* DMA Controller */ typedef struct { __IO uint32_t CFGR; __IO uint32_t CNTR; __IO uint32_t PADDR; __IO uint32_t MADDR; __IO uint32_t M1ADDR; } DMA_Channel_TypeDef; typedef struct { __IO uint32_t INTFR; __IO uint32_t INTFCR; } DMA_TypeDef; /* DMA MUX Controller */ typedef struct { __IO uint32_t CFGR0_3; __IO uint32_t CFGR4_7; __IO uint32_t CFGR8_11; __IO uint32_t CFGR12_15; } DMAMUX_TypeDef; /* External Interrupt/Event Controller */ typedef struct { __IO uint32_t INTENR; __IO uint32_t EVENR; __IO uint32_t RTENR; __IO uint32_t FTENR; __IO uint32_t SWIEVR; __IO uint32_t INTFR; } EXTI_TypeDef; /* FLASH Registers */ typedef struct { __IO uint32_t ACTLR; __IO uint32_t KEYR; __IO uint32_t OBKEYR; __IO uint32_t STATR; __IO uint32_t CTLR; __IO uint32_t ADDR; __IO uint32_t RESERVED; __IO uint32_t OBR; __IO uint32_t WPR; __IO uint32_t MODEKEYR; __IO uint32_t BOOT_MODEKEYR; } FLASH_TypeDef; /* Option Bytes Registers */ typedef struct { __IO uint16_t RDPR; __IO uint16_t USER; __IO uint16_t Data0; __IO uint16_t Data1; __IO uint16_t WRPR0; __IO uint16_t WRPR1; __IO uint16_t WRPR2; __IO uint16_t WRPR3; } OB_TypeDef; /* FMC Bank1 Registers */ typedef struct { __IO uint32_t BTCR[8]; } FMC_Bank1_TypeDef; /* FMC Bank1E Registers */ typedef struct { __IO uint32_t BWTR[7]; } FMC_Bank1E_TypeDef; /* FMC Bank3 Registers */ typedef struct { __IO uint32_t PCR; __IO uint32_t SR; __IO uint32_t PMEM; __IO uint32_t PATT; uint32_t RESERVED0; __IO uint32_t ECCR; } FMC_Bank3_TypeDef; /* FMC Bank5_6 Registers */ typedef struct { __IO uint32_t SDCR[2]; __IO uint32_t SDTR[2]; __IO uint32_t SDCMR; __IO uint32_t SDRTR; __IO uint32_t SDSR; uint32_t RESERVED0[9]; __IO uint32_t MISC; } FMC_Bank5_6_TypeDef; /* General Purpose I/O */ typedef enum { GPIO_CFGLR_IN_ANALOG = 0, GPIO_CFGLR_IN_FLOAT = 4, GPIO_CFGLR_IN_PUPD = 8, GPIO_CFGLR_OUT_PP = 1, GPIO_CFGLR_OUT_OD = 5, GPIO_CFGLR_OUT_AF_PP = 9, GPIO_CFGLR_OUT_AF_OD = 13, } GPIO_CFGLR_PIN_MODE_Typedef; typedef union { uint32_t __FULL; struct { GPIO_CFGLR_PIN_MODE_Typedef PIN0 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN1 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN2 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN3 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN4 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN5 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN6 :4; GPIO_CFGLR_PIN_MODE_Typedef PIN7 :4; }; } GPIO_CFGLR_t; typedef union { uint32_t __FULL; const struct { uint32_t IDR0 :1; uint32_t IDR1 :1; uint32_t IDR2 :1; uint32_t IDR3 :1; uint32_t IDR4 :1; uint32_t IDR5 :1; uint32_t IDR6 :1; uint32_t IDR7 :1; uint32_t IDR8 :1; uint32_t IDR9 :1; uint32_t IDR10 :1; uint32_t IDR11:1; uint32_t IDR12 :1; uint32_t IDR13 :1; uint32_t IDR14 :1; uint32_t IDR15 :1; uint32_t :16; }; } GPIO_INDR_t; typedef union { uint32_t __FULL; struct { uint32_t ODR0 :1; uint32_t ODR1 :1; uint32_t ODR2 :1; uint32_t ODR3 :1; uint32_t ODR4 :1; uint32_t ODR5 :1; uint32_t ODR6 :1; uint32_t ODR7 :1; uint32_t ODR8 :1; uint32_t ODR9 :1; uint32_t ODR10 :1; uint32_t ODR11 :1; uint32_t ODR12 :1; uint32_t ODR13 :1; uint32_t ODR14 :1; uint32_t ODR15 :1; uint32_t :16; }; } GPIO_OUTDR_t; typedef union { uint32_t __FULL; struct { uint32_t BS0 :1; uint32_t BS1 :1; uint32_t BS2 :1; uint32_t BS3 :1; uint32_t BS4 :1; uint32_t BS5 :1; uint32_t BS6 :1; uint32_t BS7 :1; uint32_t BS8 :1; uint32_t BS9 :1; uint32_t BS10 :1; uint32_t BS11 :1; uint32_t BS12 :1; uint32_t BS13 :1; uint32_t BS14 :1; uint32_t BS15 :1; uint32_t BR0 :1; uint32_t BR1 :1; uint32_t BR2 :1; uint32_t BR3 :1; uint32_t BR4 :1; uint32_t BR5 :1; uint32_t BR6 :1; uint32_t BR7 :1; uint32_t BR8 :1; uint32_t BR9 :1; uint32_t BR10 :1; uint32_t BR11 :1; uint32_t BR12 :1; uint32_t BR13 :1; uint32_t BR14 :1; uint32_t BR15 :1; }; } GPIO_BSHR_t; typedef union { uint32_t __FULL; struct { uint32_t BR0 :1; uint32_t BR1 :1; uint32_t BR2 :1; uint32_t BR3 :1; uint32_t BR4 :1; uint32_t BR5 :1; uint32_t BR6 :1; uint32_t BR7 :1; uint32_t BR8 :1; uint32_t BR9 :1; uint32_t BR10 :1; uint32_t BR11 :1; uint32_t BR12 :1; uint32_t BR13 :1; uint32_t BR14 :1; uint32_t BR15 :1; uint32_t :16; }; } GPIO_BCR_t; typedef union { uint32_t __FULL; struct { uint32_t LCK0 :1; uint32_t LCK1 :1; uint32_t LCK2 :1; uint32_t LCK3 :1; uint32_t LCK4 :1; uint32_t LCK5 :1; uint32_t LCK6 :1; uint32_t LCK7 :1; uint32_t LCK8 :1; uint32_t LCK9 :1; uint32_t LCK10 :1; uint32_t LCK11 :1; uint32_t LCK12 :1; uint32_t LCK13 :1; uint32_t LCK14 :1; uint32_t LCK15 :1; uint32_t LCKK :1; uint32_t :15; }; } GPIO_LCKR_t; typedef union { uint32_t __FULL; struct { uint32_t SPEED0 :1; uint32_t SPEED1 :1; uint32_t SPEED2 :1; uint32_t SPEED3 :1; uint32_t SPEED4 :1; uint32_t SPEED5 :1; uint32_t SPEED6 :1; uint32_t SPEED7 :1; uint32_t SPEED8 :1; uint32_t SPEED9 :1; uint32_t SPEED10 :1; uint32_t SPEED11 :1; uint32_t SPEED12 :1; uint32_t SPEED13 :1; uint32_t SPEED14 :1; uint32_t SPEED15 :1; uint32_t SPEED16 :1; uint32_t SPEED17 :1; uint32_t SPEED18 :1; uint32_t SPEED19 :1; uint32_t SPEED20 :1; uint32_t SPEED21 :1; uint32_t SPEED22 :1; uint32_t SPEED23 :1; uint32_t SPEED24 :1; uint32_t SPEED25 :1; uint32_t SPEED26 :1; uint32_t SPEED27 :1; uint32_t SPEED28 :1; uint32_t SPEED29 :1; uint32_t SPEED30 :1; uint32_t SPEED31 :1; }; } GPIO_SPEED_t; typedef struct { __IO uint32_t CFGLR; __IO uint32_t CFGHR; __I uint32_t INDR; __IO uint32_t OUTDR; __IO uint32_t BSHR; __IO uint32_t BCR; __IO uint32_t LCKR; __IO uint32_t SPEED; } GPIO_TypeDef; #define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t) { .__FULL = gpio->field }) #define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t) __VA_ARGS__).__FULL #define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} /* Alternate Function I/O */ typedef struct { __IO uint32_t PCFR1; __IO uint32_t GPIOA_AFLR; __IO uint32_t GPIOA_AFHR; __IO uint32_t GPIOB_AFLR; __IO uint32_t GPIOB_AFHR; __IO uint32_t GPIOC_AFLR; __IO uint32_t GPIOC_AFHR; __IO uint32_t GPIOD_AFLR; __IO uint32_t GPIOD_AFHR; __IO uint32_t GPIOE_AFLR; __IO uint32_t GPIOE_AFHR; __IO uint32_t GPIOF_AFLR; __IO uint32_t GPIOF_AFHR; uint32_t RESERVED0[2]; __IO uint32_t EXTICR1; __IO uint32_t EXTICR2; } AFIO_TypeDef; /* Inter Integrated Circuit Interface */ typedef struct { __IO uint16_t CTLR1; uint16_t RESERVED0; __IO uint16_t CTLR2; uint16_t RESERVED1; __IO uint16_t OADDR1; uint16_t RESERVED2; __IO uint16_t OADDR2; uint16_t RESERVED3; __IO uint16_t DATAR; uint16_t RESERVED4; __IO uint16_t STAR1; uint16_t RESERVED5; __IO uint16_t STAR2; uint16_t RESERVED6; __IO uint16_t CKCFGR; uint16_t RESERVED7; __IO uint16_t RTR; uint16_t RESERVED8; } I2C_TypeDef; /* Inter Integrated 3 Circuit Interface */ typedef struct { __IO uint32_t CTLR; __IO uint32_t CFGR; uint32_t RESERVED0[2]; __IO uint32_t RDBR; __IO uint32_t RDWR; __IO uint32_t TDBR; __IO uint32_t TDWR; __IO uint32_t IBIDR; __IO uint32_t TGTTDR; uint32_t RESERVED1; __IO uint32_t RESET; __IO uint32_t STATR; __IO uint32_t STATER; uint32_t RESERVED2[2]; __IO uint32_t RMR; uint32_t RESERVED3[3]; __IO uint32_t EVR; __IO uint32_t INTENR; __IO uint32_t CEVR; uint32_t RESERVED4; __IO uint32_t DEVR0; __IO uint32_t DEVR1; __IO uint32_t DEVR2; __IO uint32_t DEVR3; __IO uint32_t DEVR4; uint32_t RESERVED5[7]; __IO uint32_t MAXRLR; __IO uint32_t MAXWLR; uint32_t RESERVED6[2]; __IO uint32_t TIMINGR0; __IO uint32_t TIMINGR1; __IO uint32_t TIMINGR2; uint32_t RESERVED7[5]; __IO uint32_t BCR; __IO uint32_t DCR; __IO uint32_t GETCAPR; __IO uint32_t CRCAPR; __IO uint32_t GETMDSR; __IO uint32_t EPIDR; } I3C_TypeDef; /* Independent WatchDog */ typedef struct { __IO uint32_t CTLR; __IO uint32_t PSCR; __IO uint32_t RLDR; __IO uint32_t STATR; } IWDG_TypeDef; /* Power Control */ typedef struct { __IO uint32_t CTLR; __IO uint32_t CSR; } PWR_TypeDef; /* Reset and Clock Control */ typedef struct { __IO uint32_t CTLR; __IO uint32_t CFGR0; __IO uint32_t PLLCFGR; __IO uint32_t INTR; __IO uint32_t HB2PRSTR; __IO uint32_t HB1PRSTR; __IO uint32_t HBPCENR; __IO uint32_t HB2PCENR; __IO uint32_t HB1PCENR; __IO uint32_t BDCTLR; __IO uint32_t RSTSCKR; __IO uint32_t HBRSTR; __IO uint32_t CFGR2; __IO uint32_t PLLCFGR2; } RCC_TypeDef; /* Real-Time Clock */ typedef struct { __IO uint16_t CTLRH; uint16_t RESERVED0; __IO uint16_t CTLRL; uint16_t RESERVED1; __IO uint16_t PSCRH; uint16_t RESERVED2; __IO uint16_t PSCRL; uint16_t RESERVED3; __IO uint16_t DIVH; uint16_t RESERVED4; __IO uint16_t DIVL; uint16_t RESERVED5; __IO uint16_t CNTH; uint16_t RESERVED6; __IO uint16_t CNTL; uint16_t RESERVED7; __IO uint16_t ALRMH; uint16_t RESERVED8; __IO uint16_t ALRML; uint16_t RESERVED9; } RTC_TypeDef; /* SDIO Registers */ typedef struct { __IO uint32_t POWER; __IO uint32_t CLKCR; __IO uint32_t ARG; __IO uint32_t CMD; __I uint32_t RESPCMD; __I uint32_t RESP1; __I uint32_t RESP2; __I uint32_t RESP3; __I uint32_t RESP4; __IO uint32_t DTIMER; __IO uint32_t DLEN; __IO uint32_t DCTRL; __I uint32_t DCOUNT; __I uint32_t STA; __IO uint32_t ICR; __IO uint32_t MASK; uint32_t RESERVED0[2]; __I uint32_t FIFOCNT; uint32_t RESERVED1[5]; __IO uint32_t DCTRL2; uint32_t RESERVED2[7]; __IO uint32_t FIFO; } SDIO_TypeDef; /* Serial Peripheral Interface */ typedef struct { __IO uint16_t CTLR1; uint16_t RESERVED0; __IO uint16_t CTLR2; uint16_t RESERVED1; __IO uint16_t STATR; uint16_t RESERVED2; __IO uint16_t DATAR; uint16_t RESERVED3; __IO uint16_t CRCR; uint16_t RESERVED4; __IO uint16_t RCRCR; uint16_t RESERVED5; __IO uint16_t TCRCR; uint16_t RESERVED6; __IO uint16_t I2SCFGR; uint16_t RESERVED7; __IO uint16_t I2SPR; uint16_t RESERVED8; __IO uint16_t HSCR; uint16_t RESERVED9; } SPI_TypeDef; /* TIM */ typedef struct { __IO uint16_t CTLR1; uint16_t RESERVED0; __IO uint16_t CTLR2; uint16_t RESERVED1; __IO uint16_t SMCFGR; uint16_t RESERVED2; __IO uint16_t DMAINTENR; uint16_t RESERVED3; __IO uint16_t INTFR; uint16_t RESERVED4; __IO uint16_t SWEVGR; uint16_t RESERVED5; __IO uint16_t CHCTLR1; uint16_t RESERVED6; __IO uint16_t CHCTLR2; uint16_t RESERVED7; __IO uint16_t CCER; uint16_t RESERVED8; union { __IO uint32_t CNT_32; //TIM9,10,11,12 struct { __IO uint16_t CNT; uint16_t RESERVED9; }; }; __IO uint16_t PSC; uint16_t RESERVED10; union { __IO uint32_t ATRLR_32;//TIM9,10,11,12 struct { __IO uint16_t ATRLR; uint16_t RESERVED11; }; }; __IO uint16_t RPTCR; uint16_t RESERVED12; union { __IO uint32_t CH1CVR_32; struct { __IO uint16_t CH1CVR; uint16_t RESERVED13; }; }; union { __IO uint32_t CH2CVR_32; struct { __IO uint16_t CH2CVR; uint16_t RESERVED14; }; }; union { __IO uint32_t CH3CVR_32; struct { __IO uint16_t CH3CVR; uint16_t RESERVED15; }; }; union { __IO uint32_t CH4CVR_32; struct { __IO uint16_t CH4CVR; uint16_t RESERVED16; }; }; __IO uint16_t BDTR; uint16_t RESERVED17; __IO uint16_t DMACFGR; uint16_t RESERVED18; __IO uint16_t DMAADR; uint16_t RESERVED19; __IO uint16_t AUX; uint16_t RESERVED20; } TIM_TypeDef; /* Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t STATR; uint16_t RESERVED0; __IO uint16_t DATAR; uint16_t RESERVED1; __IO uint16_t BRR; uint16_t RESERVED2; __IO uint16_t CTLR1; uint16_t RESERVED3; __IO uint16_t CTLR2; uint16_t RESERVED4; __IO uint16_t CTLR3; uint16_t RESERVED5; __IO uint16_t GPR; uint16_t RESERVED6; __IO uint16_t CTLR4; uint16_t RESERVED7; } USART_TypeDef; /* Window WatchDog */ typedef struct { __IO uint32_t CTLR; __IO uint32_t CFGR; __IO uint32_t STATR; } WWDG_TypeDef; /* OPA Registers */ typedef struct { __IO uint32_t CTLR1; __IO uint32_t CTLR2; __IO uint32_t CTLR3; __IO uint32_t CMP_CTLR; __IO uint32_t CMP_STATR; } OPA_TypeDef; /* RNG Registers */ typedef struct { __IO uint32_t CR; __IO uint32_t SR; __IO uint32_t DR; } RNG_TypeDef; /* LPTIM Registers */ typedef struct { __IO uint32_t ISR; __IO uint32_t ICR; __IO uint32_t IER; __IO uint32_t CFGR; __IO uint32_t CR; __IO uint16_t CMP; uint16_t Reserved0; __IO uint16_t ARR; uint16_t Reserved1; __IO uint16_t CNT; uint16_t Reserved2; } LPTIM_TypeDef; /* DVP Registers */ typedef struct { __IO uint8_t CR0; __IO uint8_t CR1; __IO uint8_t IER; __IO uint8_t Reserved0; __IO uint16_t ROW_NUM; __IO uint16_t COL_NUM; __IO uint32_t DMA_BUF0; __IO uint32_t DMA_BUF1; __IO uint8_t IFR; __IO uint8_t STATUS; __IO uint16_t Reserved1; __IO uint16_t ROW_CNT; __IO uint16_t Reserved2; __IO uint16_t HOFFCNT; __IO uint16_t VST; __IO uint16_t CAPCNT; __IO uint16_t VLINE; __IO uint32_t DR; } DVP_TypeDef; /* PD Registers */ typedef struct { union { __IO uint32_t USBPD_CONFIG; struct { __IO uint16_t CONFIG; __IO uint16_t BMC_CLK_CNT; }; }; union { __IO uint32_t USBPD_CONTROL; struct { union { __IO uint16_t R16_CONTROL; struct { __IO uint8_t CONTROL; __IO uint8_t TX_SEL; }; }; __IO uint16_t BMC_TX_SZ; }; }; union { __IO uint32_t USBPD_STATUS; struct { union { __IO uint16_t R16_STATUS; struct { __IO uint8_t DATA_BUF; __IO uint8_t STATUS; }; }; __IO uint16_t BMC_BYTE_CNT; }; }; union { __IO uint32_t USBPD_PORT; struct { __IO uint16_t PORT_CC1; __IO uint16_t PORT_CC2; }; }; __IO uint32_t USBPD_DMA; } USBPD_TypeDef; /* USBSS Deveice Registers */ typedef struct { __IO uint8_t UEP_TX_CFG; // 0x0 __IO uint8_t UEP_TX_CR; // 0x1 __IO uint8_t UEP_TX_SEQ; // 0x2 __IO uint8_t UEP_TX_ST; // 0x3 __IO uint8_t UEP_TX_CHAIN_CR; // 0x4 __IO uint8_t UEP_TX_CHAIN_ST; // 0x5 __IO uint16_t UEP_TX_CHAIN_LEN; // 0x6 __IO uint8_t UEP_TX_CHAIN_EXP_NUMP; // 0x8 __IO uint8_t UEP_TX_CHAIN_NUMP; // 0x9 __IO uint16_t UEP_TX_DMA_OFS; // 0xA __IO uint32_t UEP_TX_DMA; // 0xC } USBSS_EP_TX_TypeDef; typedef struct { __IO uint8_t UEP_RX_CFG; // 0x0 __IO uint8_t UEP_RX_CR; // 0x1 __IO uint8_t UEP_RX_SEQ; // 0x2 __IO uint8_t UEP_RX_ST; // 0x3 __IO uint8_t UEP_RX_CHAIN_CR; // 0x4 __IO uint8_t UEP_RX_CHAIN_ST; // 0x5 __IO uint16_t UEP_RX_CHAIN_LEN; // 0x6 __IO uint8_t UEP_RX_CHAIN_MAX_NUMP; // 0x8 __IO uint8_t UEP_RX_CHAIN_NUMP; // 0x9 __IO uint16_t UEP_RX_DMA_OFS; // 0xA __IO uint32_t UEP_RX_DMA; // 0xC } USBSS_EP_RX_TypeDef; typedef struct { __IO uint32_t LINK_CFG; __IO uint32_t LINK_CTRL; __IO uint32_t LINK_INT_CTRL; __IO uint32_t LINK_INT_FLAG; __IO uint32_t LINK_STATUS; uint8_t Reserved0[3]; __IO uint8_t LINK_ITP_PRE; uint8_t Reserved1[5]; __IO uint8_t LINK_U2_INACT_TIMER; uint8_t Reserved2[10]; __IO uint8_t LINK_U1_WKUP_FILTER; uint8_t Reserved3[1]; __IO uint16_t LINK_U1_WKUP_TMR; __IO uint8_t LINK_U2_WKUP_FILTER; uint8_t Reserved4[3]; __IO uint8_t LINK_U3_WKUP_FILTER; uint8_t Reserved5[1]; __IO uint16_t LINK_U3_WKUP_TMR; uint8_t Reserved6[12]; __IO uint16_t LINK_ISO_DLY; uint8_t Reserved7[14]; __IO uint16_t LINK_LPM_CR; uint8_t Reserved8[2]; __IO uint32_t LINK_LMP_PORT_CAP; __IO uint32_t LINK_LMP_RX_DATA0; __IO uint32_t LINK_LMP_RX_DATA1; __IO uint32_t LINK_LMP_RX_DATA2; __IO uint32_t LINK_LMP_TX_DATA0; __IO uint32_t LINK_LMP_TX_DATA1; __IO uint32_t LINK_LMP_TX_DATA2; __IO uint32_t USB_CONTROL; __IO uint32_t USB_STATUS; __IO uint32_t USB_ITP; __IO uint32_t USB_ITP_ADJ; __IO uint16_t UEP_TX_EN; __IO uint16_t UEP_RX_EN; __IO uint32_t UEP0_TX_CTRL; __IO uint32_t UEP0_RX_CTRL; __IO uint32_t UEP0_TX_DMA; __IO uint32_t UEP0_RX_DMA; __IO uint32_t UEP0_TX_DMA_OFS; __IO uint32_t UEP0_RX_DMA_OFS; uint8_t Reserved9[36]; __IO USBSS_EP_TX_TypeDef EP1_TX; __IO USBSS_EP_RX_TypeDef EP1_RX; __IO USBSS_EP_TX_TypeDef EP2_TX; __IO USBSS_EP_RX_TypeDef EP2_RX; __IO USBSS_EP_TX_TypeDef EP3_TX; __IO USBSS_EP_RX_TypeDef EP3_RX; __IO USBSS_EP_TX_TypeDef EP4_TX; __IO USBSS_EP_RX_TypeDef EP4_RX; __IO USBSS_EP_TX_TypeDef EP5_TX; __IO USBSS_EP_RX_TypeDef EP5_RX; __IO USBSS_EP_TX_TypeDef EP6_TX; __IO USBSS_EP_RX_TypeDef EP6_RX; __IO USBSS_EP_TX_TypeDef EP7_TX; __IO USBSS_EP_RX_TypeDef EP7_RX; } USBSSD_TypeDef; typedef struct { __IO uint32_t LINK_CFG; __IO uint32_t LINK_CTRL; __IO uint32_t LINK_INT_CTRL; __IO uint32_t LINK_INT_FLAG; __IO uint32_t LINK_STATUS; uint8_t Reserved0[3]; __IO uint8_t LINK_ITP_PRE; uint8_t Reserved1[5]; __IO uint8_t LINK_U2_INACT_TIMER; uint8_t Reserved2[10]; __IO uint8_t LINK_U1_WKUP_FILTER; uint8_t Reserved3[3]; __IO uint8_t LINK_U2_WKUP_FILTER; uint8_t Reserved4[3]; __IO uint8_t LINK_U3_WKUP_FILTER; uint8_t Reserved5[15]; __IO uint16_t LINK_ISO_DLY; uint8_t Reserved6[14]; __IO uint16_t LINK_LPM_CR; uint8_t Reserved7[2]; __IO uint32_t LINK_LMP_PORT_CAP; __IO uint32_t LINK_LMP_RX_DATA0; __IO uint32_t LINK_LMP_RX_DATA1; __IO uint32_t LINK_LMP_RX_DATA2; __IO uint32_t LINK_LMP_TX_DATA0; __IO uint32_t LINK_LMP_TX_DATA1; __IO uint32_t LINK_LMP_TX_DATA2; __IO uint32_t USB_CONTROL; __IO uint32_t USB_STATUS; __IO uint32_t USB_ITP; __IO uint32_t USB_ITP_ADJ; __IO uint16_t UEP_TX_EN; __IO uint16_t UEP_RX_EN; __IO uint32_t UH_TX_CTRL; __IO uint32_t UH_RX_CTRL; __IO uint32_t UH_TX_DMA; __IO uint32_t UH_RX_DMA; __IO uint32_t UH_TX_DMA_OFS; __IO uint32_t UH_RX_DMA_OFS; __IO uint16_t HOST_TX_NUMP; __IO uint16_t HOST_RX_NUMP; __IO uint32_t HOST_STATUS; __IO uint16_t HOST_TX_FC_STATUS; __IO uint16_t HOST_RX_FC_STATUS; __IO uint32_t TP_RX_DATA0; __IO uint32_t TP_RX_DATA1; __IO uint32_t TP_RX_DATA2; } USBSSH_TypeDef; /* USBHS Device Registers */ typedef struct { __IO uint8_t CONTROL; __IO uint8_t BASE_MODE; __IO uint8_t INT_EN; __IO uint8_t DEV_AD; __IO uint8_t WAKE_CTRL; __IO uint8_t TEST_MODE; __IO uint16_t LPM_DATA; __IO uint8_t INT_FG; __IO uint8_t INT_ST; __IO uint8_t MIS_ST; uint8_t RESERVED0; __IO uint16_t FRAME_NO; __IO uint16_t BUS; __IO uint16_t UEP_TX_EN; __IO uint16_t UEP_RX_EN; __IO uint16_t UEP_TX_TOG_AUTO; __IO uint16_t UEP_RX_TOG_AUTO; __IO uint8_t UEP_TX_BURST; __IO uint8_t UEP_TX_BURST_MODE; __IO uint8_t UEP_RX_BURST; __IO uint8_t UEP_RX_RES_MODE; __IO uint32_t UEP_AF_MODE; __IO uint32_t UEP0_DMA; __IO uint32_t UEP1_RX_DMA; __IO uint32_t UEP2_RX_DMA; __IO uint32_t UEP3_RX_DMA; __IO uint32_t UEP4_RX_DMA; __IO uint32_t UEP5_RX_DMA; __IO uint32_t UEP6_RX_DMA; __IO uint32_t UEP7_RX_DMA; __IO uint32_t UEP1_TX_DMA; __IO uint32_t UEP2_TX_DMA; __IO uint32_t UEP3_TX_DMA; __IO uint32_t UEP4_TX_DMA; __IO uint32_t UEP5_TX_DMA; __IO uint32_t UEP6_TX_DMA; __IO uint32_t UEP7_TX_DMA; __IO uint32_t UEP0_MAX_LEN; __IO uint32_t UEP1_MAX_LEN; __IO uint32_t UEP2_MAX_LEN; __IO uint32_t UEP3_MAX_LEN; __IO uint32_t UEP4_MAX_LEN; __IO uint32_t UEP5_MAX_LEN; __IO uint32_t UEP6_MAX_LEN; __IO uint32_t UEP7_MAX_LEN; __IO uint16_t UEP0_RX_LEN; uint16_t RESERVED1; __IO uint16_t UEP1_RX_LEN; __IO uint16_t UEP1_RX_SIZE; __IO uint16_t UEP2_RX_LEN; __IO uint16_t UEP2_RX_SIZE; __IO uint16_t UEP3_RX_LEN; __IO uint16_t UEP3_RX_SIZE; __IO uint16_t UEP4_RX_LEN; __IO uint16_t UEP4_RX_SIZE; __IO uint16_t UEP5_RX_LEN; __IO uint16_t UEP5_RX_SIZE; __IO uint16_t UEP6_RX_LEN; __IO uint16_t UEP6_RX_SIZE; __IO uint16_t UEP7_RX_LEN; __IO uint16_t UEP7_RX_SIZE; __IO uint16_t UEP0_TX_LEN; __IO uint8_t UEP0_TX_CTRL; __IO uint8_t UEP0_RX_CTRL; __IO uint16_t UEP1_TX_LEN; __IO uint8_t UEP1_TX_CTRL; __IO uint8_t UEP1_RX_CTRL; __IO uint16_t UEP2_TX_LEN; __IO uint8_t UEP2_TX_CTRL; __IO uint8_t UEP2_RX_CTRL; __IO uint16_t UEP3_TX_LEN; __IO uint8_t UEP3_TX_CTRL; __IO uint8_t UEP3_RX_CTRL; __IO uint16_t UEP4_TX_LEN; __IO uint8_t UEP4_TX_CTRL; __IO uint8_t UEP4_RX_CTRL; __IO uint16_t UEP5_TX_LEN; __IO uint8_t UEP5_TX_CTRL; __IO uint8_t UEP5_RX_CTRL; __IO uint16_t UEP6_TX_LEN; __IO uint8_t UEP6_TX_CTRL; __IO uint8_t UEP6_RX_CTRL; __IO uint16_t UEP7_TX_LEN; __IO uint8_t UEP7_TX_CTRL; __IO uint8_t UEP7_RX_CTRL; __IO uint16_t UEP_TX_ISO; __IO uint16_t UEP_RX_ISO; __IO uint32_t UEP1_RX_FIFO; __IO uint32_t UEP2_RX_FIFO; __IO uint32_t UEP3_RX_FIFO; __IO uint32_t UEP4_RX_FIFO; __IO uint32_t UEP5_RX_FIFO; __IO uint32_t UEP6_RX_FIFO; __IO uint32_t UEP7_RX_FIFO; __IO uint32_t UEP1_TX_FIFO; __IO uint32_t UEP2_TX_FIFO; __IO uint32_t UEP3_TX_FIFO; __IO uint32_t UEP4_TX_FIFO; __IO uint32_t UEP5_TX_FIFO; __IO uint32_t UEP6_TX_FIFO; __IO uint32_t UEP7_TX_FIFO; } USBHSD_TypeDef; /* USBHS Host Registers */ typedef struct __attribute__((packed)) { __IO uint8_t CFG; uint8_t RESERVED0; __IO uint8_t INT_EN; __IO uint8_t DEV_ADDR; __IO uint32_t CONTROL; __IO uint8_t INT_FLAG; __IO uint8_t INT_ST; __IO uint8_t MIS_ST; uint8_t RESERVED1; __IO uint32_t LPM; __IO uint32_t SPLIT; __IO uint32_t FRAME; __IO uint32_t TX_LEN; __IO uint32_t RX_LEN; __IO uint32_t RX_MAX_LEN; __IO uint32_t RX_DMA; __IO uint32_t TX_DMA; __IO uint32_t PORT_CTRL; __IO uint8_t PORT_CFG; uint8_t RESERVED2; __IO uint8_t PORT_INT_EN; __IO uint8_t PORT_TEST_CT; __IO uint16_t PORT_STATUS; __IO uint8_t PORT_STATUS_CHG; uint8_t RESERVED3[5]; __IO uint32_t ROOT_BC_CTRL; } USBHSH_TypeDef; /* USBFS Device Registers */ typedef struct { __IO uint8_t BASE_CTRL; __IO uint8_t UDEV_CTRL; __IO uint8_t INT_EN; __IO uint8_t DEV_ADDR; uint8_t RESERVED0; __IO uint8_t MIS_ST; __IO uint8_t INT_FG; __IO uint8_t INT_ST; __IO uint16_t RX_LEN; uint16_t RESERVED1; __IO uint8_t UEP4_1_MOD; __IO uint8_t UEP2_3_MOD; __IO uint8_t UEP5_6_MOD; __IO uint8_t UEP7_MOD; __IO uint32_t UEP0_DMA; __IO uint32_t UEP1_DMA; __IO uint32_t UEP2_DMA; __IO uint32_t UEP3_DMA; __IO uint32_t UEP4_DMA; __IO uint32_t UEP5_DMA; __IO uint32_t UEP6_DMA; __IO uint32_t UEP7_DMA; __IO uint8_t UEP0_TX_LEN; uint8_t RESERVED2; __IO uint8_t UEP0_TX_CTRL; __IO uint8_t UEP0_RX_CTRL; __IO uint8_t UEP1_TX_LEN; uint8_t RESERVED3; __IO uint8_t UEP1_TX_CTRL; __IO uint8_t UEP1_RX_CTRL; __IO uint8_t UEP2_TX_LEN; uint8_t RESERVED4; __IO uint8_t UEP2_TX_CTRL; __IO uint8_t UEP2_RX_CTRL; __IO uint16_t UEP3_TX_LEN; __IO uint8_t UEP3_TX_CTRL; __IO uint8_t UEP3_RX_CTRL; __IO uint8_t UEP4_TX_LEN; uint8_t RESERVED5; __IO uint8_t UEP4_TX_CTRL; __IO uint8_t UEP4_RX_CTRL; __IO uint8_t UEP5_TX_LEN; uint8_t RESERVED6; __IO uint8_t UEP5_TX_CTRL; __IO uint8_t UEP5_RX_CTRL; __IO uint8_t UEP6_TX_LEN; uint8_t RESERVED7; __IO uint8_t UEP6_TX_CTRL; __IO uint8_t UEP6_RX_CTRL; __IO uint8_t UEP7_TX_LEN; uint8_t RESERVED8; __IO uint8_t UEP7_TX_CTRL; __IO uint8_t UEP7_RX_CTRL; uint32_t RESERVED9; __IO uint32_t OTG_CR; __IO uint32_t OTG_SR; } USBFSD_TypeDef; /* USBFS Host Registers */ typedef struct __attribute__((packed)) { __IO uint8_t BASE_CTRL; __IO uint8_t HOST_CTRL; __IO uint8_t INT_EN; __IO uint8_t DEV_ADDR; uint8_t RESERVED0; __IO uint8_t MIS_ST; __IO uint8_t INT_FG; __IO uint8_t INT_ST; __IO uint16_t RX_LEN; uint16_t RESERVED1; uint8_t RESERVED2; __IO uint8_t HOST_EP_MOD; uint16_t RESERVED3; uint32_t RESERVED4; uint32_t RESERVED5; __IO uint32_t HOST_RX_DMA; __IO uint32_t HOST_TX_DMA; uint32_t RESERVED6; uint32_t RESERVED7; uint32_t RESERVED8; uint32_t RESERVED9; uint32_t RESERVED10; uint16_t RESERVED11; __IO uint16_t HOST_SETUP; __IO uint8_t HOST_EP_PID; uint8_t RESERVED12; uint8_t RESERVED13; __IO uint8_t HOST_RX_CTRL; __IO uint16_t HOST_TX_LEN; __IO uint8_t HOST_TX_CTRL; uint8_t RESERVED14; uint32_t RESERVED15; uint32_t RESERVED16; uint32_t RESERVED17; uint32_t RESERVED18; uint32_t RESERVED19; __IO uint32_t OTG_CR; __IO uint32_t OTG_SR; } USBFSH_TypeDef; /* Ethernet MAC Registers */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; __IO uint32_t MACPMTCSR; uint32_t RESERVED1[2]; __IO uint32_t MACSR; __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; uint32_t RESERVED2[8]; __IO uint32_t MACPHYCR; uint32_t RESERVED3[5]; __IO uint32_t MACCFG0; uint32_t RESERVED4[25]; __IO uint32_t MMCCR; __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; uint32_t RESERVED5[14]; __IO uint32_t MMCTGFSCCR; __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED6[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED7[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; __IO uint32_t MMCRAFCR; uint32_t RESERVED8[9]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED9[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; uint32_t RESERVED10[567]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; uint32_t RESERVED11[9]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; /* SDMMC Registers */ typedef struct { __IO uint32_t ARGUMENT; __IO uint16_t CMD_SET; uint16_t RESERVED0; __IO uint32_t RESPONSE0; __IO uint32_t RESPONSE1; __IO uint32_t RESPONSE2; union { __IO uint32_t RESPONSE3; __IO uint32_t WRITE_CONT; }; __IO uint16_t CONTROL; uint16_t RESERVED1; __IO uint8_t TIMEOUT; uint8_t RESERVED3[3]; __IO uint32_t STATUS; __IO uint16_t INT_FG; uint16_t RESERVED4; __IO uint16_t INT_EN; uint16_t RESERVED5; __IO uint32_t DMA_BEG1; __IO uint32_t BLOCK_CFG; __IO uint32_t TRAN_MODE; __IO uint16_t CLK_DIV; uint16_t RESERVED6; __IO uint32_t DMA_BEG2; __IO uint32_t TUNE_DATO; __IO uint32_t TUNE_DATI; __IO uint32_t TUNE_CLK_CMD; } SDMMC_TypeDef; /* SAI Registers */ typedef struct { __IO uint32_t CFGR1; __IO uint32_t CFGR2; __IO uint32_t FRCR; __IO uint32_t SLOTR; __IO uint32_t INTENR; __IO uint32_t SR; uint32_t RESERVED0; __IO uint32_t DATAR; } SAI_Block_TypeDef; /* QSPI Registers */ typedef struct { __IO uint32_t CR; __IO uint32_t DCR; __IO uint32_t SR; __IO uint32_t FCR; __IO uint32_t DLR; __IO uint32_t CCR; __IO uint32_t AR; __IO uint32_t ABR; __IO uint32_t DR; __IO uint32_t PSMKR; __IO uint32_t PSMAR; __IO uint32_t PIR; __IO uint32_t LPTR; } QSPI_TypeDef; /* SWPMI Registers */ typedef struct { __IO uint32_t CR; __IO uint32_t BRR; uint32_t RESERVED0; __IO uint32_t ISR; __IO uint32_t ICR; __IO uint32_t IER; __IO uint32_t RFL; __IO uint32_t TDR; __IO uint32_t RDR; __IO uint32_t OR; } SWPMI_TypeDef; /* ECDC Registers */ typedef struct { __IO uint32_t CTRL; __IO uint32_t INT_FG; __IO uint32_t KEY_255T224; __IO uint32_t KEY_223T192; __IO uint32_t KEY_191T160; __IO uint32_t KEY_159T128; __IO uint32_t KEY_127T96; __IO uint32_t KEY_95T64; __IO uint32_t KEY_63T32; __IO uint32_t KEY_31T0; __IO uint32_t IV_127T96; __IO uint32_t IV_95T64; __IO uint32_t IV_63T32; __IO uint32_t IV_31T0; uint32_t RESERVED3[2]; __IO uint32_t SGSD_127T96; __IO uint32_t SGSD_95T64; __IO uint32_t SGSD_63T32; __IO uint32_t SGSD_31T0; __IO uint32_t SGRT_127T96; __IO uint32_t SGRT_95T64; __IO uint32_t SGRT_63T32; __IO uint32_t SGRT_31T0; __IO uint32_t SRC_ADDR; __IO uint32_t DST_ADDR; __IO uint32_t SRAM_LEN; } ECDC_TypeDef; /* DFSDM filter Registers */ typedef struct { __IO uint32_t CR1; uint32_t RESERVED0; __IO uint32_t CR2; uint32_t RESERVED1; __IO uint32_t ISR; uint32_t RESERVED2; __IO uint32_t ICR; uint32_t RESERVED3; __IO uint32_t JCHGR; uint32_t RESERVED4; __IO uint32_t FCR3; uint32_t RESERVED5; __IO uint32_t JDATAR; uint32_t RESERVED6; __IO uint32_t RDATAR; uint32_t RESERVED7; __IO uint32_t AWHTR; uint32_t RESERVED8; __IO uint32_t AWLTR; uint32_t RESERVED9; __IO uint32_t AWSR; uint32_t RESERVED10; __IO uint32_t AWCFR; uint32_t RESERVED11; __IO uint32_t EXMAX; uint32_t RESERVED12; __IO uint32_t EXMIN; uint32_t RESERVED13; __IO uint32_t NVTIMR; uint32_t RESERVED14; } DFSDM_FLT_TypeDef; /* DFSDM channel Registers */ typedef struct { __IO uint32_t CFGR1; uint32_t RESERVED0; __IO uint32_t CFGR2; uint32_t RESERVED1; __IO uint32_t AWSCDR; uint32_t RESERVED2; __IO uint32_t WDATR; uint32_t RESERVED3; union{ __IO uint32_t DATINR; struct{ __IO int16_t DATINR0; __IO int16_t DATINR1; }; }; } DFSDM_Channel_TypeDef; /* LTDC Registers */ typedef struct { __IO uint32_t SSCR; __IO uint32_t BPCR; __IO uint32_t AWCR; __IO uint32_t TWCR; __IO uint32_t GCR; __IO uint32_t SRCR; __IO uint32_t BCCR; __IO uint32_t IER; __IO uint32_t ISR; __IO uint32_t ICR; __IO uint32_t LIPCR; __IO uint32_t CPSR; __IO uint32_t CDSR; } LTDC_TypeDef; /* LTDC Layer Registers */ typedef struct { __IO uint32_t CR; __IO uint32_t WHPCR; __IO uint32_t WVPCR; __IO uint32_t CKCR; __IO uint32_t PFCR; __IO uint32_t CACR; __IO uint32_t DCCR; __IO uint32_t BFCR; __IO uint32_t CFBAR; __IO uint32_t CFBLR; __IO uint32_t CFBLNR; __IO uint32_t CLUTWR; } LTDC_Layer_TypeDef; /* GPHA Registers */ typedef struct { __IO uint32_t CTLR; __IO uint32_t ISR; __IO uint32_t IFCR; __IO uint32_t FGMAR; __IO uint32_t FGOR; __IO uint32_t BGMAR; __IO uint32_t BGOR; __IO uint32_t FGPFCCR; __IO uint32_t FGCOLR; __IO uint32_t BGPFCCR; __IO uint32_t BGCOLR; __IO uint32_t FGCMAR; __IO uint32_t BGCMAR; __IO uint32_t OPFCCR; __IO uint32_t OCOLR; __IO uint32_t OMAR; __IO uint32_t OOR; __IO uint32_t NLR; __IO uint32_t LWR; __IO uint32_t AMTCR; __IO uint32_t FGCWRS; __IO uint32_t FGCDAT; __IO uint32_t BGCWRS; __IO uint32_t BGCDAT; } GPHA_TypeDef; /* HSADC Registers */ typedef struct { __IO uint32_t CFGR; __IO uint32_t CTLR1; __IO uint32_t CTLR2; __IO uint32_t STATR; __IO uint32_t DATAR; __IO uint32_t ADDR0; __IO uint32_t ADDR1; } HSADC_TypeDef; /* SerDes Registers */ typedef struct { __IO uint32_t CTRL; __IO uint32_t INT_EN; __IO uint32_t STATUS; __IO uint32_t RTX_CTRL; __IO uint32_t RX_LEN0; __IO uint32_t DATA0; __IO uint32_t DMA_0; __IO uint32_t RX_LEN1; __IO uint32_t DATA1; __IO uint32_t DMA_1; } SDS_TypeDef; /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ typedef struct{ __I uint32_t ISR[8]; __I uint32_t IPR[8]; __IO uint32_t ITHRESDR; uint32_t RESERVED; __IO uint32_t CFGR; __I uint32_t GISR; __IO uint8_t VTFIDR[4]; uint8_t RESERVED0[12]; __IO uint32_t VTFADDR[4]; uint8_t RESERVED1[0x90]; __O uint32_t IENR[8]; uint8_t RESERVED2[0x60]; __O uint32_t IRER[8]; uint8_t RESERVED3[0x60]; __O uint32_t IPSR[8]; uint8_t RESERVED4[0x60]; __O uint32_t IPRR[8]; uint8_t RESERVED5[0x60]; __IO uint32_t IACTR[8]; uint8_t RESERVED6[0xE0]; __IO uint8_t IPRIOR[256]; uint8_t RESERVED7[0x100]; __IO uint8_t IALLOCR[256]; __I uint32_t IAUTR[8]; __IO uint32_t WAKEIP[2]; uint8_t RESERVED8[0x58]; __I uint32_t CSTAR[2]; uint8_t RESERVED9[0x4F8]; __IO uint32_t EENR; __IO uint32_t EPR; __IO uint32_t EWUPR; uint8_t RESERVED10[0x84]; __IO uint32_t SCTLR; }PFIC_Type; #endif // !__ASSEMBLER__ /* Peripheral memory map */ #ifdef __ASSEMBLER__ #define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */ #define ITCM_BASE (0x200A0000) /* ITCM base address in the alias region */ #define DTCM_BASE (0x200C0000) /* DTCM base address in the alias region */ #define SRAM_BASE (0x20100000) /* SRAM base address in the alias region */ #define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */ #define CORE_PERIPH_BASE (0xE0000000) /* System peripherals base address in the alias region */ #else #define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ #define ITCM_BASE ((uint32_t)0x200A0000) /* ITCM base address in the alias region */ #define DTCM_BASE ((uint32_t)0x200C0000) /* DTCM base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20100000) /* SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ #define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ #endif #define HBPERIPH_BASE (PERIPH_BASE) #define TIM2_BASE (HBPERIPH_BASE + 0x00000) #define TIM3_BASE (HBPERIPH_BASE + 0x00400) #define TIM4_BASE (HBPERIPH_BASE + 0x00800) #define TIM5_BASE (HBPERIPH_BASE + 0x00C00) #define TIM6_BASE (HBPERIPH_BASE + 0x01000) #define TIM7_BASE (HBPERIPH_BASE + 0x01400) #define USART6_BASE (HBPERIPH_BASE + 0x01800) #define USART7_BASE (HBPERIPH_BASE + 0x01C00) #define USART8_BASE (HBPERIPH_BASE + 0x02000) #define LPTIM1_BASE (HBPERIPH_BASE + 0x02400) #define RTC_BASE (HBPERIPH_BASE + 0x02800) #define WWDG_BASE (HBPERIPH_BASE + 0x02C00) #define IWDG_BASE (HBPERIPH_BASE + 0x03000) #define LPTIM2_BASE (HBPERIPH_BASE + 0x03400) #define SPI2_BASE (HBPERIPH_BASE + 0x03800) #define SPI3_BASE (HBPERIPH_BASE + 0x03C00) #define SPI4_BASE (HBPERIPH_BASE + 0x04000) #define USART2_BASE (HBPERIPH_BASE + 0x04400) #define USART3_BASE (HBPERIPH_BASE + 0x04800) #define USART4_BASE (HBPERIPH_BASE + 0x04C00) #define USART5_BASE (HBPERIPH_BASE + 0x05000) #define I2C1_BASE (HBPERIPH_BASE + 0x05400) #define I2C2_BASE (HBPERIPH_BASE + 0x05800) #define I2C3_BASE (HBPERIPH_BASE + 0x05C00) #define CAN1_BASE (HBPERIPH_BASE + 0x06400) #define CAN2_BASE (HBPERIPH_BASE + 0x06800) #define PWR_BASE (HBPERIPH_BASE + 0x07000) #define DAC_BASE (HBPERIPH_BASE + 0x07400) #define CAN3_BASE (HBPERIPH_BASE + 0x07800) #define SWPMI_BASE (HBPERIPH_BASE + 0x08400) #define AFIO_BASE (HBPERIPH_BASE + 0x10000) #define EXTI_BASE (HBPERIPH_BASE + 0x10400) #define GPIOA_BASE (HBPERIPH_BASE + 0x10800) #define GPIOB_BASE (HBPERIPH_BASE + 0x10C00) #define GPIOC_BASE (HBPERIPH_BASE + 0x11000) #define GPIOD_BASE (HBPERIPH_BASE + 0x11400) #define GPIOE_BASE (HBPERIPH_BASE + 0x11800) #define GPIOF_BASE (HBPERIPH_BASE + 0x11C00) #define ADC1_BASE (HBPERIPH_BASE + 0x12400) #define ADC2_BASE (HBPERIPH_BASE + 0x12800) #define TIM1_BASE (HBPERIPH_BASE + 0x12C00) #define SPI1_BASE (HBPERIPH_BASE + 0x13000) #define TIM8_BASE (HBPERIPH_BASE + 0x13400) #define USART1_BASE (HBPERIPH_BASE + 0x13800) #define TIM12_BASE (HBPERIPH_BASE + 0x13C00) #define I2C4_BASE (HBPERIPH_BASE + 0x14000) #define I3C_BASE (HBPERIPH_BASE + 0x14400) #define LTDC_BASE (HBPERIPH_BASE + 0x14800) #define LTDC_L1_BASE (HBPERIPH_BASE + 0x14834) #define LTDC_L2_BASE (HBPERIPH_BASE + 0x14864) #define TIM9_BASE (HBPERIPH_BASE + 0x14C00) #define TIM10_BASE (HBPERIPH_BASE + 0x15000) #define TIM11_BASE (HBPERIPH_BASE + 0x15400) #define SAI_BASE (HBPERIPH_BASE + 0x15800) #define SAI_Block_A_BASE (SAI_BASE + 0x04) #define SAI_Block_B_BASE (SAI_BASE + 0x24) #define GPHA_BASE (HBPERIPH_BASE + 0x16800) #define ECDC_BASE (HBPERIPH_BASE + 0x16C00) #define DFSDM_BASE (HBPERIPH_BASE + 0x17000) #define DFSDM_Channel0_BASE (HBPERIPH_BASE + 0x17000) #define DFSDM_Channel1_BASE (HBPERIPH_BASE + 0x17004) #define DFSDM_FLT0_BASE (HBPERIPH_BASE + 0x17028) #define DFSDM_FLT1_BASE (HBPERIPH_BASE + 0x1702C) #define HSADC_BASE (HBPERIPH_BASE + 0x17400) #define OPA_BASE (HBPERIPH_BASE + 0x17800) #define SDIO_BASE (HBPERIPH_BASE + 0x18000) #define DMA1_BASE (HBPERIPH_BASE + 0x20000) #define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x20008) #define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x2001C) #define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x20030) #define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x20044) #define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x20058) #define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x2006C) #define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x20080) #define DMA1_Channel8_BASE (HBPERIPH_BASE + 0x20094) #define DMA2_BASE (HBPERIPH_BASE + 0x20400) #define DMA2_Channel1_BASE (HBPERIPH_BASE + 0x20408) #define DMA2_Channel2_BASE (HBPERIPH_BASE + 0x2041C) #define DMA2_Channel3_BASE (HBPERIPH_BASE + 0x20430) #define DMA2_Channel4_BASE (HBPERIPH_BASE + 0x20444) #define DMA2_Channel5_BASE (HBPERIPH_BASE + 0x20458) #define DMA2_Channel6_BASE (HBPERIPH_BASE + 0x2046C) #define DMA2_Channel7_BASE (HBPERIPH_BASE + 0x20480) #define DMA2_Channel8_BASE (HBPERIPH_BASE + 0x20494) #define DMAMUX_BASE (HBPERIPH_BASE + 0x20800) #define RCC_BASE (HBPERIPH_BASE + 0x21000) #define FLASH_R_BASE (HBPERIPH_BASE + 0x22000) #define CRC_BASE (HBPERIPH_BASE + 0x23000) #define USBFS_BASE (HBPERIPH_BASE + 0x23400) #define RNG_BASE (HBPERIPH_BASE + 0x23C00) #define SDMMC_BASE (HBPERIPH_BASE + 0x24000) #define USBPD_BASE (HBPERIPH_BASE + 0x24400) #define QSPI1_BASE (HBPERIPH_BASE + 0x24C00) #define QSPI2_BASE (HBPERIPH_BASE + 0x25000) #define FMC_R_BASE (HBPERIPH_BASE + 0x25400) #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) #define DVP_BASE (HBPERIPH_BASE + 0x25800) #define PIOC_BASE (HBPERIPH_BASE + 0x25C00) #define SERDES_BASE (HBPERIPH_BASE + 0x27C00) #define SERDES1_BASE (SERDES_BASE) #define SERDES2_BASE (SERDES_BASE+0x0040) #define ETH_BASE (HBPERIPH_BASE + 0x28000) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) #define USBHS_BASE (HBPERIPH_BASE + 0x30000) #define USBHSD_BASE (USBHS_BASE) #define USBHSH_BASE (USBHS_BASE + 0x100) #define USBSS_BASE (HBPERIPH_BASE + 0x34000) #define UHSIF_BASE (HBPERIPH_BASE + 0x38000) #define OB_BASE ((uint32_t)0x1FFFF800) #define FLASH_CFGR0_BASE ((uint32_t)0x4002202C) #define SYS_CFGR0_BASE ((uint32_t)0x5003C000) #define SYS_CFGR4_BASE ((uint32_t)0x5003C010) #define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) #define SysTick0_BASE (CORE_PERIPH_BASE + 0xF000) #define SysTick1_BASE (CORE_PERIPH_BASE + 0xF080) #define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) /* Peripheral declaration */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define USART7 ((USART_TypeDef *) USART7_BASE) #define USART8 ((USART_TypeDef *) USART8_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define USART4 ((USART_TypeDef *) USART4_BASE) #define USART5 ((USART_TypeDef *) USART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define CAN3 ((CAN_TypeDef *) CAN3_BASE) #define SWPMI ((SWPMI_TypeDef *) SWPMI_BASE) #define AFIO ((AFIO_TypeDef *) AFIO_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define TKey1 ((ADC_TypeDef *) ADC1_BASE) #define TKey2 ((ADC_TypeDef *) ADC2_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define I2C4 ((I2C_TypeDef *) I2C4_BASE) #define I3C ((I3C_TypeDef *) I3C_BASE) #define LTDC ((LTDC_TypeDef *) LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *) LTDC_L1_BASE) #define LTDC_Layer2 ((LTDC_Layer_TypeDef *) LTDC_L2_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define SAI_Block_A ((SAI_Block_TypeDef *) SAI_Block_A_BASE) #define SAI_Block_B ((SAI_Block_TypeDef *) SAI_Block_B_BASE) #define GPHA ((GPHA_TypeDef *) GPHA_BASE) #define ECDC ((ECDC_TypeDef *) ECDC_BASE) #define DFSDM_FLT0 ((DFSDM_FLT_TypeDef *) DFSDM_FLT0_BASE) #define DFSDM_FLT1 ((DFSDM_FLT_TypeDef *) DFSDM_FLT1_BASE) #define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE) #define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE) #define HSADC ((HSADC_TypeDef *) HSADC_BASE) #define OPA ((OPA_TypeDef *) OPA_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) #define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) #define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) #define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) #define USBPD ((USBPD_TypeDef *) USBPD_BASE) #define QSPI1 ((QSPI_TypeDef *) QSPI1_BASE) #define QSPI2 ((QSPI_TypeDef *) QSPI2_BASE) #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) #define DVP ((DVP_TypeDef *) DVP_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define USBHSD ((USBHSD_TypeDef *) USBHSD_BASE) #define USBHSH ((USBHSH_TypeDef *) USBHSH_BASE) #define USBSSD ((USBSSD_TypeDef *) USBSS_BASE) #define USBSSH ((USBSSH_TypeDef *) USBSS_BASE) #define SDS1 ((SDS_TypeDef *) SERDES1_BASE) #define SDS2 ((SDS_TypeDef *) SERDES2_BASE) #define UHSIF ((UHSIF_TypeDef *) UHSIF_BASE) #define OB ((OB_TypeDef *) OB_BASE) /******************************************************************************/ /* Peripheral Registers Bits Definition */ /******************************************************************************/ /******************************************************************************/ /* Analog to Digital Converter */ /******************************************************************************/ /******************** Bit definition for ADC_STATR register ********************/ #define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ #define ADC_EOC ((uint8_t)0x02) /* End of conversion */ #define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ #define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ #define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ #define ADC_RSTF ((uint16_t)0x8000) /* Reset flag */ /******************* Bit definition for ADC_CTLR1 register ********************/ #define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ #define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ #define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ #define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ #define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ #define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ #define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ #define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ #define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ #define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ #define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ #define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ #define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ #define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ #define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ #define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ #define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ #define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ #define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ #define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ #define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ #define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ #define ADC_TKENABLE ((uint32_t)0x01000000) /*TKEY enable*/ #define ADC_TKITUNE ((uint32_t)0x02000000) #define ADC_BUFEN ((uint32_t)0x04000000) #define ADC_PGA ((uint32_t)0x18000000) #define ADC_PGA_0 ((uint32_t)0x08000000) #define ADC_PGA_1 ((uint32_t)0x10000000) #define ADC_ANA_RST ((uint32_t)0x40000000) #define ADC_SW_PRE ((uint32_t)0x80000000) /******************* Bit definition for ADC_CTLR2 register ********************/ #define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ #define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ #define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ #define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ #define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ #define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ #define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ #define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ #define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ #define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ #define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ #define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ #define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ #define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ #define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ #define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ #define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ #define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ #define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ /****************** Bit definition for ADC_SAMPTR1 register *******************/ #define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ #define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ #define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ #define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ #define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ #define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ #define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ #define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ #define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ #define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ #define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ #define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ #define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ #define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ #define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ #define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ #define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ #define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ #define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ #define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ #define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ #define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ #define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ #define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ #define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ #define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ #define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ #define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ #define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ /****************** Bit definition for ADC_SAMPTR2 register *******************/ #define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ #define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ #define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ #define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ #define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ #define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ #define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ #define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ #define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ #define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ #define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ #define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ #define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ #define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ #define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ #define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ #define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ #define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ #define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ #define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ #define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ #define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ #define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ #define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ #define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ #define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ #define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ #define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ #define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ #define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ #define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ #define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ #define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ #define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ #define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ #define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ #define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ /****************** Bit definition for ADC_IOFR1 register *******************/ #define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ /****************** Bit definition for ADC_IOFR2 register *******************/ #define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ /****************** Bit definition for ADC_IOFR3 register *******************/ #define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ /****************** Bit definition for ADC_IOFR4 register *******************/ #define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ /******************* Bit definition for ADC_WDHTR register ********************/ #define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ /******************* Bit definition for ADC_WDLTR register ********************/ #define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ /******************* Bit definition for ADC_RSQR1 register *******************/ #define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ #define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ #define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ #define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ #define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ #define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ #define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ #define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ #define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ #define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ #define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ #define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ #define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ #define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ #define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ #define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ #define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ #define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ #define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ #define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ #define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ #define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ #define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ #define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ #define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ #define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ /******************* Bit definition for ADC_RSQR2 register *******************/ #define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ #define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ #define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ #define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ #define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ #define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ #define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ #define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ #define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ #define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ #define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ #define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ #define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ #define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ #define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ #define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ #define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ #define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ #define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ #define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ #define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ #define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ #define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ #define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ #define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ #define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ #define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ #define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ #define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ #define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ #define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ #define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ #define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ /******************* Bit definition for ADC_RSQR3 register *******************/ #define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ #define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ #define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ #define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ #define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ #define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ #define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ #define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ #define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ #define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ #define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ #define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ #define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ #define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ #define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ #define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ #define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ #define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ #define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ #define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ #define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ #define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ #define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ #define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ #define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ #define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ #define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ #define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ #define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ #define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ #define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ #define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ #define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ /******************* Bit definition for ADC_ISQR register *******************/ #define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ #define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ #define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ #define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ #define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ #define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ #define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ #define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ #define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ #define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ #define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ #define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ #define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ #define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ #define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ #define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ #define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ #define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ #define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ #define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ #define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ #define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ #define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ #define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ /******************* Bit definition for ADC_IDATAR1 register *******************/ #define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ /******************* Bit definition for ADC_IDATAR2 register *******************/ #define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ /******************* Bit definition for ADC_IDATAR3 register *******************/ #define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ /******************* Bit definition for ADC_IDATAR4 register *******************/ #define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ /******************** Bit definition for ADC_RDATAR register ********************/ #define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ #define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ /******************** Bit definition for ADC_AUX register ********************/ #define ADC_SMP_SEL_0 ((uint32_t)0x00000001) /* channel_0 */ #define ADC_SMP_SEL_1 ((uint32_t)0x00000002) /* channel_1 */ #define ADC_SMP_SEL_2 ((uint32_t)0x00000004) /* channel_2 */ #define ADC_SMP_SEL_3 ((uint32_t)0x00000008) /* channel_3 */ #define ADC_SMP_SEL_4 ((uint32_t)0x00000010) /* channel_4 */ #define ADC_SMP_SEL_5 ((uint32_t)0x00000020) /* channel_5 */ #define ADC_SMP_SEL_6 ((uint32_t)0x00000040) /* channel_6 */ #define ADC_SMP_SEL_7 ((uint32_t)0x00000080) /* channel_7 */ #define ADC_SMP_SEL_8 ((uint32_t)0x00000100) /* channel_8 */ #define ADC_SMP_SEL_9 ((uint32_t)0x00000200) /* channel_9 */ #define ADC_SMP_SEL_10 ((uint32_t)0x00000400) /* channel_10 */ #define ADC_SMP_SEL_11 ((uint32_t)0x00000800) /* channel_11 */ #define ADC_SMP_SEL_12 ((uint32_t)0x00001000) /* channel_12 */ #define ADC_SMP_SEL_13 ((uint32_t)0x00002000) /* channel_13 */ #define ADC_SMP_SEL_14 ((uint32_t)0x00004000) /* channel_14 */ #define ADC_SMP_SEL_15 ((uint32_t)0x00008000) /* channel_15 */ #define ADC_SMP_SEL_16 ((uint32_t)0x00010000) /* channel_16 */ #define ADC_SMP_SEL_17 ((uint32_t)0x00020000) /* channel_17 */ #define ADC_TO_DFSDM ((uint32_t)0x80000000) /******************** Bit definition for ADC_DRV register ********************/ #define ADC_DRV_TKEY_OUTEN ((uint32_t)0x0000FFFF) /* Touchkey enables multi-channel shielding of each channel */ #define ADC_DRV_TKEY_EN ((uint32_t)0x00010000) /* Touchkey Multi Channel Shielding Enable */ /******************************************************************************/ /* High Speed Analog to Digital Converter */ /******************************************************************************/ /******************** Bit definition for HSADC_CFGR register ********************/ #define HSADC_EN ((uint32_t)0x00000001) #define HSADC_DMAEN ((uint32_t)0x00000002) #define HSADC_CHSEL ((uint32_t)0x0000001C) #define HSADC_CHSEL_0 ((uint32_t)0x00000004) #define HSADC_CHSEL_1 ((uint32_t)0x00000008) #define HSADC_CHSEL_2 ((uint32_t)0x00000010) #define HSADC_SETUP ((uint32_t)0x00000060) #define HSADC_SETUP_0 ((uint32_t)0x00000020) #define HSADC_SETUP_1 ((uint32_t)0x00000040) #define HSADC_WIDTH ((uint32_t)0x00000080) #define HSADC_CLKDIV ((uint32_t)0x00003F00) #define HSADC_CLKDIV_0 ((uint32_t)0x00000100) #define HSADC_CLKDIV_1 ((uint32_t)0x00000200) #define HSADC_CLKDIV_2 ((uint32_t)0x00000400) #define HSADC_CLKDIV_3 ((uint32_t)0x00000800) #define HSADC_CLKDIV_4 ((uint32_t)0x00001000) #define HSADC_CLKDIV_5 ((uint32_t)0x00002000) #define HSADC_PPMODE ((uint32_t)0x00004000) #define HSADC_BURST_EN ((uint32_t)0x00008000) #define HSADC_DMA_LEN ((uint32_t)0xFFFF0000) /******************** Bit definition for HSADC_CTLR1 register ********************/ #define HSADC_START ((uint32_t)0x00000001) #define HSADC_BURSTEND ((uint32_t)0x00000002) #define HSADC_EOCIE ((uint32_t)0x00000100) #define HSADC_DMAIE ((uint32_t)0x00000200) #define HSADC_BURSTIE ((uint32_t)0x00000400) /******************** Bit definition for HSADC_CTLR2 register ********************/ #define HSADC_BURST_LEN ((uint32_t)0x0000FFFF) #define HSADC_BURST_DMA_LEN ((uint32_t)0xFFFF0000) /******************** Bit definition for HSADC_STATR register ********************/ #define HSADC_EOCIF ((uint32_t)0x00000001) #define HSADC_DMAIF ((uint32_t)0x00000002) #define HSADC_BURSTIF ((uint32_t)0x00000004) #define HSADC_RXNE ((uint32_t)0x00000008) #define HSADC_PP_ADDR ((uint32_t)0x00000010) #define HSADC_FIFO_RDY ((uint32_t)0x00000100) #define HSADC_FIFO_FULL ((uint32_t)0x00000200) #define HSADC_FIFO_OV ((uint32_t)0x00000400) #define HSADC_FIFO_CNT ((uint32_t)0x00003800) /******************** Bit definition for HSADC_DATAR register ********************/ #define HSADC_DR ((uint32_t)0x000003FF) /******************** Bit definition for HSADC_ADDR0 register ********************/ #define HSADC_DMA_ADDR0 ((uint32_t)0xFFFFFFFF) /******************** Bit definition for HSADC_ADDR1 register ********************/ #define HSADC_DMA_ADDR1 ((uint32_t)0xFFFFFFFF) /******************************************************************************/ /* Controller Area Network */ /******************************************************************************/ /******************* Bit definition for CAN_CTLR register ********************/ #define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ #define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ #define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ #define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ #define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ #define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ #define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ #define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ #define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ #define CAN_CTLR_DBF ((uint32_t)0x10000) #define CAN_CTLR_CFGCANM ((uint32_t)0x20000) /******************* Bit definition for CAN_STATR register ********************/ #define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ #define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ #define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ #define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ #define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ #define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ #define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ #define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ #define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ /******************* Bit definition for CAN_TSTATR register ********************/ #define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ #define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ #define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ #define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ #define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ #define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ #define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ #define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ #define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ #define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ #define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ #define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ #define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ #define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ #define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ #define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ #define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ #define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ #define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ #define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ #define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ #define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ #define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ #define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ /******************* Bit definition for CAN_RFIFO0 register *******************/ #define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ #define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ #define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ #define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ /******************* Bit definition for CAN_RFIFO1 register *******************/ #define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ #define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ #define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ #define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ /******************** Bit definition for CAN_INTENR register *******************/ #define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ #define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ #define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ #define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ #define CAN_INTENR_EMPIE1 ((uint32_t)0x00000010) /* FIF1 Message Pending Interrupt Enable */ #define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIF1 Full Interrupt Enable */ #define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIF1 Overrun Interrupt Enable */ #define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ #define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ #define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ #define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ #define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ #define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ #define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ /******************** Bit definition for CAN_ERRSR register *******************/ #define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ #define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ #define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ #define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ #define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ #define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ #define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ #define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ #define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ /******************** Bit definition for CAN_BTIMR register *******************/ #define CAN_BTIMR_BRP ((uint32_t)0x000003FF) #define CAN_BTIMR_BTR_TS1_T ((uint32_t)0x0000F000) #define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) #define CAN_BTIMR_TS2 ((uint32_t)0x00F00000) #define CAN_BTIMR_SJW ((uint32_t)0x0F000000) #define CAN_BTIMR_LBKM ((uint32_t)0x40000000) #define CAN_BTIMR_SILM ((uint32_t)0x80000000) /******************* Bit definition for CAN_TTCTLR register ********************/ #define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) #define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) #define CAN_TTCTLR_MODE ((uint32_t)0x00020000) /******************* Bit definition for CAN_TTCNT register ********************/ #define CAN_TIMCNT ((uint32_t)0x0000FFFF) /******************* Bit definition for CAN_TERR_CNT register ********************/ #define CAN_TERR_CNT ((uint32_t)0x000001FF) /****************** Bit definition for CAN_TXMI0R register ********************/ #define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ #define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ #define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ #define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ #define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ /****************** Bit definition for CAN_TXMDT0R register *******************/ #define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ #define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ #define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ /****************** Bit definition for CAN_TXMDL0R register *******************/ #define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ #define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ #define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ #define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ /****************** Bit definition for CAN_TXMDH0R register *******************/ #define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ #define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ #define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ #define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ /******************* Bit definition for CAN_TXMI1R register *******************/ #define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ #define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ #define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ #define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ #define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_TXMDT1R register ******************/ #define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ #define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ #define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ /******************* Bit definition for CAN_TXMDL1R register ******************/ #define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ #define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ #define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ #define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ /******************* Bit definition for CAN_TXMDH1R register ******************/ #define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ #define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ #define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ #define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ /******************* Bit definition for CAN_TXMI2R register *******************/ #define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ #define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ #define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ #define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ #define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_TXMDT2R register ******************/ #define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ #define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ #define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ /******************* Bit definition for CAN_TXMDL2R register ******************/ #define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ #define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ #define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ #define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ /******************* Bit definition for CAN_TXMDH2R register ******************/ #define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ #define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ #define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ #define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ /******************* Bit definition for CAN_RXMI0R register *******************/ #define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ #define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ #define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ #define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_RXMDT0R register ******************/ #define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ #define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) #define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) #define CAN_RXMDH0R_RES ((uint32_t)0x00000100) #define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ /******************* Bit definition for CAN_RXMDL0R register ******************/ #define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ #define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ #define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ #define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ /******************* Bit definition for CAN_RXMDH0R register ******************/ #define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ #define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ #define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ #define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ /******************* Bit definition for CAN_RXMI1R register *******************/ #define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ #define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ #define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ #define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_RXMDT1R register ******************/ #define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ #define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) #define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) #define CAN_RXMDH1R_RES ((uint32_t)0x00000100) #define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ /******************* Bit definition for CAN_RXMDL1R register ******************/ #define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ #define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ #define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ #define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ /******************* Bit definition for CAN_RXMDH1R register ******************/ #define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ #define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ #define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ #define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ /******************* Bit definition for CAN_FCTLR register *******************/ #define CAN_FCTLR_TINIT ((uint32_t)0x00000001) #define CAN_FCTLR_CAN2SB ((uint32_t)0x00001F00) #define CAN_FCTLR_CAN3SB ((uint32_t)0x003F0000) /****************** Bit definition for CAN_FMCFGR register ******************/ #define CAN_FMCFGR_FBM0 ((uint32_t)0x00000001) #define CAN_FMCFGR_FBM1 ((uint32_t)0x00000002) #define CAN_FMCFGR_FBM2 ((uint32_t)0x00000004) #define CAN_FMCFGR_FBM3 ((uint32_t)0x00000008) #define CAN_FMCFGR_FBM4 ((uint32_t)0x00000010) #define CAN_FMCFGR_FBM5 ((uint32_t)0x00000020) #define CAN_FMCFGR_FBM6 ((uint32_t)0x00000040) #define CAN_FMCFGR_FBM7 ((uint32_t)0x00000080) #define CAN_FMCFGR_FBM8 ((uint32_t)0x00000100) #define CAN_FMCFGR_FBM9 ((uint32_t)0x00000200) #define CAN_FMCFGR_FBM10 ((uint32_t)0x00000400) #define CAN_FMCFGR_FBM11 ((uint32_t)0x00000800) #define CAN_FMCFGR_FBM12 ((uint32_t)0x00001000) #define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) #define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) #define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) #define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) #define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) #define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) #define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) #define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) #define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) #define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) #define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) #define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) #define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) #define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) #define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) /****************** Bit definition for CAN_FMCFGR1 register ******************/ #define CAN_FMCFGR1_FBM28 ((uint32_t)0x00000001) #define CAN_FMCFGR1_FBM29 ((uint32_t)0x00000002) #define CAN_FMCFGR1_FBM30 ((uint32_t)0x00000004) #define CAN_FMCFGR1_FBM31 ((uint32_t)0x00000008) #define CAN_FMCFGR1_FBM32 ((uint32_t)0x00000010) #define CAN_FMCFGR1_FBM33 ((uint32_t)0x00000020) #define CAN_FMCFGR1_FBM34 ((uint32_t)0x00000040) #define CAN_FMCFGR1_FBM35 ((uint32_t)0x00000080) #define CAN_FMCFGR1_FBM36 ((uint32_t)0x00000100) #define CAN_FMCFGR1_FBM37 ((uint32_t)0x00000200) #define CAN_FMCFGR1_FBM38 ((uint32_t)0x00000400) #define CAN_FMCFGR1_FBM39 ((uint32_t)0x00000800) #define CAN_FMCFGR1_FBM40 ((uint32_t)0x00001000) #define CAN_FMCFGR1_FBM41 ((uint32_t)0x00002000) /****************** Bit definition for CAN_FSCFGR register ******************/ #define CAN_FSCFGR_FSC0 ((uint32_t)0x00000001) #define CAN_FSCFGR_FSC1 ((uint32_t)0x00000002) #define CAN_FSCFGR_FSC2 ((uint32_t)0x00000004) #define CAN_FSCFGR_FSC3 ((uint32_t)0x00000008) #define CAN_FSCFGR_FSC4 ((uint32_t)0x00000010) #define CAN_FSCFGR_FSC5 ((uint32_t)0x00000020) #define CAN_FSCFGR_FSC6 ((uint32_t)0x00000040) #define CAN_FSCFGR_FSC7 ((uint32_t)0x00000080) #define CAN_FSCFGR_FSC8 ((uint32_t)0x00000100) #define CAN_FSCFGR_FSC9 ((uint32_t)0x00000200) #define CAN_FSCFGR_FSC10 ((uint32_t)0x00000400) #define CAN_FSCFGR_FSC11 ((uint32_t)0x00000800) #define CAN_FSCFGR_FSC12 ((uint32_t)0x00001000) #define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) #define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) #define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) #define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) #define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) #define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) #define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) #define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) #define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) #define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) #define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) #define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) #define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) #define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) #define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) /****************** Bit definition for CAN_FSCFGR1 register ******************/ #define CAN_FSCFGR1_FSC28 ((uint32_t)0x00000001) #define CAN_FSCFGR1_FSC29 ((uint32_t)0x00000002) #define CAN_FSCFGR1_FSC30 ((uint32_t)0x00000004) #define CAN_FSCFGR1_FSC31 ((uint32_t)0x00000008) #define CAN_FSCFGR1_FSC32 ((uint32_t)0x00000010) #define CAN_FSCFGR1_FSC33 ((uint32_t)0x00000020) #define CAN_FSCFGR1_FSC34 ((uint32_t)0x00000040) #define CAN_FSCFGR1_FSC35 ((uint32_t)0x00000080) #define CAN_FSCFGR1_FSC36 ((uint32_t)0x00000100) #define CAN_FSCFGR1_FSC37 ((uint32_t)0x00000200) #define CAN_FSCFGR1_FSC38 ((uint32_t)0x00000400) #define CAN_FSCFGR1_FSC39 ((uint32_t)0x00000800) #define CAN_FSCFGR1_FSC40 ((uint32_t)0x00001000) #define CAN_FSCFGR1_FSC41 ((uint32_t)0x00002000) /****************** Bit definition for CAN_FAFIFOR register ******************/ #define CAN_FAFIFOR_FFA0 ((uint32_t)0x00000001) #define CAN_FAFIFOR_FFA1 ((uint32_t)0x00000002) #define CAN_FAFIFOR_FFA2 ((uint32_t)0x00000004) #define CAN_FAFIFOR_FFA3 ((uint32_t)0x00000008) #define CAN_FAFIFOR_FFA4 ((uint32_t)0x00000010) #define CAN_FAFIFOR_FFA5 ((uint32_t)0x00000020) #define CAN_FAFIFOR_FFA6 ((uint32_t)0x00000040) #define CAN_FAFIFOR_FFA7 ((uint32_t)0x00000080) #define CAN_FAFIFOR_FFA8 ((uint32_t)0x00000100) #define CAN_FAFIFOR_FFA9 ((uint32_t)0x00000200) #define CAN_FAFIFOR_FFA10 ((uint32_t)0x00000400) #define CAN_FAFIFOR_FFA11 ((uint32_t)0x00000800) #define CAN_FAFIFOR_FFA12 ((uint32_t)0x00001000) #define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) #define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) #define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) #define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) #define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) #define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) #define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) #define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) #define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) #define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) #define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) #define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) #define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) #define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) #define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) /****************** Bit definition for CAN_FAFIFOR1 register ******************/ #define CAN_FAFIFOR1_FFA28 ((uint32_t)0x00000001) #define CAN_FAFIFOR1_FFA29 ((uint32_t)0x00000002) #define CAN_FAFIFOR1_FFA30 ((uint32_t)0x00000004) #define CAN_FAFIFOR1_FFA31 ((uint32_t)0x00000008) #define CAN_FAFIFOR1_FFA32 ((uint32_t)0x00000010) #define CAN_FAFIFOR1_FFA33 ((uint32_t)0x00000020) #define CAN_FAFIFOR1_FFA34 ((uint32_t)0x00000040) #define CAN_FAFIFOR1_FFA35 ((uint32_t)0x00000080) #define CAN_FAFIFOR1_FFA36 ((uint32_t)0x00000100) #define CAN_FAFIFOR1_FFA37 ((uint32_t)0x00000200) #define CAN_FAFIFOR1_FFA38 ((uint32_t)0x00000400) #define CAN_FAFIFOR1_FFA39 ((uint32_t)0x00000800) #define CAN_FAFIFOR1_FFA40 ((uint32_t)0x00001000) #define CAN_FAFIFOR1_FFA41 ((uint32_t)0x00002000) /******************** Bit definition for CAN_FWR register ********************/ #define CAN_FWR_FACT0 ((uint32_t)0x00000001) #define CAN_FWR_FACT1 ((uint32_t)0x00000002) #define CAN_FWR_FACT2 ((uint32_t)0x00000004) #define CAN_FWR_FACT3 ((uint32_t)0x00000008) #define CAN_FWR_FACT4 ((uint32_t)0x00000010) #define CAN_FWR_FACT5 ((uint32_t)0x00000020) #define CAN_FWR_FACT6 ((uint32_t)0x00000040) #define CAN_FWR_FACT7 ((uint32_t)0x00000080) #define CAN_FWR_FACT8 ((uint32_t)0x00000100) #define CAN_FWR_FACT9 ((uint32_t)0x00000200) #define CAN_FWR_FACT10 ((uint32_t)0x00000400) #define CAN_FWR_FACT11 ((uint32_t)0x00000800) #define CAN_FWR_FACT12 ((uint32_t)0x00001000) #define CAN_FWR_FACT13 ((uint32_t)0x00002000) #define CAN_FWR_FACT14 ((uint32_t)0x00004000) #define CAN_FWR_FACT15 ((uint32_t)0x00008000) #define CAN_FWR_FACT16 ((uint32_t)0x00010000) #define CAN_FWR_FACT17 ((uint32_t)0x00020000) #define CAN_FWR_FACT18 ((uint32_t)0x00040000) #define CAN_FWR_FACT19 ((uint32_t)0x00080000) #define CAN_FWR_FACT20 ((uint32_t)0x00100000) #define CAN_FWR_FACT21 ((uint32_t)0x00200000) #define CAN_FWR_FACT22 ((uint32_t)0x00400000) #define CAN_FWR_FACT23 ((uint32_t)0x00800000) #define CAN_FWR_FACT24 ((uint32_t)0x01000000) #define CAN_FWR_FACT25 ((uint32_t)0x02000000) #define CAN_FWR_FACT26 ((uint32_t)0x04000000) #define CAN_FWR_FACT27 ((uint32_t)0x08000000) /******************** Bit definition for CAN_FWR1 register ********************/ #define CAN_FWR1_FACT28 ((uint32_t)0x00000001) #define CAN_FWR1_FACT29 ((uint32_t)0x00000002) #define CAN_FWR1_FACT30 ((uint32_t)0x00000004) #define CAN_FWR1_FACT31 ((uint32_t)0x00000008) #define CAN_FWR1_FACT32 ((uint32_t)0x00000010) #define CAN_FWR1_FACT33 ((uint32_t)0x00000020) #define CAN_FWR1_FACT34 ((uint32_t)0x00000040) #define CAN_FWR1_FACT35 ((uint32_t)0x00000080) #define CAN_FWR1_FACT36 ((uint32_t)0x00000100) #define CAN_FWR1_FACT37 ((uint32_t)0x00000200) #define CAN_FWR1_FACT38 ((uint32_t)0x00000400) #define CAN_FWR1_FACT39 ((uint32_t)0x00000800) #define CAN_FWR1_FACT40 ((uint32_t)0x00001000) #define CAN_FWR1_FACT41 ((uint32_t)0x00002000) /******************** Bit definition for CAN_F0R1 register ********************/ #define CAN_F0R1_FB0 ((uint32_t)0x00000001) #define CAN_F0R1_FB1 ((uint32_t)0x00000002) #define CAN_F0R1_FB2 ((uint32_t)0x00000004) #define CAN_F0R1_FB3 ((uint32_t)0x00000008) #define CAN_F0R1_FB4 ((uint32_t)0x00000010) #define CAN_F0R1_FB5 ((uint32_t)0x00000020) #define CAN_F0R1_FB6 ((uint32_t)0x00000040) #define CAN_F0R1_FB7 ((uint32_t)0x00000080) #define CAN_F0R1_FB8 ((uint32_t)0x00000100) #define CAN_F0R1_FB9 ((uint32_t)0x00000200) #define CAN_F0R1_FB10 ((uint32_t)0x00000400) #define CAN_F0R1_FB11 ((uint32_t)0x00000800) #define CAN_F0R1_FB12 ((uint32_t)0x00001000) #define CAN_F0R1_FB13 ((uint32_t)0x00002000) #define CAN_F0R1_FB14 ((uint32_t)0x00004000) #define CAN_F0R1_FB15 ((uint32_t)0x00008000) #define CAN_F0R1_FB16 ((uint32_t)0x00010000) #define CAN_F0R1_FB17 ((uint32_t)0x00020000) #define CAN_F0R1_FB18 ((uint32_t)0x00040000) #define CAN_F0R1_FB19 ((uint32_t)0x00080000) #define CAN_F0R1_FB20 ((uint32_t)0x00100000) #define CAN_F0R1_FB21 ((uint32_t)0x00200000) #define CAN_F0R1_FB22 ((uint32_t)0x00400000) #define CAN_F0R1_FB23 ((uint32_t)0x00800000) #define CAN_F0R1_FB24 ((uint32_t)0x01000000) #define CAN_F0R1_FB25 ((uint32_t)0x02000000) #define CAN_F0R1_FB26 ((uint32_t)0x04000000) #define CAN_F0R1_FB27 ((uint32_t)0x08000000) #define CAN_F0R1_FB28 ((uint32_t)0x10000000) #define CAN_F0R1_FB29 ((uint32_t)0x20000000) #define CAN_F0R1_FB30 ((uint32_t)0x40000000) #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F1R1 register ********************/ #define CAN_F1R1_FB0 ((uint32_t)0x00000001) #define CAN_F1R1_FB1 ((uint32_t)0x00000002) #define CAN_F1R1_FB2 ((uint32_t)0x00000004) #define CAN_F1R1_FB3 ((uint32_t)0x00000008) #define CAN_F1R1_FB4 ((uint32_t)0x00000010) #define CAN_F1R1_FB5 ((uint32_t)0x00000020) #define CAN_F1R1_FB6 ((uint32_t)0x00000040) #define CAN_F1R1_FB7 ((uint32_t)0x00000080) #define CAN_F1R1_FB8 ((uint32_t)0x00000100) #define CAN_F1R1_FB9 ((uint32_t)0x00000200) #define CAN_F1R1_FB10 ((uint32_t)0x00000400) #define CAN_F1R1_FB11 ((uint32_t)0x00000800) #define CAN_F1R1_FB12 ((uint32_t)0x00001000) #define CAN_F1R1_FB13 ((uint32_t)0x00002000) #define CAN_F1R1_FB14 ((uint32_t)0x00004000) #define CAN_F1R1_FB15 ((uint32_t)0x00008000) #define CAN_F1R1_FB16 ((uint32_t)0x00010000) #define CAN_F1R1_FB17 ((uint32_t)0x00020000) #define CAN_F1R1_FB18 ((uint32_t)0x00040000) #define CAN_F1R1_FB19 ((uint32_t)0x00080000) #define CAN_F1R1_FB20 ((uint32_t)0x00100000) #define CAN_F1R1_FB21 ((uint32_t)0x00200000) #define CAN_F1R1_FB22 ((uint32_t)0x00400000) #define CAN_F1R1_FB23 ((uint32_t)0x00800000) #define CAN_F1R1_FB24 ((uint32_t)0x01000000) #define CAN_F1R1_FB25 ((uint32_t)0x02000000) #define CAN_F1R1_FB26 ((uint32_t)0x04000000) #define CAN_F1R1_FB27 ((uint32_t)0x08000000) #define CAN_F1R1_FB28 ((uint32_t)0x10000000) #define CAN_F1R1_FB29 ((uint32_t)0x20000000) #define CAN_F1R1_FB30 ((uint32_t)0x40000000) #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F2R1 register ********************/ #define CAN_F2R1_FB0 ((uint32_t)0x00000001) #define CAN_F2R1_FB1 ((uint32_t)0x00000002) #define CAN_F2R1_FB2 ((uint32_t)0x00000004) #define CAN_F2R1_FB3 ((uint32_t)0x00000008) #define CAN_F2R1_FB4 ((uint32_t)0x00000010) #define CAN_F2R1_FB5 ((uint32_t)0x00000020) #define CAN_F2R1_FB6 ((uint32_t)0x00000040) #define CAN_F2R1_FB7 ((uint32_t)0x00000080) #define CAN_F2R1_FB8 ((uint32_t)0x00000100) #define CAN_F2R1_FB9 ((uint32_t)0x00000200) #define CAN_F2R1_FB10 ((uint32_t)0x00000400) #define CAN_F2R1_FB11 ((uint32_t)0x00000800) #define CAN_F2R1_FB12 ((uint32_t)0x00001000) #define CAN_F2R1_FB13 ((uint32_t)0x00002000) #define CAN_F2R1_FB14 ((uint32_t)0x00004000) #define CAN_F2R1_FB15 ((uint32_t)0x00008000) #define CAN_F2R1_FB16 ((uint32_t)0x00010000) #define CAN_F2R1_FB17 ((uint32_t)0x00020000) #define CAN_F2R1_FB18 ((uint32_t)0x00040000) #define CAN_F2R1_FB19 ((uint32_t)0x00080000) #define CAN_F2R1_FB20 ((uint32_t)0x00100000) #define CAN_F2R1_FB21 ((uint32_t)0x00200000) #define CAN_F2R1_FB22 ((uint32_t)0x00400000) #define CAN_F2R1_FB23 ((uint32_t)0x00800000) #define CAN_F2R1_FB24 ((uint32_t)0x01000000) #define CAN_F2R1_FB25 ((uint32_t)0x02000000) #define CAN_F2R1_FB26 ((uint32_t)0x04000000) #define CAN_F2R1_FB27 ((uint32_t)0x08000000) #define CAN_F2R1_FB28 ((uint32_t)0x10000000) #define CAN_F2R1_FB29 ((uint32_t)0x20000000) #define CAN_F2R1_FB30 ((uint32_t)0x40000000) #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F3R1 register ********************/ #define CAN_F3R1_FB0 ((uint32_t)0x00000001) #define CAN_F3R1_FB1 ((uint32_t)0x00000002) #define CAN_F3R1_FB2 ((uint32_t)0x00000004) #define CAN_F3R1_FB3 ((uint32_t)0x00000008) #define CAN_F3R1_FB4 ((uint32_t)0x00000010) #define CAN_F3R1_FB5 ((uint32_t)0x00000020) #define CAN_F3R1_FB6 ((uint32_t)0x00000040) #define CAN_F3R1_FB7 ((uint32_t)0x00000080) #define CAN_F3R1_FB8 ((uint32_t)0x00000100) #define CAN_F3R1_FB9 ((uint32_t)0x00000200) #define CAN_F3R1_FB10 ((uint32_t)0x00000400) #define CAN_F3R1_FB11 ((uint32_t)0x00000800) #define CAN_F3R1_FB12 ((uint32_t)0x00001000) #define CAN_F3R1_FB13 ((uint32_t)0x00002000) #define CAN_F3R1_FB14 ((uint32_t)0x00004000) #define CAN_F3R1_FB15 ((uint32_t)0x00008000) #define CAN_F3R1_FB16 ((uint32_t)0x00010000) #define CAN_F3R1_FB17 ((uint32_t)0x00020000) #define CAN_F3R1_FB18 ((uint32_t)0x00040000) #define CAN_F3R1_FB19 ((uint32_t)0x00080000) #define CAN_F3R1_FB20 ((uint32_t)0x00100000) #define CAN_F3R1_FB21 ((uint32_t)0x00200000) #define CAN_F3R1_FB22 ((uint32_t)0x00400000) #define CAN_F3R1_FB23 ((uint32_t)0x00800000) #define CAN_F3R1_FB24 ((uint32_t)0x01000000) #define CAN_F3R1_FB25 ((uint32_t)0x02000000) #define CAN_F3R1_FB26 ((uint32_t)0x04000000) #define CAN_F3R1_FB27 ((uint32_t)0x08000000) #define CAN_F3R1_FB28 ((uint32_t)0x10000000) #define CAN_F3R1_FB29 ((uint32_t)0x20000000) #define CAN_F3R1_FB30 ((uint32_t)0x40000000) #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F4R1 register ********************/ #define CAN_F4R1_FB0 ((uint32_t)0x00000001) #define CAN_F4R1_FB1 ((uint32_t)0x00000002) #define CAN_F4R1_FB2 ((uint32_t)0x00000004) #define CAN_F4R1_FB3 ((uint32_t)0x00000008) #define CAN_F4R1_FB4 ((uint32_t)0x00000010) #define CAN_F4R1_FB5 ((uint32_t)0x00000020) #define CAN_F4R1_FB6 ((uint32_t)0x00000040) #define CAN_F4R1_FB7 ((uint32_t)0x00000080) #define CAN_F4R1_FB8 ((uint32_t)0x00000100) #define CAN_F4R1_FB9 ((uint32_t)0x00000200) #define CAN_F4R1_FB10 ((uint32_t)0x00000400) #define CAN_F4R1_FB11 ((uint32_t)0x00000800) #define CAN_F4R1_FB12 ((uint32_t)0x00001000) #define CAN_F4R1_FB13 ((uint32_t)0x00002000) #define CAN_F4R1_FB14 ((uint32_t)0x00004000) #define CAN_F4R1_FB15 ((uint32_t)0x00008000) #define CAN_F4R1_FB16 ((uint32_t)0x00010000) #define CAN_F4R1_FB17 ((uint32_t)0x00020000) #define CAN_F4R1_FB18 ((uint32_t)0x00040000) #define CAN_F4R1_FB19 ((uint32_t)0x00080000) #define CAN_F4R1_FB20 ((uint32_t)0x00100000) #define CAN_F4R1_FB21 ((uint32_t)0x00200000) #define CAN_F4R1_FB22 ((uint32_t)0x00400000) #define CAN_F4R1_FB23 ((uint32_t)0x00800000) #define CAN_F4R1_FB24 ((uint32_t)0x01000000) #define CAN_F4R1_FB25 ((uint32_t)0x02000000) #define CAN_F4R1_FB26 ((uint32_t)0x04000000) #define CAN_F4R1_FB27 ((uint32_t)0x08000000) #define CAN_F4R1_FB28 ((uint32_t)0x10000000) #define CAN_F4R1_FB29 ((uint32_t)0x20000000) #define CAN_F4R1_FB30 ((uint32_t)0x40000000) #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F5R1 register ********************/ #define CAN_F5R1_FB0 ((uint32_t)0x00000001) #define CAN_F5R1_FB1 ((uint32_t)0x00000002) #define CAN_F5R1_FB2 ((uint32_t)0x00000004) #define CAN_F5R1_FB3 ((uint32_t)0x00000008) #define CAN_F5R1_FB4 ((uint32_t)0x00000010) #define CAN_F5R1_FB5 ((uint32_t)0x00000020) #define CAN_F5R1_FB6 ((uint32_t)0x00000040) #define CAN_F5R1_FB7 ((uint32_t)0x00000080) #define CAN_F5R1_FB8 ((uint32_t)0x00000100) #define CAN_F5R1_FB9 ((uint32_t)0x00000200) #define CAN_F5R1_FB10 ((uint32_t)0x00000400) #define CAN_F5R1_FB11 ((uint32_t)0x00000800) #define CAN_F5R1_FB12 ((uint32_t)0x00001000) #define CAN_F5R1_FB13 ((uint32_t)0x00002000) #define CAN_F5R1_FB14 ((uint32_t)0x00004000) #define CAN_F5R1_FB15 ((uint32_t)0x00008000) #define CAN_F5R1_FB16 ((uint32_t)0x00010000) #define CAN_F5R1_FB17 ((uint32_t)0x00020000) #define CAN_F5R1_FB18 ((uint32_t)0x00040000) #define CAN_F5R1_FB19 ((uint32_t)0x00080000) #define CAN_F5R1_FB20 ((uint32_t)0x00100000) #define CAN_F5R1_FB21 ((uint32_t)0x00200000) #define CAN_F5R1_FB22 ((uint32_t)0x00400000) #define CAN_F5R1_FB23 ((uint32_t)0x00800000) #define CAN_F5R1_FB24 ((uint32_t)0x01000000) #define CAN_F5R1_FB25 ((uint32_t)0x02000000) #define CAN_F5R1_FB26 ((uint32_t)0x04000000) #define CAN_F5R1_FB27 ((uint32_t)0x08000000) #define CAN_F5R1_FB28 ((uint32_t)0x10000000) #define CAN_F5R1_FB29 ((uint32_t)0x20000000) #define CAN_F5R1_FB30 ((uint32_t)0x40000000) #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F6R1 register ********************/ #define CAN_F6R1_FB0 ((uint32_t)0x00000001) #define CAN_F6R1_FB1 ((uint32_t)0x00000002) #define CAN_F6R1_FB2 ((uint32_t)0x00000004) #define CAN_F6R1_FB3 ((uint32_t)0x00000008) #define CAN_F6R1_FB4 ((uint32_t)0x00000010) #define CAN_F6R1_FB5 ((uint32_t)0x00000020) #define CAN_F6R1_FB6 ((uint32_t)0x00000040) #define CAN_F6R1_FB7 ((uint32_t)0x00000080) #define CAN_F6R1_FB8 ((uint32_t)0x00000100) #define CAN_F6R1_FB9 ((uint32_t)0x00000200) #define CAN_F6R1_FB10 ((uint32_t)0x00000400) #define CAN_F6R1_FB11 ((uint32_t)0x00000800) #define CAN_F6R1_FB12 ((uint32_t)0x00001000) #define CAN_F6R1_FB13 ((uint32_t)0x00002000) #define CAN_F6R1_FB14 ((uint32_t)0x00004000) #define CAN_F6R1_FB15 ((uint32_t)0x00008000) #define CAN_F6R1_FB16 ((uint32_t)0x00010000) #define CAN_F6R1_FB17 ((uint32_t)0x00020000) #define CAN_F6R1_FB18 ((uint32_t)0x00040000) #define CAN_F6R1_FB19 ((uint32_t)0x00080000) #define CAN_F6R1_FB20 ((uint32_t)0x00100000) #define CAN_F6R1_FB21 ((uint32_t)0x00200000) #define CAN_F6R1_FB22 ((uint32_t)0x00400000) #define CAN_F6R1_FB23 ((uint32_t)0x00800000) #define CAN_F6R1_FB24 ((uint32_t)0x01000000) #define CAN_F6R1_FB25 ((uint32_t)0x02000000) #define CAN_F6R1_FB26 ((uint32_t)0x04000000) #define CAN_F6R1_FB27 ((uint32_t)0x08000000) #define CAN_F6R1_FB28 ((uint32_t)0x10000000) #define CAN_F6R1_FB29 ((uint32_t)0x20000000) #define CAN_F6R1_FB30 ((uint32_t)0x40000000) #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F7R1 register ********************/ #define CAN_F7R1_FB0 ((uint32_t)0x00000001) #define CAN_F7R1_FB1 ((uint32_t)0x00000002) #define CAN_F7R1_FB2 ((uint32_t)0x00000004) #define CAN_F7R1_FB3 ((uint32_t)0x00000008) #define CAN_F7R1_FB4 ((uint32_t)0x00000010) #define CAN_F7R1_FB5 ((uint32_t)0x00000020) #define CAN_F7R1_FB6 ((uint32_t)0x00000040) #define CAN_F7R1_FB7 ((uint32_t)0x00000080) #define CAN_F7R1_FB8 ((uint32_t)0x00000100) #define CAN_F7R1_FB9 ((uint32_t)0x00000200) #define CAN_F7R1_FB10 ((uint32_t)0x00000400) #define CAN_F7R1_FB11 ((uint32_t)0x00000800) #define CAN_F7R1_FB12 ((uint32_t)0x00001000) #define CAN_F7R1_FB13 ((uint32_t)0x00002000) #define CAN_F7R1_FB14 ((uint32_t)0x00004000) #define CAN_F7R1_FB15 ((uint32_t)0x00008000) #define CAN_F7R1_FB16 ((uint32_t)0x00010000) #define CAN_F7R1_FB17 ((uint32_t)0x00020000) #define CAN_F7R1_FB18 ((uint32_t)0x00040000) #define CAN_F7R1_FB19 ((uint32_t)0x00080000) #define CAN_F7R1_FB20 ((uint32_t)0x00100000) #define CAN_F7R1_FB21 ((uint32_t)0x00200000) #define CAN_F7R1_FB22 ((uint32_t)0x00400000) #define CAN_F7R1_FB23 ((uint32_t)0x00800000) #define CAN_F7R1_FB24 ((uint32_t)0x01000000) #define CAN_F7R1_FB25 ((uint32_t)0x02000000) #define CAN_F7R1_FB26 ((uint32_t)0x04000000) #define CAN_F7R1_FB27 ((uint32_t)0x08000000) #define CAN_F7R1_FB28 ((uint32_t)0x10000000) #define CAN_F7R1_FB29 ((uint32_t)0x20000000) #define CAN_F7R1_FB30 ((uint32_t)0x40000000) #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F8R1 register ********************/ #define CAN_F8R1_FB0 ((uint32_t)0x00000001) #define CAN_F8R1_FB1 ((uint32_t)0x00000002) #define CAN_F8R1_FB2 ((uint32_t)0x00000004) #define CAN_F8R1_FB3 ((uint32_t)0x00000008) #define CAN_F8R1_FB4 ((uint32_t)0x00000010) #define CAN_F8R1_FB5 ((uint32_t)0x00000020) #define CAN_F8R1_FB6 ((uint32_t)0x00000040) #define CAN_F8R1_FB7 ((uint32_t)0x00000080) #define CAN_F8R1_FB8 ((uint32_t)0x00000100) #define CAN_F8R1_FB9 ((uint32_t)0x00000200) #define CAN_F8R1_FB10 ((uint32_t)0x00000400) #define CAN_F8R1_FB11 ((uint32_t)0x00000800) #define CAN_F8R1_FB12 ((uint32_t)0x00001000) #define CAN_F8R1_FB13 ((uint32_t)0x00002000) #define CAN_F8R1_FB14 ((uint32_t)0x00004000) #define CAN_F8R1_FB15 ((uint32_t)0x00008000) #define CAN_F8R1_FB16 ((uint32_t)0x00010000) #define CAN_F8R1_FB17 ((uint32_t)0x00020000) #define CAN_F8R1_FB18 ((uint32_t)0x00040000) #define CAN_F8R1_FB19 ((uint32_t)0x00080000) #define CAN_F8R1_FB20 ((uint32_t)0x00100000) #define CAN_F8R1_FB21 ((uint32_t)0x00200000) #define CAN_F8R1_FB22 ((uint32_t)0x00400000) #define CAN_F8R1_FB23 ((uint32_t)0x00800000) #define CAN_F8R1_FB24 ((uint32_t)0x01000000) #define CAN_F8R1_FB25 ((uint32_t)0x02000000) #define CAN_F8R1_FB26 ((uint32_t)0x04000000) #define CAN_F8R1_FB27 ((uint32_t)0x08000000) #define CAN_F8R1_FB28 ((uint32_t)0x10000000) #define CAN_F8R1_FB29 ((uint32_t)0x20000000) #define CAN_F8R1_FB30 ((uint32_t)0x40000000) #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F9R1 register ********************/ #define CAN_F9R1_FB0 ((uint32_t)0x00000001) #define CAN_F9R1_FB1 ((uint32_t)0x00000002) #define CAN_F9R1_FB2 ((uint32_t)0x00000004) #define CAN_F9R1_FB3 ((uint32_t)0x00000008) #define CAN_F9R1_FB4 ((uint32_t)0x00000010) #define CAN_F9R1_FB5 ((uint32_t)0x00000020) #define CAN_F9R1_FB6 ((uint32_t)0x00000040) #define CAN_F9R1_FB7 ((uint32_t)0x00000080) #define CAN_F9R1_FB8 ((uint32_t)0x00000100) #define CAN_F9R1_FB9 ((uint32_t)0x00000200) #define CAN_F9R1_FB10 ((uint32_t)0x00000400) #define CAN_F9R1_FB11 ((uint32_t)0x00000800) #define CAN_F9R1_FB12 ((uint32_t)0x00001000) #define CAN_F9R1_FB13 ((uint32_t)0x00002000) #define CAN_F9R1_FB14 ((uint32_t)0x00004000) #define CAN_F9R1_FB15 ((uint32_t)0x00008000) #define CAN_F9R1_FB16 ((uint32_t)0x00010000) #define CAN_F9R1_FB17 ((uint32_t)0x00020000) #define CAN_F9R1_FB18 ((uint32_t)0x00040000) #define CAN_F9R1_FB19 ((uint32_t)0x00080000) #define CAN_F9R1_FB20 ((uint32_t)0x00100000) #define CAN_F9R1_FB21 ((uint32_t)0x00200000) #define CAN_F9R1_FB22 ((uint32_t)0x00400000) #define CAN_F9R1_FB23 ((uint32_t)0x00800000) #define CAN_F9R1_FB24 ((uint32_t)0x01000000) #define CAN_F9R1_FB25 ((uint32_t)0x02000000) #define CAN_F9R1_FB26 ((uint32_t)0x04000000) #define CAN_F9R1_FB27 ((uint32_t)0x08000000) #define CAN_F9R1_FB28 ((uint32_t)0x10000000) #define CAN_F9R1_FB29 ((uint32_t)0x20000000) #define CAN_F9R1_FB30 ((uint32_t)0x40000000) #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F10R1 register ********************/ #define CAN_F10R1_FB0 ((uint32_t)0x00000001) #define CAN_F10R1_FB1 ((uint32_t)0x00000002) #define CAN_F10R1_FB2 ((uint32_t)0x00000004) #define CAN_F10R1_FB3 ((uint32_t)0x00000008) #define CAN_F10R1_FB4 ((uint32_t)0x00000010) #define CAN_F10R1_FB5 ((uint32_t)0x00000020) #define CAN_F10R1_FB6 ((uint32_t)0x00000040) #define CAN_F10R1_FB7 ((uint32_t)0x00000080) #define CAN_F10R1_FB8 ((uint32_t)0x00000100) #define CAN_F10R1_FB9 ((uint32_t)0x00000200) #define CAN_F10R1_FB10 ((uint32_t)0x00000400) #define CAN_F10R1_FB11 ((uint32_t)0x00000800) #define CAN_F10R1_FB12 ((uint32_t)0x00001000) #define CAN_F10R1_FB13 ((uint32_t)0x00002000) #define CAN_F10R1_FB14 ((uint32_t)0x00004000) #define CAN_F10R1_FB15 ((uint32_t)0x00008000) #define CAN_F10R1_FB16 ((uint32_t)0x00010000) #define CAN_F10R1_FB17 ((uint32_t)0x00020000) #define CAN_F10R1_FB18 ((uint32_t)0x00040000) #define CAN_F10R1_FB19 ((uint32_t)0x00080000) #define CAN_F10R1_FB20 ((uint32_t)0x00100000) #define CAN_F10R1_FB21 ((uint32_t)0x00200000) #define CAN_F10R1_FB22 ((uint32_t)0x00400000) #define CAN_F10R1_FB23 ((uint32_t)0x00800000) #define CAN_F10R1_FB24 ((uint32_t)0x01000000) #define CAN_F10R1_FB25 ((uint32_t)0x02000000) #define CAN_F10R1_FB26 ((uint32_t)0x04000000) #define CAN_F10R1_FB27 ((uint32_t)0x08000000) #define CAN_F10R1_FB28 ((uint32_t)0x10000000) #define CAN_F10R1_FB29 ((uint32_t)0x20000000) #define CAN_F10R1_FB30 ((uint32_t)0x40000000) #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F11R1 register ********************/ #define CAN_F11R1_FB0 ((uint32_t)0x00000001) #define CAN_F11R1_FB1 ((uint32_t)0x00000002) #define CAN_F11R1_FB2 ((uint32_t)0x00000004) #define CAN_F11R1_FB3 ((uint32_t)0x00000008) #define CAN_F11R1_FB4 ((uint32_t)0x00000010) #define CAN_F11R1_FB5 ((uint32_t)0x00000020) #define CAN_F11R1_FB6 ((uint32_t)0x00000040) #define CAN_F11R1_FB7 ((uint32_t)0x00000080) #define CAN_F11R1_FB8 ((uint32_t)0x00000100) #define CAN_F11R1_FB9 ((uint32_t)0x00000200) #define CAN_F11R1_FB10 ((uint32_t)0x00000400) #define CAN_F11R1_FB11 ((uint32_t)0x00000800) #define CAN_F11R1_FB12 ((uint32_t)0x00001000) #define CAN_F11R1_FB13 ((uint32_t)0x00002000) #define CAN_F11R1_FB14 ((uint32_t)0x00004000) #define CAN_F11R1_FB15 ((uint32_t)0x00008000) #define CAN_F11R1_FB16 ((uint32_t)0x00010000) #define CAN_F11R1_FB17 ((uint32_t)0x00020000) #define CAN_F11R1_FB18 ((uint32_t)0x00040000) #define CAN_F11R1_FB19 ((uint32_t)0x00080000) #define CAN_F11R1_FB20 ((uint32_t)0x00100000) #define CAN_F11R1_FB21 ((uint32_t)0x00200000) #define CAN_F11R1_FB22 ((uint32_t)0x00400000) #define CAN_F11R1_FB23 ((uint32_t)0x00800000) #define CAN_F11R1_FB24 ((uint32_t)0x01000000) #define CAN_F11R1_FB25 ((uint32_t)0x02000000) #define CAN_F11R1_FB26 ((uint32_t)0x04000000) #define CAN_F11R1_FB27 ((uint32_t)0x08000000) #define CAN_F11R1_FB28 ((uint32_t)0x10000000) #define CAN_F11R1_FB29 ((uint32_t)0x20000000) #define CAN_F11R1_FB30 ((uint32_t)0x40000000) #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F12R1 register ********************/ #define CAN_F12R1_FB0 ((uint32_t)0x00000001) #define CAN_F12R1_FB1 ((uint32_t)0x00000002) #define CAN_F12R1_FB2 ((uint32_t)0x00000004) #define CAN_F12R1_FB3 ((uint32_t)0x00000008) #define CAN_F12R1_FB4 ((uint32_t)0x00000010) #define CAN_F12R1_FB5 ((uint32_t)0x00000020) #define CAN_F12R1_FB6 ((uint32_t)0x00000040) #define CAN_F12R1_FB7 ((uint32_t)0x00000080) #define CAN_F12R1_FB8 ((uint32_t)0x00000100) #define CAN_F12R1_FB9 ((uint32_t)0x00000200) #define CAN_F12R1_FB10 ((uint32_t)0x00000400) #define CAN_F12R1_FB11 ((uint32_t)0x00000800) #define CAN_F12R1_FB12 ((uint32_t)0x00001000) #define CAN_F12R1_FB13 ((uint32_t)0x00002000) #define CAN_F12R1_FB14 ((uint32_t)0x00004000) #define CAN_F12R1_FB15 ((uint32_t)0x00008000) #define CAN_F12R1_FB16 ((uint32_t)0x00010000) #define CAN_F12R1_FB17 ((uint32_t)0x00020000) #define CAN_F12R1_FB18 ((uint32_t)0x00040000) #define CAN_F12R1_FB19 ((uint32_t)0x00080000) #define CAN_F12R1_FB20 ((uint32_t)0x00100000) #define CAN_F12R1_FB21 ((uint32_t)0x00200000) #define CAN_F12R1_FB22 ((uint32_t)0x00400000) #define CAN_F12R1_FB23 ((uint32_t)0x00800000) #define CAN_F12R1_FB24 ((uint32_t)0x01000000) #define CAN_F12R1_FB25 ((uint32_t)0x02000000) #define CAN_F12R1_FB26 ((uint32_t)0x04000000) #define CAN_F12R1_FB27 ((uint32_t)0x08000000) #define CAN_F12R1_FB28 ((uint32_t)0x10000000) #define CAN_F12R1_FB29 ((uint32_t)0x20000000) #define CAN_F12R1_FB30 ((uint32_t)0x40000000) #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F13R1 register ********************/ #define CAN_F13R1_FB0 ((uint32_t)0x00000001) #define CAN_F13R1_FB1 ((uint32_t)0x00000002) #define CAN_F13R1_FB2 ((uint32_t)0x00000004) #define CAN_F13R1_FB3 ((uint32_t)0x00000008) #define CAN_F13R1_FB4 ((uint32_t)0x00000010) #define CAN_F13R1_FB5 ((uint32_t)0x00000020) #define CAN_F13R1_FB6 ((uint32_t)0x00000040) #define CAN_F13R1_FB7 ((uint32_t)0x00000080) #define CAN_F13R1_FB8 ((uint32_t)0x00000100) #define CAN_F13R1_FB9 ((uint32_t)0x00000200) #define CAN_F13R1_FB10 ((uint32_t)0x00000400) #define CAN_F13R1_FB11 ((uint32_t)0x00000800) #define CAN_F13R1_FB12 ((uint32_t)0x00001000) #define CAN_F13R1_FB13 ((uint32_t)0x00002000) #define CAN_F13R1_FB14 ((uint32_t)0x00004000) #define CAN_F13R1_FB15 ((uint32_t)0x00008000) #define CAN_F13R1_FB16 ((uint32_t)0x00010000) #define CAN_F13R1_FB17 ((uint32_t)0x00020000) #define CAN_F13R1_FB18 ((uint32_t)0x00040000) #define CAN_F13R1_FB19 ((uint32_t)0x00080000) #define CAN_F13R1_FB20 ((uint32_t)0x00100000) #define CAN_F13R1_FB21 ((uint32_t)0x00200000) #define CAN_F13R1_FB22 ((uint32_t)0x00400000) #define CAN_F13R1_FB23 ((uint32_t)0x00800000) #define CAN_F13R1_FB24 ((uint32_t)0x01000000) #define CAN_F13R1_FB25 ((uint32_t)0x02000000) #define CAN_F13R1_FB26 ((uint32_t)0x04000000) #define CAN_F13R1_FB27 ((uint32_t)0x08000000) #define CAN_F13R1_FB28 ((uint32_t)0x10000000) #define CAN_F13R1_FB29 ((uint32_t)0x20000000) #define CAN_F13R1_FB30 ((uint32_t)0x40000000) #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F14R1 register ********************/ #define CAN_F14R1_FB0 ((uint32_t)0x00000001) #define CAN_F14R1_FB1 ((uint32_t)0x00000002) #define CAN_F14R1_FB2 ((uint32_t)0x00000004) #define CAN_F14R1_FB3 ((uint32_t)0x00000008) #define CAN_F14R1_FB4 ((uint32_t)0x00000010) #define CAN_F14R1_FB5 ((uint32_t)0x00000020) #define CAN_F14R1_FB6 ((uint32_t)0x00000040) #define CAN_F14R1_FB7 ((uint32_t)0x00000080) #define CAN_F14R1_FB8 ((uint32_t)0x00000100) #define CAN_F14R1_FB9 ((uint32_t)0x00000200) #define CAN_F14R1_FB10 ((uint32_t)0x00000400) #define CAN_F14R1_FB11 ((uint32_t)0x00000800) #define CAN_F14R1_FB12 ((uint32_t)0x00001000) #define CAN_F14R1_FB13 ((uint32_t)0x00002000) #define CAN_F14R1_FB14 ((uint32_t)0x00004000) #define CAN_F14R1_FB15 ((uint32_t)0x00008000) #define CAN_F14R1_FB16 ((uint32_t)0x00010000) #define CAN_F14R1_FB17 ((uint32_t)0x00020000) #define CAN_F14R1_FB18 ((uint32_t)0x00040000) #define CAN_F14R1_FB19 ((uint32_t)0x00080000) #define CAN_F14R1_FB20 ((uint32_t)0x00100000) #define CAN_F14R1_FB21 ((uint32_t)0x00200000) #define CAN_F14R1_FB22 ((uint32_t)0x00400000) #define CAN_F14R1_FB23 ((uint32_t)0x00800000) #define CAN_F14R1_FB24 ((uint32_t)0x01000000) #define CAN_F14R1_FB25 ((uint32_t)0x02000000) #define CAN_F14R1_FB26 ((uint32_t)0x04000000) #define CAN_F14R1_FB27 ((uint32_t)0x08000000) #define CAN_F14R1_FB28 ((uint32_t)0x10000000) #define CAN_F14R1_FB29 ((uint32_t)0x20000000) #define CAN_F14R1_FB30 ((uint32_t)0x40000000) #define CAN_F14R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F15R1 register ********************/ #define CAN_F15R1_FB0 ((uint32_t)0x00000001) #define CAN_F15R1_FB1 ((uint32_t)0x00000002) #define CAN_F15R1_FB2 ((uint32_t)0x00000004) #define CAN_F15R1_FB3 ((uint32_t)0x00000008) #define CAN_F15R1_FB4 ((uint32_t)0x00000010) #define CAN_F15R1_FB5 ((uint32_t)0x00000020) #define CAN_F15R1_FB6 ((uint32_t)0x00000040) #define CAN_F15R1_FB7 ((uint32_t)0x00000080) #define CAN_F15R1_FB8 ((uint32_t)0x00000100) #define CAN_F15R1_FB9 ((uint32_t)0x00000200) #define CAN_F15R1_FB10 ((uint32_t)0x00000400) #define CAN_F15R1_FB11 ((uint32_t)0x00000800) #define CAN_F15R1_FB12 ((uint32_t)0x00001000) #define CAN_F15R1_FB13 ((uint32_t)0x00002000) #define CAN_F15R1_FB14 ((uint32_t)0x00004000) #define CAN_F15R1_FB15 ((uint32_t)0x00008000) #define CAN_F15R1_FB16 ((uint32_t)0x00010000) #define CAN_F15R1_FB17 ((uint32_t)0x00020000) #define CAN_F15R1_FB18 ((uint32_t)0x00040000) #define CAN_F15R1_FB19 ((uint32_t)0x00080000) #define CAN_F15R1_FB20 ((uint32_t)0x00100000) #define CAN_F15R1_FB21 ((uint32_t)0x00200000) #define CAN_F15R1_FB22 ((uint32_t)0x00400000) #define CAN_F15R1_FB23 ((uint32_t)0x00800000) #define CAN_F15R1_FB24 ((uint32_t)0x01000000) #define CAN_F15R1_FB25 ((uint32_t)0x02000000) #define CAN_F15R1_FB26 ((uint32_t)0x04000000) #define CAN_F15R1_FB27 ((uint32_t)0x08000000) #define CAN_F15R1_FB28 ((uint32_t)0x10000000) #define CAN_F15R1_FB29 ((uint32_t)0x20000000) #define CAN_F15R1_FB30 ((uint32_t)0x40000000) #define CAN_F15R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F16R1 register ********************/ #define CAN_F16R1_FB0 ((uint32_t)0x00000001) #define CAN_F16R1_FB1 ((uint32_t)0x00000002) #define CAN_F16R1_FB2 ((uint32_t)0x00000004) #define CAN_F16R1_FB3 ((uint32_t)0x00000008) #define CAN_F16R1_FB4 ((uint32_t)0x00000010) #define CAN_F16R1_FB5 ((uint32_t)0x00000020) #define CAN_F16R1_FB6 ((uint32_t)0x00000040) #define CAN_F16R1_FB7 ((uint32_t)0x00000080) #define CAN_F16R1_FB8 ((uint32_t)0x00000100) #define CAN_F16R1_FB9 ((uint32_t)0x00000200) #define CAN_F16R1_FB10 ((uint32_t)0x00000400) #define CAN_F16R1_FB11 ((uint32_t)0x00000800) #define CAN_F16R1_FB12 ((uint32_t)0x00001000) #define CAN_F16R1_FB13 ((uint32_t)0x00002000) #define CAN_F16R1_FB14 ((uint32_t)0x00004000) #define CAN_F16R1_FB15 ((uint32_t)0x00008000) #define CAN_F16R1_FB16 ((uint32_t)0x00010000) #define CAN_F16R1_FB17 ((uint32_t)0x00020000) #define CAN_F16R1_FB18 ((uint32_t)0x00040000) #define CAN_F16R1_FB19 ((uint32_t)0x00080000) #define CAN_F16R1_FB20 ((uint32_t)0x00100000) #define CAN_F16R1_FB21 ((uint32_t)0x00200000) #define CAN_F16R1_FB22 ((uint32_t)0x00400000) #define CAN_F16R1_FB23 ((uint32_t)0x00800000) #define CAN_F16R1_FB24 ((uint32_t)0x01000000) #define CAN_F16R1_FB25 ((uint32_t)0x02000000) #define CAN_F16R1_FB26 ((uint32_t)0x04000000) #define CAN_F16R1_FB27 ((uint32_t)0x08000000) #define CAN_F16R1_FB28 ((uint32_t)0x10000000) #define CAN_F16R1_FB29 ((uint32_t)0x20000000) #define CAN_F16R1_FB30 ((uint32_t)0x40000000) #define CAN_F16R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F17R1 register ********************/ #define CAN_F17R1_FB0 ((uint32_t)0x00000001) #define CAN_F17R1_FB1 ((uint32_t)0x00000002) #define CAN_F17R1_FB2 ((uint32_t)0x00000004) #define CAN_F17R1_FB3 ((uint32_t)0x00000008) #define CAN_F17R1_FB4 ((uint32_t)0x00000010) #define CAN_F17R1_FB5 ((uint32_t)0x00000020) #define CAN_F17R1_FB6 ((uint32_t)0x00000040) #define CAN_F17R1_FB7 ((uint32_t)0x00000080) #define CAN_F17R1_FB8 ((uint32_t)0x00000100) #define CAN_F17R1_FB9 ((uint32_t)0x00000200) #define CAN_F17R1_FB10 ((uint32_t)0x00000400) #define CAN_F17R1_FB11 ((uint32_t)0x00000800) #define CAN_F17R1_FB12 ((uint32_t)0x00001000) #define CAN_F17R1_FB13 ((uint32_t)0x00002000) #define CAN_F17R1_FB14 ((uint32_t)0x00004000) #define CAN_F17R1_FB15 ((uint32_t)0x00008000) #define CAN_F17R1_FB16 ((uint32_t)0x00010000) #define CAN_F17R1_FB17 ((uint32_t)0x00020000) #define CAN_F17R1_FB18 ((uint32_t)0x00040000) #define CAN_F17R1_FB19 ((uint32_t)0x00080000) #define CAN_F17R1_FB20 ((uint32_t)0x00100000) #define CAN_F17R1_FB21 ((uint32_t)0x00200000) #define CAN_F17R1_FB22 ((uint32_t)0x00400000) #define CAN_F17R1_FB23 ((uint32_t)0x00800000) #define CAN_F17R1_FB24 ((uint32_t)0x01000000) #define CAN_F17R1_FB25 ((uint32_t)0x02000000) #define CAN_F17R1_FB26 ((uint32_t)0x04000000) #define CAN_F17R1_FB27 ((uint32_t)0x08000000) #define CAN_F17R1_FB28 ((uint32_t)0x10000000) #define CAN_F17R1_FB29 ((uint32_t)0x20000000) #define CAN_F17R1_FB30 ((uint32_t)0x40000000) #define CAN_F17R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F18R1 register ********************/ #define CAN_F18R1_FB0 ((uint32_t)0x00000001) #define CAN_F18R1_FB1 ((uint32_t)0x00000002) #define CAN_F18R1_FB2 ((uint32_t)0x00000004) #define CAN_F18R1_FB3 ((uint32_t)0x00000008) #define CAN_F18R1_FB4 ((uint32_t)0x00000010) #define CAN_F18R1_FB5 ((uint32_t)0x00000020) #define CAN_F18R1_FB6 ((uint32_t)0x00000040) #define CAN_F18R1_FB7 ((uint32_t)0x00000080) #define CAN_F18R1_FB8 ((uint32_t)0x00000100) #define CAN_F18R1_FB9 ((uint32_t)0x00000200) #define CAN_F18R1_FB10 ((uint32_t)0x00000400) #define CAN_F18R1_FB11 ((uint32_t)0x00000800) #define CAN_F18R1_FB12 ((uint32_t)0x00001000) #define CAN_F18R1_FB13 ((uint32_t)0x00002000) #define CAN_F18R1_FB14 ((uint32_t)0x00004000) #define CAN_F18R1_FB15 ((uint32_t)0x00008000) #define CAN_F18R1_FB16 ((uint32_t)0x00010000) #define CAN_F18R1_FB17 ((uint32_t)0x00020000) #define CAN_F18R1_FB18 ((uint32_t)0x00040000) #define CAN_F18R1_FB19 ((uint32_t)0x00080000) #define CAN_F18R1_FB20 ((uint32_t)0x00100000) #define CAN_F18R1_FB21 ((uint32_t)0x00200000) #define CAN_F18R1_FB22 ((uint32_t)0x00400000) #define CAN_F18R1_FB23 ((uint32_t)0x00800000) #define CAN_F18R1_FB24 ((uint32_t)0x01000000) #define CAN_F18R1_FB25 ((uint32_t)0x02000000) #define CAN_F18R1_FB26 ((uint32_t)0x04000000) #define CAN_F18R1_FB27 ((uint32_t)0x08000000) #define CAN_F18R1_FB28 ((uint32_t)0x10000000) #define CAN_F18R1_FB29 ((uint32_t)0x20000000) #define CAN_F18R1_FB30 ((uint32_t)0x40000000) #define CAN_F18R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F19R1 register ********************/ #define CAN_F19R1_FB0 ((uint32_t)0x00000001) #define CAN_F19R1_FB1 ((uint32_t)0x00000002) #define CAN_F19R1_FB2 ((uint32_t)0x00000004) #define CAN_F19R1_FB3 ((uint32_t)0x00000008) #define CAN_F19R1_FB4 ((uint32_t)0x00000010) #define CAN_F19R1_FB5 ((uint32_t)0x00000020) #define CAN_F19R1_FB6 ((uint32_t)0x00000040) #define CAN_F19R1_FB7 ((uint32_t)0x00000080) #define CAN_F19R1_FB8 ((uint32_t)0x00000100) #define CAN_F19R1_FB9 ((uint32_t)0x00000200) #define CAN_F19R1_FB10 ((uint32_t)0x00000400) #define CAN_F19R1_FB11 ((uint32_t)0x00000800) #define CAN_F19R1_FB12 ((uint32_t)0x00001000) #define CAN_F19R1_FB13 ((uint32_t)0x00002000) #define CAN_F19R1_FB14 ((uint32_t)0x00004000) #define CAN_F19R1_FB15 ((uint32_t)0x00008000) #define CAN_F19R1_FB16 ((uint32_t)0x00010000) #define CAN_F19R1_FB17 ((uint32_t)0x00020000) #define CAN_F19R1_FB18 ((uint32_t)0x00040000) #define CAN_F19R1_FB19 ((uint32_t)0x00080000) #define CAN_F19R1_FB20 ((uint32_t)0x00100000) #define CAN_F19R1_FB21 ((uint32_t)0x00200000) #define CAN_F19R1_FB22 ((uint32_t)0x00400000) #define CAN_F19R1_FB23 ((uint32_t)0x00800000) #define CAN_F19R1_FB24 ((uint32_t)0x01000000) #define CAN_F19R1_FB25 ((uint32_t)0x02000000) #define CAN_F19R1_FB26 ((uint32_t)0x04000000) #define CAN_F19R1_FB27 ((uint32_t)0x08000000) #define CAN_F19R1_FB28 ((uint32_t)0x10000000) #define CAN_F19R1_FB29 ((uint32_t)0x20000000) #define CAN_F19R1_FB30 ((uint32_t)0x40000000) #define CAN_F19R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F20R1 register ********************/ #define CAN_F20R1_FB0 ((uint32_t)0x00000001) #define CAN_F20R1_FB1 ((uint32_t)0x00000002) #define CAN_F20R1_FB2 ((uint32_t)0x00000004) #define CAN_F20R1_FB3 ((uint32_t)0x00000008) #define CAN_F20R1_FB4 ((uint32_t)0x00000010) #define CAN_F20R1_FB5 ((uint32_t)0x00000020) #define CAN_F20R1_FB6 ((uint32_t)0x00000040) #define CAN_F20R1_FB7 ((uint32_t)0x00000080) #define CAN_F20R1_FB8 ((uint32_t)0x00000100) #define CAN_F20R1_FB9 ((uint32_t)0x00000200) #define CAN_F20R1_FB10 ((uint32_t)0x00000400) #define CAN_F20R1_FB11 ((uint32_t)0x00000800) #define CAN_F20R1_FB12 ((uint32_t)0x00001000) #define CAN_F20R1_FB13 ((uint32_t)0x00002000) #define CAN_F20R1_FB14 ((uint32_t)0x00004000) #define CAN_F20R1_FB15 ((uint32_t)0x00008000) #define CAN_F20R1_FB16 ((uint32_t)0x00010000) #define CAN_F20R1_FB17 ((uint32_t)0x00020000) #define CAN_F20R1_FB18 ((uint32_t)0x00040000) #define CAN_F20R1_FB19 ((uint32_t)0x00080000) #define CAN_F20R1_FB20 ((uint32_t)0x00100000) #define CAN_F20R1_FB21 ((uint32_t)0x00200000) #define CAN_F20R1_FB22 ((uint32_t)0x00400000) #define CAN_F20R1_FB23 ((uint32_t)0x00800000) #define CAN_F20R1_FB24 ((uint32_t)0x01000000) #define CAN_F20R1_FB25 ((uint32_t)0x02000000) #define CAN_F20R1_FB26 ((uint32_t)0x04000000) #define CAN_F20R1_FB27 ((uint32_t)0x08000000) #define CAN_F20R1_FB28 ((uint32_t)0x10000000) #define CAN_F20R1_FB29 ((uint32_t)0x20000000) #define CAN_F20R1_FB30 ((uint32_t)0x40000000) #define CAN_F20R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F21R1 register ********************/ #define CAN_F21R1_FB0 ((uint32_t)0x00000001) #define CAN_F21R1_FB1 ((uint32_t)0x00000002) #define CAN_F21R1_FB2 ((uint32_t)0x00000004) #define CAN_F21R1_FB3 ((uint32_t)0x00000008) #define CAN_F21R1_FB4 ((uint32_t)0x00000010) #define CAN_F21R1_FB5 ((uint32_t)0x00000020) #define CAN_F21R1_FB6 ((uint32_t)0x00000040) #define CAN_F21R1_FB7 ((uint32_t)0x00000080) #define CAN_F21R1_FB8 ((uint32_t)0x00000100) #define CAN_F21R1_FB9 ((uint32_t)0x00000200) #define CAN_F21R1_FB10 ((uint32_t)0x00000400) #define CAN_F21R1_FB11 ((uint32_t)0x00000800) #define CAN_F21R1_FB12 ((uint32_t)0x00001000) #define CAN_F21R1_FB13 ((uint32_t)0x00002000) #define CAN_F21R1_FB14 ((uint32_t)0x00004000) #define CAN_F21R1_FB15 ((uint32_t)0x00008000) #define CAN_F21R1_FB16 ((uint32_t)0x00010000) #define CAN_F21R1_FB17 ((uint32_t)0x00020000) #define CAN_F21R1_FB18 ((uint32_t)0x00040000) #define CAN_F21R1_FB19 ((uint32_t)0x00080000) #define CAN_F21R1_FB20 ((uint32_t)0x00100000) #define CAN_F21R1_FB21 ((uint32_t)0x00200000) #define CAN_F21R1_FB22 ((uint32_t)0x00400000) #define CAN_F21R1_FB23 ((uint32_t)0x00800000) #define CAN_F21R1_FB24 ((uint32_t)0x01000000) #define CAN_F21R1_FB25 ((uint32_t)0x02000000) #define CAN_F21R1_FB26 ((uint32_t)0x04000000) #define CAN_F21R1_FB27 ((uint32_t)0x08000000) #define CAN_F21R1_FB28 ((uint32_t)0x10000000) #define CAN_F21R1_FB29 ((uint32_t)0x20000000) #define CAN_F21R1_FB30 ((uint32_t)0x40000000) #define CAN_F21R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F22R1 register ********************/ #define CAN_F22R1_FB0 ((uint32_t)0x00000001) #define CAN_F22R1_FB1 ((uint32_t)0x00000002) #define CAN_F22R1_FB2 ((uint32_t)0x00000004) #define CAN_F22R1_FB3 ((uint32_t)0x00000008) #define CAN_F22R1_FB4 ((uint32_t)0x00000010) #define CAN_F22R1_FB5 ((uint32_t)0x00000020) #define CAN_F22R1_FB6 ((uint32_t)0x00000040) #define CAN_F22R1_FB7 ((uint32_t)0x00000080) #define CAN_F22R1_FB8 ((uint32_t)0x00000100) #define CAN_F22R1_FB9 ((uint32_t)0x00000200) #define CAN_F22R1_FB10 ((uint32_t)0x00000400) #define CAN_F22R1_FB11 ((uint32_t)0x00000800) #define CAN_F22R1_FB12 ((uint32_t)0x00001000) #define CAN_F22R1_FB13 ((uint32_t)0x00002000) #define CAN_F22R1_FB14 ((uint32_t)0x00004000) #define CAN_F22R1_FB15 ((uint32_t)0x00008000) #define CAN_F22R1_FB16 ((uint32_t)0x00010000) #define CAN_F22R1_FB17 ((uint32_t)0x00020000) #define CAN_F22R1_FB18 ((uint32_t)0x00040000) #define CAN_F22R1_FB19 ((uint32_t)0x00080000) #define CAN_F22R1_FB20 ((uint32_t)0x00100000) #define CAN_F22R1_FB21 ((uint32_t)0x00200000) #define CAN_F22R1_FB22 ((uint32_t)0x00400000) #define CAN_F22R1_FB23 ((uint32_t)0x00800000) #define CAN_F22R1_FB24 ((uint32_t)0x01000000) #define CAN_F22R1_FB25 ((uint32_t)0x02000000) #define CAN_F22R1_FB26 ((uint32_t)0x04000000) #define CAN_F22R1_FB27 ((uint32_t)0x08000000) #define CAN_F22R1_FB28 ((uint32_t)0x10000000) #define CAN_F22R1_FB29 ((uint32_t)0x20000000) #define CAN_F22R1_FB30 ((uint32_t)0x40000000) #define CAN_F22R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F23R1 register ********************/ #define CAN_F23R1_FB0 ((uint32_t)0x00000001) #define CAN_F23R1_FB1 ((uint32_t)0x00000002) #define CAN_F23R1_FB2 ((uint32_t)0x00000004) #define CAN_F23R1_FB3 ((uint32_t)0x00000008) #define CAN_F23R1_FB4 ((uint32_t)0x00000010) #define CAN_F23R1_FB5 ((uint32_t)0x00000020) #define CAN_F23R1_FB6 ((uint32_t)0x00000040) #define CAN_F23R1_FB7 ((uint32_t)0x00000080) #define CAN_F23R1_FB8 ((uint32_t)0x00000100) #define CAN_F23R1_FB9 ((uint32_t)0x00000200) #define CAN_F23R1_FB10 ((uint32_t)0x00000400) #define CAN_F23R1_FB11 ((uint32_t)0x00000800) #define CAN_F23R1_FB12 ((uint32_t)0x00001000) #define CAN_F23R1_FB13 ((uint32_t)0x00002000) #define CAN_F23R1_FB14 ((uint32_t)0x00004000) #define CAN_F23R1_FB15 ((uint32_t)0x00008000) #define CAN_F23R1_FB16 ((uint32_t)0x00010000) #define CAN_F23R1_FB17 ((uint32_t)0x00020000) #define CAN_F23R1_FB18 ((uint32_t)0x00040000) #define CAN_F23R1_FB19 ((uint32_t)0x00080000) #define CAN_F23R1_FB20 ((uint32_t)0x00100000) #define CAN_F23R1_FB21 ((uint32_t)0x00200000) #define CAN_F23R1_FB22 ((uint32_t)0x00400000) #define CAN_F23R1_FB23 ((uint32_t)0x00800000) #define CAN_F23R1_FB24 ((uint32_t)0x01000000) #define CAN_F23R1_FB25 ((uint32_t)0x02000000) #define CAN_F23R1_FB26 ((uint32_t)0x04000000) #define CAN_F23R1_FB27 ((uint32_t)0x08000000) #define CAN_F23R1_FB28 ((uint32_t)0x10000000) #define CAN_F23R1_FB29 ((uint32_t)0x20000000) #define CAN_F23R1_FB30 ((uint32_t)0x40000000) #define CAN_F23R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F24R1 register ********************/ #define CAN_F24R1_FB0 ((uint32_t)0x00000001) #define CAN_F24R1_FB1 ((uint32_t)0x00000002) #define CAN_F24R1_FB2 ((uint32_t)0x00000004) #define CAN_F24R1_FB3 ((uint32_t)0x00000008) #define CAN_F24R1_FB4 ((uint32_t)0x00000010) #define CAN_F24R1_FB5 ((uint32_t)0x00000020) #define CAN_F24R1_FB6 ((uint32_t)0x00000040) #define CAN_F24R1_FB7 ((uint32_t)0x00000080) #define CAN_F24R1_FB8 ((uint32_t)0x00000100) #define CAN_F24R1_FB9 ((uint32_t)0x00000200) #define CAN_F24R1_FB10 ((uint32_t)0x00000400) #define CAN_F24R1_FB11 ((uint32_t)0x00000800) #define CAN_F24R1_FB12 ((uint32_t)0x00001000) #define CAN_F24R1_FB13 ((uint32_t)0x00002000) #define CAN_F24R1_FB14 ((uint32_t)0x00004000) #define CAN_F24R1_FB15 ((uint32_t)0x00008000) #define CAN_F24R1_FB16 ((uint32_t)0x00010000) #define CAN_F24R1_FB17 ((uint32_t)0x00020000) #define CAN_F24R1_FB18 ((uint32_t)0x00040000) #define CAN_F24R1_FB19 ((uint32_t)0x00080000) #define CAN_F24R1_FB20 ((uint32_t)0x00100000) #define CAN_F24R1_FB21 ((uint32_t)0x00200000) #define CAN_F24R1_FB22 ((uint32_t)0x00400000) #define CAN_F24R1_FB23 ((uint32_t)0x00800000) #define CAN_F24R1_FB24 ((uint32_t)0x01000000) #define CAN_F24R1_FB25 ((uint32_t)0x02000000) #define CAN_F24R1_FB26 ((uint32_t)0x04000000) #define CAN_F24R1_FB27 ((uint32_t)0x08000000) #define CAN_F24R1_FB28 ((uint32_t)0x10000000) #define CAN_F24R1_FB29 ((uint32_t)0x20000000) #define CAN_F24R1_FB30 ((uint32_t)0x40000000) #define CAN_F24R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F25R1 register ********************/ #define CAN_F25R1_FB0 ((uint32_t)0x00000001) #define CAN_F25R1_FB1 ((uint32_t)0x00000002) #define CAN_F25R1_FB2 ((uint32_t)0x00000004) #define CAN_F25R1_FB3 ((uint32_t)0x00000008) #define CAN_F25R1_FB4 ((uint32_t)0x00000010) #define CAN_F25R1_FB5 ((uint32_t)0x00000020) #define CAN_F25R1_FB6 ((uint32_t)0x00000040) #define CAN_F25R1_FB7 ((uint32_t)0x00000080) #define CAN_F25R1_FB8 ((uint32_t)0x00000100) #define CAN_F25R1_FB9 ((uint32_t)0x00000200) #define CAN_F25R1_FB10 ((uint32_t)0x00000400) #define CAN_F25R1_FB11 ((uint32_t)0x00000800) #define CAN_F25R1_FB12 ((uint32_t)0x00001000) #define CAN_F25R1_FB13 ((uint32_t)0x00002000) #define CAN_F25R1_FB14 ((uint32_t)0x00004000) #define CAN_F25R1_FB15 ((uint32_t)0x00008000) #define CAN_F25R1_FB16 ((uint32_t)0x00010000) #define CAN_F25R1_FB17 ((uint32_t)0x00020000) #define CAN_F25R1_FB18 ((uint32_t)0x00040000) #define CAN_F25R1_FB19 ((uint32_t)0x00080000) #define CAN_F25R1_FB20 ((uint32_t)0x00100000) #define CAN_F25R1_FB21 ((uint32_t)0x00200000) #define CAN_F25R1_FB22 ((uint32_t)0x00400000) #define CAN_F25R1_FB23 ((uint32_t)0x00800000) #define CAN_F25R1_FB24 ((uint32_t)0x01000000) #define CAN_F25R1_FB25 ((uint32_t)0x02000000) #define CAN_F25R1_FB26 ((uint32_t)0x04000000) #define CAN_F25R1_FB27 ((uint32_t)0x08000000) #define CAN_F25R1_FB28 ((uint32_t)0x10000000) #define CAN_F25R1_FB29 ((uint32_t)0x20000000) #define CAN_F25R1_FB30 ((uint32_t)0x40000000) #define CAN_F25R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F26R1 register ********************/ #define CAN_F26R1_FB0 ((uint32_t)0x00000001) #define CAN_F26R1_FB1 ((uint32_t)0x00000002) #define CAN_F26R1_FB2 ((uint32_t)0x00000004) #define CAN_F26R1_FB3 ((uint32_t)0x00000008) #define CAN_F26R1_FB4 ((uint32_t)0x00000010) #define CAN_F26R1_FB5 ((uint32_t)0x00000020) #define CAN_F26R1_FB6 ((uint32_t)0x00000040) #define CAN_F26R1_FB7 ((uint32_t)0x00000080) #define CAN_F26R1_FB8 ((uint32_t)0x00000100) #define CAN_F26R1_FB9 ((uint32_t)0x00000200) #define CAN_F26R1_FB10 ((uint32_t)0x00000400) #define CAN_F26R1_FB11 ((uint32_t)0x00000800) #define CAN_F26R1_FB12 ((uint32_t)0x00001000) #define CAN_F26R1_FB13 ((uint32_t)0x00002000) #define CAN_F26R1_FB14 ((uint32_t)0x00004000) #define CAN_F26R1_FB15 ((uint32_t)0x00008000) #define CAN_F26R1_FB16 ((uint32_t)0x00010000) #define CAN_F26R1_FB17 ((uint32_t)0x00020000) #define CAN_F26R1_FB18 ((uint32_t)0x00040000) #define CAN_F26R1_FB19 ((uint32_t)0x00080000) #define CAN_F26R1_FB20 ((uint32_t)0x00100000) #define CAN_F26R1_FB21 ((uint32_t)0x00200000) #define CAN_F26R1_FB22 ((uint32_t)0x00400000) #define CAN_F26R1_FB23 ((uint32_t)0x00800000) #define CAN_F26R1_FB24 ((uint32_t)0x01000000) #define CAN_F26R1_FB25 ((uint32_t)0x02000000) #define CAN_F26R1_FB26 ((uint32_t)0x04000000) #define CAN_F26R1_FB27 ((uint32_t)0x08000000) #define CAN_F26R1_FB28 ((uint32_t)0x10000000) #define CAN_F26R1_FB29 ((uint32_t)0x20000000) #define CAN_F26R1_FB30 ((uint32_t)0x40000000) #define CAN_F26R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F27R1 register ********************/ #define CAN_F27R1_FB0 ((uint32_t)0x00000001) #define CAN_F27R1_FB1 ((uint32_t)0x00000002) #define CAN_F27R1_FB2 ((uint32_t)0x00000004) #define CAN_F27R1_FB3 ((uint32_t)0x00000008) #define CAN_F27R1_FB4 ((uint32_t)0x00000010) #define CAN_F27R1_FB5 ((uint32_t)0x00000020) #define CAN_F27R1_FB6 ((uint32_t)0x00000040) #define CAN_F27R1_FB7 ((uint32_t)0x00000080) #define CAN_F27R1_FB8 ((uint32_t)0x00000100) #define CAN_F27R1_FB9 ((uint32_t)0x00000200) #define CAN_F27R1_FB10 ((uint32_t)0x00000400) #define CAN_F27R1_FB11 ((uint32_t)0x00000800) #define CAN_F27R1_FB12 ((uint32_t)0x00001000) #define CAN_F27R1_FB13 ((uint32_t)0x00002000) #define CAN_F27R1_FB14 ((uint32_t)0x00004000) #define CAN_F27R1_FB15 ((uint32_t)0x00008000) #define CAN_F27R1_FB16 ((uint32_t)0x00010000) #define CAN_F27R1_FB17 ((uint32_t)0x00020000) #define CAN_F27R1_FB18 ((uint32_t)0x00040000) #define CAN_F27R1_FB19 ((uint32_t)0x00080000) #define CAN_F27R1_FB20 ((uint32_t)0x00100000) #define CAN_F27R1_FB21 ((uint32_t)0x00200000) #define CAN_F27R1_FB22 ((uint32_t)0x00400000) #define CAN_F27R1_FB23 ((uint32_t)0x00800000) #define CAN_F27R1_FB24 ((uint32_t)0x01000000) #define CAN_F27R1_FB25 ((uint32_t)0x02000000) #define CAN_F27R1_FB26 ((uint32_t)0x04000000) #define CAN_F27R1_FB27 ((uint32_t)0x08000000) #define CAN_F27R1_FB28 ((uint32_t)0x10000000) #define CAN_F27R1_FB29 ((uint32_t)0x20000000) #define CAN_F27R1_FB30 ((uint32_t)0x40000000) #define CAN_F27R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F28R1 register ********************/ #define CAN_F28R1_FB0 ((uint32_t)0x00000001) #define CAN_F28R1_FB1 ((uint32_t)0x00000002) #define CAN_F28R1_FB2 ((uint32_t)0x00000004) #define CAN_F28R1_FB3 ((uint32_t)0x00000008) #define CAN_F28R1_FB4 ((uint32_t)0x00000010) #define CAN_F28R1_FB5 ((uint32_t)0x00000020) #define CAN_F28R1_FB6 ((uint32_t)0x00000040) #define CAN_F28R1_FB7 ((uint32_t)0x00000080) #define CAN_F28R1_FB8 ((uint32_t)0x00000100) #define CAN_F28R1_FB9 ((uint32_t)0x00000200) #define CAN_F28R1_FB10 ((uint32_t)0x00000400) #define CAN_F28R1_FB11 ((uint32_t)0x00000800) #define CAN_F28R1_FB12 ((uint32_t)0x00001000) #define CAN_F28R1_FB13 ((uint32_t)0x00002000) #define CAN_F28R1_FB14 ((uint32_t)0x00004000) #define CAN_F28R1_FB15 ((uint32_t)0x00008000) #define CAN_F28R1_FB16 ((uint32_t)0x00010000) #define CAN_F28R1_FB17 ((uint32_t)0x00020000) #define CAN_F28R1_FB18 ((uint32_t)0x00040000) #define CAN_F28R1_FB19 ((uint32_t)0x00080000) #define CAN_F28R1_FB20 ((uint32_t)0x00100000) #define CAN_F28R1_FB21 ((uint32_t)0x00200000) #define CAN_F28R1_FB22 ((uint32_t)0x00400000) #define CAN_F28R1_FB23 ((uint32_t)0x00800000) #define CAN_F28R1_FB24 ((uint32_t)0x01000000) #define CAN_F28R1_FB25 ((uint32_t)0x02000000) #define CAN_F28R1_FB26 ((uint32_t)0x04000000) #define CAN_F28R1_FB27 ((uint32_t)0x08000000) #define CAN_F28R1_FB28 ((uint32_t)0x10000000) #define CAN_F28R1_FB29 ((uint32_t)0x20000000) #define CAN_F28R1_FB30 ((uint32_t)0x40000000) #define CAN_F28R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F29R1 register ********************/ #define CAN_F29R1_FB0 ((uint32_t)0x00000001) #define CAN_F29R1_FB1 ((uint32_t)0x00000002) #define CAN_F29R1_FB2 ((uint32_t)0x00000004) #define CAN_F29R1_FB3 ((uint32_t)0x00000008) #define CAN_F29R1_FB4 ((uint32_t)0x00000010) #define CAN_F29R1_FB5 ((uint32_t)0x00000020) #define CAN_F29R1_FB6 ((uint32_t)0x00000040) #define CAN_F29R1_FB7 ((uint32_t)0x00000080) #define CAN_F29R1_FB8 ((uint32_t)0x00000100) #define CAN_F29R1_FB9 ((uint32_t)0x00000200) #define CAN_F29R1_FB10 ((uint32_t)0x00000400) #define CAN_F29R1_FB11 ((uint32_t)0x00000800) #define CAN_F29R1_FB12 ((uint32_t)0x00001000) #define CAN_F29R1_FB13 ((uint32_t)0x00002000) #define CAN_F29R1_FB14 ((uint32_t)0x00004000) #define CAN_F29R1_FB15 ((uint32_t)0x00008000) #define CAN_F29R1_FB16 ((uint32_t)0x00010000) #define CAN_F29R1_FB17 ((uint32_t)0x00020000) #define CAN_F29R1_FB18 ((uint32_t)0x00040000) #define CAN_F29R1_FB19 ((uint32_t)0x00080000) #define CAN_F29R1_FB20 ((uint32_t)0x00100000) #define CAN_F29R1_FB21 ((uint32_t)0x00200000) #define CAN_F29R1_FB22 ((uint32_t)0x00400000) #define CAN_F29R1_FB23 ((uint32_t)0x00800000) #define CAN_F29R1_FB24 ((uint32_t)0x01000000) #define CAN_F29R1_FB25 ((uint32_t)0x02000000) #define CAN_F29R1_FB26 ((uint32_t)0x04000000) #define CAN_F29R1_FB27 ((uint32_t)0x08000000) #define CAN_F29R1_FB28 ((uint32_t)0x10000000) #define CAN_F29R1_FB29 ((uint32_t)0x20000000) #define CAN_F29R1_FB30 ((uint32_t)0x40000000) #define CAN_F29R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F30R1 register ********************/ #define CAN_F30R1_FB0 ((uint32_t)0x00000001) #define CAN_F30R1_FB1 ((uint32_t)0x00000002) #define CAN_F30R1_FB2 ((uint32_t)0x00000004) #define CAN_F30R1_FB3 ((uint32_t)0x00000008) #define CAN_F30R1_FB4 ((uint32_t)0x00000010) #define CAN_F30R1_FB5 ((uint32_t)0x00000020) #define CAN_F30R1_FB6 ((uint32_t)0x00000040) #define CAN_F30R1_FB7 ((uint32_t)0x00000080) #define CAN_F30R1_FB8 ((uint32_t)0x00000100) #define CAN_F30R1_FB9 ((uint32_t)0x00000200) #define CAN_F30R1_FB10 ((uint32_t)0x00000400) #define CAN_F30R1_FB11 ((uint32_t)0x00000800) #define CAN_F30R1_FB12 ((uint32_t)0x00001000) #define CAN_F30R1_FB13 ((uint32_t)0x00002000) #define CAN_F30R1_FB14 ((uint32_t)0x00004000) #define CAN_F30R1_FB15 ((uint32_t)0x00008000) #define CAN_F30R1_FB16 ((uint32_t)0x00010000) #define CAN_F30R1_FB17 ((uint32_t)0x00020000) #define CAN_F30R1_FB18 ((uint32_t)0x00040000) #define CAN_F30R1_FB19 ((uint32_t)0x00080000) #define CAN_F30R1_FB20 ((uint32_t)0x00100000) #define CAN_F30R1_FB21 ((uint32_t)0x00200000) #define CAN_F30R1_FB22 ((uint32_t)0x00400000) #define CAN_F30R1_FB23 ((uint32_t)0x00800000) #define CAN_F30R1_FB24 ((uint32_t)0x01000000) #define CAN_F30R1_FB25 ((uint32_t)0x02000000) #define CAN_F30R1_FB26 ((uint32_t)0x04000000) #define CAN_F30R1_FB27 ((uint32_t)0x08000000) #define CAN_F30R1_FB28 ((uint32_t)0x10000000) #define CAN_F30R1_FB29 ((uint32_t)0x20000000) #define CAN_F30R1_FB30 ((uint32_t)0x40000000) #define CAN_F30R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F31R1 register ********************/ #define CAN_F31R1_FB0 ((uint32_t)0x00000001) #define CAN_F31R1_FB1 ((uint32_t)0x00000002) #define CAN_F31R1_FB2 ((uint32_t)0x00000004) #define CAN_F31R1_FB3 ((uint32_t)0x00000008) #define CAN_F31R1_FB4 ((uint32_t)0x00000010) #define CAN_F31R1_FB5 ((uint32_t)0x00000020) #define CAN_F31R1_FB6 ((uint32_t)0x00000040) #define CAN_F31R1_FB7 ((uint32_t)0x00000080) #define CAN_F31R1_FB8 ((uint32_t)0x00000100) #define CAN_F31R1_FB9 ((uint32_t)0x00000200) #define CAN_F31R1_FB10 ((uint32_t)0x00000400) #define CAN_F31R1_FB11 ((uint32_t)0x00000800) #define CAN_F31R1_FB12 ((uint32_t)0x00001000) #define CAN_F31R1_FB13 ((uint32_t)0x00002000) #define CAN_F31R1_FB14 ((uint32_t)0x00004000) #define CAN_F31R1_FB15 ((uint32_t)0x00008000) #define CAN_F31R1_FB16 ((uint32_t)0x00010000) #define CAN_F31R1_FB17 ((uint32_t)0x00020000) #define CAN_F31R1_FB18 ((uint32_t)0x00040000) #define CAN_F31R1_FB19 ((uint32_t)0x00080000) #define CAN_F31R1_FB20 ((uint32_t)0x00100000) #define CAN_F31R1_FB21 ((uint32_t)0x00200000) #define CAN_F31R1_FB22 ((uint32_t)0x00400000) #define CAN_F31R1_FB23 ((uint32_t)0x00800000) #define CAN_F31R1_FB24 ((uint32_t)0x01000000) #define CAN_F31R1_FB25 ((uint32_t)0x02000000) #define CAN_F31R1_FB26 ((uint32_t)0x04000000) #define CAN_F31R1_FB27 ((uint32_t)0x08000000) #define CAN_F31R1_FB28 ((uint32_t)0x10000000) #define CAN_F31R1_FB29 ((uint32_t)0x20000000) #define CAN_F31R1_FB30 ((uint32_t)0x40000000) #define CAN_F31R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F32R1 register ********************/ #define CAN_F32R1_FB0 ((uint32_t)0x00000001) #define CAN_F32R1_FB1 ((uint32_t)0x00000002) #define CAN_F32R1_FB2 ((uint32_t)0x00000004) #define CAN_F32R1_FB3 ((uint32_t)0x00000008) #define CAN_F32R1_FB4 ((uint32_t)0x00000010) #define CAN_F32R1_FB5 ((uint32_t)0x00000020) #define CAN_F32R1_FB6 ((uint32_t)0x00000040) #define CAN_F32R1_FB7 ((uint32_t)0x00000080) #define CAN_F32R1_FB8 ((uint32_t)0x00000100) #define CAN_F32R1_FB9 ((uint32_t)0x00000200) #define CAN_F32R1_FB10 ((uint32_t)0x00000400) #define CAN_F32R1_FB11 ((uint32_t)0x00000800) #define CAN_F32R1_FB12 ((uint32_t)0x00001000) #define CAN_F32R1_FB13 ((uint32_t)0x00002000) #define CAN_F32R1_FB14 ((uint32_t)0x00004000) #define CAN_F32R1_FB15 ((uint32_t)0x00008000) #define CAN_F32R1_FB16 ((uint32_t)0x00010000) #define CAN_F32R1_FB17 ((uint32_t)0x00020000) #define CAN_F32R1_FB18 ((uint32_t)0x00040000) #define CAN_F32R1_FB19 ((uint32_t)0x00080000) #define CAN_F32R1_FB20 ((uint32_t)0x00100000) #define CAN_F32R1_FB21 ((uint32_t)0x00200000) #define CAN_F32R1_FB22 ((uint32_t)0x00400000) #define CAN_F32R1_FB23 ((uint32_t)0x00800000) #define CAN_F32R1_FB24 ((uint32_t)0x01000000) #define CAN_F32R1_FB25 ((uint32_t)0x02000000) #define CAN_F32R1_FB26 ((uint32_t)0x04000000) #define CAN_F32R1_FB27 ((uint32_t)0x08000000) #define CAN_F32R1_FB28 ((uint32_t)0x10000000) #define CAN_F32R1_FB29 ((uint32_t)0x20000000) #define CAN_F32R1_FB30 ((uint32_t)0x40000000) #define CAN_F32R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F33R1 register ********************/ #define CAN_F33R1_FB0 ((uint32_t)0x00000001) #define CAN_F33R1_FB1 ((uint32_t)0x00000002) #define CAN_F33R1_FB2 ((uint32_t)0x00000004) #define CAN_F33R1_FB3 ((uint32_t)0x00000008) #define CAN_F33R1_FB4 ((uint32_t)0x00000010) #define CAN_F33R1_FB5 ((uint32_t)0x00000020) #define CAN_F33R1_FB6 ((uint32_t)0x00000040) #define CAN_F33R1_FB7 ((uint32_t)0x00000080) #define CAN_F33R1_FB8 ((uint32_t)0x00000100) #define CAN_F33R1_FB9 ((uint32_t)0x00000200) #define CAN_F33R1_FB10 ((uint32_t)0x00000400) #define CAN_F33R1_FB11 ((uint32_t)0x00000800) #define CAN_F33R1_FB12 ((uint32_t)0x00001000) #define CAN_F33R1_FB13 ((uint32_t)0x00002000) #define CAN_F33R1_FB14 ((uint32_t)0x00004000) #define CAN_F33R1_FB15 ((uint32_t)0x00008000) #define CAN_F33R1_FB16 ((uint32_t)0x00010000) #define CAN_F33R1_FB17 ((uint32_t)0x00020000) #define CAN_F33R1_FB18 ((uint32_t)0x00040000) #define CAN_F33R1_FB19 ((uint32_t)0x00080000) #define CAN_F33R1_FB20 ((uint32_t)0x00100000) #define CAN_F33R1_FB21 ((uint32_t)0x00200000) #define CAN_F33R1_FB22 ((uint32_t)0x00400000) #define CAN_F33R1_FB23 ((uint32_t)0x00800000) #define CAN_F33R1_FB24 ((uint32_t)0x01000000) #define CAN_F33R1_FB25 ((uint32_t)0x02000000) #define CAN_F33R1_FB26 ((uint32_t)0x04000000) #define CAN_F33R1_FB27 ((uint32_t)0x08000000) #define CAN_F33R1_FB28 ((uint32_t)0x10000000) #define CAN_F33R1_FB29 ((uint32_t)0x20000000) #define CAN_F33R1_FB30 ((uint32_t)0x40000000) #define CAN_F33R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F34R1 register ********************/ #define CAN_F34R1_FB0 ((uint32_t)0x00000001) #define CAN_F34R1_FB1 ((uint32_t)0x00000002) #define CAN_F34R1_FB2 ((uint32_t)0x00000004) #define CAN_F34R1_FB3 ((uint32_t)0x00000008) #define CAN_F34R1_FB4 ((uint32_t)0x00000010) #define CAN_F34R1_FB5 ((uint32_t)0x00000020) #define CAN_F34R1_FB6 ((uint32_t)0x00000040) #define CAN_F34R1_FB7 ((uint32_t)0x00000080) #define CAN_F34R1_FB8 ((uint32_t)0x00000100) #define CAN_F34R1_FB9 ((uint32_t)0x00000200) #define CAN_F34R1_FB10 ((uint32_t)0x00000400) #define CAN_F34R1_FB11 ((uint32_t)0x00000800) #define CAN_F34R1_FB12 ((uint32_t)0x00001000) #define CAN_F34R1_FB13 ((uint32_t)0x00002000) #define CAN_F34R1_FB14 ((uint32_t)0x00004000) #define CAN_F34R1_FB15 ((uint32_t)0x00008000) #define CAN_F34R1_FB16 ((uint32_t)0x00010000) #define CAN_F34R1_FB17 ((uint32_t)0x00020000) #define CAN_F34R1_FB18 ((uint32_t)0x00040000) #define CAN_F34R1_FB19 ((uint32_t)0x00080000) #define CAN_F34R1_FB20 ((uint32_t)0x00100000) #define CAN_F34R1_FB21 ((uint32_t)0x00200000) #define CAN_F34R1_FB22 ((uint32_t)0x00400000) #define CAN_F34R1_FB23 ((uint32_t)0x00800000) #define CAN_F34R1_FB24 ((uint32_t)0x01000000) #define CAN_F34R1_FB25 ((uint32_t)0x02000000) #define CAN_F34R1_FB26 ((uint32_t)0x04000000) #define CAN_F34R1_FB27 ((uint32_t)0x08000000) #define CAN_F34R1_FB28 ((uint32_t)0x10000000) #define CAN_F34R1_FB29 ((uint32_t)0x20000000) #define CAN_F34R1_FB30 ((uint32_t)0x40000000) #define CAN_F34R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F35R1 register ********************/ #define CAN_F35R1_FB0 ((uint32_t)0x00000001) #define CAN_F35R1_FB1 ((uint32_t)0x00000002) #define CAN_F35R1_FB2 ((uint32_t)0x00000004) #define CAN_F35R1_FB3 ((uint32_t)0x00000008) #define CAN_F35R1_FB4 ((uint32_t)0x00000010) #define CAN_F35R1_FB5 ((uint32_t)0x00000020) #define CAN_F35R1_FB6 ((uint32_t)0x00000040) #define CAN_F35R1_FB7 ((uint32_t)0x00000080) #define CAN_F35R1_FB8 ((uint32_t)0x00000100) #define CAN_F35R1_FB9 ((uint32_t)0x00000200) #define CAN_F35R1_FB10 ((uint32_t)0x00000400) #define CAN_F35R1_FB11 ((uint32_t)0x00000800) #define CAN_F35R1_FB12 ((uint32_t)0x00001000) #define CAN_F35R1_FB13 ((uint32_t)0x00002000) #define CAN_F35R1_FB14 ((uint32_t)0x00004000) #define CAN_F35R1_FB15 ((uint32_t)0x00008000) #define CAN_F35R1_FB16 ((uint32_t)0x00010000) #define CAN_F35R1_FB17 ((uint32_t)0x00020000) #define CAN_F35R1_FB18 ((uint32_t)0x00040000) #define CAN_F35R1_FB19 ((uint32_t)0x00080000) #define CAN_F35R1_FB20 ((uint32_t)0x00100000) #define CAN_F35R1_FB21 ((uint32_t)0x00200000) #define CAN_F35R1_FB22 ((uint32_t)0x00400000) #define CAN_F35R1_FB23 ((uint32_t)0x00800000) #define CAN_F35R1_FB24 ((uint32_t)0x01000000) #define CAN_F35R1_FB25 ((uint32_t)0x02000000) #define CAN_F35R1_FB26 ((uint32_t)0x04000000) #define CAN_F35R1_FB27 ((uint32_t)0x08000000) #define CAN_F35R1_FB28 ((uint32_t)0x10000000) #define CAN_F35R1_FB29 ((uint32_t)0x20000000) #define CAN_F35R1_FB30 ((uint32_t)0x40000000) #define CAN_F35R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F36R1 register ********************/ #define CAN_F36R1_FB0 ((uint32_t)0x00000001) #define CAN_F36R1_FB1 ((uint32_t)0x00000002) #define CAN_F36R1_FB2 ((uint32_t)0x00000004) #define CAN_F36R1_FB3 ((uint32_t)0x00000008) #define CAN_F36R1_FB4 ((uint32_t)0x00000010) #define CAN_F36R1_FB5 ((uint32_t)0x00000020) #define CAN_F36R1_FB6 ((uint32_t)0x00000040) #define CAN_F36R1_FB7 ((uint32_t)0x00000080) #define CAN_F36R1_FB8 ((uint32_t)0x00000100) #define CAN_F36R1_FB9 ((uint32_t)0x00000200) #define CAN_F36R1_FB10 ((uint32_t)0x00000400) #define CAN_F36R1_FB11 ((uint32_t)0x00000800) #define CAN_F36R1_FB12 ((uint32_t)0x00001000) #define CAN_F36R1_FB13 ((uint32_t)0x00002000) #define CAN_F36R1_FB14 ((uint32_t)0x00004000) #define CAN_F36R1_FB15 ((uint32_t)0x00008000) #define CAN_F36R1_FB16 ((uint32_t)0x00010000) #define CAN_F36R1_FB17 ((uint32_t)0x00020000) #define CAN_F36R1_FB18 ((uint32_t)0x00040000) #define CAN_F36R1_FB19 ((uint32_t)0x00080000) #define CAN_F36R1_FB20 ((uint32_t)0x00100000) #define CAN_F36R1_FB21 ((uint32_t)0x00200000) #define CAN_F36R1_FB22 ((uint32_t)0x00400000) #define CAN_F36R1_FB23 ((uint32_t)0x00800000) #define CAN_F36R1_FB24 ((uint32_t)0x01000000) #define CAN_F36R1_FB25 ((uint32_t)0x02000000) #define CAN_F36R1_FB26 ((uint32_t)0x04000000) #define CAN_F36R1_FB27 ((uint32_t)0x08000000) #define CAN_F36R1_FB28 ((uint32_t)0x10000000) #define CAN_F36R1_FB29 ((uint32_t)0x20000000) #define CAN_F36R1_FB30 ((uint32_t)0x40000000) #define CAN_F36R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F37R1 register ********************/ #define CAN_F37R1_FB0 ((uint32_t)0x00000001) #define CAN_F37R1_FB1 ((uint32_t)0x00000002) #define CAN_F37R1_FB2 ((uint32_t)0x00000004) #define CAN_F37R1_FB3 ((uint32_t)0x00000008) #define CAN_F37R1_FB4 ((uint32_t)0x00000010) #define CAN_F37R1_FB5 ((uint32_t)0x00000020) #define CAN_F37R1_FB6 ((uint32_t)0x00000040) #define CAN_F37R1_FB7 ((uint32_t)0x00000080) #define CAN_F37R1_FB8 ((uint32_t)0x00000100) #define CAN_F37R1_FB9 ((uint32_t)0x00000200) #define CAN_F37R1_FB10 ((uint32_t)0x00000400) #define CAN_F37R1_FB11 ((uint32_t)0x00000800) #define CAN_F37R1_FB12 ((uint32_t)0x00001000) #define CAN_F37R1_FB13 ((uint32_t)0x00002000) #define CAN_F37R1_FB14 ((uint32_t)0x00004000) #define CAN_F37R1_FB15 ((uint32_t)0x00008000) #define CAN_F37R1_FB16 ((uint32_t)0x00010000) #define CAN_F37R1_FB17 ((uint32_t)0x00020000) #define CAN_F37R1_FB18 ((uint32_t)0x00040000) #define CAN_F37R1_FB19 ((uint32_t)0x00080000) #define CAN_F37R1_FB20 ((uint32_t)0x00100000) #define CAN_F37R1_FB21 ((uint32_t)0x00200000) #define CAN_F37R1_FB22 ((uint32_t)0x00400000) #define CAN_F37R1_FB23 ((uint32_t)0x00800000) #define CAN_F37R1_FB24 ((uint32_t)0x01000000) #define CAN_F37R1_FB25 ((uint32_t)0x02000000) #define CAN_F37R1_FB26 ((uint32_t)0x04000000) #define CAN_F37R1_FB27 ((uint32_t)0x08000000) #define CAN_F37R1_FB28 ((uint32_t)0x10000000) #define CAN_F37R1_FB29 ((uint32_t)0x20000000) #define CAN_F37R1_FB30 ((uint32_t)0x40000000) #define CAN_F37R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F38R1 register ********************/ #define CAN_F38R1_FB0 ((uint32_t)0x00000001) #define CAN_F38R1_FB1 ((uint32_t)0x00000002) #define CAN_F38R1_FB2 ((uint32_t)0x00000004) #define CAN_F38R1_FB3 ((uint32_t)0x00000008) #define CAN_F38R1_FB4 ((uint32_t)0x00000010) #define CAN_F38R1_FB5 ((uint32_t)0x00000020) #define CAN_F38R1_FB6 ((uint32_t)0x00000040) #define CAN_F38R1_FB7 ((uint32_t)0x00000080) #define CAN_F38R1_FB8 ((uint32_t)0x00000100) #define CAN_F38R1_FB9 ((uint32_t)0x00000200) #define CAN_F38R1_FB10 ((uint32_t)0x00000400) #define CAN_F38R1_FB11 ((uint32_t)0x00000800) #define CAN_F38R1_FB12 ((uint32_t)0x00001000) #define CAN_F38R1_FB13 ((uint32_t)0x00002000) #define CAN_F38R1_FB14 ((uint32_t)0x00004000) #define CAN_F38R1_FB15 ((uint32_t)0x00008000) #define CAN_F38R1_FB16 ((uint32_t)0x00010000) #define CAN_F38R1_FB17 ((uint32_t)0x00020000) #define CAN_F38R1_FB18 ((uint32_t)0x00040000) #define CAN_F38R1_FB19 ((uint32_t)0x00080000) #define CAN_F38R1_FB20 ((uint32_t)0x00100000) #define CAN_F38R1_FB21 ((uint32_t)0x00200000) #define CAN_F38R1_FB22 ((uint32_t)0x00400000) #define CAN_F38R1_FB23 ((uint32_t)0x00800000) #define CAN_F38R1_FB24 ((uint32_t)0x01000000) #define CAN_F38R1_FB25 ((uint32_t)0x02000000) #define CAN_F38R1_FB26 ((uint32_t)0x04000000) #define CAN_F38R1_FB27 ((uint32_t)0x08000000) #define CAN_F38R1_FB28 ((uint32_t)0x10000000) #define CAN_F38R1_FB29 ((uint32_t)0x20000000) #define CAN_F38R1_FB30 ((uint32_t)0x40000000) #define CAN_F38R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F39R1 register ********************/ #define CAN_F39R1_FB0 ((uint32_t)0x00000001) #define CAN_F39R1_FB1 ((uint32_t)0x00000002) #define CAN_F39R1_FB2 ((uint32_t)0x00000004) #define CAN_F39R1_FB3 ((uint32_t)0x00000008) #define CAN_F39R1_FB4 ((uint32_t)0x00000010) #define CAN_F39R1_FB5 ((uint32_t)0x00000020) #define CAN_F39R1_FB6 ((uint32_t)0x00000040) #define CAN_F39R1_FB7 ((uint32_t)0x00000080) #define CAN_F39R1_FB8 ((uint32_t)0x00000100) #define CAN_F39R1_FB9 ((uint32_t)0x00000200) #define CAN_F39R1_FB10 ((uint32_t)0x00000400) #define CAN_F39R1_FB11 ((uint32_t)0x00000800) #define CAN_F39R1_FB12 ((uint32_t)0x00001000) #define CAN_F39R1_FB13 ((uint32_t)0x00002000) #define CAN_F39R1_FB14 ((uint32_t)0x00004000) #define CAN_F39R1_FB15 ((uint32_t)0x00008000) #define CAN_F39R1_FB16 ((uint32_t)0x00010000) #define CAN_F39R1_FB17 ((uint32_t)0x00020000) #define CAN_F39R1_FB18 ((uint32_t)0x00040000) #define CAN_F39R1_FB19 ((uint32_t)0x00080000) #define CAN_F39R1_FB20 ((uint32_t)0x00100000) #define CAN_F39R1_FB21 ((uint32_t)0x00200000) #define CAN_F39R1_FB22 ((uint32_t)0x00400000) #define CAN_F39R1_FB23 ((uint32_t)0x00800000) #define CAN_F39R1_FB24 ((uint32_t)0x01000000) #define CAN_F39R1_FB25 ((uint32_t)0x02000000) #define CAN_F39R1_FB26 ((uint32_t)0x04000000) #define CAN_F39R1_FB27 ((uint32_t)0x08000000) #define CAN_F39R1_FB28 ((uint32_t)0x10000000) #define CAN_F39R1_FB29 ((uint32_t)0x20000000) #define CAN_F39R1_FB30 ((uint32_t)0x40000000) #define CAN_F39R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F40R1 register ********************/ #define CAN_F40R1_FB0 ((uint32_t)0x00000001) #define CAN_F40R1_FB1 ((uint32_t)0x00000002) #define CAN_F40R1_FB2 ((uint32_t)0x00000004) #define CAN_F40R1_FB3 ((uint32_t)0x00000008) #define CAN_F40R1_FB4 ((uint32_t)0x00000010) #define CAN_F40R1_FB5 ((uint32_t)0x00000020) #define CAN_F40R1_FB6 ((uint32_t)0x00000040) #define CAN_F40R1_FB7 ((uint32_t)0x00000080) #define CAN_F40R1_FB8 ((uint32_t)0x00000100) #define CAN_F40R1_FB9 ((uint32_t)0x00000200) #define CAN_F40R1_FB10 ((uint32_t)0x00000400) #define CAN_F40R1_FB11 ((uint32_t)0x00000800) #define CAN_F40R1_FB12 ((uint32_t)0x00001000) #define CAN_F40R1_FB13 ((uint32_t)0x00002000) #define CAN_F40R1_FB14 ((uint32_t)0x00004000) #define CAN_F40R1_FB15 ((uint32_t)0x00008000) #define CAN_F40R1_FB16 ((uint32_t)0x00010000) #define CAN_F40R1_FB17 ((uint32_t)0x00020000) #define CAN_F40R1_FB18 ((uint32_t)0x00040000) #define CAN_F40R1_FB19 ((uint32_t)0x00080000) #define CAN_F40R1_FB20 ((uint32_t)0x00100000) #define CAN_F40R1_FB21 ((uint32_t)0x00200000) #define CAN_F40R1_FB22 ((uint32_t)0x00400000) #define CAN_F40R1_FB23 ((uint32_t)0x00800000) #define CAN_F40R1_FB24 ((uint32_t)0x01000000) #define CAN_F40R1_FB25 ((uint32_t)0x02000000) #define CAN_F40R1_FB26 ((uint32_t)0x04000000) #define CAN_F40R1_FB27 ((uint32_t)0x08000000) #define CAN_F40R1_FB28 ((uint32_t)0x10000000) #define CAN_F40R1_FB29 ((uint32_t)0x20000000) #define CAN_F40R1_FB30 ((uint32_t)0x40000000) #define CAN_F40R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F41R1 register ********************/ #define CAN_F41R1_FB0 ((uint32_t)0x00000001) #define CAN_F41R1_FB1 ((uint32_t)0x00000002) #define CAN_F41R1_FB2 ((uint32_t)0x00000004) #define CAN_F41R1_FB3 ((uint32_t)0x00000008) #define CAN_F41R1_FB4 ((uint32_t)0x00000010) #define CAN_F41R1_FB5 ((uint32_t)0x00000020) #define CAN_F41R1_FB6 ((uint32_t)0x00000040) #define CAN_F41R1_FB7 ((uint32_t)0x00000080) #define CAN_F41R1_FB8 ((uint32_t)0x00000100) #define CAN_F41R1_FB9 ((uint32_t)0x00000200) #define CAN_F41R1_FB10 ((uint32_t)0x00000400) #define CAN_F41R1_FB11 ((uint32_t)0x00000800) #define CAN_F41R1_FB12 ((uint32_t)0x00001000) #define CAN_F41R1_FB13 ((uint32_t)0x00002000) #define CAN_F41R1_FB14 ((uint32_t)0x00004000) #define CAN_F41R1_FB15 ((uint32_t)0x00008000) #define CAN_F41R1_FB16 ((uint32_t)0x00010000) #define CAN_F41R1_FB17 ((uint32_t)0x00020000) #define CAN_F41R1_FB18 ((uint32_t)0x00040000) #define CAN_F41R1_FB19 ((uint32_t)0x00080000) #define CAN_F41R1_FB20 ((uint32_t)0x00100000) #define CAN_F41R1_FB21 ((uint32_t)0x00200000) #define CAN_F41R1_FB22 ((uint32_t)0x00400000) #define CAN_F41R1_FB23 ((uint32_t)0x00800000) #define CAN_F41R1_FB24 ((uint32_t)0x01000000) #define CAN_F41R1_FB25 ((uint32_t)0x02000000) #define CAN_F41R1_FB26 ((uint32_t)0x04000000) #define CAN_F41R1_FB27 ((uint32_t)0x08000000) #define CAN_F41R1_FB28 ((uint32_t)0x10000000) #define CAN_F41R1_FB29 ((uint32_t)0x20000000) #define CAN_F41R1_FB30 ((uint32_t)0x40000000) #define CAN_F41R1_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F0R2 register ********************/ #define CAN_F0R2_FB0 ((uint32_t)0x00000001) #define CAN_F0R2_FB1 ((uint32_t)0x00000002) #define CAN_F0R2_FB2 ((uint32_t)0x00000004) #define CAN_F0R2_FB3 ((uint32_t)0x00000008) #define CAN_F0R2_FB4 ((uint32_t)0x00000010) #define CAN_F0R2_FB5 ((uint32_t)0x00000020) #define CAN_F0R2_FB6 ((uint32_t)0x00000040) #define CAN_F0R2_FB7 ((uint32_t)0x00000080) #define CAN_F0R2_FB8 ((uint32_t)0x00000100) #define CAN_F0R2_FB9 ((uint32_t)0x00000200) #define CAN_F0R2_FB10 ((uint32_t)0x00000400) #define CAN_F0R2_FB11 ((uint32_t)0x00000800) #define CAN_F0R2_FB12 ((uint32_t)0x00001000) #define CAN_F0R2_FB13 ((uint32_t)0x00002000) #define CAN_F0R2_FB14 ((uint32_t)0x00004000) #define CAN_F0R2_FB15 ((uint32_t)0x00008000) #define CAN_F0R2_FB16 ((uint32_t)0x00010000) #define CAN_F0R2_FB17 ((uint32_t)0x00020000) #define CAN_F0R2_FB18 ((uint32_t)0x00040000) #define CAN_F0R2_FB19 ((uint32_t)0x00080000) #define CAN_F0R2_FB20 ((uint32_t)0x00100000) #define CAN_F0R2_FB21 ((uint32_t)0x00200000) #define CAN_F0R2_FB22 ((uint32_t)0x00400000) #define CAN_F0R2_FB23 ((uint32_t)0x00800000) #define CAN_F0R2_FB24 ((uint32_t)0x01000000) #define CAN_F0R2_FB25 ((uint32_t)0x02000000) #define CAN_F0R2_FB26 ((uint32_t)0x04000000) #define CAN_F0R2_FB27 ((uint32_t)0x08000000) #define CAN_F0R2_FB28 ((uint32_t)0x10000000) #define CAN_F0R2_FB29 ((uint32_t)0x20000000) #define CAN_F0R2_FB30 ((uint32_t)0x40000000) #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F1R2 register ********************/ #define CAN_F1R2_FB0 ((uint32_t)0x00000001) #define CAN_F1R2_FB1 ((uint32_t)0x00000002) #define CAN_F1R2_FB2 ((uint32_t)0x00000004) #define CAN_F1R2_FB3 ((uint32_t)0x00000008) #define CAN_F1R2_FB4 ((uint32_t)0x00000010) #define CAN_F1R2_FB5 ((uint32_t)0x00000020) #define CAN_F1R2_FB6 ((uint32_t)0x00000040) #define CAN_F1R2_FB7 ((uint32_t)0x00000080) #define CAN_F1R2_FB8 ((uint32_t)0x00000100) #define CAN_F1R2_FB9 ((uint32_t)0x00000200) #define CAN_F1R2_FB10 ((uint32_t)0x00000400) #define CAN_F1R2_FB11 ((uint32_t)0x00000800) #define CAN_F1R2_FB12 ((uint32_t)0x00001000) #define CAN_F1R2_FB13 ((uint32_t)0x00002000) #define CAN_F1R2_FB14 ((uint32_t)0x00004000) #define CAN_F1R2_FB15 ((uint32_t)0x00008000) #define CAN_F1R2_FB16 ((uint32_t)0x00010000) #define CAN_F1R2_FB17 ((uint32_t)0x00020000) #define CAN_F1R2_FB18 ((uint32_t)0x00040000) #define CAN_F1R2_FB19 ((uint32_t)0x00080000) #define CAN_F1R2_FB20 ((uint32_t)0x00100000) #define CAN_F1R2_FB21 ((uint32_t)0x00200000) #define CAN_F1R2_FB22 ((uint32_t)0x00400000) #define CAN_F1R2_FB23 ((uint32_t)0x00800000) #define CAN_F1R2_FB24 ((uint32_t)0x01000000) #define CAN_F1R2_FB25 ((uint32_t)0x02000000) #define CAN_F1R2_FB26 ((uint32_t)0x04000000) #define CAN_F1R2_FB27 ((uint32_t)0x08000000) #define CAN_F1R2_FB28 ((uint32_t)0x10000000) #define CAN_F1R2_FB29 ((uint32_t)0x20000000) #define CAN_F1R2_FB30 ((uint32_t)0x40000000) #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F2R2 register ********************/ #define CAN_F2R2_FB0 ((uint32_t)0x00000001) #define CAN_F2R2_FB1 ((uint32_t)0x00000002) #define CAN_F2R2_FB2 ((uint32_t)0x00000004) #define CAN_F2R2_FB3 ((uint32_t)0x00000008) #define CAN_F2R2_FB4 ((uint32_t)0x00000010) #define CAN_F2R2_FB5 ((uint32_t)0x00000020) #define CAN_F2R2_FB6 ((uint32_t)0x00000040) #define CAN_F2R2_FB7 ((uint32_t)0x00000080) #define CAN_F2R2_FB8 ((uint32_t)0x00000100) #define CAN_F2R2_FB9 ((uint32_t)0x00000200) #define CAN_F2R2_FB10 ((uint32_t)0x00000400) #define CAN_F2R2_FB11 ((uint32_t)0x00000800) #define CAN_F2R2_FB12 ((uint32_t)0x00001000) #define CAN_F2R2_FB13 ((uint32_t)0x00002000) #define CAN_F2R2_FB14 ((uint32_t)0x00004000) #define CAN_F2R2_FB15 ((uint32_t)0x00008000) #define CAN_F2R2_FB16 ((uint32_t)0x00010000) #define CAN_F2R2_FB17 ((uint32_t)0x00020000) #define CAN_F2R2_FB18 ((uint32_t)0x00040000) #define CAN_F2R2_FB19 ((uint32_t)0x00080000) #define CAN_F2R2_FB20 ((uint32_t)0x00100000) #define CAN_F2R2_FB21 ((uint32_t)0x00200000) #define CAN_F2R2_FB22 ((uint32_t)0x00400000) #define CAN_F2R2_FB23 ((uint32_t)0x00800000) #define CAN_F2R2_FB24 ((uint32_t)0x01000000) #define CAN_F2R2_FB25 ((uint32_t)0x02000000) #define CAN_F2R2_FB26 ((uint32_t)0x04000000) #define CAN_F2R2_FB27 ((uint32_t)0x08000000) #define CAN_F2R2_FB28 ((uint32_t)0x10000000) #define CAN_F2R2_FB29 ((uint32_t)0x20000000) #define CAN_F2R2_FB30 ((uint32_t)0x40000000) #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F3R2 register ********************/ #define CAN_F3R2_FB0 ((uint32_t)0x00000001) #define CAN_F3R2_FB1 ((uint32_t)0x00000002) #define CAN_F3R2_FB2 ((uint32_t)0x00000004) #define CAN_F3R2_FB3 ((uint32_t)0x00000008) #define CAN_F3R2_FB4 ((uint32_t)0x00000010) #define CAN_F3R2_FB5 ((uint32_t)0x00000020) #define CAN_F3R2_FB6 ((uint32_t)0x00000040) #define CAN_F3R2_FB7 ((uint32_t)0x00000080) #define CAN_F3R2_FB8 ((uint32_t)0x00000100) #define CAN_F3R2_FB9 ((uint32_t)0x00000200) #define CAN_F3R2_FB10 ((uint32_t)0x00000400) #define CAN_F3R2_FB11 ((uint32_t)0x00000800) #define CAN_F3R2_FB12 ((uint32_t)0x00001000) #define CAN_F3R2_FB13 ((uint32_t)0x00002000) #define CAN_F3R2_FB14 ((uint32_t)0x00004000) #define CAN_F3R2_FB15 ((uint32_t)0x00008000) #define CAN_F3R2_FB16 ((uint32_t)0x00010000) #define CAN_F3R2_FB17 ((uint32_t)0x00020000) #define CAN_F3R2_FB18 ((uint32_t)0x00040000) #define CAN_F3R2_FB19 ((uint32_t)0x00080000) #define CAN_F3R2_FB20 ((uint32_t)0x00100000) #define CAN_F3R2_FB21 ((uint32_t)0x00200000) #define CAN_F3R2_FB22 ((uint32_t)0x00400000) #define CAN_F3R2_FB23 ((uint32_t)0x00800000) #define CAN_F3R2_FB24 ((uint32_t)0x01000000) #define CAN_F3R2_FB25 ((uint32_t)0x02000000) #define CAN_F3R2_FB26 ((uint32_t)0x04000000) #define CAN_F3R2_FB27 ((uint32_t)0x08000000) #define CAN_F3R2_FB28 ((uint32_t)0x10000000) #define CAN_F3R2_FB29 ((uint32_t)0x20000000) #define CAN_F3R2_FB30 ((uint32_t)0x40000000) #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F4R2 register ********************/ #define CAN_F4R2_FB0 ((uint32_t)0x00000001) #define CAN_F4R2_FB1 ((uint32_t)0x00000002) #define CAN_F4R2_FB2 ((uint32_t)0x00000004) #define CAN_F4R2_FB3 ((uint32_t)0x00000008) #define CAN_F4R2_FB4 ((uint32_t)0x00000010) #define CAN_F4R2_FB5 ((uint32_t)0x00000020) #define CAN_F4R2_FB6 ((uint32_t)0x00000040) #define CAN_F4R2_FB7 ((uint32_t)0x00000080) #define CAN_F4R2_FB8 ((uint32_t)0x00000100) #define CAN_F4R2_FB9 ((uint32_t)0x00000200) #define CAN_F4R2_FB10 ((uint32_t)0x00000400) #define CAN_F4R2_FB11 ((uint32_t)0x00000800) #define CAN_F4R2_FB12 ((uint32_t)0x00001000) #define CAN_F4R2_FB13 ((uint32_t)0x00002000) #define CAN_F4R2_FB14 ((uint32_t)0x00004000) #define CAN_F4R2_FB15 ((uint32_t)0x00008000) #define CAN_F4R2_FB16 ((uint32_t)0x00010000) #define CAN_F4R2_FB17 ((uint32_t)0x00020000) #define CAN_F4R2_FB18 ((uint32_t)0x00040000) #define CAN_F4R2_FB19 ((uint32_t)0x00080000) #define CAN_F4R2_FB20 ((uint32_t)0x00100000) #define CAN_F4R2_FB21 ((uint32_t)0x00200000) #define CAN_F4R2_FB22 ((uint32_t)0x00400000) #define CAN_F4R2_FB23 ((uint32_t)0x00800000) #define CAN_F4R2_FB24 ((uint32_t)0x01000000) #define CAN_F4R2_FB25 ((uint32_t)0x02000000) #define CAN_F4R2_FB26 ((uint32_t)0x04000000) #define CAN_F4R2_FB27 ((uint32_t)0x08000000) #define CAN_F4R2_FB28 ((uint32_t)0x10000000) #define CAN_F4R2_FB29 ((uint32_t)0x20000000) #define CAN_F4R2_FB30 ((uint32_t)0x40000000) #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F5R2 register ********************/ #define CAN_F5R2_FB0 ((uint32_t)0x00000001) #define CAN_F5R2_FB1 ((uint32_t)0x00000002) #define CAN_F5R2_FB2 ((uint32_t)0x00000004) #define CAN_F5R2_FB3 ((uint32_t)0x00000008) #define CAN_F5R2_FB4 ((uint32_t)0x00000010) #define CAN_F5R2_FB5 ((uint32_t)0x00000020) #define CAN_F5R2_FB6 ((uint32_t)0x00000040) #define CAN_F5R2_FB7 ((uint32_t)0x00000080) #define CAN_F5R2_FB8 ((uint32_t)0x00000100) #define CAN_F5R2_FB9 ((uint32_t)0x00000200) #define CAN_F5R2_FB10 ((uint32_t)0x00000400) #define CAN_F5R2_FB11 ((uint32_t)0x00000800) #define CAN_F5R2_FB12 ((uint32_t)0x00001000) #define CAN_F5R2_FB13 ((uint32_t)0x00002000) #define CAN_F5R2_FB14 ((uint32_t)0x00004000) #define CAN_F5R2_FB15 ((uint32_t)0x00008000) #define CAN_F5R2_FB16 ((uint32_t)0x00010000) #define CAN_F5R2_FB17 ((uint32_t)0x00020000) #define CAN_F5R2_FB18 ((uint32_t)0x00040000) #define CAN_F5R2_FB19 ((uint32_t)0x00080000) #define CAN_F5R2_FB20 ((uint32_t)0x00100000) #define CAN_F5R2_FB21 ((uint32_t)0x00200000) #define CAN_F5R2_FB22 ((uint32_t)0x00400000) #define CAN_F5R2_FB23 ((uint32_t)0x00800000) #define CAN_F5R2_FB24 ((uint32_t)0x01000000) #define CAN_F5R2_FB25 ((uint32_t)0x02000000) #define CAN_F5R2_FB26 ((uint32_t)0x04000000) #define CAN_F5R2_FB27 ((uint32_t)0x08000000) #define CAN_F5R2_FB28 ((uint32_t)0x10000000) #define CAN_F5R2_FB29 ((uint32_t)0x20000000) #define CAN_F5R2_FB30 ((uint32_t)0x40000000) #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F6R2 register ********************/ #define CAN_F6R2_FB0 ((uint32_t)0x00000001) #define CAN_F6R2_FB1 ((uint32_t)0x00000002) #define CAN_F6R2_FB2 ((uint32_t)0x00000004) #define CAN_F6R2_FB3 ((uint32_t)0x00000008) #define CAN_F6R2_FB4 ((uint32_t)0x00000010) #define CAN_F6R2_FB5 ((uint32_t)0x00000020) #define CAN_F6R2_FB6 ((uint32_t)0x00000040) #define CAN_F6R2_FB7 ((uint32_t)0x00000080) #define CAN_F6R2_FB8 ((uint32_t)0x00000100) #define CAN_F6R2_FB9 ((uint32_t)0x00000200) #define CAN_F6R2_FB10 ((uint32_t)0x00000400) #define CAN_F6R2_FB11 ((uint32_t)0x00000800) #define CAN_F6R2_FB12 ((uint32_t)0x00001000) #define CAN_F6R2_FB13 ((uint32_t)0x00002000) #define CAN_F6R2_FB14 ((uint32_t)0x00004000) #define CAN_F6R2_FB15 ((uint32_t)0x00008000) #define CAN_F6R2_FB16 ((uint32_t)0x00010000) #define CAN_F6R2_FB17 ((uint32_t)0x00020000) #define CAN_F6R2_FB18 ((uint32_t)0x00040000) #define CAN_F6R2_FB19 ((uint32_t)0x00080000) #define CAN_F6R2_FB20 ((uint32_t)0x00100000) #define CAN_F6R2_FB21 ((uint32_t)0x00200000) #define CAN_F6R2_FB22 ((uint32_t)0x00400000) #define CAN_F6R2_FB23 ((uint32_t)0x00800000) #define CAN_F6R2_FB24 ((uint32_t)0x01000000) #define CAN_F6R2_FB25 ((uint32_t)0x02000000) #define CAN_F6R2_FB26 ((uint32_t)0x04000000) #define CAN_F6R2_FB27 ((uint32_t)0x08000000) #define CAN_F6R2_FB28 ((uint32_t)0x10000000) #define CAN_F6R2_FB29 ((uint32_t)0x20000000) #define CAN_F6R2_FB30 ((uint32_t)0x40000000) #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F7R2 register ********************/ #define CAN_F7R2_FB0 ((uint32_t)0x00000001) #define CAN_F7R2_FB1 ((uint32_t)0x00000002) #define CAN_F7R2_FB2 ((uint32_t)0x00000004) #define CAN_F7R2_FB3 ((uint32_t)0x00000008) #define CAN_F7R2_FB4 ((uint32_t)0x00000010) #define CAN_F7R2_FB5 ((uint32_t)0x00000020) #define CAN_F7R2_FB6 ((uint32_t)0x00000040) #define CAN_F7R2_FB7 ((uint32_t)0x00000080) #define CAN_F7R2_FB8 ((uint32_t)0x00000100) #define CAN_F7R2_FB9 ((uint32_t)0x00000200) #define CAN_F7R2_FB10 ((uint32_t)0x00000400) #define CAN_F7R2_FB11 ((uint32_t)0x00000800) #define CAN_F7R2_FB12 ((uint32_t)0x00001000) #define CAN_F7R2_FB13 ((uint32_t)0x00002000) #define CAN_F7R2_FB14 ((uint32_t)0x00004000) #define CAN_F7R2_FB15 ((uint32_t)0x00008000) #define CAN_F7R2_FB16 ((uint32_t)0x00010000) #define CAN_F7R2_FB17 ((uint32_t)0x00020000) #define CAN_F7R2_FB18 ((uint32_t)0x00040000) #define CAN_F7R2_FB19 ((uint32_t)0x00080000) #define CAN_F7R2_FB20 ((uint32_t)0x00100000) #define CAN_F7R2_FB21 ((uint32_t)0x00200000) #define CAN_F7R2_FB22 ((uint32_t)0x00400000) #define CAN_F7R2_FB23 ((uint32_t)0x00800000) #define CAN_F7R2_FB24 ((uint32_t)0x01000000) #define CAN_F7R2_FB25 ((uint32_t)0x02000000) #define CAN_F7R2_FB26 ((uint32_t)0x04000000) #define CAN_F7R2_FB27 ((uint32_t)0x08000000) #define CAN_F7R2_FB28 ((uint32_t)0x10000000) #define CAN_F7R2_FB29 ((uint32_t)0x20000000) #define CAN_F7R2_FB30 ((uint32_t)0x40000000) #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F8R2 register ********************/ #define CAN_F8R2_FB0 ((uint32_t)0x00000001) #define CAN_F8R2_FB1 ((uint32_t)0x00000002) #define CAN_F8R2_FB2 ((uint32_t)0x00000004) #define CAN_F8R2_FB3 ((uint32_t)0x00000008) #define CAN_F8R2_FB4 ((uint32_t)0x00000010) #define CAN_F8R2_FB5 ((uint32_t)0x00000020) #define CAN_F8R2_FB6 ((uint32_t)0x00000040) #define CAN_F8R2_FB7 ((uint32_t)0x00000080) #define CAN_F8R2_FB8 ((uint32_t)0x00000100) #define CAN_F8R2_FB9 ((uint32_t)0x00000200) #define CAN_F8R2_FB10 ((uint32_t)0x00000400) #define CAN_F8R2_FB11 ((uint32_t)0x00000800) #define CAN_F8R2_FB12 ((uint32_t)0x00001000) #define CAN_F8R2_FB13 ((uint32_t)0x00002000) #define CAN_F8R2_FB14 ((uint32_t)0x00004000) #define CAN_F8R2_FB15 ((uint32_t)0x00008000) #define CAN_F8R2_FB16 ((uint32_t)0x00010000) #define CAN_F8R2_FB17 ((uint32_t)0x00020000) #define CAN_F8R2_FB18 ((uint32_t)0x00040000) #define CAN_F8R2_FB19 ((uint32_t)0x00080000) #define CAN_F8R2_FB20 ((uint32_t)0x00100000) #define CAN_F8R2_FB21 ((uint32_t)0x00200000) #define CAN_F8R2_FB22 ((uint32_t)0x00400000) #define CAN_F8R2_FB23 ((uint32_t)0x00800000) #define CAN_F8R2_FB24 ((uint32_t)0x01000000) #define CAN_F8R2_FB25 ((uint32_t)0x02000000) #define CAN_F8R2_FB26 ((uint32_t)0x04000000) #define CAN_F8R2_FB27 ((uint32_t)0x08000000) #define CAN_F8R2_FB28 ((uint32_t)0x10000000) #define CAN_F8R2_FB29 ((uint32_t)0x20000000) #define CAN_F8R2_FB30 ((uint32_t)0x40000000) #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F9R2 register ********************/ #define CAN_F9R2_FB0 ((uint32_t)0x00000001) #define CAN_F9R2_FB1 ((uint32_t)0x00000002) #define CAN_F9R2_FB2 ((uint32_t)0x00000004) #define CAN_F9R2_FB3 ((uint32_t)0x00000008) #define CAN_F9R2_FB4 ((uint32_t)0x00000010) #define CAN_F9R2_FB5 ((uint32_t)0x00000020) #define CAN_F9R2_FB6 ((uint32_t)0x00000040) #define CAN_F9R2_FB7 ((uint32_t)0x00000080) #define CAN_F9R2_FB8 ((uint32_t)0x00000100) #define CAN_F9R2_FB9 ((uint32_t)0x00000200) #define CAN_F9R2_FB10 ((uint32_t)0x00000400) #define CAN_F9R2_FB11 ((uint32_t)0x00000800) #define CAN_F9R2_FB12 ((uint32_t)0x00001000) #define CAN_F9R2_FB13 ((uint32_t)0x00002000) #define CAN_F9R2_FB14 ((uint32_t)0x00004000) #define CAN_F9R2_FB15 ((uint32_t)0x00008000) #define CAN_F9R2_FB16 ((uint32_t)0x00010000) #define CAN_F9R2_FB17 ((uint32_t)0x00020000) #define CAN_F9R2_FB18 ((uint32_t)0x00040000) #define CAN_F9R2_FB19 ((uint32_t)0x00080000) #define CAN_F9R2_FB20 ((uint32_t)0x00100000) #define CAN_F9R2_FB21 ((uint32_t)0x00200000) #define CAN_F9R2_FB22 ((uint32_t)0x00400000) #define CAN_F9R2_FB23 ((uint32_t)0x00800000) #define CAN_F9R2_FB24 ((uint32_t)0x01000000) #define CAN_F9R2_FB25 ((uint32_t)0x02000000) #define CAN_F9R2_FB26 ((uint32_t)0x04000000) #define CAN_F9R2_FB27 ((uint32_t)0x08000000) #define CAN_F9R2_FB28 ((uint32_t)0x10000000) #define CAN_F9R2_FB29 ((uint32_t)0x20000000) #define CAN_F9R2_FB30 ((uint32_t)0x40000000) #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F10R2 register ********************/ #define CAN_F10R2_FB0 ((uint32_t)0x00000001) #define CAN_F10R2_FB1 ((uint32_t)0x00000002) #define CAN_F10R2_FB2 ((uint32_t)0x00000004) #define CAN_F10R2_FB3 ((uint32_t)0x00000008) #define CAN_F10R2_FB4 ((uint32_t)0x00000010) #define CAN_F10R2_FB5 ((uint32_t)0x00000020) #define CAN_F10R2_FB6 ((uint32_t)0x00000040) #define CAN_F10R2_FB7 ((uint32_t)0x00000080) #define CAN_F10R2_FB8 ((uint32_t)0x00000100) #define CAN_F10R2_FB9 ((uint32_t)0x00000200) #define CAN_F10R2_FB10 ((uint32_t)0x00000400) #define CAN_F10R2_FB11 ((uint32_t)0x00000800) #define CAN_F10R2_FB12 ((uint32_t)0x00001000) #define CAN_F10R2_FB13 ((uint32_t)0x00002000) #define CAN_F10R2_FB14 ((uint32_t)0x00004000) #define CAN_F10R2_FB15 ((uint32_t)0x00008000) #define CAN_F10R2_FB16 ((uint32_t)0x00010000) #define CAN_F10R2_FB17 ((uint32_t)0x00020000) #define CAN_F10R2_FB18 ((uint32_t)0x00040000) #define CAN_F10R2_FB19 ((uint32_t)0x00080000) #define CAN_F10R2_FB20 ((uint32_t)0x00100000) #define CAN_F10R2_FB21 ((uint32_t)0x00200000) #define CAN_F10R2_FB22 ((uint32_t)0x00400000) #define CAN_F10R2_FB23 ((uint32_t)0x00800000) #define CAN_F10R2_FB24 ((uint32_t)0x01000000) #define CAN_F10R2_FB25 ((uint32_t)0x02000000) #define CAN_F10R2_FB26 ((uint32_t)0x04000000) #define CAN_F10R2_FB27 ((uint32_t)0x08000000) #define CAN_F10R2_FB28 ((uint32_t)0x10000000) #define CAN_F10R2_FB29 ((uint32_t)0x20000000) #define CAN_F10R2_FB30 ((uint32_t)0x40000000) #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F11R2 register ********************/ #define CAN_F11R2_FB0 ((uint32_t)0x00000001) #define CAN_F11R2_FB1 ((uint32_t)0x00000002) #define CAN_F11R2_FB2 ((uint32_t)0x00000004) #define CAN_F11R2_FB3 ((uint32_t)0x00000008) #define CAN_F11R2_FB4 ((uint32_t)0x00000010) #define CAN_F11R2_FB5 ((uint32_t)0x00000020) #define CAN_F11R2_FB6 ((uint32_t)0x00000040) #define CAN_F11R2_FB7 ((uint32_t)0x00000080) #define CAN_F11R2_FB8 ((uint32_t)0x00000100) #define CAN_F11R2_FB9 ((uint32_t)0x00000200) #define CAN_F11R2_FB10 ((uint32_t)0x00000400) #define CAN_F11R2_FB11 ((uint32_t)0x00000800) #define CAN_F11R2_FB12 ((uint32_t)0x00001000) #define CAN_F11R2_FB13 ((uint32_t)0x00002000) #define CAN_F11R2_FB14 ((uint32_t)0x00004000) #define CAN_F11R2_FB15 ((uint32_t)0x00008000) #define CAN_F11R2_FB16 ((uint32_t)0x00010000) #define CAN_F11R2_FB17 ((uint32_t)0x00020000) #define CAN_F11R2_FB18 ((uint32_t)0x00040000) #define CAN_F11R2_FB19 ((uint32_t)0x00080000) #define CAN_F11R2_FB20 ((uint32_t)0x00100000) #define CAN_F11R2_FB21 ((uint32_t)0x00200000) #define CAN_F11R2_FB22 ((uint32_t)0x00400000) #define CAN_F11R2_FB23 ((uint32_t)0x00800000) #define CAN_F11R2_FB24 ((uint32_t)0x01000000) #define CAN_F11R2_FB25 ((uint32_t)0x02000000) #define CAN_F11R2_FB26 ((uint32_t)0x04000000) #define CAN_F11R2_FB27 ((uint32_t)0x08000000) #define CAN_F11R2_FB28 ((uint32_t)0x10000000) #define CAN_F11R2_FB29 ((uint32_t)0x20000000) #define CAN_F11R2_FB30 ((uint32_t)0x40000000) #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F12R2 register ********************/ #define CAN_F12R2_FB0 ((uint32_t)0x00000001) #define CAN_F12R2_FB1 ((uint32_t)0x00000002) #define CAN_F12R2_FB2 ((uint32_t)0x00000004) #define CAN_F12R2_FB3 ((uint32_t)0x00000008) #define CAN_F12R2_FB4 ((uint32_t)0x00000010) #define CAN_F12R2_FB5 ((uint32_t)0x00000020) #define CAN_F12R2_FB6 ((uint32_t)0x00000040) #define CAN_F12R2_FB7 ((uint32_t)0x00000080) #define CAN_F12R2_FB8 ((uint32_t)0x00000100) #define CAN_F12R2_FB9 ((uint32_t)0x00000200) #define CAN_F12R2_FB10 ((uint32_t)0x00000400) #define CAN_F12R2_FB11 ((uint32_t)0x00000800) #define CAN_F12R2_FB12 ((uint32_t)0x00001000) #define CAN_F12R2_FB13 ((uint32_t)0x00002000) #define CAN_F12R2_FB14 ((uint32_t)0x00004000) #define CAN_F12R2_FB15 ((uint32_t)0x00008000) #define CAN_F12R2_FB16 ((uint32_t)0x00010000) #define CAN_F12R2_FB17 ((uint32_t)0x00020000) #define CAN_F12R2_FB18 ((uint32_t)0x00040000) #define CAN_F12R2_FB19 ((uint32_t)0x00080000) #define CAN_F12R2_FB20 ((uint32_t)0x00100000) #define CAN_F12R2_FB21 ((uint32_t)0x00200000) #define CAN_F12R2_FB22 ((uint32_t)0x00400000) #define CAN_F12R2_FB23 ((uint32_t)0x00800000) #define CAN_F12R2_FB24 ((uint32_t)0x01000000) #define CAN_F12R2_FB25 ((uint32_t)0x02000000) #define CAN_F12R2_FB26 ((uint32_t)0x04000000) #define CAN_F12R2_FB27 ((uint32_t)0x08000000) #define CAN_F12R2_FB28 ((uint32_t)0x10000000) #define CAN_F12R2_FB29 ((uint32_t)0x20000000) #define CAN_F12R2_FB30 ((uint32_t)0x40000000) #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F13R2 register ********************/ #define CAN_F13R2_FB0 ((uint32_t)0x00000001) #define CAN_F13R2_FB1 ((uint32_t)0x00000002) #define CAN_F13R2_FB2 ((uint32_t)0x00000004) #define CAN_F13R2_FB3 ((uint32_t)0x00000008) #define CAN_F13R2_FB4 ((uint32_t)0x00000010) #define CAN_F13R2_FB5 ((uint32_t)0x00000020) #define CAN_F13R2_FB6 ((uint32_t)0x00000040) #define CAN_F13R2_FB7 ((uint32_t)0x00000080) #define CAN_F13R2_FB8 ((uint32_t)0x00000100) #define CAN_F13R2_FB9 ((uint32_t)0x00000200) #define CAN_F13R2_FB10 ((uint32_t)0x00000400) #define CAN_F13R2_FB11 ((uint32_t)0x00000800) #define CAN_F13R2_FB12 ((uint32_t)0x00001000) #define CAN_F13R2_FB13 ((uint32_t)0x00002000) #define CAN_F13R2_FB14 ((uint32_t)0x00004000) #define CAN_F13R2_FB15 ((uint32_t)0x00008000) #define CAN_F13R2_FB16 ((uint32_t)0x00010000) #define CAN_F13R2_FB17 ((uint32_t)0x00020000) #define CAN_F13R2_FB18 ((uint32_t)0x00040000) #define CAN_F13R2_FB19 ((uint32_t)0x00080000) #define CAN_F13R2_FB20 ((uint32_t)0x00100000) #define CAN_F13R2_FB21 ((uint32_t)0x00200000) #define CAN_F13R2_FB22 ((uint32_t)0x00400000) #define CAN_F13R2_FB23 ((uint32_t)0x00800000) #define CAN_F13R2_FB24 ((uint32_t)0x01000000) #define CAN_F13R2_FB25 ((uint32_t)0x02000000) #define CAN_F13R2_FB26 ((uint32_t)0x04000000) #define CAN_F13R2_FB27 ((uint32_t)0x08000000) #define CAN_F13R2_FB28 ((uint32_t)0x10000000) #define CAN_F13R2_FB29 ((uint32_t)0x20000000) #define CAN_F13R2_FB30 ((uint32_t)0x40000000) #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F14R2 register ********************/ #define CAN_F14R2_FB0 ((uint32_t)0x00000001) #define CAN_F14R2_FB1 ((uint32_t)0x00000002) #define CAN_F14R2_FB2 ((uint32_t)0x00000004) #define CAN_F14R2_FB3 ((uint32_t)0x00000008) #define CAN_F14R2_FB4 ((uint32_t)0x00000010) #define CAN_F14R2_FB5 ((uint32_t)0x00000020) #define CAN_F14R2_FB6 ((uint32_t)0x00000040) #define CAN_F14R2_FB7 ((uint32_t)0x00000080) #define CAN_F14R2_FB8 ((uint32_t)0x00000100) #define CAN_F14R2_FB9 ((uint32_t)0x00000200) #define CAN_F14R2_FB10 ((uint32_t)0x00000400) #define CAN_F14R2_FB11 ((uint32_t)0x00000800) #define CAN_F14R2_FB12 ((uint32_t)0x00001000) #define CAN_F14R2_FB13 ((uint32_t)0x00002000) #define CAN_F14R2_FB14 ((uint32_t)0x00004000) #define CAN_F14R2_FB15 ((uint32_t)0x00008000) #define CAN_F14R2_FB16 ((uint32_t)0x00010000) #define CAN_F14R2_FB17 ((uint32_t)0x00020000) #define CAN_F14R2_FB18 ((uint32_t)0x00040000) #define CAN_F14R2_FB19 ((uint32_t)0x00080000) #define CAN_F14R2_FB20 ((uint32_t)0x00100000) #define CAN_F14R2_FB21 ((uint32_t)0x00200000) #define CAN_F14R2_FB22 ((uint32_t)0x00400000) #define CAN_F14R2_FB23 ((uint32_t)0x00800000) #define CAN_F14R2_FB24 ((uint32_t)0x01000000) #define CAN_F14R2_FB25 ((uint32_t)0x02000000) #define CAN_F14R2_FB26 ((uint32_t)0x04000000) #define CAN_F14R2_FB27 ((uint32_t)0x08000000) #define CAN_F14R2_FB28 ((uint32_t)0x10000000) #define CAN_F14R2_FB29 ((uint32_t)0x20000000) #define CAN_F14R2_FB30 ((uint32_t)0x40000000) #define CAN_F14R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F15R2 register ********************/ #define CAN_F15R2_FB0 ((uint32_t)0x00000001) #define CAN_F15R2_FB1 ((uint32_t)0x00000002) #define CAN_F15R2_FB2 ((uint32_t)0x00000004) #define CAN_F15R2_FB3 ((uint32_t)0x00000008) #define CAN_F15R2_FB4 ((uint32_t)0x00000010) #define CAN_F15R2_FB5 ((uint32_t)0x00000020) #define CAN_F15R2_FB6 ((uint32_t)0x00000040) #define CAN_F15R2_FB7 ((uint32_t)0x00000080) #define CAN_F15R2_FB8 ((uint32_t)0x00000100) #define CAN_F15R2_FB9 ((uint32_t)0x00000200) #define CAN_F15R2_FB10 ((uint32_t)0x00000400) #define CAN_F15R2_FB11 ((uint32_t)0x00000800) #define CAN_F15R2_FB12 ((uint32_t)0x00001000) #define CAN_F15R2_FB13 ((uint32_t)0x00002000) #define CAN_F15R2_FB14 ((uint32_t)0x00004000) #define CAN_F15R2_FB15 ((uint32_t)0x00008000) #define CAN_F15R2_FB16 ((uint32_t)0x00010000) #define CAN_F15R2_FB17 ((uint32_t)0x00020000) #define CAN_F15R2_FB18 ((uint32_t)0x00040000) #define CAN_F15R2_FB19 ((uint32_t)0x00080000) #define CAN_F15R2_FB20 ((uint32_t)0x00100000) #define CAN_F15R2_FB21 ((uint32_t)0x00200000) #define CAN_F15R2_FB22 ((uint32_t)0x00400000) #define CAN_F15R2_FB23 ((uint32_t)0x00800000) #define CAN_F15R2_FB24 ((uint32_t)0x01000000) #define CAN_F15R2_FB25 ((uint32_t)0x02000000) #define CAN_F15R2_FB26 ((uint32_t)0x04000000) #define CAN_F15R2_FB27 ((uint32_t)0x08000000) #define CAN_F15R2_FB28 ((uint32_t)0x10000000) #define CAN_F15R2_FB29 ((uint32_t)0x20000000) #define CAN_F15R2_FB30 ((uint32_t)0x40000000) #define CAN_F15R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F16R2 register ********************/ #define CAN_F16R2_FB0 ((uint32_t)0x00000001) #define CAN_F16R2_FB1 ((uint32_t)0x00000002) #define CAN_F16R2_FB2 ((uint32_t)0x00000004) #define CAN_F16R2_FB3 ((uint32_t)0x00000008) #define CAN_F16R2_FB4 ((uint32_t)0x00000010) #define CAN_F16R2_FB5 ((uint32_t)0x00000020) #define CAN_F16R2_FB6 ((uint32_t)0x00000040) #define CAN_F16R2_FB7 ((uint32_t)0x00000080) #define CAN_F16R2_FB8 ((uint32_t)0x00000100) #define CAN_F16R2_FB9 ((uint32_t)0x00000200) #define CAN_F16R2_FB10 ((uint32_t)0x00000400) #define CAN_F16R2_FB11 ((uint32_t)0x00000800) #define CAN_F16R2_FB12 ((uint32_t)0x00001000) #define CAN_F16R2_FB13 ((uint32_t)0x00002000) #define CAN_F16R2_FB14 ((uint32_t)0x00004000) #define CAN_F16R2_FB15 ((uint32_t)0x00008000) #define CAN_F16R2_FB16 ((uint32_t)0x00010000) #define CAN_F16R2_FB17 ((uint32_t)0x00020000) #define CAN_F16R2_FB18 ((uint32_t)0x00040000) #define CAN_F16R2_FB19 ((uint32_t)0x00080000) #define CAN_F16R2_FB20 ((uint32_t)0x00100000) #define CAN_F16R2_FB21 ((uint32_t)0x00200000) #define CAN_F16R2_FB22 ((uint32_t)0x00400000) #define CAN_F16R2_FB23 ((uint32_t)0x00800000) #define CAN_F16R2_FB24 ((uint32_t)0x01000000) #define CAN_F16R2_FB25 ((uint32_t)0x02000000) #define CAN_F16R2_FB26 ((uint32_t)0x04000000) #define CAN_F16R2_FB27 ((uint32_t)0x08000000) #define CAN_F16R2_FB28 ((uint32_t)0x10000000) #define CAN_F16R2_FB29 ((uint32_t)0x20000000) #define CAN_F16R2_FB30 ((uint32_t)0x40000000) #define CAN_F16R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F17R2 register ********************/ #define CAN_F17R2_FB0 ((uint32_t)0x00000001) #define CAN_F17R2_FB1 ((uint32_t)0x00000002) #define CAN_F17R2_FB2 ((uint32_t)0x00000004) #define CAN_F17R2_FB3 ((uint32_t)0x00000008) #define CAN_F17R2_FB4 ((uint32_t)0x00000010) #define CAN_F17R2_FB5 ((uint32_t)0x00000020) #define CAN_F17R2_FB6 ((uint32_t)0x00000040) #define CAN_F17R2_FB7 ((uint32_t)0x00000080) #define CAN_F17R2_FB8 ((uint32_t)0x00000100) #define CAN_F17R2_FB9 ((uint32_t)0x00000200) #define CAN_F17R2_FB10 ((uint32_t)0x00000400) #define CAN_F17R2_FB11 ((uint32_t)0x00000800) #define CAN_F17R2_FB12 ((uint32_t)0x00001000) #define CAN_F17R2_FB13 ((uint32_t)0x00002000) #define CAN_F17R2_FB14 ((uint32_t)0x00004000) #define CAN_F17R2_FB15 ((uint32_t)0x00008000) #define CAN_F17R2_FB16 ((uint32_t)0x00010000) #define CAN_F17R2_FB17 ((uint32_t)0x00020000) #define CAN_F17R2_FB18 ((uint32_t)0x00040000) #define CAN_F17R2_FB19 ((uint32_t)0x00080000) #define CAN_F17R2_FB20 ((uint32_t)0x00100000) #define CAN_F17R2_FB21 ((uint32_t)0x00200000) #define CAN_F17R2_FB22 ((uint32_t)0x00400000) #define CAN_F17R2_FB23 ((uint32_t)0x00800000) #define CAN_F17R2_FB24 ((uint32_t)0x01000000) #define CAN_F17R2_FB25 ((uint32_t)0x02000000) #define CAN_F17R2_FB26 ((uint32_t)0x04000000) #define CAN_F17R2_FB27 ((uint32_t)0x08000000) #define CAN_F17R2_FB28 ((uint32_t)0x10000000) #define CAN_F17R2_FB29 ((uint32_t)0x20000000) #define CAN_F17R2_FB30 ((uint32_t)0x40000000) #define CAN_F17R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F18R2 register ********************/ #define CAN_F18R2_FB0 ((uint32_t)0x00000001) #define CAN_F18R2_FB1 ((uint32_t)0x00000002) #define CAN_F18R2_FB2 ((uint32_t)0x00000004) #define CAN_F18R2_FB3 ((uint32_t)0x00000008) #define CAN_F18R2_FB4 ((uint32_t)0x00000010) #define CAN_F18R2_FB5 ((uint32_t)0x00000020) #define CAN_F18R2_FB6 ((uint32_t)0x00000040) #define CAN_F18R2_FB7 ((uint32_t)0x00000080) #define CAN_F18R2_FB8 ((uint32_t)0x00000100) #define CAN_F18R2_FB9 ((uint32_t)0x00000200) #define CAN_F18R2_FB10 ((uint32_t)0x00000400) #define CAN_F18R2_FB11 ((uint32_t)0x00000800) #define CAN_F18R2_FB12 ((uint32_t)0x00001000) #define CAN_F18R2_FB13 ((uint32_t)0x00002000) #define CAN_F18R2_FB14 ((uint32_t)0x00004000) #define CAN_F18R2_FB15 ((uint32_t)0x00008000) #define CAN_F18R2_FB16 ((uint32_t)0x00010000) #define CAN_F18R2_FB17 ((uint32_t)0x00020000) #define CAN_F18R2_FB18 ((uint32_t)0x00040000) #define CAN_F18R2_FB19 ((uint32_t)0x00080000) #define CAN_F18R2_FB20 ((uint32_t)0x00100000) #define CAN_F18R2_FB21 ((uint32_t)0x00200000) #define CAN_F18R2_FB22 ((uint32_t)0x00400000) #define CAN_F18R2_FB23 ((uint32_t)0x00800000) #define CAN_F18R2_FB24 ((uint32_t)0x01000000) #define CAN_F18R2_FB25 ((uint32_t)0x02000000) #define CAN_F18R2_FB26 ((uint32_t)0x04000000) #define CAN_F18R2_FB27 ((uint32_t)0x08000000) #define CAN_F18R2_FB28 ((uint32_t)0x10000000) #define CAN_F18R2_FB29 ((uint32_t)0x20000000) #define CAN_F18R2_FB30 ((uint32_t)0x40000000) #define CAN_F18R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F19R2 register ********************/ #define CAN_F19R2_FB0 ((uint32_t)0x00000001) #define CAN_F19R2_FB1 ((uint32_t)0x00000002) #define CAN_F19R2_FB2 ((uint32_t)0x00000004) #define CAN_F19R2_FB3 ((uint32_t)0x00000008) #define CAN_F19R2_FB4 ((uint32_t)0x00000010) #define CAN_F19R2_FB5 ((uint32_t)0x00000020) #define CAN_F19R2_FB6 ((uint32_t)0x00000040) #define CAN_F19R2_FB7 ((uint32_t)0x00000080) #define CAN_F19R2_FB8 ((uint32_t)0x00000100) #define CAN_F19R2_FB9 ((uint32_t)0x00000200) #define CAN_F19R2_FB10 ((uint32_t)0x00000400) #define CAN_F19R2_FB11 ((uint32_t)0x00000800) #define CAN_F19R2_FB12 ((uint32_t)0x00001000) #define CAN_F19R2_FB13 ((uint32_t)0x00002000) #define CAN_F19R2_FB14 ((uint32_t)0x00004000) #define CAN_F19R2_FB15 ((uint32_t)0x00008000) #define CAN_F19R2_FB16 ((uint32_t)0x00010000) #define CAN_F19R2_FB17 ((uint32_t)0x00020000) #define CAN_F19R2_FB18 ((uint32_t)0x00040000) #define CAN_F19R2_FB19 ((uint32_t)0x00080000) #define CAN_F19R2_FB20 ((uint32_t)0x00100000) #define CAN_F19R2_FB21 ((uint32_t)0x00200000) #define CAN_F19R2_FB22 ((uint32_t)0x00400000) #define CAN_F19R2_FB23 ((uint32_t)0x00800000) #define CAN_F19R2_FB24 ((uint32_t)0x01000000) #define CAN_F19R2_FB25 ((uint32_t)0x02000000) #define CAN_F19R2_FB26 ((uint32_t)0x04000000) #define CAN_F19R2_FB27 ((uint32_t)0x08000000) #define CAN_F19R2_FB28 ((uint32_t)0x10000000) #define CAN_F19R2_FB29 ((uint32_t)0x20000000) #define CAN_F19R2_FB30 ((uint32_t)0x40000000) #define CAN_F19R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F20R2 register ********************/ #define CAN_F20R2_FB0 ((uint32_t)0x00000001) #define CAN_F20R2_FB1 ((uint32_t)0x00000002) #define CAN_F20R2_FB2 ((uint32_t)0x00000004) #define CAN_F20R2_FB3 ((uint32_t)0x00000008) #define CAN_F20R2_FB4 ((uint32_t)0x00000010) #define CAN_F20R2_FB5 ((uint32_t)0x00000020) #define CAN_F20R2_FB6 ((uint32_t)0x00000040) #define CAN_F20R2_FB7 ((uint32_t)0x00000080) #define CAN_F20R2_FB8 ((uint32_t)0x00000100) #define CAN_F20R2_FB9 ((uint32_t)0x00000200) #define CAN_F20R2_FB10 ((uint32_t)0x00000400) #define CAN_F20R2_FB11 ((uint32_t)0x00000800) #define CAN_F20R2_FB12 ((uint32_t)0x00001000) #define CAN_F20R2_FB13 ((uint32_t)0x00002000) #define CAN_F20R2_FB14 ((uint32_t)0x00004000) #define CAN_F20R2_FB15 ((uint32_t)0x00008000) #define CAN_F20R2_FB16 ((uint32_t)0x00010000) #define CAN_F20R2_FB17 ((uint32_t)0x00020000) #define CAN_F20R2_FB18 ((uint32_t)0x00040000) #define CAN_F20R2_FB19 ((uint32_t)0x00080000) #define CAN_F20R2_FB20 ((uint32_t)0x00100000) #define CAN_F20R2_FB21 ((uint32_t)0x00200000) #define CAN_F20R2_FB22 ((uint32_t)0x00400000) #define CAN_F20R2_FB23 ((uint32_t)0x00800000) #define CAN_F20R2_FB24 ((uint32_t)0x01000000) #define CAN_F20R2_FB25 ((uint32_t)0x02000000) #define CAN_F20R2_FB26 ((uint32_t)0x04000000) #define CAN_F20R2_FB27 ((uint32_t)0x08000000) #define CAN_F20R2_FB28 ((uint32_t)0x10000000) #define CAN_F20R2_FB29 ((uint32_t)0x20000000) #define CAN_F20R2_FB30 ((uint32_t)0x40000000) #define CAN_F20R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F21R2 register ********************/ #define CAN_F21R2_FB0 ((uint32_t)0x00000001) #define CAN_F21R2_FB1 ((uint32_t)0x00000002) #define CAN_F21R2_FB2 ((uint32_t)0x00000004) #define CAN_F21R2_FB3 ((uint32_t)0x00000008) #define CAN_F21R2_FB4 ((uint32_t)0x00000010) #define CAN_F21R2_FB5 ((uint32_t)0x00000020) #define CAN_F21R2_FB6 ((uint32_t)0x00000040) #define CAN_F21R2_FB7 ((uint32_t)0x00000080) #define CAN_F21R2_FB8 ((uint32_t)0x00000100) #define CAN_F21R2_FB9 ((uint32_t)0x00000200) #define CAN_F21R2_FB10 ((uint32_t)0x00000400) #define CAN_F21R2_FB11 ((uint32_t)0x00000800) #define CAN_F21R2_FB12 ((uint32_t)0x00001000) #define CAN_F21R2_FB13 ((uint32_t)0x00002000) #define CAN_F21R2_FB14 ((uint32_t)0x00004000) #define CAN_F21R2_FB15 ((uint32_t)0x00008000) #define CAN_F21R2_FB16 ((uint32_t)0x00010000) #define CAN_F21R2_FB17 ((uint32_t)0x00020000) #define CAN_F21R2_FB18 ((uint32_t)0x00040000) #define CAN_F21R2_FB19 ((uint32_t)0x00080000) #define CAN_F21R2_FB20 ((uint32_t)0x00100000) #define CAN_F21R2_FB21 ((uint32_t)0x00200000) #define CAN_F21R2_FB22 ((uint32_t)0x00400000) #define CAN_F21R2_FB23 ((uint32_t)0x00800000) #define CAN_F21R2_FB24 ((uint32_t)0x01000000) #define CAN_F21R2_FB25 ((uint32_t)0x02000000) #define CAN_F21R2_FB26 ((uint32_t)0x04000000) #define CAN_F21R2_FB27 ((uint32_t)0x08000000) #define CAN_F21R2_FB28 ((uint32_t)0x10000000) #define CAN_F21R2_FB29 ((uint32_t)0x20000000) #define CAN_F21R2_FB30 ((uint32_t)0x40000000) #define CAN_F21R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F22R2 register ********************/ #define CAN_F22R2_FB0 ((uint32_t)0x00000001) #define CAN_F22R2_FB1 ((uint32_t)0x00000002) #define CAN_F22R2_FB2 ((uint32_t)0x00000004) #define CAN_F22R2_FB3 ((uint32_t)0x00000008) #define CAN_F22R2_FB4 ((uint32_t)0x00000010) #define CAN_F22R2_FB5 ((uint32_t)0x00000020) #define CAN_F22R2_FB6 ((uint32_t)0x00000040) #define CAN_F22R2_FB7 ((uint32_t)0x00000080) #define CAN_F22R2_FB8 ((uint32_t)0x00000100) #define CAN_F22R2_FB9 ((uint32_t)0x00000200) #define CAN_F22R2_FB10 ((uint32_t)0x00000400) #define CAN_F22R2_FB11 ((uint32_t)0x00000800) #define CAN_F22R2_FB12 ((uint32_t)0x00001000) #define CAN_F22R2_FB13 ((uint32_t)0x00002000) #define CAN_F22R2_FB14 ((uint32_t)0x00004000) #define CAN_F22R2_FB15 ((uint32_t)0x00008000) #define CAN_F22R2_FB16 ((uint32_t)0x00010000) #define CAN_F22R2_FB17 ((uint32_t)0x00020000) #define CAN_F22R2_FB18 ((uint32_t)0x00040000) #define CAN_F22R2_FB19 ((uint32_t)0x00080000) #define CAN_F22R2_FB20 ((uint32_t)0x00100000) #define CAN_F22R2_FB21 ((uint32_t)0x00200000) #define CAN_F22R2_FB22 ((uint32_t)0x00400000) #define CAN_F22R2_FB23 ((uint32_t)0x00800000) #define CAN_F22R2_FB24 ((uint32_t)0x01000000) #define CAN_F22R2_FB25 ((uint32_t)0x02000000) #define CAN_F22R2_FB26 ((uint32_t)0x04000000) #define CAN_F22R2_FB27 ((uint32_t)0x08000000) #define CAN_F22R2_FB28 ((uint32_t)0x10000000) #define CAN_F22R2_FB29 ((uint32_t)0x20000000) #define CAN_F22R2_FB30 ((uint32_t)0x40000000) #define CAN_F22R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F23R2 register ********************/ #define CAN_F23R2_FB0 ((uint32_t)0x00000001) #define CAN_F23R2_FB1 ((uint32_t)0x00000002) #define CAN_F23R2_FB2 ((uint32_t)0x00000004) #define CAN_F23R2_FB3 ((uint32_t)0x00000008) #define CAN_F23R2_FB4 ((uint32_t)0x00000010) #define CAN_F23R2_FB5 ((uint32_t)0x00000020) #define CAN_F23R2_FB6 ((uint32_t)0x00000040) #define CAN_F23R2_FB7 ((uint32_t)0x00000080) #define CAN_F23R2_FB8 ((uint32_t)0x00000100) #define CAN_F23R2_FB9 ((uint32_t)0x00000200) #define CAN_F23R2_FB10 ((uint32_t)0x00000400) #define CAN_F23R2_FB11 ((uint32_t)0x00000800) #define CAN_F23R2_FB12 ((uint32_t)0x00001000) #define CAN_F23R2_FB13 ((uint32_t)0x00002000) #define CAN_F23R2_FB14 ((uint32_t)0x00004000) #define CAN_F23R2_FB15 ((uint32_t)0x00008000) #define CAN_F23R2_FB16 ((uint32_t)0x00010000) #define CAN_F23R2_FB17 ((uint32_t)0x00020000) #define CAN_F23R2_FB18 ((uint32_t)0x00040000) #define CAN_F23R2_FB19 ((uint32_t)0x00080000) #define CAN_F23R2_FB20 ((uint32_t)0x00100000) #define CAN_F23R2_FB21 ((uint32_t)0x00200000) #define CAN_F23R2_FB22 ((uint32_t)0x00400000) #define CAN_F23R2_FB23 ((uint32_t)0x00800000) #define CAN_F23R2_FB24 ((uint32_t)0x01000000) #define CAN_F23R2_FB25 ((uint32_t)0x02000000) #define CAN_F23R2_FB26 ((uint32_t)0x04000000) #define CAN_F23R2_FB27 ((uint32_t)0x08000000) #define CAN_F23R2_FB28 ((uint32_t)0x10000000) #define CAN_F23R2_FB29 ((uint32_t)0x20000000) #define CAN_F23R2_FB30 ((uint32_t)0x40000000) #define CAN_F23R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F24R2 register ********************/ #define CAN_F24R2_FB0 ((uint32_t)0x00000001) #define CAN_F24R2_FB1 ((uint32_t)0x00000002) #define CAN_F24R2_FB2 ((uint32_t)0x00000004) #define CAN_F24R2_FB3 ((uint32_t)0x00000008) #define CAN_F24R2_FB4 ((uint32_t)0x00000010) #define CAN_F24R2_FB5 ((uint32_t)0x00000020) #define CAN_F24R2_FB6 ((uint32_t)0x00000040) #define CAN_F24R2_FB7 ((uint32_t)0x00000080) #define CAN_F24R2_FB8 ((uint32_t)0x00000100) #define CAN_F24R2_FB9 ((uint32_t)0x00000200) #define CAN_F24R2_FB10 ((uint32_t)0x00000400) #define CAN_F24R2_FB11 ((uint32_t)0x00000800) #define CAN_F24R2_FB12 ((uint32_t)0x00001000) #define CAN_F24R2_FB13 ((uint32_t)0x00002000) #define CAN_F24R2_FB14 ((uint32_t)0x00004000) #define CAN_F24R2_FB15 ((uint32_t)0x00008000) #define CAN_F24R2_FB16 ((uint32_t)0x00010000) #define CAN_F24R2_FB17 ((uint32_t)0x00020000) #define CAN_F24R2_FB18 ((uint32_t)0x00040000) #define CAN_F24R2_FB19 ((uint32_t)0x00080000) #define CAN_F24R2_FB20 ((uint32_t)0x00100000) #define CAN_F24R2_FB21 ((uint32_t)0x00200000) #define CAN_F24R2_FB22 ((uint32_t)0x00400000) #define CAN_F24R2_FB23 ((uint32_t)0x00800000) #define CAN_F24R2_FB24 ((uint32_t)0x01000000) #define CAN_F24R2_FB25 ((uint32_t)0x02000000) #define CAN_F24R2_FB26 ((uint32_t)0x04000000) #define CAN_F24R2_FB27 ((uint32_t)0x08000000) #define CAN_F24R2_FB28 ((uint32_t)0x10000000) #define CAN_F24R2_FB29 ((uint32_t)0x20000000) #define CAN_F24R2_FB30 ((uint32_t)0x40000000) #define CAN_F24R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F25R2 register ********************/ #define CAN_F25R2_FB0 ((uint32_t)0x00000001) #define CAN_F25R2_FB1 ((uint32_t)0x00000002) #define CAN_F25R2_FB2 ((uint32_t)0x00000004) #define CAN_F25R2_FB3 ((uint32_t)0x00000008) #define CAN_F25R2_FB4 ((uint32_t)0x00000010) #define CAN_F25R2_FB5 ((uint32_t)0x00000020) #define CAN_F25R2_FB6 ((uint32_t)0x00000040) #define CAN_F25R2_FB7 ((uint32_t)0x00000080) #define CAN_F25R2_FB8 ((uint32_t)0x00000100) #define CAN_F25R2_FB9 ((uint32_t)0x00000200) #define CAN_F25R2_FB10 ((uint32_t)0x00000400) #define CAN_F25R2_FB11 ((uint32_t)0x00000800) #define CAN_F25R2_FB12 ((uint32_t)0x00001000) #define CAN_F25R2_FB13 ((uint32_t)0x00002000) #define CAN_F25R2_FB14 ((uint32_t)0x00004000) #define CAN_F25R2_FB15 ((uint32_t)0x00008000) #define CAN_F25R2_FB16 ((uint32_t)0x00010000) #define CAN_F25R2_FB17 ((uint32_t)0x00020000) #define CAN_F25R2_FB18 ((uint32_t)0x00040000) #define CAN_F25R2_FB19 ((uint32_t)0x00080000) #define CAN_F25R2_FB20 ((uint32_t)0x00100000) #define CAN_F25R2_FB21 ((uint32_t)0x00200000) #define CAN_F25R2_FB22 ((uint32_t)0x00400000) #define CAN_F25R2_FB23 ((uint32_t)0x00800000) #define CAN_F25R2_FB24 ((uint32_t)0x01000000) #define CAN_F25R2_FB25 ((uint32_t)0x02000000) #define CAN_F25R2_FB26 ((uint32_t)0x04000000) #define CAN_F25R2_FB27 ((uint32_t)0x08000000) #define CAN_F25R2_FB28 ((uint32_t)0x10000000) #define CAN_F25R2_FB29 ((uint32_t)0x20000000) #define CAN_F25R2_FB30 ((uint32_t)0x40000000) #define CAN_F25R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F26R2 register ********************/ #define CAN_F26R2_FB0 ((uint32_t)0x00000001) #define CAN_F26R2_FB1 ((uint32_t)0x00000002) #define CAN_F26R2_FB2 ((uint32_t)0x00000004) #define CAN_F26R2_FB3 ((uint32_t)0x00000008) #define CAN_F26R2_FB4 ((uint32_t)0x00000010) #define CAN_F26R2_FB5 ((uint32_t)0x00000020) #define CAN_F26R2_FB6 ((uint32_t)0x00000040) #define CAN_F26R2_FB7 ((uint32_t)0x00000080) #define CAN_F26R2_FB8 ((uint32_t)0x00000100) #define CAN_F26R2_FB9 ((uint32_t)0x00000200) #define CAN_F26R2_FB10 ((uint32_t)0x00000400) #define CAN_F26R2_FB11 ((uint32_t)0x00000800) #define CAN_F26R2_FB12 ((uint32_t)0x00001000) #define CAN_F26R2_FB13 ((uint32_t)0x00002000) #define CAN_F26R2_FB14 ((uint32_t)0x00004000) #define CAN_F26R2_FB15 ((uint32_t)0x00008000) #define CAN_F26R2_FB16 ((uint32_t)0x00010000) #define CAN_F26R2_FB17 ((uint32_t)0x00020000) #define CAN_F26R2_FB18 ((uint32_t)0x00040000) #define CAN_F26R2_FB19 ((uint32_t)0x00080000) #define CAN_F26R2_FB20 ((uint32_t)0x00100000) #define CAN_F26R2_FB21 ((uint32_t)0x00200000) #define CAN_F26R2_FB22 ((uint32_t)0x00400000) #define CAN_F26R2_FB23 ((uint32_t)0x00800000) #define CAN_F26R2_FB24 ((uint32_t)0x01000000) #define CAN_F26R2_FB25 ((uint32_t)0x02000000) #define CAN_F26R2_FB26 ((uint32_t)0x04000000) #define CAN_F26R2_FB27 ((uint32_t)0x08000000) #define CAN_F26R2_FB28 ((uint32_t)0x10000000) #define CAN_F26R2_FB29 ((uint32_t)0x20000000) #define CAN_F26R2_FB30 ((uint32_t)0x40000000) #define CAN_F26R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F27R2 register ********************/ #define CAN_F27R2_FB0 ((uint32_t)0x00000001) #define CAN_F27R2_FB1 ((uint32_t)0x00000002) #define CAN_F27R2_FB2 ((uint32_t)0x00000004) #define CAN_F27R2_FB3 ((uint32_t)0x00000008) #define CAN_F27R2_FB4 ((uint32_t)0x00000010) #define CAN_F27R2_FB5 ((uint32_t)0x00000020) #define CAN_F27R2_FB6 ((uint32_t)0x00000040) #define CAN_F27R2_FB7 ((uint32_t)0x00000080) #define CAN_F27R2_FB8 ((uint32_t)0x00000100) #define CAN_F27R2_FB9 ((uint32_t)0x00000200) #define CAN_F27R2_FB10 ((uint32_t)0x00000400) #define CAN_F27R2_FB11 ((uint32_t)0x00000800) #define CAN_F27R2_FB12 ((uint32_t)0x00001000) #define CAN_F27R2_FB13 ((uint32_t)0x00002000) #define CAN_F27R2_FB14 ((uint32_t)0x00004000) #define CAN_F27R2_FB15 ((uint32_t)0x00008000) #define CAN_F27R2_FB16 ((uint32_t)0x00010000) #define CAN_F27R2_FB17 ((uint32_t)0x00020000) #define CAN_F27R2_FB18 ((uint32_t)0x00040000) #define CAN_F27R2_FB19 ((uint32_t)0x00080000) #define CAN_F27R2_FB20 ((uint32_t)0x00100000) #define CAN_F27R2_FB21 ((uint32_t)0x00200000) #define CAN_F27R2_FB22 ((uint32_t)0x00400000) #define CAN_F27R2_FB23 ((uint32_t)0x00800000) #define CAN_F27R2_FB24 ((uint32_t)0x01000000) #define CAN_F27R2_FB25 ((uint32_t)0x02000000) #define CAN_F27R2_FB26 ((uint32_t)0x04000000) #define CAN_F27R2_FB27 ((uint32_t)0x08000000) #define CAN_F27R2_FB28 ((uint32_t)0x10000000) #define CAN_F27R2_FB29 ((uint32_t)0x20000000) #define CAN_F27R2_FB30 ((uint32_t)0x40000000) #define CAN_F27R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F28R2 register ********************/ #define CAN_F28R2_FB0 ((uint32_t)0x00000001) #define CAN_F28R2_FB1 ((uint32_t)0x00000002) #define CAN_F28R2_FB2 ((uint32_t)0x00000004) #define CAN_F28R2_FB3 ((uint32_t)0x00000008) #define CAN_F28R2_FB4 ((uint32_t)0x00000010) #define CAN_F28R2_FB5 ((uint32_t)0x00000020) #define CAN_F28R2_FB6 ((uint32_t)0x00000040) #define CAN_F28R2_FB7 ((uint32_t)0x00000080) #define CAN_F28R2_FB8 ((uint32_t)0x00000100) #define CAN_F28R2_FB9 ((uint32_t)0x00000200) #define CAN_F28R2_FB10 ((uint32_t)0x00000400) #define CAN_F28R2_FB11 ((uint32_t)0x00000800) #define CAN_F28R2_FB12 ((uint32_t)0x00001000) #define CAN_F28R2_FB13 ((uint32_t)0x00002000) #define CAN_F28R2_FB14 ((uint32_t)0x00004000) #define CAN_F28R2_FB15 ((uint32_t)0x00008000) #define CAN_F28R2_FB16 ((uint32_t)0x00010000) #define CAN_F28R2_FB17 ((uint32_t)0x00020000) #define CAN_F28R2_FB18 ((uint32_t)0x00040000) #define CAN_F28R2_FB19 ((uint32_t)0x00080000) #define CAN_F28R2_FB20 ((uint32_t)0x00100000) #define CAN_F28R2_FB21 ((uint32_t)0x00200000) #define CAN_F28R2_FB22 ((uint32_t)0x00400000) #define CAN_F28R2_FB23 ((uint32_t)0x00800000) #define CAN_F28R2_FB24 ((uint32_t)0x01000000) #define CAN_F28R2_FB25 ((uint32_t)0x02000000) #define CAN_F28R2_FB26 ((uint32_t)0x04000000) #define CAN_F28R2_FB27 ((uint32_t)0x08000000) #define CAN_F28R2_FB28 ((uint32_t)0x10000000) #define CAN_F28R2_FB29 ((uint32_t)0x20000000) #define CAN_F28R2_FB30 ((uint32_t)0x40000000) #define CAN_F28R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F29R2 register ********************/ #define CAN_F29R2_FB0 ((uint32_t)0x00000001) #define CAN_F29R2_FB1 ((uint32_t)0x00000002) #define CAN_F29R2_FB2 ((uint32_t)0x00000004) #define CAN_F29R2_FB3 ((uint32_t)0x00000008) #define CAN_F29R2_FB4 ((uint32_t)0x00000010) #define CAN_F29R2_FB5 ((uint32_t)0x00000020) #define CAN_F29R2_FB6 ((uint32_t)0x00000040) #define CAN_F29R2_FB7 ((uint32_t)0x00000080) #define CAN_F29R2_FB8 ((uint32_t)0x00000100) #define CAN_F29R2_FB9 ((uint32_t)0x00000200) #define CAN_F29R2_FB10 ((uint32_t)0x00000400) #define CAN_F29R2_FB11 ((uint32_t)0x00000800) #define CAN_F29R2_FB12 ((uint32_t)0x00001000) #define CAN_F29R2_FB13 ((uint32_t)0x00002000) #define CAN_F29R2_FB14 ((uint32_t)0x00004000) #define CAN_F29R2_FB15 ((uint32_t)0x00008000) #define CAN_F29R2_FB16 ((uint32_t)0x00010000) #define CAN_F29R2_FB17 ((uint32_t)0x00020000) #define CAN_F29R2_FB18 ((uint32_t)0x00040000) #define CAN_F29R2_FB19 ((uint32_t)0x00080000) #define CAN_F29R2_FB20 ((uint32_t)0x00100000) #define CAN_F29R2_FB21 ((uint32_t)0x00200000) #define CAN_F29R2_FB22 ((uint32_t)0x00400000) #define CAN_F29R2_FB23 ((uint32_t)0x00800000) #define CAN_F29R2_FB24 ((uint32_t)0x01000000) #define CAN_F29R2_FB25 ((uint32_t)0x02000000) #define CAN_F29R2_FB26 ((uint32_t)0x04000000) #define CAN_F29R2_FB27 ((uint32_t)0x08000000) #define CAN_F29R2_FB28 ((uint32_t)0x10000000) #define CAN_F29R2_FB29 ((uint32_t)0x20000000) #define CAN_F29R2_FB30 ((uint32_t)0x40000000) #define CAN_F29R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F30R2 register ********************/ #define CAN_F30R2_FB0 ((uint32_t)0x00000001) #define CAN_F30R2_FB1 ((uint32_t)0x00000002) #define CAN_F30R2_FB2 ((uint32_t)0x00000004) #define CAN_F30R2_FB3 ((uint32_t)0x00000008) #define CAN_F30R2_FB4 ((uint32_t)0x00000010) #define CAN_F30R2_FB5 ((uint32_t)0x00000020) #define CAN_F30R2_FB6 ((uint32_t)0x00000040) #define CAN_F30R2_FB7 ((uint32_t)0x00000080) #define CAN_F30R2_FB8 ((uint32_t)0x00000100) #define CAN_F30R2_FB9 ((uint32_t)0x00000200) #define CAN_F30R2_FB10 ((uint32_t)0x00000400) #define CAN_F30R2_FB11 ((uint32_t)0x00000800) #define CAN_F30R2_FB12 ((uint32_t)0x00001000) #define CAN_F30R2_FB13 ((uint32_t)0x00002000) #define CAN_F30R2_FB14 ((uint32_t)0x00004000) #define CAN_F30R2_FB15 ((uint32_t)0x00008000) #define CAN_F30R2_FB16 ((uint32_t)0x00010000) #define CAN_F30R2_FB17 ((uint32_t)0x00020000) #define CAN_F30R2_FB18 ((uint32_t)0x00040000) #define CAN_F30R2_FB19 ((uint32_t)0x00080000) #define CAN_F30R2_FB20 ((uint32_t)0x00100000) #define CAN_F30R2_FB21 ((uint32_t)0x00200000) #define CAN_F30R2_FB22 ((uint32_t)0x00400000) #define CAN_F30R2_FB23 ((uint32_t)0x00800000) #define CAN_F30R2_FB24 ((uint32_t)0x01000000) #define CAN_F30R2_FB25 ((uint32_t)0x02000000) #define CAN_F30R2_FB26 ((uint32_t)0x04000000) #define CAN_F30R2_FB27 ((uint32_t)0x08000000) #define CAN_F30R2_FB28 ((uint32_t)0x10000000) #define CAN_F30R2_FB29 ((uint32_t)0x20000000) #define CAN_F30R2_FB30 ((uint32_t)0x40000000) #define CAN_F30R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F31R2 register ********************/ #define CAN_F31R2_FB0 ((uint32_t)0x00000001) #define CAN_F31R2_FB1 ((uint32_t)0x00000002) #define CAN_F31R2_FB2 ((uint32_t)0x00000004) #define CAN_F31R2_FB3 ((uint32_t)0x00000008) #define CAN_F31R2_FB4 ((uint32_t)0x00000010) #define CAN_F31R2_FB5 ((uint32_t)0x00000020) #define CAN_F31R2_FB6 ((uint32_t)0x00000040) #define CAN_F31R2_FB7 ((uint32_t)0x00000080) #define CAN_F31R2_FB8 ((uint32_t)0x00000100) #define CAN_F31R2_FB9 ((uint32_t)0x00000200) #define CAN_F31R2_FB10 ((uint32_t)0x00000400) #define CAN_F31R2_FB11 ((uint32_t)0x00000800) #define CAN_F31R2_FB12 ((uint32_t)0x00001000) #define CAN_F31R2_FB13 ((uint32_t)0x00002000) #define CAN_F31R2_FB14 ((uint32_t)0x00004000) #define CAN_F31R2_FB15 ((uint32_t)0x00008000) #define CAN_F31R2_FB16 ((uint32_t)0x00010000) #define CAN_F31R2_FB17 ((uint32_t)0x00020000) #define CAN_F31R2_FB18 ((uint32_t)0x00040000) #define CAN_F31R2_FB19 ((uint32_t)0x00080000) #define CAN_F31R2_FB20 ((uint32_t)0x00100000) #define CAN_F31R2_FB21 ((uint32_t)0x00200000) #define CAN_F31R2_FB22 ((uint32_t)0x00400000) #define CAN_F31R2_FB23 ((uint32_t)0x00800000) #define CAN_F31R2_FB24 ((uint32_t)0x01000000) #define CAN_F31R2_FB25 ((uint32_t)0x02000000) #define CAN_F31R2_FB26 ((uint32_t)0x04000000) #define CAN_F31R2_FB27 ((uint32_t)0x08000000) #define CAN_F31R2_FB28 ((uint32_t)0x10000000) #define CAN_F31R2_FB29 ((uint32_t)0x20000000) #define CAN_F31R2_FB30 ((uint32_t)0x40000000) #define CAN_F31R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F32R2 register ********************/ #define CAN_F32R2_FB0 ((uint32_t)0x00000001) #define CAN_F32R2_FB1 ((uint32_t)0x00000002) #define CAN_F32R2_FB2 ((uint32_t)0x00000004) #define CAN_F32R2_FB3 ((uint32_t)0x00000008) #define CAN_F32R2_FB4 ((uint32_t)0x00000010) #define CAN_F32R2_FB5 ((uint32_t)0x00000020) #define CAN_F32R2_FB6 ((uint32_t)0x00000040) #define CAN_F32R2_FB7 ((uint32_t)0x00000080) #define CAN_F32R2_FB8 ((uint32_t)0x00000100) #define CAN_F32R2_FB9 ((uint32_t)0x00000200) #define CAN_F32R2_FB10 ((uint32_t)0x00000400) #define CAN_F32R2_FB11 ((uint32_t)0x00000800) #define CAN_F32R2_FB12 ((uint32_t)0x00001000) #define CAN_F32R2_FB13 ((uint32_t)0x00002000) #define CAN_F32R2_FB14 ((uint32_t)0x00004000) #define CAN_F32R2_FB15 ((uint32_t)0x00008000) #define CAN_F32R2_FB16 ((uint32_t)0x00010000) #define CAN_F32R2_FB17 ((uint32_t)0x00020000) #define CAN_F32R2_FB18 ((uint32_t)0x00040000) #define CAN_F32R2_FB19 ((uint32_t)0x00080000) #define CAN_F32R2_FB20 ((uint32_t)0x00100000) #define CAN_F32R2_FB21 ((uint32_t)0x00200000) #define CAN_F32R2_FB22 ((uint32_t)0x00400000) #define CAN_F32R2_FB23 ((uint32_t)0x00800000) #define CAN_F32R2_FB24 ((uint32_t)0x01000000) #define CAN_F32R2_FB25 ((uint32_t)0x02000000) #define CAN_F32R2_FB26 ((uint32_t)0x04000000) #define CAN_F32R2_FB27 ((uint32_t)0x08000000) #define CAN_F32R2_FB28 ((uint32_t)0x10000000) #define CAN_F32R2_FB29 ((uint32_t)0x20000000) #define CAN_F32R2_FB30 ((uint32_t)0x40000000) #define CAN_F32R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F33R2 register ********************/ #define CAN_F33R2_FB0 ((uint32_t)0x00000001) #define CAN_F33R2_FB1 ((uint32_t)0x00000002) #define CAN_F33R2_FB2 ((uint32_t)0x00000004) #define CAN_F33R2_FB3 ((uint32_t)0x00000008) #define CAN_F33R2_FB4 ((uint32_t)0x00000010) #define CAN_F33R2_FB5 ((uint32_t)0x00000020) #define CAN_F33R2_FB6 ((uint32_t)0x00000040) #define CAN_F33R2_FB7 ((uint32_t)0x00000080) #define CAN_F33R2_FB8 ((uint32_t)0x00000100) #define CAN_F33R2_FB9 ((uint32_t)0x00000200) #define CAN_F33R2_FB10 ((uint32_t)0x00000400) #define CAN_F33R2_FB11 ((uint32_t)0x00000800) #define CAN_F33R2_FB12 ((uint32_t)0x00001000) #define CAN_F33R2_FB13 ((uint32_t)0x00002000) #define CAN_F33R2_FB14 ((uint32_t)0x00004000) #define CAN_F33R2_FB15 ((uint32_t)0x00008000) #define CAN_F33R2_FB16 ((uint32_t)0x00010000) #define CAN_F33R2_FB17 ((uint32_t)0x00020000) #define CAN_F33R2_FB18 ((uint32_t)0x00040000) #define CAN_F33R2_FB19 ((uint32_t)0x00080000) #define CAN_F33R2_FB20 ((uint32_t)0x00100000) #define CAN_F33R2_FB21 ((uint32_t)0x00200000) #define CAN_F33R2_FB22 ((uint32_t)0x00400000) #define CAN_F33R2_FB23 ((uint32_t)0x00800000) #define CAN_F33R2_FB24 ((uint32_t)0x01000000) #define CAN_F33R2_FB25 ((uint32_t)0x02000000) #define CAN_F33R2_FB26 ((uint32_t)0x04000000) #define CAN_F33R2_FB27 ((uint32_t)0x08000000) #define CAN_F33R2_FB28 ((uint32_t)0x10000000) #define CAN_F33R2_FB29 ((uint32_t)0x20000000) #define CAN_F33R2_FB30 ((uint32_t)0x40000000) #define CAN_F33R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F34R2 register ********************/ #define CAN_F34R2_FB0 ((uint32_t)0x00000001) #define CAN_F34R2_FB1 ((uint32_t)0x00000002) #define CAN_F34R2_FB2 ((uint32_t)0x00000004) #define CAN_F34R2_FB3 ((uint32_t)0x00000008) #define CAN_F34R2_FB4 ((uint32_t)0x00000010) #define CAN_F34R2_FB5 ((uint32_t)0x00000020) #define CAN_F34R2_FB6 ((uint32_t)0x00000040) #define CAN_F34R2_FB7 ((uint32_t)0x00000080) #define CAN_F34R2_FB8 ((uint32_t)0x00000100) #define CAN_F34R2_FB9 ((uint32_t)0x00000200) #define CAN_F34R2_FB10 ((uint32_t)0x00000400) #define CAN_F34R2_FB11 ((uint32_t)0x00000800) #define CAN_F34R2_FB12 ((uint32_t)0x00001000) #define CAN_F34R2_FB13 ((uint32_t)0x00002000) #define CAN_F34R2_FB14 ((uint32_t)0x00004000) #define CAN_F34R2_FB15 ((uint32_t)0x00008000) #define CAN_F34R2_FB16 ((uint32_t)0x00010000) #define CAN_F34R2_FB17 ((uint32_t)0x00020000) #define CAN_F34R2_FB18 ((uint32_t)0x00040000) #define CAN_F34R2_FB19 ((uint32_t)0x00080000) #define CAN_F34R2_FB20 ((uint32_t)0x00100000) #define CAN_F34R2_FB21 ((uint32_t)0x00200000) #define CAN_F34R2_FB22 ((uint32_t)0x00400000) #define CAN_F34R2_FB23 ((uint32_t)0x00800000) #define CAN_F34R2_FB24 ((uint32_t)0x01000000) #define CAN_F34R2_FB25 ((uint32_t)0x02000000) #define CAN_F34R2_FB26 ((uint32_t)0x04000000) #define CAN_F34R2_FB27 ((uint32_t)0x08000000) #define CAN_F34R2_FB28 ((uint32_t)0x10000000) #define CAN_F34R2_FB29 ((uint32_t)0x20000000) #define CAN_F34R2_FB30 ((uint32_t)0x40000000) #define CAN_F34R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F35R2 register ********************/ #define CAN_F35R2_FB0 ((uint32_t)0x00000001) #define CAN_F35R2_FB1 ((uint32_t)0x00000002) #define CAN_F35R2_FB2 ((uint32_t)0x00000004) #define CAN_F35R2_FB3 ((uint32_t)0x00000008) #define CAN_F35R2_FB4 ((uint32_t)0x00000010) #define CAN_F35R2_FB5 ((uint32_t)0x00000020) #define CAN_F35R2_FB6 ((uint32_t)0x00000040) #define CAN_F35R2_FB7 ((uint32_t)0x00000080) #define CAN_F35R2_FB8 ((uint32_t)0x00000100) #define CAN_F35R2_FB9 ((uint32_t)0x00000200) #define CAN_F35R2_FB10 ((uint32_t)0x00000400) #define CAN_F35R2_FB11 ((uint32_t)0x00000800) #define CAN_F35R2_FB12 ((uint32_t)0x00001000) #define CAN_F35R2_FB13 ((uint32_t)0x00002000) #define CAN_F35R2_FB14 ((uint32_t)0x00004000) #define CAN_F35R2_FB15 ((uint32_t)0x00008000) #define CAN_F35R2_FB16 ((uint32_t)0x00010000) #define CAN_F35R2_FB17 ((uint32_t)0x00020000) #define CAN_F35R2_FB18 ((uint32_t)0x00040000) #define CAN_F35R2_FB19 ((uint32_t)0x00080000) #define CAN_F35R2_FB20 ((uint32_t)0x00100000) #define CAN_F35R2_FB21 ((uint32_t)0x00200000) #define CAN_F35R2_FB22 ((uint32_t)0x00400000) #define CAN_F35R2_FB23 ((uint32_t)0x00800000) #define CAN_F35R2_FB24 ((uint32_t)0x01000000) #define CAN_F35R2_FB25 ((uint32_t)0x02000000) #define CAN_F35R2_FB26 ((uint32_t)0x04000000) #define CAN_F35R2_FB27 ((uint32_t)0x08000000) #define CAN_F35R2_FB28 ((uint32_t)0x10000000) #define CAN_F35R2_FB29 ((uint32_t)0x20000000) #define CAN_F35R2_FB30 ((uint32_t)0x40000000) #define CAN_F35R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F36R2 register ********************/ #define CAN_F36R2_FB0 ((uint32_t)0x00000001) #define CAN_F36R2_FB1 ((uint32_t)0x00000002) #define CAN_F36R2_FB2 ((uint32_t)0x00000004) #define CAN_F36R2_FB3 ((uint32_t)0x00000008) #define CAN_F36R2_FB4 ((uint32_t)0x00000010) #define CAN_F36R2_FB5 ((uint32_t)0x00000020) #define CAN_F36R2_FB6 ((uint32_t)0x00000040) #define CAN_F36R2_FB7 ((uint32_t)0x00000080) #define CAN_F36R2_FB8 ((uint32_t)0x00000100) #define CAN_F36R2_FB9 ((uint32_t)0x00000200) #define CAN_F36R2_FB10 ((uint32_t)0x00000400) #define CAN_F36R2_FB11 ((uint32_t)0x00000800) #define CAN_F36R2_FB12 ((uint32_t)0x00001000) #define CAN_F36R2_FB13 ((uint32_t)0x00002000) #define CAN_F36R2_FB14 ((uint32_t)0x00004000) #define CAN_F36R2_FB15 ((uint32_t)0x00008000) #define CAN_F36R2_FB16 ((uint32_t)0x00010000) #define CAN_F36R2_FB17 ((uint32_t)0x00020000) #define CAN_F36R2_FB18 ((uint32_t)0x00040000) #define CAN_F36R2_FB19 ((uint32_t)0x00080000) #define CAN_F36R2_FB20 ((uint32_t)0x00100000) #define CAN_F36R2_FB21 ((uint32_t)0x00200000) #define CAN_F36R2_FB22 ((uint32_t)0x00400000) #define CAN_F36R2_FB23 ((uint32_t)0x00800000) #define CAN_F36R2_FB24 ((uint32_t)0x01000000) #define CAN_F36R2_FB25 ((uint32_t)0x02000000) #define CAN_F36R2_FB26 ((uint32_t)0x04000000) #define CAN_F36R2_FB27 ((uint32_t)0x08000000) #define CAN_F36R2_FB28 ((uint32_t)0x10000000) #define CAN_F36R2_FB29 ((uint32_t)0x20000000) #define CAN_F36R2_FB30 ((uint32_t)0x40000000) #define CAN_F36R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F37R2 register ********************/ #define CAN_F37R2_FB0 ((uint32_t)0x00000001) #define CAN_F37R2_FB1 ((uint32_t)0x00000002) #define CAN_F37R2_FB2 ((uint32_t)0x00000004) #define CAN_F37R2_FB3 ((uint32_t)0x00000008) #define CAN_F37R2_FB4 ((uint32_t)0x00000010) #define CAN_F37R2_FB5 ((uint32_t)0x00000020) #define CAN_F37R2_FB6 ((uint32_t)0x00000040) #define CAN_F37R2_FB7 ((uint32_t)0x00000080) #define CAN_F37R2_FB8 ((uint32_t)0x00000100) #define CAN_F37R2_FB9 ((uint32_t)0x00000200) #define CAN_F37R2_FB10 ((uint32_t)0x00000400) #define CAN_F37R2_FB11 ((uint32_t)0x00000800) #define CAN_F37R2_FB12 ((uint32_t)0x00001000) #define CAN_F37R2_FB13 ((uint32_t)0x00002000) #define CAN_F37R2_FB14 ((uint32_t)0x00004000) #define CAN_F37R2_FB15 ((uint32_t)0x00008000) #define CAN_F37R2_FB16 ((uint32_t)0x00010000) #define CAN_F37R2_FB17 ((uint32_t)0x00020000) #define CAN_F37R2_FB18 ((uint32_t)0x00040000) #define CAN_F37R2_FB19 ((uint32_t)0x00080000) #define CAN_F37R2_FB20 ((uint32_t)0x00100000) #define CAN_F37R2_FB21 ((uint32_t)0x00200000) #define CAN_F37R2_FB22 ((uint32_t)0x00400000) #define CAN_F37R2_FB23 ((uint32_t)0x00800000) #define CAN_F37R2_FB24 ((uint32_t)0x01000000) #define CAN_F37R2_FB25 ((uint32_t)0x02000000) #define CAN_F37R2_FB26 ((uint32_t)0x04000000) #define CAN_F37R2_FB27 ((uint32_t)0x08000000) #define CAN_F37R2_FB28 ((uint32_t)0x10000000) #define CAN_F37R2_FB29 ((uint32_t)0x20000000) #define CAN_F37R2_FB30 ((uint32_t)0x40000000) #define CAN_F37R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F38R2 register ********************/ #define CAN_F38R2_FB0 ((uint32_t)0x00000001) #define CAN_F38R2_FB1 ((uint32_t)0x00000002) #define CAN_F38R2_FB2 ((uint32_t)0x00000004) #define CAN_F38R2_FB3 ((uint32_t)0x00000008) #define CAN_F38R2_FB4 ((uint32_t)0x00000010) #define CAN_F38R2_FB5 ((uint32_t)0x00000020) #define CAN_F38R2_FB6 ((uint32_t)0x00000040) #define CAN_F38R2_FB7 ((uint32_t)0x00000080) #define CAN_F38R2_FB8 ((uint32_t)0x00000100) #define CAN_F38R2_FB9 ((uint32_t)0x00000200) #define CAN_F38R2_FB10 ((uint32_t)0x00000400) #define CAN_F38R2_FB11 ((uint32_t)0x00000800) #define CAN_F38R2_FB12 ((uint32_t)0x00001000) #define CAN_F38R2_FB13 ((uint32_t)0x00002000) #define CAN_F38R2_FB14 ((uint32_t)0x00004000) #define CAN_F38R2_FB15 ((uint32_t)0x00008000) #define CAN_F38R2_FB16 ((uint32_t)0x00010000) #define CAN_F38R2_FB17 ((uint32_t)0x00020000) #define CAN_F38R2_FB18 ((uint32_t)0x00040000) #define CAN_F38R2_FB19 ((uint32_t)0x00080000) #define CAN_F38R2_FB20 ((uint32_t)0x00100000) #define CAN_F38R2_FB21 ((uint32_t)0x00200000) #define CAN_F38R2_FB22 ((uint32_t)0x00400000) #define CAN_F38R2_FB23 ((uint32_t)0x00800000) #define CAN_F38R2_FB24 ((uint32_t)0x01000000) #define CAN_F38R2_FB25 ((uint32_t)0x02000000) #define CAN_F38R2_FB26 ((uint32_t)0x04000000) #define CAN_F38R2_FB27 ((uint32_t)0x08000000) #define CAN_F38R2_FB28 ((uint32_t)0x10000000) #define CAN_F38R2_FB29 ((uint32_t)0x20000000) #define CAN_F38R2_FB30 ((uint32_t)0x40000000) #define CAN_F38R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F39R2 register ********************/ #define CAN_F39R2_FB0 ((uint32_t)0x00000001) #define CAN_F39R2_FB1 ((uint32_t)0x00000002) #define CAN_F39R2_FB2 ((uint32_t)0x00000004) #define CAN_F39R2_FB3 ((uint32_t)0x00000008) #define CAN_F39R2_FB4 ((uint32_t)0x00000010) #define CAN_F39R2_FB5 ((uint32_t)0x00000020) #define CAN_F39R2_FB6 ((uint32_t)0x00000040) #define CAN_F39R2_FB7 ((uint32_t)0x00000080) #define CAN_F39R2_FB8 ((uint32_t)0x00000100) #define CAN_F39R2_FB9 ((uint32_t)0x00000200) #define CAN_F39R2_FB10 ((uint32_t)0x00000400) #define CAN_F39R2_FB11 ((uint32_t)0x00000800) #define CAN_F39R2_FB12 ((uint32_t)0x00001000) #define CAN_F39R2_FB13 ((uint32_t)0x00002000) #define CAN_F39R2_FB14 ((uint32_t)0x00004000) #define CAN_F39R2_FB15 ((uint32_t)0x00008000) #define CAN_F39R2_FB16 ((uint32_t)0x00010000) #define CAN_F39R2_FB17 ((uint32_t)0x00020000) #define CAN_F39R2_FB18 ((uint32_t)0x00040000) #define CAN_F39R2_FB19 ((uint32_t)0x00080000) #define CAN_F39R2_FB20 ((uint32_t)0x00100000) #define CAN_F39R2_FB21 ((uint32_t)0x00200000) #define CAN_F39R2_FB22 ((uint32_t)0x00400000) #define CAN_F39R2_FB23 ((uint32_t)0x00800000) #define CAN_F39R2_FB24 ((uint32_t)0x01000000) #define CAN_F39R2_FB25 ((uint32_t)0x02000000) #define CAN_F39R2_FB26 ((uint32_t)0x04000000) #define CAN_F39R2_FB27 ((uint32_t)0x08000000) #define CAN_F39R2_FB28 ((uint32_t)0x10000000) #define CAN_F39R2_FB29 ((uint32_t)0x20000000) #define CAN_F39R2_FB30 ((uint32_t)0x40000000) #define CAN_F39R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F40R2 register ********************/ #define CAN_F40R2_FB0 ((uint32_t)0x00000001) #define CAN_F40R2_FB1 ((uint32_t)0x00000002) #define CAN_F40R2_FB2 ((uint32_t)0x00000004) #define CAN_F40R2_FB3 ((uint32_t)0x00000008) #define CAN_F40R2_FB4 ((uint32_t)0x00000010) #define CAN_F40R2_FB5 ((uint32_t)0x00000020) #define CAN_F40R2_FB6 ((uint32_t)0x00000040) #define CAN_F40R2_FB7 ((uint32_t)0x00000080) #define CAN_F40R2_FB8 ((uint32_t)0x00000100) #define CAN_F40R2_FB9 ((uint32_t)0x00000200) #define CAN_F40R2_FB10 ((uint32_t)0x00000400) #define CAN_F40R2_FB11 ((uint32_t)0x00000800) #define CAN_F40R2_FB12 ((uint32_t)0x00001000) #define CAN_F40R2_FB13 ((uint32_t)0x00002000) #define CAN_F40R2_FB14 ((uint32_t)0x00004000) #define CAN_F40R2_FB15 ((uint32_t)0x00008000) #define CAN_F40R2_FB16 ((uint32_t)0x00010000) #define CAN_F40R2_FB17 ((uint32_t)0x00020000) #define CAN_F40R2_FB18 ((uint32_t)0x00040000) #define CAN_F40R2_FB19 ((uint32_t)0x00080000) #define CAN_F40R2_FB20 ((uint32_t)0x00100000) #define CAN_F40R2_FB21 ((uint32_t)0x00200000) #define CAN_F40R2_FB22 ((uint32_t)0x00400000) #define CAN_F40R2_FB23 ((uint32_t)0x00800000) #define CAN_F40R2_FB24 ((uint32_t)0x01000000) #define CAN_F40R2_FB25 ((uint32_t)0x02000000) #define CAN_F40R2_FB26 ((uint32_t)0x04000000) #define CAN_F40R2_FB27 ((uint32_t)0x08000000) #define CAN_F40R2_FB28 ((uint32_t)0x10000000) #define CAN_F40R2_FB29 ((uint32_t)0x20000000) #define CAN_F40R2_FB30 ((uint32_t)0x40000000) #define CAN_F40R2_FB31 ((uint32_t)0x80000000) /******************** Bit definition for CAN_F41R2 register ********************/ #define CAN_F41R2_FB0 ((uint32_t)0x00000001) #define CAN_F41R2_FB1 ((uint32_t)0x00000002) #define CAN_F41R2_FB2 ((uint32_t)0x00000004) #define CAN_F41R2_FB3 ((uint32_t)0x00000008) #define CAN_F41R2_FB4 ((uint32_t)0x00000010) #define CAN_F41R2_FB5 ((uint32_t)0x00000020) #define CAN_F41R2_FB6 ((uint32_t)0x00000040) #define CAN_F41R2_FB7 ((uint32_t)0x00000080) #define CAN_F41R2_FB8 ((uint32_t)0x00000100) #define CAN_F41R2_FB9 ((uint32_t)0x00000200) #define CAN_F41R2_FB10 ((uint32_t)0x00000400) #define CAN_F41R2_FB11 ((uint32_t)0x00000800) #define CAN_F41R2_FB12 ((uint32_t)0x00001000) #define CAN_F41R2_FB13 ((uint32_t)0x00002000) #define CAN_F41R2_FB14 ((uint32_t)0x00004000) #define CAN_F41R2_FB15 ((uint32_t)0x00008000) #define CAN_F41R2_FB16 ((uint32_t)0x00010000) #define CAN_F41R2_FB17 ((uint32_t)0x00020000) #define CAN_F41R2_FB18 ((uint32_t)0x00040000) #define CAN_F41R2_FB19 ((uint32_t)0x00080000) #define CAN_F41R2_FB20 ((uint32_t)0x00100000) #define CAN_F41R2_FB21 ((uint32_t)0x00200000) #define CAN_F41R2_FB22 ((uint32_t)0x00400000) #define CAN_F41R2_FB23 ((uint32_t)0x00800000) #define CAN_F41R2_FB24 ((uint32_t)0x01000000) #define CAN_F41R2_FB25 ((uint32_t)0x02000000) #define CAN_F41R2_FB26 ((uint32_t)0x04000000) #define CAN_F41R2_FB27 ((uint32_t)0x08000000) #define CAN_F41R2_FB28 ((uint32_t)0x10000000) #define CAN_F41R2_FB29 ((uint32_t)0x20000000) #define CAN_F41R2_FB30 ((uint32_t)0x40000000) #define CAN_F41R2_FB31 ((uint32_t)0x80000000) /******************************************************************************/ /* CRC Calculation Unit */ /******************************************************************************/ /******************* Bit definition for CRC_DATAR register *********************/ #define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ /******************* Bit definition for CRC_IDATAR register ********************/ #define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CTLR register ********************/ #define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ /******************************************************************************/ /* Digital to Analog Converter */ /******************************************************************************/ /******************** Bit definition for DAC_CTLR register ********************/ #define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ #define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ #define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ #define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ #define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ #define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ #define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ #define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ #define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ #define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ #define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ #define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ #define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ #define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ #define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ #define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ #define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ #define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ #define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ #define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ #define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ #define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ #define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ #define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ #define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ #define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ #define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ #define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ #define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ #define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ #define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ #define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ /***************** Bit definition for DAC_SWTR register ******************/ #define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ #define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ /***************** Bit definition for DAC_R12BDHR1 register ******************/ #define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_L12BDHR1 register ******************/ #define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_R8BDHR1 register ******************/ #define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_R12BDHR2 register ******************/ #define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_L12BDHR2 register ******************/ #define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_R8BDHR2 register ******************/ #define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ /***************** Bit definition for DAC_RD12BDHR register ******************/ #define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ #define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_LD12BDHR register ******************/ #define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ #define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_RD8BDHR register ******************/ #define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ #define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ #define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ /******************* Bit definition for DAC_DOR2 register *******************/ #define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ /******************************************************************************/ /* DMA Controller */ /******************************************************************************/ /******************* Bit definition for DMA_INTFR register ********************/ #define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ #define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ #define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ #define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ #define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ #define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ #define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ #define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ #define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ #define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ #define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ #define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ #define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ #define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ #define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ #define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ #define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ #define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ #define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ #define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ #define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ #define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ #define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ #define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ #define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ #define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ #define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ #define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ #define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ #define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ #define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ #define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ /******************* Bit definition for DMA_INTFCR register *******************/ #define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ #define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ #define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ #define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ #define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ #define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ #define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ #define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ #define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ #define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ #define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ #define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ #define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ #define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ #define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ #define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ #define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ #define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ #define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ #define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ #define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ #define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ #define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ #define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ #define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ #define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ #define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ #define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ #define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ #define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ #define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ #define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ /******************* Bit definition for DMA_CFGR1 register *******************/ #define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ #define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ #define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR2 register *******************/ #define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR3 register *******************/ #define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR4 register *******************/ #define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /****************** Bit definition for DMA_CFGR5 register *******************/ #define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CCFGR_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ /******************* Bit definition for DMA_CFGR6 register *******************/ #define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ /******************* Bit definition for DMA_CFGR7 register *******************/ #define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ /******************* Bit definition for DMA_CFGR8 register *******************/ #define DMA_CFGR8_EN ((uint16_t)0x0001) /* Channel enable */ #define DMA_CFGR8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ #define DMA_CFGR8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ #define DMA_CFGR8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ #define DMA_CFGR8_DIR ((uint16_t)0x0010) /* Data transfer direction */ #define DMA_CFGR8_CIRC ((uint16_t)0x0020) /* Circular mode */ #define DMA_CFGR8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ #define DMA_CFGR8_MINC ((uint16_t)0x0080) /* Memory increment mode */ #define DMA_CFGR8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ #define DMA_CFGR8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ #define DMA_CFGR8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ #define DMA_CFGR8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ #define DMA_CFGR8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ #define DMA_CFGR8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ #define DMA_CFGR8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ #define DMA_CFGR8_PL_0 ((uint16_t)0x1000) /* Bit 0 */ #define DMA_CFGR8_PL_1 ((uint16_t)0x2000) /* Bit 1 */ #define DMA_CFGR8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ /****************** Bit definition for DMA_CNTR1 register ******************/ #define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR2 register ******************/ #define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR3 register ******************/ #define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR4 register ******************/ #define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR5 register ******************/ #define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR6 register ******************/ #define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR7 register ******************/ #define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_CNTR8 register ******************/ #define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ /****************** Bit definition for DMA_PADDR1 register *******************/ #define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR2 register *******************/ #define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR3 register *******************/ #define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR4 register *******************/ #define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR5 register *******************/ #define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR6 register *******************/ #define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR7 register *******************/ #define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_PADDR8 register *******************/ #define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ /****************** Bit definition for DMA_MADDR1 register *******************/ #define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR2 register *******************/ #define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR3 register *******************/ #define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR4 register *******************/ #define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR5 register *******************/ #define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR6 register *******************/ #define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR7 register *******************/ #define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MADDR8 register *******************/ #define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR1 register *******************/ #define DMA_M1ADDR1_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR2 register *******************/ #define DMA_M1ADDR2_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR3 register *******************/ #define DMA_M1ADDR3_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR4 register *******************/ #define DMA_M1ADDR4_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR5 register *******************/ #define DMA_M1ADDR5_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR6 register *******************/ #define DMA_M1ADDR6_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR7 register *******************/ #define DMA_M1ADDR7_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_M1ADDR8 register *******************/ #define DMA_M1ADDR8_M1A ((uint32_t)0xFFFFFFFF) /* Memory Address */ /****************** Bit definition for DMA_MUX0_3_CFGR register *******************/ #define DMA_MUX_CH0 ((uint32_t)0x0000007F) #define DMA_MUX_CH1 ((uint32_t)0x00007F00) #define DMA_MUX_CH2 ((uint32_t)0x007F0000) #define DMA_MUX_CH3 ((uint32_t)0x7F000000) /****************** Bit definition for DMA_MUX4_7_CFGR register *******************/ #define DMA_MUX_CH4 ((uint32_t)0x0000007F) #define DMA_MUX_CH5 ((uint32_t)0x00007F00) #define DMA_MUX_CH6 ((uint32_t)0x007F0000) #define DMA_MUX_CH7 ((uint32_t)0x7F000000) /****************** Bit definition for DMA_MUX8_11_CFGR register *******************/ #define DMA_MUX_CH8 ((uint32_t)0x0000007F) #define DMA_MUX_CH9 ((uint32_t)0x00007F00) #define DMA_MUX_CH10 ((uint32_t)0x007F0000) #define DMA_MUX_CH11 ((uint32_t)0x7F000000) /****************** Bit definition for DMA_MUX12_15_CFGR register *******************/ #define DMA_MUX_CH12 ((uint32_t)0x0000007F) #define DMA_MUX_CH13 ((uint32_t)0x00007F00) #define DMA_MUX_CH14 ((uint32_t)0x007F0000) #define DMA_MUX_CH15 ((uint32_t)0x7F000000) /******************************************************************************/ /* External Interrupt/Event Controller */ /******************************************************************************/ /******************* Bit definition for EXTI_INTENR register *******************/ #define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ #define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ #define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ #define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ #define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ #define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ #define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ #define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ #define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ #define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ #define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ #define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ #define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ #define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ #define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ #define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ #define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ #define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ #define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ #define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ #define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ #define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ #define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ #define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */ #define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */ #define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */ /******************* Bit definition for EXTI_EVENR register *******************/ #define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ #define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ #define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ #define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ #define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ #define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ #define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ #define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ #define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ #define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ #define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ #define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ #define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ #define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ #define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ #define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ #define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ #define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ #define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ #define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ #define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ #define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ #define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ #define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */ #define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */ #define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */ /****************** Bit definition for EXTI_RTENR register *******************/ #define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ #define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ #define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ #define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ #define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ #define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ #define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ #define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ #define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ #define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ #define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ #define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ #define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ #define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ #define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ #define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ #define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ #define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ #define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ #define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ #define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ #define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ #define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ #define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */ #define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */ #define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */ /****************** Bit definition for EXTI_FTENR register *******************/ #define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ #define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ #define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ #define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ #define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ #define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ #define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ #define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ #define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ #define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ #define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ #define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ #define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ #define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ #define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ #define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ #define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ #define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ #define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ #define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ #define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ #define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ #define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ #define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */ #define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */ #define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */ /****************** Bit definition for EXTI_SWIEVR register ******************/ #define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ #define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ #define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ #define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ #define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ #define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ #define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ #define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ #define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ #define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ #define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ #define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ #define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ #define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ #define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ #define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ #define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ #define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ #define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ #define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ #define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ #define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ #define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ #define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */ #define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */ #define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */ /******************* Bit definition for EXTI_INTFR register ********************/ #define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ #define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ #define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ #define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ #define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ #define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ #define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ #define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ #define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ #define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ #define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ #define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ #define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ #define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ #define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ #define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ #define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ #define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ #define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ #define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ #define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ #define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ #define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ #define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */ #define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */ #define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */ /******************************************************************************/ /* FLASH and Option Bytes Registers */ /******************************************************************************/ /******************* Bit definition for FLASH_ACTLR register ******************/ /****************** Bit definition for FLASH_ACTLR register ******************/ #define FLASH_ACTLR_SCK_CFG ((uint32_t)0x00000003) #define FLASH_ACTLR_SCK_CFG_0 ((uint32_t)0x00000001) #define FLASH_ACTLR_SCK_CFG_1 ((uint32_t)0x00000002) #define FLASH_ACTLR_LATENCY_HCLK_DIV1 ((uint32_t)0x00000000) #define FLASH_ACTLR_LATENCY_HCLK_DIV2 ((uint32_t)0x00000001) #define FLASH_ACTLR_LATENCY_HCLK_DIV4 ((uint32_t)0x00000002) #define FLASH_ACTLR_ENHANCE_STATUS ((uint32_t)0x00000040) #define FLASH_ACTLR_EHMOD ((uint32_t)0x00000080) #define FLASH_ACTLR_LP ((uint32_t)0x00000100) #define FLASH_ACTLR_RD_MD ((uint32_t)0x00000800) #define FLASH_ACTLR_READY ((uint32_t)0x00004000) #define FLASH_ACTLR_ST ((uint32_t)0x00008000) /****************** Bit definition for FLASH_KEYR register ******************/ #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ #define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) #define FLASH_KEYR_KEY2 ((uint32_t)0xCDEF89AB) /***************** Bit definition for FLASH_OBKEYR register ****************/ #define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ /****************** Bit definition for FLASH_STATR register *******************/ #define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ #define FLASH_STATR_WRBSY ((uint8_t)0x02) #define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ #define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ #define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) #define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) #define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) #define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /******************* Bit definition for FLASH_CTLR register *******************/ #define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ #define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ #define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ #define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ #define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ #define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ #define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ #define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ #define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ #define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ #define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ #define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ #define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ #define FLASH_CTLR_RSENACT ((uint32_t)0x00400000) /******************* Bit definition for FLASH_ADDR register *******************/ #define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ /****************** Bit definition for FLASH_OBR register *******************/ #define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ #define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ #define FLASH_OBR_USER ((uint16_t)0x0304) /* User Option Bytes */ #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ #define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* nRST_STOP */ #define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) #define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /****************** Bit definition for FLASH_WPR register ******************/ #define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ /****************** Bit definition for FLASH_MODEKEYR register ******************/ #define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) #define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) /****************** Bit definition for FLASH_RDPR register *******************/ #define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ #define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ /****************** Bit definition for FLASH_USER register ******************/ #define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ /****************** Bit definition for FLASH_Data0 register *****************/ #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ /****************** Bit definition for FLASH_Data1 register *****************/ #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ /****************** Bit definition for FLASH_WRPR0 register ******************/ #define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ #define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ /****************** Bit definition for FLASH_WRPR1 register ******************/ #define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ #define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ /****************** Bit definition for FLASH_WRPR2 register ******************/ #define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ #define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ /****************** Bit definition for FLASH_WRPR3 register ******************/ #define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ #define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ /******************************************************************************/ /* General Purpose and Alternate Function I/O */ /******************************************************************************/ /******************* Bit definition for GPIO_CFGLR register *******************/ #define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ #define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ #define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ #define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ #define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ #define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ #define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ #define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ #define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ #define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ #define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ #define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ #define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ #define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ #define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ #define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ #define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ #define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ #define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ #define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ #define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ #define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ #define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ #define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ #define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ #define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ #define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ #define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ #define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ #define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ #define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ #define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ #define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ #define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ /******************* Bit definition for GPIO_CFGHR register *******************/ #define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ #define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ #define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ #define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ #define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ #define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ #define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ #define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ #define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ #define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ #define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ #define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ #define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ #define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ #define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ #define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ #define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ #define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ #define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ #define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ #define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ #define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ #define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ #define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ #define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ #define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ #define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ #define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ #define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ #define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ #define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ #define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ #define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ #define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ /******************* Bit definition for GPIO_INDR register *******************/ #define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ #define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ #define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ #define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ #define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ #define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ #define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ #define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ #define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ #define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ #define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ #define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ #define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ #define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ #define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ #define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ /******************* Bit definition for GPIO_OUTDR register *******************/ #define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ #define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ #define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ #define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ #define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ #define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ #define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ #define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ #define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ #define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ #define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ #define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ #define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ #define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ #define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ #define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ /****************** Bit definition for GPIO_BSHR register *******************/ #define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ #define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ #define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ #define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ #define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ #define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ #define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ #define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ #define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ #define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ #define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ #define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ #define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ #define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ #define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ #define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ #define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ #define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ #define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ #define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ #define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ #define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ #define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ #define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ #define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ #define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ #define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ #define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ #define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ #define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ #define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ #define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ /******************* Bit definition for GPIO_BCR register *******************/ #define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ #define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ #define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ #define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ #define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ #define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ #define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ #define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ #define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ #define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ #define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ #define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ #define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ #define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ #define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ #define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ /****************** Bit definition for GPIO_LCKR register *******************/ #define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ #define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ #define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ #define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ #define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ #define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ #define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ #define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ #define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ #define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ #define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ #define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ #define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ #define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ #define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ #define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ #define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ /****************** Bit definition for AFIO_PCFR1 register ******************/ #define AFIO_PCFR1_PD0_1_REMAP ((uint32_t)0x00000001) #define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00000002) #define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00000004) #define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00000008) #define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00000010) #define AFIO_PCFR1_UHSIF_CLK_REMAP ((uint32_t)0x000000C0) #define AFIO_PCFR1_UHSIF_CLK_REMAP_0 ((uint32_t)0x00000040) #define AFIO_PCFR1_UHSIF_CLK_REMAP_1 ((uint32_t)0x00000080) #define AFIO_PCFR1_UHSIF_PORT_REMAP ((uint32_t)0x00000300) #define AFIO_PCFR1_UHSIF_PORT_REMAP_0 ((uint32_t)0x00000100) #define AFIO_PCFR1_UHSIF_PORT_REMAP_1 ((uint32_t)0x00000200) #define AFIO_PCFR1_SDMMC_REMAP ((uint32_t)0x00000C00) #define AFIO_PCFR1_SDMMC_REMAP_0 ((uint32_t)0x00000400) #define AFIO_PCFR1_SDMMC_REMAP_1 ((uint32_t)0x00000800) #define AFIO_PCFR1_TIM2ITR1_REMAP ((uint32_t)0x00001000) #define AFIO_PCFR1_VIO18_IO_HSLV ((uint32_t)0x00010000) #define AFIO_PCFR1_VIO33_IO_HSLV ((uint32_t)0x00020000) #define AFIO_PCFR1_VDD33_IO_HSLV ((uint32_t)0x00040000) #define AFIO_PCFR1_USBPD_CC_HVT ((uint32_t)0x00100000) #define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ #define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ #define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ /****************** Bit definition for AFIO_AFLR register *******************/ #define AFIO_AFLR_AFR0 ((uint32_t)0x0000000F) #define AFIO_AFLR_AFR0_0 ((uint32_t)0x00000001) #define AFIO_AFLR_AFR0_1 ((uint32_t)0x00000002) #define AFIO_AFLR_AFR0_2 ((uint32_t)0x00000004) #define AFIO_AFLR_AFR0_3 ((uint32_t)0x00000008) #define AFIO_AFLR_AFR1 ((uint32_t)0x000000F0) #define AFIO_AFLR_AFR1_0 ((uint32_t)0x00000010) #define AFIO_AFLR_AFR1_1 ((uint32_t)0x00000020) #define AFIO_AFLR_AFR1_2 ((uint32_t)0x00000040) #define AFIO_AFLR_AFR1_3 ((uint32_t)0x00000080) #define AFIO_AFLR_AFR2 ((uint32_t)0x00000F00) #define AFIO_AFLR_AFR2_0 ((uint32_t)0x00000100) #define AFIO_AFLR_AFR2_1 ((uint32_t)0x00000200) #define AFIO_AFLR_AFR2_2 ((uint32_t)0x00000400) #define AFIO_AFLR_AFR2_3 ((uint32_t)0x00000800) #define AFIO_AFLR_AFR3 ((uint32_t)0x0000F000) #define AFIO_AFLR_AFR3_0 ((uint32_t)0x00001000) #define AFIO_AFLR_AFR3_1 ((uint32_t)0x00002000) #define AFIO_AFLR_AFR3_2 ((uint32_t)0x00004000) #define AFIO_AFLR_AFR3_3 ((uint32_t)0x00008000) #define AFIO_AFLR_AFR4 ((uint32_t)0x000F0000) #define AFIO_AFLR_AFR4_0 ((uint32_t)0x00010000) #define AFIO_AFLR_AFR4_1 ((uint32_t)0x00020000) #define AFIO_AFLR_AFR4_2 ((uint32_t)0x00040000) #define AFIO_AFLR_AFR4_3 ((uint32_t)0x00080000) #define AFIO_AFLR_AFR5 ((uint32_t)0x00F00000) #define AFIO_AFLR_AFR5_0 ((uint32_t)0x00100000) #define AFIO_AFLR_AFR5_1 ((uint32_t)0x00200000) #define AFIO_AFLR_AFR5_2 ((uint32_t)0x00400000) #define AFIO_AFLR_AFR5_3 ((uint32_t)0x00800000) #define AFIO_AFLR_AFR6 ((uint32_t)0x0F000000) #define AFIO_AFLR_AFR6_0 ((uint32_t)0x01000000) #define AFIO_AFLR_AFR6_1 ((uint32_t)0x02000000) #define AFIO_AFLR_AFR6_2 ((uint32_t)0x04000000) #define AFIO_AFLR_AFR6_3 ((uint32_t)0x08000000) #define AFIO_AFLR_AFR7 ((uint32_t)0xF0000000) #define AFIO_AFLR_AFR7_0 ((uint32_t)0x10000000) #define AFIO_AFLR_AFR7_1 ((uint32_t)0x20000000) #define AFIO_AFLR_AFR7_2 ((uint32_t)0x40000000) #define AFIO_AFLR_AFR7_3 ((uint32_t)0x80000000) /****************** Bit definition for AFIO_AFHR register *******************/ #define AFIO_AFHR_AFR8 ((uint32_t)0x0000000F) #define AFIO_AFHR_AFR8_0 ((uint32_t)0x00000001) #define AFIO_AFHR_AFR8_1 ((uint32_t)0x00000002) #define AFIO_AFHR_AFR8_2 ((uint32_t)0x00000004) #define AFIO_AFHR_AFR8_3 ((uint32_t)0x00000008) #define AFIO_AFHR_AFR9 ((uint32_t)0x000000F0) #define AFIO_AFHR_AFR9_0 ((uint32_t)0x00000010) #define AFIO_AFHR_AFR9_1 ((uint32_t)0x00000020) #define AFIO_AFHR_AFR9_2 ((uint32_t)0x00000040) #define AFIO_AFHR_AFR9_3 ((uint32_t)0x00000080) #define AFIO_AFHR_AFR10 ((uint32_t)0x00000F00) #define AFIO_AFHR_AFR10_0 ((uint32_t)0x00000100) #define AFIO_AFHR_AFR10_1 ((uint32_t)0x00000200) #define AFIO_AFHR_AFR10_2 ((uint32_t)0x00000400) #define AFIO_AFHR_AFR10_3 ((uint32_t)0x00000800) #define AFIO_AFHR_AFR11 ((uint32_t)0x0000F000) #define AFIO_AFHR_AFR11_0 ((uint32_t)0x00001000) #define AFIO_AFHR_AFR11_1 ((uint32_t)0x00002000) #define AFIO_AFHR_AFR11_2 ((uint32_t)0x00004000) #define AFIO_AFHR_AFR11_3 ((uint32_t)0x00008000) #define AFIO_AFHR_AFR12 ((uint32_t)0x000F0000) #define AFIO_AFHR_AFR12_0 ((uint32_t)0x00010000) #define AFIO_AFHR_AFR12_1 ((uint32_t)0x00020000) #define AFIO_AFHR_AFR12_2 ((uint32_t)0x00040000) #define AFIO_AFHR_AFR12_3 ((uint32_t)0x00080000) #define AFIO_AFHR_AFR13 ((uint32_t)0x00F00000) #define AFIO_AFHR_AFR13_0 ((uint32_t)0x00100000) #define AFIO_AFHR_AFR13_1 ((uint32_t)0x00200000) #define AFIO_AFHR_AFR13_2 ((uint32_t)0x00400000) #define AFIO_AFHR_AFR13_3 ((uint32_t)0x00800000) #define AFIO_AFHR_AFR14 ((uint32_t)0x0F000000) #define AFIO_AFHR_AFR14_0 ((uint32_t)0x01000000) #define AFIO_AFHR_AFR14_1 ((uint32_t)0x02000000) #define AFIO_AFHR_AFR14_2 ((uint32_t)0x04000000) #define AFIO_AFHR_AFR14_3 ((uint32_t)0x08000000) #define AFIO_AFHR_AFR15 ((uint32_t)0xF0000000) #define AFIO_AFHR_AFR15_0 ((uint32_t)0x10000000) #define AFIO_AFHR_AFR15_1 ((uint32_t)0x20000000) #define AFIO_AFHR_AFR15_2 ((uint32_t)0x40000000) #define AFIO_AFHR_AFR15_3 ((uint32_t)0x80000000) /****************** Bit definition for AFIO_EXTICR1 register *******************/ #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /* EXTI 0 configuration */ #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /* EXTI 1 configuration */ #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /* EXTI 2 configuration */ #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /* EXTI 3 configuration */ #define AFIO_EXTICR1_EXTI4 ((uint32_t)0x000F0000) /* EXTI 4 configuration */ #define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00F00000) /* EXTI 5 configuration */ #define AFIO_EXTICR1_EXTI6 ((uint32_t)0x0F000000) /* EXTI 6 configuration */ #define AFIO_EXTICR1_EXTI7 ((uint32_t)0xF0000000) /* EXTI 7 configuration */ #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /* PD[0] pin */ #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /* PE[0] pin */ #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /* PF[0] pin */ #define AFIO_EXTICR1_EXTI0_CMPOUT ((uint32_t)0x00000006) /* CMP OUT */ #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /* PB[1] pin */ #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /* PC[1] pin */ #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /* PD[1] pin */ #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /* PE[1] pin */ #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /* PF[1] pin */ #define AFIO_EXTICR1_EXTI1_CMPOUT ((uint32_t)0x00000060) /* CMP OUT */ #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /* PB[2] pin */ #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /* PC[2] pin */ #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /* PD[2] pin */ #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /* PE[2] pin */ #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /* PF[2] pin */ #define AFIO_EXTICR1_EXTI2_CMPOUT ((uint32_t)0x00000600) /* CMP OUT */ #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /* PB[3] pin */ #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /* PC[3] pin */ #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /* PD[3] pin */ #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /* PE[3] pin */ #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /* PF[3] pin */ #define AFIO_EXTICR1_EXTI3_CMPOUT ((uint32_t)0x00006000) /* CMP OUT */ #define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ #define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00010000) /* PB[4] pin */ #define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00020000) /* PC[4] pin */ #define AFIO_EXTICR1_EXTI4_PD ((uint32_t)0x00030000) /* PD[4] pin */ #define AFIO_EXTICR1_EXTI4_PE ((uint32_t)0x00040000) /* PE[4] pin */ #define AFIO_EXTICR1_EXTI4_PF ((uint32_t)0x00050000) /* PF[4] pin */ #define AFIO_EXTICR1_EXTI4_CMPOUT ((uint32_t)0x00060000) /* CMP OUT */ #define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ #define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00100000) /* PB[5] pin */ #define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00200000) /* PC[5] pin */ #define AFIO_EXTICR1_EXTI5_PD ((uint32_t)0x00300000) /* PD[5] pin */ #define AFIO_EXTICR1_EXTI5_PE ((uint32_t)0x00400000) /* PE[5] pin */ #define AFIO_EXTICR1_EXTI5_PF ((uint32_t)0x00500000) /* PF[5] pin */ #define AFIO_EXTICR1_EXTI5_CMPOUT ((uint32_t)0x00600000) /* CMP OUT */ #define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ #define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x01000000) /* PB[6] pin */ #define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x02000000) /* PC[6] pin */ #define AFIO_EXTICR1_EXTI6_PD ((uint32_t)0x03000000) /* PD[6] pin */ #define AFIO_EXTICR1_EXTI6_PE ((uint32_t)0x04000000) /* PE[6] pin */ #define AFIO_EXTICR1_EXTI6_PF ((uint32_t)0x05000000) /* PF[6] pin */ #define AFIO_EXTICR1_EXTI6_CMPOUT ((uint32_t)0x06000000) /* CMP OUT */ #define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ #define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x10000000) /* PB[7] pin */ #define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x20000000) /* PC[7] pin */ #define AFIO_EXTICR1_EXTI7_PD ((uint32_t)0x30000000) /* PD[7] pin */ #define AFIO_EXTICR1_EXTI7_PE ((uint32_t)0x40000000) /* PE[7] pin */ #define AFIO_EXTICR1_EXTI7_PF ((uint32_t)0x50000000) /* PF[7] pin */ #define AFIO_EXTICR1_EXTI7_CMPOUT ((uint32_t)0x60000000) /* CMP OUT */ /****************** Bit definition for AFIO_EXTICR2 register *******************/ #define AFIO_EXTICR2_EXTI8 ((uint32_t)0x0000000F) /* EXTI 0 configuration */ #define AFIO_EXTICR2_EXTI9 ((uint32_t)0x000000F0) /* EXTI 1 configuration */ #define AFIO_EXTICR2_EXTI10 ((uint32_t)0x00000F00) /* EXTI 2 configuration */ #define AFIO_EXTICR2_EXTI11 ((uint32_t)0x0000F000) /* EXTI 3 configuration */ #define AFIO_EXTICR2_EXTI12 ((uint32_t)0x000F0000) /* EXTI 4 configuration */ #define AFIO_EXTICR2_EXTI13 ((uint32_t)0x00F00000) /* EXTI 5 configuration */ #define AFIO_EXTICR2_EXTI14 ((uint32_t)0x0F000000) /* EXTI 6 configuration */ #define AFIO_EXTICR2_EXTI15 ((uint32_t)0xF0000000) /* EXTI 7 configuration */ #define AFIO_EXTICR2_EXTI8_PA ((uint32_t)0x00000000) /* PA[0] pin */ #define AFIO_EXTICR2_EXTI8_PB ((uint32_t)0x00000001) /* PB[0] pin */ #define AFIO_EXTICR2_EXTI8_PC ((uint32_t)0x00000002) /* PC[0] pin */ #define AFIO_EXTICR2_EXTI8_PD ((uint32_t)0x00000003) /* PD[0] pin */ #define AFIO_EXTICR2_EXTI8_PE ((uint32_t)0x00000004) /* PE[0] pin */ #define AFIO_EXTICR2_EXTI8_PF ((uint32_t)0x00000005) /* PF[0] pin */ #define AFIO_EXTICR2_EXTI8_CMPOUT ((uint32_t)0x00000006) /* CMP OUT */ #define AFIO_EXTICR2_EXTI9_PA ((uint32_t)0x00000000) /* PA[1] pin */ #define AFIO_EXTICR2_EXTI9_PB ((uint32_t)0x00000010) /* PB[1] pin */ #define AFIO_EXTICR2_EXTI9_PC ((uint32_t)0x00000020) /* PC[1] pin */ #define AFIO_EXTICR2_EXTI9_PD ((uint32_t)0x00000030) /* PD[1] pin */ #define AFIO_EXTICR2_EXTI9_PE ((uint32_t)0x00000040) /* PE[1] pin */ #define AFIO_EXTICR2_EXTI9_PF ((uint32_t)0x00000050) /* PF[1] pin */ #define AFIO_EXTICR2_EXTI9_CMPOUT ((uint32_t)0x00000060) /* CMP OUT */ #define AFIO_EXTICR2_EXTI10_PA ((uint32_t)0x00000000) /* PA[2] pin */ #define AFIO_EXTICR2_EXTI10_PB ((uint32_t)0x00000100) /* PB[2] pin */ #define AFIO_EXTICR2_EXTI10_PC ((uint32_t)0x00000200) /* PC[2] pin */ #define AFIO_EXTICR2_EXTI10_PD ((uint32_t)0x00000300) /* PD[2] pin */ #define AFIO_EXTICR2_EXTI10_PE ((uint32_t)0x00000400) /* PE[2] pin */ #define AFIO_EXTICR2_EXTI10_PF ((uint32_t)0x00000500) /* PF[2] pin */ #define AFIO_EXTICR2_EXTI10_CMPOUT ((uint32_t)0x00000600) /* CMP OUT */ #define AFIO_EXTICR2_EXTI11_PA ((uint32_t)0x00000000) /* PA[3] pin */ #define AFIO_EXTICR2_EXTI11_PB ((uint32_t)0x00001000) /* PB[3] pin */ #define AFIO_EXTICR2_EXTI11_PC ((uint32_t)0x00002000) /* PC[3] pin */ #define AFIO_EXTICR2_EXTI11_PD ((uint32_t)0x00003000) /* PD[3] pin */ #define AFIO_EXTICR2_EXTI11_PE ((uint32_t)0x00004000) /* PE[3] pin */ #define AFIO_EXTICR2_EXTI11_PF ((uint32_t)0x00005000) /* PF[3] pin */ #define AFIO_EXTICR2_EXTI11_CMPOUT ((uint32_t)0x00006000) /* CMP OUT */ #define AFIO_EXTICR2_EXTI12_PA ((uint32_t)0x00000000) /* PA[4] pin */ #define AFIO_EXTICR2_EXTI12_PB ((uint32_t)0x00010000) /* PB[4] pin */ #define AFIO_EXTICR2_EXTI12_PC ((uint32_t)0x00020000) /* PC[4] pin */ #define AFIO_EXTICR2_EXTI12_PD ((uint32_t)0x00030000) /* PD[4] pin */ #define AFIO_EXTICR2_EXTI12_PE ((uint32_t)0x00040000) /* PE[4] pin */ #define AFIO_EXTICR2_EXTI12_PF ((uint32_t)0x00050000) /* PF[4] pin */ #define AFIO_EXTICR2_EXTI12_CMPOUT ((uint32_t)0x00060000) /* CMP OUT */ #define AFIO_EXTICR2_EXTI13_PA ((uint32_t)0x00000000) /* PA[5] pin */ #define AFIO_EXTICR2_EXTI13_PB ((uint32_t)0x00100000) /* PB[5] pin */ #define AFIO_EXTICR2_EXTI13_PC ((uint32_t)0x00200000) /* PC[5] pin */ #define AFIO_EXTICR2_EXTI13_PD ((uint32_t)0x00300000) /* PD[5] pin */ #define AFIO_EXTICR2_EXTI13_PE ((uint32_t)0x00400000) /* PE[5] pin */ #define AFIO_EXTICR2_EXTI13_PF ((uint32_t)0x00500000) /* PF[5] pin */ #define AFIO_EXTICR2_EXTI13_CMPOUT ((uint32_t)0x00600000) /* CMP OUT */ #define AFIO_EXTICR2_EXTI14_PA ((uint32_t)0x00000000) /* PA[6] pin */ #define AFIO_EXTICR2_EXTI14_PB ((uint32_t)0x01000000) /* PB[6] pin */ #define AFIO_EXTICR2_EXTI14_PC ((uint32_t)0x02000000) /* PC[6] pin */ #define AFIO_EXTICR2_EXTI14_PD ((uint32_t)0x03000000) /* PD[6] pin */ #define AFIO_EXTICR2_EXTI14_PE ((uint32_t)0x04000000) /* PE[6] pin */ #define AFIO_EXTICR2_EXTI14_PF ((uint32_t)0x05000000) /* PF[6] pin */ #define AFIO_EXTICR2_EXTI14_CMPOUT ((uint32_t)0x06000000) /* CMP OUT */ #define AFIO_EXTICR2_EXTI15_PA ((uint32_t)0x00000000) /* PA[7] pin */ #define AFIO_EXTICR2_EXTI15_PB ((uint32_t)0x10000000) /* PB[7] pin */ #define AFIO_EXTICR2_EXTI15_PC ((uint32_t)0x20000000) /* PC[7] pin */ #define AFIO_EXTICR2_EXTI15_PD ((uint32_t)0x30000000) /* PD[7] pin */ #define AFIO_EXTICR2_EXTI15_PE ((uint32_t)0x40000000) /* PE[7] pin */ #define AFIO_EXTICR2_EXTI15_PF ((uint32_t)0x50000000) /* PF[7] pin */ #define AFIO_EXTICR2_EXTI15_CMPOUT ((uint32_t)0x60000000) /* CMP OUT */ /******************************************************************************/ /* Independent WATCHDOG */ /******************************************************************************/ /******************* Bit definition for IWDG_CTLR register ********************/ #define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PSCR register ********************/ #define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ #define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ #define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ #define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ /******************* Bit definition for IWDG_RLDR register *******************/ #define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ /******************* Bit definition for IWDG_STATR register ********************/ #define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ #define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ /******************************************************************************/ /* Inter-integrated Circuit Interface */ /******************************************************************************/ /******************* Bit definition for I2C_CTLR1 register ********************/ #define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ #define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ #define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ #define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ #define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ #define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ #define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ #define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ #define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ #define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ #define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ #define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ #define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ #define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ /******************* Bit definition for I2C_CTLR2 register ********************/ #define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ #define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ #define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ #define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ #define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ #define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ #define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ #define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ #define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ #define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ #define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ #define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ /******************* Bit definition for I2C_OADDR1 register *******************/ #define I2C_OADDR1_ADD0 ((uint16_t)0x0001) #define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ #define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ #define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ #define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ #define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ #define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ #define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ #define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ #define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ #define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ #define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ #define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ #define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ /******************* Bit definition for I2C_OADDR2 register *******************/ #define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ #define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ /******************** Bit definition for I2C_DATAR register ********************/ #define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ /******************* Bit definition for I2C_STAR1 register ********************/ #define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ #define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ #define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ #define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ #define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ #define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ #define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ #define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ #define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ #define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ #define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ #define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ #define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ #define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ /******************* Bit definition for I2C_STAR2 register ********************/ #define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ #define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ #define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ #define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ #define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ #define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ #define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ #define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ /******************* Bit definition for I2C_CKCFGR register ********************/ #define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ #define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ #define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ /****************** Bit definition for I2C_RTR register *******************/ #define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ /******************************************************************************/ /* Improved Inter-integrated Circuit Interface */ /******************************************************************************/ /******************* Bit definition for I3C_CTLR register ********************/ #define I3C_CTLR_DCNT ((uint32_t)0x0000FFFF) #define I3C_CTLR_RNW ((uint32_t)0x00010000) #define I3C_CTLR_ADD ((uint32_t)0x00FE0000) #define I3C_CTLR_CCC ((uint32_t)0x00FF0000) #define I3C_CTLR_MTYPE ((uint32_t)0x78000000) #define I3C_CTLR_MTYPE_0 ((uint32_t)0x08000000) #define I3C_CTLR_MTYPE_1 ((uint32_t)0x10000000) #define I3C_CTLR_MTYPE_2 ((uint32_t)0x20000000) #define I3C_CTLR_MTYPE_3 ((uint32_t)0x40000000) #define I3C_CTLR_MEND ((uint32_t)0x80000000) /******************* Bit definition for I3C_CFGR register ********************/ #define I3C_CFGR_EN ((uint32_t)0x00000001) #define I3C_CFGR_CRINIT ((uint32_t)0x00000002) #define I3C_CFGR_NOARBH ((uint32_t)0x00000004) #define I3C_CFGR_RSTPTRN ((uint32_t)0x00000008) #define I3C_CFGR_EXITPTRN ((uint32_t)0x00000010) #define I3C_CFGR_HJACK ((uint32_t)0x00000080) #define I3C_CFGR_RXDMAEN ((uint32_t)0x00000100) #define I3C_CFGR_RXFLUSH ((uint32_t)0x00000200) #define I3C_CFGR_RXTHRES ((uint32_t)0x00000400) #define I3C_CFGR_TXMAEN ((uint32_t)0x00001000) #define I3C_CFGR_TXFLUSH ((uint32_t)0x00002000) #define I3C_CFGR_TXTHRES ((uint32_t)0x00004000) #define I3C_CFGR_SDMAEN ((uint32_t)0x00010000) #define I3C_CFGR_SFLUSH ((uint32_t)0x00020000) #define I3C_CFGR_SMODE ((uint32_t)0x00040000) #define I3C_CFGR_TMODE ((uint32_t)0x00080000) #define I3C_CFGR_CDMAEN ((uint32_t)0x00010000) #define I3C_CFGR_CFLUSH ((uint32_t)0x00020000) #define I3C_CFGR_TSFSET ((uint32_t)0x40000000) /******************* Bit definition for I3C_RDR register ********************/ #define I3C_RDR_RDB0 ((uint32_t)0x000000FF) /******************* Bit definition for I3C_RDWR register ********************/ #define I3C_RDWR_RDB0 ((uint32_t)0x000000FF) #define I3C_RDWR_RDB1 ((uint32_t)0x0000FF00) #define I3C_RDWR_RDB2 ((uint32_t)0x00FF0000) #define I3C_RDWR_RDB3 ((uint32_t)0xFF000000) /******************* Bit definition for I3C_TDR register ********************/ #define I3C_TDR_TDB0 ((uint32_t)0x000000FF) /******************* Bit definition for I3C_TDWR register ********************/ #define I3C_TDWR_TDB0 ((uint32_t)0x000000FF) #define I3C_TDWR_TDB1 ((uint32_t)0x0000FF00) #define I3C_TDWR_TDB2 ((uint32_t)0x00FF0000) #define I3C_TDWR_TDB3 ((uint32_t)0xFF000000) /******************* Bit definition for I3C_IBIDR register ********************/ #define I3C_IBIDR_IBIDB0 ((uint32_t)0x000000FF) #define I3C_IBIDR_IBIDB1 ((uint32_t)0x0000FF00) #define I3C_IBIDR_IBIDB2 ((uint32_t)0x00FF0000) #define I3C_IBIDR_IBIDB3 ((uint32_t)0xFF000000) /******************* Bit definition for I3C_TGTTDR register ********************/ #define I3C_TGTTDR_TGTTDCNT ((uint32_t)0x0000FFFF) #define I3C_TGTTDR_PRELOAD ((uint32_t)0x00010000) /******************* Bit definition for I3C_RESET register ********************/ #define I3C_RESET_HST_SIE_RST ((uint32_t)0x01000000) #define I3C_RESET_TGT_SIE_RST ((uint32_t)0x02000000) /******************* Bit definition for I3C_STATR register ********************/ #define I3C_STATR_XDCNT ((uint32_t)0x0000FFFF) #define I3C_STATR_ABT ((uint32_t)0x00020000) #define I3C_STATR_DIR ((uint32_t)0x00040000) #define I3C_STATR_MID ((uint32_t)0xFF000000) /******************* Bit definition for I3C_STATER register ********************/ #define I3C_STATER_CODERR ((uint32_t)0x0000000F) #define I3C_STATER_PERR ((uint32_t)0x00000010) #define I3C_STATER_STALL ((uint32_t)0x00000020) #define I3C_STATER_DOVR ((uint32_t)0x00000040) #define I3C_STATER_COVR ((uint32_t)0x00000080) #define I3C_STATER_ANACK ((uint32_t)0x00000100) #define I3C_STATER_DNACK ((uint32_t)0x00000200) #define I3C_STATER_DERR ((uint32_t)0x00000400) /******************* Bit definition for I3C_RMR register ********************/ #define I3C_RMR_IBIRDCNT ((uint32_t)0x00000007) #define I3C_RMR_RCODE ((uint32_t)0x0000FF00) #define I3C_RMR_RADD ((uint32_t)0x00FE0000) /******************* Bit definition for I3C_EVR register ********************/ #define I3C_EVR_CFEF ((uint32_t)0x00000001) #define I3C_EVR_TXFEF ((uint32_t)0x00000002) #define I3C_EVR_CFNFF ((uint32_t)0x00000004) #define I3C_EVR_SFNEF ((uint32_t)0x00000008) #define I3C_EVR_TXFNFF ((uint32_t)0x00000010) #define I3C_EVR_RXFNEF ((uint32_t)0x00000020) #define I3C_EVR_TXLASTF ((uint32_t)0x00000040) #define I3C_EVR_RXLASTF ((uint32_t)0x00000080) #define I3C_EVR_FCF ((uint32_t)0x00000200) #define I3C_EVR_RXTGTENDF ((uint32_t)0x00000400) #define I3C_EVR_ERRF ((uint32_t)0x00000800) #define I3C_EVR_IBIF ((uint32_t)0x00008000) #define I3C_EVR_IBIENDF ((uint32_t)0x00010000) #define I3C_EVR_CRF ((uint32_t)0x00020000) #define I3C_EVR_CRUPDF ((uint32_t)0x00040000) #define I3C_EVR_HJF ((uint32_t)0x00080000) #define I3C_EVR_WKPF ((uint32_t)0x00200000) #define I3C_EVR_GETF ((uint32_t)0x00400000) #define I3C_EVR_STAF ((uint32_t)0x00800000) #define I3C_EVR_DAUPDF ((uint32_t)0x01000000) #define I3C_EVR_MWLUPDF ((uint32_t)0x02000000) #define I3C_EVR_MRLUPDF ((uint32_t)0x04000000) #define I3C_EVR_RSTF ((uint32_t)0x08000000) #define I3C_EVR_ASUPDF ((uint32_t)0x10000000) #define I3C_EVR_INTUPDF ((uint32_t)0x20000000) #define I3C_EVR_DEFF ((uint32_t)0x40000000) #define I3C_EVR_GRPF ((uint32_t)0x80000000) /***************** Bit definition for I3C_INTENR register ******************/ #define I3C_INTENR_CFNFIE ((uint32_t)0x00000004) #define I3C_INTENR_SFNEIE ((uint32_t)0x00000008) #define I3C_INTENR_TXFNEIE ((uint32_t)0x00000010) #define I3C_INTENR_RXFNEIE ((uint32_t)0x00000020) #define I3C_INTENR_FCIE ((uint32_t)0x00000200) #define I3C_INTENR_RXTGTENDIE ((uint32_t)0x00000400) #define I3C_INTENR_ERRIE ((uint32_t)0x00000800) #define I3C_INTENR_IBIIE ((uint32_t)0x00008000) #define I3C_INTENR_IBIENDIE ((uint32_t)0x00010000) #define I3C_INTENR_CRIE ((uint32_t)0x00020000) #define I3C_INTENR_CRUPDIE ((uint32_t)0x00040000) #define I3C_INTENR_HJIE ((uint32_t)0x00080000) #define I3C_INTENR_WKPIE ((uint32_t)0x00200000) #define I3C_INTENR_GETIE ((uint32_t)0x00400000) #define I3C_INTENR_STAIE ((uint32_t)0x00800000) #define I3C_INTENR_DAUPDIE ((uint32_t)0x01000000) #define I3C_INTENR_MWLUPDIE ((uint32_t)0x02000000) #define I3C_INTENR_MRLUPDIE ((uint32_t)0x04000000) #define I3C_INTENR_RSTIE ((uint32_t)0x08000000) #define I3C_INTENR_ASUPDIE ((uint32_t)0x10000000) #define I3C_INTENR_INTUPDIE ((uint32_t)0x20000000) #define I3C_INTENR_DEFIE ((uint32_t)0x40000000) #define I3C_INTENR_GRPIE ((uint32_t)0x80000000) /***************** Bit definition for I3C_CEVR register ******************/ #define I3C_CEVR_CFCR ((uint32_t)0x00000200) #define I3C_CEVR_CRXTGTENDF ((uint32_t)0x00000400) #define I3C_CEVR_CERRF ((uint32_t)0x00000800) #define I3C_CEVR_CIBIF ((uint32_t)0x00008000) #define I3C_CEVR_CIBIENDF ((uint32_t)0x00010000) #define I3C_CEVR_CCRF ((uint32_t)0x00020000) #define I3C_CEVR_CCRUPDF ((uint32_t)0x00040000) #define I3C_CEVR_CHJF ((uint32_t)0x00080000) #define I3C_CEVR_CWKPF ((uint32_t)0x00200000) #define I3C_CEVR_CGETF ((uint32_t)0x00400000) #define I3C_CEVR_CSTAF ((uint32_t)0x00800000) #define I3C_CEVR_CDAUPDF ((uint32_t)0x01000000) #define I3C_CEVR_CMWLUPDF ((uint32_t)0x02000000) #define I3C_CEVR_CMRLUPDF ((uint32_t)0x04000000) #define I3C_CEVR_CRSTF ((uint32_t)0x08000000) #define I3C_CEVR_CASUPDF ((uint32_t)0x10000000) #define I3C_CEVR_CINTUPDF ((uint32_t)0x20000000) #define I3C_CEVR_CDEFF ((uint32_t)0x40000000) #define I3C_CEVR_CGRPF ((uint32_t)0x80000000) /***************** Bit definition for I3C_DEVR0 register ******************/ #define I3C_DEVR0_DAVAL ((uint32_t)0x00000001) #define I3C_DEVR0_DA ((uint32_t)0x000000FE) #define I3C_DEVR0_IBIEN ((uint32_t)0x00010000) #define I3C_DEVR0_CREN ((uint32_t)0x00020000) #define I3C_DEVR0_HJEN ((uint32_t)0x00080000) #define I3C_DEVR0_AS ((uint32_t)0x00300000) #define I3C_DEVR0_AS_0 ((uint32_t)0x00100000) #define I3C_DEVR0_AS_1 ((uint32_t)0x00200000) #define I3C_DEVR0_RSTACT ((uint32_t)0x00C00000) #define I3C_DEVR0_RSTACT_0 ((uint32_t)0x00400000) #define I3C_DEVR0_RSTACT_1 ((uint32_t)0x00800000) #define I3C_DEVR0_RSTVAL ((uint32_t)0x01000000) /***************** Bit definition for I3C_DEVR1 register ******************/ #define I3C_DEVR1_DA ((uint32_t)0x000000FE) #define I3C_DEVR1_IBIACK ((uint32_t)0x00010000) #define I3C_DEVR1_CRACK ((uint32_t)0x00020000) #define I3C_DEVR1_IBIDEN ((uint32_t)0x00040000) #define I3C_DEVR1_SUSP ((uint32_t)0x00080000) #define I3C_DEVR1_DIS ((uint32_t)0x80000000) /***************** Bit definition for I3C_DEVR2 register ******************/ #define I3C_DEVR2_DA ((uint32_t)0x000000FE) #define I3C_DEVR2_IBIACK ((uint32_t)0x00010000) #define I3C_DEVR2_CRACK ((uint32_t)0x00020000) #define I3C_DEVR2_IBIDEN ((uint32_t)0x00040000) #define I3C_DEVR2_SUSP ((uint32_t)0x00080000) #define I3C_DEVR2_DIS ((uint32_t)0x80000000) /***************** Bit definition for I3C_DEVR3 register ******************/ #define I3C_DEVR3_DA ((uint32_t)0x000000FE) #define I3C_DEVR3_IBIACK ((uint32_t)0x00010000) #define I3C_DEVR3_CRACK ((uint32_t)0x00020000) #define I3C_DEVR3_IBIDEN ((uint32_t)0x00040000) #define I3C_DEVR3_SUSP ((uint32_t)0x00080000) #define I3C_DEVR3_DIS ((uint32_t)0x80000000) /***************** Bit definition for I3C_DEVR4 register ******************/ #define I3C_DEVR4_DA ((uint32_t)0x000000FE) #define I3C_DEVR4_IBIACK ((uint32_t)0x00010000) #define I3C_DEVR4_CRACK ((uint32_t)0x00020000) #define I3C_DEVR4_IBIDEN ((uint32_t)0x00040000) #define I3C_DEVR4_SUSP ((uint32_t)0x00080000) #define I3C_DEVR4_DIS ((uint32_t)0x80000000) /***************** Bit definition for I3C_MAXRLR register ******************/ #define I3C_MAXRLR_MRL ((uint32_t)0x0000FFFF) #define I3C_MAXRLR_IBIP ((uint32_t)0x00070000) #define I3C_MAXRLR_IBIP_0 ((uint32_t)0x00010000) #define I3C_MAXRLR_IBIP_1 ((uint32_t)0x00020000) #define I3C_MAXRLR_IBIP_2 ((uint32_t)0x00040000) /***************** Bit definition for I3C_MAXWLR register ******************/ #define I3C_MAXWLR_MWL ((uint32_t)0x0000FFFF) /***************** Bit definition for I3C_TIMINGR0 register ******************/ #define I3C_TIMINGR0_SCLL_PP ((uint32_t)0x000000FF) #define I3C_TIMINGR0_SCLH_I3C ((uint32_t)0x0000FF00) #define I3C_TIMINGR0_SCLL_OD ((uint32_t)0x00FF0000) #define I3C_TIMINGR0_SCLH_I2C ((uint32_t)0xFF000000) /***************** Bit definition for I3C_TIMINGR1 register ******************/ #define I3C_TIMINGR1_AVAL ((uint32_t)0x000000FF) #define I3C_TIMINGR1_ASNCR ((uint32_t)0x00000300) #define I3C_TIMINGR1_FREE ((uint32_t)0x007F0000) #define I3C_TIMINGR1_SDA_HD ((uint32_t)0x10000000) /***************** Bit definition for I3C_TIMINGR2 register ******************/ #define I3C_TIMINGR2_STALLT ((uint32_t)0x00000001) #define I3C_TIMINGR2_STALLD ((uint32_t)0x00000002) #define I3C_TIMINGR2_STALLC ((uint32_t)0x00000004) #define I3C_TIMINGR2_STALLA ((uint32_t)0x00000008) #define I3C_TIMINGR2_STALL ((uint32_t)0x0000FF00) /***************** Bit definition for I3C_DCR register ******************/ #define I3C_DCR ((uint32_t)0x000000FF) /***************** Bit definition for I3C_GETCAPR register ******************/ #define I3C_GETCAPR_CAPPEND ((uint32_t)0x00004000) /***************** Bit definition for I3C_CRCAPR register ******************/ #define I3C_CRCAPR_CAPDHOFF ((uint32_t)0x00000008) #define I3C_CRCAPR_CAPGRP ((uint32_t)0x00000200) /***************** Bit definition for I3C_GETMDSR register ******************/ #define I3C_GETMDSR_HOFFAS ((uint32_t)0x00000003) #define I3C_GETMDSR_HOFFAS_0 ((uint32_t)0x00000001) #define I3C_GETMDSR_HOFFAS_1 ((uint32_t)0x00000002) #define I3C_GETMDSR_FMT ((uint32_t)0x00000300) #define I3C_GETMDSR_FMT_0 ((uint32_t)0x00000100) #define I3C_GETMDSR_FMT_1 ((uint32_t)0x00000200) #define I3C_GETMDSR_RDTURN ((uint32_t)0x00FF0000) #define I3C_GETMDSR_TSCO ((uint32_t)0x01000000) /***************** Bit definition for I3C_EPIDR register ******************/ #define I3C_EPIDR_MIPIID ((uint32_t)0x0000F000) #define I3C_EPIDR_IDTSEL ((uint32_t)0x00010000) #define I3C_EPIDR_MIPIMID ((uint32_t)0xFFFE0000) /******************************************************************************/ /* LOW POWER TIM */ /******************************************************************************/ /******************* Bit definition for LPTIM_ISR register *******************/ #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) #define LPTIM_ISR_ARROK ((uint32_t)0000000010) #define LPTIM_ISR_UP ((uint32_t)0x00000020) #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) #define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) /******************* Bit definition for LPTIM_ICR register *******************/ #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /******************* Bit definition for LPTIM_IER register *******************/ #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) #define LPTIM_IER_UPIE ((uint32_t)0x00000020) #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /******************* Bit definition for LPTIM_CFGR register *******************/ #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) #define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) #define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) #define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) /******************* Bit definition for LPTIM_CR register *******************/ #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) #define LPTIM_CR_OUTEN ((uint32_t)0x00000008) #define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) /******************* Bit definition for LPTIM_CMP register *******************/ #define LPTIM_CMP ((uint32_t)0x0000FFFF) /******************* Bit definition for LPTIM_ARR register *******************/ #define LPTIM_ARR ((uint32_t)0x0000FFFF) /******************* Bit definition for LPTIM_CNT register *******************/ #define LPTIM_COUNT ((uint32_t)0x0000FFFF) /******************************************************************************/ /* Power Control */ /******************************************************************************/ /******************** Bit definition for PWR_CTLR register ********************/ #define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ #define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ #define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ #define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ #define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ #define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ #define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) #define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) #define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) #define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) #define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) #define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) #define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) #define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) #define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ #define PWR_CTLR_VIO_SWCR ((uint16_t)0x0200) #define PWR_CTLR_VSEL_VIO18 ((uint16_t)0x1C00) #define PWR_CTLR_VSEL_VIO18_0 ((uint16_t)0x0400) #define PWR_CTLR_VSEL_VIO18_1 ((uint16_t)0x0800) #define PWR_CTLR_VSEL_VIO18_2 ((uint16_t)0x1000) #define PWR_CTLR_VSEL_VIO18_MODE0 ((uint16_t)0x0000) #define PWR_CTLR_VSEL_VIO18_MODE1 ((uint16_t)0x0400) #define PWR_CTLR_VSEL_VIO18_MODE2 ((uint16_t)0x0800) #define PWR_CTLR_VSEL_VIO18_MODE3 ((uint16_t)0x0C00) #define PWR_CTLR_VSEL_VIO18_MODE4 ((uint16_t)0x1000) #define PWR_CTLR_VSEL_VIO18_MODE5 ((uint16_t)0x1400) #define PWR_CTLR_VSEL_VIO18_MODE6 ((uint16_t)0x1800) #define PWR_CTLR_VSEL_VIO18_MODE7 ((uint16_t)0x1C00) /******************* Bit definition for PWR_CSR register ********************/ #define PWR_CSR_PVDO ((uint16_t)0x0001) #define PWR_CSR_VIO18_SR ((uint16_t)0x0300) #define PWR_CSR_VIO18_SR_0 ((uint16_t)0x0100) #define PWR_CSR_VIO18_SR_1 ((uint16_t)0x0200) /******************************************************************************/ /* Reset and Clock Control */ /******************************************************************************/ /******************** Bit definition for RCC_CTLR register ********************/ #define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ #define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ #define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ #define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ #define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ #define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ #define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ #define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ #define RCC_USBHS_PLLON ((uint32_t)0x00100000) #define RCC_USBHS_PLLRDY ((uint32_t)0x00200000) #define RCC_USBSS_PLLON ((uint32_t)0x00400000) #define RCC_USBSS_PLLRDY ((uint32_t)0x00800000) #define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ #define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ #define RCC_ETH_PLLON ((uint32_t)0x04000000) #define RCC_ETH_PLLRDY ((uint32_t)0x08000000) #define RCC_SERDES_PLLON ((uint32_t)0x10000000) #define RCC_SERDES_PLLRDY ((uint32_t)0x20000000) #define RCC_CSS_HSE_DIS ((uint32_t)0x80000000) /******************* Bit definition for RCC_CFGR0 register *******************/ #define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ #define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ #define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ #define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ #define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ #define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ #define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ #define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ #define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ #define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ #define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ #define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ #define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ #define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ #define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ #define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ #define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ #define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ #define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ #define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ #define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ #define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ #define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ #define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ #define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ #define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ #define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ #define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ #define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ #define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ #define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ #define RCC_PPRE1_DIV2 ((uint32_t)0x00000500) /* HCLK divided by 2 */ #define RCC_PPRE1_DIV4 ((uint32_t)0x00000600) /* HCLK divided by 4 */ #define RCC_PPRE1_DIV8 ((uint32_t)0x00000700) /* HCLK divided by 8 */ #define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ #define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ #define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ #define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ #define RCC_PPRE2_TIM_DIV1 ((uint32_t)0x00000000) /* HCLK divided by 1 for TIM1,8,9,10*/ #define RCC_PPRE2_TIM_DIV2 ((uint32_t)0x00002800) /* HCLK divided by 2 for TIM1,8,9,10*/ #define RCC_PPRE2_TIM_DIV4 ((uint32_t)0x00003000) /* HCLK divided by 4 for TIM1,8,9,10*/ #define RCC_PPRE2_TIM_DIV8 ((uint32_t)0x00003800) /* HCLK divided by 8 for TIM1,8,9,10*/ #define RCC_PPRE2_ADCL_DIV1 ((uint32_t)0x00000000) /* HCLK divided by 1 for ADC*/ #define RCC_PPRE2_ADCL_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 for ADC*/ #define RCC_PPRE2_ADCL_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 for ADC*/ #define RCC_PPRE2_ADCL_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 for ADC*/ #define RCC_PPRE2_ADCL_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 for ADC*/ #define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ #define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ #define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ #define RCC_ADCPRE_ADCH_DIV2 ((uint32_t)0x00000000) /* HCLK divided by 2 for ADC*/ #define RCC_ADCPRE_ADCH_DIV4 ((uint32_t)0x00001000) /* HCLK divided by 4 for ADC*/ #define RCC_ADCPRE_ADCH_DIV6 ((uint32_t)0x00002000) /* HCLK divided by 6 for ADC*/ #define RCC_ADCPRE_ADCH_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 for ADC*/ #define RCC_ADCPRE_DIV5 ((uint32_t)0x00000000) /* USBHS PLL divided by 5 for ADC */ #define RCC_ADCPRE_DIV6 ((uint32_t)0x00000800) /* USBHS PLL divided by 6 for ADC */ #define RCC_ADCPRE_DIV7 ((uint32_t)0x00001000) /* USBHS PLL divided by 7 for ADC */ #define RCC_ADCPRE_DIV8 ((uint32_t)0x00001800) /* USBHS PLL divided by 8 for ADC */ #define RCC_ADCPRE_DIV9 ((uint32_t)0x00002000) /* USBHS PLL divided by 9 for ADC */ #define RCC_ADCPRE_DIV10 ((uint32_t)0x00002800) /* USBHS PLL divided by 10 for ADC */ #define RCC_ADCPRE_DIV11 ((uint32_t)0x00003000) /* USBHS PLL divided by 11 for ADC */ #define RCC_ADCPRE_DIV12 ((uint32_t)0x00003800) /* USBHS PLL divided by 12 for ADC */ #define RCC_ADCPRE_DIV13 ((uint32_t)0x00004000) /* USBHS PLL divided by 13 for ADC */ #define RCC_ADCPRE_DIV14 ((uint32_t)0x00004800) /* USBHS PLL divided by 14 for ADC */ #define RCC_ADCPRE_DIV15 ((uint32_t)0x00005000) /* USBHS PLL divided by 15 for ADC */ #define RCC_ADCPRE_DIV16 ((uint32_t)0x00005800) /* USBHS PLL divided by 16 for ADC */ #define RCC_ADCPRE_DIV17 ((uint32_t)0x00006000) /* USBHS PLL divided by 17 for ADC */ #define RCC_ADCPRE_DIV18 ((uint32_t)0x00006800) /* USBHS PLL divided by 18 for ADC */ #define RCC_ADCPRE_DIV19 ((uint32_t)0x00007000) /* USBHS PLL divided by 19 for ADC */ #define RCC_ADCPRE_DIV20 ((uint32_t)0x00007800) /* USBHS PLL divided by 20 for ADC */ #define RCC_ADCPRE_DIV21 ((uint32_t)0x00008000) /* USBHS PLL divided by 21 for ADC */ #define RCC_ADCPRE_DIV22 ((uint32_t)0x00008800) /* USBHS PLL divided by 22 for ADC */ #define RCC_ADCPRE_DIV23 ((uint32_t)0x00009000) /* USBHS PLL divided by 23 for ADC */ #define RCC_ADCPRE_DIV24 ((uint32_t)0x00009800) /* USBHS PLL divided by 24 for ADC */ #define RCC_ADCPRE_DIV25 ((uint32_t)0x0000A000) /* USBHS PLL divided by 25 for ADC */ #define RCC_ADCPRE_DIV26 ((uint32_t)0x0000A800) /* USBHS PLL divided by 26 for ADC */ #define RCC_ADCPRE_DIV27 ((uint32_t)0x0000B000) /* USBHS PLL divided by 27 for ADC */ #define RCC_ADCPRE_DIV28 ((uint32_t)0x0000B800) /* USBHS PLL divided by 28 for ADC */ #define RCC_ADCPRE_DIV29 ((uint32_t)0x0000C000) /* USBHS PLL divided by 29 for ADC */ #define RCC_ADCPRE_DIV30 ((uint32_t)0x0000C800) /* USBHS PLL divided by 30 for ADC */ #define RCC_ADCPRE_DIV31 ((uint32_t)0x0000D000) /* USBHS PLL divided by 31 for ADC */ #define RCC_ADCPRE_DIV32 ((uint32_t)0x0000D800) /* USBHS PLL divided by 32 for ADC */ #define RCC_ADCPRE_DIV33 ((uint32_t)0x0000E000) /* USBHS PLL divided by 33 for ADC */ #define RCC_ADCPRE_DIV34 ((uint32_t)0x0000E800) /* USBHS PLL divided by 34 for ADC */ #define RCC_ADCPRE_DIV35 ((uint32_t)0x0000F000) /* USBHS PLL divided by 35 for ADC */ #define RCC_ADCPRE_DIV36 ((uint32_t)0x0000F800) /* USBHS PLL divided by 36 for ADC */ #define RCC_FPRE ((uint32_t)0x00030000) #define RCC_FPRE_0 ((uint32_t)0x00010000) #define RCC_FPRE_1 ((uint32_t)0x00020000) #define RCC_FPRE_DIV1 ((uint32_t)0x00000000) #define RCC_FPRE_DIV2 ((uint32_t)0x00010000) #define RCC_FPRE_DIV4 ((uint32_t)0x00020000) #define RCC_RGMIION ((uint32_t)0x00200000) #define RCC_PIPEON ((uint32_t)0x00400000) #define RCC_UTMION ((uint32_t)0x00800000) #define RCC_CFGR0_MCO ((uint32_t)0x0F000000) #define RCC_MCO_0 ((uint32_t)0x01000000) #define RCC_MCO_1 ((uint32_t)0x02000000) #define RCC_MCO_2 ((uint32_t)0x04000000) #define RCC_MCO_3 ((uint32_t)0x08000000) #define RCC_CFGR0_MCO_NOCLOCK ((uint32_t)0x00000000) #define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) #define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) #define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) #define RCC_CFGR0_MCO_PLL_DIV2 ((uint32_t)0x07000000) #define RCC_CFGR0_MCO_UTMI ((uint32_t)0x08000000) #define RCC_CFGR0_MCO_USBSS_PLL_DIV2 ((uint32_t)0x09000000) #define RCC_CFGR0_MCO_ETH_PLL_DIV8 ((uint32_t)0x0A000000) #define RCC_CFGR0_MCO_SERDES_DIV16 ((uint32_t)0x0B000000) #define RCC_ADC_DUTY_SEL ((uint32_t)0x40000000) #define RCC_ADCSRC ((uint32_t)0x80000000) /******************* Bit definition for RCC_PLLCFGR register *******************/ #define RCC_PLLMUL ((uint32_t)0x0000001F) #define RCC_PLLMUL_0 ((uint32_t)0x00000001) #define RCC_PLLMUL_1 ((uint32_t)0x00000002) #define RCC_PLLMUL_2 ((uint32_t)0x00000004) #define RCC_PLLMUL_3 ((uint32_t)0x00000008) #define RCC_PLLMUL_4 ((uint32_t)0x00000010) #define RCC_PLLMUL4 ((uint32_t)0x00000000) #define RCC_PLLMUL6 ((uint32_t)0x00000001) #define RCC_PLLMUL7 ((uint32_t)0x00000002) #define RCC_PLLMUL8 ((uint32_t)0x00000003) #define RCC_PLLMUL8_5 ((uint32_t)0x00000004) #define RCC_PLLMUL9 ((uint32_t)0x00000005) #define RCC_PLLMUL9_5 ((uint32_t)0x00000006) #define RCC_PLLMUL10 ((uint32_t)0x00000007) #define RCC_PLLMUL10_5 ((uint32_t)0x00000008) #define RCC_PLLMUL11 ((uint32_t)0x00000009) #define RCC_PLLMUL11_5 ((uint32_t)0x0000000A) #define RCC_PLLMUL12 ((uint32_t)0x0000000B) #define RCC_PLLMUL12_5 ((uint32_t)0x0000000C) #define RCC_PLLMUL13 ((uint32_t)0x0000000D) #define RCC_PLLMUL14 ((uint32_t)0x0000000E) #define RCC_PLLMUL15 ((uint32_t)0x0000000F) #define RCC_PLLMUL16 ((uint32_t)0x00000010) #define RCC_PLLMUL17 ((uint32_t)0x00000011) #define RCC_PLLMUL18 ((uint32_t)0x00000012) #define RCC_PLLMUL19 ((uint32_t)0x00000013) #define RCC_PLLMUL20 ((uint32_t)0x00000014) #define RCC_PLLMUL22 ((uint32_t)0x00000015) #define RCC_PLLMUL24 ((uint32_t)0x00000016) #define RCC_PLLMUL26 ((uint32_t)0x00000017) #define RCC_PLLMUL28 ((uint32_t)0x00000018) #define RCC_PLLMUL30 ((uint32_t)0x00000019) #define RCC_PLLMUL32 ((uint32_t)0x0000001A) #define RCC_PLLMUL34 ((uint32_t)0x0000001B) #define RCC_PLLMUL36 ((uint32_t)0x0000001C) #define RCC_PLLMUL38 ((uint32_t)0x0000001D) #define RCC_PLLMUL40 ((uint32_t)0x0000001E) #define RCC_PLLMUL59 ((uint32_t)0x0000001F) #define RCC_PLLSRC ((uint32_t)0x000000E0) #define RCC_PLLSRC_0 ((uint32_t)0x00000020) #define RCC_PLLSRC_2 ((uint32_t)0x00000040) #define RCC_PLLSRC_4 ((uint32_t)0x00000080) #define RCC_PLLSRC_HSI ((uint32_t)0x00000000) #define RCC_PLLSRC_HSE ((uint32_t)0x00000020) #define RCC_PLLSRC_USBHS_PLL ((uint32_t)0x00000080) #define RCC_PLLSRC_ETH_PLL ((uint32_t)0x000000A0) #define RCC_PLLSRC_USBSS_PLL ((uint32_t)0x000000C0) #define RCC_PLLSRC_SERDES_PLL ((uint32_t)0x000000E0) #define RCC_PLL_SRC_DIV ((uint32_t)0x00003F00) #define RCC_PLL_SRC_DIV_0 ((uint32_t)0x00000100) #define RCC_PLL_SRC_DIV_1 ((uint32_t)0x00000200) #define RCC_PLL_SRC_DIV_2 ((uint32_t)0x00000400) #define RCC_PLL_SRC_DIV_3 ((uint32_t)0x00000800) #define RCC_PLL_SRC_DIV_4 ((uint32_t)0x00001000) #define RCC_PLL_SRC_DIV_5 ((uint32_t)0x00002000) #define RCC_PLL_SRC_DIV1 ((uint32_t)0x00000000) #define RCC_PLL_SRC_DIV2 ((uint32_t)0x00000100) #define RCC_PLL_SRC_DIV3 ((uint32_t)0x00000200) #define RCC_PLL_SRC_DIV4 ((uint32_t)0x00000300) #define RCC_PLL_SRC_DIV5 ((uint32_t)0x00000400) #define RCC_PLL_SRC_DIV6 ((uint32_t)0x00000500) #define RCC_PLL_SRC_DIV7 ((uint32_t)0x00000600) #define RCC_PLL_SRC_DIV8 ((uint32_t)0x00000700) #define RCC_PLL_SRC_DIV9 ((uint32_t)0x00000800) #define RCC_PLL_SRC_DIV10 ((uint32_t)0x00000900) #define RCC_PLL_SRC_DIV11 ((uint32_t)0x00000A00) #define RCC_PLL_SRC_DIV12 ((uint32_t)0x00000B00) #define RCC_PLL_SRC_DIV13 ((uint32_t)0x00000C00) #define RCC_PLL_SRC_DIV14 ((uint32_t)0x00000D00) #define RCC_PLL_SRC_DIV15 ((uint32_t)0x00000E00) #define RCC_PLL_SRC_DIV16 ((uint32_t)0x00000F00) #define RCC_PLL_SRC_DIV17 ((uint32_t)0x00001000) #define RCC_PLL_SRC_DIV18 ((uint32_t)0x00001100) #define RCC_PLL_SRC_DIV19 ((uint32_t)0x00001200) #define RCC_PLL_SRC_DIV20 ((uint32_t)0x00001300) #define RCC_PLL_SRC_DIV21 ((uint32_t)0x00001400) #define RCC_PLL_SRC_DIV22 ((uint32_t)0x00001500) #define RCC_PLL_SRC_DIV23 ((uint32_t)0x00001600) #define RCC_PLL_SRC_DIV24 ((uint32_t)0x00001700) #define RCC_PLL_SRC_DIV25 ((uint32_t)0x00001800) #define RCC_PLL_SRC_DIV26 ((uint32_t)0x00001900) #define RCC_PLL_SRC_DIV27 ((uint32_t)0x00001A00) #define RCC_PLL_SRC_DIV28 ((uint32_t)0x00001B00) #define RCC_PLL_SRC_DIV29 ((uint32_t)0x00001C00) #define RCC_PLL_SRC_DIV30 ((uint32_t)0x00001D00) #define RCC_PLL_SRC_DIV31 ((uint32_t)0x00001E00) #define RCC_PLL_SRC_DIV32 ((uint32_t)0x00001F00) #define RCC_PLL_SRC_DIV33 ((uint32_t)0x00002000) #define RCC_PLL_SRC_DIV34 ((uint32_t)0x00002100) #define RCC_PLL_SRC_DIV35 ((uint32_t)0x00002200) #define RCC_PLL_SRC_DIV36 ((uint32_t)0x00002300) #define RCC_PLL_SRC_DIV37 ((uint32_t)0x00002400) #define RCC_PLL_SRC_DIV38 ((uint32_t)0x00002500) #define RCC_PLL_SRC_DIV39 ((uint32_t)0x00002600) #define RCC_PLL_SRC_DIV40 ((uint32_t)0x00002700) #define RCC_PLL_SRC_DIV41 ((uint32_t)0x00002800) #define RCC_PLL_SRC_DIV42 ((uint32_t)0x00002900) #define RCC_PLL_SRC_DIV43 ((uint32_t)0x00002A00) #define RCC_PLL_SRC_DIV44 ((uint32_t)0x00002B00) #define RCC_PLL_SRC_DIV45 ((uint32_t)0x00002C00) #define RCC_PLL_SRC_DIV46 ((uint32_t)0x00002D00) #define RCC_PLL_SRC_DIV47 ((uint32_t)0x00002E00) #define RCC_PLL_SRC_DIV48 ((uint32_t)0x00002F00) #define RCC_PLL_SRC_DIV49 ((uint32_t)0x00003000) #define RCC_PLL_SRC_DIV50 ((uint32_t)0x00003100) #define RCC_PLL_SRC_DIV51 ((uint32_t)0x00003200) #define RCC_PLL_SRC_DIV52 ((uint32_t)0x00003300) #define RCC_PLL_SRC_DIV53 ((uint32_t)0x00003400) #define RCC_PLL_SRC_DIV54 ((uint32_t)0x00003500) #define RCC_PLL_SRC_DIV55 ((uint32_t)0x00003600) #define RCC_PLL_SRC_DIV56 ((uint32_t)0x00003700) #define RCC_PLL_SRC_DIV57 ((uint32_t)0x00003800) #define RCC_PLL_SRC_DIV58 ((uint32_t)0x00003900) #define RCC_PLL_SRC_DIV59 ((uint32_t)0x00003A00) #define RCC_PLL_SRC_DIV60 ((uint32_t)0x00003B00) #define RCC_PLL_SRC_DIV61 ((uint32_t)0x00003C00) #define RCC_PLL_SRC_DIV62 ((uint32_t)0x00003D00) #define RCC_PLL_SRC_DIV63 ((uint32_t)0x00003E00) #define RCC_PLL_SRC_DIV64 ((uint32_t)0x00003F00) #define RCC_SYSPLL_SEL ((uint32_t)0x70000000) #define RCC_SYSPLL_SEL_0 ((uint32_t)0x10000000) #define RCC_SYSPLL_SEL_1 ((uint32_t)0x20000000) #define RCC_SYSPLL_SEL_2 ((uint32_t)0x40000000) #define RCC_SYSPLL_PLL ((uint32_t)0x00000000) #define RCC_SYSPLL_USBHS ((uint32_t)0x40000000) #define RCC_SYSPLL_ETH ((uint32_t)0x50000000) #define RCC_SYSPLL_SERDES ((uint32_t)0x60000000) #define RCC_SYSPLL_USBSS ((uint32_t)0x70000000) #define RCC_SYSPLL_GATE ((uint32_t)0x80000000) /******************* Bit definition for RCC_INTR register ********************/ #define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ #define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ #define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ #define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ #define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ #define RCC_ETHPLLRDYF ((uint32_t)0x00000020) #define RCC_SERDESPLLRDYF ((uint32_t)0x00000040) #define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ #define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ #define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ #define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ #define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ #define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ #define RCC_ETHPLLRDYIE ((uint32_t)0x00002000) #define RCC_SERDESPLLRDYIE ((uint32_t)0x00004000) #define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ #define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ #define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ #define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ #define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ #define RCC_ETHPLLRDYC ((uint32_t)0x00200000) #define RCC_SERDESPLLRDYC ((uint32_t)0x00400000) #define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_HB2PRSTR register *****************/ #define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ #define RCC_HSADCRST ((uint32_t)0x00000002) #define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ #define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ #define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ #define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ #define RCC_IOPERST ((uint32_t)0x00000040) #define RCC_IOPFRST ((uint32_t)0x00000080) #define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ #define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ #define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ #define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ #define RCC_TIM8RST ((uint32_t)0x00002000) #define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ #define RCC_I2C4RST ((uint32_t)0x00008000) #define RCC_SAIRST ((uint32_t)0x00010000) #define RCC_SDIORST ((uint32_t)0x00040000) #define RCC_TIM9RST ((uint32_t)0x00080000) #define RCC_TIM10RST ((uint32_t)0x00100000) #define RCC_TIM11RST ((uint32_t)0x00200000) #define RCC_TIM12RST ((uint32_t)0x00400000) #define RCC_OPCMRST ((uint32_t)0x00800000) #define RCC_DFSDMRST ((uint32_t)0x02000000) #define RCC_ECDCRST ((uint32_t)0x04000000) #define RCC_GPHARST ((uint32_t)0x08000000) #define RCC_LTDCRST ((uint32_t)0x40000000) #define RCC_I3CRST ((uint32_t)0x80000000) /***************** Bit definition for RCC_HB1PRSTR register *****************/ #define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ #define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ #define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ #define RCC_TIM5RST ((uint32_t)0x00000008) /* Timer 5 reset */ #define RCC_TIM6RST ((uint32_t)0x00000010) /* Timer 6 reset */ #define RCC_TIM7RST ((uint32_t)0x00000020) /* Timer 7 reset */ #define RCC_USART6RST ((uint32_t)0x00000040) /* USART 2 reset */ #define RCC_USART7RST ((uint32_t)0x00000080) /* USART 2 reset */ #define RCC_USART8RST ((uint32_t)0x00000100) /* USART 2 reset */ #define RCC_LPTIM1RST ((uint32_t)0x00000200) #define RCC_LPTIM2RST ((uint32_t)0x00000400) #define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ #define RCC_QSPI1RST ((uint32_t)0x00001000) #define RCC_QSPI2RST ((uint32_t)0x00002000) #define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ #define RCC_SPI3RST ((uint32_t)0x00008000) /* SPI 3 reset */ #define RCC_SPI4RST ((uint32_t)0x00010000) #define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ #define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ #define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ #define RCC_USART5RST ((uint32_t)0x00100000) /* USART 5 reset */ #define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ #define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ #define RCC_CAN3RST ((uint32_t)0x01000000) #define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ #define RCC_CAN2RST ((uint32_t)0x04000000) /* CAN2 reset */ #define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ #define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ #define RCC_DACRST ((uint32_t)0x20000000) /* DAC reset */ #define RCC_I2C3RST ((uint32_t)0x40000000) #define RCC_SWPMIRST ((uint32_t)0x80000000) /****************** Bit definition for RCC_HBPCENR register ******************/ #define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ #define RCC_DMA2EN ((uint16_t)0x0002) #define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ #define RCC_FMCEN ((uint16_t)0x0100) #define RCC_RNGEN ((uint16_t)0x0200) #define RCC_SDMMCEN ((uint16_t)0x0400) #define RCC_USBHSEN ((uint16_t)0x0800) #define RCC_USBSSEN ((uint16_t)0x1000) #define RCC_DVPEN ((uint16_t)0x2000) #define RCC_ETHEN ((uint16_t)0x4000) #define RCC_USBOTGEN ((uint32_t)0x00020000) #define RCC_UHSIFEN ((uint32_t)0x00040000) #define RCC_USBPDEN ((uint32_t)0x00080000) #define RCC_SERDESEN ((uint32_t)0x00100000) #define RCC_PIOCEN ((uint32_t)0x00400000) /****************** Bit definition for RCC_HB2PCENR register *****************/ #define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ #define RCC_HSADCEN ((uint32_t)0x00000002) #define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ #define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ #define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ #define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ #define RCC_IOPEEN ((uint32_t)0x00000040) #define RCC_IOPFEN ((uint32_t)0x00000080) #define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ #define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ #define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ #define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ #define RCC_TIM8EN ((uint32_t)0x00002000) #define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ #define RCC_I2C4EN ((uint32_t)0x00008000) #define RCC_SAIEN ((uint32_t)0x00010000) #define RCC_SDIOEN ((uint32_t)0x00040000) #define RCC_TIM9EN ((uint32_t)0x00080000) #define RCC_TIM10EN ((uint32_t)0x00100000) #define RCC_TIM11EN ((uint32_t)0x00200000) #define RCC_TIM12EN ((uint32_t)0x00400000) #define RCC_OPCMEN ((uint32_t)0x00800000) #define RCC_DFSDMEN ((uint32_t)0x02000000) #define RCC_ECDCEN ((uint32_t)0x04000000) #define RCC_GPHAEN ((uint32_t)0x08000000) #define RCC_LTDCEN ((uint32_t)0x40000000) #define RCC_I3CEN ((uint32_t)0x80000000) /***************** Bit definition for RCC_HB1PCENR register ******************/ #define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ #define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ #define RCC_TIM4EN ((uint32_t)0x00000004) #define RCC_TIM5EN ((uint32_t)0x00000008) #define RCC_TIM6EN ((uint32_t)0x00000010) #define RCC_TIM7EN ((uint32_t)0x00000020) #define RCC_USART6EN ((uint32_t)0x00000040) #define RCC_USART7EN ((uint32_t)0x00000080) #define RCC_USART8EN ((uint32_t)0x00000100) #define RCC_LPTIM1EN ((uint32_t)0x00000200) #define RCC_LPTIM2EN ((uint32_t)0x00000400) #define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ #define RCC_QSPI1EN ((uint32_t)0x00001000) #define RCC_QSPI2EN ((uint32_t)0x00002000) #define RCC_SPI2EN ((uint32_t)0x00004000) #define RCC_SPI3EN ((uint32_t)0x00008000) #define RCC_SPI4EN ((uint32_t)0x00010000) #define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ #define RCC_USART3EN ((uint32_t)0x00040000) #define RCC_USART4EN ((uint32_t)0x00080000) #define RCC_USART5EN ((uint32_t)0x00100000) #define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ #define RCC_I2C2EN ((uint32_t)0x00400000) #define RCC_CAN3EN ((uint32_t)0x01000000) /* USB Device clock enable */ #define RCC_CAN1EN ((uint32_t)0x02000000) #define RCC_CAN2EN ((uint32_t)0x04000000) #define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ #define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ #define RCC_DACEN ((uint32_t)0x20000000) #define RCC_I2C3EN ((uint32_t)0x40000000) #define RCC_SWPMIEN ((uint32_t)0x80000000) /******************* Bit definition for RCC_BDCTLR register *******************/ #define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ #define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ #define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ #define RCC_CCO ((uint32_t)0x00000008) #define RCC_ASOE ((uint32_t)0x00000010) #define RCC_ASOS ((uint32_t)0x00000020) #define RCC_RTCSEL ((uint32_t)0x000000C0) /* RTCSEL[1:0] bits (RTC clock source selection) */ #define RCC_RTCSEL_0 ((uint32_t)0x00000040) /* Bit 0 */ #define RCC_RTCSEL_1 ((uint32_t)0x00000080) /* Bit 1 */ #define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ #define RCC_RTCSEL_LSE ((uint32_t)0x00000040) /* LSE oscillator clock used as RTC clock */ #define RCC_RTCSEL_LSI ((uint32_t)0x00000080) /* LSI oscillator clock used as RTC clock */ #define RCC_RTCSEL_HSE ((uint32_t)0x000000C0) #define RCC_RTCEN ((uint32_t)0x00000100) /* RTC clock enable */ #define RCC_RTCCAL ((uint32_t)0x0000FE00) #define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ /******************* Bit definition for RCC_RSTSCKR register ********************/ #define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ #define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ #define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ #define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ #define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ #define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ #define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ #define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ #define RCC_LOCKUPRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ /******************* Bit definition for RCC_HBRSTR register ********************/ #define RCC_DMA1RST ((uint32_t)0x00000001) #define RCC_DMA2RST ((uint32_t)0x00000002) #define RCC_FMCRST ((uint32_t)0x00000100) #define RCC_RNGRST ((uint32_t)0x00000200) #define RCC_SDMMCRST ((uint32_t)0x00000400) #define RCC_USBHSRST ((uint32_t)0x00000800) #define RCC_USBSSRST ((uint32_t)0x00001000) #define RCC_DVPRST ((uint32_t)0x00002000) #define RCC_ETHRST ((uint32_t)0x00004000) #define RCC_USBOTGRST ((uint32_t)0x00020000) #define RCC_UHSIFRST ((uint32_t)0x00040000) #define RCC_USBPDRST ((uint32_t)0x00080000) #define RCC_SERDESRST ((uint32_t)0x00100000) #define RCC_PIOCRST ((uint32_t)0x00400000) /******************* Bit definition for RCC_CFGR2 register ********************/ #define RCC_UHSIFDIV ((uint32_t)0x0000003F) #define RCC_UHSIFDIV_0 ((uint32_t)0x00000001) #define RCC_UHSIFDIV_1 ((uint32_t)0x00000002) #define RCC_UHSIFDIV_2 ((uint32_t)0x00000004) #define RCC_UHSIFDIV_3 ((uint32_t)0x00000008) #define RCC_UHSIFDIV_4 ((uint32_t)0x00000010) #define RCC_UHSIFDIV_5 ((uint32_t)0x00000020) #define RCC_UHSIFDIV_DIV1 ((uint32_t)0x00000000) #define RCC_UHSIFDIV_DIV2 ((uint32_t)0x00000001) #define RCC_UHSIFDIV_DIV3 ((uint32_t)0x00000002) #define RCC_UHSIFDIV_DIV4 ((uint32_t)0x00000003) #define RCC_UHSIFDIV_DIV5 ((uint32_t)0x00000004) #define RCC_UHSIFDIV_DIV6 ((uint32_t)0x00000005) #define RCC_UHSIFDIV_DIV7 ((uint32_t)0x00000006) #define RCC_UHSIFDIV_DIV8 ((uint32_t)0x00000007) #define RCC_UHSIFDIV_DIV9 ((uint32_t)0x00000008) #define RCC_UHSIFDIV_DIV10 ((uint32_t)0x00000009) #define RCC_UHSIFDIV_DIV11 ((uint32_t)0x0000000A) #define RCC_UHSIFDIV_DIV12 ((uint32_t)0x0000000B) #define RCC_UHSIFDIV_DIV13 ((uint32_t)0x0000000C) #define RCC_UHSIFDIV_DIV14 ((uint32_t)0x0000000D) #define RCC_UHSIFDIV_DIV15 ((uint32_t)0x0000000E) #define RCC_UHSIFDIV_DIV16 ((uint32_t)0x0000000F) #define RCC_UHSIFDIV_DIV17 ((uint32_t)0x00000010) #define RCC_UHSIFDIV_DIV18 ((uint32_t)0x00000011) #define RCC_UHSIFDIV_DIV19 ((uint32_t)0x00000012) #define RCC_UHSIFDIV_DIV20 ((uint32_t)0x00000013) #define RCC_UHSIFDIV_DIV21 ((uint32_t)0x00000014) #define RCC_UHSIFDIV_DIV22 ((uint32_t)0x00000015) #define RCC_UHSIFDIV_DIV23 ((uint32_t)0x00000016) #define RCC_UHSIFDIV_DIV24 ((uint32_t)0x00000017) #define RCC_UHSIFDIV_DIV25 ((uint32_t)0x00000018) #define RCC_UHSIFDIV_DIV26 ((uint32_t)0x00000019) #define RCC_UHSIFDIV_DIV27 ((uint32_t)0x0000001A) #define RCC_UHSIFDIV_DIV28 ((uint32_t)0x0000001B) #define RCC_UHSIFDIV_DIV29 ((uint32_t)0x0000001C) #define RCC_UHSIFDIV_DIV30 ((uint32_t)0x0000001D) #define RCC_UHSIFDIV_DIV31 ((uint32_t)0x0000001E) #define RCC_UHSIFDIV_DIV32 ((uint32_t)0x0000001F) #define RCC_UHSIFDIV_DIV33 ((uint32_t)0x00000020) #define RCC_UHSIFDIV_DIV34 ((uint32_t)0x00000021) #define RCC_UHSIFDIV_DIV35 ((uint32_t)0x00000022) #define RCC_UHSIFDIV_DIV36 ((uint32_t)0x00000023) #define RCC_UHSIFDIV_DIV37 ((uint32_t)0x00000024) #define RCC_UHSIFDIV_DIV38 ((uint32_t)0x00000025) #define RCC_UHSIFDIV_DIV39 ((uint32_t)0x00000026) #define RCC_UHSIFDIV_DIV40 ((uint32_t)0x00000027) #define RCC_UHSIFDIV_DIV41 ((uint32_t)0x00000028) #define RCC_UHSIFDIV_DIV42 ((uint32_t)0x00000029) #define RCC_UHSIFDIV_DIV43 ((uint32_t)0x0000002A) #define RCC_UHSIFDIV_DIV44 ((uint32_t)0x0000002B) #define RCC_UHSIFDIV_DIV45 ((uint32_t)0x0000002C) #define RCC_UHSIFDIV_DIV46 ((uint32_t)0x0000002D) #define RCC_UHSIFDIV_DIV47 ((uint32_t)0x0000002E) #define RCC_UHSIFDIV_DIV48 ((uint32_t)0x0000002F) #define RCC_UHSIFDIV_DIV49 ((uint32_t)0x00000030) #define RCC_UHSIFDIV_DIV50 ((uint32_t)0x00000031) #define RCC_UHSIFDIV_DIV51 ((uint32_t)0x00000032) #define RCC_UHSIFDIV_DIV52 ((uint32_t)0x00000033) #define RCC_UHSIFDIV_DIV53 ((uint32_t)0x00000034) #define RCC_UHSIFDIV_DIV54 ((uint32_t)0x00000035) #define RCC_UHSIFDIV_DIV55 ((uint32_t)0x00000036) #define RCC_UHSIFDIV_DIV56 ((uint32_t)0x00000037) #define RCC_UHSIFDIV_DIV57 ((uint32_t)0x00000038) #define RCC_UHSIFDIV_DIV58 ((uint32_t)0x00000039) #define RCC_UHSIFDIV_DIV59 ((uint32_t)0x0000003A) #define RCC_UHSIFDIV_DIV60 ((uint32_t)0x0000003B) #define RCC_UHSIFDIV_DIV61 ((uint32_t)0x0000003C) #define RCC_UHSIFDIV_DIV62 ((uint32_t)0x0000003D) #define RCC_UHSIFDIV_DIV63 ((uint32_t)0x0000003E) #define RCC_UHSIFDIV_DIV64 ((uint32_t)0x0000003F) #define RCC_UHSIFSRC ((uint32_t)0x000000C0) #define RCC_UHSIFSRC_0 ((uint32_t)0x00000040) #define RCC_UHSIFSRC_1 ((uint32_t)0x00000080) #define RCC_UHSIFSRC_SYSCLK ((uint32_t)0x00000000) #define RCC_UHSIFSRC_PLLCLK ((uint32_t)0x00000040) #define RCC_UHSIFSRC_USBHSPLL ((uint32_t)0x00000080) #define RCC_UHSIFSRC_ETHPLL ((uint32_t)0x000000C0) #define RCC_LTDCDIV ((uint32_t)0x00003F00) #define RCC_LTDCDIV_0 ((uint32_t)0x00000100) #define RCC_LTDCDIV_1 ((uint32_t)0x00000200) #define RCC_LTDCDIV_2 ((uint32_t)0x00000400) #define RCC_LTDCDIV_3 ((uint32_t)0x00000800) #define RCC_LTDCDIV_4 ((uint32_t)0x00001000) #define RCC_LTDCDIV_5 ((uint32_t)0x00002000) #define RCC_LTDCDIV_DIV1 ((uint32_t)0x00000000) #define RCC_LTDCDIV_DIV2 ((uint32_t)0x00000100) #define RCC_LTDCDIV_DIV3 ((uint32_t)0x00000200) #define RCC_LTDCDIV_DIV4 ((uint32_t)0x00000300) #define RCC_LTDCDIV_DIV5 ((uint32_t)0x00000400) #define RCC_LTDCDIV_DIV6 ((uint32_t)0x00000500) #define RCC_LTDCDIV_DIV7 ((uint32_t)0x00000600) #define RCC_LTDCDIV_DIV8 ((uint32_t)0x00000700) #define RCC_LTDCDIV_DIV9 ((uint32_t)0x00000800) #define RCC_LTDCDIV_DIV10 ((uint32_t)0x00000900) #define RCC_LTDCDIV_DIV11 ((uint32_t)0x00000A00) #define RCC_LTDCDIV_DIV12 ((uint32_t)0x00000B00) #define RCC_LTDCDIV_DIV13 ((uint32_t)0x00000C00) #define RCC_LTDCDIV_DIV14 ((uint32_t)0x00000D00) #define RCC_LTDCDIV_DIV15 ((uint32_t)0x00000E00) #define RCC_LTDCDIV_DIV16 ((uint32_t)0x00000F00) #define RCC_LTDCDIV_DIV17 ((uint32_t)0x00001000) #define RCC_LTDCDIV_DIV18 ((uint32_t)0x00001100) #define RCC_LTDCDIV_DIV19 ((uint32_t)0x00001200) #define RCC_LTDCDIV_DIV20 ((uint32_t)0x00001300) #define RCC_LTDCDIV_DIV21 ((uint32_t)0x00001400) #define RCC_LTDCDIV_DIV22 ((uint32_t)0x00001500) #define RCC_LTDCDIV_DIV23 ((uint32_t)0x00001600) #define RCC_LTDCDIV_DIV24 ((uint32_t)0x00001700) #define RCC_LTDCDIV_DIV25 ((uint32_t)0x00001800) #define RCC_LTDCDIV_DIV26 ((uint32_t)0x00001900) #define RCC_LTDCDIV_DIV27 ((uint32_t)0x00001A00) #define RCC_LTDCDIV_DIV28 ((uint32_t)0x00001B00) #define RCC_LTDCDIV_DIV29 ((uint32_t)0x00001C00) #define RCC_LTDCDIV_DIV30 ((uint32_t)0x00001D00) #define RCC_LTDCDIV_DIV31 ((uint32_t)0x00001E00) #define RCC_LTDCDIV_DIV32 ((uint32_t)0x00001F00) #define RCC_LTDCDIV_DIV33 ((uint32_t)0x00002000) #define RCC_LTDCDIV_DIV34 ((uint32_t)0x00002100) #define RCC_LTDCDIV_DIV35 ((uint32_t)0x00002200) #define RCC_LTDCDIV_DIV36 ((uint32_t)0x00002300) #define RCC_LTDCDIV_DIV37 ((uint32_t)0x00002400) #define RCC_LTDCDIV_DIV38 ((uint32_t)0x00002500) #define RCC_LTDCDIV_DIV39 ((uint32_t)0x00002600) #define RCC_LTDCDIV_DIV40 ((uint32_t)0x00002700) #define RCC_LTDCDIV_DIV41 ((uint32_t)0x00002800) #define RCC_LTDCDIV_DIV42 ((uint32_t)0x00002900) #define RCC_LTDCDIV_DIV43 ((uint32_t)0x00002A00) #define RCC_LTDCDIV_DIV44 ((uint32_t)0x00002B00) #define RCC_LTDCDIV_DIV45 ((uint32_t)0x00002C00) #define RCC_LTDCDIV_DIV46 ((uint32_t)0x00002D00) #define RCC_LTDCDIV_DIV47 ((uint32_t)0x00002E00) #define RCC_LTDCDIV_DIV48 ((uint32_t)0x00002F00) #define RCC_LTDCDIV_DIV49 ((uint32_t)0x00003000) #define RCC_LTDCDIV_DIV50 ((uint32_t)0x00003100) #define RCC_LTDCDIV_DIV51 ((uint32_t)0x00003200) #define RCC_LTDCDIV_DIV52 ((uint32_t)0x00003300) #define RCC_LTDCDIV_DIV53 ((uint32_t)0x00003400) #define RCC_LTDCDIV_DIV54 ((uint32_t)0x00003500) #define RCC_LTDCDIV_DIV55 ((uint32_t)0x00003600) #define RCC_LTDCDIV_DIV56 ((uint32_t)0x00003700) #define RCC_LTDCDIV_DIV57 ((uint32_t)0x00003800) #define RCC_LTDCDIV_DIV58 ((uint32_t)0x00003900) #define RCC_LTDCDIV_DIV59 ((uint32_t)0x00003A00) #define RCC_LTDCDIV_DIV60 ((uint32_t)0x00003B00) #define RCC_LTDCDIV_DIV61 ((uint32_t)0x00003C00) #define RCC_LTDCDIV_DIV62 ((uint32_t)0x00003D00) #define RCC_LTDCDIV_DIV63 ((uint32_t)0x00003E00) #define RCC_LTDCDIV_DIV64 ((uint32_t)0x00003F00) #define RCC_LTDCSRC ((uint32_t)0x0000C000) #define RCC_LTDCSRC_0 ((uint32_t)0x00004000) #define RCC_LTDCSRC_1 ((uint32_t)0x00008000) #define RCC_LTDCSRC_PLLCLK ((uint32_t)0x00000000) #define RCC_LTDCSRC_SERDESPLL ((uint32_t)0x00004000) #define RCC_LTDCSRC_ETHPLL ((uint32_t)0x00008000) #define RCC_LTDCSRC_USBHSPLL ((uint32_t)0x0000C000) #define RCC_USBFSDIV ((uint32_t)0x000F0000) #define RCC_USBFSDIV_0 ((uint32_t)0x00010000) #define RCC_USBFSDIV_1 ((uint32_t)0x00020000) #define RCC_USBFSDIV_2 ((uint32_t)0x00040000) #define RCC_USBFSDIV_3 ((uint32_t)0x00080000) #define RCC_USBFSDIV_DIV1 ((uint32_t)0x00000000) #define RCC_USBFSDIV_DIV2 ((uint32_t)0x00010000) #define RCC_USBFSDIV_DIV3 ((uint32_t)0x00020000) #define RCC_USBFSDIV_DIV4 ((uint32_t)0x00030000) #define RCC_USBFSDIV_DIV5 ((uint32_t)0x00040000) #define RCC_USBFSDIV_DIV6 ((uint32_t)0x00050000) #define RCC_USBFSDIV_DIV8 ((uint32_t)0x00060000) #define RCC_USBFSDIV_DIV10 ((uint32_t)0x00070000) #define RCC_USBFSDIV_DIV1_5 ((uint32_t)0x00080000) #define RCC_USBFSDIV_DIV2_5 ((uint32_t)0x00090000) #define RCC_USBFSDIV_DIV3_5 ((uint32_t)0x000A0000) #define RCC_USBFSDIV_DIV4_5 ((uint32_t)0x000B0000) #define RCC_USBFSDIV_DIV5_5 ((uint32_t)0x000C0000) #define RCC_USBFSDIV_DIV6_5 ((uint32_t)0x000D0000) #define RCC_USBFSDIV_DIV7_5 ((uint32_t)0x000E0000) #define RCC_USBFSDIV_DIV9_5 ((uint32_t)0x000F0000) #define RCC_USBFSSRC ((uint32_t)0x00100000) #define RCC_USBFSSRC_PLLCLK ((uint32_t)0x00000000) #define RCC_USBFSSRC_USBHSPLL ((uint32_t)0x00100000) #define RCC_RNGSRC ((uint32_t)0x00800000) #define RCC_RNGSRC_SYSCLK ((uint32_t)0x00000000) #define RCC_RNGSRC_PLLCLK ((uint32_t)0x00800000) #define RCC_I2S2SRC ((uint32_t)0x01000000) #define RCC_I2S2SRC_SYSCLK ((uint32_t)0x00000000) #define RCC_I2S2SRC_PLLCLK ((uint32_t)0x01000000) #define RCC_I2S3SRC ((uint32_t)0x02000000) #define RCC_I2S3SRC_SYSCLK ((uint32_t)0x00000000) #define RCC_I2S3SRC_PLLCLK ((uint32_t)0x02000000) #define RCC_HSADCSRC ((uint32_t)0x30000000) #define RCC_HSADCSRC_0 ((uint32_t)0x10000000) #define RCC_HSADCSRC_1 ((uint32_t)0x20000000) #define RCC_HSADCSRC_SYSCLK ((uint32_t)0x00000000) #define RCC_HSADCSRC_PLLCLK ((uint32_t)0x10000000) #define RCC_HSADCSRC_USBHSPLL ((uint32_t)0x20000000) #define RCC_HSADCSRC_ETHPLL ((uint32_t)0x30000000) #define RCC_ETH1GSRC ((uint32_t)0xC0000000) #define RCC_ETH1GSRC_0 ((uint32_t)0x40000000) #define RCC_ETH1GSRC_1 ((uint32_t)0x80000000) #define RCC_ETH1GSRC_PLLCLK ((uint32_t)0x00000000) #define RCC_ETH1GSRC_USBSSPLL ((uint32_t)0x40000000) #define RCC_ETH1GSRC_ETHPLL_DIV4 ((uint32_t)0x80000000) #define RCC_ETH1GSRC_SERDESPLL_DIV8 ((uint32_t)0xC0000000) /******************* Bit definition for RCC_PLLCFGR2 register ********************/ #define RCC_USBHSPLLSRC ((uint32_t)0x00000003) #define RCC_USBHSPLLSRC_0 ((uint32_t)0x00000001) #define RCC_USBHSPLLSRC_1 ((uint32_t)0x00000002) #define RCC_USBHSPLLSRC_HSE ((uint32_t)0x00000000) #define RCC_USBHSPLLSRC_HSI ((uint32_t)0x00000001) #define RCC_USBHSPLLSRC_ETHCLK_20M ((uint32_t)0x00000002) #define RCC_USBHSPLLSRC_PLLCLK ((uint32_t)0x00000003) #define RCC_USBHSPLL_REFSEL ((uint32_t)0x0000000C) #define RCC_USBHSPLL_REFSEL_0 ((uint32_t)0x00000004) #define RCC_USBHSPLL_REFSEL_1 ((uint32_t)0x00000008) #define RCC_USBHSPLL_REFSEL_25MHZ ((uint32_t)0x00000000) #define RCC_USBHSPLL_REFSEL_20MHZ ((uint32_t)0x00000004) #define RCC_USBHSPLL_REFSEL_24MHZ ((uint32_t)0x00000008) #define RCC_USBHSPLL_REFSEL_32MHZ ((uint32_t)0x0000000C) #define RCC_USBSSPLL_REFSEL ((uint32_t)0x00000070) #define RCC_USBSSPLL_REFSEL_0 ((uint32_t)0x00000010) #define RCC_USBSSPLL_REFSEL_1 ((uint32_t)0x00000020) #define RCC_USBSSPLL_REFSEL_2 ((uint32_t)0x00000030) #define RCC_USBSSPLL_REFSEL_20MHz ((uint32_t)0x00000000) #define RCC_USBSSPLL_REFSEL_24MHz ((uint32_t)0x00000010) #define RCC_USBSSPLL_REFSEL_25MHz ((uint32_t)0x00000020) #define RCC_USBSSPLL_REFSEL_30MHz ((uint32_t)0x00000030) #define RCC_USBSSPLL_REFSEL_32MHz ((uint32_t)0x00000040) #define RCC_USBSSPLL_REFSEL_40MHz ((uint32_t)0x00000050) #define RCC_USBSSPLL_REFSEL_60MHz ((uint32_t)0x00000060) #define RCC_USBSSPLL_REFSEL_80MHz ((uint32_t)0x00000070) #define RCC_USBHSPLL_IN_DIV ((uint32_t)0x00001F00) #define RCC_USBHSPLL_IN_DIV_0 ((uint32_t)0x00000100) #define RCC_USBHSPLL_IN_DIV_1 ((uint32_t)0x00000200) #define RCC_USBHSPLL_IN_DIV_2 ((uint32_t)0x00000400) #define RCC_USBHSPLL_IN_DIV_3 ((uint32_t)0x00000800) #define RCC_USBHSPLL_IN_DIV_4 ((uint32_t)0x00001000) #define RCC_USBHSPLL_IN_DIV1 ((uint32_t)0x00000000) #define RCC_USBHSPLL_IN_DIV2 ((uint32_t)0x00000100) #define RCC_USBHSPLL_IN_DIV3 ((uint32_t)0x00000200) #define RCC_USBHSPLL_IN_DIV4 ((uint32_t)0x00000300) #define RCC_USBHSPLL_IN_DIV5 ((uint32_t)0x00000400) #define RCC_USBHSPLL_IN_DIV6 ((uint32_t)0x00000500) #define RCC_USBHSPLL_IN_DIV7 ((uint32_t)0x00000600) #define RCC_USBHSPLL_IN_DIV8 ((uint32_t)0x00000700) #define RCC_USBHSPLL_IN_DIV9 ((uint32_t)0x00000800) #define RCC_USBHSPLL_IN_DIV10 ((uint32_t)0x00000900) #define RCC_USBHSPLL_IN_DIV11 ((uint32_t)0x00000A00) #define RCC_USBHSPLL_IN_DIV12 ((uint32_t)0x00000B00) #define RCC_USBHSPLL_IN_DIV13 ((uint32_t)0x00000C00) #define RCC_USBHSPLL_IN_DIV14 ((uint32_t)0x00000D00) #define RCC_USBHSPLL_IN_DIV15 ((uint32_t)0x00000E00) #define RCC_USBHSPLL_IN_DIV16 ((uint32_t)0x00000F00) #define RCC_USBHSPLL_IN_DIV17 ((uint32_t)0x00001000) #define RCC_USBHSPLL_IN_DIV18 ((uint32_t)0x00001100) #define RCC_USBHSPLL_IN_DIV19 ((uint32_t)0x00001200) #define RCC_USBHSPLL_IN_DIV20 ((uint32_t)0x00001300) #define RCC_USBHSPLL_IN_DIV21 ((uint32_t)0x00001400) #define RCC_USBHSPLL_IN_DIV22 ((uint32_t)0x00001500) #define RCC_USBHSPLL_IN_DIV23 ((uint32_t)0x00001600) #define RCC_USBHSPLL_IN_DIV24 ((uint32_t)0x00001700) #define RCC_USBHSPLL_IN_DIV25 ((uint32_t)0x00001800) #define RCC_USBHSPLL_IN_DIV26 ((uint32_t)0x00001900) #define RCC_USBHSPLL_IN_DIV27 ((uint32_t)0x00001A00) #define RCC_USBHSPLL_IN_DIV28 ((uint32_t)0x00001B00) #define RCC_USBHSPLL_IN_DIV29 ((uint32_t)0x00001C00) #define RCC_USBHSPLL_IN_DIV30 ((uint32_t)0x00001D00) #define RCC_USBHSPLL_IN_DIV31 ((uint32_t)0x00001E00) #define RCC_USBHSPLL_IN_DIV32 ((uint32_t)0x00001F00) #define RCC_SERDESPLL_MUL ((uint32_t)0x000F0000) #define RCC_SERDESPLL_MUL_0 ((uint32_t)0x00010000) #define RCC_SERDESPLL_MUL_1 ((uint32_t)0x00020000) #define RCC_SERDESPLL_MUL_2 ((uint32_t)0x00040000) #define RCC_SERDESPLL_MUL_3 ((uint32_t)0x00080000) #define RCC_SERDESPLL_MUL25 ((uint32_t)0x00000000) #define RCC_SERDESPLL_MUL28 ((uint32_t)0x00010000) #define RCC_SERDESPLL_MUL30 ((uint32_t)0x00020000) #define RCC_SERDESPLL_MUL32 ((uint32_t)0x00030000) #define RCC_SERDESPLL_MUL35 ((uint32_t)0x00040000) #define RCC_SERDESPLL_MUL38 ((uint32_t)0x00050000) #define RCC_SERDESPLL_MUL40 ((uint32_t)0x00060000) #define RCC_SERDESPLL_MUL45 ((uint32_t)0x00070000) #define RCC_SERDESPLL_MUL50 ((uint32_t)0x00080000) #define RCC_SERDESPLL_MUL56 ((uint32_t)0x00090000) #define RCC_SERDESPLL_MUL60 ((uint32_t)0x000A0000) #define RCC_SERDESPLL_MUL64 ((uint32_t)0x000B0000) #define RCC_SERDESPLL_MUL70 ((uint32_t)0x000C0000) #define RCC_SERDESPLL_MUL76 ((uint32_t)0x000D0000) #define RCC_SERDESPLL_MUL80 ((uint32_t)0x000E0000) #define RCC_SERDESPLL_MUL90 ((uint32_t)0x000F0000) /******************************************************************************/ /* RNG */ /******************************************************************************/ /******************** Bit definition for RNG_CR register *******************/ #define RNG_CR_RNGEN ((uint32_t)0x00000004) #define RNG_CR_IE ((uint32_t)0x00000008) /******************** Bit definition for RNG_SR register *******************/ #define RNG_SR_DRDY ((uint32_t)0x00000001) #define RNG_SR_CECS ((uint32_t)0x00000002) #define RNG_SR_SECS ((uint32_t)0x00000004) #define RNG_SR_CEIS ((uint32_t)0x00000020) #define RNG_SR_SEIS ((uint32_t)0x00000040) /******************************************************************************/ /* Real-Time Clock */ /******************************************************************************/ /******************* Bit definition for RTC_CTLRH register ********************/ #define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ #define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ #define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ /******************* Bit definition for RTC_CTLRL register ********************/ #define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ #define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ #define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ #define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ #define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ #define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ /******************* Bit definition for RTC_PSCRH register *******************/ #define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ /******************* Bit definition for RTC_PSCRL register *******************/ #define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ /******************* Bit definition for RTC_DIVH register *******************/ #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ /******************* Bit definition for RTC_DIVL register *******************/ #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ /******************* Bit definition for RTC_CNTH register *******************/ #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ /******************* Bit definition for RTC_CNTL register *******************/ #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ /******************* Bit definition for RTC_ALRMH register *******************/ #define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ /******************* Bit definition for RTC_ALRML register *******************/ #define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ /******************************************************************************/ /* Serial Peripheral Interface */ /******************************************************************************/ /******************* Bit definition for SPI_CTLR1 register ********************/ #define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ #define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ #define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ #define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ #define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ #define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ #define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ #define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ #define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ #define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ #define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ #define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ #define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ #define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ #define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ #define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ #define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ /******************* Bit definition for SPI_CTLR2 register ********************/ #define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ #define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ #define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ #define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ #define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ #define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_STATR register ********************/ #define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ #define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ #define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ #define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ #define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ #define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ #define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ #define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ /******************** Bit definition for SPI_DATAR register ********************/ #define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ /******************* Bit definition for SPI_CRCR register ******************/ #define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ /****************** Bit definition for SPI_RCRCR register ******************/ #define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ /****************** Bit definition for SPI_TCRCR register ******************/ #define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ /****************** Bit definition for SPI_I2SPR register *******************/ #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ #define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ /****************** Bit definition for SPI_HSCR register *******************/ #define SPI_HSCR_HSRXEN ((uint16_t)0x0001) #define SPI_HSCR_HSRXEN2 ((uint16_t)0x0004) /******************************************************************************/ /* TIM */ /******************************************************************************/ /******************* Bit definition for TIM_CTLR1 register ********************/ #define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ #define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ #define TIM_URS ((uint16_t)0x0004) /* Update request source */ #define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ #define TIM_DIR ((uint16_t)0x0010) /* Direction */ #define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ #define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ #define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ #define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ #define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ #define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ #define TIM_CAPOV ((uint16_t)0x4000) #define TIM_CAPLVL ((uint16_t)0x8000) /******************* Bit definition for TIM_CTLR2 register ********************/ #define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ #define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ #define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ #define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ #define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ #define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ #define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ #define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ #define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ #define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ #define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ #define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ #define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ #define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ #define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ /******************* Bit definition for TIM_SMCFGR register *******************/ #define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ #define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ #define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ #define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ #define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ #define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ #define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ #define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ #define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ #define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ #define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ #define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ #define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ #define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ #define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ #define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ #define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ #define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ /******************* Bit definition for TIM_DMAINTENR register *******************/ #define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ #define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ #define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ #define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ #define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ #define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ #define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ #define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ #define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ #define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ #define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ #define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ #define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ #define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ #define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ /******************** Bit definition for TIM_INTFR register ********************/ #define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ #define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ #define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ #define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ #define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ #define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ #define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ #define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ #define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ #define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ #define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ #define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ /******************* Bit definition for TIM_SWEVGR register ********************/ #define TIM_UG ((uint8_t)0x01) /* Update Generation */ #define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ #define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ #define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ #define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ #define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ #define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ #define TIM_BG ((uint8_t)0x80) /* Break Generation */ /****************** Bit definition for TIM_CHCTLR1 register *******************/ #define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ #define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ #define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ #define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ #define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ #define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ #define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ #define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ #define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ #define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ #define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ #define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ #define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ #define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ #define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ #define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ #define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ #define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ #define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ #define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ #define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ #define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ #define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ #define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ #define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ #define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ #define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ #define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ #define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ #define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ #define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ #define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ #define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ #define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ #define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ /****************** Bit definition for TIM_CHCTLR2 register *******************/ #define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ #define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ #define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ #define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ #define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ #define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ #define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ #define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ #define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ #define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ #define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ #define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ #define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ #define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ #define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ #define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ #define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ #define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ #define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ #define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ #define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ #define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ #define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ #define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ #define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ #define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ #define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ #define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ #define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ #define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ #define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ #define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ #define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ #define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ #define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ /******************* Bit definition for TIM_CCER register *******************/ #define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ #define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ #define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ #define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ #define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ #define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ #define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ #define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ #define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ #define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ #define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ #define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ #define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ #define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ /******************* Bit definition for TIM_CNT register ********************/ #define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ /******************* Bit definition for TIM_PSC register ********************/ #define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ /******************* Bit definition for TIM_ATRLR register ********************/ #define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ /******************* Bit definition for TIM_RPTCR register ********************/ #define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ /******************* Bit definition for TIM_CH1CVR register *******************/ #define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ #define TIM_LEVEL1 ((uint32_t)0x00010000) /******************* Bit definition for TIM_CH2CVR register *******************/ #define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ #define TIM_LEVEL2 ((uint32_t)0x00010000) /******************* Bit definition for TIM_CH3CVR register *******************/ #define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ #define TIM_LEVEL3 ((uint32_t)0x00010000) /******************* Bit definition for TIM_CH4CVR register *******************/ #define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ #define TIM_LEVEL4 ((uint32_t)0x00010000) /******************* Bit definition for TIM_BDTR register *******************/ #define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ #define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ #define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ #define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ #define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ #define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ #define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ #define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ #define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ #define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ #define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ #define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ #define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ #define TIM_BKE ((uint16_t)0x1000) /* Break enable */ #define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ #define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ #define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ /******************* Bit definition for TIM_DMACFGR register ********************/ #define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ #define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ #define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ #define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ #define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ #define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ #define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ #define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ #define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ #define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ #define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ /******************* Bit definition for TIM_DMAADR register *******************/ #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ /******************* Bit definition for TIM_AUX register *******************/ #define TIM_AUX_CAPCH2_ED ((uint16_t)0x0001) #define TIM_AUX_CAPCH3_ED ((uint16_t)0x0002) #define TIM_AUX_CAPCH4_ED ((uint16_t)0x0004) #define TIM_AUX_BK_SEL ((uint16_t)0x0038) #define TIM_AUX_BK_SEL_0 ((uint16_t)0x0008) #define TIM_AUX_BK_SEL_1 ((uint16_t)0x0010) #define TIM_AUX_BK_SEL_2 ((uint16_t)0x0020) #define TIM_AUX_DT_MODE ((uint16_t)0x0040) #define TIM_AUX_DTN_MODE ((uint16_t)0x0080) #define TIM_AUX_DT_VLU2 ((uint16_t)0xFF00) /******************************************************************************/ /* Universal Synchronous Asynchronous Receiver Transmitter */ /******************************************************************************/ /******************* Bit definition for USART_STATR register *******************/ #define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ #define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ #define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ #define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ #define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ #define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ #define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ #define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ #define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ #define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ #define USART_STATR_RX_BUSY ((uint16_t)0x0400) #define USART_STATR_MS_ERR ((uint16_t)0x0800) #define USART_STATR_USART_WKUP ((uint16_t)0x8000) /******************* Bit definition for USART_DATAR register *******************/ #define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ /****************** Bit definition for USART_BRR register *******************/ #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ /****************** Bit definition for USART_CTLR1 register *******************/ #define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ #define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ #define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ #define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ #define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ #define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ #define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ #define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ #define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ #define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ #define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ #define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ #define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ #define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ #define USART_CTLR1_M_EXT ((uint16_t)0xC000) #define USART_CTLR1_M_EXT_0 ((uint16_t)0x4000) #define USART_CTLR1_M_EXT_1 ((uint16_t)0x8000) #define USART_CTLR1_M_EXT5 ((uint16_t)0xC000) #define USART_CTLR1_M_EXT6 ((uint16_t)0x8000) #define USART_CTLR1_M_EXT7 ((uint16_t)0x4000) /****************** Bit definition for USART_CTLR2 register *******************/ #define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ #define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ #define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ #define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ #define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ #define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ #define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ #define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ #define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ #define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ #define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ /****************** Bit definition for USART_CTLR3 register *******************/ #define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ #define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ #define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ #define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ #define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ #define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ #define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ #define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ #define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ #define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ #define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ #define USART_CTLR3_LPWKUP_EN ((uint16_t)0x0800) #define USART_CTLR3_LPWKUP_CK_SRC ((uint16_t)0x1000) #define USART_CTLR3_LPWKUP_DLY_CFG ((uint16_t)0xE000) /****************** Bit definition for USART_GPR register ******************/ #define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ #define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ #define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ #define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ #define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ #define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ #define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ #define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ #define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ #define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ /****************** Bit definition for USART_CTLR4 register ******************/ #define USART_CTLR4_MS_ERRIE ((uint16_t)0x0002) #define USART_CTLR4_CHECK_SEL ((uint16_t)0x000C) #define USART_CTLR4_CHECK_MARKENABLE ((uint16_t)0x0008) #define USART_CTLR4_CHECK_APACEENABLE ((uint16_t)0x000C) /******************************************************************************/ /* OPA */ /******************************************************************************/ /******************* Bit definition for OPA_CTLR1 register ********************/ #define OPA_CTLR1_EN1 ((uint16_t)0x0001) #define OPA_CTLR1_MODE1 ((uint16_t)0x0006) #define OPA_CTLR1_MODE1_0 ((uint16_t)0x0002) #define OPA_CTLR1_MODE1_1 ((uint16_t)0x0004) #define OPA_CTLR1_PSEL1 ((uint16_t)0x0008) #define OPA_CTLR1_NSEL1 ((uint16_t)0x0070) #define OPA_CTLR1_NSEL1_0 ((uint16_t)0x0010) #define OPA_CTLR1_NSEL1_1 ((uint16_t)0x0020) #define OPA_CTLR1_NSEL1_2 ((uint16_t)0x0030) #define OPA_CTLR1_FBEN1 ((uint16_t)0x0100) #define OPA_CTLR1_PGADIF1 ((uint16_t)0x0200) #define OPA_CTLR1_HS1 ((uint16_t)0x0400) /******************* Bit definition for OPA_CTLR2 register ********************/ #define OPA_CTLR2_EN2 ((uint16_t)0x0001) #define OPA_CTLR2_MODE2 ((uint16_t)0x0006) #define OPA_CTLR2_MODE2_0 ((uint16_t)0x0002) #define OPA_CTLR2_MODE2_1 ((uint16_t)0x0004) #define OPA_CTLR2_PSEL2 ((uint16_t)0x0008) #define OPA_CTLR2_NSEL2 ((uint16_t)0x0070) #define OPA_CTLR2_NSEL2_0 ((uint16_t)0x0010) #define OPA_CTLR2_NSEL2_1 ((uint16_t)0x0020) #define OPA_CTLR2_NSEL2_2 ((uint16_t)0x0030) #define OPA_CTLR2_FBEN2 ((uint16_t)0x0100) #define OPA_CTLR2_PGADIF2 ((uint16_t)0x0200) #define OPA_CTLR2_HS2 ((uint16_t)0x0400) /******************* Bit definition for OPA_CTLR3 register ********************/ #define OPA_CTLR3_EN3 ((uint16_t)0x0001) #define OPA_CTLR3_MODE3 ((uint16_t)0x0006) #define OPA_CTLR3_MODE3_0 ((uint16_t)0x0002) #define OPA_CTLR3_MODE3_1 ((uint16_t)0x0004) #define OPA_CTLR3_PSEL3 ((uint16_t)0x0008) #define OPA_CTLR3_NSEL3 ((uint16_t)0x0070) #define OPA_CTLR3_NSEL3_0 ((uint16_t)0x0010) #define OPA_CTLR3_NSEL3_1 ((uint16_t)0x0020) #define OPA_CTLR3_NSEL3_2 ((uint16_t)0x0030) #define OPA_CTLR3_FBEN3 ((uint16_t)0x0100) #define OPA_CTLR3_PGADIF3 ((uint16_t)0x0200) #define OPA_CTLR3_HS3 ((uint16_t)0x0400) /******************* Bit definition for CMP_CTLR register ********************/ #define OPA_CMP_CTLR_PSEL ((uint32_t)0x00000003) #define OPA_CMP_CTLR_PSEL_0 ((uint32_t)0x00000001) #define OPA_CMP_CTLR_PSEL_1 ((uint32_t)0x00000002) #define OPA_CMP_CTLR_NSEL ((uint32_t)0x0000000C) #define OPA_CMP_CTLR_NSEL_0 ((uint32_t)0x00000004) #define OPA_CMP_CTLR_NSEL_1 ((uint32_t)0x00000008) #define OPA_CMP_CTLR_MODE ((uint32_t)0x000000F0) #define OPA_CMP_CTLR_MODE_0 ((uint32_t)0x00000010) #define OPA_CMP_CTLR_MODE_1 ((uint32_t)0x00000020) #define OPA_CMP_CTLR_MODE_2 ((uint32_t)0x00000040) #define OPA_CMP_CTLR_MODE_3 ((uint32_t)0x00000080) #define OPA_CMP_CTLR_EN ((uint32_t)0x00000100) #define OPA_CMP_CTLR_HYPSEL ((uint32_t)0x00000600) #define OPA_CMP_CTLR_HYPSEL_0 ((uint32_t)0x00000200) #define OPA_CMP_CTLR_HYPSEL_1 ((uint32_t)0x00000400) #define OPA_CMP_CTLR_VREF ((uint32_t)0x00001800) #define OPA_CMP_CTLR_VREF_0 ((uint32_t)0x00000800) #define OPA_CMP_CTLR_VREF_1 ((uint32_t)0x00001000) #define OPA_CMP_CTLR_FILT_EN ((uint32_t)0x00002000) #define OPA_CMP_CTLR_FILT_CFG ((uint32_t)0x01FF0000) #define OPA_CMP_CTLR_FILT_BASE ((uint32_t)0x70000000) /******************* Bit definition for CMP_STATR register ********************/ #define OPA_CMP_STATR_OUTFILT ((uint8_t)0x01) /******************************************************************************/ /* Window WATCHDOG */ /******************************************************************************/ /******************* Bit definition for WWDG_CTLR register ********************/ #define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ #define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ #define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ #define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ #define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ #define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ #define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ #define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ #define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ /******************* Bit definition for WWDG_CFGR register *******************/ #define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ #define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ #define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ #define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ #define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ #define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ #define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ #define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ #define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ #define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ #define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ #define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ /******************* Bit definition for WWDG_STATR register ********************/ #define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ /******************************************************************************/ /* DVP */ /******************************************************************************/ /******************* Bit definition for DVP_CR0 register ********************/ #define RB_DVP_ENABLE 0x01 // RW, DVP enable #define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert #define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert #define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert #define RB_DVP_MSK_DAT_MOD 0x30 #define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode #define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode #define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode #define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode /******************* Bit definition for DVP_CR1 register ********************/ #define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable #define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action #define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action #define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 #define RB_DVP_CM 0x10 // RW, DVP capture mode #define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable #define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: #define DVP_RATE_100P 0x00 // 00 = every frame captured (100%) #define DVP_RATE_50P 0x40 // 01 = every alternate frame captured (50%) #define DVP_RATE_25P 0x80 // 10 = one frame in four frame captured (25%) /******************* Bit definition for DVP_IER register ********************/ #define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable #define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable #define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable #define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable #define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable /******************* Bit definition for DVP_ROW_NUM register ********************/ #define RB_DVP_ROW_NUM ((uint16_t)0xFFFF) /******************* Bit definition for DVP_COL_NUM register ********************/ #define RB_DVP_COL_NUM ((uint16_t)0xFFFF) /******************* Bit definition for DVP_DMA_BUF0 register ********************/ #define RB_DVP_DMA_BUF0 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for DVP_DMA_BUF1 register ********************/ #define RB_DVP_DMA_BUF1 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for DVP_IFR register ********************/ #define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start #define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done #define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done #define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow #define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop /******************* Bit definition for DVP_STATUS register ********************/ #define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready #define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full #define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow #define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count /******************* Bit definition for DVP_ROW_CNT register ********************/ #define RB_DVP_ROW_CNT ((uint16_t)0xFF) /******************* Bit definition for DVP_HOFFCNT register ********************/ #define RB_DVP_HOFFCNT ((uint16_t)0xFF) /******************* Bit definition for DVP_VST register ********************/ #define RB_DVP_VST ((uint16_t)0xFF) /******************* Bit definition for DVP_CAPCNT register ********************/ #define RB_DVP_CAPCNT ((uint16_t)0xFF) /******************* Bit definition for DVP_VLINE register ********************/ #define RB_DVP_VLINE ((uint16_t)0xFF) /******************* Bit definition for DVP_DR register ********************/ #define RB_DVP_DR ((uint16_t)0xFF) /******************************************************************************/ /* TKEY */ /******************************************************************************/ /******************* Bit definition for TKEY_CHARGE1 register *******************/ #define TKEY_CHARGE1_TKCG10 ((uint32_t)0x0007) #define TKEY_CHARGE1_TKCG10_1C5 ((uint32_t)0x0000) #define TKEY_CHARGE1_TKCG10_7C5 ((uint32_t)0x0001) #define TKEY_CHARGE1_TKCG10_13C5 ((uint32_t)0x0002) #define TKEY_CHARGE1_TKCG10_28C5 ((uint32_t)0x0003) #define TKEY_CHARGE1_TKCG10_41C5 ((uint32_t)0x0004) #define TKEY_CHARGE1_TKCG10_55C5 ((uint32_t)0x0005) #define TKEY_CHARGE1_TKCG10_71C5 ((uint32_t)0x0006) #define TKEY_CHARGE1_TKCG10_239C5 ((uint32_t)0x0007) #define TKEY_CHARGE1_TKCG11 ((uint32_t)0x0038) #define TKEY_CHARGE1_TKCG11_1C5 ((uint32_t)0x0000) #define TKEY_CHARGE1_TKCG11_7C5 ((uint32_t)0x0008) #define TKEY_CHARGE1_TKCG11_13C5 ((uint32_t)0x0010) #define TKEY_CHARGE1_TKCG11_28C5 ((uint32_t)0x0018) #define TKEY_CHARGE1_TKCG11_41C5 ((uint32_t)0x0020) #define TKEY_CHARGE1_TKCG11_55C5 ((uint32_t)0x0028) #define TKEY_CHARGE1_TKCG11_71C5 ((uint32_t)0x0030) #define TKEY_CHARGE1_TKCG11_239C5 ((uint32_t)0x0038) #define TKEY_CHARGE1_TKCG12 ((uint32_t)0x01C0) #define TKEY_CHARGE1_TKCG12_1C5 ((uint32_t)0x0000) #define TKEY_CHARGE1_TKCG12_7C5 ((uint32_t)0x0040) #define TKEY_CHARGE1_TKCG12_13C5 ((uint32_t)0x0080) #define TKEY_CHARGE1_TKCG12_28C5 ((uint32_t)0x00C0) #define TKEY_CHARGE1_TKCG12_41C5 ((uint32_t)0x0100) #define TKEY_CHARGE1_TKCG12_55C5 ((uint32_t)0x0140) #define TKEY_CHARGE1_TKCG12_71C5 ((uint32_t)0x0180) #define TKEY_CHARGE1_TKCG12_239C5 ((uint32_t)0x01C0) #define TKEY_CHARGE1_TKCG13 ((uint32_t)0x0E00) #define TKEY_CHARGE1_TKCG13_1C5 ((uint32_t)0x0000) #define TKEY_CHARGE1_TKCG13_7C5 ((uint32_t)0x0200) #define TKEY_CHARGE1_TKCG13_13C5 ((uint32_t)0x0400) #define TKEY_CHARGE1_TKCG13_28C5 ((uint32_t)0x0600) #define TKEY_CHARGE1_TKCG13_41C5 ((uint32_t)0x0800) #define TKEY_CHARGE1_TKCG13_55C5 ((uint32_t)0x0A00) #define TKEY_CHARGE1_TKCG13_71C5 ((uint32_t)0x0C00) #define TKEY_CHARGE1_TKCG13_239C5 ((uint32_t)0x0E00) #define TKEY_CHARGE1_TKCG14 ((uint32_t)0x7000) #define TKEY_CHARGE1_TKCG15 ((uint32_t)0x38000) /******************************************************************************/ /* SDMMC */ /******************************************************************************/ /******************* Bit definition for SDMMC_ARGUMENT register *******************/ #define SDMMC_ARGUMENT ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_CMD_SET register *******************/ #define SDMMC_CMDIDX_MASK ((uint16_t)0x003F) #define SDMMC_RPTY_MASK ((uint16_t)0x0300) #define SDMMC_CKCRC ((uint16_t)0x0400) #define SDMMC_CKIDX ((uint16_t)0x0800) /******************* Bit definition for SDMMC_RESPONSE0 register *******************/ #define SDMMC_RESPONSE0 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_RESPONSE1 register *******************/ #define SDMMC_RESPONSE1 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_RESPONSE2 register *******************/ #define SDMMC_RESPONSE2 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_RESPONSE3 register *******************/ #define SDMMC_RESPONSE3 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_WRITE_CONT register *******************/ #define SDMMC_WRITE_CONT ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_CONTROL register *******************/ #define SDMMC_LW_MASK ((uint16_t)0x0003) #define SDMMC_LW_MASK_0 ((uint16_t)0x0001) #define SDMMC_LW_MASK_1 ((uint16_t)0x0002) #define SDMMC_ALL_CLR ((uint16_t)0x0004) #define SDMMC_DMAEN ((uint16_t)0x0008) #define SDMMC_RST_LGC ((uint16_t)0x0010) #define SDMMC_NEGSMP ((uint16_t)0x0020) #define SDMMC_SLV_MODE ((uint16_t)0x0100) #define SDMMC_SLV_FORCE_ERR ((uint16_t)000200) /******************* Bit definition for SDMMC_TIMEOUT register *******************/ #define SDMMC_TOCNT_MASK ((uint8_t)0x0F) /******************* Bit definition for SDMMC_STATUS register *******************/ #define SDMMC_MASK_BLOCK_NUM ((uint16_t)0xFFFF) #define SDMMC_CMDSTA ((uint32_t)0x00010000) #define SDMMC_DAT0STA ((uint32_t)0x00020000) /******************* Bit definition for SDMMC_INT_FG register *******************/ #define SDMMC_IF_RE_TMOUT ((uint16_t)0x0001) #define SDMMC_IF_RECRC_WR ((uint16_t)0x0002) #define SDMMC_IF_REIDX_ER ((uint16_t)0x0004) #define SDMMC_IF_CMDDONE ((uint16_t)0x0008) #define SDMMC_IF_DATTMO ((uint16_t)0x0010) #define SDMMC_IF_TRANERR ((uint16_t)0x0020) #define SDMMC_IF_TRANDONE ((uint16_t)0x0040) #define SDMMC_IF_BKGAP ((uint16_t)0x0080) #define SDMMC_IF_FIFO_OV ((uint16_t)0x0100) #define SDMMC_IF_SDIOINT ((uint16_t)0x0200) #define SDMMC_SIF_SLV_BUF_RELEAS ((uint16_t)0x0400) /******************* Bit definition for SDMMC_INT_EN register *******************/ #define SDMMC_IE_RE_TMOUT ((uint16_t)0x0001) #define SDMMC_IE_RECRC_WR ((uint16_t)0x0002) #define SDMMC_IE_REIDX_ER ((uint16_t)0x0004) #define SDMMC_IE_CMDDONE ((uint16_t)0x0008) #define SDMMC_IE_DATTMO ((uint16_t)0x0010) #define SDMMC_IE_TRANERR ((uint16_t)0x0020) #define SDMMC_IE_TRANDONE ((uint16_t)0x0040) #define SDMMC_IE_FIFO_OV ((uint16_t)0x0080) #define SDMMC_IE_SDIOINT ((uint16_t)0x0100) /******************* Bit definition for SDMMC_DMA_BEG1 register *******************/ #define SDMMC_DMAAD1_MASK ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_BLOCK_CFG register *******************/ #define SDMMC_BKNUM_MASK ((uint32_t)0x0000FFFF) #define SDMMC_BKSIZE_MASK ((uint32_t)0x0FFF0000) /******************* Bit definition for SDMMC_TRAN_MODE register *******************/ #define SDMMC_DMA_DIR ((uint32_t)0x00000001) #define SDMMC_GAP_STOP ((uint32_t)0x00000002) #define SDMMC_MODE_BOOT ((uint32_t)0x00000004) #define SDMMC_AUTOGAPSTOP ((uint32_t)0x00000010) #define SDMMC_DMATN_CNT ((uint32_t)0x00007F00) #define SDMMC_DULEDMA_EN ((uint32_t)0x00010000) #define SDMMC_DDR_MODE ((uint32_t)0x00020000) #define SDMMC_CARE_NEG ((uint32_t)0x00040000) #define SDMMC_SW ((uint32_t)0x00180000) #define SDMMC_SW_0 ((uint32_t)0x00080000) #define SDMMC_SW_1 ((uint32_t)0x00100000) /******************* Bit definition for SDMMC_CLK_DIV register *******************/ #define SDMMC_DIV_MASK ((uint32_t)0x0000001F) #define SDMMC_CLKOE ((uint32_t)0x00000100) #define SDMMC_CLKMode ((uint32_t)0x00000200) #define SDMMC_PHASEINV ((uint32_t)0x00000400) /******************* Bit definition for SDMMC_DMA_BEG2 register *******************/ #define SDMMC_DMAAD2_MASK ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SDMMC_TUNE_DATO register *******************/ #define SDMMC_TUNNE_DAT0_O ((uint32_t)0x0000000F) #define SDMMC_TUNNE_DAT1_O ((uint32_t)0x000000F0) #define SDMMC_TUNNE_DAT2_O ((uint32_t)0x00000F00) #define SDMMC_TUNNE_DAT3_O ((uint32_t)0x0000F000) #define SDMMC_TUNNE_DAT4_O ((uint32_t)0x000F0000) #define SDMMC_TUNNE_DAT5_O ((uint32_t)0x00F00000) #define SDMMC_TUNNE_DAT6_O ((uint32_t)0x0F000000) #define SDMMC_TUNNE_DAT7_O ((uint32_t)0xF0000000) /******************* Bit definition for SDMMC_TUNE_DATI register *******************/ #define SDMMC_TUNNE_DAT0_I ((uint32_t)0x0000000F) #define SDMMC_TUNNE_DAT1_I ((uint32_t)0x000000F0) #define SDMMC_TUNNE_DAT2_I ((uint32_t)0x00000F00) #define SDMMC_TUNNE_DAT3_I ((uint32_t)0x0000F000) #define SDMMC_TUNNE_DAT4_I ((uint32_t)0x000F0000) #define SDMMC_TUNNE_DAT5_I ((uint32_t)0x00F00000) #define SDMMC_TUNNE_DAT6_I ((uint32_t)0x0F000000) #define SDMMC_TUNNE_DAT7_I ((uint32_t)0xF0000000) /******************* Bit definition for SDMMC_TUNE_CLK_CMD register *******************/ #define SDMMC_TUNNE_CLK_O ((uint32_t)0x0000000F) #define SDMMC_TUNNE_CLK_I ((uint32_t)0x000000F0) #define SDMMC_TUNNE_CMD_O ((uint32_t)0x000F0000) #define SDMMC_TUNNE_CMD_I ((uint32_t)0x00F00000) /******************* Bit definition for SDMMC_ARGUMENT register *******************/ #define EMMC_ARGUMENT SDMMC_ARGUMENT /******************* Bit definition for SDMMC_CMD_SET register *******************/ #define EMMC_CMDIDX_MASK SDMMC_CMDIDX_MASK #define EMMC_RPTY_MASK SDMMC_RPTY_MASK #define EMMC_CKCRC SDMMC_CKCRC #define EMMC_CKIDX SDMMC_CKIDX /******************* Bit definition for SDMMC_RESPONSE0 register *******************/ #define EMMC_RESPONSE0 SDMMC_RESPONSE0 /******************* Bit definition for SDMMC_RESPONSE1 register *******************/ #define EMMC_RESPONSE1 SDMMC_RESPONSE1 /******************* Bit definition for SDMMC_RESPONSE2 register *******************/ #define EMMC_RESPONSE2 SDMMC_RESPONSE2 /******************* Bit definition for SDMMC_RESPONSE3 register *******************/ #define EMMC_RESPONSE3 SDMMC_RESPONSE3 /******************* Bit definition for SDMMC_WRITE_CONT register *******************/ #define EMMC_WRITE_CONT SDMMC_WRITE_CONT /******************* Bit definition for SDMMC_CONTROL register *******************/ #define EMMC_LW_MASK SDMMC_LW_MASK #define EMMC_LW_MASK_0 SDMMC_LW_MASK_0 #define EMMC_LW_MASK_1 SDMMC_LW_MASK_1 #define EMMC_ALL_CLR SDMMC_ALL_CLR #define EMMC_DMAEN SDMMC_DMAEN #define EMMC_RST_LGC SDMMC_RST_LGC #define EMMC_NEGSMP SDMMC_NEGSMP #define EMMC_SLV_MODE SDMMC_SLV_MODE #define EMMC_SLV_FORCE_ERR SDMMC_SLV_FORCE_ERR /******************* Bit definition for SDMMC_TIMEOUT register *******************/ #define EMMC_TOCNT_MASK SDMMC_TOCNT_MASK /******************* Bit definition for SDMMC_STATUS register *******************/ #define EMMC_MASK_BLOCK_NUM SDMMC_MASK_BLOCK_NUM #define EMMC_CMDSTA SDMMC_CMDSTA #define EMMC_DAT0STA SDMMC_DAT0STA /******************* Bit definition for SDMMC_INT_FG register *******************/ #define EMMC_IF_RE_TMOUT SDMMC_IF_RE_TMOUT #define EMMC_IF_RECRC_WR SDMMC_IF_RECRC_WR #define EMMC_IF_REIDX_ER SDMMC_IF_REIDX_ER #define EMMC_IF_CMDDONE SDMMC_IF_CMDDONE #define EMMC_IF_DATTMO SDMMC_IF_DATTMO #define EMMC_IF_TRANERR SDMMC_IF_TRANERR #define EMMC_IF_TRANDONE SDMMC_IF_TRANDONE #define EMMC_IF_BKGAP SDMMC_IF_BKGAP #define EMMC_IF_FIFO_OV SDMMC_IF_FIFO_OV #define EMMC_IF_SDIOINT SDMMC_IF_SDIOINT #define EMMC_SIF_SLV_BUF_RELEAS SDMMC_SIF_SLV_BUF_RELEAS /******************* Bit definition for SDMMC_INT_EN register *******************/ #define EMMC_IE_RE_TMOUT SDMMC_IE_RE_TMOUT #define EMMC_IE_RECRC_WR SDMMC_IE_RECRC_WR #define EMMC_IE_REIDX_ER SDMMC_IE_REIDX_ER #define EMMC_IE_CMDDONE SDMMC_IE_CMDDONE #define EMMC_IE_DATTMO SDMMC_IE_DATTMO #define EMMC_IE_TRANERR SDMMC_IE_TRANERR #define EMMC_IE_TRANDONE SDMMC_IE_TRANDONE #define EMMC_IE_FIFO_OV SDMMC_IE_FIFO_OV #define EMMC_IE_SDIOINT SDMMC_IE_SDIOINT /******************* Bit definition for SDMMC_DMA_BEG1 register *******************/ #define EMMC_DMAAD1_MASK SDMMC_DMAAD1_MASK /******************* Bit definition for SDMMC_BLOCK_CFG register *******************/ #define EMMC_BKNUM_MASK SDMMC_BKNUM_MASK #define EMMC_BKSIZE_MASK SDMMC_BKSIZE_MASK /******************* Bit definition for SDMMC_TRAN_MODE register *******************/ #define EMMC_DMA_DIR SDMMC_DMA_DIR #define EMMC_GAP_STOP SDMMC_GAP_STOP #define EMMC_MODE_BOOT SDMMC_MODE_BOOT #define EMMC_AUTOGAPSTOP SDMMC_AUTOGAPSTOP #define EMMC_DMATN_CNT SDMMC_DMATN_CNT #define EMMC_DULEDMA_EN SDMMC_DULEDMA_EN #define EMMC_DDR_MODE SDMMC_DDR_MODE #define EMMC_CARE_NEG SDMMC_CARE_NEG #define EMMC_SW SDMMC_SW #define EMMC_SW_0 SDMMC_SW_0 #define EMMC_SW_1 SDMMC_SW_1 /******************* Bit definition for SDMMC_CLK_DIV register *******************/ #define EMMC_DIV_MASK SDMMC_DIV_MASK #define EMMC_CLKOE SDMMC_CLKOE #define EMMC_CLKMode SDMMC_CLKMode #define EMMC_PHASEINV SDMMC_PHASEINV /******************* Bit definition for SDMMC_DMA_BEG2 register *******************/ #define EMMC_DMAAD2_MASK SDMMC_DMAAD2_MASK /******************* Bit definition for SDMMC_TUNE_DATO register *******************/ #define EMMC_TUNNE_DAT0_O SDMMC_TUNNE_DAT0_O #define EMMC_TUNNE_DAT1_O SDMMC_TUNNE_DAT1_O #define EMMC_TUNNE_DAT2_O SDMMC_TUNNE_DAT2_O #define EMMC_TUNNE_DAT3_O SDMMC_TUNNE_DAT3_O #define EMMC_TUNNE_DAT4_O SDMMC_TUNNE_DAT4_O #define EMMC_TUNNE_DAT5_O SDMMC_TUNNE_DAT5_O #define EMMC_TUNNE_DAT6_O SDMMC_TUNNE_DAT6_O #define EMMC_TUNNE_DAT7_O SDMMC_TUNNE_DAT7_O /******************* Bit definition for SDMMC_TUNE_DATI register *******************/ #define EMMC_TUNNE_DAT0_I SDMMC_TUNNE_DAT0_I #define EMMC_TUNNE_DAT1_I SDMMC_TUNNE_DAT1_I #define EMMC_TUNNE_DAT2_I SDMMC_TUNNE_DAT2_I #define EMMC_TUNNE_DAT3_I SDMMC_TUNNE_DAT3_I #define EMMC_TUNNE_DAT4_I SDMMC_TUNNE_DAT4_I #define EMMC_TUNNE_DAT5_I SDMMC_TUNNE_DAT5_I #define EMMC_TUNNE_DAT6_I SDMMC_TUNNE_DAT6_I #define EMMC_TUNNE_DAT7_I SDMMC_TUNNE_DAT7_I /******************* Bit definition for SDMMC_TUNE_CLK_CMD register *******************/ #define EMMC_TUNNE_CLK_O SDMMC_TUNNE_CLK_O #define EMMC_TUNNE_CLK_I SDMMC_TUNNE_CLK_I #define EMMC_TUNNE_CMD_O SDMMC_TUNNE_CMD_O #define EMMC_TUNNE_CMD_I SDMMC_TUNNE_CMD_I /******************************************************************************/ /* SAI */ /******************************************************************************/ /******************* Bit definition for SAI_xCFGR1 register *******************/ #define SAI_CFGR1_MODE ((uint32_t)0x00000003) #define SAI_CFGR1_MODE_0 ((uint32_t)0x00000001) #define SAI_CFGR1_MODE_1 ((uint32_t)0x00000002) #define SAI_CFGR1_PRTCFG ((uint32_t)0x0000000C) #define SAI_CFGR1_PRTCFG_0 ((uint32_t)0x00000004) #define SAI_CFGR1_PRTCFG_1 ((uint32_t)0x00000008) #define SAI_CFGR1_DS ((uint32_t)0x000000E0) #define SAI_CFGR1_DS_0 ((uint32_t)0x00000020) #define SAI_CFGR1_DS_1 ((uint32_t)0x00000040) #define SAI_CFGR1_DS_2 ((uint32_t)0x00000080) #define SAI_CFGR1_LSBFIRST ((uint32_t)0x00000100) #define SAI_CFGR1_CKSTR ((uint32_t)0x00000200) #define SAI_CFGR1_SYNCEN ((uint32_t)0x00000C00) #define SAI_CFGR1_SYNCEN_0 ((uint32_t)0x00000400) #define SAI_CFGR1_SYNCEN_1 ((uint32_t)0x00000800) #define SAI_CFGR1_MONO ((uint32_t)0x00001000) #define SAI_CFGR1_EN ((uint32_t)0x00010000) #define SAI_CFGR1_DMAEN ((uint32_t)0x00020000) #define SAI_CFGR1_NODIV ((uint32_t)0x00080000) #define SAI_CFGR1_MCKDIV ((uint32_t)0x03F00000) #define SAI_CFGR1_OSR ((uint32_t)0x04000000) /******************* Bit definition for SAI_xCFGR2 register *******************/ #define SAI_CFGR2_FTH ((uint32_t)0x00000007) #define SAI_CFGR2_FTH_0 ((uint32_t)0x00000001) #define SAI_CFGR2_FTH_1 ((uint32_t)0x00000002) #define SAI_CFGR2_FTH_2 ((uint32_t)0x00000004) #define SAI_CFGR2_FFLUSH ((uint32_t)0x00000008) #define SAI_CFGR2_TRIS ((uint32_t)0x00000010) #define SAI_CFGR2_MUTE ((uint32_t)0x00000020) #define SAI_CFGR2_MUTEVAL ((uint32_t)0x00000040) #define SAI_CFGR2_MUTECNT ((uint32_t)0x00001F80) #define SAI_CFGR2_CPL ((uint32_t)0x00002000) #define SAI_CFGR2_COMP ((uint32_t)0x0000C000) /******************* Bit definition for SAI_xFRCR register *******************/ #define SAI_FRCR_FRL ((uint32_t)0x000000FF) #define SAI_FRCR_FSALL ((uint32_t)0x00007F00) #define SAI_FRCR_FSDEF ((uint32_t)0x00010000) #define SAI_FRCR_FSPOL ((uint32_t)0x00020000) #define SAI_FRCR_FSOFF ((uint32_t)0x00040000) /******************* Bit definition for SAI_xSLOTR register *******************/ #define SAI_SLOTR_FBOFF ((uint32_t)0x0000001F) #define SAI_SLOTR_SLOTSZ ((uint32_t)0x000000C0) #define SAI_SLOTR_NBSLOT ((uint32_t)0x00000F00) #define SAI_SLOTR_SLOTEN ((uint32_t)0xFFFF0000) /******************* Bit definition for SAI_xINTENR register *******************/ #define SAI_INTENR_OVRUDRIE ((uint32_t)0x00000001) #define SAI_INTENR_MUTEDETIE ((uint32_t)0x00000002) #define SAI_INTENR_WCKCFGIE ((uint32_t)0x00000004) #define SAI_INTENR_FREQIE ((uint32_t)0x00000008) #define SAI_INTENR_CNRDYIE ((uint32_t)0x00000010) #define SAI_INTENR_AFSDETIE ((uint32_t)0x00000020) #define SAI_INTENR_LFSDETIE ((uint32_t)0x00000040) /********************* Bit definition for SAI_xSR register *********************/ #define SAI_SR_OVRUDR ((uint32_t)0x00000001) #define SAI_SR_MUTEDET ((uint32_t)0x00000002) #define SAI_SR_WCKCFG ((uint32_t)0x00000004) #define SAI_SR_FREQ ((uint32_t)0x00000008) #define SAI_SR_CNRDY ((uint32_t)0x00000010) #define SAI_SR_AFSDET ((uint32_t)0x00000020) #define SAI_SR_LFSDET ((uint32_t)0x00000040) #define SAI_SR_FLTH ((uint32_t)0x00070000) #define SAI_SR_FLTH_0 ((uint32_t)0x00010000) #define SAI_SR_FLTH_1 ((uint32_t)0x00020000) #define SAI_SR_FLTH_2 ((uint32_t)0x00030000) /********************* Bit definition for SAI_xDATAR register *********************/ #define SAI_DATAR_DR ((uint32_t)0xFFFFFFFF) /******************************************************************************/ /* SERDES */ /******************************************************************************/ /********************* Bit definition for SERDES_CTRL register *********************/ #define SDS_CLR_ALL ((uint32_t)0x00000001) #define SDS_RESET_LINK ((uint32_t)0x00000002) #define SDS_RESET_PHY ((uint32_t)0x00000004) #define SDS_INT_BUSY_EN ((uint32_t)0x00000008) #define SDS_RX_POLARITY ((uint32_t)0x00000010) #define SDS_RX_EN ((uint32_t)0x00000020) #define SDS_TX_EN ((uint32_t)0x00000040) #define SDS_DMA_EN ((uint32_t)0x00000080) #define SDS_PLL_FACTOR ((uint32_t)0x00001F00) #define SDS_PLL_PWR_UP ((uint32_t)0x00002000) #define SDS_RX_PWR_UP ((uint32_t)0x00004000) #define SDS_TX_PWR_UP ((uint32_t)0x00008000) #define SDS_PHY_PWR_UP ((uint32_t)0x00010000) #define SDS_CONT_EN ((uint32_t)0x00020000) #define SDS_ALIGN_EN ((uint32_t)0x00040000) /********************* Bit definition for SERDES_INT_EN register *********************/ #define SDS_PHYRDY_IE ((uint32_t)0x00000001) #define SDS_RECV_ERR_IE ((uint32_t)0x00000002) #define SDS_TRAN_DONE_IE ((uint32_t)0x00000002) #define SDS_RECV_DONE_IE ((uint32_t)0x00000004) #define SDS_FIFO_OV_IE ((uint32_t)0x00000008) #define SDS_COMINIT_IE ((uint32_t)0x00000020) /********************* Bit definition for SERDES_INT_FG register *********************/ #define SDS_PHYRDY_IF ((uint32_t)0x00000001) #define SDS_RECV_ERR_IF ((uint32_t)0x00000002) #define SDS_TRAN_DONE_IF ((uint32_t)0x00000002) #define SDS_RECV_DONE_IF ((uint32_t)0x00000004) #define SDS_FIFO_OV_IF ((uint32_t)0x00000008) #define SDS_COMINIT_IF ((uint32_t)0x00000020) #define SDS_PHYRDY ((uint32_t)0x00010000) #define SDS_RX_SEQ_MATCH ((uint32_t)0x00020000) #define SDS_RECV_CRC_OK ((uint32_t)0x00040000) #define SDS_PLL_LOCK ((uint32_t)0x00080000) #define SDS_LINK_FREE ((uint32_t)0x00100000) #define SDS_R_FIFO_RDY ((uint32_t)0x00200000) #define SDS_RX_SEQ_NUM ((uint32_t)0x0F000000) #define SDS_TX_SEQ_NUM ((uint32_t)0xF0000000) /********************* Bit definition for SERDES_RTX_CTRL register *********************/ #define SDS_SERDES_TX_LEN ((uint32_t)0x0000FFFF) #define SDS_LINK_INIT ((uint32_t)0x00010000) #define SDS_TX_VLD ((uint32_t)0x00020000) #define SDS_BUF_MODE ((uint32_t)0x00040000) /********************* Bit definition for SERDES_RX_LEN0 register *********************/ #define SDS_SERDES_RX_LEN0 ((uint32_t)0x0000FFFF) /********************* Bit definition for SERDES_DATA0 register *********************/ #define SDS_SERDES_DATA0 ((uint32_t)0xFFFFFFFF) /********************* Bit definition for SERDES_DMA0 register *********************/ #define SDS_SERDES_DMA0 ((uint32_t)0xFFFFFFFF) /********************* Bit definition for SERDES_RX_LEN1 register *********************/ #define SDS_SERDES_RX_LEN1 ((uint32_t)0x0000FFFF) /********************* Bit definition for SERDES_DATA1 register *********************/ #define SDS_SERDES_DATA1 ((uint32_t)0xFFFFFFFF) /********************* Bit definition for SERDES_DMA1 register *********************/ #define SDS_SERDES_DMA1 ((uint32_t)0xFFFFFFFF) /******************************************************************************/ /* SWPMI */ /******************************************************************************/ /******************* Bit definition for SWPMI_CR register *******************/ #define SWPMI_RXDMA ((uint32_t)0x00000001) #define SWPMI_TXDMA ((uint32_t)0x00000002) #define SWPMI_RXMODE ((uint32_t)0x00000004) #define SWPMI_TXMODE ((uint32_t)0x00000008) #define SWPMI_LPBK ((uint32_t)0x00000010) #define SWPMI_SWPACT ((uint32_t)0x00000020) #define SWPMI_DEACT ((uint32_t)0x00000400) #define SWPMI_SWPTEN ((uint32_t)0x00000800) /******************* Bit definition for SWPMI_BRR register *******************/ #define SWPMI_BR ((uint32_t)0x000000FF) /******************* Bit definition for SWPMI_ISR register *******************/ #define SWPMI_RXBFF ((uint32_t)0x00000001) #define SWPMI_TXBEF ((uint32_t)0x00000002) #define SWPMI_RXBERF ((uint32_t)0x00000004) #define SWPMI_RXOVRF ((uint32_t)0x00000008) #define SWPMI_TXUNRF ((uint32_t)0x00000010) #define SWPMI_RXNE ((uint32_t)0x00000020) #define SWPMI_TXE ((uint32_t)0x00000040) #define SWPMI_TCF ((uint32_t)0x00000080) #define SWPMI_SRF ((uint32_t)0x00000100) #define SWPMI_SUSP ((uint32_t)0x00000200) #define SWPMI_DEACTF ((uint32_t)0x00000400) #define SWPMI_RDYF ((uint32_t)0x00000800) /******************* Bit definition for SWPMI_ICR register *******************/ #define SWPMI_CRXBFF ((uint32_t)0x00000001) #define SWPMI_CTXBEF ((uint32_t)0x00000002) #define SWPMI_CRXBERF ((uint32_t)0x00000004) #define SWPMI_CRXOVRF ((uint32_t)0x00000008) #define SWPMI_CTXUNRF ((uint32_t)0x00000010) #define SWPMI_CTCF ((uint32_t)0x00000080) #define SWPMI_CSRF ((uint32_t)0x00000100) #define SWPMI_CRDYF ((uint32_t)0x00000800) /******************* Bit definition for SWPMI_IER register *******************/ #define SWPMI_RXBFIE ((uint32_t)0x00000001) #define SWPMI_TXBEIE ((uint32_t)0x00000002) #define SWPMI_RXBERIE ((uint32_t)0x00000004) #define SWPMI_RXOVRIE ((uint32_t)0x00000008) #define SWPMI_TXUNRIE ((uint32_t)0x00000010) #define SWPMI_RIE ((uint32_t)0x00000020) #define SWPMI_TIE ((uint32_t)0x00000040) #define SWPMI_TCIE ((uint32_t)0x00000080) #define SWPMI_SRIE ((uint32_t)0x00000100) #define SWPMI_RDYIE ((uint32_t)0x00000800) /******************* Bit definition for SWPMI_RFL register *******************/ #define SWPMI_RFL ((uint32_t)0x0000001F) /******************* Bit definition for SWPMI_TDR register *******************/ #define SWPMI_TD ((uint32_t)0xFFFFFFFF) /******************* Bit definition for SWPMI_OR register *******************/ #define SWPMI_SWP_TBYP ((uint32_t)0x00000001) #define SWPMI_SWP_ISEL ((uint32_t)0x0000000C) #define SWPMI_SWP_ISEL_0 ((uint32_t)0x00000004) #define SWPMI_SWP_ISEL_1 ((uint32_t)0x00000008) /******************************************************************************/ /* FMC */ /******************************************************************************/ /******************* Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) #define FMC_BCR1_MWID ((uint32_t)0x00000030) #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) #define FMC_BCR1_MFACCEN ((uint32_t)0x00000040) #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) #define FMC_BCR1_WREN ((uint32_t)0x00001000) #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) #define FMC_BCR1_BMP ((uint32_t)0x03000000) #define FMC_BCR1_BMP_0 ((uint32_t)0x01000000) #define FMC_BCR1_BMP_1 ((uint32_t)0x02000000) #define FMC_BCR1_FMCEN ((uint32_t)0x80000000) /******************* Bit definition for FMC_BCR2 register *******************/ #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) #define FMC_BCR2_MWID ((uint32_t)0x00000030) #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) #define FMC_BCR2_WREN ((uint32_t)0x00001000) #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) #define FMC_BCR2_CPSZIE ((uint32_t)0x00070000) #define FMC_BCR2_CPSZIE_0 ((uint32_t)0x00010000) #define FMC_BCR2_CPSZIE_1 ((uint32_t)0x00020000) #define FMC_BCR2_CPSZIE_2 ((uint32_t)0x00040000) #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) #define FMC_BCR2_BMP ((uint32_t)0x03000000) #define FMC_BCR2_BMP_0 ((uint32_t)0x01000000) #define FMC_BCR2_BMP_1 ((uint32_t)0x02000000) #define FMC_BCR2_FMCEN ((uint32_t)0x80000000) /******************* Bit definition for FMC_BCR3 register *******************/ #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) #define FMC_BCR3_MWID ((uint32_t)0x00000030) #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) #define FMC_BCR3_WREN ((uint32_t)0x00001000) #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) #define FMC_BCR3_CPSZIE ((uint32_t)0x00070000) #define FMC_BCR3_CPSZIE_0 ((uint32_t)0x00010000) #define FMC_BCR3_CPSZIE_1 ((uint32_t)0x00020000) #define FMC_BCR3_CPSZIE_2 ((uint32_t)0x00040000) #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) #define FMC_BCR3_BMP ((uint32_t)0x03000000) #define FMC_BCR3_BMP_0 ((uint32_t)0x01000000) #define FMC_BCR3_BMP_1 ((uint32_t)0x02000000) #define FMC_BCR3_FMCEN ((uint32_t)0x80000000) /******************* Bit definition for FMC_BCR4 register *******************/ #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) #define FMC_BCR4_MWID ((uint32_t)0x00000030) #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) #define FMC_BCR4_WREN ((uint32_t)0x00001000) #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) #define FMC_BCR4_CPSZIE ((uint32_t)0x00070000) #define FMC_BCR4_CPSZIE_0 ((uint32_t)0x00010000) #define FMC_BCR4_CPSZIE_1 ((uint32_t)0x00020000) #define FMC_BCR4_CPSZIE_2 ((uint32_t)0x00040000) #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) #define FMC_BCR4_BMP ((uint32_t)0x03000000) #define FMC_BCR4_BMP_0 ((uint32_t)0x01000000) #define FMC_BCR4_BMP_1 ((uint32_t)0x02000000) #define FMC_BCR4_FMCEN ((uint32_t)0x80000000) /******************* Bit definition for FMC_BTR1 register *******************/ #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BTR2 register *******************/ #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BTR3 register *******************/ #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BTR4 register *******************/ #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BWTR1 register *******************/ #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BWTR2 register *******************/ #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BWTR3 register *******************/ #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_BWTR4 register *******************/ #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /******************* Bit definition for FMC_PCR register *******************/ #define FMC_PCR_PWAITEN ((uint32_t)0x00000020) #define FMC_PCR_PBKEN ((uint32_t)0x00000040) #define FMC_PCR_PTYP ((uint32_t)0x00000080) #define FMC_PCR_PWID ((uint32_t)0x00000300) #define FMC_PCR_PWID_0 ((uint32_t)0x00000100) #define FMC_PCR_PWID_1 ((uint32_t)0x00000200) #define FMC_PCR_ECCEN ((uint32_t)0x00000400) #define FMC_PCR_TCLR ((uint32_t)0x00001E00) #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) #define FMC_PCR_TAR ((uint32_t)0x0001E000) #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /******************* Bit definition for FMC_SR register *******************/ #define FMC_SR_IRS ((uint32_t)0x00000001) #define FMC_SR_ILS ((uint32_t)0x00000002) #define FMC_SR_IFS ((uint32_t)0x00000004) #define FMC_SR_IREN ((uint32_t)0x00000008) #define FMC_SR_ILEN ((uint32_t)0x00000010) #define FMC_SR_IFEN ((uint32_t)0x00000020) #define FMC_SR_FEMPT ((uint32_t)0x00000040) /******************* Bit definition for FMC_PMEM register *******************/ #define FMC_PMEM_MEMSET ((uint32_t)0x000000FF) #define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00) #define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000) #define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000) /******************* Bit definition for FMC_PATT register *******************/ #define FMC_PATT_ATTSET ((uint32_t)0x000000FF) #define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00) #define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000) #define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000) /******************* Bit definition for FMC_ECCR register *******************/ #define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFF) /******************* Bit definition for FMC_SDCR1 register *******************/ #define FMC_SDCR1_NC ((uint32_t)0x00000003) #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) #define FMC_SDCR1_NR ((uint32_t)0x0000000C) #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) #define FMC_SDCR1_MWID ((uint32_t)0x00000030) #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) #define FMC_SDCR1_NB ((uint32_t)0x00000040) #define FMC_SDCR1_CAS ((uint32_t)0x00000180) #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) #define FMC_SDCR1_WP ((uint32_t)0x00000200) #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /******************* Bit definition for FMC_SDCR2 register *******************/ #define FMC_SDCR2_NC ((uint32_t)0x00000003) #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) #define FMC_SDCR2_NR ((uint32_t)0x0000000C) #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) #define FMC_SDCR2_MWID ((uint32_t)0x00000030) #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) #define FMC_SDCR2_NB ((uint32_t)0x00000040) #define FMC_SDCR2_CAS ((uint32_t)0x00000180) #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) #define FMC_SDCR2_WP ((uint32_t)0x00000200) #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /******************* Bit definition for FMC_SDTR1 register *******************/ #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000020) #define FMC_SDTR1_TXSR_4 ((uint32_t)0x00000040) #define FMC_SDTR1_TXSR_8 ((uint32_t)0x00000080) #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) #define FMC_SDTR1_TRC_3 ((uint32_t)0x00008000) #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) #define FMC_SDTR1_TWR_3 ((uint32_t)0x00080000) #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) #define FMC_SDTR1_TRP_2 ((uint32_t)0x00200000) #define FMC_SDTR1_TRP_3 ((uint32_t)0x00400000) #define FMC_SDTR1_TRP_4 ((uint32_t)0x00800000) #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) #define FMC_SDTR1_TRCD_3 ((uint32_t)0x08000000) /******************* Bit definition for FMC_SDTR2 register *******************/ #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000020) #define FMC_SDTR2_TXSR_4 ((uint32_t)0x00000040) #define FMC_SDTR2_TXSR_8 ((uint32_t)0x00000080) #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) #define FMC_SDTR2_TRC_3 ((uint32_t)0x00008000) #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) #define FMC_SDTR2_TWR_3 ((uint32_t)0x00080000) #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) #define FMC_SDTR2_TRP_2 ((uint32_t)0x00200000) #define FMC_SDTR2_TRP_3 ((uint32_t)0x00400000) #define FMC_SDTR2_TRP_4 ((uint32_t)0x00800000) #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) #define FMC_SDTR2_TRCD_3 ((uint32_t)0x08000000) /******************* Bit definition for FMC_SDCMR register *******************/ #define FMC_SDCMR_MODE ((uint32_t)0x00000007) #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /******************* Bit definition for FMC_SDRTR register *******************/ #define FMC_SDRTR_CRE ((uint32_t)0x00000001) #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /******************* Bit definition for FMC_SDSR register *******************/ #define FMC_SDSR_RE ((uint32_t)0x00000001) #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /******************* Bit definition for FMC_MISC register *******************/ #define FMC_MISC_NRFS_CNT ((uint32_t)0x0000000F) #define FMC_MISC_NRFS_CNT_0 ((uint32_t)0x00000001) #define FMC_MISC_NRFS_CNT_1 ((uint32_t)0x00000002) #define FMC_MISC_NRFS_CNT_2 ((uint32_t)0x00000004) #define FMC_MISC_NRFS_CNT_3 ((uint32_t)0x00000008) #define FMC_MISC_Phase_Sel ((uint32_t)0x000000F0) #define FMC_MISC_Phase_Sel_0 ((uint32_t)0x00000010) #define FMC_MISC_Phase_Sel_1 ((uint32_t)0x00000020) #define FMC_MISC_Phase_Sel_2 ((uint32_t)0x00000040) #define FMC_MISC_Phase_Sel_3 ((uint32_t)0x00000080) #define FMC_MISC_Enhance_read_mode ((uint32_t)0x00001000) #define FMC_MISC_En_Bank1 ((uint32_t)0x00010000) #define FMC_MISC_En_Bank2 ((uint32_t)0x00020000) /******************************************************************************/ /* ECDC */ /******************************************************************************/ /******************* Bit definition for ECDC_CTRL register *******************/ #define ECDC_KEYEX_EN ((uint32_t)0x00000001) #define ECDC_NORMAL_EN ((uint32_t)0x00000002) #define ECDC_MODE_SEL ((uint32_t)0x00000008) #define ECDC_CLKDIV_MASK ((uint32_t)0x00000070) #define ECDC_WRSRAM_EN ((uint32_t)0x00000080) #define ECDC_ALGRM_MOD ((uint32_t)0x00000100) #define ECDC_CIPHER_MOD ((uint32_t)0x00000200) #define ECDC_KLEN_MASK ((uint32_t)0x00000C00) #define ECDC_DAT_MOD ((uint32_t)0x00002000) #define ECDC_IE_SINGLE ((uint32_t)0x00020000) #define ECDC_IE_WRSRAM ((uint32_t)0x00040000) #define ECDC_CLOCK_SELECT ((uint32_t)0x01000000) #define ECDC_ECDC_SM4_CLOCK_EN ((uint32_t)0x02000000) /******************* Bit definition for ECDC_INT_FG register *******************/ #define ECDC_IF_EKDONE ((uint32_t)0x00010000) #define ECDC_IF_SINGLE ((uint32_t)0x00020000) #define ECDC_IF_WRSRAM ((uint32_t)0x00040000) /******************* Bit definition for ECDC_KEY register *******************/ #define ECDC_KEY_255T224 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_223T192 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_191T160 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_159T128 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_127T96 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_95T64 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_63T32 ((uint32_t)0xFFFFFFFF) #define ECDC_KEY_31T0 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for ECDC_IV register *******************/ #define ECDC_IV_127T96 ((uint32_t)0xFFFFFFFF) #define ECDC_IV_95T64 ((uint32_t)0xFFFFFFFF) #define ECDC_IV_63T32 ((uint32_t)0xFFFFFFFF) #define ECDC_IV_31T0 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for ECDC_SGSD register *******************/ #define ECDC_SGSD_127T96 ((uint32_t)0xFFFFFFFF) #define ECDC_SGSD_95T64 ((uint32_t)0xFFFFFFFF) #define ECDC_SGSD_63T32 ((uint32_t)0xFFFFFFFF) #define ECDC_SGSD_31T0 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for ECDC_SGRT register *******************/ #define ECDC_SGRT_127T96 ((uint32_t)0xFFFFFFFF) #define ECDC_SGRT_95T64 ((uint32_t)0xFFFFFFFF) #define ECDC_SGRT_63T32 ((uint32_t)0xFFFFFFFF) #define ECDC_SGRT_31T0 ((uint32_t)0xFFFFFFFF) /******************* Bit definition for ECDC_SRC_ADDR register *******************/ #define ECDC_SRAM_SRC_ADDR ((uint32_t)0xFFFFFFFF) /******************* Bit definition for ECDC_DST_ADDR register *******************/ #define ECDC_SRAM_DST_ADDR ((uint32_t)0xFFFFFFFF) /******************* Bit definition for ECDC_SRAM_LEN register *******************/ #define ECDC_SRAM_LEN ((uint32_t)0xFFFFFFFF) /******************************************************************************/ /* DFSDM */ /******************************************************************************/ /******************* Bit definition for DFSDM_CFGR1 register *******************/ #define DFSDM_CFGR1_SITP ((uint32_t)0x00000003) #define DFSDM_CFGR1_SITP_0 ((uint32_t)0x00000001) #define DFSDM_CFGR1_SITP_1 ((uint32_t)0x00000002) #define DFSDM_CFGR1_SPICKSEL ((uint32_t)0x0000000C) #define DFSDM_CFGR1_SPICKSEL_0 ((uint32_t)0x00000004) #define DFSDM_CFGR1_SPICKSEL_1 ((uint32_t)0x00000008) #define DFSDM_CFGR1_SCDEN ((uint32_t)0x00000020) #define DFSDM_CFGR1_CKABEN ((uint32_t)0x00000040) #define DFSDM_CFGR1_CHEN ((uint32_t)0x00000080) #define DFSDM_CFGR1_CHINSEL ((uint32_t)0x00000100) #define DFSDM_CFGR1_DATMPX ((uint32_t)0x00003000) #define DFSDM_CFGR1_DATMPX_0 ((uint32_t)0x00001000) #define DFSDM_CFGR1_DATMPX_1 ((uint32_t)0x00002000) #define DFSDM_CFGR1_DATPACK ((uint32_t)0x0000C000) #define DFSDM_CFGR1_DATPACK_0 ((uint32_t)0x00004000) #define DFSDM_CFGR1_DATPACK_1 ((uint32_t)0x00008000) #define DFSDM_CFGR1_CKOUTDIV ((uint32_t)0x00FF0000) #define DFSDM_CFGR1_CKOUTSRC ((uint32_t)0x40000000) #define DFSDM_CFGR1_DFSDMEN ((uint32_t)0x80000000) /******************* Bit definition for DFSDM_CFGR2 register *******************/ #define DFSDM_CFGR2_DTRBS ((uint32_t)0x000000F8) #define DFSDM_CFGR2_OFFSET ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_AWSCDR register *******************/ #define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FF) #define DFSDM_AWSCDR_BKSCD ((uint32_t)0x00003000) #define DFSDM_AWSCDR_BKSCD_0 ((uint32_t)0x00001000) #define DFSDM_AWSCDR_BKSCD_1 ((uint32_t)0x00002000) #define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000) #define DFSDM_AWSCDR_AWFOSR_0 ((uint32_t)0x00010000) #define DFSDM_AWSCDR_AWFOSR_1 ((uint32_t)0x00020000) #define DFSDM_AWSCDR_AWFOSR_2 ((uint32_t)0x00040000) #define DFSDM_AWSCDR_AWFOSR_3 ((uint32_t)0x00080000) #define DFSDM_AWSCDR_AWFOSR_4 ((uint32_t)0x00100000) #define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000) #define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000) #define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000) /******************* Bit definition for DFSDM_WDATR register *******************/ #define DFSDM_WDATR ((uint16_t)0xFFFF) /******************* Bit definition for DFSDM_DATINR register *******************/ #define DFSDM_DATINR_INDAT0 ((uint32_t)0x0000FFFF) #define DFSDM_DATINR_INDAT1 ((uint32_t)0xFFFF0000) /******************* Bit definition for DFSDM_FLTCR1 register *******************/ #define DFSDM_FLTCR1_DFEN ((uint32_t)0x00000001) #define DFSDM_FLTCR1_JSWSTART ((uint32_t)0x00000002) #define DFSDM_FLTCR1_JSYNC ((uint32_t)0x00000008) #define DFSDM_FLTCR1_JSCAN ((uint32_t)0x00000010) #define DFSDM_FLTCR1_JDMAEN ((uint32_t)0x00000020) #define DFSDM_FLTCR1_JEXTSEL ((uint32_t)0x00000F00) #define DFSDM_FLTCR1_JEXTSEL_0 ((uint32_t)0x00000100) #define DFSDM_FLTCR1_JEXTSEL_1 ((uint32_t)0x00000200) #define DFSDM_FLTCR1_JEXTSEL_2 ((uint32_t)0x00000400) #define DFSDM_FLTCR1_JEXTSEL_3 ((uint32_t)0x00000800) #define DFSDM_FLTCR1_JEXTEN ((uint32_t)0x00006000) #define DFSDM_FLTCR1_JEXTEN_0 ((uint32_t)0x00002000) #define DFSDM_FLTCR1_JEXTEN_1 ((uint32_t)0x00004000) #define DFSDM_FLTCR1_RSWSTART ((uint32_t)0x00020000) #define DFSDM_FLTCR1_RCONT ((uint32_t)0x00040000) #define DFSDM_FLTCR1_RSYNC ((uint32_t)0x00080000) #define DFSDM_FLTCR1_RDMAEN ((uint32_t)0x00200000) #define DFSDM_FLTCR1_RCH ((uint32_t)0x01000000) #define DFSDM_FLTCR1_FAST ((uint32_t)0x20000000) #define DFSDM_FLTCR1_AWFSEL ((uint32_t)0x40000000) /******************* Bit definition for DFSDM_FLTCR2 register *******************/ #define DFSDM_FLTCR2_JEOCIE ((uint32_t)0x00000001) #define DFSDM_FLTCR2_REOCIE ((uint32_t)0x00000002) #define DFSDM_FLTCR2_JOVRIE ((uint32_t)0x00000004) #define DFSDM_FLTCR2_ROVRIE ((uint32_t)0x00000008) #define DFSDM_FLTCR2_AWDIE ((uint32_t)0x00000010) #define DFSDM_FLTCR2_SCDIE ((uint32_t)0x00000020) #define DFSDM_FLTCR2_CKABIE ((uint32_t)0x00000040) #define DFSDM_FLTCR2_EXCH ((uint32_t)0x00000300) #define DFSDM_FLTCR2_EXCH_0 ((uint32_t)0x00000100) #define DFSDM_FLTCR2_EXCH_1 ((uint32_t)0x00000200) #define DFSDM_FLTCR2_AWDCH ((uint32_t)0x00030000) #define DFSDM_FLTCR2_AWDCH_0 ((uint32_t)0x00010000) #define DFSDM_FLTCR2_AWDCH_1 ((uint32_t)0x00020000) /******************* Bit definition for DFSDM_FLTISR register *******************/ #define DFSDM_FLTISR_JEOCF ((uint32_t)0x00000001) #define DFSDM_FLTISR_REOCF ((uint32_t)0x00000002) #define DFSDM_FLTISR_JOVRF ((uint32_t)0x00000004) #define DFSDM_FLTISR_ROVRF ((uint32_t)0x00000008) #define DFSDM_FLTISR_AWDF ((uint32_t)0x00000010) #define DFSDM_FLTISR_JCIP ((uint32_t)0x00002000) #define DFSDM_FLTISR_RCIP ((uint32_t)0x00004000) #define DFSDM_FLTISR_CKABF ((uint32_t)0x00030000) #define DFSDM_FLTISR_CKABF_0 ((uint32_t)0x00010000) #define DFSDM_FLTISR_CKABF_1 ((uint32_t)0x00020000) #define DFSDM_FLTISR_SCDF ((uint32_t)0x03000000) #define DFSDM_FLTISR_SCDF_0 ((uint32_t)0x01000000) #define DFSDM_FLTISR_SCDF_1 ((uint32_t)0x02000000) /******************* Bit definition for DFSDM_FLTICR register *******************/ #define DFSDM_FLTICR_CLRJOVRF ((uint32_t)0x00000004) #define DFSDM_FLTICR_CLRROVRF ((uint32_t)0x00000008) #define DFSDM_FLTICR_CLRCKABF ((uint32_t)0x00030000) #define DFSDM_FLTICR_CLRCKABF_0 ((uint32_t)0x00010000) #define DFSDM_FLTICR_CLRCKABF_1 ((uint32_t)0x00020000) #define DFSDM_FLTICR_CLRSCDF ((uint32_t)0x03000000) #define DFSDM_FLTICR_CLRSCDF_0 ((uint32_t)0x01000000) #define DFSDM_FLTICR_CLRSCDF_1 ((uint32_t)0x02000000) /******************* Bit definition for DFSDM_FLTJCHGR register *******************/ #define DFSDM_FLTJCHGR_JCHG ((uint32_t)0x00000003) /******************* Bit definition for DFSDM_FLTFCR3 register *******************/ #define DFSDM_FLTFCR3_IOSR ((uint32_t)0x000000FF) #define DFSDM_FLTFCR3_IOSR_0 ((uint32_t)0x00000001) #define DFSDM_FLTFCR3_IOSR_1 ((uint32_t)0x00000002) #define DFSDM_FLTFCR3_IOSR_2 ((uint32_t)0x00000004) #define DFSDM_FLTFCR3_IOSR_3 ((uint32_t)0x00000008) #define DFSDM_FLTFCR3_IOSR_4 ((uint32_t)0x00000010) #define DFSDM_FLTFCR3_IOSR_5 ((uint32_t)0x00000020) #define DFSDM_FLTFCR3_IOSR_6 ((uint32_t)0x00000040) #define DFSDM_FLTFCR3_IOSR_7 ((uint32_t)0x00000080) #define DFSDM_FLTFCR3_FOSR ((uint32_t)0x03FF0000) #define DFSDM_FLTFCR3_FOSR_0 ((uint32_t)0x00010000) #define DFSDM_FLTFCR3_FOSR_1 ((uint32_t)0x00020000) #define DFSDM_FLTFCR3_FOSR_2 ((uint32_t)0x00040000) #define DFSDM_FLTFCR3_FOSR_3 ((uint32_t)0x00080000) #define DFSDM_FLTFCR3_FOSR_4 ((uint32_t)0x00100000) #define DFSDM_FLTFCR3_FOSR_5 ((uint32_t)0x00200000) #define DFSDM_FLTFCR3_FOSR_6 ((uint32_t)0x00400000) #define DFSDM_FLTFCR3_FOSR_7 ((uint32_t)0x00800000) #define DFSDM_FLTFCR3_FOSR_8 ((uint32_t)0x01000000) #define DFSDM_FLTFCR3_FOSR_9 ((uint32_t)0x03FF0000) #define DFSDM_FLTFCR3_FORD ((uint32_t)0xE0000000) #define DFSDM_FLTFCR3_FORD_0 ((uint32_t)0x20000000) #define DFSDM_FLTFCR3_FORD_1 ((uint32_t)0x40000000) #define DFSDM_FLTFCR3_FORD_2 ((uint32_t)0x80000000) /******************* Bit definition for DFSDM_FLTJDATAR register *******************/ #define DFSDM_FLTJDATAR_JDATACH ((uint32_t)0x00000001) #define DFSDM_FLTJDATAR_JDATA ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_FLTRDATAR register *******************/ #define DFSDM_FLTRDATAR_RDATACH ((uint32_t)0x00000001) #define DFSDM_FLTRDATAR_RPEND ((uint32_t)0x00000010) #define DFSDM_FLTRDATAR_RDATA ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_FLTAWHTR register *******************/ #define DFSDM_FLTAWHTR_BKAWH ((uint32_t)0x0000000F) #define DFSDM_FLTAWHTR_BKAWH_0 ((uint32_t)0x00000001) #define DFSDM_FLTAWHTR_BKAWH_1 ((uint32_t)0x00000002) #define DFSDM_FLTAWHTR_BKAWH_2 ((uint32_t)0x00000004) #define DFSDM_FLTAWHTR_BKAWH_3 ((uint32_t)0x00000008) #define DFSDM_FLTAWHTR_AWHT ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_FLTAWLTR register *******************/ #define DFSDM_FLTAWLTR_BKAWL ((uint32_t)0x0000000F) #define DFSDM_FLTAWLTR_BKAWL_0 ((uint32_t)0x00000001) #define DFSDM_FLTAWLTR_BKAWL_1 ((uint32_t)0x00000002) #define DFSDM_FLTAWLTR_BKAWL_2 ((uint32_t)0x00000004) #define DFSDM_FLTAWLTR_BKAWL_3 ((uint32_t)0x00000008) #define DFSDM_FLTAWLTR_AWLT ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_FLTAWSR register *******************/ #define DFSDM_FLTAWSR_AWLTF ((uint32_t)0x00000003) #define DFSDM_FLTAWSR_AWHTF ((uint32_t)0x00000300) /******************* Bit definition for DFSDM_FLTAWCFR register *******************/ #define DFSDM_FLTAWCFR_CLRAWLTF ((uint32_t)0x00000003) #define DFSDM_FLTAWCFR_CLRAWLTF_0 ((uint32_t)0x00000001) #define DFSDM_FLTAWCFR_CLRAWLTF_1 ((uint32_t)0x00000002) #define DFSDM_FLTAWCFR_CLRAWHTF ((uint32_t)0x00000300) #define DFSDM_FLTAWCFR_CLRAWHTF_0 ((uint32_t)0x00000100) #define DFSDM_FLTAWCFR_CLRAWHTF_1 ((uint32_t)0x00000200) /******************* Bit definition for DFSDM_FLTEXMAX register *******************/ #define DFSDM_FLTEXMAX_EXMAXCH ((uint32_t)0x00000001) #define DFSDM_FLTEXMAX_EXMAX ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_FLTEXMIN register *******************/ #define DFSDM_FLTEXMIN_EXMINCH ((uint32_t)0x00000001) #define DFSDM_FLTEXMIN_EXMIN ((uint32_t)0xFFFFFF00) /******************* Bit definition for DFSDM_FLTCNVTIMR register *******************/ #define DFSDM_FLTCNVTIMR_CNVCNT ((uint32_t)0xFFFFFF00) /******************************************************************************/ /* LTDC */ /******************************************************************************/ /******************* Bit definition for LTDC_SSCR register *******************/ #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /******************* Bit definition for LTDC_BPCR register *******************/ #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /******************* Bit definition for LTDC_AWCR register *******************/ #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /******************* Bit definition for LTDC_TWCR register *******************/ #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /******************* Bit definition for LTDC_GCR register *******************/ #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) #define LTDC_GCR_DBW ((uint32_t)0x00000070) #define LTDC_GCR_DBW_0 ((uint32_t)0x00000010) #define LTDC_GCR_DBW_1 ((uint32_t)0x00000020) #define LTDC_GCR_DBW_2 ((uint32_t)0x00000040) #define LTDC_GCR_DGW ((uint32_t)0x00000700) #define LTDC_GCR_DGW_0 ((uint32_t)0x00000100) #define LTDC_GCR_DGW_1 ((uint32_t)0x00000200) #define LTDC_GCR_DGW_2 ((uint32_t)0x00000400) #define LTDC_GCR_DRW ((uint32_t)0x00007000) #define LTDC_GCR_DRW_0 ((uint32_t)0x00001000) #define LTDC_GCR_DRW_1 ((uint32_t)0x00002000) #define LTDC_GCR_DRW_2 ((uint32_t)0x00004000) #define LTDC_GCR_DEN ((uint32_t)0x00010000) #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /******************* Bit definition for LTDC_SRCR register *******************/ #define LTDC_SRCR_IMR ((uint32_t)0x00000001) #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /******************* Bit definition for LTDC_BCCR register *******************/ #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /******************* Bit definition for LTDC_IER register *******************/ #define LTDC_IER_LIE ((uint32_t)0x00000001) #define LTDC_IER_FUIE ((uint32_t)0x00000002) #define LTDC_IER_RRIE ((uint32_t)0x00000008) /******************* Bit definition for LTDC_ISR register *******************/ #define LTDC_ISR_LIF ((uint32_t)0x00000001) #define LTDC_ISR_FUIF ((uint32_t)0x00000002) #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /******************* Bit definition for LTDC_ICR register *******************/ #define LTDC_ICR_CLIF ((uint32_t)0x00000001) #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /******************* Bit definition for LTDC_LIPCR register *******************/ #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /******************* Bit definition for LTDC_CPSR register *******************/ #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /******************* Bit definition for LTDC_CDSR register *******************/ #define LTDC_CDSR_VDES ((uint32_t)0x00000001) #define LTDC_CDSR_HDES ((uint32_t)0x00000002) #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /******************* Bit definition for LTDC_CR register *******************/ #define LTDC_CR_LEN ((uint32_t)0x00000001) #define LTDC_CR_COLKEN ((uint32_t)0x00000002) #define LTDC_CR_CLUTEN ((uint32_t)0x00000010) /******************* Bit definition for LTDC_WHPCR register *******************/ #define LTDC_WHPCR_WHSTPOS ((uint32_t)0x00000FFF) #define LTDC_WHPCR_WHSPPOS ((uint32_t)0x0FFF0000) /******************* Bit definition for LTDC_WVPCR register *******************/ #define LTDC_WVPCR_WVSTPOS ((uint32_t)0x000007FF) #define LTDC_WVPCR_WVSPPOS ((uint32_t)0x07FF0000) /******************* Bit definition for LTDC_CKCR register *******************/ #define LTDC_CKCR_CKBLUE ((uint32_t)0x000000FF) #define LTDC_CKCR_CKGREEN ((uint32_t)0x0000FF00) #define LTDC_CKCR_CKRED ((uint32_t)0x00FF0000) /******************* Bit definition for LTDC_PFCR register *******************/ #define LTDC_PFCR_PF ((uint32_t)0x00000007) #define LTDC_PFCR_PF_0 ((uint32_t)0x00000001) #define LTDC_PFCR_PF_1 ((uint32_t)0x00000002) #define LTDC_PFCR_PF_2 ((uint32_t)0x00000004) #define LTDC_PFCR_PF_ARGB8888 ((uint32_t)0x00000000) #define LTDC_PFCR_PF_RGB888 ((uint32_t)0x00000001) #define LTDC_PFCR_PF_RGB565 ((uint32_t)0x00000002) #define LTDC_PFCR_PF_ARGB1555 ((uint32_t)0x00000003) #define LTDC_PFCR_PF_ARGB4444 ((uint32_t)0x00000004) #define LTDC_PFCR_PF_L8 ((uint32_t)0x00000005) #define LTDC_PFCR_PF_AL44 ((uint32_t)0x00000006) #define LTDC_PFCR_PF_AL88 ((uint32_t)0x00000007) /******************* Bit definition for LTDC_CACR register *******************/ #define LTDC_CACR_CONSTA ((uint32_t)0x000000FF) /******************* Bit definition for LTDC_DCCR register *******************/ #define LTDC_DCCR_DCBLUE ((uint32_t)0x000000FF) #define LTDC_DCCR_DCGREEN ((uint32_t)0x0000FF00) #define LTDC_DCCR_DCRED ((uint32_t)0x00FF0000) #define LTDC_DCCR_DCALPHA ((uint32_t)0xFF000000) /******************* Bit definition for LTDC_BFCR register *******************/ #define LTDC_BFCR_BF2 ((uint32_t)0x00000007) #define LTDC_BFCR_BF2_0 ((uint32_t)0x00000001) #define LTDC_BFCR_BF2_1 ((uint32_t)0x00000002) #define LTDC_BFCR_BF2_2 ((uint32_t)0x00000004) #define LTDC_BFCR_BF1 ((uint32_t)0x00000700) #define LTDC_BFCR_BF1_0 ((uint32_t)0x00000100) #define LTDC_BFCR_BF1_1 ((uint32_t)0x00000200) #define LTDC_BFCR_BF1_2 ((uint32_t)0x00000400) /******************* Bit definition for LTDC_CFBAR register *******************/ #define LTDC_CFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /******************* Bit definition for LTDC_CFBLR register *******************/ #define LTDC_CFBLR_CFBLL ((uint32_t)0x00001FFF) #define LTDC_CFBLR_CFBP ((uint32_t)0x1FFF0000) /******************* Bit definition for LTDC_CFBLNR register *******************/ #define LTDC_CFBLNR_CFBLNBR ((uint32_t)0x000007FF) /******************* Bit definition for LTDC_CLUTWR register *******************/ #define LTDC_CLUTWR_BLUE ((uint32_t)0x000000FF) #define LTDC_CLUTWR_GREEN ((uint32_t)0x0000FF00) #define LTDC_CLUTWR_RED ((uint32_t)0x00FF0000) #define LTDC_CLUTWR_CLUTADD ((uint32_t)0xFF000000) /******************************************************************************/ /* GPHA */ /******************************************************************************/ /******************* Bit definition for GPHA_CTLR register *******************/ #define GPHA_CTLR_START ((uint32_t)0x00000001) #define GPHA_CTLR_SUSP ((uint32_t)0x00000002) #define GPHA_CTLR_ABORT ((uint32_t)0x00000004) #define GPHA_CTLR_TCIE ((uint32_t)0x00000200) #define GPHA_CTLR_TWIE ((uint32_t)0x00000400) #define GPHA_CTLR_CAEIE ((uint32_t)0x00000800) #define GPHA_CTLR_CTCIE ((uint32_t)0x00001000) #define GPHA_CTLR_CEIE ((uint32_t)0x00002000) #define GPHA_CTLR_MODE ((uint32_t)0x00070000) #define GPHA_CTLR_MODE_0 ((uint32_t)0x00010000) #define GPHA_CTLR_MODE_1 ((uint32_t)0x00020000) #define GPHA_CTLR_MODE_2 ((uint32_t)0x00040000) /******************* Bit definition for GPHA_ISR register *******************/ #define GPHA_ISR_TCIF ((uint32_t)0x00000002) #define GPHA_ISR_TWIF ((uint32_t)0x00000004) #define GPHA_ISR_CAEIF ((uint32_t)0x00000008) #define GPHA_ISR_CTCIF ((uint32_t)0x00000010) #define GPHA_ISR_CEIF ((uint32_t)0x00000020) /******************* Bit definition for GPHA_IFCR register *******************/ #define GPHA_IFCR_CTCIF ((uint32_t)0x00000002) #define GPHA_IFCR_CTWIF ((uint32_t)0x00000004) #define GPHA_IFCR_CAECIF ((uint32_t)0x00000008) #define GPHA_IFCR_CCTCIF ((uint32_t)0x00000010) #define GPHA_IFCR_CCEIF ((uint32_t)0x00000020) /******************* Bit definition for GPHA_FGMAR register *******************/ #define GPHA_FGMAR_MA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for GPHA_FGOR register *******************/ #define GPHA_FGOR_LO ((uint32_t)0x00003FFF) /******************* Bit definition for GPHA_BGMAR register *******************/ #define GPHA_BGMAR_MA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for GPHA_BGOR register *******************/ #define GPHA_BGOR_LO ((uint32_t)0x00003FFF) /******************* Bit definition for GPHA_FGPFCCR register *******************/ #define GPHA_FGPFCCR_CM ((uint32_t)0x0000000F) #define GPHA_FGPFCCR_CM_0 ((uint32_t)0x00000001) #define GPHA_FGPFCCR_CM_1 ((uint32_t)0x00000002) #define GPHA_FGPFCCR_CM_2 ((uint32_t)0x00000004) #define GPHA_FGPFCCR_CM_3 ((uint32_t)0x00000008) #define GPHA_FGPFCCR_CM_ARGB8888 ((uint32_t)0x00000000) #define GPHA_FGPFCCR_CM_RGB888 ((uint32_t)0x00000001) #define GPHA_FGPFCCR_CM_RGB565 ((uint32_t)0x00000002) #define GPHA_FGPFCCR_CM_ARGB1555 ((uint32_t)0x00000003) #define GPHA_FGPFCCR_CM_ARGB4444 ((uint32_t)0x00000004) #define GPHA_FGPFCCR_CM_L8 ((uint32_t)0x00000005) #define GPHA_FGPFCCR_CM_AL44 ((uint32_t)0x00000006) #define GPHA_FGPFCCR_CM_AL88 ((uint32_t)0x00000007) #define GPHA_FGPFCCR_CM_L4 ((uint32_t)0x00000008) #define GPHA_FGPFCCR_CM_A8 ((uint32_t)0x00000009) #define GPHA_FGPFCCR_CM_A4 ((uint32_t)0x0000000A) #define GPHA_FGPFCCR_CM_YcbCr ((uint32_t)0x0000000B) #define GPHA_FGPFCCR_CCM ((uint32_t)0x00000010) #define GPHA_FGPFCCR_START ((uint32_t)0x00000020) #define GPHA_FGPFCCR_CS ((uint32_t)0x0000FF00) #define GPHA_FGPFCCR_AM ((uint32_t)0x00030000) #define GPHA_FGPFCCR_AM_0 ((uint32_t)0x00010000) #define GPHA_FGPFCCR_AM_1 ((uint32_t)0x00020000) #define GPHA_FGPFCCR_CSS ((uint32_t)0x000C0000) #define GPHA_FGPFCCR_CSS_0 ((uint32_t)0x00040000) #define GPHA_FGPFCCR_CSS_1 ((uint32_t)0x00080000) #define GPHA_FGPFCCR_AI ((uint32_t)0x00100000) #define GPHA_FGPFCCR_RBS ((uint32_t)0x00200000) #define GPHA_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /******************* Bit definition for GPHA_FGCOLR register *******************/ #define GPHA_FGCOLR_BLUE ((uint32_t)0x000000FF) #define GPHA_FGCOLR_GREEN ((uint32_t)0x0000FF00) #define GPHA_FGCOLR_RED ((uint32_t)0x00FF0000) /******************* Bit definition for GPHA_BGPFCCR register *******************/ #define GPHA_BGPFCCR_CM ((uint32_t)0x0000000F) #define GPHA_BGPFCCR_CM_0 ((uint32_t)0x00000001) #define GPHA_BGPFCCR_CM_1 ((uint32_t)0x00000002) #define GPHA_BGPFCCR_CM_2 ((uint32_t)0x00000004) #define GPHA_BGPFCCR_CM_3 ((uint32_t)0x00000008) #define GPHA_BGPFCCR_CM_ARGB8888 ((uint32_t)0x00000000) #define GPHA_BGPFCCR_CM_RGB888 ((uint32_t)0x00000001) #define GPHA_BGPFCCR_CM_RGB565 ((uint32_t)0x00000002) #define GPHA_BGPFCCR_CM_ARGB1555 ((uint32_t)0x00000003) #define GPHA_BGPFCCR_CM_ARGB4444 ((uint32_t)0x00000004) #define GPHA_BGPFCCR_CM_L8 ((uint32_t)0x00000005) #define GPHA_BGPFCCR_CM_AL44 ((uint32_t)0x00000006) #define GPHA_BGPFCCR_CM_AL88 ((uint32_t)0x00000007) #define GPHA_BGPFCCR_CM_L4 ((uint32_t)0x00000008) #define GPHA_BGPFCCR_CM_A8 ((uint32_t)0x00000009) #define GPHA_BGPFCCR_CM_A4 ((uint32_t)0x0000000A) #define GPHA_BGPFCCR_CCM ((uint32_t)0x00000010) #define GPHA_BGPFCCR_START ((uint32_t)0x00000020) #define GPHA_BGPFCCR_CS ((uint32_t)0x0000FF00) #define GPHA_BGPFCCR_AM ((uint32_t)0x00030000) #define GPHA_BGPFCCR_AM_0 ((uint32_t)0x00010000) #define GPHA_BGPFCCR_AM_1 ((uint32_t)0x00020000) #define GPHA_BGPFCCR_AI ((uint32_t)0x00100000) #define GPHA_BGPFCCR_RBS ((uint32_t)0x00200000) #define GPHA_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /******************* Bit definition for GPHA_BGCOLR register *******************/ #define GPHA_BGCOLR_BLUE ((uint32_t)0x000000FF) #define GPHA_BGCOLR_GREEN ((uint32_t)0x0000FF00) #define GPHA_BGCOLR_RED ((uint32_t)0x00FF0000) /******************* Bit definition for GPHA_FGCMAR register *******************/ #define GPHA_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for GPHA_BGCMAR register *******************/ #define GPHA_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for GPHA_OPFCCR register *******************/ #define GPHA_OPFCCR_CM ((uint32_t)0x00000007) #define GPHA_OPFCCR_CM_0 ((uint32_t)0x00000001) #define GPHA_OPFCCR_CM_1 ((uint32_t)0x00000002) #define GPHA_OPFCCR_CM_2 ((uint32_t)0x00000004) #define GPHA_OPFCCR_CM_ARGB8888 ((uint32_t)0x00000000) #define GPHA_OPFCCR_CM_RGB888 ((uint32_t)0x00000001) #define GPHA_OPFCCR_CM_RGB565 ((uint32_t)0x00000002) #define GPHA_OPFCCR_CM_ARGB1555 ((uint32_t)0x00000003) #define GPHA_OPFCCR_CM_ARGB4444 ((uint32_t)0x00000004) #define GPHA_OPFCCR_AI ((uint32_t)0x00100000) #define GPHA_OPFCCR_RBS ((uint32_t)0x00200000) /******************* Bit definition for GPHA_OCOLR register *******************/ #define GPHA_OCOLR_BLUE ((uint32_t)0x000000FF) #define GPHA_OCOLR_GREEN ((uint32_t)0x0000FF00) #define GPHA_OCOLR_RED ((uint32_t)0x00FF0000) #define GPHA_OCOLR_ALPHA ((uint32_t)0xFF000000) /******************* Bit definition for GPHA_OMAR register *******************/ #define GPHA_OMAR_MA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for GPHA_OOR register *******************/ #define GPHA_OOR_LO ((uint32_t)0x00003FFF) /******************* Bit definition for GPHA_NLR register *******************/ #define GPHA_NLR_NL ((uint32_t)0x0000FFFF) #define GPHA_NLR_PL ((uint32_t)0x3FFF0000) /******************* Bit definition for GPHA_LWR register *******************/ #define GPHA_LWR_LW ((uint32_t)0x0000FFFF) /******************* Bit definition for GPHA_AMTCR register *******************/ #define GPHA_AMTCR_EN ((uint32_t)0x00000001) #define GPHA_AMTCR_DT ((uint32_t)0x0000FF00) /******************* Bit definition for GPHA_FGCWRS register *******************/ #define GPHA_FGCWRS_FG_CLUT_INDEX ((uint32_t)0x000000FF) #define GPHA_FGCWRS_FG_CLUT_EN ((uint32_t)0x00000100) /******************* Bit definition for GPHA_FGCDAT register *******************/ #define GPHA_FGCDAT_FG_CLUT_DATA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for GPHA_BGCWRS register *******************/ #define GPHA_BGCWRS_BG_CLUT_INDEX ((uint32_t)0x000000FF) #define GPHA_BGCWRS_BG_CLUT_EN ((uint32_t)0x00000100) /******************* Bit definition for GPHA_BGCDAT register *******************/ #define GPHA_BGCDAT_BG_CLUT_DATA ((uint32_t)0xFFFFFFFF) /******************************************************************************/ /* QSPI */ /******************************************************************************/ /******************* Bit definition for QSPI_CR register *******************/ #define QSPI_CR_EN ((uint32_t)0x00000001) #define QSPI_CR_ABORT ((uint32_t)0x00000002) #define QSPI_CR_DMAEN ((uint32_t)0x00000004) #define QSPI_CR_TCEN ((uint32_t)0x00000008) #define QSPI_CR_START ((uint32_t)0x00000020) #define QSPI_CR_DFM ((uint32_t)0x00000040) #define QSPI_CR_FSEL ((uint32_t)0x00000080) #define QSPI_CR_FTHRES ((uint32_t)0x00001F00) #define QSPI_CR_FTHRES_0 ((uint32_t)0x00000100) #define QSPI_CR_FTHRES_1 ((uint32_t)0x00000200) #define QSPI_CR_FTHRES_2 ((uint32_t)0x00000400) #define QSPI_CR_FTHRES_3 ((uint32_t)0x00000800) #define QSPI_CR_FTHRES_4 ((uint32_t)0x00001000) #define QSPI_CR_TEIE ((uint32_t)0x00010000) #define QSPI_CR_TCIE ((uint32_t)0x00020000) #define QSPI_CR_FTIE ((uint32_t)0x00040000) #define QSPI_CR_SMIE ((uint32_t)0x00080000) #define QSPI_CR_TOIE ((uint32_t)0x00100000) #define QSPI_CR_APMS ((uint32_t)0x00400000) #define QSPI_CR_PMM ((uint32_t)0x00800000) #define QSPI_CR_PRESCALER ((uint32_t)0xFF000000) #define QSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) #define QSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) #define QSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) #define QSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) #define QSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) #define QSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) #define QSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) #define QSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /******************* Bit definition for QSPI_DCR register *******************/ #define QSPI_DCR_CKMODE ((uint32_t)0x00000001) #define QSPI_DCR_CSHT ((uint32_t)0x00000700) #define QSPI_DCR_CSHT_0 ((uint32_t)0x00000100) #define QSPI_DCR_CSHT_1 ((uint32_t)0x00000200) #define QSPI_DCR_CSHT_2 ((uint32_t)0x00000400) #define QSPI_DCR_FSIZE ((uint32_t)0x001F0000) #define QSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) #define QSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) #define QSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) #define QSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) #define QSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /******************* Bit definition for QSPI_SR register *******************/ #define QSPI_SR_TEF ((uint32_t)0x00000001) #define QSPI_SR_TCF ((uint32_t)0x00000002) #define QSPI_SR_FTF ((uint32_t)0x00000004) #define QSPI_SR_SMF ((uint32_t)0x00000008) #define QSPI_SR_TOF ((uint32_t)0x00000010) #define QSPI_SR_BUSY ((uint32_t)0x00000020) #define QSPI_SR_FLEVEL ((uint32_t)0x00003F00) #define QSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) #define QSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) #define QSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) #define QSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) #define QSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) #define QSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) #define QSPI_SR_IDLEF ((uint32_t)0x00010000) /******************* Bit definition for QSPI_FCR register *******************/ #define QSPI_FCR_CTEF ((uint32_t)0x00000001) #define QSPI_FCR_CTCF ((uint32_t)0x00000002) #define QSPI_FCR_CSMF ((uint32_t)0x00000008) #define QSPI_FCR_CTOF ((uint32_t)0x00000010) /******************* Bit definition for QSPI_DLR register *******************/ #define QSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /******************* Bit definition for QSPI_CCR register *******************/ #define QSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) #define QSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) #define QSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) #define QSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) #define QSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) #define QSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) #define QSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) #define QSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) #define QSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) #define QSPI_CCR_IMODE ((uint32_t)0x00000300) #define QSPI_CCR_IMODE_0 ((uint32_t)0x00000100) #define QSPI_CCR_IMODE_1 ((uint32_t)0x00000200) #define QSPI_CCR_ADMODE ((uint32_t)0x00000C00) #define QSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) #define QSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) #define QSPI_CCR_ADSIZE ((uint32_t)0x00003000) #define QSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) #define QSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) #define QSPI_CCR_ABMODE ((uint32_t)0x0000C000) #define QSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) #define QSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) #define QSPI_CCR_ABSIZE ((uint32_t)0x00030000) #define QSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) #define QSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) #define QSPI_CCR_DCYC ((uint32_t)0x007C0000) #define QSPI_CCR_DCYC_0 ((uint32_t)0x00040000) #define QSPI_CCR_DCYC_1 ((uint32_t)0x00080000) #define QSPI_CCR_DCYC_2 ((uint32_t)0x00100000) #define QSPI_CCR_DCYC_3 ((uint32_t)0x00200000) #define QSPI_CCR_DCYC_4 ((uint32_t)0x00400000) #define QSPI_CCR_DMODE ((uint32_t)0x03000000) #define QSPI_CCR_DMODE_0 ((uint32_t)0x01000000) #define QSPI_CCR_DMODE_1 ((uint32_t)0x02000000) #define QSPI_CCR_FMODE ((uint32_t)0x0C000000) #define QSPI_CCR_FMODE_0 ((uint32_t)0x04000000) #define QSPI_CCR_FMODE_1 ((uint32_t)0x08000000) #define QSPI_CCR_SIOO ((uint32_t)0x10000000) /******************* Bit definition for QSPI_AR register *******************/ #define QSPI_AR_ADDR ((uint32_t)0xFFFFFFFF) /******************* Bit definition for QSPI_ABR register *******************/ #define QSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /******************* Bit definition for QSPI_DR register *******************/ #define QSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /******************* Bit definition for QSPI_PSMKR register *******************/ #define QSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /******************* Bit definition for QSPI_PSMAR register *******************/ #define QSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /******************* Bit definition for QSPI_PIR register *******************/ #define QSPI_PIR_INTERVAL ((uint16_t)0xFFFF) /******************* Bit definition for QSPI_LPIR register *******************/ #define QSPI_LPIR_TIMEOUT ((uint16_t)0xFFFF) #ifdef __cplusplus } #endif #ifdef __cplusplus extern "C" { #endif /* ch32h417_gpio.c -----------------------------------------------------------*/ /* MASK */ #define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) #define LSB_MASK ((uint16_t)0xFFFF) #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) #define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) /* ch32h417_adc.c ------------------------------------------------------------*/ /* ADC DISCNUM mask */ #define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) /* ADC DISCEN mask */ #define CTLR1_DISCEN_Set ((uint32_t)0x00000800) #define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) /* ADC JAUTO mask */ #define CTLR1_JAUTO_Set ((uint32_t)0x00000400) #define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) /* ADC JDISCEN mask */ #define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) #define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) /* ADC AWDCH mask */ #define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) /* ADC Analog watchdog enable mode mask */ #define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) /* CTLR1 register Mask */ /* CTLR1_CLEAR_Mask -> ADC_CTLR1_CLEAR_Mask */ #define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) /* ADC ADON mask */ #define CTLR2_ADON_Set ((uint32_t)0x00000001) #define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) /* ADC DMA mask */ #define CTLR2_DMA_Set ((uint32_t)0x00000100) #define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) /* ADC RSTCAL mask */ #define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) /* ADC CAL mask */ #define CTLR2_CAL_Set ((uint32_t)0x00000004) /* ADC SWSTART mask */ #define CTLR2_SWSTART_Set ((uint32_t)0x00400000) /* ADC EXTTRIG mask */ #define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) #define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) /* ADC Software start mask */ #define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) #define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) /* ADC JEXTSEL mask */ #define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) /* ADC JEXTTRIG mask */ #define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) #define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) /* ADC JSWSTART mask */ #define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) /* ADC injected software start mask */ #define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) #define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) /* ADC TSPD mask */ #define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) #define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) /* CTLR2 register Mask */ #define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) /* ADC SQx mask */ #define RSQR3_SQ_Set ((uint32_t)0x0000001F) #define RSQR2_SQ_Set ((uint32_t)0x0000001F) #define RSQR1_SQ_Set ((uint32_t)0x0000001F) /* RSQR1 register Mask */ #define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) /* ADC JSQx mask */ #define ISQR_JSQ_Set ((uint32_t)0x0000001F) /* ADC JL mask */ #define ISQR_JL_Set ((uint32_t)0x00300000) #define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) /* ADC SMPx mask */ #define SAMPTR1_SMP_Set ((uint32_t)0x00000007) #define SAMPTR2_SMP_Set ((uint32_t)0x00000007) /* ADC IDATARx registers offset */ #define IDATAR_Offset ((uint8_t)0x28) /* ADC1 RDATAR register base address */ #define RDATAR_ADDRESS ((uint32_t)0x4001244C) /* ch32h417_can.c ------------------------------------------------------------*/ /* CAN CTLR Register bits */ #define CTLR_DBF ((uint32_t)0x00010000) /* CAN Mailbox Transmit Request */ #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* CAN FCTLR Register bits */ #define FCTLR_FINIT ((uint32_t)0x00000001) /* Time out for INAK bit */ #define INAK_TIMEOUT ((uint32_t)0x0000FFFF) /* Time out for SLAK bit */ #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) /* Flags in TSTATR register */ #define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) /* Flags in RFIFO1 register */ #define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) /* Flags in RFIFO0 register */ #define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) /* Flags in STATR register */ #define CAN_FLAGS_STATR ((uint32_t)0x01000000) /* Flags in ERRSR register */ #define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) /* Mailboxes definition */ #define CAN_TXMAILBOX_0 ((uint8_t)0x00) #define CAN_TXMAILBOX_1 ((uint8_t)0x01) #define CAN_TXMAILBOX_2 ((uint8_t)0x02) #define CAN_MODE_MASK ((uint32_t) 0x00000003) /* ch32v417_dac.c ------------------------------------------------------------*/ /* CTLR register Mask */ #define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) /* DAC Dual Channels SWTR masks */ #define DUAL_SWTR_SET ((uint32_t)0x00000003) #define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) /* DHR registers offsets */ #define DHR12R1_OFFSET ((uint32_t)0x00000008) #define DHR12R2_OFFSET ((uint32_t)0x00000014) #define DHR12RD_OFFSET ((uint32_t)0x00000020) /* DOR register offset */ #define DOR_OFFSET ((uint32_t)0x0000002C) /* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) /* ch32h417_dma.c ------------------------------------------------------------*/ /* DMA1 Channelx interrupt pending bit masks */ #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) #define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) /* DMA2 Channelx interrupt pending bit masks */ #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) #define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) #define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) #define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) /* DMA registers Masks */ #define CFGR_CLEAR_Mask ((uint32_t)0xFFFE000F) /* ch32v00x_exti.c -----------------------------------------------------------*/ /* No interrupt selected */ #define EXTI_LINENONE ((uint32_t)0x00000) /* ch32h417_flash.c ----------------------------------------------------------*/ /* Flash Control Register bits */ #define CR_PG_Set ((uint32_t)0x00000001) #define CR_PG_Reset ((uint32_t)0xFFFFFFFE) #define CR_PER_Set ((uint32_t)0x00000002) #define CR_PER_Reset ((uint32_t)0xFFFFFFFD) #define CR_OPTPG_Set ((uint32_t)0x00000010) #define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) #define CR_OPTER_Set ((uint32_t)0x00000020) #define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) #define CR_STRT_Set ((uint32_t)0x00000040) #define CR_LOCK_Set ((uint32_t)0x00000080) #define CR_FLOCK_Set ((uint32_t)0x00008000) #define CR_PAGE_PG ((uint32_t)0x00010000) #define CR_BER ((uint32_t)0x00040000) #define CR_PG_STRT ((uint32_t)0x00200000) /* FLASH Status Register bits */ #define SR_BSY ((uint32_t)0x00000001) #define SR_WR_BSY ((uint32_t)0x00000002) #define SR_WRPRTERR ((uint32_t)0x00000010) #define SR_EOP ((uint32_t)0x00000020) /* FLASH Mask */ #define RDPRT_Mask ((uint32_t)0x00000002) #define WRP0_Mask ((uint32_t)0x000000FF) #define WRP1_Mask ((uint32_t)0x0000FF00) #define WRP2_Mask ((uint32_t)0x00FF0000) #define WRP3_Mask ((uint32_t)0xFF000000) #define OB_USER_BFB2 ((uint16_t)0x0008) /* FLASH Keys */ #define RDP_Key ((uint16_t)0x00A5) #define FLASH_KEY1 ((uint32_t)0x45670123) #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /* FLASH BANK address */ #define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) /* Delay definition */ #define EraseTimeout ((uint32_t)0x0A000000) #define ProgramTimeout ((uint32_t)0x0A000000) /* Flash Program Valid Address */ #define ValidAddrStart (FLASH_BASE) #define ValidAddrEnd_Dual (FLASH_BASE + 0xF0000) #define ValidAddrEnd_Signal (FLASH_BASE + 0x78000) /* FLASH Size */ #define Size_256B 0x100 #define Size_4KB 0x1000 #define Size_8KB 0x2000 #define Size_32KB 0x8000 #define Size_64KB 0x10000 /* ch32h417_fmc.c -----------------------------------------------------------*/ /* FMC BCRx Mask */ #define BCR_MBKEN_Set ((uint32_t)0x00000001) #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) #define BCR_FACCEN_Set ((uint32_t)0x00000040) /* FMC PCRx Mask */ #define PCR_PBKEN_Set ((uint32_t)0x00000004) #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) #define PCR_ECCEN_Set ((uint32_t)0x00000040) #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) #define PCR_MemoryType_NAND ((uint32_t)0x00000008) /* ch32h417_i2c.c ------------------------------------------------------------*/ /* I2C SPE mask */ #define CTLR1_PE_Set ((uint16_t)0x0001) #define CTLR1_PE_Reset ((uint16_t)0xFFFE) /* I2C START mask */ #define CTLR1_START_Set ((uint16_t)0x0100) #define CTLR1_START_Reset ((uint16_t)0xFEFF) /* I2C STOP mask */ #define CTLR1_STOP_Set ((uint16_t)0x0200) #define CTLR1_STOP_Reset ((uint16_t)0xFDFF) /* I2C ACK mask */ #define CTLR1_ACK_Set ((uint16_t)0x0400) #define CTLR1_ACK_Reset ((uint16_t)0xFBFF) /* I2C ENGC mask */ #define CTLR1_ENGC_Set ((uint16_t)0x0040) #define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) /* I2C SWRST mask */ #define CTLR1_SWRST_Set ((uint16_t)0x8000) #define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) /* I2C PEC mask */ #define CTLR1_PEC_Set ((uint16_t)0x1000) #define CTLR1_PEC_Reset ((uint16_t)0xEFFF) /* I2C ENPEC mask */ #define CTLR1_ENPEC_Set ((uint16_t)0x0020) #define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) /* I2C ENARP mask */ #define CTLR1_ENARP_Set ((uint16_t)0x0010) #define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) /* I2C NOSTRETCH mask */ #define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) #define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) /* I2C registers Masks */ /* CTLR1_CLEAR_Mask -> I2C_CTLR1_CLEAR_Mask */ #define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) /* I2C DMAEN mask */ #define CTLR2_DMAEN_Set ((uint16_t)0x0800) #define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) /* I2C LAST mask */ #define CTLR2_LAST_Set ((uint16_t)0x1000) #define CTLR2_LAST_Reset ((uint16_t)0xEFFF) /* I2C FREQ mask */ #define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) /* I2C ADD0 mask */ #define OADDR1_ADD0_Set ((uint16_t)0x0001) #define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) /* I2C ENDUAL mask */ #define OADDR2_ENDUAL_Set ((uint16_t)0x0001) #define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) /* I2C ADD2 mask */ #define OADDR2_ADD2_Reset ((uint16_t)0xFF01) /* I2C F/S mask */ #define CKCFGR_FS_Set ((uint16_t)0x8000) /* I2C CCR mask */ #define CKCFGR_CCR_Set ((uint16_t)0x0FFF) /* I2C FLAG mask */ /* FLAG_Mask -> I2C_FLAG_Mask*/ #define I2C_FLAG_Mask ((uint32_t)0x00FFFFFF) /* I2C Interrupt Enable mask */ #define ITEN_Mask ((uint32_t)0x07000000) /* ch32v00x_iwdg.c -----------------------------------------------------------*/ /* CTLR register bit mask */ #define CTLR_KEY_Reload ((uint16_t)0xAAAA) #define CTLR_KEY_Enable ((uint16_t)0xCCCC) /* ch32h417_pwr.c ------------------------------------------------------------*/ /* PWR registers bit mask */ /* CTLR register bit mask */ #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFE) #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) /* ch32h417_rcc.c ------------------------------------------------------------*/ /* CTLR register bit mask */ #define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) #define CTLR_HSEBYP_Set ((uint32_t)0x00040000) #define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) #define CTLR_HSEON_Set ((uint32_t)0x00010000) #define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) /* CFGR0 register bit mask */ #define CFGR0_SWS_Mask ((uint32_t)0x0000000C) #define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) #define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) /* RSTSCKR register bit mask */ #define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) /* RCC Flag Mask */ /* FLAG_Mask -> RCC_FLAG_Mask */ #define RCC_FLAG_Mask ((uint8_t)0x1F) #ifndef __ASSEMBLER__ static __I uint8_t PLLMULTable[32] = {4,6,7,8,17,9,19,10,21,11,23,12,25,13,14,15,16,17,18,19,20,22,24,26,28,30,32,34,36,38,40,59}; static __I uint8_t HBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; static __I uint8_t SERDESPLLMULTable[16] = {25, 28, 30, 32, 35, 38, 40, 45, 50, 56, 60, 64, 70, 76, 80, 90}; static __I uint8_t FPRETable[4] = {0, 1, 2, 2}; static __I uint8_t PPRE2Table[8] = {0, 0, 0, 0, 1, 2, 3, 4}; static __I uint8_t ADCPRETable[4] = {2, 4, 6, 8}; #endif /* ch32v20x_rtc.c ------------------------------------------------------------*/ /* RTC_Private_Defines */ #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ /* ch32v00x_sdio.c -----------------------------------------------------------*/ #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) /* CLKCR register clear mask */ #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) /* SDIO PWRCTRL Mask */ #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) /* SDIO DCTRL Clear Mask */ #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) /* CMD Register clear mask */ #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) /* SDIO RESP Registers Address */ #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) /* ch32v00x_spi.c ------------------------------------------------------------*/ /* SPI SPE mask */ #define CTLR1_SPE_Set ((uint16_t)0x0040) #define CTLR1_SPE_Reset ((uint16_t)0xFFBF) /* I2S I2SE mask */ #define I2SCFGR_I2SE_Set ((uint16_t)0x0400) #define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) /* SPI CRCNext mask */ #define CTLR1_CRCNext_Set ((uint16_t)0x1000) /* SPI CRCEN mask */ #define CTLR1_CRCEN_Set ((uint16_t)0x2000) #define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) /* SPI SSOE mask */ #define CTLR2_SSOE_Set ((uint16_t)0x0004) #define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) /* SPI registers Masks */ //Editor's Note: Overloaded Definition #define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) #define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) /* SPI or I2S mode selection masks */ #define SPI_Mode_Select ((uint16_t)0xF7FF) #define I2S_Mode_Select ((uint16_t)0x0800) /* I2S clock source selection masks */ #define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) #define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) #define I2S_MUL_MASK ((uint32_t)(0x0000F000)) #define I2S_DIV_MASK ((uint32_t)(0x000000F0)) /* ch32v00x_tim.c ------------------------------------------------------------*/ /* TIM registers bit mask */ #define SMCFGR_ETR_Mask ((uint16_t)0x00FF) #define CHCTLR_Offset ((uint16_t)0x0018) #define CCER_CCE_Set ((uint16_t)0x0001) #define CCER_CCNE_Set ((uint16_t)0x0004) /* ch32h417_usart.c ----------------------------------------------------------*/ /* USART_Private_Defines */ #define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ #define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ #define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ #define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ #define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ #define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ /* CTLR1_CLEAR_Mask -> USART_CTLR1_CLEAR_Mask */ #define USART_CTLR1_CLEAR_Mask ((uint16_t)0x29F3) /* USART CTLR1 Mask */ #define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ #define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ #define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ #define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ #define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ #define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ #define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ #define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ #define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ #define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ #define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ #define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ #define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ #define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ #define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ #define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ #define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ #define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ #define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ /* ch32v00x_wwdg.c ------------------------------------------------------------*/ /* CTLR register bit mask */ #define CTLR_WDGA_Set ((uint32_t)0x00000080) /* CFGR register bit mask */ #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) #define CFGR_W_Mask ((uint32_t)0xFFFFFF80) #define BIT_Mask ((uint8_t)0x7F) /* ch32h417_adc.h ------------------------------------------------------------*/ /* ADC_mode */ #define ADC_Mode_Independent ((uint32_t)0x00000000) #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) #define ADC_Mode_InjecSimult ((uint32_t)0x00050000) #define ADC_Mode_RegSimult ((uint32_t)0x00060000) #define ADC_Mode_FastInterl ((uint32_t)0x00070000) #define ADC_Mode_SlowInterl ((uint32_t)0x00080000) #define ADC_Mode_AlterTrig ((uint32_t)0x00090000) /* ADC_external_trigger_sources_for_regular_channels_conversion */ #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /* ADC_data_align */ #define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Left ((uint32_t)0x00000800) /* ADC_channels */ #define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_12 ((uint8_t)0x0C) #define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_16 ((uint8_t)0x10) #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) /*ADC_output_buffer*/ #define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) #define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) /*ADC_pga*/ #define ADC_Pga_1 ((uint32_t)0x00000000) #define ADC_Pga_4 ((uint32_t)0x08000000) #define ADC_Pga_16 ((uint32_t)0x10000000) #define ADC_Pga_64 ((uint32_t)0x18000000) /* ADC_sampling_time */ #define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) #define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) #define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) #define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) #define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) #define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) #define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) #define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) /* ADC_external_trigger_sources_for_injected_channels_conversion */ #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /* ADC_injected_channel_selection */ #define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_4 ((uint8_t)0x20) /* ADC_analog_watchdog_selection */ #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /* ADC_interrupts_definition */ #define ADC_IT_EOC ((uint16_t)0x0220) #define ADC_IT_AWD ((uint16_t)0x0140) #define ADC_IT_JEOC ((uint16_t)0x0480) /* ADC_flags_definition */ #define ADC_FLAG_AWD ((uint16_t)0x0001) #define ADC_FLAG_EOC ((uint16_t)0x0002) #define ADC_FLAG_JEOC ((uint16_t)0x0004) #define ADC_FLAG_JSTRT ((uint16_t)0x0008) #define ADC_FLAG_STRT ((uint16_t)0x0010) #define ADC_FLAG_RST ((uint16_t)0x8000) /* ADC_SMP_CFG_MODE_definition */ #define ADC_SMP_CFG_MODE0 ((uint8_t)0x00) #define ADC_SMP_CFG_MODE1 ((uint8_t)0x01) /* ADC_CalibrationVoltage_Mode_definition */ #define ADC_CalibrationVoltage_Mode0 ((uint32_t)0x00000000) #define ADC_CalibrationVoltage_Mode1 ((uint32_t)0x00000010) #define ADC_CalibrationVoltage_Mode2 ((uint32_t)0x00000020) #define ADC_CalibrationVoltage_Mode3 ((uint32_t)0x00000030) /* ch32h417_dbgmcu.h ---------------------------------------------------------*/ #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) #define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) #define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) #define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) #define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) #define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) #define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) #define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) #define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) #define DBGMCU_TIM9_STOP ((uint32_t)0x00100000) #define DBGMCU_TIM10_STOP ((uint32_t)0x00200000) #define DBGMCU_TIM11_STOP ((uint32_t)0x00400000) #define DBGMCU_TIM12_STOP ((uint32_t)0x00800000) #define DBGMCU_LPTIM1_STOP ((uint32_t)0x01000000) #define DBGMCU_LPTIM2_STOP ((uint32_t)0x02000000) #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x04000000) #define DBGMCU_I2C4_SMBUS_TIMEOUT ((uint32_t)0x08000000) #define DBGMCU_CAN1_STOP ((uint32_t)0x10000000) #define DBGMCU_CAN2_STOP ((uint32_t)0x20000000) #define DBGMCU_CAN3_STOP ((uint32_t)0x40000000) /* ch32h417_dma.h ------------------------------------------------------------*/ /* DMA_data_transfer_direction */ #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) /* DMA_peripheral_incremented_mode */ #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) /* DMA_memory_incremented_mode */ #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) /* DMA_peripheral_data_size */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) #define DMA_PeripheralDataSize_256 ((uint32_t)0x00000300) /* DMA_memory_data_size */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) #define DMA_MemoryDataSize_256 ((uint32_t)0x00000C00) /* DMA_circular_normal_mode */ #define DMA_Mode_Circular ((uint32_t)0x00000020) #define DMA_Mode_Normal ((uint32_t)0x00000000) /* DMA_priority_level */ #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) #define DMA_Priority_High ((uint32_t)0x00002000) #define DMA_Priority_Medium ((uint32_t)0x00001000) #define DMA_Priority_Low ((uint32_t)0x00000000) /* DMA_memory_to_memory */ #define DMA_M2M_Enable ((uint32_t)0x00004000) #define DMA_M2M_Disable ((uint32_t)0x00000000) /* DMA_interrupts_definition */ #define DMA_IT_TC ((uint32_t)0x00000002) #define DMA_IT_HT ((uint32_t)0x00000004) #define DMA_IT_TE ((uint32_t)0x00000008) #define DMA1_IT_GL1 ((uint32_t)0x00000001) #define DMA1_IT_TC1 ((uint32_t)0x00000002) #define DMA1_IT_HT1 ((uint32_t)0x00000004) #define DMA1_IT_TE1 ((uint32_t)0x00000008) #define DMA1_IT_GL2 ((uint32_t)0x00000010) #define DMA1_IT_TC2 ((uint32_t)0x00000020) #define DMA1_IT_HT2 ((uint32_t)0x00000040) #define DMA1_IT_TE2 ((uint32_t)0x00000080) #define DMA1_IT_GL3 ((uint32_t)0x00000100) #define DMA1_IT_TC3 ((uint32_t)0x00000200) #define DMA1_IT_HT3 ((uint32_t)0x00000400) #define DMA1_IT_TE3 ((uint32_t)0x00000800) #define DMA1_IT_GL4 ((uint32_t)0x00001000) #define DMA1_IT_TC4 ((uint32_t)0x00002000) #define DMA1_IT_HT4 ((uint32_t)0x00004000) #define DMA1_IT_TE4 ((uint32_t)0x00008000) #define DMA1_IT_GL5 ((uint32_t)0x00010000) #define DMA1_IT_TC5 ((uint32_t)0x00020000) #define DMA1_IT_HT5 ((uint32_t)0x00040000) #define DMA1_IT_TE5 ((uint32_t)0x00080000) #define DMA1_IT_GL6 ((uint32_t)0x00100000) #define DMA1_IT_TC6 ((uint32_t)0x00200000) #define DMA1_IT_HT6 ((uint32_t)0x00400000) #define DMA1_IT_TE6 ((uint32_t)0x00800000) #define DMA1_IT_GL7 ((uint32_t)0x01000000) #define DMA1_IT_TC7 ((uint32_t)0x02000000) #define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA1_IT_GL8 ((uint32_t)0x10000000) #define DMA1_IT_TC8 ((uint32_t)0x20000000) #define DMA1_IT_HT8 ((uint32_t)0x40000000) #define DMA1_IT_TE8 ((uint32_t)0x80000000) #define DMA2_IT_GL1 ((uint32_t)0x00000001) #define DMA2_IT_TC1 ((uint32_t)0x00000002) #define DMA2_IT_HT1 ((uint32_t)0x00000004) #define DMA2_IT_TE1 ((uint32_t)0x00000008) #define DMA2_IT_GL2 ((uint32_t)0x00000010) #define DMA2_IT_TC2 ((uint32_t)0x00000020) #define DMA2_IT_HT2 ((uint32_t)0x00000040) #define DMA2_IT_TE2 ((uint32_t)0x00000080) #define DMA2_IT_GL3 ((uint32_t)0x00000100) #define DMA2_IT_TC3 ((uint32_t)0x00000200) #define DMA2_IT_HT3 ((uint32_t)0x00000400) #define DMA2_IT_TE3 ((uint32_t)0x00000800) #define DMA2_IT_GL4 ((uint32_t)0x00001000) #define DMA2_IT_TC4 ((uint32_t)0x00002000) #define DMA2_IT_HT4 ((uint32_t)0x00004000) #define DMA2_IT_TE4 ((uint32_t)0x00008000) #define DMA2_IT_GL5 ((uint32_t)0x00010000) #define DMA2_IT_TC5 ((uint32_t)0x00020000) #define DMA2_IT_HT5 ((uint32_t)0x00040000) #define DMA2_IT_TE5 ((uint32_t)0x00080000) #define DMA2_IT_GL6 ((uint32_t)0x00100000) #define DMA2_IT_TC6 ((uint32_t)0x00200000) #define DMA2_IT_HT6 ((uint32_t)0x00400000) #define DMA2_IT_TE6 ((uint32_t)0x00800000) #define DMA2_IT_GL7 ((uint32_t)0x01000000) #define DMA2_IT_TC7 ((uint32_t)0x02000000) #define DMA2_IT_HT7 ((uint32_t)0x04000000) #define DMA2_IT_TE7 ((uint32_t)0x08000000) #define DMA2_IT_GL8 ((uint32_t)0x10000000) #define DMA2_IT_TC8 ((uint32_t)0x20000000) #define DMA2_IT_HT8 ((uint32_t)0x40000000) #define DMA2_IT_TE8 ((uint32_t)0x80000000) /* DMA_flags_definition */ #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA1_FLAG_GL8 ((uint32_t)0x10000000) #define DMA1_FLAG_TC8 ((uint32_t)0x20000000) #define DMA1_FLAG_HT8 ((uint32_t)0x40000000) #define DMA1_FLAG_TE8 ((uint32_t)0x80000000) #define DMA2_FLAG_GL1 ((uint32_t)0x00000001) #define DMA2_FLAG_TC1 ((uint32_t)0x00000002) #define DMA2_FLAG_HT1 ((uint32_t)0x00000004) #define DMA2_FLAG_TE1 ((uint32_t)0x00000008) #define DMA2_FLAG_GL2 ((uint32_t)0x00000010) #define DMA2_FLAG_TC2 ((uint32_t)0x00000020) #define DMA2_FLAG_HT2 ((uint32_t)0x00000040) #define DMA2_FLAG_TE2 ((uint32_t)0x00000080) #define DMA2_FLAG_GL3 ((uint32_t)0x00000100) #define DMA2_FLAG_TC3 ((uint32_t)0x00000200) #define DMA2_FLAG_HT3 ((uint32_t)0x00000400) #define DMA2_FLAG_TE3 ((uint32_t)0x00000800) #define DMA2_FLAG_GL4 ((uint32_t)0x00001000) #define DMA2_FLAG_TC4 ((uint32_t)0x00002000) #define DMA2_FLAG_HT4 ((uint32_t)0x00004000) #define DMA2_FLAG_TE4 ((uint32_t)0x00008000) #define DMA2_FLAG_GL5 ((uint32_t)0x00010000) #define DMA2_FLAG_TC5 ((uint32_t)0x00020000) #define DMA2_FLAG_HT5 ((uint32_t)0x00040000) #define DMA2_FLAG_TE5 ((uint32_t)0x00080000) #define DMA2_FLAG_GL6 ((uint32_t)0x00100000) #define DMA2_FLAG_TC6 ((uint32_t)0x00200000) #define DMA2_FLAG_HT6 ((uint32_t)0x00400000) #define DMA2_FLAG_TE6 ((uint32_t)0x00800000) #define DMA2_FLAG_GL7 ((uint32_t)0x01000000) #define DMA2_FLAG_TC7 ((uint32_t)0x02000000) #define DMA2_FLAG_HT7 ((uint32_t)0x04000000) #define DMA2_FLAG_TE7 ((uint32_t)0x08000000) #define DMA2_FLAG_GL8 ((uint32_t)0x10000000) #define DMA2_FLAG_TC8 ((uint32_t)0x20000000) #define DMA2_FLAG_HT8 ((uint32_t)0x40000000) #define DMA2_FLAG_TE8 ((uint32_t)0x80000000) /* DMA_MuxChannel_definition */ #define DMA_MuxChannel1 ((uint8_t)0x00) #define DMA_MuxChannel2 ((uint8_t)0x01) #define DMA_MuxChannel3 ((uint8_t)0x02) #define DMA_MuxChannel4 ((uint8_t)0x03) #define DMA_MuxChannel5 ((uint8_t)0x04) #define DMA_MuxChannel6 ((uint8_t)0x05) #define DMA_MuxChannel7 ((uint8_t)0x06) #define DMA_MuxChannel8 ((uint8_t)0x07) #define DMA_MuxChannel9 ((uint8_t)0x08) #define DMA_MuxChannel10 ((uint8_t)0x09) #define DMA_MuxChannel11 ((uint8_t)0x0A) #define DMA_MuxChannel12 ((uint8_t)0x0B) #define DMA_MuxChannel13 ((uint8_t)0x0C) #define DMA_MuxChannel14 ((uint8_t)0x0D) #define DMA_MuxChannel15 ((uint8_t)0x0E) #define DMA_MuxChannel16 ((uint8_t)0x0F) /* DMA_BufferMode_Memory */ #define DMA_SingleBufferMode ((uint32_t)0x00000000) #define DMA_DoubleBufferMode ((uint32_t)0x00008000) /* DMA_DoubleBufferMode_Memory */ #define DMA_DoubleBufferMode_Memory_0 ((uint32_t)0x00000000) #define DMA_DoubleBufferMode_Memory_1 ((uint32_t)0x00010000) /* ch32h417_eth.h ------------------------------------------------------------*/ #define PHY_10BASE_T_LINKED 1 #define PHY_10BASE_T_NOT_LINKED 0 #define DMA_TPS_Mask ((uint32_t)0x00700000) #define DMA_RPS_Mask ((uint32_t)0x000E0000) /* ETH delay.Just for Ethernet */ #define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ /* definition for Ethernet frame */ #define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ #define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ #define ETH_CRC 4 /* Ethernet CRC */ #define ETH_EXTRA 2 /* Extra bytes in some cases */ #define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ #define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ #define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ #define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ /** DMA Tx Desciptor ----------------------------------------------------------------------------------------------- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | ----------------------------------------------------------------------------------------------- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | ----------------------------------------------------------------------------------------------- TDES2 | Buffer1 Address [31:0] | ----------------------------------------------------------------------------------------------- TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | ------------------------------------------------------------------------------------------------ */ /* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ #define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ #define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ #define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ #define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ #define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ #define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ #define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ #define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ #define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ #define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ #define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ #define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ #define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ #define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ #define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ #define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ #define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ #define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ #define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ #define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ #define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ #define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ #define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ #define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ #define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ #define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ #define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ /* Field definition of TDES1 register */ #define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ #define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ /* Field definition of TDES2 register */ #define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ /* Field definition of TDES3 register */ #define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ /** DMA Rx Desciptor --------------------------------------------------------------------------------------------------------------------- RDES0 | OWN(31) | Status [30:0] | --------------------------------------------------------------------------------------------------------------------- RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | --------------------------------------------------------------------------------------------------------------------- RDES2 | Buffer1 Address [31:0] | --------------------------------------------------------------------------------------------------------------------- RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | ---------------------------------------------------------------------------------------------------------------------- */ /* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ #define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ #define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ #define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ #define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ #define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ #define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ #define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ #define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ #define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ #define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ #define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ #define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ #define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ #define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ #define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ #define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ #define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ #define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ #define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ /* Bit or field definition of RDES1 register */ #define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ #define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ #define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ #define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ #define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ /* Field definition of RDES2 register */ #define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ /* Field definition of RDES3 register */ #define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ /* Timeout threshold of Reading or writing PHY registers */ #define PHY_READ_TO ((uint32_t)0x004FFFFF) #define PHY_WRITE_TO ((uint32_t)0x0004FFFF) /* Delay time after reset PHY */ #define PHY_ResetDelay ((uint32_t)0x000FFFFF) /* Delay time after configure PHY */ #define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) /* PHY basic register */ #define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ #define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ #define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ #define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ #define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ #define PHY_BMCR PHY_BCR #define PHY_BMSR PHY_BSR /* Bit or field definition for PHY basic control register */ #define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ #define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ #define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ #define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ #define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ #define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ /* Bit or field definition for PHY basic status register */ #define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ #define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ #define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ #define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ /* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ #define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) #define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) /* MAC autoNegotiation enable or disable */ #define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) #define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) /* MAC watchdog enable or disable */ #define ETH_Watchdog_Enable ((uint32_t)0x00000000) #define ETH_Watchdog_Disable ((uint32_t)0x00800000) /* Bit description - MAC jabber enable or disable */ #define ETH_Jabber_Enable ((uint32_t)0x00000000) #define ETH_Jabber_Disable ((uint32_t)0x00400000) /* Value of minimum IFG between frames during transmission */ #define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ #define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ #define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ #define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ #define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ #define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ #define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ #define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ /* MAC carrier sense enable or disable */ #define ETH_CarrierSense_Enable ((uint32_t)0x00000000) #define ETH_CarrierSense_Disable ((uint32_t)0x00010000) /* MAC speed */ #define ETH_Speed_10M ((uint32_t)0x00000000) #define ETH_Speed_100M ((uint32_t)0x00004000) #define ETH_Speed_1000M ((uint32_t)0x00008000) /* MAC receive own enable or disable */ #define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) #define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) /* MAC Loopback mode enable or disable */ #define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) #define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) /* MAC fullDuplex or halfDuplex */ #define ETH_Mode_FullDuplex ((uint32_t)0x00000800) #define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) /* MAC offload checksum enable or disable */ #define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) #define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) /* MAC transmission retry enable or disable */ #define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) #define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) /* MAC automatic pad CRC strip enable or disable */ #define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) #define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) /* MAC backoff limitation */ #define ETH_BackOffLimit_10 ((uint32_t)0x00000000) #define ETH_BackOffLimit_8 ((uint32_t)0x00000020) #define ETH_BackOffLimit_4 ((uint32_t)0x00000040) #define ETH_BackOffLimit_1 ((uint32_t)0x00000060) /* MAC deferral check enable or disable */ #define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) #define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) /* Bit description : MAC receive all frame enable or disable */ #define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) #define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) /* MAC backoff limitation */ #define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) #define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) #define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) /* MAC Pass control frames */ #define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ #define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ #define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ /* MAC broadcast frames reception */ #define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) #define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) /* MAC destination address filter */ #define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) #define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) /* MAC Promiscuous mode enable or disable */ #define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) #define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) /* MAC multicast frames filter */ #define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) #define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) #define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) #define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) /* MAC unicast frames filter */ #define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) #define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) #define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) /* Bit description : MAC zero quanta pause */ #define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) #define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) /* Field description : MAC pause low threshold */ #define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ #define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ #define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ #define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ /* MAC unicast pause frame detect enable or disable*/ #define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) #define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) /* MAC receive flow control frame enable or disable */ #define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) #define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) /* MAC transmit flow control enable or disable */ #define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) #define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) /* MAC VLAN tag comparison */ #define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) #define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) /* MAC flag */ #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ /* MAC interrupt */ #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ /* MAC address */ #define ETH_MAC_Address0 ((uint32_t)0x00000000) #define ETH_MAC_Address1 ((uint32_t)0x00000008) #define ETH_MAC_Address2 ((uint32_t)0x00000010) #define ETH_MAC_Address3 ((uint32_t)0x00000018) /* MAC address filter select */ #define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) #define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) /* MAC address mask */ #define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ #define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ #define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ #define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ #define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ #define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ /******************************************************************************/ /* */ /* MAC Descriptor Register */ /* */ /******************************************************************************/ /* DMA descriptor segment */ #define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ #define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ /* DMA descriptor checksum setting */ #define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ #define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ #define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ #define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ /* DMA RX & TX buffer */ #define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ #define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ /******************************************************************************/ /* */ /* ETH DMA Register */ /* */ /******************************************************************************/ /* DMA drop TCPIP checksum error frame enable or disable */ #define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) #define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) /* DMA receive store forward enable or disable */ #define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) #define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) /* DMA flush received frame enable or disable */ #define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) #define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) /* DMA transmit store forward enable or disable */ #define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) #define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) /* DMA transmit threshold control */ #define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ #define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ #define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ #define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ #define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ #define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ #define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ #define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ /* DMA forward error frames */ #define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) #define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) /* DMA forward undersized good frames enable or disable */ #define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) #define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) /* DMA receive threshold control */ #define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ #define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ #define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ #define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ /* DMA second frame operate enable or disable */ #define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) #define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) /* Address aligned beats enable or disable */ #define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) #define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) /* DMA Fixed burst enable or disable */ #define ETH_FixedBurst_Enable ((uint32_t)0x00010000) #define ETH_FixedBurst_Disable ((uint32_t)0x00000000) /* RX DMA burst length */ #define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ #define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ #define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ #define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ #define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ #define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ /* TX DMA burst length */ #define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ #define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ #define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ #define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ #define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ #define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ /* DMA arbitration_round robin */ #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) #define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) #define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) /* DMA interrupt FALG */ #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ #define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ #define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ #define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ #define ETH_DMA_FLAG_PHYSR ((uint32_t)0x00000800) /* PHY interrupt */ #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ /* DMA interrupt */ #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ #define ETH_DMA_IT_PHYSR ((uint32_t)0x00000800) /* Internal PHY link status change interrupt */ #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ #define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ #define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ /* DMA transmit process */ #define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ #define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ #define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ #define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ #define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ #define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ /* DMA receive Process */ #define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ #define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ #define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ #define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ #define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ #define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ /* DMA overflow */ #define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ #define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ /********************************************************************************* * Ethernet PMT defines **********************************************************************************/ /* PMT flag */ #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ /********************************************************************************* * Ethernet MMC defines **********************************************************************************/ /* MMC TX interrupt flag */ #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ /* MMC RX interrupt flag */ #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ /* MMC description */ #define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ #define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ #define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ #define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ #define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ #define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ #define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ #define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ /********************************************************************************* * Ethernet PTP defines **********************************************************************************/ /* PTP fine update method or coarse Update method */ #define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ #define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ /* PTP time stamp control */ #define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ #define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ #define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ #define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ /* PTP positive/negative time value */ #define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ #define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ /******************************************************************************/ /* */ /* PTP Register */ /* */ /******************************************************************************/ #define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ #define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ #define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ #define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ #define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ #define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ #define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ #define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ #define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ #define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ #define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ #define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ #define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ #define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ #define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ #define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ #define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ #define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ #define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ #define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ #define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ #define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ #define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ #define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ #define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ #define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ #define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ #define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ #define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ /******************************************************************************/ /* */ /* ETH MAC Register */ /* */ /******************************************************************************/ #define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ #define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ #define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ #define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ #define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ #define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ #define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ #define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ #define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ #define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ #define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ #define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ #define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ #define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ #define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ #define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ #define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ #define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ #define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ #define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ #define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ #define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ #define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ #define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ #define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ #define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ #define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ #define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ #define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ #define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ #define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ #define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ #define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ #define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ #define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ #define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ #define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ #define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ #define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ #define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ #define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ #define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ #define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ #define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ #define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - RSVD - Filter1 Command - RSVD - Filter0 Command Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ #define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ #define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ #define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ #define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ #define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ #define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ #define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ #define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ #define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ #define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ #define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ #define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ #define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ #define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ #define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ #define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ #define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ #define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ #define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ #define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ #define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ #define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ #define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ #define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ #define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ #define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ #define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ #define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ #define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ #define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ /****************************************************************************** * * ETH MMC Register * ******************************************************************************/ #define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ #define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ #define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ #define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ #define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ #define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ #define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ #define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ #define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ #define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ #define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ #define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ #define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ #define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ #define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ #define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ #define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ #define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ #define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ #define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ #define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ #define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ #define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ #define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ /****************************************************************************** * * ETH Precise Clock Protocol Register * ******************************************************************************/ #define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ #define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ #define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ #define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ #define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ #define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ #define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ #define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ #define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ #define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ #define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ #define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ #define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ #define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ #define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ #define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ #define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ #define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ #define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ #define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ #define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ #define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ #define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ #define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ #define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ #define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ /****************************************************************************** * * ETH DMA Register * ******************************************************************************/ #define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ #define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ #define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ #define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ #define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ #define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ #define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ #define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ #define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ #define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ #define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ #define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ #define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ #define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ #define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ #define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ #define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ #define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ #define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ #define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ #define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ #define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ #define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ #define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ #define ETH_DMASR_PLS ((unsigned int)0x00000800) /* PHY interrupt status*/ #define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ #define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ #define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ #define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ #define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ #define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ #define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ #define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ #define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ #define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ #define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ #define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ #define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ #define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ #define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ #define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ #define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ #define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ #define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ #define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ #define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ #define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ #define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ #define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ #define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ #define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ #define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ #define ETH_DMAIER_PLE ((unsigned int)0x00000800) /* PHY interrupt enable*/ #define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ #define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ #define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ #define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ #define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ #define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ #define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ #define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ #define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ #define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ #define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ #define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ #define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ #define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ #define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ #define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ #define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ #define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ #define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ #define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ #define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ /* ETHERNET MACMIIAR register Mask */ #define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) /* ETHERNET MACCR register Mask */ #define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) /* ETHERNET MACFCR register Mask */ #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) /* ETHERNET DMAOMR register Mask */ #define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) /* ETHERNET Remote Wake-up frame register length */ #define ETH_WAKEUP_REGISTER_LENGTH 8 /* ETHERNET Missed frames counter Shift */ #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 /* ETHERNET DMA Tx descriptors Collision Count Shift */ #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 /* ETHERNET DMA Rx descriptors Frame Length Shift */ #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 /* ETHERNET errors */ #define ETH_ERROR ((uint32_t)0) #define ETH_SUCCESS ((uint32_t)1) #define PHY_REG_PAGE0 0x00 #define PHY_REG_PAGE4 0x04 #define PHY_REG_PAGE7 0x07 #define PHY_REG_PAGE17 0x11 #define PHY_REG_PAGE18 0x12 /* PHY basic register */ #define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ #define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ #define PHY_BMCR PHY_BCR #define PHY_BMSR PHY_BSR #define PHY_PHYIDR1 0x02 /*PHY Identifier Register*/ #define PHY_PHYIDR2 0x03 /*PHY Identifier Register*/ #define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ #define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ #define PHY_PAG_SEL 0x1F /****************Page 0********************/ #define PHY_CONTROL1 0x19 #define PHY_STATUS 0x1A #define PHY_INTERRUPT_IND 0x1E /****************Page 7********************/ #define PHY_INTERRUPT_MASK 0x13 #define PHY_SPEED_100M_MODE (1<<3) #define PHY_SPEED_10M_MODE (1<<2) #define PHY_FULL_DUPLEX_MODE (1<<1) #define PHY_HALF_DUPLEX_MODE (1<<1) /* ch32h417_exti.h -----------------------------------------------------------*/ #ifndef __ASSEMBLER__ /* EXTI mode enumeration */ typedef enum { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }EXTIMode_TypeDef; /* EXTI Trigger enumeration */ typedef enum { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }EXTITrigger_TypeDef; #endif /* EXTI_Lines */ #define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ #define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ #define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ #define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ #define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ #define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ #define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ #define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ #define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ #define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ #define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ #define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ #define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ #define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ #define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ #define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 Connected to the USBHS wakeup event */ #define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 Connected to the SWPMI wakeup event*/ #define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 Connected to the USBFSOTG Wakeup event */ #define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 Connected to the USBPD Wakeup event */ #define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 Connected to the ETH Wakeup event */ #define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 Connected to the USBSS Wakeup event */ #define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 Connected to the LPTIM1 Wakeup event */ #define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the LPTIM2 Wakeup event */ #define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the I3C Wakeup event */ /* ch32h417_flash.h ----------------------------------------------------------*/ #ifndef __ASSEMBLER__ /* FLASH Status */ typedef enum { FLASH_BUSY = 1, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT, FLASH_OP_RANGE_ERROR = 0xFD, FLASH_ALIGN_ERROR = 0xFE, FLASH_ADR_RANGE_ERROR = 0xFF, }FLASH_Status; #endif /* Write Protect (dual flash mode - 8K bytes/sector) (single flash mode - 4K bytes/sector)*/ #define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ #define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 */ #define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 */ #define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 */ #define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 */ #define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 */ #define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 */ #define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 */ #define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 */ #define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 */ #define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 */ #define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 */ #define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 */ #define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 */ #define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 */ #define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 */ #define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 */ #define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 */ #define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 */ #define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 */ #define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 */ #define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 */ #define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 */ #define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 */ #define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 */ #define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 */ #define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 */ #define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 */ #define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 */ #define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 */ #define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 */ #define FLASH_WRProt_Sectors31to119 ((uint32_t)0x80000000) /* Write protection of setor 31 to 119*/ #define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ /* Option_Bytes_IWatchdog */ #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ /* Option_Bytes_USBFSDLEN */ #define OB_USBFSDL_EN ((uint16_t)0x0040) /* Boot Enable USBFS Download */ #define OB_USBFSDL_NoEN ((uint16_t)0x0000) /* Boot Disable USBFS Download */ /* Option_Bytes_USARTDLEN */ #define OB_USARTDL_EN ((uint16_t)0x0080) /* Boot Enable USART Download*/ #define OB_USARTDL_NoEN ((uint16_t)0x0000) /* Boot Disable USART Download */ /* FLASH_Interrupts */ #define FLASH_IT_ERROR ((uint32_t)0x00000400) #define FLASH_IT_EOP ((uint32_t)0x00001000) /* FLASH_Flags */ #define FLASH_FLAG_BSY ((uint32_t)0x00000001) #define FLASH_FLAG_EOP ((uint32_t)0x00000020) #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) #define FLASH_FLAG_OPTERR ((uint32_t)0x80000001) #define FLASH_FLAG_ENHANCE ((uint32_t)0x00000040) #define FLASH_FLAG_READY ((uint32_t)0x00004000) #define FLASH_FLAG_LPMODE ((uint32_t)0x00008000) /* FLASH_Access_CLK */ #define FLASH_CLK_HCLKDIV1 ((uint32_t)0x00000000) #define FLASH_CLK_HCLKDIV2 ((uint32_t)0x00000001) #define FLASH_CLK_HCLKDIV4 ((uint32_t)0x00000002) #define FLASH_CLK_HCLKDIV8 ((uint32_t)0x00000003) /* System_Reset_Start_Mode */ #define Start_Mode_USER ((uint32_t)0x00000000) #define Start_Mode_BOOT ((uint32_t)0x00004000) /* ch32h417_fmc.h ------------------------------------------------------------*/ #ifndef __ASSEMBLER__ /* FMC SDRAM BANK Status enumeration */ typedef enum { FMC_SDRAM_Normal = 0, FMC_SDRAM_SelfRefresh, FMC_SDRAM_PowerOff }FMC_SDRAM_BANK_Sta_TypeDef; #endif /* FMC_NORSRAM_Bank */ #define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) /* FMC_NAND_Bank */ #define FMC_Bank3_NAND ((uint32_t)0x00000000) /* FMC_SDRAM_Bank */ #define FMC_Bank5_SDRAM ((uint32_t)0x00000000) #define FMC_Bank6_SDRAM ((uint32_t)0x00000002) /* FMC_Data_Address_Bus_Multiplexing */ #define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) /* FMC_Memory_Type */ #define FMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FMC_MemoryType_NOR ((uint32_t)0x00000008) /* FMC_Data_Width */ #define FMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define FMC_MemoryDataWidth_32b ((uint32_t)0x00000020) /* FMC_NAND_Data_Width */ #define FMC_NAND_MemDataWidth_8b ((uint32_t)0x00000000) #define FMC_NAND_MemDataWidth_16b ((uint32_t)0x00000010) /* FMC_CPSIZE */ #define FMC_CPSIZE_None ((uint32_t)0x00000000) #define FMC_CPSIZE_128Bytes ((uint32_t)0x00010000) #define FMC_CPSIZE_256Bytes ((uint32_t)0x00020000) #define FMC_CPSIZE_512Bytes ((uint32_t)0x00030000) #define FMC_CPSIZE_1024Bytes ((uint32_t)0x00040000) /* FMC_BMP */ #define FMC_BMP_Mode0 ((uint32_t)0x00000000) #define FMC_BMP_Mode1 ((uint32_t)0x00010000) /* FMC_Burst_Access_Mode */ #define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) /* FMC_AsynchronousWait */ #define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) /* FMC_Wait_Signal_Polarity */ #define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) /* FMC_Wait_Timing */ #define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) /* FMC_Write_Operation */ #define FMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FMC_WriteOperation_Enable ((uint32_t)0x00001000) /* FMC_Wait_Signal */ #define FMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FMC_WaitSignal_Enable ((uint32_t)0x00002000) /* FMC_Extended_Mode */ #define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) /* FMC_Write_Burst */ #define FMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FMC_WriteBurst_Enable ((uint32_t)0x00080000) /* FMC_Access_Mode */ #define FMC_AccessMode_A ((uint32_t)0x00000000) #define FMC_AccessMode_B ((uint32_t)0x10000000) #define FMC_AccessMode_C ((uint32_t)0x20000000) #define FMC_AccessMode_D ((uint32_t)0x30000000) /* FMC_Wait_feature */ #define FMC_Waitfeature_Disable ((uint32_t)0x00000000) #define FMC_Waitfeature_Enable ((uint32_t)0x00000002) /* FMC_ECC */ #define FMC_ECC_Disable ((uint32_t)0x00000000) #define FMC_ECC_Enable ((uint32_t)0x00000040) /* FMC_ECC_Page_Size */ #define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) #define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) #define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) #define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) #define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) #define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) /* FMC_ColumnBitsNumber */ #define FMC_ColumnBitsNumber_8 ((uint32_t)0x00000000) #define FMC_ColumnBitsNumber_9 ((uint32_t)0x00000001) #define FMC_ColumnBitsNumber_10 ((uint32_t)0x00000002) #define FMC_ColumnBitsNumber_11 ((uint32_t)0x00000003) /* FMC_RowBitsNumber */ #define FMC_ROWBitsNumber_11 ((uint32_t)0x00000000) #define FMC_ROWBitsNumber_12 ((uint32_t)0x00000001) #define FMC_ROWBitsNumber_13 ((uint32_t)0x00000002) /* FMC_MemoryDataWidth */ #define FMC_MemoryDataWidth_8 ((uint32_t)0x00000000) #define FMC_MemoryDataWidth_16 ((uint32_t)0x00000001) #define FMC_MemoryDataWidth_32 ((uint32_t)0x00000002) /* FMC_InternalBankNumber */ #define FMC_InternalBankNumber_2 ((uint32_t)0x00000000) #define FMC_InternalBankNumber_4 ((uint32_t)0x00000001) /* FMC_CASLatency */ #define FMC_CASLatency_1CLk ((uint32_t)0x00000001) #define FMC_CASLatency_2CLk ((uint32_t)0x00000002) #define FMC_CASLatency_3CLk ((uint32_t)0x00000003) /* FMC_WriteProtection */ #define FMC_WriteProtection_Enable ((uint32_t)0x00000001) #define FMC_WriteProtection_Disable ((uint32_t)0x00000000) /* FMC_SDClockPeriod */ #define FMC_SDClockPeriod_Disable ((uint32_t)0x00000000) #define FMC_SDClockPeriod_2HCLK ((uint32_t)0x00000002) #define FMC_SDClockPeriod_3HCLK ((uint32_t)0x00000003) /* FMC_ReadBurst */ #define FMC_ReadBurst_Disable ((uint32_t)0x00000000) #define FMC_ReadBurst_Enable ((uint32_t)0x00000001) /* FMC_ReadPipeDelay */ #define FMC_ReadPipeDelay_none ((uint32_t)0x00000000) #define FMC_ReadPipeDelay_1HCLK ((uint32_t)0x00000001) #define FMC_ReadPipeDelay_2HCLK ((uint32_t)0x00000002) /* FMC_ENHANCE_READ_MODE */ #define FMC_ENHANCE_READ_MODE_Enable ((uint32_t)0x00000000) #define FMC_ENHANCE_READ_MODE_Disable ((uint32_t)0x00008000) /* FMC_SDRAM_SEL */ #define FMC_SDRAM_SEL_None ((uint32_t)0x00000000) #define FMC_SDRAM_SEL_Bank5 ((uint32_t)0x00000010) #define FMC_SDRAM_SEL_Bank6 ((uint32_t)0x00000008) #define FMC_SDRAM_SEL_Bank5_6 ((uint32_t)0x00000018) /* FMC_SDRAM_CMD_Mode */ #define FMC_SDRAM_CMD_Mode0 ((uint32_t)0x00000000) #define FMC_SDRAM_CMD_Mode1 ((uint32_t)0x00000001) #define FMC_SDRAM_CMD_Mode2 ((uint32_t)0x00000002) #define FMC_SDRAM_CMD_Mode3 ((uint32_t)0x00000003) #define FMC_SDRAM_CMD_Mode4 ((uint32_t)0x00000004) #define FMC_SDRAM_CMD_Mode5 ((uint32_t)0x00000005) #define FMC_SDRAM_CMD_Mode6 ((uint32_t)0x00000006) /* FMC_interrupts_definition */ #define FMC_IT_RE ((uint32_t)0x00004000)) /* FMC_flags_definition */ #define FMC_FLAG_FEMPT ((uint32_t)0x00000040) #define FMC_FLAG_BUSY ((uint32_t)0x10000020)) #define FMC_FLAG_RE ((uint32_t)0x10000001)) /* ch32h417_gpio.h ------------------------------------------------------------*/ #ifndef __ASSEMBLER__ /* Output Maximum frequency selection */ #warning "Speeds on H41x have their own register, dont concat in CFGLR" typedef enum { GPIO_Speed_10MHz = 0, GPIO_Speed_50MHz, GPIO_Speed_100MHz, GPIO_Speed_180MHz, } GPIOSpeed_TypeDef; #endif #define GPIO_CNF_IN_ANALOG 0 #define GPIO_CNF_IN_FLOATING 4 #define GPIO_CNF_IN_PUPD 8 #define GPIO_CNF_OUT_PP 1 #define GPIO_CNF_OUT_OD 5 #define GPIO_CNF_OUT_PP_AF 9 #define GPIO_CNF_OUT_OD_AF 13 /* Configuration Mode enumeration */ /* typedef enum { GPIO_Mode_AIN = 0x0, GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IPD = 0x28, GPIO_Mode_IPU = 0x48, GPIO_Mode_Out_OD = 0x14, GPIO_Mode_Out_PP = 0x10, GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_AF_PP = 0x18 }GPIOMode_TypeDef; */ #ifndef __ASSEMBLER__ /* Bit_SET and Bit_RESET enumeration */ typedef enum { Bit_RESET = 0, Bit_SET } BitAction; #endif /* GPIO_pins_define */ #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ /* GPIO_Remap_define */ #define GPIO_Remap_PD0PD1 ((uint32_t)0x00000001) /* PD0 and PD1 Alternate Function mapping */ #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00000002) /* ADC1 external trigger regular conversion mapping */ #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00000004) /* ADC1 external trigger injection conversion mapping */ #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00000008) /* ADC2 external trigger regular conversion mapping */ #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00000010) /* ADC2 external trigger injection conversion mapping */ #define GPIO_PartialRemap_UHSIF_CLK ((uint32_t)0x00160040) /* UHSIF CLK Partial Alternate Function mapping */ #define GPIO_PartialRemap1_UHSIF_CLK ((uint32_t)0x00160080) /* UHSIF CLK Partial1 Alternate Function mapping */ #define GPIO_FullRemap_UHSIF_CLK ((uint32_t)0x001600C0) /* UHSIF CLK Full Alternate Function mapping */ #define GPIO_PartialRemap_UHSIF_PORT ((uint32_t)0x00180100) /* UHSIF Port Partial Alternate Function mapping */ #define GPIO_PartialFullRemap_UHSIF_PORT ((uint32_t)0x00180300) /* UHSIF Port Full Alternate Function mapping */ #define GPIO_PartialRemap_SDMMC ((uint32_t)0x001A0400) /* SDMMC Partial Alternate Function mapping */ #define GPIO_PartialFullRemap_SDMMC ((uint32_t)0x001A0C00) /* SDMMC Full Alternate Function mapping */ #define GPIO_Remap_TIM2ITR1 ((uint32_t)0x00001000) /* TIM2 TRIG Alternate Function mapping */ #define GPIO_Remap_VIO1V8_IO_HSLV ((uint32_t)0x00200002) /* VIO(1.8V) GPIO speed configration Alternate Function mapping */ #define GPIO_Remap_VIO3V3_IO_HSLV ((uint32_t)0x00200004) /* VIO(3.3V) GPIO speed configration Alternate Function mapping */ #define GPIO_Remap_VDD3V3_IO_HSLV ((uint32_t)0x00200008) /* VDD(3.3V) GPIO speed configration Alternate Function mapping */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* SWJ Disable Function mapping */ /* GPIO_Port_Sources */ #define GPIO_PortSourceGPIOA ((uint8_t)0x00) #define GPIO_PortSourceGPIOB ((uint8_t)0x01) #define GPIO_PortSourceGPIOC ((uint8_t)0x02) #define GPIO_PortSourceGPIOD ((uint8_t)0x03) #define GPIO_PortSourceGPIOE ((uint8_t)0x04) #define GPIO_PortSourceGPIOF ((uint8_t)0x05) #define GPIO_PortSourceCMP ((uint8_t)0x06) /* GPIO_Pin_sources */ #define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource15 ((uint8_t)0x0F) /* GPIO_AF_Define */ #define GPIO_AF0 ((uint8_t)0x00) #define GPIO_AF1 ((uint8_t)0x01) #define GPIO_AF2 ((uint8_t)0x02) #define GPIO_AF3 ((uint8_t)0x03) #define GPIO_AF4 ((uint8_t)0x04) #define GPIO_AF5 ((uint8_t)0x05) #define GPIO_AF6 ((uint8_t)0x06) #define GPIO_AF7 ((uint8_t)0x07) #define GPIO_AF8 ((uint8_t)0x08) #define GPIO_AF9 ((uint8_t)0x09) #define GPIO_AF10 ((uint8_t)0x0A) #define GPIO_AF11 ((uint8_t)0x0B) #define GPIO_AF12 ((uint8_t)0x0C) #define GPIO_AF13 ((uint8_t)0x0D) #define GPIO_AF14 ((uint8_t)0x0E) #define GPIO_AF15 ((uint8_t)0x0F) /* ch32h417_i2c.h ------------------------------------------------------------*/ /* I2C_mode */ #define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) #define I2C_Mode_SMBusHost ((uint16_t)0x000A) /* I2C_duty_cycle_in_fast_mode */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ /* I2C_acknowledgement */ #define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Disable ((uint16_t)0x0000) /* I2C_transfer_direction */ #define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Receiver ((uint8_t)0x01) /* I2C_acknowledged_address */ #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) /* I2C_registers */ #define I2C_Register_CTLR1 ((uint8_t)0x00) #define I2C_Register_CTLR2 ((uint8_t)0x04) #define I2C_Register_OADDR1 ((uint8_t)0x08) #define I2C_Register_OADDR2 ((uint8_t)0x0C) #define I2C_Register_DATAR ((uint8_t)0x10) #define I2C_Register_STAR1 ((uint8_t)0x14) #define I2C_Register_STAR2 ((uint8_t)0x18) #define I2C_Register_CKCFGR ((uint8_t)0x1C) #define I2C_Register_RTR ((uint8_t)0x20) /* I2C_SMBus_alert_pin_level */ #define I2C_SMBusAlert_Low ((uint16_t)0x2000) #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) /* I2C_PEC_position */ #define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Current ((uint16_t)0xF7FF) /* I2C_NACK_position */ #define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) /* I2C_interrupts_definition */ #define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_ERR ((uint16_t)0x0100) /* I2C_interrupts_definition */ #define I2C_IT_SMBALERT ((uint32_t)0x01008000) #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) #define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) /* SR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) /* SR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_SB ((uint32_t)0x10000001) /****************I2C Master Events (Events grouped in order of communication)********************/ /******************************************************************************************************************** * @brief Start communicate * * After master use I2C_GenerateSTART() function sending the START condition,the master * has to wait for event 5(the Start condition has been correctly * released on the I2C bus ). * */ /* EVT5 */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /******************************************************************************************************************** * @brief Address Acknowledge * * When start condition correctly released on the bus(check EVT5), the * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges * his address. If an acknowledge is sent on the bus, one of the following events will be set: * * * * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * event is set. * * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * is set * * 3) In case of 10-Bit addressing mode, the master (after generating the START * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part * of the 10-bit address (LSB) . Then master should wait for event 6. * * */ /* EVT6 */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /*EVT9 */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ /******************************************************************************************************************** * @brief Communication events * * If START condition has generated and slave address * been acknowledged. then the master has to check one of the following events for * communication procedures: * * 1) Master Receiver mode: The master has to wait on the event EVT7 then use * I2C_ReceiveData() function to read the data received from the slave . * * 2) Master Transmitter mode: The master use I2C_SendData() function to send data * then to wait on event EVT8 or EVT8_2. * These two events are similar: * - EVT8 means that the data has been written in the data register and is * being shifted out. * - EVT8_2 means that the data has been physically shifted out and output * on the bus. * In most cases, using EVT8 is sufficient for the application. * Using EVT8_2 will leads to a slower communication speed but will more reliable . * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission * * * Note: * In case the user software does not guarantee that this event EVT7 is managed before * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. * * */ /* Master Receive mode */ /* EVT7 */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master Transmitter mode*/ /* EVT8 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* EVT8_2 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /******************I2C Slave Events (Events grouped in order of communication)******************/ /******************************************************************************************************************** * @brief Start Communicate events * * Wait on one of these events at the start of the communication. It means that * the I2C peripheral detected a start condition of master device generate on the bus. * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. * * * * a) In normal case (only one address managed by the slave), when the address * sent by the master matches the own address of the peripheral (configured by * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * (where XXX could be TRANSMITTER or RECEIVER). * * b) In case the address sent by the master matches the second address of the * peripheral (configured by the function I2C_OwnAddress2Config() and enabled * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * (where XXX could be TRANSMITTER or RECEIVER) are set. * * c) In case the address sent by the master is General Call (address 0x00) and * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * */ /* EVT1 */ /* a) Case of One Single Address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* b) Case of Dual address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* c) Case of General Call enabled for the slave */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ /******************************************************************************************************************** * @brief Communication events * * Wait on one of these events when EVT1 has already been checked : * * - Slave Receiver mode: * - EVT2--The device is expecting to receive a data byte . * - EVT4--The device is expecting the end of the communication: master * sends a stop condition and data transmission is stopped. * * - Slave Transmitter mode: * - EVT3--When a byte has been transmitted by the slave and the Master is expecting * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee * the EVT3 is managed before the current byte end of transfer The second one can optionally * be used. * - EVT3_2--When the master sends a NACK to tell slave device that data transmission * shall end . The slave device has to stop sending * data bytes and wait a Stop condition from bus. * * Note: * If the user software does not guarantee that the event 2 is * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED * and I2C_FLAG_BTF flag at the same time . * In this case the communication will be slower. * */ /* Slave Receiver mode*/ /* EVT2 */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* EVT4 */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave Transmitter mode*/ /* EVT3 */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /*EVT3_2 */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ /* ch32v00x_iwdg.h -----------------------------------------------------------*/ /* IWDG_WriteAccess */ #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) /* IWDG_prescaler */ #define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_256 ((uint8_t)0x06) /* IWDG_Flag */ #define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_RVU ((uint16_t)0x0002) /* ch32h417_opa.h ------------------------------------------------------------*/ #ifndef __ASSEMBLER__ /* OPA member enumeration */ typedef enum { OPA1 = 0, OPA2, OPA3, }OPA_Num_TypeDef; /* OPA PSEL enumeration */ typedef enum { CHP0 = 0, CHP1 } OPA_PSEL_TypeDef; /* OPA NSEL enumeration */ typedef enum { CHN0 = 0, CHN1, CHN_PGA_8xIN, CHN_PGA_16xIN, CHN_PGA_32xIN, CHN_PGA_64xIN, CHN_OFF = 0x7 }OPA_NSEL_TypeDef; /* OPA out channel enumeration */ typedef enum { OUT_IO_OUT0 = 0, OUT_IO_OUT1, OUT_TO_CMP /* only for OPA1 */ }OPA_Mode_TypeDef; /* OPA_FB_enumeration */ typedef enum { FB_OFF = 0, FB_ON } OPA_FB_TypeDef; /* OPA_HS_enumeration */ typedef enum { HS_OFF = 0, HS_ON } OPA_HS_TypeDef; /* OPA_PFG_DIF_enumeration */ typedef enum { DIF_OFF = 0, DIF_ON } OPA_PGADIF_TypeDef; /* OPA Init Structure definition */ typedef struct { OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ OPA_PGADIF_TypeDef PGADIF; /* Specifies the internal PGADIF of OPA */ OPA_HS_TypeDef HS; /* specifies high speed mode enable of OPA */ }OPA_InitTypeDef; /* CMP_out_channel_enumeration */ typedef enum { OUT_TO_IO = 0, OUT_TIM1_BKIN, OUT_TIM8_BKIN, OUT_TIM1_CH4, OUT_TIM2_CH4, OUT_TIM3_CH4, OUT_TIM4_CH4, OUT_TIM5_CH4, OUT_TIM8_CH4, OUT_TIM9_CH4, OUT_TIM10_CH4, OUT_TIM11_CH4, OUT_TIM12_CH4, OUT_LPTIM1_CH1, OUT_LPTIM2_CH1, OUT_FLOAT } CMP_Mode_TypeDef; /* CMP_NSEL_enumeration */ typedef enum { CMP_CHN0 = 0, CMP_CHN1, CMP_DAC2, CMP_VREF, } CMP_NSEL_TypeDef; /* CMP_PSEL_enumeration */ typedef enum { CMP_CHP_0 = 0, CMP_CHP_1, CMP_OPA1 } CMP_PSEL_TypeDef; #define CMP_CHP1 CMP_CHP_0 #define CMP_CHP2 CMP_CHP_1 /* CMP_VREF_enumeration */ typedef enum { CMP_VREF_OFF = 0, CMP_VREF_25PER_VDD, CMP_VREF_50PERT_VDD, CMP_VREF_75PERC_VDD } CMP_VREF_TypeDef; /* CMP_HYPSEL_enumeration */ typedef enum { CMP_HYPSEL_OFF = 0, CMP_HYPSEL_10mV, CMP_HYPSEL_20mV, CMP_HYPSEL_30mV, } CMP_HYPSEL_TypeDef; /* CMP Init structure definition */ typedef struct { CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ CMP_VREF_TypeDef VREF; /* Specifies the positive VREF of CMP */ CMP_HYPSEL_TypeDef HYPSEL; /* Specifies the HYEN of CMP */ } CMP_InitTypeDef; /* CMP FILT_TimeBase division definition */ #define CMP_FILT_TimeBase_Div1 ((uint8_t)0x00) #define CMP_FILT_TimeBase_Div2 ((uint8_t)0x01) #define CMP_FILT_TimeBase_Div3 ((uint8_t)0x02) #define CMP_FILT_TimeBase_Div4 ((uint8_t)0x03) #endif /* ch32h417_pwr.h ------------------------------------------------------------*/ /* PVD_detection_level */ #define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) #define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) #define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) #define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) #define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) #define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) #define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) #define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) /* PWR_detection_level */ #define PWR_VIO18Level_MODE0 ((uint32_t)0x00000000) #define PWR_VIO18Level_MODE1 ((uint32_t)0x00000400) #define PWR_VIO18Level_MODE2 ((uint32_t)0x00000800) #define PWR_VIO18Level_MODE3 ((uint32_t)0x00000C00) #define PWR_VIO18Level_MODE4 ((uint32_t)0x00001000) #define PWR_VIO18Level_MODE5 ((uint32_t)0x00001400) /* Regulator_state_is_STOP_mode */ #define PWR_Regulator_ON ((uint32_t)0x00000000) #define PWR_Regulator_LowPower ((uint32_t)0x00000001) /* STOP_mode_entry */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) /* PWR_Flag */ #define PWR_FLAG_PVDO ((uint32_t)0x00000001) /* PWR_VIO18CFGMODE */ #define PWR_VIO18CFGMODE_HW ((uint32_t)0x00000000) #define PWR_VIO18CFGMODE_SW ((uint32_t)0x00000200) /* ch32h417_rcc.h ------------------------------------------------------------*/ /* HSE_configuration */ #define RCC_HSE_OFF ((uint32_t)0x00000000) #define RCC_HSE_ON ((uint32_t)0x00010000) #define RCC_HSE_Bypass ((uint32_t)0x00040000) /* PLL_entry_clock_source */ #define RCC_PLLSource_HSI ((uint32_t)0x00000000) #define RCC_PLLSource_HSE ((uint32_t)0x00000020) #define RCC_PLLSource_USBHS ((uint32_t)0x00000080) #define RCC_PLLSource_ETH ((uint32_t)0x000000A0) #define RCC_PLLSource_USBSS ((uint32_t)0x000000C0) #define RCC_PLLSource_SERDES ((uint32_t)0x000000E0) /* PLL_multiplication_factor */ #define RCC_PLLMul_4 ((uint32_t)0x00000000) #define RCC_PLLMul_6 ((uint32_t)0x00000001) #define RCC_PLLMul_7 ((uint32_t)0x00000002) #define RCC_PLLMul_8 ((uint32_t)0x00000003) #define RCC_PLLMul_8_5 ((uint32_t)0x00000004) #define RCC_PLLMul_9 ((uint32_t)0x00000005) #define RCC_PLLMul_9_5 ((uint32_t)0x00000006) #define RCC_PLLMul_10 ((uint32_t)0x00000007) #define RCC_PLLMul_10_5 ((uint32_t)0x00000008) #define RCC_PLLMul_11 ((uint32_t)0x00000009) #define RCC_PLLMul_11_5 ((uint32_t)0x0000000A) #define RCC_PLLMul_12 ((uint32_t)0x0000000B) #define RCC_PLLMul_12_5 ((uint32_t)0x0000000C) #define RCC_PLLMul_13 ((uint32_t)0x0000000D) #define RCC_PLLMul_14 ((uint32_t)0x0000000E) #define RCC_PLLMul_15 ((uint32_t)0x0000000F) #define RCC_PLLMul_16 ((uint32_t)0x00000010) #define RCC_PLLMul_17 ((uint32_t)0x00000011) #define RCC_PLLMul_18 ((uint32_t)0x00000012) #define RCC_PLLMul_19 ((uint32_t)0x00000013) #define RCC_PLLMul_20 ((uint32_t)0x00000014) #define RCC_PLLMul_22 ((uint32_t)0x00000015) #define RCC_PLLMul_24 ((uint32_t)0x00000016) #define RCC_PLLMul_26 ((uint32_t)0x00000017) #define RCC_PLLMul_28 ((uint32_t)0x00000018) #define RCC_PLLMul_30 ((uint32_t)0x00000019) #define RCC_PLLMul_32 ((uint32_t)0x0000001A) #define RCC_PLLMul_34 ((uint32_t)0x0000001B) #define RCC_PLLMul_36 ((uint32_t)0x0000001C) #define RCC_PLLMul_38 ((uint32_t)0x0000001D) #define RCC_PLLMul_40 ((uint32_t)0x0000001E) #define RCC_PLLMul_59 ((uint32_t)0x0000001F) /* PLL_division_factor */ #define RCC_PLLDiv_1 ((uint32_t)0x00000000) #define RCC_PLLDiv_2 ((uint32_t)0x00000001) #define RCC_PLLDiv_3 ((uint32_t)0x00000002) #define RCC_PLLDiv_4 ((uint32_t)0x00000003) #define RCC_PLLDiv_5 ((uint32_t)0x00000004) #define RCC_PLLDiv_6 ((uint32_t)0x00000005) #define RCC_PLLDiv_7 ((uint32_t)0x00000006) #define RCC_PLLDiv_8 ((uint32_t)0x00000007) #define RCC_PLLDiv_9 ((uint32_t)0x00000008) #define RCC_PLLDiv_10 ((uint32_t)0x00000009) #define RCC_PLLDiv_11 ((uint32_t)0x0000000A) #define RCC_PLLDiv_12 ((uint32_t)0x0000000B) #define RCC_PLLDiv_13 ((uint32_t)0x0000000C) #define RCC_PLLDiv_14 ((uint32_t)0x0000000D) #define RCC_PLLDiv_15 ((uint32_t)0x0000000E) #define RCC_PLLDiv_16 ((uint32_t)0x0000000F) #define RCC_PLLDiv_17 ((uint32_t)0x00000010) #define RCC_PLLDiv_18 ((uint32_t)0x00000011) #define RCC_PLLDiv_19 ((uint32_t)0x00000012) #define RCC_PLLDiv_20 ((uint32_t)0x00000013) #define RCC_PLLDiv_21 ((uint32_t)0x00000014) #define RCC_PLLDiv_22 ((uint32_t)0x00000015) #define RCC_PLLDiv_23 ((uint32_t)0x00000016) #define RCC_PLLDiv_24 ((uint32_t)0x00000017) #define RCC_PLLDiv_25 ((uint32_t)0x00000018) #define RCC_PLLDiv_26 ((uint32_t)0x00000019) #define RCC_PLLDiv_27 ((uint32_t)0x0000001A) #define RCC_PLLDiv_28 ((uint32_t)0x0000001B) #define RCC_PLLDiv_29 ((uint32_t)0x0000001C) #define RCC_PLLDiv_30 ((uint32_t)0x0000001D) #define RCC_PLLDiv_31 ((uint32_t)0x0000001E) #define RCC_PLLDiv_32 ((uint32_t)0x0000001F) #define RCC_PLLDiv_33 ((uint32_t)0x00000020) #define RCC_PLLDiv_34 ((uint32_t)0x00000021) #define RCC_PLLDiv_35 ((uint32_t)0x00000022) #define RCC_PLLDiv_36 ((uint32_t)0x00000023) #define RCC_PLLDiv_37 ((uint32_t)0x00000024) #define RCC_PLLDiv_38 ((uint32_t)0x00000025) #define RCC_PLLDiv_39 ((uint32_t)0x00000026) #define RCC_PLLDiv_40 ((uint32_t)0x00000027) #define RCC_PLLDiv_41 ((uint32_t)0x00000028) #define RCC_PLLDiv_42 ((uint32_t)0x00000029) #define RCC_PLLDiv_43 ((uint32_t)0x0000002A) #define RCC_PLLDiv_44 ((uint32_t)0x0000002B) #define RCC_PLLDiv_45 ((uint32_t)0x0000002C) #define RCC_PLLDiv_46 ((uint32_t)0x0000002D) #define RCC_PLLDiv_47 ((uint32_t)0x0000002E) #define RCC_PLLDiv_48 ((uint32_t)0x0000002F) #define RCC_PLLDiv_49 ((uint32_t)0x00000030) #define RCC_PLLDiv_50 ((uint32_t)0x00000031) #define RCC_PLLDiv_51 ((uint32_t)0x00000032) #define RCC_PLLDiv_52 ((uint32_t)0x00000033) #define RCC_PLLDiv_53 ((uint32_t)0x00000034) #define RCC_PLLDiv_54 ((uint32_t)0x00000035) #define RCC_PLLDiv_55 ((uint32_t)0x00000036) #define RCC_PLLDiv_56 ((uint32_t)0x00000037) #define RCC_PLLDiv_57 ((uint32_t)0x00000038) #define RCC_PLLDiv_58 ((uint32_t)0x00000039) #define RCC_PLLDiv_59 ((uint32_t)0x0000003A) #define RCC_PLLDiv_60 ((uint32_t)0x0000003B) #define RCC_PLLDiv_61 ((uint32_t)0x0000003C) #define RCC_PLLDiv_62 ((uint32_t)0x0000003D) #define RCC_PLLDiv_63 ((uint32_t)0x0000003E) #define RCC_PLLDiv_64 ((uint32_t)0x0000003F) /* System_clock_source */ #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) /* Core1_division_factor */ #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000008) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000009) #define RCC_SYSCLK_Div8 ((uint32_t)0x0000000A) #define RCC_SYSCLK_Div16 ((uint32_t)0x0000000B) #define RCC_SYSCLK_Div64 ((uint32_t)0x0000000C) #define RCC_SYSCLK_Div128 ((uint32_t)0x0000000D) #define RCC_SYSCLK_Div256 ((uint32_t)0x0000000E) #define RCC_SYSCLK_Div512 ((uint32_t)0x0000000F) /* HCLK_division_factor */ #define RCC_SYSCLKFPRE_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLKFPRE_Div2 ((uint32_t)0x00010000) #define RCC_SYSCLKFPRE_Div4 ((uint32_t)0x00020000) /* TIM_Clock_division_factor */ #define TIM_Clock_Div2 ((uint32_t)0x00000005) #define TIM_Clock_Div4 ((uint32_t)0x00000006) #define TIM_Clock_Div8 ((uint32_t)0x00000007) /* LPTIM_Clock_division_factor */ #define LPTIM_Clock_Div2 ((uint32_t)0x00000005) #define LPTIM_Clock_Div4 ((uint32_t)0x00000006) #define LPTIM_Clock_Div8 ((uint32_t)0x00000007) /* RCC_Interrupt_source */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_ETHPLLRDY ((uint8_t)0x20) #define RCC_IT_SERDESPLLRDY ((uint8_t)0x40) #define RCC_IT_CSSF ((uint8_t)0x80) /* ADC_Clock_source= USBHS/Divx */ #define RCC_USBHS_Div5 ((uint8_t)0x00) #define RCC_USBHS_Div6 ((uint8_t)0x01) #define RCC_USBHS_Div7 ((uint8_t)0x02) #define RCC_USBHS_Div8 ((uint8_t)0x03) #define RCC_USBHS_Div9 ((uint8_t)0x04) #define RCC_USBHS_Div10 ((uint8_t)0x05) #define RCC_USBHS_Div11 ((uint8_t)0x06) #define RCC_USBHS_Div12 ((uint8_t)0x07) #define RCC_USBHS_Div13 ((uint8_t)0x08) #define RCC_USBHS_Div14 ((uint8_t)0x09) #define RCC_USBHS_Div15 ((uint8_t)0x0A) #define RCC_USBHS_Div16 ((uint8_t)0x0B) #define RCC_USBHS_Div17 ((uint8_t)0x0C) #define RCC_USBHS_Div18 ((uint8_t)0x0D) #define RCC_USBHS_Div19 ((uint8_t)0x0E) #define RCC_USBHS_Div20 ((uint8_t)0x0F) #define RCC_USBHS_Div21 ((uint8_t)0x10) #define RCC_USBHS_Div22 ((uint8_t)0x11) #define RCC_USBHS_Div23 ((uint8_t)0x12) #define RCC_USBHS_Div24 ((uint8_t)0x13) #define RCC_USBHS_Div25 ((uint8_t)0x14) #define RCC_USBHS_Div26 ((uint8_t)0x15) #define RCC_USBHS_Div27 ((uint8_t)0x16) #define RCC_USBHS_Div28 ((uint8_t)0x17) #define RCC_USBHS_Div29 ((uint8_t)0x18) #define RCC_USBHS_Div30 ((uint8_t)0x19) #define RCC_USBHS_Div31 ((uint8_t)0x1A) #define RCC_USBHS_Div32 ((uint8_t)0x1B) #define RCC_USBHS_Div33 ((uint8_t)0x1C) #define RCC_USBHS_Div34 ((uint8_t)0x1D) #define RCC_USBHS_Div35 ((uint8_t)0x1E) #define RCC_USBHS_Div36 ((uint8_t)0x1F) /* ADC_Clock_source = HCLK/(RCC_PPRE2*RCC_ADCPRE) */ #define RCC_PPRE2_DIV0 ((uint8_t)0x00) #define RCC_PPRE2_DIV2 ((uint8_t)0x04) #define RCC_PPRE2_DIV4 ((uint8_t)0x05) #define RCC_PPRE2_DIV8 ((uint8_t)0x06) #define RCC_PPRE2_DIV16 ((uint8_t)0x07) #define RCC_HCLK_ADCPRE_DIV2 ((uint8_t)0x00) #define RCC_HCLK_ADCPRE_DIV4 ((uint8_t)0x01) #define RCC_HCLK_ADCPRE_DIV6 ((uint8_t)0x02) #define RCC_HCLK_ADCPRE_DIV8 ((uint8_t)0x03) /* LSE_configuration */ #define RCC_LSE_OFF ((uint8_t)0x00) #define RCC_LSE_ON ((uint8_t)0x01) #define RCC_LSE_Bypass ((uint8_t)0x04) /* RTC_clock_source */ #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000040) #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000080) #define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x000000C0) /* HB_peripheral */ #define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) #define RCC_HBPeriph_DMA2 ((uint32_t)0x00000002) #define RCC_HBPeriph_CRC ((uint32_t)0x00000040) #define RCC_HBPeriph_FMC ((uint32_t)0x00000100) #define RCC_HBPeriph_RNG ((uint32_t)0x00000200) #define RCC_HBPeriph_SDMMC ((uint32_t)0x00000400) #define RCC_HBPeriph_USBHS ((uint32_t)0x00000800) #define RCC_HBPeriph_USBSS ((uint32_t)0x00001000) #define RCC_HBPeriph_DVP ((uint32_t)0x00002000) #define RCC_HBPeriph_ETH ((uint32_t)0x00004000) #define RCC_HBPeriph_OTG_FS ((uint32_t)0x00020000) #define RCC_HBPeriph_UHSIF ((uint32_t)0x00040000) #define RCC_HBPeriph_USBPD ((uint32_t)0x00080000) #define RCC_HBPeriph_SERDES ((uint32_t)0x00100000) #define RCC_HBPeriph_PIOC ((uint32_t)0x00400000) /* HB2_peripheral */ #define RCC_HB2Periph_AFIO ((uint32_t)0x00000001) #define RCC_HB2Periph_HSADC ((uint32_t)0x00000002) #define RCC_HB2Periph_GPIOA ((uint32_t)0x00000004) #define RCC_HB2Periph_GPIOB ((uint32_t)0x00000008) #define RCC_HB2Periph_GPIOC ((uint32_t)0x00000010) #define RCC_HB2Periph_GPIOD ((uint32_t)0x00000020) #define RCC_HB2Periph_GPIOE ((uint32_t)0x00000040) #define RCC_HB2Periph_GPIOF ((uint32_t)0x00000080) #define RCC_HB2Periph_ADC1 ((uint32_t)0x00000200) #define RCC_HB2Periph_ADC2 ((uint32_t)0x00000400) #define RCC_HB2Periph_TIM1 ((uint32_t)0x00000800) #define RCC_HB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_HB2Periph_TIM8 ((uint32_t)0x00002000) #define RCC_HB2Periph_USART1 ((uint32_t)0x00004000) #define RCC_HB2Periph_I2C4 ((uint32_t)0x00008000) #define RCC_HB2Periph_SAI ((uint32_t)0x00010000) #define RCC_HB2Periph_SDIO ((uint32_t)0x00040000) #define RCC_HB2Periph_TIM9 ((uint32_t)0x00080000) #define RCC_HB2Periph_TIM10 ((uint32_t)0x00100000) #define RCC_HB2Periph_TIM11 ((uint32_t)0x00200000) #define RCC_HB2Periph_TIM12 ((uint32_t)0x00400000) #define RCC_HB2Periph_OPCM ((uint32_t)0x00800000) #define RCC_HB2Periph_DFSDM ((uint32_t)0x02000000) #define RCC_HB2Periph_ECDC ((uint32_t)0x04000000) #define RCC_HB2Periph_GPHA ((uint32_t)0x08000000) #define RCC_HB2Periph_LTDC ((uint32_t)0x40000000) #define RCC_HB2Periph_I3C ((uint32_t)0x80000000) /* HB1_peripheral */ #define RCC_HB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_HB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_HB1Periph_TIM4 ((uint32_t)0x00000004) #define RCC_HB1Periph_TIM5 ((uint32_t)0x00000008) #define RCC_HB1Periph_TIM6 ((uint32_t)0x00000010) #define RCC_HB1Periph_TIM7 ((uint32_t)0x00000020) #define RCC_HB1Periph_USART6 ((uint32_t)0x00000040) #define RCC_HB1Periph_USART7 ((uint32_t)0x00000080) #define RCC_HB1Periph_USART8 ((uint32_t)0x00000100) #define RCC_HB1Periph_LPTIM1 ((uint32_t)0x00000200) #define RCC_HB1Periph_LPTIM2 ((uint32_t)0x00000400) #define RCC_HB1Periph_WWDG ((uint32_t)0x00000800) #define RCC_HB1Periph_QSPI1 ((uint32_t)0x00001000) #define RCC_HB1Periph_QSPI2 ((uint32_t)0x00002000) #define RCC_HB1Periph_SPI2 ((uint32_t)0x00004000) #define RCC_HB1Periph_SPI3 ((uint32_t)0x00008000) #define RCC_HB1Periph_SPI4 ((uint32_t)0x00010000) #define RCC_HB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_HB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_HB1Periph_USART4 ((uint32_t)0x00080000) #define RCC_HB1Periph_USART5 ((uint32_t)0x00100000) #define RCC_HB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_HB1Periph_I2C2 ((uint32_t)0x00400000) #define RCC_HB1Periph_CAN3 ((uint32_t)0x01000000) #define RCC_HB1Periph_CAN1 ((uint32_t)0x02000000) #define RCC_HB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_HB1Periph_BKP ((uint32_t)0x08000000) #define RCC_HB1Periph_PWR ((uint32_t)0x10000000) #define RCC_HB1Periph_DAC ((uint32_t)0x20000000) #define RCC_HB1Periph_I2C3 ((uint32_t)0x40000000) #define RCC_HB1Periph_SWPMI ((uint32_t)0x80000000) /* CSSON */ #define RCC_CSSON_DISABLE (uint8_t)0x00 #define RCC_CSSON_ENABLE (uint8_t)0x01 /* CSSHSEDIS */ #define RCC_CSSHSEDIS_DISABLE (uint8_t)0x00 #define RCC_CSSHSEDIS_ENABLE (uint8_t)0x01 /* Clock_source_to_output_on_MCO_pin */ #define RCC_MCO_NoClock ((uint8_t)0x00) #define RCC_MCO_SYSCLK ((uint8_t)0x04) #define RCC_MCO_HSI ((uint8_t)0x05) #define RCC_MCO_HSE ((uint8_t)0x06) #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) #define RCC_MCO_UTMI ((uint8_t)0x08) #define RCC_MCO_USBSSPLL_Div2 ((uint8_t)0x09) #define RCC_MCO_ETHPLL_Div8 ((uint8_t)0x0A) #define RCC_MCO_SERDESPLL_Div16 ((uint8_t)0x0B) /* RCC_Flag */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_USBHSPLLRDY ((uint8_t)0x35) #define RCC_FLAG_USBSSPLLRDY ((uint8_t)0x37) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_ETHPLLRDY ((uint8_t)0x3B) #define RCC_FLAG_SERDESPLLRDY ((uint8_t)0x3D) #define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_LKUPRSTF ((uint8_t)0x7F) /*ETH 125M clock source*/ #define RCC_ETH125MSource_PLLCLK ((uint8_t)0x00) #define RCC_ETH125MSource_USBSS ((uint8_t)0x01) #define RCC_ETH125MSource_ETH_Div4 ((uint8_t)0x02) #define RCC_ETH125MSource_SERDES_Div8 ((uint8_t)0x03) /*HSADC clock source*/ #define RCC_HSADCSource_PLLCLK ((uint8_t)0x00) #define RCC_HSADCSource_SYSCLK ((uint8_t)0x01) #define RCC_HSADCSource_USBHS ((uint8_t)0x02) #define RCC_HSADCSource_ETH ((uint8_t)0x03) /* I2S2_clock_source */ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) #define RCC_I2S2CLKSource_PLLCLK ((uint8_t)0x01) /* I2S3_clock_source */ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) #define RCC_I2S3CLKSource_PLLCLK ((uint8_t)0x01) /* RNG_clock_source */ #define RCC_RNGCLKSource_SYSCLK ((uint8_t)0x00) #define RCC_RNGCLKSource_PLLCLK ((uint8_t)0x01) /* USBFS_clock_source */ #define RCC_USBFSCLKSource_PLL ((uint8_t)0x00) #define RCC_USBFSCLKSource_USBHSPLL ((uint8_t)0x01) /* USBFS_division_factor */ #define RCC_USBFS_Div1 ((uint8_t)0x00) #define RCC_USBFS_Div2 ((uint8_t)0x01) #define RCC_USBFS_Div3 ((uint8_t)0x02) #define RCC_USBFS_Div4 ((uint8_t)0x03) #define RCC_USBFS_Div5 ((uint8_t)0x04) #define RCC_USBFS_Div6 ((uint8_t)0x05) #define RCC_USBFS_Div8 ((uint8_t)0x06) #define RCC_USBFS_Div10 ((uint8_t)0x07) #define RCC_USBFS_1Div5 ((uint8_t)0x08) #define RCC_USBFS_2Div5 ((uint8_t)0x09) #define RCC_USBFS_3Div5 ((uint8_t)0x0A) #define RCC_USBFS_4Div5 ((uint8_t)0x0B) #define RCC_USBFS_5Div5 ((uint8_t)0x0C) #define RCC_USBFS_6Div5 ((uint8_t)0x0D) #define RCC_USBFS_7Div5 ((uint8_t)0x0E) #define RCC_USBFS_9Div5 ((uint8_t)0x0F) /* LTDC_clock_source */ #define RCC_LTDCClockSource_PLL ((uint8_t)0x00) #define RCC_LTDCClockSource_SERDESPLL ((uint8_t)0x01) #define RCC_LTDCClockSource_ETHPLL ((uint8_t)0x02) #define RCC_LTDCClockSource_USBHSPLL ((uint8_t)0x03) /* LTDC_division_factor */ #define RCC_LTDCClockSource_Div1 ((uint8_t)0x00) #define RCC_LTDCClockSource_Div2 ((uint8_t)0x01) #define RCC_LTDCClockSource_Div3 ((uint8_t)0x02) #define RCC_LTDCClockSource_Div4 ((uint8_t)0x03) #define RCC_LTDCClockSource_Div5 ((uint8_t)0x04) #define RCC_LTDCClockSource_Div6 ((uint8_t)0x05) #define RCC_LTDCClockSource_Div7 ((uint8_t)0x06) #define RCC_LTDCClockSource_Div8 ((uint8_t)0x07) #define RCC_LTDCClockSource_Div9 ((uint8_t)0x08) #define RCC_LTDCClockSource_Div10 ((uint8_t)0x09) #define RCC_LTDCClockSource_Div11 ((uint8_t)0x0A) #define RCC_LTDCClockSource_Div12 ((uint8_t)0x0B) #define RCC_LTDCClockSource_Div13 ((uint8_t)0x0C) #define RCC_LTDCClockSource_Div14 ((uint8_t)0x0D) #define RCC_LTDCClockSource_Div15 ((uint8_t)0x0E) #define RCC_LTDCClockSource_Div16 ((uint8_t)0x0F) #define RCC_LTDCClockSource_Div17 ((uint8_t)0x10) #define RCC_LTDCClockSource_Div18 ((uint8_t)0x11) #define RCC_LTDCClockSource_Div19 ((uint8_t)0x12) #define RCC_LTDCClockSource_Div20 ((uint8_t)0x13) #define RCC_LTDCClockSource_Div21 ((uint8_t)0x14) #define RCC_LTDCClockSource_Div22 ((uint8_t)0x15) #define RCC_LTDCClockSource_Div23 ((uint8_t)0x16) #define RCC_LTDCClockSource_Div24 ((uint8_t)0x17) #define RCC_LTDCClockSource_Div25 ((uint8_t)0x18) #define RCC_LTDCClockSource_Div26 ((uint8_t)0x19) #define RCC_LTDCClockSource_Div27 ((uint8_t)0x1A) #define RCC_LTDCClockSource_Div28 ((uint8_t)0x1B) #define RCC_LTDCClockSource_Div29 ((uint8_t)0x1C) #define RCC_LTDCClockSource_Div30 ((uint8_t)0x1D) #define RCC_LTDCClockSource_Div31 ((uint8_t)0x1E) #define RCC_LTDCClockSource_Div32 ((uint8_t)0x1F) #define RCC_LTDCClockSource_Div33 ((uint8_t)0x20) #define RCC_LTDCClockSource_Div34 ((uint8_t)0x21) #define RCC_LTDCClockSource_Div35 ((uint8_t)0x22) #define RCC_LTDCClockSource_Div36 ((uint8_t)0x23) #define RCC_LTDCClockSource_Div37 ((uint8_t)0x24) #define RCC_LTDCClockSource_Div38 ((uint8_t)0x25) #define RCC_LTDCClockSource_Div39 ((uint8_t)0x26) #define RCC_LTDCClockSource_Div40 ((uint8_t)0x27) #define RCC_LTDCClockSource_Div41 ((uint8_t)0x28) #define RCC_LTDCClockSource_Div42 ((uint8_t)0x29) #define RCC_LTDCClockSource_Div43 ((uint8_t)0x2A) #define RCC_LTDCClockSource_Div44 ((uint8_t)0x2B) #define RCC_LTDCClockSource_Div45 ((uint8_t)0x2C) #define RCC_LTDCClockSource_Div46 ((uint8_t)0x2D) #define RCC_LTDCClockSource_Div47 ((uint8_t)0x2E) #define RCC_LTDCClockSource_Div48 ((uint8_t)0x2F) #define RCC_LTDCClockSource_Div49 ((uint8_t)0x30) #define RCC_LTDCClockSource_Div50 ((uint8_t)0x31) #define RCC_LTDCClockSource_Div51 ((uint8_t)0x32) #define RCC_LTDCClockSource_Div52 ((uint8_t)0x33) #define RCC_LTDCClockSource_Div53 ((uint8_t)0x34) #define RCC_LTDCClockSource_Div54 ((uint8_t)0x35) #define RCC_LTDCClockSource_Div55 ((uint8_t)0x36) #define RCC_LTDCClockSource_Div56 ((uint8_t)0x37) #define RCC_LTDCClockSource_Div57 ((uint8_t)0x38) #define RCC_LTDCClockSource_Div58 ((uint8_t)0x39) #define RCC_LTDCClockSource_Div59 ((uint8_t)0x3A) #define RCC_LTDCClockSource_Div60 ((uint8_t)0x3B) #define RCC_LTDCClockSource_Div61 ((uint8_t)0x3C) #define RCC_LTDCClockSource_Div62 ((uint8_t)0x3D) #define RCC_LTDCClockSource_Div63 ((uint8_t)0x3E) #define RCC_LTDCClockSource_Div64 ((uint8_t)0x3F) /* UHSIF_clock_source */ #define RCC_UHSIFClockSource_SYSCLK ((uint8_t)0x00) #define RCC_UHSIFClockSource_PLL ((uint8_t)0x01) #define RCC_UHSIFClockSource_USBHSPLL ((uint8_t)0x02) #define RCC_UHSIFClockSource_ETHPLL ((uint8_t)0x03) /* UHSIF_division_factor */ #define RCC_UHSIFClockSource_Div1 ((uint8_t)0x00) #define RCC_UHSIFClockSource_Div2 ((uint8_t)0x01) #define RCC_UHSIFClockSource_Div3 ((uint8_t)0x02) #define RCC_UHSIFClockSource_Div4 ((uint8_t)0x03) #define RCC_UHSIFClockSource_Div5 ((uint8_t)0x04) #define RCC_UHSIFClockSource_Div6 ((uint8_t)0x05) #define RCC_UHSIFClockSource_Div7 ((uint8_t)0x06) #define RCC_UHSIFClockSource_Div8 ((uint8_t)0x07) #define RCC_UHSIFClockSource_Div9 ((uint8_t)0x08) #define RCC_UHSIFClockSource_Div10 ((uint8_t)0x09) #define RCC_UHSIFClockSource_Div11 ((uint8_t)0x0A) #define RCC_UHSIFClockSource_Div12 ((uint8_t)0x0B) #define RCC_UHSIFClockSource_Div13 ((uint8_t)0x0C) #define RCC_UHSIFClockSource_Div14 ((uint8_t)0x0D) #define RCC_UHSIFClockSource_Div15 ((uint8_t)0x0E) #define RCC_UHSIFClockSource_Div16 ((uint8_t)0x0F) #define RCC_UHSIFClockSource_Div17 ((uint8_t)0x10) #define RCC_UHSIFClockSource_Div18 ((uint8_t)0x11) #define RCC_UHSIFClockSource_Div19 ((uint8_t)0x12) #define RCC_UHSIFClockSource_Div20 ((uint8_t)0x13) #define RCC_UHSIFClockSource_Div21 ((uint8_t)0x14) #define RCC_UHSIFClockSource_Div22 ((uint8_t)0x15) #define RCC_UHSIFClockSource_Div23 ((uint8_t)0x16) #define RCC_UHSIFClockSource_Div24 ((uint8_t)0x17) #define RCC_UHSIFClockSource_Div25 ((uint8_t)0x18) #define RCC_UHSIFClockSource_Div26 ((uint8_t)0x19) #define RCC_UHSIFClockSource_Div27 ((uint8_t)0x1A) #define RCC_UHSIFClockSource_Div28 ((uint8_t)0x1B) #define RCC_UHSIFClockSource_Div29 ((uint8_t)0x1C) #define RCC_UHSIFClockSource_Div30 ((uint8_t)0x1D) #define RCC_UHSIFClockSource_Div31 ((uint8_t)0x1E) #define RCC_UHSIFClockSource_Div32 ((uint8_t)0x1F) #define RCC_UHSIFClockSource_Div33 ((uint8_t)0x20) #define RCC_UHSIFClockSource_Div34 ((uint8_t)0x21) #define RCC_UHSIFClockSource_Div35 ((uint8_t)0x22) #define RCC_UHSIFClockSource_Div36 ((uint8_t)0x23) #define RCC_UHSIFClockSource_Div37 ((uint8_t)0x24) #define RCC_UHSIFClockSource_Div38 ((uint8_t)0x25) #define RCC_UHSIFClockSource_Div39 ((uint8_t)0x26) #define RCC_UHSIFClockSource_Div40 ((uint8_t)0x27) #define RCC_UHSIFClockSource_Div41 ((uint8_t)0x28) #define RCC_UHSIFClockSource_Div42 ((uint8_t)0x29) #define RCC_UHSIFClockSource_Div43 ((uint8_t)0x2A) #define RCC_UHSIFClockSource_Div44 ((uint8_t)0x2B) #define RCC_UHSIFClockSource_Div45 ((uint8_t)0x2C) #define RCC_UHSIFClockSource_Div46 ((uint8_t)0x2D) #define RCC_UHSIFClockSource_Div47 ((uint8_t)0x2E) #define RCC_UHSIFClockSource_Div48 ((uint8_t)0x2F) #define RCC_UHSIFClockSource_Div49 ((uint8_t)0x30) #define RCC_UHSIFClockSource_Div50 ((uint8_t)0x31) #define RCC_UHSIFClockSource_Div51 ((uint8_t)0x32) #define RCC_UHSIFClockSource_Div52 ((uint8_t)0x33) #define RCC_UHSIFClockSource_Div53 ((uint8_t)0x34) #define RCC_UHSIFClockSource_Div54 ((uint8_t)0x35) #define RCC_UHSIFClockSource_Div55 ((uint8_t)0x36) #define RCC_UHSIFClockSource_Div56 ((uint8_t)0x37) #define RCC_UHSIFClockSource_Div57 ((uint8_t)0x38) #define RCC_UHSIFClockSource_Div58 ((uint8_t)0x39) #define RCC_UHSIFClockSource_Div59 ((uint8_t)0x3A) #define RCC_UHSIFClockSource_Div60 ((uint8_t)0x3B) #define RCC_UHSIFClockSource_Div61 ((uint8_t)0x3C) #define RCC_UHSIFClockSource_Div62 ((uint8_t)0x3D) #define RCC_UHSIFClockSource_Div63 ((uint8_t)0x3E) #define RCC_UHSIFClockSource_Div64 ((uint8_t)0x3F) /* USBHSPLL_clock_source */ #define RCC_USBHSPLLSource_HSE ((uint8_t)0x00) #define RCC_USBHSPLLSource_HSI ((uint8_t)0x01) #define RCC_USBHSPLLSource_20METH ((uint8_t)0x02) #define RCC_USBHSPLLSource_PLL_CLK_DIV ((uint8_t)0x03) /* USBHS PLL Refer clock */ #define RCC_USBHSPLLRefer_25M ((uint8_t)0x00) #define RCC_USBHSPLLRefer_20M ((uint8_t)0x01) #define RCC_USBHSPLLRefer_24M ((uint8_t)0x02) #define RCC_USBHSPLLRefer_32M ((uint8_t)0x03) /* USBSS PLL Refer clock */ #define RCC_USBSSPLLRefer_20M ((uint8_t)0x00) #define RCC_USBSSPLLRefer_24M ((uint8_t)0x10) #define RCC_USBSSPLLRefer_25M ((uint8_t)0x20) #define RCC_USBSSPLLRefer_30M ((uint8_t)0x30) #define RCC_USBSSPLLRefer_32M ((uint8_t)0x40) #define RCC_USBSSPLLRefer_40M ((uint8_t)0x50) #define RCC_USBSSPLLRefer_60M ((uint8_t)0x60) #define RCC_USBSSPLLRefer_80M ((uint8_t)0x70) /* USBHS PLL Source clock Division*/ #define RCC_USBHSPLL_IN_Div1 ((uint32_t)0x0000) #define RCC_USBHSPLL_IN_Div2 ((uint32_t)0x0100) #define RCC_USBHSPLL_IN_Div3 ((uint32_t)0x0200) #define RCC_USBHSPLL_IN_Div4 ((uint32_t)0x0300) #define RCC_USBHSPLL_IN_Div5 ((uint32_t)0x0400) #define RCC_USBHSPLL_IN_Div6 ((uint32_t)0x0500) #define RCC_USBHSPLL_IN_Div7 ((uint32_t)0x0600) #define RCC_USBHSPLL_IN_Div8 ((uint32_t)0x0700) #define RCC_USBHSPLL_IN_Div9 ((uint32_t)0x0800) #define RCC_USBHSPLL_IN_Div10 ((uint32_t)0x0900) #define RCC_USBHSPLL_IN_Div11 ((uint32_t)0x0A00) #define RCC_USBHSPLL_IN_Div12 ((uint32_t)0x0B00) #define RCC_USBHSPLL_IN_Div13 ((uint32_t)0x0C00) #define RCC_USBHSPLL_IN_Div14 ((uint32_t)0x0D00) #define RCC_USBHSPLL_IN_Div15 ((uint32_t)0x0E00) #define RCC_USBHSPLL_IN_Div16 ((uint32_t)0x0F00) #define RCC_USBHSPLL_IN_Div17 ((uint32_t)0x1000) #define RCC_USBHSPLL_IN_Div18 ((uint32_t)0x1100) #define RCC_USBHSPLL_IN_Div19 ((uint32_t)0x1200) #define RCC_USBHSPLL_IN_Div20 ((uint32_t)0x1300) #define RCC_USBHSPLL_IN_Div21 ((uint32_t)0x1400) #define RCC_USBHSPLL_IN_Div22 ((uint32_t)0x1500) #define RCC_USBHSPLL_IN_Div23 ((uint32_t)0x1600) #define RCC_USBHSPLL_IN_Div24 ((uint32_t)0x1700) #define RCC_USBHSPLL_IN_Div25 ((uint32_t)0x1800) #define RCC_USBHSPLL_IN_Div26 ((uint32_t)0x1900) #define RCC_USBHSPLL_IN_Div27 ((uint32_t)0x1A00) #define RCC_USBHSPLL_IN_Div28 ((uint32_t)0x1B00) #define RCC_USBHSPLL_IN_Div29 ((uint32_t)0x1C00) #define RCC_USBHSPLL_IN_Div30 ((uint32_t)0x1D00) #define RCC_USBHSPLL_IN_Div31 ((uint32_t)0x1E00) #define RCC_USBHSPLL_IN_Div32 ((uint32_t)0x1F00) /* SERDES PLL clock Mul*/ #define RCC_SERDESPLLMul_25 ((uint32_t)0x0000) #define RCC_SERDESPLLMul_28 ((uint32_t)0x0001) #define RCC_SERDESPLLMul_30 ((uint32_t)0x0002) #define RCC_SERDESPLLMul_32 ((uint32_t)0x0003) #define RCC_SERDESPLLMul_35 ((uint32_t)0x0004) #define RCC_SERDESPLLMul_38 ((uint32_t)0x0005) #define RCC_SERDESPLLMul_40 ((uint32_t)0x0006) #define RCC_SERDESPLLMul_45 ((uint32_t)0x0007) #define RCC_SERDESPLLMul_50 ((uint32_t)0x0008) #define RCC_SERDESPLLMul_56 ((uint32_t)0x0009) #define RCC_SERDESPLLMul_60 ((uint32_t)0x000A) #define RCC_SERDESPLLMul_64 ((uint32_t)0x000B) #define RCC_SERDESPLLMul_70 ((uint32_t)0x000C) #define RCC_SERDESPLLMul_76 ((uint32_t)0x000D) #define RCC_SERDESPLLMul_80 ((uint32_t)0x000E) #define RCC_SERDESPLLMul_90 ((uint32_t)0x000F) /* ADC_clock_H_Level_Duty_Cycle */ #define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) #define RCC_ADC_H_Level_Mode1 ((uint32_t)0x40000000) /* ADC_clock_source */ #define RCC_ADCCLKSource_HCLK ((uint8_t)0x00) #define RCC_ADCCLKSource_USBHSPLL ((uint8_t)0x01) /* SYSPLL_clock_source */ #define RCC_SYSPLLClockSource_PLL ((uint8_t)0x00) #define RCC_SYSPLLClockSource_USBHSPLL ((uint8_t)0x04) #define RCC_SYSPLLClockSource_ETHPLL ((uint8_t)0x05) #define RCC_SYSPLLClockSource_SERDESPLL ((uint8_t)0x06) #define RCC_SYSPLLClockSource_USBSSPLL ((uint8_t)0x07) #define RCC_RTCOutputSource_CalibClock ((uint16_t)0x0008) #define RCC_RTCOutputSource_Alarm ((uint16_t)0x0010) #define RCC_RTCOutputSource_Second ((uint16_t)0x0030) #define RCC_RTCOutputSource_None ((uint16_t)0x0000) /* ch32v00x_rng.h ------------------------------------------------------------*/ /* RNG_flags_definition*/ #define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ #define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ #define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ /* RNG_interrupts_definition */ #define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ #define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ /* ch32h417_rtc.h ------------------------------------------------------------*/ /* RTC_interrupts_define */ #define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ #define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ #define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ /* RTC_interrupts_flags */ #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ #define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ #define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ #define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ #define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ /* ch32h417_sdio.h -----------------------------------------------------------*/ /* SDIO_Clock_Edge */ #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) /* SDIO_Clock_Bypass */ #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) /* SDIO_Clock_Power_Save */ #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) /* SDIO_Bus_Wide */ #define SDIO_BusWide_1b ((uint32_t)0x00000000) #define SDIO_BusWide_4b ((uint32_t)0x00000800) #define SDIO_BusWide_8b ((uint32_t)0x00001000) /* SDIO_Hardware_Flow_Control */ #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) /* SDIO_Power_State */ #define SDIO_PowerState_OFF ((uint32_t)0x00000000) #define SDIO_PowerState_ON ((uint32_t)0x00000003) /* SDIO_Interrupt_sources */ #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) #define SDIO_IT_RXOVERR ((uint32_t)0x00000020) #define SDIO_IT_CMDREND ((uint32_t)0x00000040) #define SDIO_IT_CMDSENT ((uint32_t)0x00000080) #define SDIO_IT_DATAEND ((uint32_t)0x00000100) #define SDIO_IT_STBITERR ((uint32_t)0x00000200) #define SDIO_IT_DBCKEND ((uint32_t)0x00000400) #define SDIO_IT_CMDACT ((uint32_t)0x00000800) #define SDIO_IT_TXACT ((uint32_t)0x00001000) #define SDIO_IT_RXACT ((uint32_t)0x00002000) #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) #define SDIO_IT_TXDAVL ((uint32_t)0x00100000) #define SDIO_IT_RXDAVL ((uint32_t)0x00200000) #define SDIO_IT_SDIOIT ((uint32_t)0x00400000) #define SDIO_IT_CEATAEND ((uint32_t)0x00800000) /* SDIO_Response_Type */ #define SDIO_Response_No ((uint32_t)0x00000000) #define SDIO_Response_Short ((uint32_t)0x00000040) #define SDIO_Response_Long ((uint32_t)0x000000C0) /* SDIO_Wait_Interrupt_State */ #define SDIO_Wait_No ((uint32_t)0x00000000) #define SDIO_Wait_IT ((uint32_t)0x00000100) #define SDIO_Wait_Pend ((uint32_t)0x00000200) /* SDIO_CPSM_State */ #define SDIO_CPSM_Disable ((uint32_t)0x00000000) #define SDIO_CPSM_Enable ((uint32_t)0x00000400) /* SDIO_Response_Registers */ #define SDIO_RESP1 ((uint32_t)0x00000000) #define SDIO_RESP2 ((uint32_t)0x00000004) #define SDIO_RESP3 ((uint32_t)0x00000008) #define SDIO_RESP4 ((uint32_t)0x0000000C) /* SDIO_Data_Block_Size */ #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) /* SDIO_Transfer_Direction */ #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) /* SDIO_Transfer_Type */ #define SDIO_TransferMode_Block ((uint32_t)0x00000000) #define SDIO_TransferMode_Stream ((uint32_t)0x00000004) /* SDIO_DPSM_State */ #define SDIO_DPSM_Disable ((uint32_t)0x00000000) #define SDIO_DPSM_Enable ((uint32_t)0x00000001) /* SDIO_Flags */ #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) #define SDIO_FLAG_TXACT ((uint32_t)0x00001000) #define SDIO_FLAG_RXACT ((uint32_t)0x00002000) #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) /* SDIO_Read_Wait_Mode */ #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) #define SDIO_DataControl_DTEN ((uint32_t)0x00000001) #define SDIO_DataControl_DTDIR ((uint32_t)0x00000002) #define SDIO_DataControl_DTMODE ((uint32_t)0x00000004) #define SDIO_DataControl_DMAEN ((uint32_t)0x00000008) #define SDIO_DataControl_DBLOCKSIZE ((uint32_t)0x000000F0) #define SDIO_DataControl_RWSTART ((uint32_t)0x00000100) #define SDIO_DataControl_RWSTOP ((uint32_t)0x00000200) #define SDIO_DataControl_RWMOD ((uint32_t)0x00000400) #define SDIO_DataControl_SDIOEN ((uint32_t)0x00000800) /* ch32h417_spi.h ------------------------------------------------------------*/ /* SPI_data_direction */ #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) /* SPI_mode */ #define SPI_Mode_Master ((uint16_t)0x0104) #define SPI_Mode_Slave ((uint16_t)0x0000) /* SPI_data_size */ #define SPI_DataSize_16b ((uint16_t)0x0800) #define SPI_DataSize_8b ((uint16_t)0x0000) /* SPI_Clock_Polarity */ #define SPI_CPOL_Low ((uint16_t)0x0000) #define SPI_CPOL_High ((uint16_t)0x0002) /* SPI_Clock_Phase */ #define SPI_CPHA_1Edge ((uint16_t)0x0000) #define SPI_CPHA_2Edge ((uint16_t)0x0001) /* SPI_Slave_Select_management */ #define SPI_NSS_Soft ((uint16_t)0x0200) #define SPI_NSS_Hard ((uint16_t)0x0000) /* SPI_BaudRate_Prescaler */ #define SPI_BaudRatePrescaler_Mode0 ((uint16_t)0x0000) #define SPI_BaudRatePrescaler_Mode1 ((uint16_t)0x0008) #define SPI_BaudRatePrescaler_Mode2 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_Mode3 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_Mode4 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_Mode5 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_Mode6 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_Mode7 ((uint16_t)0x0038) /* SPI_MSB_LSB_transmission */ #define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_LSB ((uint16_t)0x0080) /* I2S_Mode */ #define I2S_Mode_SlaveTx ((uint16_t)0x0000) #define I2S_Mode_SlaveRx ((uint16_t)0x0100) #define I2S_Mode_MasterTx ((uint16_t)0x0200) #define I2S_Mode_MasterRx ((uint16_t)0x0300) /* I2S_Standard */ #define I2S_Standard_Phillips ((uint16_t)0x0000) #define I2S_Standard_MSB ((uint16_t)0x0010) #define I2S_Standard_LSB ((uint16_t)0x0020) #define I2S_Standard_PCMShort ((uint16_t)0x0030) #define I2S_Standard_PCMLong ((uint16_t)0x00B0) /* I2S_Data_Format */ #define I2S_DataFormat_16b ((uint16_t)0x0000) #define I2S_DataFormat_16bextended ((uint16_t)0x0001) #define I2S_DataFormat_24b ((uint16_t)0x0003) #define I2S_DataFormat_32b ((uint16_t)0x0005) /* I2S_MCLK_Output */ #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) /* I2S_Audio_Frequency */ #define I2S_AudioFreq_192k ((uint32_t)192000) #define I2S_AudioFreq_96k ((uint32_t)96000) #define I2S_AudioFreq_48k ((uint32_t)48000) #define I2S_AudioFreq_44k ((uint32_t)44100) #define I2S_AudioFreq_32k ((uint32_t)32000) #define I2S_AudioFreq_22k ((uint32_t)22050) #define I2S_AudioFreq_16k ((uint32_t)16000) #define I2S_AudioFreq_11k ((uint32_t)11025) #define I2S_AudioFreq_8k ((uint32_t)8000) #define I2S_AudioFreq_Default ((uint32_t)2) /* I2S_Clock_Polarity */ #define I2S_CPOL_Low ((uint16_t)0x0000) #define I2S_CPOL_High ((uint16_t)0x0008) /* SPI_I2S_DMA_transfer_requests */ #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) /* SPI_NSS_internal_software_management */ #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) /* SPI_CRC_Transmit_Receive */ #define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_CRC_Rx ((uint8_t)0x01) /* SPI_direction_transmit_receive */ #define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_Direction_Tx ((uint16_t)0x4000) /* SPI_I2S_interrupts_definition */ #define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_I2S_IT_RXNE ((uint8_t)0x60) #define SPI_I2S_IT_ERR ((uint8_t)0x50) #define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_IT_MODF ((uint8_t)0x55) #define SPI_IT_CRCERR ((uint8_t)0x54) #define I2S_IT_UDR ((uint8_t)0x53) /* SPI_I2S_flags_definition */ #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) #define I2S_FLAG_UDR ((uint16_t)0x0008) #define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_FLAG_MODF ((uint16_t)0x0020) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) /* SPI_HIGH_SPEED_MODE_definition */ #define SPI_HIGH_SPEED_MODE1 ((uint16_t)0x0001) #define SPI_HIGH_SPEED_MODE2 ((uint16_t)0x0005) /* ch32h417_tim.h ------------------------------------------------------------*/ /* TIM_Output_Compare_and_PWM_modes */ #define TIM_OCMode_Timing ((uint16_t)0x0000) #define TIM_OCMode_Active ((uint16_t)0x0010) #define TIM_OCMode_Inactive ((uint16_t)0x0020) #define TIM_OCMode_Toggle ((uint16_t)0x0030) #define TIM_OCMode_PWM1 ((uint16_t)0x0060) #define TIM_OCMode_PWM2 ((uint16_t)0x0070) /* TIM_One_Pulse_Mode */ #define TIM_OPMode_Single ((uint16_t)0x0008) #define TIM_OPMode_Repetitive ((uint16_t)0x0000) /* TIM_Channel */ #define TIM_Channel_1 ((uint16_t)0x0000) #define TIM_Channel_2 ((uint16_t)0x0004) #define TIM_Channel_3 ((uint16_t)0x0008) #define TIM_Channel_4 ((uint16_t)0x000C) /* TIM_Clock_Division_CKD */ #define TIM_CKD_DIV1 ((uint16_t)0x0000) #define TIM_CKD_DIV2 ((uint16_t)0x0100) #define TIM_CKD_DIV4 ((uint16_t)0x0200) /* TIM_Counter_Mode */ #define TIM_CounterMode_Up ((uint16_t)0x0000) #define TIM_CounterMode_Down ((uint16_t)0x0010) #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) /* TIM_Output_Compare_Polarity */ #define TIM_OCPolarity_High ((uint16_t)0x0000) #define TIM_OCPolarity_Low ((uint16_t)0x0002) /* TIM_Output_Compare_N_Polarity */ #define TIM_OCNPolarity_High ((uint16_t)0x0000) #define TIM_OCNPolarity_Low ((uint16_t)0x0008) /* TIM_Output_Compare_state */ #define TIM_OutputState_Disable ((uint16_t)0x0000) #define TIM_OutputState_Enable ((uint16_t)0x0001) /* TIM_Output_Compare_N_state */ #define TIM_OutputNState_Disable ((uint16_t)0x0000) #define TIM_OutputNState_Enable ((uint16_t)0x0004) /* TIM_Capture_Compare_state */ #define TIM_CCx_Enable ((uint16_t)0x0001) #define TIM_CCx_Disable ((uint16_t)0x0000) /* TIM_Capture_Compare_N_state */ #define TIM_CCxN_Enable ((uint16_t)0x0004) #define TIM_CCxN_Disable ((uint16_t)0x0000) /* Break_Input_enable_disable */ #define TIM_Break_Enable ((uint16_t)0x1000) #define TIM_Break_Disable ((uint16_t)0x0000) /* Break_Polarity */ #define TIM_BreakPolarity_Low ((uint16_t)0x0000) #define TIM_BreakPolarity_High ((uint16_t)0x2000) /* TIM_AOE_Bit_Set_Reset */ #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) /* Lock_level */ #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) #define TIM_LOCKLevel_1 ((uint16_t)0x0100) #define TIM_LOCKLevel_2 ((uint16_t)0x0200) #define TIM_LOCKLevel_3 ((uint16_t)0x0300) /* OSSI_Off_State_Selection_for_Idle_mode_state */ #define TIM_OSSIState_Enable ((uint16_t)0x0400) #define TIM_OSSIState_Disable ((uint16_t)0x0000) /* OSSR_Off_State_Selection_for_Run_mode_state */ #define TIM_OSSRState_Enable ((uint16_t)0x0800) #define TIM_OSSRState_Disable ((uint16_t)0x0000) /* TIM_Output_Compare_Idle_State */ #define TIM_OCIdleState_Set ((uint16_t)0x0100) #define TIM_OCIdleState_Reset ((uint16_t)0x0000) /* TIM_Output_Compare_N_Idle_State */ #define TIM_OCNIdleState_Set ((uint16_t)0x0200) #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) /* TIM_Input_Capture_Polarity */ #define TIM_ICPolarity_Rising ((uint16_t)0x0000) #define TIM_ICPolarity_Falling ((uint16_t)0x0002) #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) /* TIM_Input_Capture_Selection */ #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */ #define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ /* TIM_Input_Capture_Prescaler */ #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ /* TIM_interrupt_sources */ #define TIM_IT_Update ((uint16_t)0x0001) #define TIM_IT_CC1 ((uint16_t)0x0002) #define TIM_IT_CC2 ((uint16_t)0x0004) #define TIM_IT_CC3 ((uint16_t)0x0008) #define TIM_IT_CC4 ((uint16_t)0x0010) #define TIM_IT_COM ((uint16_t)0x0020) #define TIM_IT_Trigger ((uint16_t)0x0040) #define TIM_IT_Break ((uint16_t)0x0080) /* TIM_DMA_Base_address */ #define TIM_DMABase_CR1 ((uint16_t)0x0000) #define TIM_DMABase_CR2 ((uint16_t)0x0001) #define TIM_DMABase_SMCR ((uint16_t)0x0002) #define TIM_DMABase_DIER ((uint16_t)0x0003) #define TIM_DMABase_SR ((uint16_t)0x0004) #define TIM_DMABase_EGR ((uint16_t)0x0005) #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) #define TIM_DMABase_CCER ((uint16_t)0x0008) #define TIM_DMABase_CNT ((uint16_t)0x0009) #define TIM_DMABase_PSC ((uint16_t)0x000A) #define TIM_DMABase_ARR ((uint16_t)0x000B) #define TIM_DMABase_RCR ((uint16_t)0x000C) #define TIM_DMABase_CCR1 ((uint16_t)0x000D) #define TIM_DMABase_CCR2 ((uint16_t)0x000E) #define TIM_DMABase_CCR3 ((uint16_t)0x000F) #define TIM_DMABase_CCR4 ((uint16_t)0x0010) #define TIM_DMABase_BDTR ((uint16_t)0x0011) #define TIM_DMABase_DCR ((uint16_t)0x0012) /* TIM_DMA_Burst_Length */ #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) /* TIM_DMA_sources */ #define TIM_DMA_Update ((uint16_t)0x0100) #define TIM_DMA_CC1 ((uint16_t)0x0200) #define TIM_DMA_CC2 ((uint16_t)0x0400) #define TIM_DMA_CC3 ((uint16_t)0x0800) #define TIM_DMA_CC4 ((uint16_t)0x1000) #define TIM_DMA_COM ((uint16_t)0x2000) #define TIM_DMA_Trigger ((uint16_t)0x4000) /* TIM_External_Trigger_Prescaler */ #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) /* TIM_Internal_Trigger_Selection */ #define TIM_TS_ITR0 ((uint16_t)0x0000) #define TIM_TS_ITR1 ((uint16_t)0x0010) #define TIM_TS_ITR2 ((uint16_t)0x0020) #define TIM_TS_ITR3 ((uint16_t)0x0030) #define TIM_TS_TI1F_ED ((uint16_t)0x0040) #define TIM_TS_TI1FP1 ((uint16_t)0x0050) #define TIM_TS_TI2FP2 ((uint16_t)0x0060) #define TIM_TS_ETRF ((uint16_t)0x0070) /* TIM_TIx_External_Clock_Source */ #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) /* TIM_External_Trigger_Polarity */ #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) /* TIM_Prescaler_Reload_Mode */ #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) /* TIM_Forced_Action */ #define TIM_ForcedAction_Active ((uint16_t)0x0050) #define TIM_ForcedAction_InActive ((uint16_t)0x0040) /* TIM_Encoder_Mode */ #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) /* TIM_Event_Source */ #define TIM_EventSource_Update ((uint16_t)0x0001) #define TIM_EventSource_CC1 ((uint16_t)0x0002) #define TIM_EventSource_CC2 ((uint16_t)0x0004) #define TIM_EventSource_CC3 ((uint16_t)0x0008) #define TIM_EventSource_CC4 ((uint16_t)0x0010) #define TIM_EventSource_COM ((uint16_t)0x0020) #define TIM_EventSource_Trigger ((uint16_t)0x0040) #define TIM_EventSource_Break ((uint16_t)0x0080) /* TIM_Update_Source */ #define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller. */ #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ /* TIM_Output_Compare_Preload_State */ #define TIM_OCPreload_Enable ((uint16_t)0x0008) #define TIM_OCPreload_Disable ((uint16_t)0x0000) /* TIM_Output_Compare_Fast_State */ #define TIM_OCFast_Enable ((uint16_t)0x0004) #define TIM_OCFast_Disable ((uint16_t)0x0000) /* TIM_Output_Compare_Clear_State */ #define TIM_OCClear_Enable ((uint16_t)0x0080) #define TIM_OCClear_Disable ((uint16_t)0x0000) /* TIM_Trigger_Output_Source */ #define TIM_TRGOSource_Reset ((uint16_t)0x0000) #define TIM_TRGOSource_Enable ((uint16_t)0x0010) #define TIM_TRGOSource_Update ((uint16_t)0x0020) #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) /* TIM_Slave_Mode */ #define TIM_SlaveMode_Reset ((uint16_t)0x0004) #define TIM_SlaveMode_Gated ((uint16_t)0x0005) #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) #define TIM_SlaveMode_External1 ((uint16_t)0x0007) /* TIM_Master_Slave_Mode */ #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) /* TIM_Flags */ #define TIM_FLAG_Update ((uint16_t)0x0001) #define TIM_FLAG_CC1 ((uint16_t)0x0002) #define TIM_FLAG_CC2 ((uint16_t)0x0004) #define TIM_FLAG_CC3 ((uint16_t)0x0008) #define TIM_FLAG_CC4 ((uint16_t)0x0010) #define TIM_FLAG_COM ((uint16_t)0x0020) #define TIM_FLAG_Trigger ((uint16_t)0x0040) #define TIM_FLAG_Break ((uint16_t)0x0080) #define TIM_FLAG_CC1OF ((uint16_t)0x0200) #define TIM_FLAG_CC2OF ((uint16_t)0x0400) #define TIM_FLAG_CC3OF ((uint16_t)0x0800) #define TIM_FLAG_CC4OF ((uint16_t)0x1000) /* TIM_DT_MODE */ #define TIM_DT_MODE_Disable ((uint16_t)0x0000) #define TIM_DT_MODE_Rising ((uint16_t)0x0040) #define TIM_DT_MODE_Falling ((uint16_t)0x0080) #define TIM_DT_MODE_BothEdge ((uint16_t)0x00C0) /* TIM_Brake Select */ #define TIM_BKIN1 ((uint16_t)0x0000) #define TIM_BKIN2 ((uint16_t)0x0001) #define TIM_BKIN1_2 ((uint16_t)0x0002) #define TIM_DFSDM_BK0 ((uint16_t)0x0004) #define TIM_DFSDM_BK1 ((uint16_t)0x0005) /* TIM_IC_OverflowMode */ #define TIM_IC_OV_Mode0 ((uint16_t)0x0000) #define TIM_IC_OV_Mode1 ((uint16_t)0x4000) /* TIM_Legacy */ #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers /* ch32h417_usart.h ----------------------------------------------------------*/ /* USART_Word_Length */ #define USART_WordLength_5b ((uint16_t)0xC000) #define USART_WordLength_6b ((uint16_t)0x8000) #define USART_WordLength_7b ((uint16_t)0x4000) #define USART_WordLength_8b ((uint16_t)0x0000) #define USART_WordLength_9b ((uint16_t)0x1000) /* USART_Stop_Bits */ #define USART_StopBits_1 ((uint16_t)0x0000) #define USART_StopBits_0_5 ((uint16_t)0x1000) #define USART_StopBits_2 ((uint16_t)0x2000) #define USART_StopBits_1_5 ((uint16_t)0x3000) /* USART_Parity */ #define USART_Parity_No ((uint16_t)0x0000) #define USART_Parity_Even ((uint16_t)0x0400) #define USART_Parity_Odd ((uint16_t)0x0600) /* USART_Mode */ #define USART_Mode_Rx ((uint16_t)0x0004) #define USART_Mode_Tx ((uint16_t)0x0008) /* USART_Hardware_Flow_Control */ #define USART_HardwareFlowControl_None ((uint16_t)0x0000) #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) /* USART_Clock */ #define USART_Clock_Disable ((uint16_t)0x0000) #define USART_Clock_Enable ((uint16_t)0x0800) /* USART_Clock_Polarity */ #define USART_CPOL_Low ((uint16_t)0x0000) #define USART_CPOL_High ((uint16_t)0x0400) /* USART_Clock_Phase */ #define USART_CPHA_1Edge ((uint16_t)0x0000) #define USART_CPHA_2Edge ((uint16_t)0x0200) /* USART_Last_Bit */ #define USART_LastBit_Disable ((uint16_t)0x0000) #define USART_LastBit_Enable ((uint16_t)0x0100) /* USART_Interrupt_definition */ #define USART_IT_PE ((uint16_t)0x0028) #define USART_IT_TXE ((uint16_t)0x0727) #define USART_IT_TC ((uint16_t)0x0626) #define USART_IT_RXNE ((uint16_t)0x0525) #define USART_IT_ORE_RX ((uint16_t)0x0325) #define USART_IT_IDLE ((uint16_t)0x0424) #define USART_IT_LBD ((uint16_t)0x0846) #define USART_IT_CTS ((uint16_t)0x096A) #define USART_IT_ERR ((uint16_t)0x0060) #define USART_IT_ORE_ER ((uint16_t)0x0360) #define USART_IT_NE ((uint16_t)0x0260) #define USART_IT_FE ((uint16_t)0x0160) #define USART_IT_MS_ER ((uint16_t)0x0B81) #define USART_IT_ORE USART_IT_ORE_ER /* USART_DMA_Requests */ #define USART_DMAReq_Tx ((uint16_t)0x0080) #define USART_DMAReq_Rx ((uint16_t)0x0040) /* USART_WakeUp_methods */ #define USART_WakeUp_IdleLine ((uint16_t)0x0000) #define USART_WakeUp_AddressMark ((uint16_t)0x0800) /* USART_LIN_Break_Detection_Length */ #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) /* USART_IrDA_Low_Power */ #define USART_IrDAMode_LowPower ((uint16_t)0x0004) #define USART_IrDAMode_Normal ((uint16_t)0x0000) /* USART_Flags */ #define USART_FLAG_LPWKUP ((uint16_t)0x8000) #define USART_FLAG_MS_ERR ((uint16_t)0x0800) #define USART_FLAG_RX_BUSY ((uint16_t)0x0400) #define USART_FLAG_CTS ((uint16_t)0x0200) #define USART_FLAG_LBD ((uint16_t)0x0100) #define USART_FLAG_TXE ((uint16_t)0x0080) #define USART_FLAG_TC ((uint16_t)0x0040) #define USART_FLAG_RXNE ((uint16_t)0x0020) #define USART_FLAG_IDLE ((uint16_t)0x0010) #define USART_FLAG_ORE ((uint16_t)0x0008) #define USART_FLAG_NE ((uint16_t)0x0004) #define USART_FLAG_FE ((uint16_t)0x0002) #define USART_FLAG_PE ((uint16_t)0x0001) /* USART_LPWKUP_DLY */ #define USART_LPWKUP_DLY_0_CLKCycle ((uint16_t)0x0000) #define USART_LPWKUP_DLY_1_CLKCycle ((uint16_t)0x2000) #define USART_LPWKUP_DLY_2_CLKCycle ((uint16_t)0x4000) #define USART_LPWKUP_DLY_3_CLKCycle ((uint16_t)0x6000) #define USART_LPWKUP_DLY_4_CLKCycle ((uint16_t)0x8000) #define USART_LPWKUP_DLY_5_CLKCycle ((uint16_t)0xA000) #define USART_LPWKUP_DLY_6_CLKCycle ((uint16_t)0xC000) #define USART_LPWKUP_DLY_7_CLKCycle ((uint16_t)0xE000) /* USART_LPWKUP_CLK_SRC */ #define USART_LPWKUP_CLK_SRC_LSI ((uint16_t)0x0000) #define USART_LPWKUP_CLK_SRC_LSE ((uint16_t)0x1000) /* USART_MARKorSPACE_Mode */ #define USART_VerifyMode_NoMARKorSPACE ((uint16_t)0x0000) #define USART_VerifyMode_MARK ((uint16_t)0x0008) #define USART_VerifyMode_SPACE ((uint16_t)0x000C) /* ch32h417_usb.h ------------------------------------------------------------*/ /*******************************************************************************/ /* USB Communication Related Macro Definition */ /* USB Endpoint0 Size */ #ifndef DEFAULT_ENDP0_SIZE #define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 #endif #ifndef MAX_PACKET_SIZE #define MAX_PACKET_SIZE 64 // maximum packet size #endif /* USB PID */ #ifndef USB_PID_SETUP #define USB_PID_NULL 0x00 #define USB_PID_SOF 0x05 #define USB_PID_SETUP 0x0D #define USB_PID_IN 0x09 #define USB_PID_OUT 0x01 #define USB_PID_NYET 0x06 #define USB_PID_ACK 0x02 #define USB_PID_NAK 0x0A #define USB_PID_STALL 0x0E #define USB_PID_DATA0 0x03 #define USB_PID_DATA1 0x0B #define USB_PID_DATA2 0x07 #define USB_PID_MDATA 0x0F #define USB_PID_PRE 0x0C #endif /* USB standard device request code */ #ifndef USB_GET_DESCRIPTOR #define USB_GET_STATUS 0x00 #define USB_CLEAR_FEATURE 0x01 #define USB_SET_ENDPOINT 0x02 #define USB_SET_FEATURE 0x03 #define USB_SET_ADDRESS 0x05 #define USB_GET_DESCRIPTOR 0x06 #define USB_SET_DESCRIPTOR 0x07 #define USB_GET_CONFIGURATION 0x08 #define USB_SET_CONFIGURATION 0x09 #define USB_GET_INTERFACE 0x0A #define USB_SET_INTERFACE 0x0B #define USB_SYNCH_FRAME 0x0C #define USB_SET_SEL 0x30 #define USB_SET_ISOCH_DLY 0x31 #endif #define DEF_STRING_DESC_LANG 0x00 #define DEF_STRING_DESC_MANU 0x01 #define DEF_STRING_DESC_PROD 0x02 #define DEF_STRING_DESC_SERN 0x03 #define DEF_STRING_DESC_OS 0xEE /* USB hub class request code */ #ifndef HUB_GET_DESCRIPTOR #define HUB_GET_STATUS 0x00 #define HUB_CLEAR_FEATURE 0x01 #define HUB_GET_STATE 0x02 #define HUB_SET_FEATURE 0x03 #define HUB_GET_DESCRIPTOR 0x06 #define HUB_SET_DESCRIPTOR 0x07 #endif /* USB HID class request code */ #ifndef HID_GET_REPORT #define HID_GET_REPORT 0x01 #define HID_GET_IDLE 0x02 #define HID_GET_PROTOCOL 0x03 #define HID_SET_REPORT 0x09 #define HID_SET_IDLE 0x0A #define HID_SET_PROTOCOL 0x0B #endif /* USB CDC Class request code */ #ifndef CDC_GET_LINE_CODING #define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ #define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ #define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ #define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ #endif /* USB UVC device request code */ #define UVC_GET_CUR 0x81 #define UVC_GET_MIN 0x82 #define UVC_GET_MAX 0x83 #define UVC_GET_RES 0x84 #define UVC_GET_LEN 0x85 #define UVC_GET_INFO 0x86 #define UVC_GET_DEF 0x87 /* Bit Define for USB Request Type */ #ifndef USB_REQ_TYP_MASK #define USB_REQ_TYP_IN 0x80 #define USB_REQ_TYP_OUT 0x00 #define USB_REQ_TYP_READ 0x80 #define USB_REQ_TYP_WRITE 0x00 #define USB_REQ_TYP_MASK 0x60 #define USB_REQ_TYP_STANDARD 0x00 #define USB_REQ_TYP_CLASS 0x20 #define USB_REQ_TYP_VENDOR 0x40 #define USB_REQ_TYP_RESERVED 0x60 #define USB_REQ_RECIP_MASK 0x1F #define USB_REQ_RECIP_DEVICE 0x00 #define USB_REQ_RECIP_INTERF 0x01 #define USB_REQ_RECIP_ENDP 0x02 #define USB_REQ_RECIP_OTHER 0x03 #define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 #define USB_REQ_FEAT_ENDP_HALT 0x00 #endif /* USB Descriptor Type */ #ifndef USB_DESCR_TYP_DEVICE #define USB_DESCR_TYP_DEVICE 0x01 #define USB_DESCR_TYP_CONFIG 0x02 #define USB_DESCR_TYP_STRING 0x03 #define USB_DESCR_TYP_INTERF 0x04 #define USB_DESCR_TYP_ENDP 0x05 #define USB_DESCR_TYP_QUALIF 0x06 #define USB_DESCR_TYP_SPEED 0x07 #define USB_DESCR_TYP_OTG 0x09 #define USB_DESCR_TYP_BOS 0X0F #define USB_DESCR_TYP_HID 0x21 #define USB_DESCR_TYP_REPORT 0x22 #define USB_DESCR_TYP_PHYSIC 0x23 #define USB_DESCR_TYP_CS_INTF 0x24 #define USB_DESCR_TYP_CS_ENDP 0x25 #define USB_DESCR_TYP_HUB 0x29 #endif /* USB Device Class */ #ifndef USB_DEV_CLASS_HUB #define USB_DEV_CLASS_RESERVED 0x00 #define USB_DEV_CLASS_AUDIO 0x01 #define USB_DEV_CLASS_COMMUNIC 0x02 #define USB_DEV_CLASS_HID 0x03 #define USB_DEV_CLASS_MONITOR 0x04 #define USB_DEV_CLASS_PHYSIC_IF 0x05 #define USB_DEV_CLASS_POWER 0x06 #define USB_DEV_CLASS_IMAGE 0x06 #define USB_DEV_CLASS_PRINTER 0x07 #define USB_DEV_CLASS_STORAGE 0x08 #define USB_DEV_CLASS_HUB 0x09 #define USB_DEV_CLASS_VEN_SPEC 0xFF #endif /* USB Hub Class Request */ #ifndef HUB_GET_HUB_DESCRIPTOR #define HUB_CLEAR_HUB_FEATURE 0x20 #define HUB_CLEAR_PORT_FEATURE 0x23 #define HUB_GET_BUS_STATE 0xA3 #define HUB_GET_HUB_DESCRIPTOR 0xA0 #define HUB_GET_HUB_STATUS 0xA0 #define HUB_GET_PORT_STATUS 0xA3 #define HUB_SET_HUB_DESCRIPTOR 0x20 #define HUB_SET_HUB_FEATURE 0x20 #define HUB_SET_PORT_FEATURE 0x23 #endif /* Hub Class Feature Selectors */ #ifndef HUB_PORT_RESET #define HUB_C_HUB_LOCAL_POWER 0 #define HUB_C_HUB_OVER_CURRENT 1 #define HUB_PORT_CONNECTION 0 #define HUB_PORT_ENABLE 1 #define HUB_PORT_SUSPEND 2 #define HUB_PORT_OVER_CURRENT 3 #define HUB_PORT_RESET 4 #define HUB_PORT_POWER 8 #define HUB_PORT_LOW_SPEED 9 #define HUB_C_PORT_CONNECTION 16 #define HUB_C_PORT_ENABLE 17 #define HUB_C_PORT_SUSPEND 18 #define HUB_C_PORT_OVER_CURRENT 19 #define HUB_C_PORT_RESET 20 #endif /* USB UDisk */ #ifndef USB_BO_CBW_SIZE #define USB_BO_CBW_SIZE 0x1F #define USB_BO_CSW_SIZE 0x0D #endif #ifndef USB_BO_CBW_SIG0 #define USB_BO_CBW_SIG0 0x55 #define USB_BO_CBW_SIG1 0x53 #define USB_BO_CBW_SIG2 0x42 #define USB_BO_CBW_SIG3 0x43 #define USB_BO_CSW_SIG0 0x55 #define USB_BO_CSW_SIG1 0x53 #define USB_BO_CSW_SIG2 0x42 #define USB_BO_CSW_SIG3 0x53 #endif #define USB_U1_ENABLE 0x30 #define USB_U2_ENABLE 0x31 /*******************************************************************************/ /* USBSS Related Register Macro Definition */ /* LINK_CFG */ #define U3_LINK_RESET 0x80000000 #define LINK_FORCE_RXTERM 0x00800000 #define LINK_FORCE_POLLING 0x00400000 #define LINK_TOUT_MODE 0x00200000 #define LINK_U1_PING_EN 0x00100000 #define LINK_U2_ALLOW 0x00020000 #define LINK_U1_ALLOW 0x00010000 #define LINK_LTSSM_MODE 0x00008000 #define LINK_LOOPBACK_ACT 0x00004000 #define LINK_LOOPBACK_EN 0x00002000 #define LINK_U2_RXDET 0x00001000 #define LINK_CP78_SEL_MASK 0x00000C00 #define LINK_CP78_SEL_190BITS 0x00000000 #define LINK_CP78_SEL_120BITS 0x00000400 #define LINK_CP78_SEL_50BITS 0x00000800 #define LINK_CP78_SEL_250BITS 0x00000C00 #define LINK_TX_DEEMPH_MASK 0x00000300 #define LINK_TX_DEEMPH_6DB 0x00000000 #define LINK_TX_DEEMPH_3_5DB 0x00000100 #define LINK_TX_SWING 0x00000080 #define LINK_RX_EQ_EN 0x00000040 #define LINK_LFPS_RX_PD 0x00000020 #define LINK_COMPLIANCE_EN 0x00000010 #define LINK_PHY_RESET 0x00000008 #define LINK_SS_PLR_SWAP 0x00000004 #define LINK_RX_TERM_EN 0x00000002 #define LINK_DOWN_MODE 0x00000001 /* LINK_CTRL */ #define LINK_RX_TS_CFG_MASK 0xFF000000 #define LINK_TX_TS_CFG_MASK 0x00FF0000 #define LINK_HOT_RESET 0x00010000 #define LINK_TX_LGO_U3 0x00008000 #define LINK_TX_LGO_U2 0x00004000 #define LINK_TX_LGO_U1 0x00002000 #define LINK_POLLING_EN 0x00001000 #define LINK_REG_ROUT_EN 0x00000800 #define LINK_LUP_LDN_EN 0x00000400 #define LINK_TX_UX_EXIT 0x00000200 #define LINK_TX_WARM_RESET 0x00000100 #define LINK_GO_RX_DET 0x00000080 #define LINK_GO_RECOVERY 0x00000040 #define LINK_GO_INACTIVE 0x00000020 #define LINK_GO_DISABLED 0x00000010 #define LINK_PD_MODE_MASK 0x00000003 #define LINK_P0_MODE 0x00000000 #define LINK_P1_MODE 0x00000001 #define LINK_P2_MODE 0x00000002 #define LINK_P3_MODE 0x00000003 /* LINK_INT_CTRL */ #define LINK_IE_STATE_CHG 0x80000000 #define LINK_IE_U1_TOUT 0x40000000 #define LINK_IE_U2_TOUT 0x20000000 #define LINK_IE_UX_FAIL 0x10000000 #define LINK_IE_TX_WARMRST 0x08000000 #define LINK_IE_UX_EXIT_FAIL 0x04000000 #define LINK_IE_RX_LMP_TOUT 0x00800000 #define LINK_IE_TX_LMP 0x00400000 #define LINK_IE_RX_LMP 0x00200000 #define LINK_IE_RX_DET 0x00100000 #define LINK_IE_LOOPBACK 0x00080000 #define LINK_IE_COMPLIANCE 0x00040000 #define LINK_IE_HPBUF_FULL 0x00020000 #define LINK_IE_HPBUF_EMPTY 0x00010000 #define LINK_IE_HOT_RST 0x00008000 #define LINK_IE_WAKEUP 0x00004000 #define LINK_IE_WARM_RST 0x00002000 #define LINK_IE_UX_EXIT 0x00001000 #define LINK_IE_TXEQ 0x00000800 #define LINK_IE_TERM_PRES 0x00000400 #define LINK_IE_UX_REJ 0x00000200 #define LINK_IE_U3_WK_TOUT 0x00000100 #define LINK_IE_GO_U0 0x00000080 #define LINK_IE_GO_U1 0x00000040 #define LINK_IE_GO_U2 0x00000020 #define LINK_IE_GO_U3 0x00000010 #define LINK_IE_DISABLE 0x00000008 #define LINK_IE_INACTIVE 0x00000004 #define LINK_IE_RECOVERY 0x00000002 #define LINK_IE_READY 0x00000001 /* LINK_INT_FLAG */ #define LINK_IF_STATE_CHG 0x80000000 #define LINK_IF_U1_TOUT 0x40000000 #define LINK_IF_U2_TOUT 0x20000000 #define LINK_IF_UX_FAIL 0x10000000 #define LINK_IF_TX_WARMRST 0x08000000 #define LINK_IF_UX_EXIT_FAIL 0x04000000 #define LINK_IF_RX_LMP_TOUT 0x00800000 #define LINK_IF_TX_LMP 0x00400000 #define LINK_IF_RX_LMP 0x00200000 #define LINK_IF_RX_DET 0x00100000 #define LINK_IF_LOOPBACK 0x00080000 #define LINK_IF_COMPLIANCE 0x00040000 #define LINK_IF_HPBUF_FULL 0x00020000 #define LINK_IF_HPBUF_EMPTY 0x00010000 #define LINK_IF_HOT_RST 0x00008000 #define LINK_IF_WAKEUP 0x00004000 #define LINK_IF_WARM_RST 0x00002000 #define LINK_IF_UX_EXIT 0x00001000 #define LINK_IF_TXEQ 0x00000800 #define LINK_IF_TERM_PRES 0x00000400 #define LINK_IF_UX_REJ 0x00000200 #define LINK_IF_U3_WK_TOUT 0x00000100 #define LINK_IF_GO_U0 0x00000080 #define LINK_IF_GO_U1 0x00000040 #define LINK_IF_GO_U2 0x00000020 #define LINK_IF_GO_U3 0x00000010 #define LINK_IF_DISABLE 0x00000008 #define LINK_IF_INACTIVE 0x00000004 #define LINK_IF_RECOVERY 0x00000002 #define LINK_IF_READY 0x00000001 /* LINK_STATUS */ #define LINK_HPBUF_EMPTY 0x80000000 #define LINK_HPBUF_FULL 0x40000000 #define LINK_HPBUF_IDLE 0x20000000 #define LINK_U3_SLEEP_ALLOW 0x00400000 #define LINK_U2_SLEEP_ALLOW 0x00200000 #define LINK_RXDET_SLEEP_ALLOW 0x00100000 #define LINK_WAKUP 0x00080000 #define LINK_RX_LFPS 0x00040000 #define LINK_RX_DETECT 0x00020000 #define LINK_RX_UX_EXIT_REQ 0x00010000 #define LINK_STATE_MASK 0x00000F00 #define LINK_STATE_U0 0x00000000 #define LINK_STATE_U1 0x00000100 #define LINK_STATE_U2 0x00000200 #define LINK_STATE_U3 0x00000300 #define LINK_STATE_DISABLE 0x00000400 #define LINK_STATE_RXDET 0x00000500 #define LINK_STATE_INACTIVE 0x00000600 #define LINK_STATE_POLLING 0x00000700 #define LINK_STATE_RECOVERY 0x00000800 #define LINK_STATE_HOTRST 0x00000900 #define LINK_STATE_COMPLIANCE 0x00000A00 #define LINK_STATE_LOOPBACK 0x00000B00 #define LINK_TXEQ 0x00000040 #define LINK_PD_MODE_ST_MASK 0x00000030 #define LINK_PD_MODE_ST_P0 0x00000000 #define LINK_PD_MODE_ST_P1 0x00000010 #define LINK_PD_MODE_ST_P2 0x00000020 #define LINK_PD_MODE_ST_P3 0x00000030 #define LINK_READY 0x00000008 #define LINK_BUSY 0x00000004 #define LINK_RX_WARM_RST 0x00000002 #define LINK_RX_TERM_PRES 0x00000001 /* LINK_LPM_CR */ #define LINK_LPM_TERM_PRESENT 0x00000800 #define LINK_LPM_TERM_CHG 0x00000400 #define LINK_LPM_EN 0x00000200 #define LINK_LPM_RST 0x00000100 /* LINK_PORT_CAP */ #define LINK_LMP_RX_CAP_VLD 0x80000000 #define LINK_LMP_TX_CAP_VLD 0x40000000 #define LINK_SPEED_MASK 0x3F000000 #define LINK_PORT_CAP_MASK 0x00FFFFFF /* USB_CONTROL */ #define USBSS_DEV_ADDR_MASK 0x7F000000 #define USBSS_UIE_FIFO_RXOV 0x00800000 #define USBSS_UIE_FIFO_TXOV 0x00400000 #define USBSS_UIE_ITP 0x00100000 #define USBSS_UIE_RX_PING 0x00080000 #define USBSS_UDIE_STATUS 0x00040000 #define USBSS_UHIE_NOTIF 0x00040000 #define USBSS_UDIE_SETUP 0x00020000 #define USBSS_UHIE_ERDY 0x00020000 #define USBSS_UIE_TRANSFER 0x00010000 #define USBSS_CHAIN_CONFLICT 0x00008000 #define USBSS_TX_ERDY_MODE 0x00004000 #define USBSS_HP_PEND_MASK 0x00000300 #define USBSS_HP_PENDING 0x00000200 #define USBSS_HOST_MODE 0x00000080 #define USBSS_ITP_EN 0x00000040 #define USBSS_SETUP_FLOW 0x00000020 #define USBSS_DIR_ABORT 0x00000010 #define USBSS_DMA_MODE 0x00000008 #define USBSS_FORCE_RST 0x00000004 #define USBSS_USB_CLR_ALL 0x00000002 #define USBSS_DMA_EN 0x00000001 /* USB_STATUS */ #define USBSS_HRX_RES_MASK 0xC0000000 #define USBSS_HTX_RES_MASK 0x00C00000 #define USBSS_EP_DIR_MASK 0x00001000 #define USBSS_EP_ID_MASK 0x00000700 #define USBSS_UIF_FIFO_RXOV 0x00000080 #define USBSS_UIF_FIFO_TXOV 0x00000040 #define USBSS_UIF_ITP 0x00000010 #define USBSS_UIF_RX_PING 0x00000008 #define USBSS_UDIF_STATUS 0x00000004 #define USBSS_UHIF_NOTIF 0x00000004 #define USBSS_UDIF_SETUP 0x00000002 #define USBSS_UHIF_ERDY 0x00000002 #define USBSS_UIF_TRANSFER 0x00000001 /* USB_ITP */ #define USBSS_ITP_INTERVAL_MASK 0x00003FFF /* USB_ITP_ADJ */ #define USBSS_ITP_DELTA 0x001FFF00 #define USBSS_ITP_DELAYED 0x00000080 #define USBSS_ITP_ADJ_CR_MASK 0x0000007F /* UEP_TX_EN */ #define USBSS_EP15_TX_EN 0x00008000 #define USBSS_EP14_TX_EN 0x00004000 #define USBSS_EP13_TX_EN 0x00002000 #define USBSS_EP12_TX_EN 0x00001000 #define USBSS_EP11_TX_EN 0x00000800 #define USBSS_EP10_TX_EN 0x00000400 #define USBSS_EP9_TX_EN 0x00000200 #define USBSS_EP8_TX_EN 0x00000100 #define USBSS_EP7_TX_EN 0x00000080 #define USBSS_EP6_TX_EN 0x00000040 #define USBSS_EP5_TX_EN 0x00000020 #define USBSS_EP4_TX_EN 0x00000010 #define USBSS_EP3_TX_EN 0x00000008 #define USBSS_EP2_TX_EN 0x00000004 #define USBSS_EP1_TX_EN 0x00000002 #define USBSS_UH_TX_EN 0x00000002 /* UEP_RX_EN */ #define USBSS_EP15_RX_EN 0x00008000 #define USBSS_EP14_RX_EN 0x00004000 #define USBSS_EP13_RX_EN 0x00002000 #define USBSS_EP12_RX_EN 0x00001000 #define USBSS_EP11_RX_EN 0x00000800 #define USBSS_EP10_RX_EN 0x00000400 #define USBSS_EP9_RX_EN 0x00000200 #define USBSS_EP8_RX_EN 0x00000100 #define USBSS_EP7_RX_EN 0x00000080 #define USBSS_EP6_RX_EN 0x00000040 #define USBSS_EP5_RX_EN 0x00000020 #define USBSS_EP4_RX_EN 0x00000010 #define USBSS_EP3_RX_EN 0x00000008 #define USBSS_EP2_RX_EN 0x00000004 #define USBSS_EP1_RX_EN 0x00000002 #define USBSS_UH_RX_EN 0x00000002 /* UEP0_TX_CTRL */ #define USBSS_UIF_EP0_TX_ACT 0x80000000 #define USBSS_EP0_TX_FLOW 0x02000000 #define USBSS_EP0_TX_PP 0x01000000 #define USBSS_EP0_TX_ERDY 0x00800000 #define USBSS_EP0_TX_RES 0x00600000 #define USBSS_EP0_TX_NRDY 0x00000000 #define USBSS_EP0_TX_DPH 0x00200000 #define USBSS_EP0_TX_STALL 0x00400000 #define USBSS_EP0_TX_SEQ_MASK 0x001F0000 #define USBSS_NUMP_1 0x00010000 #define USBSS_NUMP_2 0x00020000 #define USBSS_NUMP_3 0x00030000 #define USBSS_NUMP_4 0x00040000 #define USBSS_NUMP_5 0x00050000 #define USBSS_NUMP_6 0x00060000 #define USBSS_NUMP_7 0x00070000 #define USBSS_NUMP_8 0x00080000 #define USBSS_NUMP_9 0x00090000 #define USBSS_NUMP_10 0x000A0000 #define USBSS_NUMP_11 0x000B0000 #define USBSS_NUMP_12 0x000C0000 #define USBSS_NUMP_13 0x000D0000 #define USBSS_NUMP_14 0x000E0000 #define USBSS_NUMP_15 0x000F0000 #define USBSS_NUMP_16 0x00100000 #define USBSS_EP0_TX_LEN_MASK 0x000007FF /* UEP0_RX_CTRL */ #define USBSS_UIF_EP0_RX_ACT 0x80000000 #define USBSS_EP0_RX_PP 0x01000000 #define USBSS_EP0_RX_ERDY 0x00800000 #define USBSS_EP0_RX_RES 0x00600000 #define USBSS_EP0_RX_NRDY 0x00000000 #define USBSS_EP0_RX_ACK 0x00200000 #define USBSS_EP0_RX_STALL 0x00400000 #define USBSS_EP0_RX_SEQ_MASK 0x001F0000 #define USBSS_EP0_RX_LEN_MASK 0x000007FF /* R8_UEPn_TX_CFG */ #define USBSS_EP_TX_CHAIN_AUTO 0x80 #define USBSS_EP_TX_FIFO_MODE 0x40 #define USBSS_EP_TX_FIFO_CFG 0x20 #define USBSS_EP_TX_EOB_MODE 0x08 #define USBSS_EP_TX_ERDY_AUTO 0x04 #define USBSS_EP_TX_SEQ_AUTO 0x02 #define USBSS_EP_TX_ISO_MODE 0x01 /* R8_UEPn_TX_CR */ #define USBSS_EP_TX_HALT 0x80 #define USBSS_EP_TX_CLR 0x40 #define USBSS_EP_TX_CHAIN_CLR 0x20 #define USBSS_EP_TX_ERDY_NUMP_MASK 0x1F /* R8_UEPn_TX_SEQ */ #define USBSS_EP_TX_SEQ_NUM_MASK 0x1F /* R8_UEPn_TX_ST */ #define USBSS_EP_TX_INT_FLAG 0x80 #define USBSS_EP_TX_FC_ST 0x40 #define USBSS_EP_TX_ERDY_REQ 0x20 #define USBSS_EP_TX_CHAIN_RES 0x10 #define USBSS_EP_TX_CHAIN_EN_MASK 0x0F /* R8_UEPn_TX_CHAIN_CR */ #define USBSS_EP_TX_CUR_USE 0xC0 #define USBSS_EP_TX_CUR_CFG 0x30 #define USBSS_EP_TX_FORCE_RET 0x04 #define USBSS_EP_TX_RET_SEL 0x03 /* R8_UEPn_TX_CHAIN_ST */ #define USBSS_EP_TX_CHAIN_EN 0x80 #define USBSS_EP_TX_CHAIN_IF 0x40 #define USBSS_EP_TX_EOB_LPF 0x20 #define USBSS_EP_TX_NUMP_EMPTY 0x08 #define USBSS_EP_TX_DPH_PP 0x04 #define USBSS_EP_TX_CHAIN_NO_MASK 0x03 /* R8_UEPn_RX_CFG */ #define USBSS_EP_RX_CHAIN_AUTO 0x80 #define USBSS_EP_RX_FIFO_MODE 0x40 #define USBSS_EP_RX_FIFO_CFG 0x20 #define USBSS_EP_RX_EOB_MODE 0x08 #define USBSS_EP_RX_ERDY_AUTO 0x04 #define USBSS_EP_RX_SEQ_AUTO 0x02 #define USBSS_EP_RX_ISO_MODE 0x01 /* R8_UEPn_RX_CR */ #define USBSS_EP_RX_HALT 0x80 #define USBSS_EP_RX_CLR 0x40 #define USBSS_EP_RX_CHAIN_CLR 0x20 #define USBSS_EP_RX_ERDY_NUMP_MASK 0x1F /* R8_UEPn_RX_SEQ */ #define USBSS_EP_RX_SEQ_NUM_MASK 0x1F /* R8_UEPn_RX_ST */ #define USBSS_EP_RX_INT_FLAG 0x80 #define USBSS_EP_RX_FC_ST 0x40 #define USBSS_EP_RX_ERDY_REQ 0x20 #define USBSS_EP_RX_CHAIN_RES 0x10 #define USBSS_EP_RX_CHAIN_EN_MASK 0x0F /* R8_UEPn_RX_CHAIN_CR */ #define USBSS_EP_RX_CUR_USE 0xC0 #define USBSS_EP_RX_CUR_CFG 0x30 #define USBSS_EP_RX_FORCE_RET 0x04 #define USBSS_EP_RX_RET_SEL 0x03 /* R8_UEPn_RX_CHAIN_ST */ #define USBSS_EP_RX_CHAIN_EN 0x80 #define USBSS_EP_RX_CHAIN_IF 0x40 #define USBSS_EP_RX_LPF_FLAG 0x20 #define USBSS_EP_RX_ISO_PKT_ERR 0x10 #define USBSS_EP_RX_NUMP_EMPTY 0x08 #define USBSS_EP_RX_DPH_PP 0x04 #define USBSS_EP_RX_CHAIN_NO_MASK 0x03 /* R32_UH_TX_CTRL */ #define USBSS_UH_TX_ACT 0x80000000 #define USBSS_UH_TX_ISO 0x40000000 #define USBSS_UH_TX_SETUP 0x20000000 #define USBSS_UH_TX_STATUS 0x10000000 #define USBSS_UH_TX_LPF 0x00800000 #define USBSS_UH_TX_RES 0x00600000 #define USBSS_UH_TX_NRDY 0x00000000 #define USBSS_UH_TX_ACK 0x00200000 #define USBSS_UH_TX_STALL 0x00400000 #define USBSS_UH_TX_SEQ 0x001F0000 #define USBSS_UH_TX_EP 0x0000F000 #define USBSS_UH_TX_LEN_MASK 0x000007FF /* R32_UH_RX_CTRL */ #define USBSS_UH_RX_ACT 0x80000000 #define USBSS_UH_RX_ISO 0x40000000 #define USBSS_UH_RX_NUMP 0x1F000000 #define USBSS_UH_RX_RES 0x00600000 #define USBSS_UH_RX_NRDY 0x00000000 #define USBSS_UH_RX_ACK 0x00200000 #define USBSS_UH_RX_STALL 0x00400000 #define USBSS_UH_RX_SEQ 0x001F0000 #define USBSS_UH_RX_EP 0x0000F000 #define USBSS_UH_RX_LEN_MASK 0x000007FF /* R32_HOST_STATUS */ #define USBSS_UH_ITP_PRESAGE 0x000C0000 #define USBSS_UH_RX_ISO_PKT_ERR 0x00020000 #define USBSS_UH_RX_EOB_LPF 0x00010000 #define USBSS_UH_RX_ERDY_DIR 0x00008000 #define USBSS_UH_RX_ERDY_NUMP 0x00001F00 #define USBSS_UH_RX_ERDY_EP 0x000000F0 /*******************************************************************************/ /* USBHS Related Register Macro Definition */ /* R8_USB_CTRL */ #define USBHS_UD_LPM_EN 0x80 #define USBHS_UD_DEV_EN 0x20 #define USBHS_UD_DMA_EN 0x10 #define USBHS_UD_PHY_SUSPENDM 0x08 #define USBHS_UD_CLR_ALL 0x04 #define USBHS_UD_RST_SIE 0x02 #define USBHS_UD_RST_LINK 0x01 /* R8_USB_BASE_MODE */ #define USBHS_UD_SPEED_FULL 0x00 #define USBHS_UD_SPEED_HIGH 0x01 #define USBHS_UD_SPEED_LOW 0x02 #define USBHS_UD_SPEED_TYPE 0x03 /* R8_USB_INT_EN */ #define USBHS_UDIE_FIFO_OVER 0x80 #define USBHS_UDIE_LINK_RDY 0x40 #define USBHS_UDIE_SOF_ACT 0x20 #define USBHS_UDIE_TRANSFER 0x10 #define USBHS_UDIE_LPM_ACT 0x08 #define USBHS_UDIE_BUS_SLEEP 0x04 #define USBHS_UDIE_SUSPEND 0x02 #define USBHS_UDIE_BUS_RST 0x01 /* R8_USB_DEV_AD */ #define USBHS_UD_DEV_ADDR 0x7F /* R8_USB_WAKE_CTRL */ #define USBHS_UD_REMOTE_WKUP 0x01 /* R8_USB_TEST_MODE */ #define USBHS_UD_TEST_EN 0x80 #define USBHS_UD_TEST_SE0NAK 0x08 #define USBHS_UD_TEST_PKT 0x04 #define USBHS_UD_TEST_K 0x02 #define USBHS_UD_TEST_J 0x01 /* R16_USB_LPM_DATA */ #define USBHS_UD_LPM_BUSY 0x8000 #define USBHS_UD_LPM_DATA 0x07FF /* R8_USB_INT_FG */ #define USBHS_UDIF_FIFO_OV 0x80 #define USBHS_UDIF_LINK_RDY 0x40 #define USBHS_UDIF_RX_SOF 0x20 #define USBHS_UDIF_TRANSFER 0x10 #define USBHS_UDIF_RTX_ACT 0x10 #define USBHS_UDIF_LPM_ACT 0x08 #define USBHS_UDIF_BUS_SLEEP 0x04 #define USBHS_UDIF_SUSPEND 0x02 #define USBHS_UDIF_BUS_RST 0x01 /* R8_USB_INT_ST */ #define USBHS_UDIS_EP_DIR 0x10 #define USBHS_UDIS_EP_ID_MASK 0x07 /* R8_USB_MIS_ST */ #define USBHS_UDMS_HS_MOD 0x80 #define USBHS_UDMS_SUSP_REQ 0x10 #define USBHS_UDMS_SIE_FREE 0x08 #define USBHS_UDMS_SLEEP 0x04 #define USBHS_UDMS_SUSPEND 0x02 #define USBHS_UDMS_READY 0x01 /* R16_USB_FRAME_NO */ #define USBHS_UD_MFRAME_NO 0xE000 #define USBHS_UD_FRAME_NO 0x07FF /* R16_USB_BUS */ #define USBHS_USB_DM_ST 0x08 #define USBHS_USB_DP_ST 0x04 #define USB_WAKEUP 0x01 /* R16_UEP_TX_EN */ #define USBHS_UEP0_T_EN 0x0001 #define USBHS_UEP1_T_EN 0x0002 #define USBHS_UEP2_T_EN 0x0004 #define USBHS_UEP3_T_EN 0x0008 #define USBHS_UEP4_T_EN 0x0010 #define USBHS_UEP5_T_EN 0x0020 #define USBHS_UEP6_T_EN 0x0040 #define USBHS_UEP7_T_EN 0x0080 #define USBHS_UEP8_T_EN 0x0100 #define USBHS_UEP9_T_EN 0x0200 #define USBHS_UEP10_T_EN 0x0400 #define USBHS_UEP11_T_EN 0x0800 #define USBHS_UEP12_T_EN 0x1000 #define USBHS_UEP13_T_EN 0x2000 #define USBHS_UEP14_T_EN 0x4000 #define USBHS_UEP15_T_EN 0x8000 /* R16_UEP_RX_EN */ #define USBHS_UEP0_R_EN 0x0001 #define USBHS_UEP1_R_EN 0x0002 #define USBHS_UEP2_R_EN 0x0004 #define USBHS_UEP3_R_EN 0x0008 #define USBHS_UEP4_R_EN 0x0010 #define USBHS_UEP5_R_EN 0x0020 #define USBHS_UEP6_R_EN 0x0040 #define USBHS_UEP7_R_EN 0x0080 #define USBHS_UEP8_R_EN 0x0100 #define USBHS_UEP9_R_EN 0x0200 #define USBHS_UEP10_R_EN 0x0400 #define USBHS_UEP11_R_EN 0x0800 #define USBHS_UEP12_R_EN 0x1000 #define USBHS_UEP13_R_EN 0x2000 #define USBHS_UEP14_R_EN 0x4000 #define USBHS_UEP15_R_EN 0x8000 /* R16_UEP_T_TOG_AUTO */ #define USBHS_UEP_T_TOG_AUTO 0xFF /* R16_UEP_R_TOG_AUTO */ #define USBHS_UEP_R_TOG_AUTO 0xFF /* R8_UEP_T_BURST */ #define USBHS_UEP_T_BURST_EN 0xFF /* R8_UEP_T_BURST_MODE */ #define USBHS_UEP_T_BURST_MODE 0xFF /* R8_UEP_R_BURST */ #define USBHS_UEP_R_BURST_EN 0xFF /* R8_UEP_R_RES_MODE */ #define USBHS_UEP_R_RES_MODE 0xFF /* R32_UEP_AF_MODE */ #define USBHS_UEP_T_AF 0xFE /* R32_UEP0_DMA */ #define UEPn_DMA 0xFFFFFF /* R32_UEPn_RX_DMA */ #define UEPn_RX_DMA 0xFFFFFF /* R32_UEPn_TX_DMA */ #define UEPn_TX_DMA 0xFFFFFF /* R32_UEPn_MAX_LEN */ #define USBHS_UEP0_MAX_LEN 0x007F #define USBHS_UEPn_MAX_LEN 0x07FF /* R16_UEPn_RX_LEN */ #define USBHS_UEP0_RX_LEN 0x007F /* R16_UEPn_RX_LEN */ #define USBHS_UEPn_RX_LEN 0xFFFF /* R16_UEPn_R_SIZE */ #define USBHS_UEPn_R_SIZE 0xFFFF /* R16_UEP0_T_LEN */ #define USBHS_UEP0_T_LEN 0x7F /**R16_UEPn_T_LEN**/ #define USBHS_UEPn_T_LEN 0xFFFF /**R8_UEPn_TX_CTRL**/ #define USBHS_UEP_T_DONE 0x80 #define USBHS_UEP_T_NAK_ACT 0x40 #define USBHS_UEP_T_TOG_MASK 0x0C #define USBHS_UEP_T_TOG_MDATA 0x0C #define USBHS_UEP_T_TOG_DATA2 0x08 #define USBHS_UEP_T_TOG_DATA1 0x04 #define USBHS_UEP_T_TOG_DATA0 0x00 #define USBHS_UEP_T_RES_MASK 0x03 #define USBHS_UEP_T_RES_ACK 0x02 #define USBHS_UEP_T_RES_STALL 0x01 #define USBHS_UEP_T_RES_NAK 0x00 /**R8_UEP0_RX_CTRL**/ /**R8_UEPn_RX_CTRL**/ #define USBHS_UEP_R_DONE 0x80 #define USBHS_UEP_R_NAK_ACT 0x40 #define USBHS_UEP_R_NAK_TOG 0x20 #define USBHS_UEP_R_TOG_MATCH 0x10 #define USBHS_UEP_R_SETUP_IS 0x08 #define USBHS_UEP_R_TOG_MASK 0x0C #define USBHS_UEP_R_TOG_MDATA 0x0C #define USBHS_UEP_R_TOG_DATA2 0x08 #define USBHS_UEP_R_TOG_DATA1 0x04 #define USBHS_UEP_R_TOG_DATA0 0x00 #define USBHS_UEP_R_RES_MASK 0x03 #define USBHS_UEP_R_RES_ACK 0x02 #define USBHS_UEP_R_RES_STALL 0x01 #define USBHS_UEP_R_RES_NAK 0x00 /* R16_UEP_T_ISO */ #define USBHS_UEP1_T_FIFO_EN 0x0200 #define USBHS_UEP2_T_FIFO_EN 0x0400 #define USBHS_UEP3_T_FIFO_EN 0x0800 #define USBHS_UEP4_T_FIFO_EN 0x1000 #define USBHS_UEP5_T_FIFO_EN 0x2000 #define USBHS_UEP6_T_FIFO_EN 0x4000 #define USBHS_UEP7_T_FIFO_EN 0x8000 #define USBHS_UEP1_T_ISO_EN 0x0002 #define USBHS_UEP2_T_ISO_EN 0x0004 #define USBHS_UEP3_T_ISO_EN 0x0008 #define USBHS_UEP4_T_ISO_EN 0x0010 #define USBHS_UEP5_T_ISO_EN 0x0020 #define USBHS_UEP6_T_ISO_EN 0x0040 #define USBHS_UEP7_T_ISO_EN 0x0080 /* R16_UEP_R_ISO */ #define USBHS_UEP1_R_FIFO_EN 0x0200 #define USBHS_UEP2_R_FIFO_EN 0x0400 #define USBHS_UEP3_R_FIFO_EN 0x0800 #define USBHS_UEP4_R_FIFO_EN 0x1000 #define USBHS_UEP5_R_FIFO_EN 0x2000 #define USBHS_UEP6_R_FIFO_EN 0x4000 #define USBHS_UEP7_R_FIFO_EN 0x8000 #define USBHS_UEP1_R_ISO_EN 0x0002 #define USBHS_UEP2_R_ISO_EN 0x0004 #define USBHS_UEP3_R_ISO_EN 0x0008 #define USBHS_UEP4_R_ISO_EN 0x0010 #define USBHS_UEP5_R_ISO_EN 0x0020 #define USBHS_UEP6_R_ISO_EN 0x0040 #define USBHS_UEP7_R_ISO_EN 0x0080 /* R32_UEPn_RX_FIFO */ #define USBHS_UEP_RX_FIFO_E 0xFF00 #define USBHS_UEP_RX_FIFO_S 0x00FF /* R32_UEPn_TX_FIFO */ #define USBHS_UEP_TX_FIFO_E 0xFF00 #define USBHS_UEP_TX_FIFO_S 0x00FF /* USB high speed host register */ /* R8_UH_CFG */ #define USBHS_UH_LPM_EN 0x80 #define USBHS_UH_FORCE_FS 0x40 #define USBHS_UH_SOF_EN 0x20 #define USBHS_UH_DMA_EN 0x10 #define USBHS_UH_PHY_SUSPENDM 0x08 #define USBHS_UH_CLR_ALL 0x04 #define USBHS_RST_SIE 0x02 #define USBHS_RST_LINK 0x01 /* R8_UH_INT_EN */ #define USBHS_UHIE_FIFO_OVER 0x80 #define USBHS_UHIE_TX_HALT 0x40 #define USBHS_UHIE_SOF_ACT 0x20 #define USBHS_UHIE_TRANSFER 0x10 #define USBHS_UHIE_RESUME_ACT 0x08 #define USBHS_UHIE_WKUP_ACT 0x04 /* R8_UH_DEV_AD */ #define USBHS_UH_DEV_ADDR 0x7F /* R32_UH_CONTROL */ #define USBHS_UH_RX_NO_RES 0x800000 #define USBHS_UH_TX_NO_RES 0x400000 #define USBHS_UH_RX_NO_DATA 0x200000 #define USBHS_UH_TX_NO_DATA 0x100000 #define USBHS_UH_PRE_PID_EN 0x080000 #define USBHS_UH_SPLIT_VALID 0x040000 #define USBHS_UH_LPM_VALID 0x020000 #define USBHS_UH_HOST_ACTION 0x010000 #define USBHS_UH_BUF_MODE 0x0400 #define USBHS_UH_T_TOG_MASK 0x0300 #define USBHS_UH_T_TOG_MDATA 0x0300 #define USBHS_UH_T_TOG_DATA2 0x0200 #define USBHS_UH_T_TOG_DATA1 0x0100 #define USBHS_UH_T_TOG_DATA0 0x0000 #define USBHS_UH_T_ENDP_MASK 0xF0 #define USBHS_UH_T_TOKEN_MASK 0x0F /* R8_UH_INT_FLAG */ #define USBHS_UHIF_FIFO_OVER 0x80 #define USBHS_UHIF_TX_HALT 0x40 #define USBHS_UHIF_SOF_ACT 0x20 #define USBHS_UHIF_TRANSFER 0x10 #define USBHS_UHIF_RESUME_ACT 0x08 #define USBHS_UHIF_WKUP_ACT 0x04 /* R8_UH_INT_ST */ #define USBHS_UHIF_PORT_RX_RESUME 0x10 #define USBHS_UH_R_TOKEN_MASK 0x0F /* R8_UH_MIS_ST */ #define USBHS_UHMS_BUS_SE0 0x80 #define USBHS_UHMS_BUS_J 0x40 #define USBHS_UHMS_LINESTATE 0x30 #define USBHS_UHMS_USB_WAKEUP 0x08 #define USBHS_UHMS_SOF_ACT 0x04 #define USBHS_UHMS_SOF_PRE 0x02 #define USBHS_UHMS_SOF_FREE 0x01 /* R32_UH_LPM_DATA */ #define USBHS_UH_LPM_DATA 0x07FF /* R32_UH_SPLIT_DATA */ #define USBHS_UH_SPLIT_DATA 0x07FFFF /* R32_UH_FRAME */ #define USBHS_UH_SOF_CNT_CLR 0x02000000 #define USBHS_UH_SOF_CNT_EN 0x01000000 #define USBHS_UH_MFRAME_NO 0x070000 #define USBHS_UH_FRAME_NO 0x07FF /* R32_UH_TX_LEN */ #define USBHS_UH_TX_LEN 0x07FF /* R32_UH_RX_LEN */ #define USBHS_UH_RX_LEN 0x07FF /* R32_UH_RX_MAX_LEN */ #define USBHS_UH_RX_MAX_LEN 0x07FF /* R32_UH_RX_DMA */ #define USBHS_R32_UH_RX_DMA 0x01FFFF /* R32_UH_TX_DMA */ #define USBHS_R32_UH_TX_DMA 0x01FFFF /* R32_UH_PORT_CTRL */ #define USBHS_UH_BUS_RST_LONG 0x010000 #define USBHS_UH_PORT_SLEEP_BESL 0xF000 #define USBHS_UH_CLR_PORT_SLEEP 0x0100 #define USBHS_UH_CLR_PORT_CONNECT 0x20 #define USBHS_UH_CLR_PORT_EN 0x10 #define USBHS_UH_SET_PORT_SLEEP 0x08 #define USBHS_UH_CLR_PORT_SUSP 0x04 #define USBHS_UH_SET_PORT_SUSP 0x02 #define USBHS_UH_SET_PORT_RESET 0x01 /* R8_UH_PORT_CFG */ #define USBHS_UH_PD_EN 0x80 #define USBHS_UH_HOST_EN 0x01 /* R8_UH_PORT_INT_EN */ #define USBHS_UHIE_PORT_SLP 0x20 #define USBHS_UHIE_PORT_RESET 0x10 #define USBHS_UHIE_PORT_SUSP 0x04 #define USBHS_UHIE_PORT_EN 0x02 #define USBHS_UHIE_PORT_CONNECT 0x01 /* R8_UH_PORT_TEST_CT */ #define USBHS_UH_TEST_SE0_NAK 0x10 #define USBHS_UH_TEST_PACKET 0x08 #define USBHS_UH_TEST_FORCE_EN 0x04 #define USBHS_UH_TEST_K 0x02 #define USBHS_UH_TEST_J 0x01 /* R16_UH_PORT_ST */ #define USBHS_UHIS_PORT_TEST 0x0800 #define USBHS_UHIS_PORT_SPEED_MASK 0x0600 #define USBHS_UHIS_PORT_HS 0x0400 #define USBHS_UHIS_PORT_LS 0x0200 #define USBHS_UHIS_PORT_FS 0x0000 #define USBHS_UHIS_PORT_SLP 0x20 #define USBHS_UHIS_PORT_RST 0x10 #define USBHS_UHIS_PORT_SUSP 0x04 #define USBHS_UHIS_PORT_EN 0x02 #define USBHS_UHIS_PORT_CONNECT 0x01 /* R8_UH_PORT_CHG */ #define USBHS_UHIF_PORT_SLP 0x20 #define USBHS_UHIF_PORT_RESET 0x10 #define USBHS_UHIF_PORT_SUSP 0x04 #define USBHS_UHIF_PORT_EN 0x02 #define USBHS_UHIF_PORT_CONNECT 0x01 /* R32_UH_BC_CTRL */ #define UDM_VSRC_ACT 0x0400 #define UDM_BC_VSRC 0x0200 #define UDP_BC_VSRC 0x0100 #define BC_AUTO_MODE 0x40 #define UDM_BC_CMPE 0x20 #define UDP_BC_CMPE 0x10 #define UDM_BC_CMPO 0x02 #define UDP_BC_CMPO 0x01 /*******************************************************************************/ /* USBFS Related Register Macro Definition */ /* R8_USB_CTRL */ #define USBFS_UC_HOST_MODE 0x80 #define USBFS_UC_LOW_SPEED 0x40 #define USBFS_UC_DEV_PU_EN 0x20 #define USBFS_UC_SYS_CTRL_MASK 0x30 #define USBFS_UC_SYS_CTRL0 0x00 #define USBFS_UC_SYS_CTRL1 0x10 #define USBFS_UC_SYS_CTRL2 0x20 #define USBFS_UC_SYS_CTRL3 0x30 #define USBFS_UC_INT_BUSY 0x08 #define USBFS_UC_RESET_SIE 0x04 #define USBFS_UC_CLR_ALL 0x02 #define USBFS_UC_DMA_EN 0x01 /* R8_USB_INT_EN */ #define USBFS_UIE_DEV_SOF 0x80 #define USBFS_UIE_DEV_NAK 0x40 #define USBFS_U_1WIRE_MODE 0x20 #define USBFS_UIE_FIFO_OV 0x10 #define USBFS_UIE_HST_SOF 0x08 #define USBFS_UIE_SUSPEND 0x04 #define USBFS_UIE_TRANSFER 0x02 #define USBFS_UIE_DETECT 0x01 #define USBFS_UIE_BUS_RST 0x01 /* R8_USB_DEV_AD */ #define USBFS_UDA_GP_BIT 0x80 #define USBFS_USB_ADDR_MASK 0x7F /* R8_USB_MIS_ST */ #define USBFS_UMS_SOF_PRES 0x80 #define USBFS_UMS_SOF_ACT 0x40 #define USBFS_UMS_SIE_FREE 0x20 #define USBFS_UMS_R_FIFO_RDY 0x10 #define USBFS_UMS_BUS_RESET 0x08 #define USBFS_UMS_SUSPEND 0x04 #define USBFS_UMS_DM_LEVEL 0x02 #define USBFS_UMS_DEV_ATTACH 0x01 /* R8_USB_INT_FG */ #define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received #define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK #define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status #define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear #define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear #define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear #define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear #define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear #define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear /* R8_USB_INT_ST */ #define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode #define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK #define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode #define USBFS_UIS_TOKEN_OUT 0x00 #define USBFS_UIS_TOKEN_SOF 0x10 #define USBFS_UIS_TOKEN_IN 0x20 #define USBFS_UIS_TOKEN_SETUP 0x30 // bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode // 00: OUT token PID received // 01: SOF token PID received // 10: IN token PID received // 11: SETUP token PID received #define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode #define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received /* R32_USB_OTG_CR */ #define USBFS_CR_SESS_VTH 0x20 #define USBFS_CR_VBUS_VTH 0x10 #define USBFS_CR_OTG_EN 0x08 #define USBFS_CR_IDPU 0x04 #define USBFS_CR_CHARGE_VBUS 0x02 #define USBFS_CR_DISCHAR_VBUS 0x01 /* R32_USB_OTG_SR */ #define USBFS_SR_ID_DIG 0x08 #define USBFS_SR_SESS_END 0x04 #define USBFS_SR_SESS_VLD 0x02 #define USBFS_SR_VBUS_VLD 0x01 /* R8_UDEV_CTRL */ #define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable #define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level #define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level #define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed #define USBFS_UD_GP_BIT 0x02 // general purpose bit #define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable /* R8_UEP4_1_MOD */ #define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) #define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) #define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 #define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) #define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) #define USBFS_UEP4_BUF_MOD 0x01 /* R8_UEP2_3_MOD */ #define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) #define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) #define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 #define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) #define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) #define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 /* R8_UEP5_6_MOD */ #define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) #define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) #define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 #define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) #define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) #define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 /* R8_UEP7_MOD */ #define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) #define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) #define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 /* R8_UEPn_TX_CTRL */ #define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle #define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 #define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) #define USBFS_UEP_T_RES_ACK 0x00 #define USBFS_UEP_T_RES_NONE 0x01 #define USBFS_UEP_T_RES_NAK 0x02 #define USBFS_UEP_T_RES_STALL 0x03 // bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) // 00: DATA0 or DATA1 then expecting ACK (ready) // 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions // 10: NAK (busy) // 11: STALL (error) // host aux setup /* R8_UEPn_RX_CTRL, n=0-7 */ #define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle #define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 #define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) #define USBFS_UEP_R_RES_ACK 0x00 #define USBFS_UEP_R_RES_NONE 0x01 #define USBFS_UEP_R_RES_NAK 0x02 #define USBFS_UEP_R_RES_STALL 0x03 // RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) // 00: ACK (ready) // 01: no response, time out to host, for non-zero endpoint isochronous transactions // 10: NAK (busy) // 11: STALL (error) /* R8_UHOST_CTRL */ #define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable #define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level #define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level #define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed #define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset #define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached /* R32_UH_EP_MOD */ #define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal #define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint // bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA // 0 x: disable endpoint and disable buffer // 1 0: 64 bytes buffer for transmittal (OUT endpoint) // 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes #define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving #define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint // bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA // 0 x: disable endpoint and disable buffer // 1 0: 64 bytes buffer for receiving (IN endpoint) // 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes /* R16_UH_SETUP */ #define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub #define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable /* R8_UH_EP_PID */ #define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer #define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer /* R8_UH_RX_CTRL */ #define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle #define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 #define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions /* R8_UH_TX_CTRL */ #define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle #define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 #define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions /* ch32v00x_wwdg.h -----------------------------------------------------------*/ /* WWDG_Prescaler */ #define WWDG_Prescaler_1 ((uint32_t)0x00000000) #define WWDG_Prescaler_2 ((uint32_t)0x00000080) #define WWDG_Prescaler_4 ((uint32_t)0x00000100) #define WWDG_Prescaler_8 ((uint32_t)0x00000180) /* ch32h417_hsadc.h -----------------------------------------------------------*/ /* HSADC_First_Conversion_Cycle */ #define HSADC_First_Conversion_Cycle_8 ((uint32_t)0x00000000) #define HSADC_First_Conversion_Cycle_9 ((uint32_t)0x00000020) #define HSADC_First_Conversion_Cycle_10 ((uint32_t)0x00000040) #define HSADC_First_Conversion_Cycle_11 ((uint32_t)0x00000060) /* HSADC_data_size */ #define HSADC_DataSize_16b ((uint32_t)0x00000000) #define HSADC_DataSize_8b ((uint32_t)0x00000080) /* HSADC_channels */ #define HSADC_Channel_0 ((uint8_t)0x00) #define HSADC_Channel_1 ((uint8_t)0x01) #define HSADC_Channel_2 ((uint8_t)0x02) #define HSADC_Channel_3 ((uint8_t)0x03) #define HSADC_Channel_4 ((uint8_t)0x04) #define HSADC_Channel_5 ((uint8_t)0x05) #define HSADC_Channel_6 ((uint8_t)0x06) /* HSADC_interrupts_definition */ #define HSADC_IT_EOC ((uint16_t)0x0100) #define HSADC_IT_DMAEnd ((uint16_t)0x0200) #define HSADC_IT_BurstEnd ((uint16_t)0x0400) /* HSADC_flags_definition */ #define HSADC_FLAG_EOC ((uint16_t)0x0001) #define HSADC_FLAG_DMAEnd ((uint16_t)0x0002) #define HSADC_FLAG_BurstEnd ((uint16_t)0x0004) #define HSADC_FLAG_RXNE ((uint16_t)0x0008) #define HSADC_FLAG_DualBufferAddr1 ((uint16_t)0x0010) #define HSADC_FLAG_FIFO_NE ((uint16_t)0x0100) #define HSADC_FLAG_FIFO_Full ((uint16_t)0x0200) #define HSADC_FLAG_FIFO_OV ((uint16_t)0x0400) /* ch32h417_hsem.h -----------------------------------------------------------*/ /* HSEM_Core_ID */ #define HSEM_Core_ID_V3F ((uint32_t)0x00000000) #define HSEM_Core_ID_V5F ((uint32_t)0x00000100) /* ch32h417_i3c.h -----------------------------------------------------------*/ /* I3C_SDAHoldTime*/ #define I3C_SDAHoldTime_0_5 ((uint32_t)0x00000000) #define I3C_SDAHoldTime_1_5 ((uint32_t)0x10000000) /* I3C_WaitTime */ #define I3C_WaitTime_State_0 ((uint32_t)0x00000000) #define I3C_WaitTime_State_1 ((uint32_t)0x00000100) #define I3C_WaitTime_State_2 ((uint32_t)0x00000200) #define I3C_WaitTime_State_3 ((uint32_t)0x00000300) /* I3C_IBIPayloadSize */ #define I3C_IBIPayloadSize_None ((uint32_t)0x00000000) #define I3C_IBIPayloadSize_1B ((uint32_t)0x00010000) #define I3C_IBIPayloadSize_2B ((uint32_t)0x00020000) #define I3C_IBIPayloadSize_3B ((uint32_t)0x00030000) #define I3C_IBIPayloadSize_4B ((uint32_t)0x00040000) /* I3C_DataTurnAroundDuration */ #define I3C_DataTurnAroundDuration_Mode0 ((uint32_t)0x00000000) #define I3C_DataTurnAroundDuration_Mode1 ((uint32_t)0x01000000) /* I3C_MaxDataSpeed */ #define I3C_MaxDataSpeed_Format_Mode0 ((uint32_t)0x00000000) #define I3C_MaxDataSpeed_Format_Mode1 ((uint32_t)0x00000100) #define I3C_MaxDataSpeed_Format_Mode2 ((uint32_t)0x00000200) #define I3C_MaxDataSpeed_Format_Mode3 ((uint32_t)0x00000300) /* I3C_HandOffActivityState */ #define I3C_HandOffActivityState_0 ((uint32_t)0x00000000) #define I3C_HandOffActivityState_1 ((uint32_t)0x00000001) #define I3C_HandOffActivityState_2 ((uint32_t)0x00000002) #define I3C_HandOffActivityState_3 ((uint32_t)0x00000003) /* I3C_DeviceIndex */ #define I3C_DeviceIndex_1 ((uint32_t)0x00000001) #define I3C_DeviceIndex_2 ((uint32_t)0x00000002) #define I3C_DeviceIndex_3 ((uint32_t)0x00000003) #define I3C_DeviceIndex_4 ((uint32_t)0x00000004) /* I3C_Direction */ #define I3C_Direction_WR ((uint32_t)0x00000000) #define I3C_Direction_RD ((uint32_t)0x00010000) /* I3C_CONTROLLER MessageType */ #define I3C_CONTROLLER_MTYPE_RELEASE ((uint32_t)0x00000000) #define I3C_CONTROLLER_MTYPE_HEADER I3C_CTLR_MTYPE_0 #define I3C_CONTROLLER_MTYPE_PRIVATE I3C_CTLR_MTYPE_1 #define I3C_CONTROLLER_MTYPE_DIRECT (I3C_CTLR_MTYPE_1 | I3C_CTLR_MTYPE_0) #define I3C_CONTROLLER_MTYPE_LEGACY_I2C I3C_CTLR_MTYPE_2 #define I3C_CONTROLLER_MTYPE_CCC (I3C_CTLR_MTYPE_2 | I3C_CTLR_MTYPE_1) /* I3C_EndMode */ #define I3C_GENERATE_STOP I3C_CTLR_MEND #define I3C_GENERATE_RESTART ((uint32_t)0x00000000) /* I3C_TARGET_MessageType */ #define I3C_TARGET_MTYPE_HOT_JOIN I3C_CTLR_MTYPE_3 #define I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CTLR_MTYPE_3 | I3C_CTLR_MTYPE_0) #define I3C_TARGET_MTYPE_IBI (I3C_CTLR_MTYPE_3 | I3C_CTLR_MTYPE_1) /* I3C_PeripheralMode */ #define PeripheralMode_CONTROLLER ((uint32_t)0x00000000) #define PeripheralMode_TARGET ((uint32_t)0x00000002) /* I3C_RX_FIFO_THRESHOLD */ #define I3C_RXFIFO_THRESHOLD_1_4 ((uint32_t)0x00000000) #define I3C_RXFIFO_THRESHOLD_4_4 I3C_CFGR_RXTHRES /* I3C_TX_FIFO_THRESHOLD */ #define I3C_TXFIFO_THRESHOLD_1_4 ((uint32_t)0x00000000) #define I3C_TXFIFO_THRESHOLD_4_4 I3C_CFGR_TXTHRES /* I3C_CONTROL_FIFO_STATE */ #define I3C_CONTROLFIFO_DISABLE ((uint32_t)0x00000000) #define I3C_CONTROLFIFO_ENABLE I3C_CFGR_TMODE /* I3C_STATUS_FIFO_STATE */ #define I3C_STATUSFIFO_DISABLE ((uint32_t)0x00000000) #define I3C_STATUSFIFO_ENABLE I3C_CFGR_SMODE /* I3C_flags_definition */ #define I3C_FLAG_CFEF ((uint32_t)0x00000001) #define I3C_FLAG_TXFEF ((uint32_t)0x00000002) #define I3C_FLAG_CFNFF ((uint32_t)0x00000004) #define I3C_FLAG_SFNEF ((uint32_t)0x00000008) #define I3C_FLAG_TXFNFF ((uint32_t)0x00000010) #define I3C_FLAG_RXFNEF ((uint32_t)0x00000020) #define I3C_FLAG_TXLASTF ((uint32_t)0x00000040) #define I3C_FLAG_RXLASTF ((uint32_t)0x00000080) #define I3C_FLAG_FCF ((uint32_t)0x00000200) #define I3C_FLAG_RXTGTENDF ((uint32_t)0x00000400) #define I3C_FLAG_ERRF ((uint32_t)0x00000800) #define I3C_FLAG_IBIF ((uint32_t)0x00008000) #define I3C_FLAG_IBIENDF ((uint32_t)0x00010000) #define I3C_FLAG_CRF ((uint32_t)0x00020000) #define I3C_FLAG_CRUPDF ((uint32_t)0x00040000) #define I3C_FLAG_HJF ((uint32_t)0x00080000) #define I3C_FLAG_WKPF ((uint32_t)0x00200000) #define I3C_FLAG_GETF ((uint32_t)0x00400000) #define I3C_FLAG_STAF ((uint32_t)0x00800000) #define I3C_FLAG_DAUPDF ((uint32_t)0x01000000) #define I3C_FLAG_MWLUPDF ((uint32_t)0x02000000) #define I3C_FLAG_MRLUPDF ((uint32_t)0x04000000) #define I3C_FLAG_RSTF ((uint32_t)0x08000000) #define I3C_FLAG_ASUPDF ((uint32_t)0x10000000) #define I3C_FLAG_INTUPDF ((uint32_t)0x20000000) #define I3C_FLAG_DEFF ((uint32_t)0x40000000) #define I3C_FLAG_GRPF ((uint32_t)0x80000000) /* I3C_interrupts_definition */ #define I3C_IT_CFNFIE ((uint32_t)0x00000004) #define I3C_IT_SFNEIE ((uint32_t)0x00000008) #define I3C_IT_TXFNEIE ((uint32_t)0x00000010) #define I3C_IT_RXFNEIE ((uint32_t)0x00000020) #define I3C_IT_FCIE ((uint32_t)0x00000200) #define I3C_IT_RXTGTENDIE ((uint32_t)0x00000400) #define I3C_IT_ERRIE ((uint32_t)0x00000800) #define I3C_IT_IBIIE ((uint32_t)0x00008000) #define I3C_IT_IBIENDIE ((uint32_t)0x00010000) #define I3C_IT_CRIE ((uint32_t)0x00020000) #define I3C_IT_HJIE ((uint32_t)0x00080000) #define I3C_IT_CRUPDIE ((uint32_t)0x00040000) #define I3C_IT_WKPIE ((uint32_t)0x00200000) #define I3C_IT_GETIE ((uint32_t)0x00400000) #define I3C_IT_STAIE ((uint32_t)0x00800000) #define I3C_IT_DAUPDIE ((uint32_t)0x01000000) #define I3C_IT_MWLUPDIE ((uint32_t)0x02000000) #define I3C_IT_MRLUPDIE ((uint32_t)0x04000000) #define I3C_IT_RSTIE ((uint32_t)0x08000000) #define I3C_IT_ASUPDIE ((uint32_t)0x10000000) #define I3C_IT_INTUPDIE ((uint32_t)0x20000000) #define I3C_IT_DEFIE ((uint32_t)0x40000000) #define I3C_IT_GRPIE ((uint32_t)0x80000000) /* I3C_ERROR */ #define I3C_ERROR_CE0 ((uint32_t)0x00000000) #define I3C_ERROR_CE1 ((uint32_t)0x00000001) #define I3C_ERROR_CE2 ((uint32_t)0x00000002) #define I3C_ERROR_CE3 ((uint32_t)0x00000003) #define I3C_ERROR_TE0 ((uint32_t)0x00000008) #define I3C_ERROR_TE1 ((uint32_t)0x00000009) #define I3C_ERROR_TE2 ((uint32_t)0x0000000A) #define I3C_ERROR_TE3 ((uint32_t)0x0000000B) #define I3C_ERROR_TE4 ((uint32_t)0x0000000C) #define I3C_ERROR_TE5 ((uint32_t)0x0000000D) #define I3C_ERROR_TE6 ((uint32_t)0x0000000E) #define I3C_ERROR_PERR ((uint32_t)0x00000010) #define I3C_ERROR_STALL ((uint32_t)0x00000020) #define I3C_ERROR_DOVR ((uint32_t)0x00000040) #define I3C_ERROR_COVR ((uint32_t)0x00000080) #define I3C_ERROR_ADDRESS_NACK ((uint32_t)0x00000100) #define I3C_ERROR_DATA_NACK ((uint32_t)0x00000200) #define I3C_ERROR_DATA_HAND_OFF ((uint32_t)0x00000400) /* ch32h417_lptim.h -----------------------------------------------------------*/ /* LPTIM_Clock_Source */ #define LPTIM_ClockSource_In ((uint32_t)0x00000000) #define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) /* LPTIM_ClockPolarity */ #define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) #define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) #define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) /* LPTIM_ClockPrescalerTime */ #define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) #define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) #define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) #define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) /* LPTIM_TriggerSampleTime */ #define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) #define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) #define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) #define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) /* LPTIM_ClockPrescaler */ #define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) #define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) #define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) #define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) #define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) #define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) #define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) #define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) /* LPTIM_TriggerSource */ #define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) #define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) #define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) /* LPTIM_ExTriggerPolarity */ #define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) #define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) #define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) #define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) /* LPTIM_OutputPolarity */ #define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) #define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) /* LPTIM_UpdateMode */ #define LPTIM_UpdateMode0 ((uint32_t)0x00000000) #define LPTIM_UpdateMode1 ((uint32_t)0x00400000) /* LPTIM_CountSource */ #define LPTIM_CountSource_Internal ((uint32_t)0x00000000) #define LPTIM_CountSource_External ((uint32_t)0x00800000) /* LPTIM_InClockSource */ #define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) #define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) #define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) #define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) /* LPTIM_Flag_Definition */ #define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) #define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) #define LPTIM_FLAG_UP ((uint32_t)0x00000020) #define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) #define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) #define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) #define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) #define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) /* LPTIM_Interrupts_Definition */ #define LPTIM_IT_DOWN ((uint32_t)0x00000040) #define LPTIM_IT_UP ((uint32_t)0x00000020) #define LPTIM_IT_ARROK ((uint32_t)0x00000010) #define LPTIM_IT_CMPOK ((uint32_t)0x00000008) #define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) #define LPTIM_IT_ARRM ((uint32_t)0x00000002) #define LPTIM_IT_CMPM ((uint32_t)0x00000001) /* ch32h417_ltdc.h -----------------------------------------------------------*/ /* LTDC_HSPolarity */ #define LTDC_HSPolarity_AL ((uint32_t)0x00000000) #define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /* LTDC_VSPolarity */ #define LTDC_VSPolarity_AL ((uint32_t)0x00000000) #define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /* LTDC_DEPolarity */ #define LTDC_DEPolarity_AL ((uint32_t)0x00000000) #define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /* LTDC_PCPolarity */ #define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) #define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /* LTDC_Reload */ #define LTDC_IMReload LTDC_SRCR_IMR #define LTDC_VBReload LTDC_SRCR_VBR /* LTDC_Position */ #define LTDC_POS_CY LTDC_CPSR_CYPOS #define LTDC_POS_CX LTDC_CPSR_CXPOS /* LTDC_CurrentStatus */ #define LTDC_CD_VDES LTDC_CDSR_VDES #define LTDC_CD_HDES LTDC_CDSR_HDES #define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS #define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS /* LTDC_Interrupts_definition */ #define LTDC_IT_LI LTDC_IER_LIE #define LTDC_IT_FU LTDC_IER_FUIE #define LTDC_IT_RR LTDC_IER_RRIE /* LTDC_Flag_definition */ #define LTDC_FLAG_LI LTDC_ISR_LIF #define LTDC_FLAG_FU LTDC_ISR_FUIF #define LTDC_FLAG_RR LTDC_ISR_RRIF /* LTDC_Pixelformat */ #define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) #define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) #define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) #define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) #define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) #define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) #define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) #define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) /* LTDC_BlendingFactor1 */ #define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) #define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) /* LTDC_BlendingFactor2 */ #define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) #define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) /* ch32h417_pioc.h -----------------------------------------------------------*/ // Register Bit Attribute / Bit Access Type // RO: Read Only (internal change) // RW: Read / Write // Attribute: master/PIOC /* Register name rule: R32_* for 32 bits register (UINT32,ULONG) R16_* for 16 bits register (UINT16,USHORT) R8_* for 8 bits register (UINT8,UCHAR) RB_* for bit or bit mask of 8 bit register */ /* ********************************************************************************************************************* */ #define PIOC_SRAM_BASE (0x50040000) // PIOC code RAM base address #define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address #define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR #define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address #define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count #define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit #define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag #define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag #define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset #define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset #define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM #define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2 #define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1 #define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0 #define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value #define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config #define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle #define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output #define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1 #define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2 #define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode //#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3 //#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2 //#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1 //#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0 //#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable //#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable #define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction #define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction #define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output #define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input #define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received #define RB_PORT_IN1 0x20 // RO/RO, IO1 port input #define RB_PORT_IN0 0x10 // RO/RO, IO0 port input #define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input #define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input #define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output #define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output #define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control #define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config #define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect) #define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD #define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR #define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0 #define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0 #define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0 #define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0 #define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0 #define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only #define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only #define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange #define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3 #define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0 #define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1 #define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2 #define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3 #define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7 #define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4 #define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5 #define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6 #define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7 #define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11 #define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8 #define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9 #define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10 #define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11 #define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15 #define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12 #define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13 #define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14 #define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15 #define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19 #define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16 #define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17 #define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18 #define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19 #define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23 #define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20 #define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21 #define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22 #define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23 #define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27 #define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24 #define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25 #define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26 #define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27 #define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31 #define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28 #define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29 #define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30 #define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31 /* ******************************************************************************************************* */ /* PIOC Registers */ typedef struct { uint32_t RESERVED00; union { __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR struct { __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value } ; } ; union { __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config struct { __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2 __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output } ; } ; uint32_t RESERVED0C; uint32_t RESERVED10; uint32_t RESERVED14; uint32_t RESERVED18; union { __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control struct { __IO uint8_t D8_SYS_CFG; // RW/RW, port config __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange } ; } ; union { __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3 struct { __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0 __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1 __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2 __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3 } ; __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1 } ; union { __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7 struct { __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4 __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5 __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6 __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7 } ; } ; union { __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11 struct { __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8 __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9 __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10 __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11 } ; } ; union { __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15 struct { __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12 __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13 __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14 __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15 } ; } ; union { __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19 struct { __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16 __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17 __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18 __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19 } ; } ; union { __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23 struct { __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20 __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21 __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22 __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23 } ; } ; union { __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27 struct { __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24 __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25 __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26 __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27 } ; } ; union { __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31 struct { __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28 __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29 __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30 __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31 } ; } ; } PIOC_TypeDef; #define PIOC ((PIOC_TypeDef *)PIOC_BASE) /* ch32h417_qspi.h -----------------------------------------------------------*/ /* QSPI_Clock_Mode */ #define QSPI_CKMode_Mode0 ((uint32_t)0x00000000) #define QSPI_CKMode_Mode3 ((uint32_t)QSPI_DCR_CKMODE) /* QSPI_ChipSelectHighTime */ #define QSPI_CSHTime_1Cycle ((uint32_t)0x00000000) #define QSPI_CSHTime_2Cycle ((uint32_t)QSPI_DCR_CSHT_0) #define QSPI_CSHTime_3Cycle ((uint32_t)QSPI_DCR_CSHT_1) #define QSPI_CSHTime_4Cycle ((uint32_t)QSPI_DCR_CSHT_0 | QSPI_DCR_CSHT_1) #define QSPI_CSHTime_5Cycle ((uint32_t)QSPI_DCR_CSHT_2) #define QSPI_CSHTime_6Cycle ((uint32_t)QSPI_DCR_CSHT_2 | QSPI_DCR_CSHT_0) #define QSPI_CSHTime_7Cycle ((uint32_t)QSPI_DCR_CSHT_2 | QSPI_DCR_CSHT_1) #define QSPI_CSHTime_8Cycle ((uint32_t)QSPI_DCR_CSHT) /* QSPI_Fash_Select */ #define QSPI_FSelect_1 ((uint32_t)0x00000000) #define QSPI_FSelect_2 ((uint32_t)QSPI_CR_FSEL) /* QSPI_Dual_Flash */ #define QSPI_DFlash_Disable ((uint32_t)0x00000000) #define QSPI_DFlash_Enable ((uint32_t)QSPI_CR_DFM) /* QSPI_ComConfig_Functional_Mode */ #define QSPI_ComConfig_FMode_Indirect_Write ((uint32_t)0x00000000) #define QSPI_ComConfig_FMode_Indirect_Read ((uint32_t)QSPI_CCR_FMODE_0) #define QSPI_ComConfig_FMode_Auto_Polling ((uint32_t)QSPI_CCR_FMODE_1) #define QSPI_ComConfig_FMode_Memory_Mapped ((uint32_t)QSPI_CCR_FMODE) /* QSPI_ComConfig_SendInstructionOnlyOnceMode */ #define QSPI_ComConfig_SIOOMode_Disable ((uint32_t)0x00000000) #define QSPI_ComConfig_SIOOMode_Enable ((uint32_t)QSPI_CCR_SIOO) /* QSPI_ComConfig_DataMode */ #define QSPI_ComConfig_DMode_NoData ((uint32_t)0x00000000) #define QSPI_ComConfig_DMode_1Line ((uint32_t)QSPI_CCR_DMODE_0) #define QSPI_ComConfig_DMode_2Line ((uint32_t)QSPI_CCR_DMODE_1) #define QSPI_ComConfig_DMode_4Line ((uint32_t)QSPI_CCR_DMODE) /* QSPI_ComConfig_AlternateBytesSize */ #define QSPI_ComConfig_ABSize_8bit ((uint32_t)0x00000000) #define QSPI_ComConfig_ABSize_16bit ((uint32_t)QSPI_CCR_ABSIZE_0) #define QSPI_ComConfig_ABSize_24bit ((uint32_t)QSPI_CCR_ABSIZE_1) #define QSPI_ComConfig_ABSize_32bit ((uint32_t)QSPI_CCR_ABSIZE) /* QSPI_ComConfig_AlternateBytesMode */ #define QSPI_ComConfig_ABMode_NoAlternateByte ((uint32_t)0x00000000) #define QSPI_ComConfig_ABMode_1Line ((uint32_t)QSPI_CCR_ABMODE_0) #define QSPI_ComConfig_ABMode_2Line ((uint32_t)QSPI_CCR_ABMODE_1) #define QSPI_ComConfig_ABMode_4Line ((uint32_t)QSPI_CCR_ABMODE) /* QSPI_ComConfig_AddressSize */ #define QSPI_ComConfig_ADSize_8bit ((uint32_t)0x00000000) #define QSPI_ComConfig_ADSize_16bit ((uint32_t)QSPI_CCR_ADSIZE_0) #define QSPI_ComConfig_ADSize_24bit ((uint32_t)QSPI_CCR_ADSIZE_1) #define QSPI_ComConfig_ADSize_32bit ((uint32_t)QSPI_CCR_ADSIZE) /* QSPI_ComConfig_AddressMode */ #define QSPI_ComConfig_ADMode_NoAddress ((uint32_t)0x00000000) #define QSPI_ComConfig_ADMode_1Line ((uint32_t)QSPI_CCR_ADMODE_0) #define QSPI_ComConfig_ADMode_2Line ((uint32_t)QSPI_CCR_ADMODE_1) #define QSPI_ComConfig_ADMode_4Line ((uint32_t)QSPI_CCR_ADMODE) /* QSPI_ComConfig_InstructionMode */ #define QSPI_ComConfig_IMode_NoInstruction ((uint32_t)0x00000000) #define QSPI_ComConfig_IMode_1Line ((uint32_t)QSPI_CCR_IMODE_0) #define QSPI_ComConfig_IMode_2Line ((uint32_t)QSPI_CCR_IMODE_1) #define QSPI_ComConfig_IMode_4Line ((uint32_t)QSPI_CCR_IMODE) /* QSPI_Interrupts_definition */ #define QSPI_IT_TO (uint32_t)(QSPI_CR_TOIE | QSPI_SR_TOF) #define QSPI_IT_SM (uint32_t)(QSPI_CR_SMIE | QSPI_SR_SMF) #define QSPI_IT_FT (uint32_t)(QSPI_CR_FTIE | QSPI_SR_FTF) #define QSPI_IT_TC (uint32_t)(QSPI_CR_TCIE | QSPI_SR_TCF) #define QSPI_IT_TE (uint32_t)(QSPI_CR_TEIE | QSPI_SR_TEF) /* QSPI_Flags_definition */ #define QSPI_FLAG_TO QSPI_SR_TOF #define QSPI_FLAG_SM QSPI_SR_SMF #define QSPI_FLAG_FT QSPI_SR_FTF #define QSPI_FLAG_TC QSPI_SR_TCF #define QSPI_FLAG_TE QSPI_SR_TEF #define QSPI_FLAG_BUSY QSPI_SR_BUSY #define QSPI_FLAG_IDLE QSPI_SR_IDLEF /* QSPI_Polling_Match_Mode */ #define QSPI_PMM_AND ((uint32_t)0x00000000) #define QSPI_PMM_OR ((uint32_t)QSPI_CR_PMM) /* QSPI_SIOXEN */ #define QSPI_SIOXEN ((uint32_t)0x00002000) /* ch32h417_sai.h -----------------------------------------------------------*/ /* SAI_Block_Mode */ #define SAI_Mode_MasterTx ((uint32_t)0x00000000) #define SAI_Mode_MasterRx ((uint32_t)0x00000001) #define SAI_Mode_SlaveTx ((uint32_t)0x00000002) #define SAI_Mode_SlaveRx ((uint32_t)0x00000003) /* SAI_Block_Protocol */ #define SAI_Free_Protocol ((uint32_t)0x00000000) #define SAI_SPDIF_Protocol ((uint32_t)SAI_CFGR1_PRTCFG_0) #define SAI_AC97_Protocol ((uint32_t)SAI_CFGR1_PRTCFG_1) /* SAI_Block_Data_Size */ #define SAI_DataSize_8b ((uint32_t)0x00000040) #define SAI_DataSize_10b ((uint32_t)0x00000060) #define SAI_DataSize_16b ((uint32_t)0x00000080) #define SAI_DataSize_20b ((uint32_t)0x000000A0) #define SAI_DataSize_24b ((uint32_t)0x000000C0) #define SAI_DataSize_32b ((uint32_t)0x000000E0) /* SAI_Block_MSB_LSB_transmission */ #define SAI_FirstBit_MSB ((uint32_t)0x00000000) #define SAI_FirstBit_LSB ((uint32_t)SAI_CFGR1_LSBFIRST) /* SAI_Block_Clock_Strobing */ #define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) #define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_CFGR1_CKSTR) /* SAI_Block_Synchronization */ #define SAI_Asynchronous ((uint32_t)0x00000000) #define SAI_Synchronous ((uint32_t)SAI_CFGR1_SYNCEN_0) /* SAI_Block_NoDivider */ #define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) #define SAI_MasterDivider_Disabled ((uint32_t)SAI_CFGR1_NODIV) /* SAI_Block_FS_Definition */ #define SAI_FS_StartFrame ((uint32_t)0x00000000) #define I2S_FS_ChannelIdentification ((uint32_t)SAI_FRCR_FSDEF) /* SAI_Block_FS_Polarity */ #define SAI_FS_ActiveLow ((uint32_t)0x00000000) #define SAI_FS_ActiveHigh ((uint32_t)SAI_FRCR_FSPOL) /* SAI_Block_FS_Offset */ #define SAI_FS_FirstBit ((uint32_t)0x00000000) #define SAI_FS_BeforeFirstBit ((uint32_t)SAI_FRCR_FSOFF) /* SAI_Block_Slot_Size */ #define SAI_SlotSize_DataSize ((uint32_t)0x00000000) #define SAI_SlotSize_16b ((uint32_t)0x00000040) #define SAI_SlotSize_32b ((uint32_t)0x00000080) /* SAI_Block_Slot_Active */ #define SAI_Slot_NotActive ((uint32_t)0x00000000) #define SAI_SlotActive_0 ((uint32_t)0x00010000) #define SAI_SlotActive_1 ((uint32_t)0x00020000) #define SAI_SlotActive_2 ((uint32_t)0x00040000) #define SAI_SlotActive_3 ((uint32_t)0x00080000) #define SAI_SlotActive_4 ((uint32_t)0x00100000) #define SAI_SlotActive_5 ((uint32_t)0x00200000) #define SAI_SlotActive_6 ((uint32_t)0x00400000) #define SAI_SlotActive_7 ((uint32_t)0x00800000) #define SAI_SlotActive_8 ((uint32_t)0x01000000) #define SAI_SlotActive_9 ((uint32_t)0x02000000) #define SAI_SlotActive_10 ((uint32_t)0x04000000) #define SAI_SlotActive_11 ((uint32_t)0x08000000) #define SAI_SlotActive_12 ((uint32_t)0x10000000) #define SAI_SlotActive_13 ((uint32_t)0x20000000) #define SAI_SlotActive_14 ((uint32_t)0x40000000) #define SAI_SlotActive_15 ((uint32_t)0x80000000) #define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) /* SAI_Mono_Streo_Mode */ #define SAI_MonoMode ((uint32_t)SAI_CFGR1_MONO) #define SAI_StreoMode ((uint32_t)0x00000000) /* SAI_TRIState_Management */ #define SAI_Output_NotReleased ((uint32_t)0x00000000) #define SAI_Output_Released ((uint32_t)SAI_CFGR2_TRIS) /* SAI_Block_Fifo_Threshold */ #define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) #define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) #define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) #define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) #define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) /* SAI_Block_Companding_Mode */ #define SAI_NoCompanding ((uint32_t)0x00000000) #define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) #define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) #define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) #define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) /* SAI_Block_Mute_Value */ #define SAI_ZeroValue ((uint32_t)0x00000000) #define SAI_LastSentValue ((uint32_t)SAI_CFGR2_MUTEVAL) /* SAI_Block_Interrupts_Definition */ #define SAI_IT_OVRUDR ((uint32_t)SAI_INTENR_OVRUDRIE) #define SAI_IT_MUTEDET ((uint32_t)SAI_INTENR_MUTEDETIE) #define SAI_IT_WCKCFG ((uint32_t)SAI_INTENR_WCKCFGIE) #define SAI_IT_FREQ ((uint32_t)SAI_INTENR_FREQIE) #define SAI_IT_CNRDY ((uint32_t)SAI_INTENR_CNRDYIE) #define SAI_IT_AFSDET ((uint32_t)SAI_INTENR_AFSDETIE) #define SAI_IT_LFSDET ((uint32_t)SAI_INTENR_LFSDETIE) /* SAI_Block_Flags_Definition */ #define SAI_FLAG_OVRUDR ((uint32_t)SAI_SR_OVRUDR) #define SAI_FLAG_MUTEDET ((uint32_t)SAI_SR_MUTEDET) #define SAI_FLAG_WCKCFG ((uint32_t)SAI_SR_WCKCFG) #define SAI_FLAG_FREQ ((uint32_t)SAI_SR_FREQ) #define SAI_FLAG_CNRDY ((uint32_t)SAI_SR_CNRDY) #define SAI_FLAG_AFSDET ((uint32_t)SAI_SR_AFSDET) #define SAI_FLAG_LFSDET ((uint32_t)SAI_SR_LFSDET) /* SAI_Block_Fifo_Status_Level */ #define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) #define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) #define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) #define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) #define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) #define SAI_FIFOStatus_Full ((uint32_t)0x00050000) /* ch32h417_sdmmc.h -----------------------------------------------------------*/ /* SDMMC_Mode */ #define SDMMC_Mode_Host ((uint16_t)0x00000000) #define SDMMC_Mode_Slave ((uint16_t)SDMMC_SLV_MODE) /* SDMMC_PhaseInv */ #define SDMMC_Phase_No_Inverse ((uint16_t)0x00000000) #define SDMMC_Phase_Inverse ((uint16_t)SDMMC_PHASEINV) /* SDMMC_ClockSpeed */ #define SDMMC_ClockSpeed_Low ((uint16_t)0x00000000) #define SDMMC_ClockSpeed_High ((uint16_t)(SDMMC_CLKMode)) /* SDMMC_BusWidth */ #define SDMMC_BusWidth_1 ((uint32_t)0x00000000) #define SDMMC_BusWidth_4 ((uint32_t)0x00000001) #define SDMMC_BusWidth_8 ((uint32_t)0x00000002) /* SDMMC_ClockEdge */ #define SDMMC_SampleClock_Rising ((uint8_t)0x00000000) #define SDMMC_SampleClock_Falling ((uint8_t)SDMMC_NEGSMP) /* SDMMC_RespExpect */ #define SDMMC_Resp_NONE ((uint16_t)0x0000) #define SDMMC_Resp_136 ((uint16_t)0x00100) #define SDMMC_Resp_48 ((uint16_t)0x00200) #define SDMMC_Resp_R1b ((uint16_t)0x00300) /* TranMode_Direction */ #define SDMMC_TranDir_Receive ((uint32_t)0x00000000) #define SDMMC_TranDir_Send ((uint32_t)SDMMC_DMA_DIR) /* DDR_ClockSW_Mode */ #define SDMMC_DDR_ClockSW_Mode_In ((uint32_t)0x00000000) #define SDMMC_DDR_ClockSW_Mode_Auto ((uint32_t)0x00080000) #define SDMMC_DDR_ClockSW_Mode_Force ((uint32_t)0x00100000) /* SDMMC_Flags */ #define SDMMC_FLAG_SLV_BUF_RELEASE ((uint16_t)0x0400) #define SDMMC_FLAG_SDIOINT ((uint16_t)0x0200) #define SDMMC_FLAG_FIFO_OV ((uint16_t)0x0100) #define SDMMC_FLAG_BKGAP ((uint16_t)0x0080) #define SDMMC_FLAG_TRANDONE ((uint16_t)0x0040) #define SDMMC_FLAG_TRANERR ((uint16_t)0x0020) #define SDMMC_FLAG_DATTMO ((uint16_t)0x0010) #define SDMMC_FLAG_CMDDONE ((uint16_t)0x0008) #define SDMMC_FLAG_REIDX_ER ((uint16_t)0x0004) #define SDMMC_FLAG_RECRC_WR ((uint16_t)0x0002) #define SDMMC_FLAG_RE_TMOUT ((uint16_t)0x0001) /* SDMMC_Interrupt_Sources */ #define SDMMC_IT_SDIOINT ((uint16_t)0x0200) #define SDMMC_IT_FIFO_OV ((uint16_t)0x0100) #define SDMMC_IT_BKGAP ((uint16_t)0x0080) #define SDMMC_IT_TRANDONE ((uint16_t)0x0040) #define SDMMC_IT_TRANERR ((uint16_t)0x0020) #define SDMMC_IT_DATTMO ((uint16_t)0x0010) #define SDMMC_IT_CMDDONE ((uint16_t)0x0008) #define SDMMC_IT_REIDX_ER ((uint16_t)0x0004) #define SDMMC_IT_RECRC_WR ((uint16_t)0x0002) #define SDMMC_IT_RE_TMOUT ((uint16_t)0x0001) /* ch32h417_swpmi.h -----------------------------------------------------------*/ /* Tx_Buffering_Mode */ #define SWPMI_TxMode_Buffering_None ((uint32_t)0x0) #define SWPMI_TxMode_Buffering_Single ((uint32_t)0x2) #define SWPMI_TxMode_Buffering_Multi ((uint32_t)0xA) /* Rx_Buffering_Mode */ #define SWPMI_RxMode_Buffering_None ((uint32_t)0x0) #define SWPMI_RxMode_Buffering_Single ((uint32_t)0x1) #define SWPMI_RxMode_Buffering_Multi ((uint32_t)0x5) /* SWPMI interrupts definition */ #define SWPMI_IT_RXBF ((uint16_t)0x0001) #define SWPMI_IT_TXBE ((uint16_t)0x0002) #define SWPMI_IT_RXBER ((uint16_t)0x0004) #define SWPMI_IT_RXOVR ((uint16_t)0x0008) #define SWPMI_IT_TXUNR ((uint16_t)0x0010) #define SWPMI_IT_RXNE ((uint16_t)0x0020) #define SWPMI_IT_TXE ((uint16_t)0x0040) #define SWPMI_IT_TC ((uint16_t)0x0080) #define SWPMI_IT_SR ((uint16_t)0x0100) #define SWPMI_IT_RDY ((uint16_t)0x0800) /* SWPMI flags definition */ #define SWPMI_FLAG_RXBF ((uint16_t)0x0001) #define SWPMI_FLAG_TXBE ((uint16_t)0x0002) #define SWPMI_FLAG_RXBER ((uint16_t)0x0004) #define SWPMI_FLAG_RXOVR ((uint16_t)0x0008) #define SWPMI_FLAG_TXUNR ((uint16_t)0x0010) #define SWPMI_FLAG_RXNE ((uint16_t)0x0020) #define SWPMI_FLAG_TXE ((uint16_t)0x0040) #define SWPMI_FLAG_TC ((uint16_t)0x0080) #define SWPMI_FLAG_SR ((uint16_t)0x0100) #define SWPMI_FLAG_SUSP ((uint16_t)0x0200) #define SWPMI_FLAG_DEACT ((uint16_t)0x0400) #define SWPMI_FLAG_RDY ((uint16_t)0x0800) /* ch32h417_usbpd.h -----------------------------------------------------------*/ /* Register Bit Definition */ /* USBPD->CONFIG */ #define PD_FILT_ED (1<<0) /* PD pin input filter enable */ #define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ #define CC_SEL (1<<2) /* Select PD communication port */ #define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ #define PD_RST_EN (1<<4) /* PD mode reset command enable */ #define WAKE_POLAR (1<<5) /* PD port wake-up level */ #define IE_PD_IO (1<<10) /* PD IO interrupt enable */ #define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ #define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ #define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ #define IE_RX_RESET (1<<14) /* Reset interrupt enable */ #define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ /* USBPD->CONTROL */ #define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ #define BMC_START (1<<1) /* BMC send start signal */ #define RX_STATE_0 (1<<2) /* PD received state bit 0 */ #define RX_STATE_1 (1<<3) /* PD received state bit 1 */ #define RX_STATE_2 (1<<4) /* PD received state bit 2 */ #define DATA_FLAG (1<<5) /* Cache data valid flag bit */ #define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ #define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ /* USBPD->TX_SEL */ #define TX_SEL1 (0<<0) #define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ #define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ #define TX_SEL2_Mask (3<<2) #define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ #define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ #define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ #define TX_SEL3_Mask (3<<4) #define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ #define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ #define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ #define TX_SEL4_Mask (3<<6) #define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ #define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ #define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ /* USBPD->STATUS */ #define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ #define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ #define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ #define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ #define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ #define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ #define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ #define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ #define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ #define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ #define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ /* USBPD->PORT_CC1 */ /* USBPD->PORT_CC2 */ #define PA_CC_AI (1<<0) /* CC port comparator analogue input */ #define CC_PD (1<<1) /* CC port pull-down resistor enable */ #define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ #define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ #define CC_PU_330 (1<<2) /* 01-330uA */ #define CC_PU_180 (2<<2) /* 10-180uA */ #define CC_PU_80 (3<<2) /* 11-80uA */ #define CC_LVE (1<<4) /* CC port output low voltage enable */ #define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ #define CC_NO_CMP (0<<5) /* 000-closed */ #define CC_CMP_22 (2<<5) /* 010-0.22V */ #define CC_CMP_45 (3<<5) /* 011-0.45V */ #define CC_CMP_55 (4<<5) /* 100-0.55V */ #define CC_CMP_66 (5<<5) /* 101-0.66V */ #define CC_CMP_95 (6<<5) /* 110-0.95V */ #define CC_CMP_123 (7<<5) /* 111-1.23V */ #define USBPD_IN_HVT (1<<9) /********************************************************* * PD pin PC14/PC15 high threshold input mode: * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication * 0-Normal GPIO threshold input * *******************************************************/ #define USBPD_PHY_V33 (1<<8) /********************************************************** * PD transceiver PHY pull-up limit configuration bits: * 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V * 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V * ********************************************************/ /* Control Message Types */ #define DEF_TYPE_RESERVED 0x00 #define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ #define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_PING 0x05 /* Send By: Source */ #define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ #define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ #define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ #define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ #define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ #define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ #define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ #define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ #define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ #define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ #define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ #define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ #define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ #define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ #define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ #define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ #define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ #define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ #define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ /* Data Message Types */ #define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ #define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ #define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ #define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ #define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ #define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ #define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ #define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ #define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ #define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ #define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ #define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ /* Vendor Define Message Command */ #define DEF_VDM_DISC_IDENT 0x01 #define DEF_VDM_DISC_SVID 0x02 #define DEF_VDM_DISC_MODE 0x03 #define DEF_VDM_ENTER_MODE 0x04 #define DEF_VDM_EXIT_MODE 0x05 #define DEF_VDM_ATTENTION 0x06 #define DEF_VDM_DP_S_UPDATE 0x10 #define DEF_VDM_DP_CONFIG 0x11 /* PD Revision */ #define DEF_PD_REVISION_10 0x00 #define DEF_PD_REVISION_20 0x01 #define DEF_PD_REVISION_30 0x02 /* PD PHY Channel */ #define DEF_PD_CC1 0x00 #define DEF_PD_CC2 0x01 #define PIN_CC1 GPIO_Pin_3 #define PIN_CC2 GPIO_Pin_4 /* PD Tx Status */ #define DEF_PD_TX_OK 0x00 #define DEF_PD_TX_FAIL 0x01 /* PDO INDEX */ #define PDO_INDEX_1 1 #define PDO_INDEX_2 2 #define PDO_INDEX_3 3 #define PDO_INDEX_4 4 #define PDO_INDEX_5 5 /******************************************************************************/ #define UPD_TMR_TX_120M (200-1) /* timer value for USB PD BMC transmittal @Fsys=120MHz */ #define UPD_TMR_RX_120M (300-1) /* timer value for USB PD BMC receiving @Fsys=120MHz */ #define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ #define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ #define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ #define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ #define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ #define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ #define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ #define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ #define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ #define PD_RX_SOP0 0x01 /* SOP0 received */ #define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ #define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ #define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ #define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ #define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ #define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ #define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ /* ch32h417_hsem.c -----------------------------------------------------------*/ /* HSEM Key */ #define HSEM_KEY (0x5AA50000) #ifdef __cplusplus }; #endif // For debug writing to the debug interface. #define DMDATA0 ((volatile uint32_t*)0xe0000340) #define DMDATA1 ((volatile uint32_t*)0xe0000344) #define DMSTATUS_SENTINEL ((volatile uint32_t*)0xe0000348)// Reads as 0x00000000 if debugger is attached. // Determination of PLL multiplication factor for non-V003 chips #if !defined(FUNCONF_SYSTEM_CORE_CLOCK) #define PLL_MULTIPLICATION ((uint32_t)0) #elif defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL #if FUNCONF_PLL_MULTIPLIER == 4 #define PLL_MULTIPLICATION RCC_PLLMUL4 #elif FUNCONF_PLL_MULTIPLIER == 6 #define PLL_MULTIPLICATION RCC_PLLMUL6 #elif FUNCONF_PLL_MULTIPLIER == 7 #define PLL_MULTIPLICATION RCC_PLLMUL7 #elif FUNCONF_PLL_MULTIPLIER == 8 #define PLL_MULTIPLICATION RCC_PLLMUL8 #elif FUNCONF_PLL_MULTIPLIER == 9 #define PLL_MULTIPLICATION RCC_PLLMUL9 #elif FUNCONF_PLL_MULTIPLIER == 10 #define PLL_MULTIPLICATION RCC_PLLMUL10 #elif FUNCONF_PLL_MULTIPLIER == 11 #define PLL_MULTIPLICATION RCC_PLLMUL11 #elif FUNCONF_PLL_MULTIPLIER == 12 #define PLL_MULTIPLICATION RCC_PLLMUL12 #elif FUNCONF_PLL_MULTIPLIER == 13 #define PLL_MULTIPLICATION RCC_PLLMUL13 #elif FUNCONF_PLL_MULTIPLIER == 14 #define PLL_MULTIPLICATION RCC_PLLMUL14 #elif FUNCONF_PLL_MULTIPLIER == 15 #define PLL_MULTIPLICATION RCC_PLLMUL15 #elif FUNCONF_PLL_MULTIPLIER == 16 #define PLL_MULTIPLICATION RCC_PLLMUL16 #elif FUNCONF_PLL_MULTIPLIER == 17 #define PLL_MULTIPLICATION RCC_PLLMUL17 #elif FUNCONF_PLL_MULTIPLIER == 18 #define PLL_MULTIPLICATION RCC_PLLMUL18 #elif FUNCONF_PLL_MULTIPLIER == 19 #define PLL_MULTIPLICATION RCC_PLLMUL19 #elif FUNCONF_PLL_MULTIPLIER == 20 #define PLL_MULTIPLICATION RCC_PLLMUL20 #elif FUNCONF_PLL_MULTIPLIER == 22 #define PLL_MULTIPLICATION RCC_PLLMUL22 #elif FUNCONF_PLL_MULTIPLIER == 24 #define PLL_MULTIPLICATION RCC_PLLMUL24 #elif FUNCONF_PLL_MULTIPLIER == 26 #define PLL_MULTIPLICATION RCC_PLLMUL26 #elif FUNCONF_PLL_MULTIPLIER == 28 #define PLL_MULTIPLICATION RCC_PLLMUL28 #elif FUNCONF_PLL_MULTIPLIER == 30 #define PLL_MULTIPLICATION RCC_PLLMUL30 #elif FUNCONF_PLL_MULTIPLIER == 32 #define PLL_MULTIPLICATION RCC_PLLMUL32 #elif FUNCONF_PLL_MULTIPLIER == 34 #define PLL_MULTIPLICATION RCC_PLLMUL34 #elif FUNCONF_PLL_MULTIPLIER == 36 #define PLL_MULTIPLICATION RCC_PLLMUL36 #elif FUNCONF_PLL_MULTIPLIER == 38 #define PLL_MULTIPLICATION RCC_PLLMUL38 #elif FUNCONF_PLL_MULTIPLIER == 40 #define PLL_MULTIPLICATION RCC_PLLMUL40 #elif FUNCONF_PLL_MULTIPLIER == 59 #define PLL_MULTIPLICATION RCC_PLLMUL59 #else #error "Invalid PLL multiplier" #endif #endif /* some bit definitions for systick regs */ #define SYSTICK_SR_CNTIF_V3F (1<<0) #define SYSTICK_SR_SWIE (1<<31) #define SYSTICK_SR_CNTIF_V5F (1<<1) #define SYSTICK_CTLR_STE (1<<0) #define SYSTICK_CTLR_STIE (1<<1) #define SYSTICK_CTLR_STCLK (1<<2) #define SYSTICK_CTLR_STRE (1<<3) #define PFIC ((PFIC_Type *) PFIC_BASE ) #define NVIC PFIC #define NVIC_KEY3 ((uint32_t)0xBEEF0080) #define SysTick ((SysTick_Type *) SysTick_BASE) #define PA0 0 #define PA1 1 #define PA2 2 #define PA3 3 #define PA4 4 #define PA5 5 #define PA6 6 #define PA7 7 #define PA8 8 #define PA9 9 #define PA10 10 #define PA11 11 #define PA12 12 #define PA13 13 #define PA14 14 #define PA15 15 #define PB0 16 #define PB1 17 #define PB2 18 #define PB3 19 #define PB4 20 #define PB5 21 #define PB6 22 #define PB7 23 #define PB8 24 #define PB9 25 #define PB10 26 #define PB11 27 #define PB12 28 #define PB13 29 #define PB14 30 #define PB15 31 #define PC0 32 #define PC1 33 #define PC2 34 #define PC3 35 #define PC4 36 #define PC5 37 #define PC6 38 #define PC7 39 #define PC8 40 #define PC9 41 #define PC10 42 #define PC11 43 #define PC12 44 #define PC13 45 #define PC14 46 #define PC15 47 #define PD0 48 #define PD1 49 #define PD2 50 #define PD3 51 #define PD4 52 #define PD5 53 #define PD6 54 #define PD7 55 #define PD8 56 #define PD9 57 #define PD10 58 #define PD11 59 #define PD12 60 #define PD13 61 #define PD14 62 #define PD15 63 #define PE0 64 #define PE1 65 #define PE2 66 #define PE3 67 #define PE4 68 #define PE5 69 #define PE6 70 #define PE7 71 #define PE8 72 #define PE9 73 #define PE10 74 #define PE11 75 #define PE12 76 #define PE13 77 #define PE14 78 #define PE15 79 #define PF0 80 #define PF1 81 #define PF2 82 #define PF3 83 #define PF4 84 #define PF5 85 #define PF6 86 #define PF7 87 #define PF8 88 #define PF9 89 #define PF10 90 #define PF11 91 #define PF12 92 #define PF13 93 #define PF14 94 #define PF15 95 #define GPIO_CNF_IN_ANALOG 0 #define GPIO_CNF_IN_FLOATING 4 #define GPIO_CNF_IN_PUPD 8 #define GPIO_CNF_OUT_PP 1 #define GPIO_CNF_OUT_OD 5 #define GPIO_CNF_OUT_PP_AF 9 #define GPIO_CNF_OUT_OD_AF 13 typedef enum { GPIO_Mode_AIN = GPIO_CNF_IN_ANALOG, GPIO_Mode_IN_FLOATING = GPIO_CNF_IN_FLOATING, GPIO_Mode_IPUPD = GPIO_CNF_IN_PUPD, GPIO_Mode_Out_OD = GPIO_CNF_OUT_OD, GPIO_Mode_Out_PP = GPIO_CNF_OUT_PP, GPIO_Mode_AF_OD = GPIO_CNF_OUT_OD_AF, GPIO_Mode_AF_PP = GPIO_CNF_OUT_PP_AF } GPIOMode_TypeDef; #define __DTCM __attribute__((section(".dtcm"))) #define __ITCM __attribute__((section(".itcm"))) typedef int (*v5f_main)(void); void StartV5F(v5f_main function); /* * This file contains various parts of the official WCH EVT Headers which * were originally under a restrictive license. * * The collection of this file was generated by * cnlohr, 2023-02-18 and * AlexanderMandera, 2023-06-23 * It was significantly reworked into several files cnlohr, 2025-01-29 * * While originally under a restrictive copyright, WCH has approved use * under MIT-licensed use, because of inclusion in Zephyr, as well as other * open-source licensed projects. * * These copies of the headers from WCH are available now under: * * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the “Software”), to * deal in the Software without restriction, including without limitation the * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #endif // Header guard