generated from TDD-Templates/cmake_cpputest_template_avr
398 lines
12 KiB
C
398 lines
12 KiB
C
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/* Copyright (c) 2004, Theodore A. Roth
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id$ */
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/* avr/iotn13.h - definitions for ATtiny13 */
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/* Verified 5/20/04 by Bruce Graham */
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#ifndef _AVR_IOTN13_H_
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#define _AVR_IOTN13_H_ 1
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/* This file should only be included from <avr/io.h>, never directly. */
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#ifndef _AVR_IO_H_
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# error "Include <avr/io.h> instead of this file."
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#endif
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#ifndef _AVR_IOXXX_H_
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# define _AVR_IOXXX_H_ "iotn13.h"
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#else
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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#endif
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/* I/O registers and bit names */
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/* ADC Control and Status Register B */
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#define ADCSRB _SFR_IO8(0x03)
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# define ACME 6
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# define ADTS2 2
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# define ADTS1 1
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# define ADTS0 0
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/* ADC Data Register */
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#ifndef __ASSEMBLER__
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#define ADC _SFR_IO16 (0x04)
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#endif
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#define ADCW _SFR_IO16 (0x04)
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#define ADCL _SFR_IO8(0x04)
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#define ADCH _SFR_IO8(0x05)
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/* ADC Control and Status Register A */
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#define ADCSRA _SFR_IO8(0x06)
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# define ADEN 7
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# define ADSC 6
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# define ADATE 5
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# define ADIF 4
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# define ADIE 3
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# define ADPS2 2
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# define ADPS1 1
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# define ADPS0 0
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/* ADC Multiplex Selection Register */
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#define ADMUX _SFR_IO8(0x07)
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# define REFS0 6
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# define ADLAR 5
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# define MUX1 1
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# define MUX0 0
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/* Analog Comparator Control and Status Register */
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#define ACSR _SFR_IO8(0x08)
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# define ACD 7
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# define ACBG 6
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# define ACO 5
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# define ACI 4
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# define ACIE 3
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# define ACIS1 1
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# define ACIS0 0
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/* Digital Input Disable Register 0 */
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#define DIDR0 _SFR_IO8(0x14)
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# define ADC0D 5
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# define ADC2D 4
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# define ADC3D 3
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# define ADC1D 2
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# define AIN1D 1
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# define AIN0D 0
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/* PIN Change Mask Register */
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#define PCMSK _SFR_IO8(0x15)
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# define PCINT5 5
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# define PCINT4 4
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# define PCINT3 3
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# define PCINT2 2
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# define PCINT1 1
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# define PCINT0 0
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/* Port B Pin Utilization [2535D-AVR-04/04]
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- PORTB5 = PCINT5/RESET#/ADC0/dW
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- PORTB4 = PCINT4/ADC2
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- PORTB3 = PCINT3/CLKI/ADC3
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- PORTB2 = SCK/ADC1/T0/PCINT2
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- PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1
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- PORTB0 = MOSI/AIN0/OC0A/PCINT0 */
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/* Input Pins, Port B */
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#define PINB _SFR_IO8(0x16)
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# define PINB5 5
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# define PINB4 4
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# define PINB3 3
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# define PINB2 2
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# define PINB1 1
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# define PINB0 0
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/* Data Direction Register, Port B */
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#define DDRB _SFR_IO8(0x17)
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# define DDB5 5
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# define DDB4 4
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# define DDB3 3
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# define DDB2 2
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# define DDB1 1
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# define DDB0 0
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/* Data Register, Port B */
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#define PORTB _SFR_IO8(0x18)
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# define PB5 5
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# define PB4 4
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# define PB3 3
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# define PB2 2
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# define PB1 1
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# define PB0 0
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/* ATtiny EEPROM Control Register EECR */
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#define EECR _SFR_IO8(0x1C)
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#define EEPM1 5
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#define EEPM0 4
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#define EERIE 3
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#define EEMPE 2
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#define EEPE 1
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#define EERE 0
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/* EEPROM Data Register */
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#define EEDR _SFR_IO8(0x1D)
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/* The EEPROM Address Register EEAR[6:0] */
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#define EEAR _SFR_IO8(0x1E)
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#define EEARL _SFR_IO8(0x1E)
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/* Watchdog Timer Control Register */
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#define WDTCR _SFR_IO8(0x21)
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# define WDTIF 7
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# define WDTIE 6
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# define WDP3 5
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# define WDCE 4
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# define WDE 3
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# define WDP2 2
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# define WDP1 1
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# define WDP0 0
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/* Clock Prescale Register */
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#define CLKPR _SFR_IO8(0x26)
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# define CLKPCE 7
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# define CLKPS3 3
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# define CLKPS2 2
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# define CLKPS1 1
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# define CLKPS0 0
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/* General Timer/Counter Control Register */
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#define GTCCR _SFR_IO8(0x28)
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# define TSM 7
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# define PSR10 0
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/* Output Compare 0 Register B */
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#define OCR0B _SFR_IO8(0x29)
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/* debugWIRE Data Register */
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#define DWDR _SFR_IO8(0x2e)
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/* Timer/Counter 0 Control Register A */
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#define TCCR0A _SFR_IO8(0x2f)
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# define COM0A1 7
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# define COM0A0 6
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# define COM0B1 5
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# define COM0B0 4
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# define WGM01 1
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# define WGM00 0
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/* Oscillator Calibration Register */
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#define OSCCAL _SFR_IO8(0x31)
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/* Timer/Counter0 (8-bit) */
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#define TCNT0 _SFR_IO8(0x32)
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/* Timer/Counter 0 Control Register B */
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#define TCCR0B _SFR_IO8(0x33)
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# define FOC0A 7
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# define FOC0B 6
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# define WGM02 3
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# define CS02 2
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# define CS01 1
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# define CS00 0
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/* MCU General Status Register */
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#define MCUSR _SFR_IO8(0x34)
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# define WDRF 3
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# define BORF 2
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# define EXTRF 1
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# define PORF 0
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/* MCU General Control Register */
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#define MCUCR _SFR_IO8(0x35)
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# define PUD 6
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# define SE 5
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# define SM1 4
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# define SM0 3
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# define ISC01 1
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# define ISC00 0
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/* Output Compare 0 REgister A */
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#define OCR0A _SFR_IO8(0x36)
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/* Store Program Memory Control and Status Register */
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#define SPMCSR _SFR_IO8(0x37)
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# define CTPB 4
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# define RFLB 3
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# define PGWRT 2
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# define PGERS 1
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# define SPMEN 0
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# define SELFPRGEN 0
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/* Timer/Counter 0 Interrupt Flag Register */
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#define TIFR0 _SFR_IO8(0x38)
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# define OCF0B 3
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# define OCF0A 2
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# define TOV0 1
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/* Timer/Counter 0 Interrupt MaSK Register */
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#define TIMSK0 _SFR_IO8(0x39)
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# define OCIE0B 3
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# define OCIE0A 2
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# define TOIE0 1
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/* General Interrupt Flag Register */
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#define GIFR _SFR_IO8(0x3a)
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# define INTF0 6
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# define PCIF 5
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/* General Interrupt MaSK register */
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#define GIMSK _SFR_IO8(0x3b)
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# define INT0 6
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# define PCIE 5
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/* SPL and SREG are defined in <avr/io.h> */
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/* From the datasheet:
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1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset
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2 0x0001 INT0 External Interrupt Request 0
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3 0x0002 PCINT0 Pin Change Interrupt Request 0
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4 0x0003 TIM0_OVF Timer/Counter Overflow
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5 0x0004 EE_RDY EEPROM Ready
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6 0x0005 ANA_COMP Analog Comparator
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7 0x0006 TIM0_COMPA Timer/Counter Compare Match A
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8 0x0007 TIM0_COMPB Timer/Counter Compare Match B
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9 0x0008 WDT Watchdog Time-out
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10 0x0009 ADC ADC Conversion Complete */
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/* External Interrupt 0 */
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#define INT0_vect_num 1
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#define INT0_vect _VECTOR(1)
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#define SIG_INTERRUPT0 _VECTOR(1)
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/* External Interrupt Request 0 */
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#define PCINT0_vect_num 2
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#define PCINT0_vect _VECTOR(2)
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#define SIG_PIN_CHANGE0 _VECTOR(2)
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/* Timer/Counter0 Overflow */
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#define TIM0_OVF_vect_num 3
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#define TIM0_OVF_vect _VECTOR(3)
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#define SIG_OVERFLOW0 _VECTOR(3)
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/* EEPROM Ready */
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#define EE_RDY_vect_num 4
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#define EE_RDY_vect _VECTOR(4)
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#define SIG_EEPROM_READY _VECTOR(4)
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/* Analog Comparator */
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#define ANA_COMP_vect_num 5
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#define ANA_COMP_vect _VECTOR(5)
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#define SIG_COMPARATOR _VECTOR(5)
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/* Timer/Counter Compare Match A */
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#define TIM0_COMPA_vect_num 6
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#define TIM0_COMPA_vect _VECTOR(6)
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#define SIG_OUTPUT_COMPARE0A _VECTOR(6)
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/* Timer/Counter Compare Match B */
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#define TIM0_COMPB_vect_num 7
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#define TIM0_COMPB_vect _VECTOR(7)
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#define SIG_OUTPUT_COMPARE0B _VECTOR(7)
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/* Watchdog Time-out */
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#define WDT_vect_num 8
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#define WDT_vect _VECTOR(8)
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#define SIG_WATCHDOG_TIMEOUT _VECTOR(8)
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/* ADC Conversion Complete */
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#define ADC_vect_num 9
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#define ADC_vect _VECTOR(9)
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#define SIG_ADC _VECTOR(9)
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#define _VECTORS_SIZE 20
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#define SPM_PAGESIZE 32
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#define RAMSTART (0x60)
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#define RAMEND 0x9F
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#define XRAMEND RAMEND
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#define E2END 0x3F
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#define E2PAGESIZE 4
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#define FLASHEND 0x3FF
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/* Fuses */
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#define FUSE_MEMORY_SIZE 2
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/* Low Fuse Byte */
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#define FUSE_CKSEL0 (unsigned char)~_BV(0)
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#define FUSE_CKSEL1 (unsigned char)~_BV(1)
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#define FUSE_SUT0 (unsigned char)~_BV(2)
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#define FUSE_SUT1 (unsigned char)~_BV(3)
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#define FUSE_CKDIV8 (unsigned char)~_BV(4)
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#define FUSE_WDTON (unsigned char)~_BV(5)
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#define FUSE_EESAVE (unsigned char)~_BV(6)
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#define FUSE_SPIEN (unsigned char)~_BV(7)
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#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN)
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/* High Fuse Byte */
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#define FUSE_RSTDISBL (unsigned char)~_BV(0)
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#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
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#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
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#define FUSE_DWEN (unsigned char)~_BV(3)
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#define FUSE_SPMEN (unsigned char)~_BV(4)
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#define HFUSE_DEFAULT (0xFF)
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/* Lock Bits */
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#define __LOCK_BITS_EXIST
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/* Signature */
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#define SIGNATURE_0 0x1E
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#define SIGNATURE_1 0x90
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#define SIGNATURE_2 0x07
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/* Deprecated items */
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#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
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#pragma GCC system_header
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#pragma GCC poison SIG_INTERRUPT0
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#pragma GCC poison SIG_PIN_CHANGE0
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#pragma GCC poison SIG_OVERFLOW0
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#pragma GCC poison SIG_EEPROM_READY
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#pragma GCC poison SIG_COMPARATOR
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#pragma GCC poison SIG_OUTPUT_COMPARE0A
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#pragma GCC poison SIG_OUTPUT_COMPARE0B
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#pragma GCC poison SIG_WATCHDOG_TIMEOUT
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#pragma GCC poison SIG_ADC
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#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
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#define SLEEP_MODE_IDLE (0x00<<3)
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#define SLEEP_MODE_ADC (0x01<<3)
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#define SLEEP_MODE_PWR_DOWN (0x02<<3)
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||
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#endif /* _AVR_IOTN13_H_*/
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