generated from TDD-Templates/cmake_cpputest_template_avr
396 lines
8.8 KiB
C
396 lines
8.8 KiB
C
/* Copyright (c) 2008 Atmel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id$ */
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/* avr/iotn13a.h - definitions for ATtiny13 */
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/* This file should only be included from <avr/io.h>, never directly. */
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#ifndef _AVR_IO_H_
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# error "Include <avr/io.h> instead of this file."
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#endif
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#ifndef _AVR_IOXXX_H_
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# define _AVR_IOXXX_H_ "iotn13a.h"
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#else
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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#endif
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#ifndef _AVR_ATTINY13A_H_
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#define _AVR_ATTINY13A_H_ 1
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/* Registers and associated bit numbers. */
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#define ADCSRB _SFR_IO8(0x03)
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#define ADTS0 0
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#define ADTS1 1
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#define ADTS2 2
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#define ACME 6
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#ifndef __ASSEMBLER__
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#define ADC _SFR_IO16(0x04)
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#endif
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#define ADCW _SFR_IO16(0x04)
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#define ADCL _SFR_IO8(0x04)
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#define ADCL0 0
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#define ADCL1 1
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#define ADCL2 2
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#define ADCL3 3
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#define ADCL4 4
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#define ADCL5 5
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#define ADCL6 6
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#define ADCL7 7
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#define ADCH _SFR_IO8(0x05)
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#define ADCH0 0
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#define ADCH1 1
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#define ADCH2 2
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#define ADCH3 3
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#define ADCH4 4
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#define ADCH5 5
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#define ADCH6 6
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#define ADCH7 7
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#define ADCSRA _SFR_IO8(0x06)
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#define ADPS0 0
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#define ADPS1 1
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#define ADPS2 2
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#define ADIE 3
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#define ADIF 4
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#define ADATE 5
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#define ADSC 6
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#define ADEN 7
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#define ADMUX _SFR_IO8(0x07)
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#define MUX0 0
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#define MUX1 1
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#define ADLAR 5
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#define REFS0 6
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#define ACSR _SFR_IO8(0x08)
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#define ACIS0 0
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#define ACIS1 1
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#define ACIE 3
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#define ACI 4
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#define ACO 5
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#define ACBG 6
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#define ACD 7
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#define DIDR0 _SFR_IO8(0x14)
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#define AIN0D 0
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#define AIN1D 1
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#define ADC1D 2
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#define ADC3D 3
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#define ADC2D 4
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#define ADC0D 5
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#define PCMSK _SFR_IO8(0x15)
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#define PCINT0 0
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#define PCINT1 1
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#define PCINT2 2
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#define PCINT3 3
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#define PCINT4 4
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#define PCINT5 5
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#define PINB _SFR_IO8(0x16)
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#define PINB0 0
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#define PINB1 1
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#define PINB2 2
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#define PINB3 3
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#define PINB4 4
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#define PINB5 5
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#define DDRB _SFR_IO8(0x17)
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#define DDB0 0
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#define DDB1 1
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#define DDB2 2
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#define DDB3 3
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#define DDB4 4
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#define DDB5 5
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#define PORTB _SFR_IO8(0x18)
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#define PORTB0 0
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#define PORTB1 1
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#define PORTB2 2
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#define PORTB3 3
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#define PORTB4 4
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#define PORTB5 5
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#define EECR _SFR_IO8(0x1C)
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#define EERE 0
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#define EEWE 1
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#define EEPE EEWE
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#define EEMWE 2
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#define EEMPE EEMWE
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#define EERIE 3
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#define EEPM0 4
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#define EEPM1 5
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#define EEDR _SFR_IO8(0x1D)
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#define EEDR0 0
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#define EEDR1 1
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#define EEDR2 2
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#define EEDR3 3
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#define EEDR4 4
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#define EEDR5 5
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#define EEDR6 6
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#define EEDR7 7
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#define EEARL _SFR_IO8(0x1E)
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#define EEAR _SFR_IO8(0x1E)
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#define EEAR0 0
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#define EEAR1 1
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#define EEAR2 2
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#define EEAR3 3
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#define EEAR4 4
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#define EEAR5 5
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#define WDTCR _SFR_IO8(0x21)
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#define WDP0 0
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#define WDP1 1
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#define WDP2 2
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#define WDE 3
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#define WDCE 4
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#define WDP3 5
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#define WDTIE 6
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#define WDTIF 7
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#define PRR _SFR_IO8(0x25)
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#define PRADC 0
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#define PRTIM0 1
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#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRTIM0))
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#define __AVR_HAVE_PRR_PRADC
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#define __AVR_HAVE_PRR_PRTIM0
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#define CLKPR _SFR_IO8(0x26)
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#define CLKPS0 0
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#define CLKPS1 1
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#define CLKPS2 2
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#define CLKPS3 3
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#define CLKPCE 7
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#define GTCCR _SFR_IO8(0x28)
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#define PSR10 0
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#define TSM 7
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#define OCR0B _SFR_IO8(0x29)
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#define OCR0B_0 0
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#define OCR0B_1 1
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#define OCR0B_2 2
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#define OCR0B_3 3
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#define OCR0B_4 4
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#define OCR0B_5 5
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#define OCR0B_6 6
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#define OCR0B_7 7
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#define DWDR _SFR_IO8(0x2E)
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#define DWDR0 0
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#define DWDR1 1
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#define DWDR2 2
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#define DWDR3 3
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#define DWDR4 4
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#define DWDR5 5
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#define DWDR6 6
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#define DWDR7 7
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#define TCCR0A _SFR_IO8(0x2F)
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#define WGM00 0
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#define WGM01 1
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#define COM0B0 4
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#define COM0B1 5
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#define COM0A0 6
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#define COM0A1 7
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#define BODCR _SFR_IO8(0x30)
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#define BODSE 0
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#define BODS 1
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#define OSCCAL _SFR_IO8(0x31)
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#define CAL0 0
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#define CAL1 1
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#define CAL2 2
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#define CAL3 3
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#define CAL4 4
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#define CAL5 5
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#define CAL6 6
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#define TCNT0 _SFR_IO8(0x32)
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#define TCNT0_0 0
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#define TCNT0_1 1
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#define TCNT0_2 2
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#define TCNT0_3 3
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#define TCNT0_4 4
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#define TCNT0_5 5
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#define TCNT0_6 6
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#define TCNT0_7 7
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#define TCCR0B _SFR_IO8(0x33)
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#define CS00 0
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#define CS01 1
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#define CS02 2
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#define WGM02 3
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#define FOC0B 6
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#define FOC0A 7
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#define MCUSR _SFR_IO8(0x34)
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#define PORF 0
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#define EXTRF 1
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#define BORF 2
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#define WDRF 3
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#define MCUCR _SFR_IO8(0x35)
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#define ISC00 0
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#define ISC01 1
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#define SM0 3
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#define SM1 4
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#define SE 5
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#define PUD 6
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#define OCR0A _SFR_IO8(0x36)
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#define OCR0A_0 0
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#define OCR0A_1 1
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#define OCR0A_2 2
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#define OCR0A_3 3
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#define OCR0A_4 4
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#define OCR0A_5 5
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#define OCR0A_6 6
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#define OCR0A_7 7
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#define SPMCSR _SFR_IO8(0x37)
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#define SPMEN 0
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#define PGERS 1
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#define PGWRT 2
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#define RFLB 3
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#define CTPB 4
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#define TIFR0 _SFR_IO8(0x38)
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#define TOV0 1
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#define OCF0A 2
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#define OCF0B 3
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#define TIMSK0 _SFR_IO8(0x39)
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#define TOIE0 1
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#define OCIE0A 2
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#define OCIE0B 3
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#define GIFR _SFR_IO8(0x3A)
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#define PCIF 5
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#define INTF0 6
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#define GIMSK _SFR_IO8(0x3B)
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#define PCIE 5
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#define INT0 6
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/* Interrupt vectors */
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/* Vector 0 is the reset vector */
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#define INT0_vect_num 1
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#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
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#define PCINT0_vect_num 2
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#define PCINT0_vect _VECTOR(2) /* External Interrupt Request 0 */
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#define TIM0_OVF_vect_num 3
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#define TIM0_OVF_vect _VECTOR(3) /* Timer/Counter0 Overflow */
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#define EE_RDY_vect_num 4
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#define EE_RDY_vect _VECTOR(4) /* EEPROM Ready */
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#define ANA_COMP_vect_num 5
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#define ANA_COMP_vect _VECTOR(5) /* Analog Comparator */
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#define TIM0_COMPA_vect_num 6
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#define TIM0_COMPA_vect _VECTOR(6) /* Timer/Counter Compare Match A */
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#define TIM0_COMPB_vect_num 7
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#define TIM0_COMPB_vect _VECTOR(7) /* Timer/Counter Compare Match B */
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#define WDT_vect_num 8
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#define WDT_vect _VECTOR(8) /* Watchdog Time-out */
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#define ADC_vect_num 9
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#define ADC_vect _VECTOR(9) /* ADC Conversion Complete */
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#define _VECTOR_SIZE 2 /* Size of individual vector. */
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#define _VECTORS_SIZE (10 * _VECTOR_SIZE)
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/* Constants */
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#define SPM_PAGESIZE (32)
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#define RAMSTART (0x60)
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#define RAMSIZE (64)
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#define RAMEND (RAMSTART + RAMSIZE - 1)
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#define XRAMSTART (NA)
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#define XRAMSIZE (0)
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#define XRAMEND RAMEND
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#define E2END (64 - 1)
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#define E2PAGESIZE (4)
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#define FLASHEND (1024 - 1)
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/* Fuses */
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#define FUSE_MEMORY_SIZE 2
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/* Low Fuse Byte */
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#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
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#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
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#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */
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#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */
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#define FUSE_CKDIV8 (unsigned char)~_BV(4) /* Start up with system clock divided by 8 */
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#define FUSE_WDTON (unsigned char)~_BV(5) /* Watch dog timer always on */
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#define FUSE_EESAVE (unsigned char)~_BV(6) /* Keep EEprom contents during chip erase */
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#define FUSE_SPIEN (unsigned char)~_BV(7) /* SPI programming enable */
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#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0)
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/* High Fuse Byte */
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#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */
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#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Enable BOD and select level */
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#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Enable BOD and select level */
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#define FUSE_DWEN (unsigned char)~_BV(3) /* DebugWire Enable */
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#define FUSE_SELFPRGEN (unsigned char)~_BV(4) /* Self Programming Enable */
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#define HFUSE_DEFAULT (0xFF)
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/* Lock Bits */
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#define __LOCK_BITS_EXIST
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/* Signature */
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#define SIGNATURE_0 0x1E
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#define SIGNATURE_1 0x90
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#define SIGNATURE_2 0x07
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#define SLEEP_MODE_IDLE (0x00<<3)
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#define SLEEP_MODE_ADC (0x01<<3)
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#define SLEEP_MODE_PWR_DOWN (0x02<<3)
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#endif /* _AVR_ATTINY13A_H_ */
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