TDD-Templates/cmake_cpputest_template
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automatic fomatting chagnes.

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jakeg00dwin 2025-06-06 07:54:05 -07:00
parent db5dd3784d
commit 06efeab4e5
1 changed files with 3302 additions and 3398 deletions
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218
inc/ch32v003hw.h Executable file → Normal file
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@ -6,7 +6,8 @@
#ifndef __ASSEMBLER__ // Things before this can be used in assembly. #ifndef __ASSEMBLER__ // Things before this can be used in assembly.
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C"
{
#endif #endif
/* Interrupt Number Definition, according to the selected device */ /* Interrupt Number Definition, according to the selected device */
@ -89,7 +90,6 @@ typedef enum IRQn
.word TIM2_IRQHandler /* TIM2 */ \n\ .word TIM2_IRQHandler /* TIM2 */ \n\
.option pop;\n" .option pop;\n"
/* memory mapped structure for SysTick */ /* memory mapped structure for SysTick */
typedef struct typedef struct
{ {
@ -101,12 +101,10 @@ typedef struct
uint32_t RESERVED1; uint32_t RESERVED1;
} SysTick_Type; } SysTick_Type;
#endif /* __ASSEMBLER__*/ #endif /* __ASSEMBLER__*/
#define HardFault_IRQn EXC_IRQn #define HardFault_IRQn EXC_IRQn
/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ /* Standard Peripheral Library old definitions (maintained for legacy purpose) */
#define HSI_Value HSI_VALUE #define HSI_Value HSI_VALUE
#define HSE_Value HSE_VALUE #define HSE_Value HSE_VALUE
@ -139,8 +137,6 @@ typedef struct
__IO uint32_t DLYR; __IO uint32_t DLYR;
} ADC_TypeDef; } ADC_TypeDef;
/* CRC Calculation Unit */ /* CRC Calculation Unit */
typedef struct typedef struct
{ {
@ -151,7 +147,6 @@ typedef struct
__IO uint32_t CTLR; __IO uint32_t CTLR;
} CRC_TypeDef; } CRC_TypeDef;
/* Debug MCU */ /* Debug MCU */
typedef struct typedef struct
{ {
@ -232,11 +227,10 @@ typedef struct
{ {
__I uint16_t REVID; __I uint16_t REVID;
__I uint16_t DEVID; __I uint16_t DEVID;
}; }s;
}; }u;
} INFO_TypeDef; } INFO_TypeDef;
/* General Purpose I/O */ /* General Purpose I/O */
typedef enum typedef enum
{ {
@ -257,9 +251,11 @@ typedef enum
GPIO_CFGLR_OUT_50Mhz_AF_OD = 15, GPIO_CFGLR_OUT_50Mhz_AF_OD = 15,
} GPIO_CFGLR_PIN_MODE_Typedef; } GPIO_CFGLR_PIN_MODE_Typedef;
typedef union { typedef union
{
uint32_t __FULL; uint32_t __FULL;
struct { struct
{
GPIO_CFGLR_PIN_MODE_Typedef PIN0 : 4; GPIO_CFGLR_PIN_MODE_Typedef PIN0 : 4;
GPIO_CFGLR_PIN_MODE_Typedef PIN1 : 4; GPIO_CFGLR_PIN_MODE_Typedef PIN1 : 4;
GPIO_CFGLR_PIN_MODE_Typedef PIN2 : 4; GPIO_CFGLR_PIN_MODE_Typedef PIN2 : 4;
@ -268,11 +264,13 @@ typedef union {
GPIO_CFGLR_PIN_MODE_Typedef PIN5 : 4; GPIO_CFGLR_PIN_MODE_Typedef PIN5 : 4;
GPIO_CFGLR_PIN_MODE_Typedef PIN6 : 4; GPIO_CFGLR_PIN_MODE_Typedef PIN6 : 4;
GPIO_CFGLR_PIN_MODE_Typedef PIN7 : 4; GPIO_CFGLR_PIN_MODE_Typedef PIN7 : 4;
}; }s;
} GPIO_CFGLR_t; } GPIO_CFGLR_t;
typedef union { typedef union
{
uint32_t __FULL; uint32_t __FULL;
const struct { const struct
{
uint32_t IDR0 : 1; uint32_t IDR0 : 1;
uint32_t IDR1 : 1; uint32_t IDR1 : 1;
uint32_t IDR2 : 1; uint32_t IDR2 : 1;
@ -282,11 +280,13 @@ typedef union {
uint32_t IDR6 : 1; uint32_t IDR6 : 1;
uint32_t IDR7 : 1; uint32_t IDR7 : 1;
uint32_t : 24; uint32_t : 24;
}; }s;
} GPIO_INDR_t; } GPIO_INDR_t;
typedef union { typedef union
{
uint32_t __FULL; uint32_t __FULL;
struct { struct
{
uint32_t ODR0 : 1; uint32_t ODR0 : 1;
uint32_t ODR1 : 1; uint32_t ODR1 : 1;
uint32_t ODR2 : 1; uint32_t ODR2 : 1;
@ -296,11 +296,13 @@ typedef union {
uint32_t ODR6 : 1; uint32_t ODR6 : 1;
uint32_t ODR7 : 1; uint32_t ODR7 : 1;
uint32_t : 24; uint32_t : 24;
}; }s;
} GPIO_OUTDR_t; } GPIO_OUTDR_t;
typedef union { typedef union
{
uint32_t __FULL; uint32_t __FULL;
struct { struct
{
uint32_t BS0 : 1; uint32_t BS0 : 1;
uint32_t BS1 : 1; uint32_t BS1 : 1;
uint32_t BS2 : 1; uint32_t BS2 : 1;
@ -319,11 +321,13 @@ typedef union {
uint32_t BR6 : 1; uint32_t BR6 : 1;
uint32_t BR7 : 1; uint32_t BR7 : 1;
uint32_t : 8; uint32_t : 8;
}; }s;
} GPIO_BSHR_t; } GPIO_BSHR_t;
typedef union { typedef union
{
uint32_t __FULL; uint32_t __FULL;
struct { struct
{
uint32_t BR0 : 1; uint32_t BR0 : 1;
uint32_t BR1 : 1; uint32_t BR1 : 1;
uint32_t BR2 : 1; uint32_t BR2 : 1;
@ -333,11 +337,13 @@ typedef union {
uint32_t BR6 : 1; uint32_t BR6 : 1;
uint32_t BR7 : 1; uint32_t BR7 : 1;
uint32_t : 24; uint32_t : 24;
}; }s;
} GPIO_BCR_t; } GPIO_BCR_t;
typedef union { typedef union
{
uint32_t __FULL; uint32_t __FULL;
struct { struct
{
uint32_t LCK0 : 1; uint32_t LCK0 : 1;
uint32_t LCK1 : 1; uint32_t LCK1 : 1;
uint32_t LCK2 : 1; uint32_t LCK2 : 1;
@ -348,7 +354,7 @@ typedef union {
uint32_t LCK7 : 1; uint32_t LCK7 : 1;
uint32_t LCKK : 1; uint32_t LCKK : 1;
uint32_t : 23; uint32_t : 23;
}; }s;
} GPIO_LCKR_t; } GPIO_LCKR_t;
typedef struct typedef struct
{ {
@ -363,7 +369,13 @@ typedef struct
#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t){.__FULL = gpio->field}) #define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t){.__FULL = gpio->field})
#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t)__VA_ARGS__).__FULL #define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t)__VA_ARGS__).__FULL
#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;} #define DYN_GPIO_MOD(gpio, field, reg, val) \
{ \
GPIO_##field##_t tmp; \
tmp.__FULL = gpio->field; \
tmp.reg = val; \
gpio->field = tmp.__FULL; \
}
/* Alternate Function I/O */ /* Alternate Function I/O */
typedef struct typedef struct
@ -428,8 +440,6 @@ typedef struct
__IO uint32_t RSTSCKR; __IO uint32_t RSTSCKR;
} RCC_TypeDef; } RCC_TypeDef;
/* Serial Peripheral Interface */ /* Serial Peripheral Interface */
typedef struct typedef struct
{ {
@ -533,11 +543,6 @@ typedef struct
__IO uint32_t CTR; __IO uint32_t CTR;
} EXTEND_TypeDef; } EXTEND_TypeDef;
#endif #endif
/* Peripheral memory map */ /* Peripheral memory map */
@ -553,7 +558,6 @@ typedef struct
#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */ #define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */
#endif #endif
#define APB1PERIPH_BASE (PERIPH_BASE) #define APB1PERIPH_BASE (PERIPH_BASE)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
@ -586,7 +590,6 @@ typedef struct
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ #define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */
#define ESIG_BASE ((uint32_t)0x1FFFF7E0) #define ESIG_BASE ((uint32_t)0x1FFFF7E0)
#define INFO_BASE ((uint32_t)0x1FFFF704) #define INFO_BASE ((uint32_t)0x1FFFF704)
@ -599,9 +602,6 @@ typedef struct
#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000) #define PFIC_BASE (CORE_PERIPH_BASE + 0xE000)
#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000) #define SysTick_BASE (CORE_PERIPH_BASE + 0xF000)
// AFIO CTLR Bits // AFIO CTLR Bits
#define PB6_FILT_EN (1 << 27) #define PB6_FILT_EN (1 << 27)
#define PB5_FILT_EN (1 << 26) #define PB5_FILT_EN (1 << 26)
@ -634,7 +634,6 @@ typedef struct
#define UDM_PUE_10K 0x00000002 #define UDM_PUE_10K 0x00000002
#define UDM_PUE_1K5 0x00000003 #define UDM_PUE_1K5 0x00000003
// USB PD Bits // USB PD Bits
#define IE_TX_END (1 << 15) #define IE_TX_END (1 << 15)
#define IE_RX_RESET (1 << 14) #define IE_RX_RESET (1 << 14)
@ -715,8 +714,6 @@ typedef struct
#define CC2_PU_80uA (3 << 2) #define CC2_PU_80uA (3 << 2)
#define PA_CC2_AI (1 << 0) #define PA_CC2_AI (1 << 0)
/* Peripheral declaration */ /* Peripheral declaration */
#define TIM2 ((TIM_TypeDef *)TIM2_BASE) #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
#define WWDG ((WWDG_TypeDef *)WWDG_BASE) #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
@ -747,12 +744,9 @@ typedef struct
#define OB ((OB_TypeDef *)OB_BASE) #define OB ((OB_TypeDef *)OB_BASE)
#define ESIG ((ESG_TypeDef *)ESIG_BASE) #define ESIG ((ESG_TypeDef *)ESIG_BASE)
// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors. // Mentioned in ch32v30x_dbgmcu.c, may not work on all processors.
#define INFO ((INFO_TypeDef *)INFO_BASE) //#define INFO ((INFO_TypeDef *)INFO_BASE)
#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) //#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN //#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN
/******************************************************************************/ /******************************************************************************/
/* Peripheral Registers Bits Definition */ /* Peripheral Registers Bits Definition */
@ -1146,7 +1140,6 @@ typedef struct
#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ #define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ #define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_INTFCR register *******************/ /******************* Bit definition for DMA_INTFCR register *******************/
#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ #define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ #define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
@ -1494,7 +1487,6 @@ typedef struct
#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ #define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */
#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ #define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */
/****************** Bit definition for FLASH_KEYR register ******************/ /****************** Bit definition for FLASH_KEYR register ******************/
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */
@ -1826,7 +1818,6 @@ typedef struct
#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ #define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ #define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */
/****************** Bit definition for AFIO_PCFR1register *******************/ /****************** Bit definition for AFIO_PCFR1register *******************/
#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ #define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */
#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ #define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */
@ -1900,7 +1891,6 @@ typedef struct
#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ #define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ #define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
/***************** Bit definition for AFIO_EXTICR register *****************/ /***************** Bit definition for AFIO_EXTICR register *****************/
#define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ #define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */
#define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ #define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */
@ -1930,7 +1920,6 @@ typedef struct
#define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ #define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */
#define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ #define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */
/******************************************************************************/ /******************************************************************************/
/* Independent WATCHDOG */ /* Independent WATCHDOG */
/******************************************************************************/ /******************************************************************************/
@ -2041,7 +2030,6 @@ typedef struct
#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ #define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ #define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */
/******************************************************************************/ /******************************************************************************/
/* Power Control */ /* Power Control */
/******************************************************************************/ /******************************************************************************/
@ -2115,7 +2103,6 @@ typedef struct
#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ #define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */
#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ #define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */
/******************* Bit definition for RCC_CFGR0 register *******************/ /******************* Bit definition for RCC_CFGR0 register *******************/
#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ #define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ #define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */
@ -2197,7 +2184,6 @@ typedef struct
#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ #define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */
#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ #define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */
#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ #define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */
#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ #define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
@ -2302,7 +2288,6 @@ typedef struct
#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ #define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
/******************* Bit definition for RCC_RSTSCKR register ********************/ /******************* Bit definition for RCC_RSTSCKR register ********************/
#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ #define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ #define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
@ -2316,9 +2301,6 @@ typedef struct
/****************** Bit definition for RCC_AHBRSTR register *****************/ /****************** Bit definition for RCC_AHBRSTR register *****************/
/******************************************************************************/ /******************************************************************************/
/* Serial Peripheral Interface */ /* Serial Peripheral Interface */
/******************************************************************************/ /******************************************************************************/
@ -2788,28 +2770,21 @@ typedef struct
#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ #define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */
#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ #define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ #define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
#define EXTEN_OPA_EN ((uint32_t)0x00010000) #define EXTEN_OPA_EN ((uint32_t)0x00010000)
#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) #define EXTEN_OPA_NSEL ((uint32_t)0x00020000)
#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) #define EXTEN_OPA_PSEL ((uint32_t)0x00040000)
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C"
{
#endif #endif
/* ch32v00x_gpio.c -----------------------------------------------------------*/ /* ch32v00x_gpio.c -----------------------------------------------------------*/
/* MASK */ /* MASK */
#define LSB_MASK ((uint16_t)0xFFFF) #define LSB_MASK ((uint16_t)0xFFFF)
@ -2818,7 +2793,6 @@ extern "C" {
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
/* ch32v00x_adc.c ------------------------------------------------------------*/ /* ch32v00x_adc.c ------------------------------------------------------------*/
/* ADC DISCNUM mask */ /* ADC DISCNUM mask */
@ -2914,13 +2888,9 @@ extern "C" {
/* ADC IDATARx registers offset */ /* ADC IDATARx registers offset */
#define IDATAR_Offset ((uint8_t)0x28) #define IDATAR_Offset ((uint8_t)0x28)
/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/ /* ch32v00x_dbgmcu.c ---------------------------------------------------------*/
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
/* ch32v00x_dma.c ------------------------------------------------------------*/ /* ch32v00x_dma.c ------------------------------------------------------------*/
/* DMA1 Channelx interrupt pending bit masks */ /* DMA1 Channelx interrupt pending bit masks */
@ -2932,7 +2902,6 @@ extern "C" {
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
/* DMA2 FLAG mask */ /* DMA2 FLAG mask */
// Editor's note: Overloaded Definition. // Editor's note: Overloaded Definition.
#define DMA2_FLAG_Mask ((uint32_t)0x10000000) #define DMA2_FLAG_Mask ((uint32_t)0x10000000)
@ -2942,7 +2911,6 @@ extern "C" {
/* ch32v00x_exti.c -----------------------------------------------------------*/ /* ch32v00x_exti.c -----------------------------------------------------------*/
/* No interrupt selected */ /* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000) #define EXTI_LINENONE ((uint32_t)0x00000)
@ -2951,7 +2919,6 @@ extern "C" {
/* Flash Access Control Register bits */ /* Flash Access Control Register bits */
#define ACR_LATENCY_Mask ((uint32_t)0x00000038) #define ACR_LATENCY_Mask ((uint32_t)0x00000038)
/* Flash Control Register bits */ /* Flash Control Register bits */
#define CR_PG_Set ((uint32_t)0x00000001) #define CR_PG_Set ((uint32_t)0x00000001)
#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) #define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
@ -2990,7 +2957,6 @@ extern "C" {
/* FLASH BANK address */ /* FLASH BANK address */
#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) #define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
/* Delay definition */ /* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000) #define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00002000) #define ProgramTimeout ((uint32_t)0x00002000)
@ -2999,10 +2965,8 @@ extern "C" {
#define ValidAddrStart (FLASH_BASE) #define ValidAddrStart (FLASH_BASE)
#define ValidAddrEnd (FLASH_BASE + 0x4000) #define ValidAddrEnd (FLASH_BASE + 0x4000)
/* ch32v00x_i2c.c ------------------------------------------------------------*/ /* ch32v00x_i2c.c ------------------------------------------------------------*/
/* I2C SPE mask */ /* I2C SPE mask */
#define CTLR1_PE_Set ((uint16_t)0x0001) #define CTLR1_PE_Set ((uint16_t)0x0001)
#define CTLR1_PE_Reset ((uint16_t)0xFFFE) #define CTLR1_PE_Reset ((uint16_t)0xFFFE)
@ -3088,10 +3052,8 @@ extern "C" {
#define CTLR_KEY_Reload ((uint16_t)0xAAAA) #define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC) #define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/* ch32v00x_pwr.c ------------------------------------------------------------*/ /* ch32v00x_pwr.c ------------------------------------------------------------*/
/* PWR registers bit mask */ /* PWR registers bit mask */
/* CTLR register bit mask */ /* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
@ -3134,7 +3096,6 @@ extern "C" {
/* RSTSCKR register bit mask */ /* RSTSCKR register bit mask */
#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) #define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
/* RCC Flag Mask */ /* RCC Flag Mask */
// Editor's Note: Overloaded Definition // Editor's Note: Overloaded Definition
#define RCC_FLAG_Mask ((uint8_t)0x1F) #define RCC_FLAG_Mask ((uint8_t)0x1F)
@ -3156,15 +3117,12 @@ static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5
static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128};
#endif #endif
/* ch32v00x_spi.c ------------------------------------------------------------*/ /* ch32v00x_spi.c ------------------------------------------------------------*/
/* SPI SPE mask */ /* SPI SPE mask */
#define CTLR1_SPE_Set ((uint16_t)0x0040) #define CTLR1_SPE_Set ((uint16_t)0x0040)
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) #define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
/* SPI CRCNext mask */ /* SPI CRCNext mask */
#define CTLR1_CRCNext_Set ((uint16_t)0x1000) #define CTLR1_CRCNext_Set ((uint16_t)0x1000)
@ -3181,8 +3139,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040) #define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040)
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) #define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
/* ch32v00x_tim.c ------------------------------------------------------------*/ /* ch32v00x_tim.c ------------------------------------------------------------*/
/* TIM registers bit mask */ /* TIM registers bit mask */
@ -3249,7 +3205,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) #define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F) #define BIT_Mask ((uint8_t)0x7F)
/* ch32v00x_adc.h ------------------------------------------------------------*/ /* ch32v00x_adc.h ------------------------------------------------------------*/
/* ADC_mode */ /* ADC_mode */
@ -3266,8 +3221,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) #define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
/* ADC_data_align */ /* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800) #define ADC_DataAlign_Left ((uint32_t)0x00000800)
@ -3287,7 +3240,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) #define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
/* ADC_sampling_time */ /* ADC_sampling_time */
#define ADC_SampleTime_3Cycles ((uint8_t)0x00) #define ADC_SampleTime_3Cycles ((uint8_t)0x00)
#define ADC_SampleTime_9Cycles ((uint8_t)0x01) #define ADC_SampleTime_9Cycles ((uint8_t)0x01)
@ -3306,7 +3258,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) #define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
/* ADC_injected_channel_selection */ /* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_2 ((uint8_t)0x18)
@ -3342,9 +3293,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) #define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200) #define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200)
/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/ /* ch32v00x_dbgmcu.h ---------------------------------------------------------*/
/* DBGMCU_CR Register */ /* DBGMCU_CR Register */
@ -3428,7 +3376,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA1_IT_TE7 ((uint32_t)0x08000000)
/* DMA_flags_definition */ /* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
@ -3459,9 +3406,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
/* ch32v00x_exti.h -----------------------------------------------------------*/ /* ch32v00x_exti.h -----------------------------------------------------------*/
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
@ -3497,7 +3441,6 @@ typedef enum
/* ch32v00x_flash.h ----------------------------------------------------------*/ /* ch32v00x_flash.h ----------------------------------------------------------*/
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
/* FLASH Status */ /* FLASH Status */
typedef enum typedef enum
@ -3518,7 +3461,6 @@ typedef enum
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ #define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ #define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
/* Values to be used with CH32V00x devices (1page = 64Byte) */ /* Values to be used with CH32V00x devices (1page = 64Byte) */
#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ #define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ #define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
@ -3539,7 +3481,6 @@ typedef enum
#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ #define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
/* Option_Bytes_IWatchdog */ /* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
@ -3558,7 +3499,6 @@ typedef enum
#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ #define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */ #define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */
/* Option_Bytes_Power_ON_Start_Mode */ /* Option_Bytes_Power_ON_Start_Mode */
#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */ #define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */
#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */ #define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */
@ -3582,12 +3522,10 @@ typedef enum
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/* System_Reset_Start_Mode */ /* System_Reset_Start_Mode */
#define Start_Mode_USER ((uint32_t)0x00000000) #define Start_Mode_USER ((uint32_t)0x00000000)
#define Start_Mode_BOOT ((uint32_t)0x00004000) #define Start_Mode_BOOT ((uint32_t)0x00004000)
/* ch32v00x_gpio.h ------------------------------------------------------------*/ /* ch32v00x_gpio.h ------------------------------------------------------------*/
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
@ -3668,7 +3606,6 @@ typedef enum
#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ #define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */
#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ #define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */
/* GPIO_Port_Sources */ /* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00) #define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02) #define GPIO_PortSourceGPIOC ((uint8_t)0x02)
@ -3684,7 +3621,6 @@ typedef enum
#define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource7 ((uint8_t)0x07)
/* ch32v00x_i2c.h ------------------------------------------------------------*/ /* ch32v00x_i2c.h ------------------------------------------------------------*/
/* I2C_mode */ /* I2C_mode */
@ -3928,7 +3864,6 @@ typedef enum
/*EVT3_2 */ /*EVT3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
/* ch32v00x_iwdg.h -----------------------------------------------------------*/ /* ch32v00x_iwdg.h -----------------------------------------------------------*/
/* IWDG_WriteAccess */ /* IWDG_WriteAccess */
@ -3948,7 +3883,6 @@ typedef enum
#define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IWDG_FLAG_RVU ((uint16_t)0x0002)
/* ch32v00x_misc.h -----------------------------------------------------------*/ /* ch32v00x_misc.h -----------------------------------------------------------*/
/* Preemption_Priority_Group */ /* Preemption_Priority_Group */
@ -3963,7 +3897,6 @@ typedef enum
/* Editor's note: I don't know if this is actually useful */ /* Editor's note: I don't know if this is actually useful */
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
/* OPA PSEL enumeration */ /* OPA PSEL enumeration */
typedef enum typedef enum
{ {
@ -3978,8 +3911,6 @@ typedef enum
CHN1 CHN1
} OPA_NSEL_TypeDef; } OPA_NSEL_TypeDef;
/* OPA Init Structure definition */ /* OPA Init Structure definition */
typedef struct typedef struct
{ {
@ -3987,9 +3918,9 @@ typedef struct
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
} OPA_InitTypeDef; } OPA_InitTypeDef;
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
typedef struct{ typedef struct
{
__I uint32_t ISR[8]; __I uint32_t ISR[8];
__I uint32_t IPR[8]; __I uint32_t IPR[8];
__IO uint32_t ITHRESDR; __IO uint32_t ITHRESDR;
@ -4019,7 +3950,6 @@ typedef struct{
/* ch32v00x_pwr.h ------------------------------------------------------------*/ /* ch32v00x_pwr.h ------------------------------------------------------------*/
/* PVD_detection_level */ /* PVD_detection_level */
#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) #define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
@ -4055,28 +3985,22 @@ typedef struct{
/* PWR_Flag */ /* PWR_Flag */
#define PWR_FLAG_PVDO ((uint32_t)0x00000004) #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
/* ch32v00x_rcc.h ------------------------------------------------------------*/ /* ch32v00x_rcc.h ------------------------------------------------------------*/
/* HSE_configuration */ /* HSE_configuration */
#define RCC_HSE_OFF ((uint32_t)0x00000000) #define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000) #define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000) #define RCC_HSE_Bypass ((uint32_t)0x00040000)
/* PLL_entry_clock_source */ /* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) #define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) #define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
/* System_clock_source */ /* System_clock_source */
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
/* AHB_clock_source */ /* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
@ -4092,7 +4016,6 @@ typedef struct{
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) #define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
/* RCC_Interrupt_source */ /* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSIRDY ((uint8_t)0x04)
@ -4100,7 +4023,6 @@ typedef struct{
#define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80) #define RCC_IT_CSS ((uint8_t)0x80)
/* ADC_clock_source */ /* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
@ -4115,8 +4037,6 @@ typedef struct{
#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) #define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) #define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
/* AHB_peripheral */ /* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
@ -4137,8 +4057,6 @@ typedef struct{
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
/* Clock_source_to_output_on_MCO_pin */ /* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00) #define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04) #define RCC_MCO_SYSCLK ((uint8_t)0x04)
@ -4146,7 +4064,6 @@ typedef struct{
#define RCC_MCO_HSE ((uint8_t)0x06) #define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK ((uint8_t)0x07) #define RCC_MCO_PLLCLK ((uint8_t)0x07)
/* RCC_Flag */ /* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_HSERDY ((uint8_t)0x31)
@ -4159,20 +4076,12 @@ typedef struct{
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/* SysTick_clock_source */ /* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
/* ch32v00x_spi.h ------------------------------------------------------------*/ /* ch32v00x_spi.h ------------------------------------------------------------*/
/* SPI_data_direction */ /* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
@ -4212,7 +4121,6 @@ typedef struct{
/* SPI_MSB transmission */ /* SPI_MSB transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_MSB ((uint16_t)0x0000)
/* SPI_I2S_DMA_transfer_requests */ /* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
@ -4248,7 +4156,6 @@ typedef struct{
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
/* ch32v00x_tim.h ------------------------------------------------------------*/ /* ch32v00x_tim.h ------------------------------------------------------------*/
/* TIM_Output_Compare_and_PWM_modes */ /* TIM_Output_Compare_and_PWM_modes */
@ -4537,7 +4444,6 @@ typedef struct{
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
/* ch32v00x_usart.h ----------------------------------------------------------*/ /* ch32v00x_usart.h ----------------------------------------------------------*/
/* USART_Word_Length */ /* USART_Word_Length */
@ -4629,10 +4535,8 @@ typedef struct{
/* ch32v30x_usb.h ------------------------------------------------------------*/ /* ch32v30x_usb.h ------------------------------------------------------------*/
/* ch32v00x_wwdg.h -----------------------------------------------------------*/ /* ch32v00x_wwdg.h -----------------------------------------------------------*/
/* WWDG_Prescaler */ /* WWDG_Prescaler */
#define WWDG_Prescaler_1 ((uint32_t)0x00000000) #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080) #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
@ -4643,7 +4547,6 @@ typedef struct{
}; };
#endif #endif
// For debug writing to the debug interface. // For debug writing to the debug interface.
#ifndef MINICHLINK #ifndef MINICHLINK
#define DMDATA0 ((volatile uint32_t *)0xe00000f4) #define DMDATA0 ((volatile uint32_t *)0xe00000f4)
@ -4653,8 +4556,6 @@ typedef struct{
// Determination of PLL multiplication factor for non-V003 chips // Determination of PLL multiplication factor for non-V003 chips
// xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering. // xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering.
/* /*
@ -4668,7 +4569,10 @@ Examples:
*/ */
// Let us do some compile-time error checking. // Let us do some compile-time error checking.
#define ASM_ASSERT(COND) .if (!(COND)); .err; .endif #define ASM_ASSERT(COND) \
.if (!(COND)); \
.err; \
.endif
// Integer encodings of the possible compressed registers. // Integer encodings of the possible compressed registers.
#define C_s0 0 #define C_s0 0
@ -4697,10 +4601,13 @@ Examples:
#define XW_OP_SH 0b1010000000000010 #define XW_OP_SH 0b1010000000000010
// The two different XW encodings supported at the moment. // The two different XW encodings supported at the moment.
#define XW_ENCODE1(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ #define XW_ENCODE1(OP, R1, R2, IMM) \
ASM_ASSERT((IMM) >= 0 && (IMM) < 32); \
.2byte((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
(((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3))) (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3)))
#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \ #define XW_ENCODE2(OP, R1, R2, IMM) \
ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
(((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2)) (((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2))
// Compressed load byte, zero-extend result // Compressed load byte, zero-extend result
@ -4710,16 +4617,15 @@ Examples:
#define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM) #define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM)
// Compressed load half, zero-extend result // Compressed load half, zero-extend result
#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1))) #define XW_C_LHU(RD, RS, IMM) \
ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1)))
// Compressed store half // Compressed store half
#define XW_C_SH(RS1, RS2, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1))) #define XW_C_SH(RS1, RS2, IMM) \
ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1)))
// Applies to all processors // Applies to all processors
/* some bit definitions for systick regs */ /* some bit definitions for systick regs */
#define SYSTICK_SR_CNTIF (1 << 0) #define SYSTICK_SR_CNTIF (1 << 0)
#define SYSTICK_CTLR_STE (1 << 0) #define SYSTICK_CTLR_STE (1 << 0)
@ -4734,10 +4640,8 @@ Examples:
#define NVIC_KEY2 ((uint32_t)0xBCAF0000) #define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000) #define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *)SysTick_BASE) #define SysTick ((SysTick_Type *)SysTick_BASE)
#define PA1 1 #define PA1 1
#define PA2 2 #define PA2 2
#define PC0 32 #define PC0 32