automatic fomatting chagnes.
This commit is contained in:
jakeg00dwin
parent
db5dd3784d
commit
06efeab4e5
1 changed files with 3302 additions and 3398 deletions
218
inc/ch32v003hw.h
Executable file → Normal file
218
inc/ch32v003hw.h
Executable file → Normal file
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@ -6,7 +6,8 @@
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#ifndef __ASSEMBLER__ // Things before this can be used in assembly.
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#ifdef __cplusplus
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extern "C" {
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extern "C"
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{
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#endif
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/* Interrupt Number Definition, according to the selected device */
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@ -89,7 +90,6 @@ typedef enum IRQn
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.word TIM2_IRQHandler /* TIM2 */ \n\
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.option pop;\n"
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/* memory mapped structure for SysTick */
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typedef struct
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{
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@ -101,12 +101,10 @@ typedef struct
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uint32_t RESERVED1;
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} SysTick_Type;
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#endif /* __ASSEMBLER__*/
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#define HardFault_IRQn EXC_IRQn
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/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
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#define HSI_Value HSI_VALUE
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#define HSE_Value HSE_VALUE
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@ -139,8 +137,6 @@ typedef struct
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__IO uint32_t DLYR;
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} ADC_TypeDef;
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/* CRC Calculation Unit */
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typedef struct
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{
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@ -151,7 +147,6 @@ typedef struct
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__IO uint32_t CTLR;
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} CRC_TypeDef;
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/* Debug MCU */
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typedef struct
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{
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@ -232,11 +227,10 @@ typedef struct
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{
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__I uint16_t REVID;
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__I uint16_t DEVID;
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};
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};
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}s;
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}u;
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} INFO_TypeDef;
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/* General Purpose I/O */
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typedef enum
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{
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@ -257,9 +251,11 @@ typedef enum
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GPIO_CFGLR_OUT_50Mhz_AF_OD = 15,
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} GPIO_CFGLR_PIN_MODE_Typedef;
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typedef union {
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typedef union
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{
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uint32_t __FULL;
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struct {
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struct
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{
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GPIO_CFGLR_PIN_MODE_Typedef PIN0 : 4;
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GPIO_CFGLR_PIN_MODE_Typedef PIN1 : 4;
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GPIO_CFGLR_PIN_MODE_Typedef PIN2 : 4;
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@ -268,11 +264,13 @@ typedef union {
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GPIO_CFGLR_PIN_MODE_Typedef PIN5 : 4;
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GPIO_CFGLR_PIN_MODE_Typedef PIN6 : 4;
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GPIO_CFGLR_PIN_MODE_Typedef PIN7 : 4;
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};
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}s;
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} GPIO_CFGLR_t;
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typedef union {
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typedef union
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{
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uint32_t __FULL;
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const struct {
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const struct
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{
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uint32_t IDR0 : 1;
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uint32_t IDR1 : 1;
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uint32_t IDR2 : 1;
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@ -282,11 +280,13 @@ typedef union {
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uint32_t IDR6 : 1;
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uint32_t IDR7 : 1;
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uint32_t : 24;
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};
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}s;
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} GPIO_INDR_t;
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typedef union {
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typedef union
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{
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uint32_t __FULL;
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struct {
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struct
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{
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uint32_t ODR0 : 1;
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uint32_t ODR1 : 1;
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uint32_t ODR2 : 1;
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@ -296,11 +296,13 @@ typedef union {
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uint32_t ODR6 : 1;
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uint32_t ODR7 : 1;
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uint32_t : 24;
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};
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}s;
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} GPIO_OUTDR_t;
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typedef union {
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typedef union
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{
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uint32_t __FULL;
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struct {
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struct
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{
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uint32_t BS0 : 1;
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uint32_t BS1 : 1;
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uint32_t BS2 : 1;
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@ -319,11 +321,13 @@ typedef union {
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uint32_t BR6 : 1;
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uint32_t BR7 : 1;
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uint32_t : 8;
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};
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}s;
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} GPIO_BSHR_t;
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typedef union {
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typedef union
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{
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uint32_t __FULL;
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struct {
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struct
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{
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uint32_t BR0 : 1;
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uint32_t BR1 : 1;
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uint32_t BR2 : 1;
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@ -333,11 +337,13 @@ typedef union {
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uint32_t BR6 : 1;
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uint32_t BR7 : 1;
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uint32_t : 24;
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};
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}s;
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} GPIO_BCR_t;
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typedef union {
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typedef union
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{
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uint32_t __FULL;
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struct {
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struct
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{
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uint32_t LCK0 : 1;
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uint32_t LCK1 : 1;
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uint32_t LCK2 : 1;
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@ -348,7 +354,7 @@ typedef union {
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uint32_t LCK7 : 1;
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uint32_t LCKK : 1;
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uint32_t : 23;
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};
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}s;
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} GPIO_LCKR_t;
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typedef struct
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{
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@ -363,7 +369,13 @@ typedef struct
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#define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t){.__FULL = gpio->field})
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#define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t)__VA_ARGS__).__FULL
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#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;}
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#define DYN_GPIO_MOD(gpio, field, reg, val) \
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{ \
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GPIO_##field##_t tmp; \
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tmp.__FULL = gpio->field; \
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tmp.reg = val; \
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gpio->field = tmp.__FULL; \
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}
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/* Alternate Function I/O */
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typedef struct
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@ -428,8 +440,6 @@ typedef struct
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__IO uint32_t RSTSCKR;
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} RCC_TypeDef;
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/* Serial Peripheral Interface */
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typedef struct
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{
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@ -533,11 +543,6 @@ typedef struct
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__IO uint32_t CTR;
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} EXTEND_TypeDef;
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#endif
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/* Peripheral memory map */
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@ -553,7 +558,6 @@ typedef struct
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#define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */
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#endif
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#define APB1PERIPH_BASE (PERIPH_BASE)
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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@ -586,7 +590,6 @@ typedef struct
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#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
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#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */
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#define ESIG_BASE ((uint32_t)0x1FFFF7E0)
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#define INFO_BASE ((uint32_t)0x1FFFF704)
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@ -599,9 +602,6 @@ typedef struct
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#define PFIC_BASE (CORE_PERIPH_BASE + 0xE000)
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#define SysTick_BASE (CORE_PERIPH_BASE + 0xF000)
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// AFIO CTLR Bits
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#define PB6_FILT_EN (1 << 27)
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#define PB5_FILT_EN (1 << 26)
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@ -634,7 +634,6 @@ typedef struct
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#define UDM_PUE_10K 0x00000002
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#define UDM_PUE_1K5 0x00000003
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// USB PD Bits
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#define IE_TX_END (1 << 15)
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#define IE_RX_RESET (1 << 14)
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@ -715,8 +714,6 @@ typedef struct
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#define CC2_PU_80uA (3 << 2)
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#define PA_CC2_AI (1 << 0)
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/* Peripheral declaration */
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#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
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#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
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@ -747,12 +744,9 @@ typedef struct
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#define OB ((OB_TypeDef *)OB_BASE)
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#define ESIG ((ESG_TypeDef *)ESIG_BASE)
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// Mentioned in ch32v30x_dbgmcu.c, may not work on all processors.
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#define INFO ((INFO_TypeDef *)INFO_BASE)
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#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
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#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN
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//#define INFO ((INFO_TypeDef *)INFO_BASE)
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//#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
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//#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN
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/******************************************************************************/
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/* Peripheral Registers Bits Definition */
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@ -1146,7 +1140,6 @@ typedef struct
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#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
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#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
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/******************* Bit definition for DMA_INTFCR register *******************/
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#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
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#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
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@ -1494,7 +1487,6 @@ typedef struct
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#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */
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#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */
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/****************** Bit definition for FLASH_KEYR register ******************/
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#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */
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@ -1826,7 +1818,6 @@ typedef struct
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#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
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#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */
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/****************** Bit definition for AFIO_PCFR1register *******************/
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#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */
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#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */
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@ -1900,7 +1891,6 @@ typedef struct
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#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
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#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
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/***************** Bit definition for AFIO_EXTICR register *****************/
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#define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */
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#define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */
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@ -1930,7 +1920,6 @@ typedef struct
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#define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */
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#define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */
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/******************************************************************************/
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/* Independent WATCHDOG */
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/******************************************************************************/
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@ -2041,7 +2030,6 @@ typedef struct
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#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
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#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */
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/******************************************************************************/
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/* Power Control */
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/******************************************************************************/
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@ -2115,7 +2103,6 @@ typedef struct
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#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */
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#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */
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/******************* Bit definition for RCC_CFGR0 register *******************/
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#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
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#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */
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@ -2197,7 +2184,6 @@ typedef struct
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#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */
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#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */
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#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */
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#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
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@ -2302,7 +2288,6 @@ typedef struct
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#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
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/******************* Bit definition for RCC_RSTSCKR register ********************/
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#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
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#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
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@ -2316,9 +2301,6 @@ typedef struct
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/****************** Bit definition for RCC_AHBRSTR register *****************/
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/******************************************************************************/
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/* Serial Peripheral Interface */
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/******************************************************************************/
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@ -2788,28 +2770,21 @@ typedef struct
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#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */
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#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
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#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
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#define EXTEN_OPA_EN ((uint32_t)0x00010000)
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#define EXTEN_OPA_NSEL ((uint32_t)0x00020000)
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#define EXTEN_OPA_PSEL ((uint32_t)0x00040000)
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#ifdef __cplusplus
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}
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#endif
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#ifdef __cplusplus
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extern "C" {
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extern "C"
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{
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#endif
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/* ch32v00x_gpio.c -----------------------------------------------------------*/
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/* MASK */
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#define LSB_MASK ((uint16_t)0xFFFF)
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@ -2818,7 +2793,6 @@ extern "C" {
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#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
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#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
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/* ch32v00x_adc.c ------------------------------------------------------------*/
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/* ADC DISCNUM mask */
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@ -2914,13 +2888,9 @@ extern "C" {
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/* ADC IDATARx registers offset */
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#define IDATAR_Offset ((uint8_t)0x28)
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/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/
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#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
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/* ch32v00x_dma.c ------------------------------------------------------------*/
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/* DMA1 Channelx interrupt pending bit masks */
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@ -2932,7 +2902,6 @@ extern "C" {
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#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
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#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
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/* DMA2 FLAG mask */
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// Editor's note: Overloaded Definition.
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#define DMA2_FLAG_Mask ((uint32_t)0x10000000)
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@ -2942,7 +2911,6 @@ extern "C" {
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/* ch32v00x_exti.c -----------------------------------------------------------*/
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/* No interrupt selected */
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#define EXTI_LINENONE ((uint32_t)0x00000)
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@ -2951,7 +2919,6 @@ extern "C" {
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/* Flash Access Control Register bits */
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#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
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/* Flash Control Register bits */
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#define CR_PG_Set ((uint32_t)0x00000001)
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#define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
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@ -2990,7 +2957,6 @@ extern "C" {
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/* FLASH BANK address */
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#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
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/* Delay definition */
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#define EraseTimeout ((uint32_t)0x000B0000)
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#define ProgramTimeout ((uint32_t)0x00002000)
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@ -2999,10 +2965,8 @@ extern "C" {
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#define ValidAddrStart (FLASH_BASE)
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#define ValidAddrEnd (FLASH_BASE + 0x4000)
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/* ch32v00x_i2c.c ------------------------------------------------------------*/
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/* I2C SPE mask */
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#define CTLR1_PE_Set ((uint16_t)0x0001)
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#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
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@ -3088,10 +3052,8 @@ extern "C" {
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#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
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#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
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/* ch32v00x_pwr.c ------------------------------------------------------------*/
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/* PWR registers bit mask */
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/* CTLR register bit mask */
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#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
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|
|
@ -3134,7 +3096,6 @@ extern "C" {
|
|||
/* RSTSCKR register bit mask */
|
||||
#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
|
||||
|
||||
|
||||
/* RCC Flag Mask */
|
||||
// Editor's Note: Overloaded Definition
|
||||
#define RCC_FLAG_Mask ((uint8_t)0x1F)
|
||||
|
|
@ -3156,15 +3117,12 @@ static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5
|
|||
static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* ch32v00x_spi.c ------------------------------------------------------------*/
|
||||
|
||||
/* SPI SPE mask */
|
||||
#define CTLR1_SPE_Set ((uint16_t)0x0040)
|
||||
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
|
||||
/* SPI CRCNext mask */
|
||||
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
|
||||
|
||||
|
|
@ -3181,8 +3139,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||
|
||||
|
||||
|
||||
/* ch32v00x_tim.c ------------------------------------------------------------*/
|
||||
|
||||
/* TIM registers bit mask */
|
||||
|
|
@ -3249,7 +3205,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_Mask ((uint8_t)0x7F)
|
||||
|
||||
|
||||
/* ch32v00x_adc.h ------------------------------------------------------------*/
|
||||
|
||||
/* ADC_mode */
|
||||
|
|
@ -3266,8 +3221,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
|
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
|
||||
|
||||
|
||||
|
||||
/* ADC_data_align */
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
|
|
@ -3287,7 +3240,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
|
||||
#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
|
||||
|
||||
|
||||
/* ADC_sampling_time */
|
||||
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
|
||||
|
|
@ -3306,7 +3258,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
|
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
|
||||
|
||||
|
||||
/* ADC_injected_channel_selection */
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
|
|
@ -3342,9 +3293,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200)
|
||||
|
||||
|
||||
|
||||
|
||||
/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/
|
||||
|
||||
/* DBGMCU_CR Register */
|
||||
|
|
@ -3428,7 +3376,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
|
||||
/* DMA_flags_definition */
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
|
|
@ -3459,9 +3406,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
|
|||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
|
||||
|
||||
|
||||
/* ch32v00x_exti.h -----------------------------------------------------------*/
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
|
@ -3497,7 +3441,6 @@ typedef enum
|
|||
|
||||
/* ch32v00x_flash.h ----------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* FLASH Status */
|
||||
typedef enum
|
||||
|
|
@ -3518,7 +3461,6 @@ typedef enum
|
|||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
|
||||
|
||||
|
||||
/* Values to be used with CH32V00x devices (1page = 64Byte) */
|
||||
#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
|
||||
#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
|
||||
|
|
@ -3539,7 +3481,6 @@ typedef enum
|
|||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
|
||||
|
||||
|
||||
/* Option_Bytes_IWatchdog */
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
|
||||
|
|
@ -3558,7 +3499,6 @@ typedef enum
|
|||
#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
|
||||
#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */
|
||||
|
||||
|
||||
/* Option_Bytes_Power_ON_Start_Mode */
|
||||
#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */
|
||||
#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */
|
||||
|
|
@ -3582,12 +3522,10 @@ typedef enum
|
|||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
|
||||
|
||||
|
||||
/* System_Reset_Start_Mode */
|
||||
#define Start_Mode_USER ((uint32_t)0x00000000)
|
||||
#define Start_Mode_BOOT ((uint32_t)0x00004000)
|
||||
|
||||
|
||||
/* ch32v00x_gpio.h ------------------------------------------------------------*/
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
|
@ -3668,7 +3606,6 @@ typedef enum
|
|||
#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */
|
||||
#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */
|
||||
|
||||
|
||||
/* GPIO_Port_Sources */
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
|
|
@ -3684,7 +3621,6 @@ typedef enum
|
|||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
|
||||
|
||||
/* ch32v00x_i2c.h ------------------------------------------------------------*/
|
||||
|
||||
/* I2C_mode */
|
||||
|
|
@ -3928,7 +3864,6 @@ typedef enum
|
|||
/*EVT3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
|
||||
/* ch32v00x_iwdg.h -----------------------------------------------------------*/
|
||||
|
||||
/* IWDG_WriteAccess */
|
||||
|
|
@ -3948,7 +3883,6 @@ typedef enum
|
|||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
|
||||
|
||||
/* ch32v00x_misc.h -----------------------------------------------------------*/
|
||||
|
||||
/* Preemption_Priority_Group */
|
||||
|
|
@ -3963,7 +3897,6 @@ typedef enum
|
|||
/* Editor's note: I don't know if this is actually useful */
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
|
||||
/* OPA PSEL enumeration */
|
||||
typedef enum
|
||||
{
|
||||
|
|
@ -3978,8 +3911,6 @@ typedef enum
|
|||
CHN1
|
||||
} OPA_NSEL_TypeDef;
|
||||
|
||||
|
||||
|
||||
/* OPA Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -3987,9 +3918,9 @@ typedef struct
|
|||
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
|
||||
} OPA_InitTypeDef;
|
||||
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
|
|
@ -4019,7 +3950,6 @@ typedef struct{
|
|||
|
||||
/* ch32v00x_pwr.h ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* PVD_detection_level */
|
||||
|
||||
#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
|
||||
|
|
@ -4055,28 +3985,22 @@ typedef struct{
|
|||
/* PWR_Flag */
|
||||
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||
|
||||
|
||||
|
||||
/* ch32v00x_rcc.h ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* HSE_configuration */
|
||||
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||
|
||||
|
||||
/* PLL_entry_clock_source */
|
||||
#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
|
||||
|
||||
|
||||
/* System_clock_source */
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
|
||||
|
||||
/* AHB_clock_source */
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
|
||||
|
|
@ -4092,7 +4016,6 @@ typedef struct{
|
|||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
|
||||
|
||||
|
||||
/* RCC_Interrupt_source */
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
|
|
@ -4100,7 +4023,6 @@ typedef struct{
|
|||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
|
||||
/* ADC_clock_source */
|
||||
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||
|
|
@ -4115,8 +4037,6 @@ typedef struct{
|
|||
#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
|
||||
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
|
||||
|
||||
|
||||
|
||||
/* AHB_peripheral */
|
||||
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||
|
|
@ -4137,8 +4057,6 @@ typedef struct{
|
|||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
|
||||
|
||||
|
||||
/* Clock_source_to_output_on_MCO_pin */
|
||||
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
|
|
@ -4146,7 +4064,6 @@ typedef struct{
|
|||
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCO_PLLCLK ((uint8_t)0x07)
|
||||
|
||||
|
||||
/* RCC_Flag */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
|
|
@ -4159,20 +4076,12 @@ typedef struct{
|
|||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
|
||||
/* SysTick_clock_source */
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ch32v00x_spi.h ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* SPI_data_direction */
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
|
|
@ -4212,7 +4121,6 @@ typedef struct{
|
|||
/* SPI_MSB transmission */
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
|
||||
|
||||
/* SPI_I2S_DMA_transfer_requests */
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
|
|
@ -4248,7 +4156,6 @@ typedef struct{
|
|||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
|
||||
|
||||
/* ch32v00x_tim.h ------------------------------------------------------------*/
|
||||
|
||||
/* TIM_Output_Compare_and_PWM_modes */
|
||||
|
|
@ -4537,7 +4444,6 @@ typedef struct{
|
|||
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
|
||||
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
|
||||
|
||||
|
||||
/* ch32v00x_usart.h ----------------------------------------------------------*/
|
||||
|
||||
/* USART_Word_Length */
|
||||
|
|
@ -4629,10 +4535,8 @@ typedef struct{
|
|||
|
||||
/* ch32v30x_usb.h ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* ch32v00x_wwdg.h -----------------------------------------------------------*/
|
||||
|
||||
|
||||
/* WWDG_Prescaler */
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
|
|
@ -4643,7 +4547,6 @@ typedef struct{
|
|||
};
|
||||
#endif
|
||||
|
||||
|
||||
// For debug writing to the debug interface.
|
||||
#ifndef MINICHLINK
|
||||
#define DMDATA0 ((volatile uint32_t *)0xe00000f4)
|
||||
|
|
@ -4653,8 +4556,6 @@ typedef struct{
|
|||
|
||||
// Determination of PLL multiplication factor for non-V003 chips
|
||||
|
||||
|
||||
|
||||
// xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering.
|
||||
|
||||
/*
|
||||
|
|
@ -4668,7 +4569,10 @@ Examples:
|
|||
*/
|
||||
|
||||
// Let us do some compile-time error checking.
|
||||
#define ASM_ASSERT(COND) .if (!(COND)); .err; .endif
|
||||
#define ASM_ASSERT(COND) \
|
||||
.if (!(COND)); \
|
||||
.err; \
|
||||
.endif
|
||||
|
||||
// Integer encodings of the possible compressed registers.
|
||||
#define C_s0 0
|
||||
|
|
@ -4697,10 +4601,13 @@ Examples:
|
|||
#define XW_OP_SH 0b1010000000000010
|
||||
|
||||
// The two different XW encodings supported at the moment.
|
||||
#define XW_ENCODE1(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
|
||||
#define XW_ENCODE1(OP, R1, R2, IMM) \
|
||||
ASM_ASSERT((IMM) >= 0 && (IMM) < 32); \
|
||||
.2byte((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
|
||||
(((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3)))
|
||||
|
||||
#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
|
||||
#define XW_ENCODE2(OP, R1, R2, IMM) \
|
||||
ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
|
||||
(((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2))
|
||||
|
||||
// Compressed load byte, zero-extend result
|
||||
|
|
@ -4710,16 +4617,15 @@ Examples:
|
|||
#define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM)
|
||||
|
||||
// Compressed load half, zero-extend result
|
||||
#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1)))
|
||||
#define XW_C_LHU(RD, RS, IMM) \
|
||||
ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1)))
|
||||
|
||||
// Compressed store half
|
||||
#define XW_C_SH(RS1, RS2, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1)))
|
||||
|
||||
|
||||
#define XW_C_SH(RS1, RS2, IMM) \
|
||||
ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1)))
|
||||
|
||||
// Applies to all processors
|
||||
|
||||
|
||||
/* some bit definitions for systick regs */
|
||||
#define SYSTICK_SR_CNTIF (1 << 0)
|
||||
#define SYSTICK_CTLR_STE (1 << 0)
|
||||
|
|
@ -4734,10 +4640,8 @@ Examples:
|
|||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
|
||||
|
||||
#define SysTick ((SysTick_Type *)SysTick_BASE)
|
||||
|
||||
|
||||
#define PA1 1
|
||||
#define PA2 2
|
||||
#define PC0 32
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue