Commiting formatting changes.
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4 changed files with 8309 additions and 3324 deletions
6700
inc/ch32v003hw.h
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6700
inc/ch32v003hw.h
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4700
inc/ch32v003hw.hbak
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4700
inc/ch32v003hw.hbak
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@ -2,5 +2,10 @@
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#define _FUNCONFIG_H
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#define CH32V003 1
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#define FUNCONF_USE_DEBUGPRINTF 0
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#define FUNCONF_USE_UARTPRINTF 1
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#define FUNCONF_UART_PRINTF_BAUD 115200
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#endif
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src/main.c
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src/main.c
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@ -1,37 +1,221 @@
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#include "ch32fun.h"
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#include <stdio.h>
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#define ADC_BUFFER_SIZE 32
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//globals
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volatile uint16_t adc_buffer[ADC_BUFFER_SIZE] = {0};
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volatile uint16_t avg = 0;
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//Function Prototypes.
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void ADC_DMA_Init(void);
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void GPIO_Init(void);
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void DMA_Init(void);
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void ADC_Init(void);
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uint16_t ADC_Read(void) {
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//while (!(ADC1->STATR & ADC_FLAG_EOC)); // Wait for conversion to complete
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return ADC1->RDATAR; // Return ADC value
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}
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int main(void)
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{
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SystemInit();
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printf("DMA ADC TESTING\r\n");
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// Enable GPIOs
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;
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DMA_Init();
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GPIO_Init();
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ADC_Init();
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uint16_t old_value = UINT16_MAX;
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// GPIO D0 Push-Pull
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GPIOD->CFGLR &= ~(0xf << (4 * 0));
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GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 0);
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printf("DMA_Channel1->CNTR: %d\r\n", (uint16_t)DMA1_Channel1->CNTR);
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// GPIO D4 Push-Pull
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GPIOD->CFGLR &= ~(0xf << (4 * 4));
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GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4);
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if(!(ADC1->STATR & ADC_FLAG_EOC)){
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printf("ADC1 Status register EOC: False\r\n");
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}
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if(!(DMA1_Channel1->CFGR & DMA_CFGR1_EN)){
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printf("DMA1 Channel1 isn't enabled!\r\n");
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}
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// GPIO D6 Push-Pull
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GPIOD->CFGLR &= ~(0xf << (4 * 6));
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GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 6);
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/*
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while(1){
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// Start ADC conversion SWSTART bit 22
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//ADC1->CTLR2 |= (1<<22);
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printf("ADC reading: %d\r\n", ADC_Read());
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//Delay_Ms(1000);
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}
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*/
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// GPIO C0 Push-Pull
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GPIOC->CFGLR &= ~(0xf << (4 * 0));
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GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 0);
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while(1){
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printf("ADC_BUFFER: ");
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for(int i = 0; i < ADC_BUFFER_SIZE; i++){
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printf("%d ", adc_buffer[i]);
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}
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printf("\r\n");
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}
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while (1)
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{
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GPIOD->BSHR = (1 << 0) | (1 << 4) | (1 << 6); // Turn on GPIOs
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GPIOC->BSHR = (1 << 0);
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Delay_Ms(250);
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while(1){
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//printf("ADC reading: %d\r\n", avg);
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//Delay_Ms(1000);
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if(avg != old_value){
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old_value = avg;
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printf("ADC reading: %d\r\n", avg);
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Delay_Ms(500);
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}
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}
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GPIOD->BSHR = (1 << 16) | (1 << (16 + 4)) | (1 << (16 + 6)); // Turn off GPIOs
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GPIOC->BSHR = (1 << 16);
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Delay_Ms(250);
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}
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void GPIO_Init(void)
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{
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printf("GPIO_Init()\r\n");
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// Enable the clock for the GPIO port it's on
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOC;
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// Configure the GPIO pin C4 as analog input. bits[19:16]
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// CFN(config): Analog, Mode: Input
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GPIOC->CFGLR &= ~(0xf<<(4*4));
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}
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void ADC_Init(void)
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{
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printf("ADC_Init()\r\n");
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// Enable the clock for the ADC
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RCC->APB2PCENR |= RCC_APB2Periph_ADC1;
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// Reset the ADC to init all regs
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RCC->APB2PRSTR |= RCC_APB2Periph_ADC1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1;
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//I don't change the prescaler, because I'm not using an external crystal.
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//RCC->CFGR |= (0x1F<<11); //Sets the prescaler for div128.
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// Enable ADC scanning
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ADC1->CTLR1 |= ADC_SCAN;
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// Configure the ADC
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// -- Set the ADON bit.
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ADC1->CTLR2 |= (1<<0);
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// -- Set the External selection to SWSTART
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ADC1->CTLR2 |= ADC_EXTSEL;
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// -- Enable DMA for the ADC DMA_Enable --> bit8
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ADC1->CTLR2 |= (1<<8);
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// -- Set the ADC conversion for continuous
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ADC1->CTLR2 |= (1<<1);
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// -- Set ADC sample time. 3 offset, channel 2
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// Sets the sampling to 3 cycles.
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ADC1->SAMPTR2 &= ~(0xf<<(3*2));
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// Select ADC channel
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ADC1->RSQR1 = 0; // RSQR1 L num ch conversions = 1
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ADC1->RSQR2 = 0;
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ADC1->RSQR3 = 2;
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// Start ADC conversion SWSTART bit 22
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ADC1->CTLR2 |= (1<<22);
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}
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void DMA_Init(void)
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{
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//NOTE: Most of this could be a single line for the CFGR but this is more
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//explicit.
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//NOTE: See page 66 in the RM for figuring out the needed DMA channel.
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printf("DMA_Init()\r\n");
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// Enable the clock for dma1
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RCC->APB2PCENR |= RCC_AHBPeriph_DMA1;
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// Set the peripheral address
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DMA1_Channel1->PADDR = (uint32_t)&ADC1->RDATAR;
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// Set the memory address
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DMA1_Channel1->PADDR = (uint32_t)adc_buffer;
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// Set the amount of data to be transfered.
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DMA1_Channel1->CNTR = ADC_BUFFER_SIZE;
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// Set the DMA channel priority, bits[13:12]
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DMA1_Channel1->CFGR = 0; //clear it.
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DMA1_Channel2->CFGR &= ~((1<<12)|(1<<13)); //sets PL to low
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// Set the direction of data transfer, mode and datawidth for src & dst
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// along with th, tc and te interrupt enable bits.
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// Set the mem2mem as false.
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DMA1_Channel1->CFGR &= ~(1<<14);
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// Set dir as Peripheral to memory.
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DMA1_Channel1->CFGR &= ~(1<<4);
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// Set the datawidth for source and destination as 16bits.
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//DMA1_Channel1->CFGR |= (1<<10);
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//DMA1_Channel1->CFGR |= (1<<8);
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DMA1_Channel1->CFGR |= DMA_PeripheralDataSize_HalfWord;
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DMA1_Channel1->CFGR |= DMA_MemoryDataSize_HalfWord;
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// Set circular mode.
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DMA1_Channel1->CFGR |= (1<<5);
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// Enable memory address increment.
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DMA1_Channel1->CFGR |= (1<<7);
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//Enable IRQ
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//NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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// Set the transfer complete interrupt.
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DMA1_Channel1->CFGR |= (1<<1);
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// Set the enable bit in DMA_CCRx register to start channel x
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DMA1_Channel1->CFGR |= (1<<0);
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}
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void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt));
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void DMA1_Channel1_IRQHandler()
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{
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if(DMA1->INTFR & DMA1_FLAG_TC1) {
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DMA1->INTFCR = DMA_CTCIF1;
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printf("DMA ISR!\r\n");
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//current_write_buffer = current_read_buffer;
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avg = 0;
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for(int i = 0; i < ADC_BUFFER_SIZE; i++){
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avg += adc_buffer[i];
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}
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//Divide it by 32
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avg = avg >> 5;
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DMA_Init();
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}
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}
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/*
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void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt));
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void DMA1_Channel1_IRQHandler(void)
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{
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printf("DMA handler!\r\n");
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if (DMA1->INTFR & DMA_TCIF1) { // Check Transfer Complete flag
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DMA1->INTFR |= DMA_TCIF1; // Clear the flag
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// Process new ADC data in adc_buffer[]
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// Calculate average of data.
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avg = 0;
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for(int i = 0; i < ADC_BUFFER_SIZE; i++){
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avg += adc_buffer[i];
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}
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//Divide it by 32
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avg = avg >> 5;
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}
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}
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*/
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