updated test and blink sources

CMakeLists.txt

@@ -22,12 +22,12 @@ endif()
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 
 # Request C  standard features
-set(CMAKE_C_STANDARD 17)
+set(CMAKE_C_STANDARD 23)
 set(CMAKE_C_STANDARD_REQUIRED True)
 set(CMAKE_C_FLAGS "-Wall -Wpedantic")
 
 # SETUP THE CXX flags for .cpp
-set(CMAKE_CXX_STANDARD 17)
+set(CMAKE_CXX_STANDARD 23)
 set(CMAKE_CXX_STANDARD_REQUIRED True)
 set(CMAKE_CXX_FLAGS "-Wall -Werror -Wpedantic")
 

inc/ch32v003hw.h

@@ -6,7 +6,8 @@
 #ifndef __ASSEMBLER__ // Things before this can be used in assembly.
 
 #ifdef __cplusplus
-extern "C" {
+extern "C"
+{
 #endif
 
     /* Interrupt Number Definition, according to the selected device */
@@ -89,7 +90,6 @@ typedef enum IRQn
 	.word   TIM2_IRQHandler           /* TIM2 */                           \n\
 	.option   pop;\n"
 
-
     /* memory mapped structure for SysTick */
     typedef struct
     {
@@ -101,12 +101,10 @@ typedef struct
         uint32_t      RESERVED1;
     } SysTick_Type;
 
-
 #endif /* __ASSEMBLER__*/
 
 #define HardFault_IRQn EXC_IRQn
 
-
 /* Standard Peripheral Library old definitions (maintained for legacy purpose) */
 #define HSI_Value HSI_VALUE
 #define HSE_Value HSE_VALUE
@@ -139,8 +137,6 @@ typedef struct
         __IO uint32_t DLYR;
     } ADC_TypeDef;
 
-
-
     /* CRC Calculation Unit */
     typedef struct
     {
@@ -151,7 +147,6 @@ typedef struct
         __IO uint32_t CTLR;
     } CRC_TypeDef;
 
-
     /* Debug MCU */
     typedef struct
     {
@@ -232,11 +227,10 @@ typedef struct
             {
                 __I uint16_t REVID;
                 __I uint16_t DEVID;
-        };
+            }s;
-    };
+        }u;
     } INFO_TypeDef;
 
-
     /* General Purpose I/O */
     typedef enum
     {
@@ -257,9 +251,11 @@ typedef enum
         GPIO_CFGLR_OUT_50Mhz_AF_OD = 15,
     } GPIO_CFGLR_PIN_MODE_Typedef;
 
-typedef union {
+    typedef union
+    {
         uint32_t __FULL;
-	struct {
+        struct
+        {
             GPIO_CFGLR_PIN_MODE_Typedef PIN0 : 4;
             GPIO_CFGLR_PIN_MODE_Typedef PIN1 : 4;
             GPIO_CFGLR_PIN_MODE_Typedef PIN2 : 4;
@@ -268,11 +264,13 @@ typedef union {
             GPIO_CFGLR_PIN_MODE_Typedef PIN5 : 4;
             GPIO_CFGLR_PIN_MODE_Typedef PIN6 : 4;
             GPIO_CFGLR_PIN_MODE_Typedef PIN7 : 4;
-	};
+        }s;
     } GPIO_CFGLR_t;
-typedef union {
+    typedef union
+    {
         uint32_t __FULL;
-	const struct {
+        const struct
+        {
             uint32_t IDR0 : 1;
             uint32_t IDR1 : 1;
             uint32_t IDR2 : 1;
@@ -282,11 +280,13 @@ typedef union {
             uint32_t IDR6 : 1;
             uint32_t IDR7 : 1;
             uint32_t      : 24;
-	};
+        }s;
     } GPIO_INDR_t;
-typedef union {
+    typedef union
+    {
         uint32_t __FULL;
-	struct {
+        struct
+        {
             uint32_t ODR0 : 1;
             uint32_t ODR1 : 1;
             uint32_t ODR2 : 1;
@@ -296,11 +296,13 @@ typedef union {
             uint32_t ODR6 : 1;
             uint32_t ODR7 : 1;
             uint32_t      : 24;
-	};
+        }s;
     } GPIO_OUTDR_t;
-typedef union {
+    typedef union
+    {
         uint32_t __FULL;
-	struct {
+        struct
+        {
             uint32_t BS0 : 1;
             uint32_t BS1 : 1;
             uint32_t BS2 : 1;
@@ -319,11 +321,13 @@ typedef union {
             uint32_t BR6 : 1;
             uint32_t BR7 : 1;
             uint32_t     : 8;
-	};
+        }s;
     } GPIO_BSHR_t;
-typedef union {
+    typedef union
+    {
         uint32_t __FULL;
-	struct {
+        struct
+        {
             uint32_t BR0 : 1;
             uint32_t BR1 : 1;
             uint32_t BR2 : 1;
@@ -333,11 +337,13 @@ typedef union {
             uint32_t BR6 : 1;
             uint32_t BR7 : 1;
             uint32_t     : 24;
-	};
+        }s;
     } GPIO_BCR_t;
-typedef union {
+    typedef union
+    {
         uint32_t __FULL;
-	struct {
+        struct
+        {
             uint32_t LCK0 : 1;
             uint32_t LCK1 : 1;
             uint32_t LCK2 : 1;
@@ -348,7 +354,7 @@ typedef union {
             uint32_t LCK7 : 1;
             uint32_t LCKK : 1;
             uint32_t      : 23;
-	};
+        }s;
     } GPIO_LCKR_t;
     typedef struct
     {
@@ -363,7 +369,13 @@ typedef struct
 
 #define DYN_GPIO_READ(gpio, field) ((GPIO_##field##_t){.__FULL = gpio->field})
 #define DYN_GPIO_WRITE(gpio, field, ...) gpio->field = ((const GPIO_##field##_t)__VA_ARGS__).__FULL
-#define DYN_GPIO_MOD(gpio, field, reg, val) {GPIO_##field##_t tmp; tmp.__FULL = gpio->field; tmp.reg = val; gpio->field = tmp.__FULL;}
+#define DYN_GPIO_MOD(gpio, field, reg, val) \
+    {                                       \
+        GPIO_##field##_t tmp;               \
+        tmp.__FULL  = gpio->field;          \
+        tmp.reg     = val;                  \
+        gpio->field = tmp.__FULL;           \
+    }
 
     /* Alternate Function I/O */
     typedef struct
@@ -428,8 +440,6 @@ typedef struct
         __IO uint32_t RSTSCKR;
     } RCC_TypeDef;
 
-
-
     /* Serial Peripheral Interface */
     typedef struct
     {
@@ -533,11 +543,6 @@ typedef struct
         __IO uint32_t CTR;
     } EXTEND_TypeDef;
 
-
-
-
-
-
 #endif
 
 /* Peripheral memory map */
@@ -553,7 +558,6 @@ typedef struct
 #define CORE_PERIPH_BASE ((uint32_t)0xE0000000) /* System peripherals base address in the alias region */
 #endif
 
-
 #define APB1PERIPH_BASE (PERIPH_BASE)
 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
@@ -586,7 +590,6 @@ typedef struct
 
 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
 
-
 #define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */
 #define ESIG_BASE ((uint32_t)0x1FFFF7E0)
 #define INFO_BASE ((uint32_t)0x1FFFF704)
@@ -599,9 +602,6 @@ typedef struct
 #define PFIC_BASE (CORE_PERIPH_BASE + 0xE000)
 #define SysTick_BASE (CORE_PERIPH_BASE + 0xF000)
 
-
-
-
 // AFIO CTLR Bits
 #define PB6_FILT_EN (1 << 27)
 #define PB5_FILT_EN (1 << 26)
@@ -634,7 +634,6 @@ typedef struct
 #define UDM_PUE_10K 0x00000002
 #define UDM_PUE_1K5 0x00000003
 
-
 // USB PD Bits
 #define IE_TX_END (1 << 15)
 #define IE_RX_RESET (1 << 14)
@@ -715,8 +714,6 @@ typedef struct
 #define CC2_PU_80uA (3 << 2)
 #define PA_CC2_AI (1 << 0)
 
-
-
 /* Peripheral declaration */
 #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
 #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
@@ -747,12 +744,9 @@ typedef struct
 #define OB ((OB_TypeDef *)OB_BASE)
 #define ESIG ((ESG_TypeDef *)ESIG_BASE)
 // Mentioned in ch32v30x_dbgmcu.c, may not work on all processors.
-#define INFO                                    ((INFO_TypeDef *)INFO_BASE) 
+//#define INFO ((INFO_TypeDef *)INFO_BASE)
-#define EXTEN                                   ((EXTEN_TypeDef *)EXTEN_BASE)
+//#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
-#define EXTEND                                  ((EXTEND_TypeDef *)EXTEN_BASE)  // Alias to EXTEN
+//#define EXTEND ((EXTEND_TypeDef *)EXTEN_BASE) // Alias to EXTEN
-
-
-
 
 /******************************************************************************/
 /*                         Peripheral Registers Bits Definition               */
@@ -1146,7 +1140,6 @@ typedef struct
 #define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
 #define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
 
-
 /*******************  Bit definition for DMA_INTFCR register  *******************/
 #define DMA_CGIF1 ((uint32_t)0x00000001)  /* Channel 1 Global interrupt clear */
 #define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
@@ -1494,7 +1487,6 @@ typedef struct
 #define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */
 #define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */
 
-
 /******************  Bit definition for FLASH_KEYR register  ******************/
 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */
 
@@ -1826,7 +1818,6 @@ typedef struct
 #define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
 #define GPIO_LCKK ((uint32_t)0x00010000)  /* Lock key */
 
-
 /******************  Bit definition for AFIO_PCFR1register  *******************/
 #define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001)     /* SPI1 remapping */
 #define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002)     /* I2C1 remapping */
@@ -1900,7 +1891,6 @@ typedef struct
 #define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
 #define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000)     /* JTAG-DP Disabled and SW-DP Disabled */
 
-
 /*****************  Bit definition for AFIO_EXTICR register  *****************/
 #define AFIO_EXTICR_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */
 #define AFIO_EXTICR_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */
@@ -1930,7 +1920,6 @@ typedef struct
 #define AFIO_EXTICR_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */
 #define AFIO_EXTICR_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */
 
-
 /******************************************************************************/
 /*                           Independent WATCHDOG                             */
 /******************************************************************************/
@@ -2041,7 +2030,6 @@ typedef struct
 #define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
 #define I2C_CKCFGR_FS ((uint16_t)0x8000)   /* I2C Master Mode Selection */
 
-
 /******************************************************************************/
 /*                             Power Control                                  */
 /******************************************************************************/
@@ -2115,7 +2103,6 @@ typedef struct
 #define RCC_PLLON ((uint32_t)0x01000000)   /* PLL enable */
 #define RCC_PLLRDY ((uint32_t)0x02000000)  /* PLL clock ready flag */
 
-
 /*******************  Bit definition for RCC_CFGR0 register  *******************/
 #define RCC_SW ((uint32_t)0x00000003)   /* SW[1:0] bits (System clock Switch) */
 #define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */
@@ -2197,7 +2184,6 @@ typedef struct
 #define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */
 #define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */
 
-
 #define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */
 
 #define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
@@ -2302,7 +2288,6 @@ typedef struct
 
 #define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
 
-
 /*******************  Bit definition for RCC_RSTSCKR register  ********************/
 #define RCC_LSION ((uint32_t)0x00000001)    /* Internal Low Speed oscillator enable */
 #define RCC_LSIRDY ((uint32_t)0x00000002)   /* Internal Low Speed oscillator Ready */
@@ -2316,9 +2301,6 @@ typedef struct
 
 /******************  Bit definition for RCC_AHBRSTR register  *****************/
 
-
-
-
 /******************************************************************************/
 /*                        Serial Peripheral Interface                         */
 /******************************************************************************/
@@ -2788,28 +2770,21 @@ typedef struct
 #define EXTEN_LOCKUP_EN ((uint32_t)0x00000040)   /* Bit 6 */
 #define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
 
-
-
 #define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
 
-
 #define EXTEN_OPA_EN ((uint32_t)0x00010000)
 #define EXTEN_OPA_NSEL ((uint32_t)0x00020000)
 #define EXTEN_OPA_PSEL ((uint32_t)0x00040000)
 
-
 #ifdef __cplusplus
 }
 #endif
 
-
-
 #ifdef __cplusplus
-extern "C" {
+extern "C"
+{
 #endif
 
-
-
 /* ch32v00x_gpio.c -----------------------------------------------------------*/
 /* MASK */
 #define LSB_MASK ((uint16_t)0xFFFF)
@@ -2818,7 +2793,6 @@ extern "C" {
 #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
 #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
 
-
 /* ch32v00x_adc.c ------------------------------------------------------------*/
 
 /* ADC DISCNUM mask */
@@ -2914,13 +2888,9 @@ extern "C" {
 /* ADC IDATARx registers offset */
 #define IDATAR_Offset ((uint8_t)0x28)
 
-
-
-
 /* ch32v00x_dbgmcu.c ---------------------------------------------------------*/
 #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
 
-
 /* ch32v00x_dma.c ------------------------------------------------------------*/
 
 /* DMA1 Channelx interrupt pending bit masks */
@@ -2932,7 +2902,6 @@ extern "C" {
 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
 
-
 /* DMA2 FLAG mask */
 // Editor's note: Overloaded Definition.
 #define DMA2_FLAG_Mask ((uint32_t)0x10000000)
@@ -2942,7 +2911,6 @@ extern "C" {
 
 /* ch32v00x_exti.c -----------------------------------------------------------*/
 
-
 /* No interrupt selected */
 #define EXTI_LINENONE ((uint32_t)0x00000)
 
@@ -2951,7 +2919,6 @@ extern "C" {
 /* Flash Access Control Register bits */
 #define ACR_LATENCY_Mask ((uint32_t)0x00000038)
 
-
 /* Flash Control Register bits */
 #define CR_PG_Set ((uint32_t)0x00000001)
 #define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
@@ -2990,7 +2957,6 @@ extern "C" {
 /* FLASH BANK address */
 #define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
 
-
 /* Delay definition */
 #define EraseTimeout ((uint32_t)0x000B0000)
 #define ProgramTimeout ((uint32_t)0x00002000)
@@ -2999,10 +2965,8 @@ extern "C" {
 #define ValidAddrStart (FLASH_BASE)
 #define ValidAddrEnd (FLASH_BASE + 0x4000)
 
-
 /* ch32v00x_i2c.c ------------------------------------------------------------*/
 
-
 /* I2C SPE mask */
 #define CTLR1_PE_Set ((uint16_t)0x0001)
 #define CTLR1_PE_Reset ((uint16_t)0xFFFE)
@@ -3088,10 +3052,8 @@ extern "C" {
 #define CTLR_KEY_Reload ((uint16_t)0xAAAA)
 #define CTLR_KEY_Enable ((uint16_t)0xCCCC)
 
-
 /* ch32v00x_pwr.c ------------------------------------------------------------*/
 
-
 /* PWR registers bit mask */
 /* CTLR register bit mask */
 #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
@@ -3134,7 +3096,6 @@ extern "C" {
 /* RSTSCKR register bit mask */
 #define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
 
-
 /* RCC Flag Mask */
 // Editor's Note: Overloaded Definition
 #define RCC_FLAG_Mask ((uint8_t)0x1F)
@@ -3156,15 +3117,12 @@ static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5
     static __I uint8_t ADCPrescTable[20]    = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128};
 #endif
 
-
-
 /* ch32v00x_spi.c ------------------------------------------------------------*/
 
 /* SPI SPE mask */
 #define CTLR1_SPE_Set ((uint16_t)0x0040)
 #define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
 
-
 /* SPI CRCNext mask */
 #define CTLR1_CRCNext_Set ((uint16_t)0x1000)
 
@@ -3181,8 +3139,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040)
 #define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
 
-
-
 /* ch32v00x_tim.c ------------------------------------------------------------*/
 
 /* TIM registers bit mask */
@@ -3249,7 +3205,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
 #define BIT_Mask ((uint8_t)0x7F)
 
-
 /* ch32v00x_adc.h ------------------------------------------------------------*/
 
 /* ADC_mode */
@@ -3266,8 +3221,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
 #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
 
-
-
 /* ADC_data_align */
 #define ADC_DataAlign_Right ((uint32_t)0x00000000)
 #define ADC_DataAlign_Left ((uint32_t)0x00000800)
@@ -3287,7 +3240,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
 #define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
 
-
 /* ADC_sampling_time */
 #define ADC_SampleTime_3Cycles ((uint8_t)0x00)
 #define ADC_SampleTime_9Cycles ((uint8_t)0x01)
@@ -3306,7 +3258,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
 #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
 
-
 /* ADC_injected_channel_selection */
 #define ADC_InjectedChannel_1 ((uint8_t)0x14)
 #define ADC_InjectedChannel_2 ((uint8_t)0x18)
@@ -3342,9 +3293,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
 #define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200)
 
-
-
-
 /* ch32v00x_dbgmcu.h ---------------------------------------------------------*/
 
 /* DBGMCU_CR Register */
@@ -3428,7 +3376,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
 
-
 /* DMA_flags_definition */
 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
@@ -3459,9 +3406,6 @@ static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32,
 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
 
-
-
-
     /* ch32v00x_exti.h -----------------------------------------------------------*/
 
 #ifndef __ASSEMBLER__
@@ -3497,7 +3441,6 @@ typedef enum
 
     /* ch32v00x_flash.h ----------------------------------------------------------*/
 
-
 #ifndef __ASSEMBLER__
     /* FLASH Status */
     typedef enum
@@ -3518,7 +3461,6 @@ typedef enum
 #define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
 #define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
 
-
 /* Values to be used with CH32V00x devices (1page = 64Byte) */
 #define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001)    /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
 #define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002)   /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
@@ -3539,7 +3481,6 @@ typedef enum
 
 #define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
 
-
 /* Option_Bytes_IWatchdog */
 #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
 #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
@@ -3558,7 +3499,6 @@ typedef enum
 #define OB_RST_EN_DT1ms ((uint16_t)0x0008)   /* Reset IO enable (PD7) and  Ignore delay time 1ms */
 #define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and  Ignore delay time 128ms */
 
-
 /* Option_Bytes_Power_ON_Start_Mode */
 #define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */
 #define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */
@@ -3582,12 +3522,10 @@ typedef enum
 #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP           /* FLASH BANK1 End of Operation flag */
 #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
 
-
 /* System_Reset_Start_Mode */
 #define Start_Mode_USER ((uint32_t)0x00000000)
 #define Start_Mode_BOOT ((uint32_t)0x00004000)
 
-
     /* ch32v00x_gpio.h ------------------------------------------------------------*/
 
 #ifndef __ASSEMBLER__
@@ -3668,7 +3606,6 @@ typedef enum
 #define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080)        /* LSI calibration Alternate Function mapping */
 #define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400)    /* SDI Disabled */
 
-
 /* GPIO_Port_Sources */
 #define GPIO_PortSourceGPIOA ((uint8_t)0x00)
 #define GPIO_PortSourceGPIOC ((uint8_t)0x02)
@@ -3684,7 +3621,6 @@ typedef enum
 #define GPIO_PinSource6 ((uint8_t)0x06)
 #define GPIO_PinSource7 ((uint8_t)0x07)
 
-
 /* ch32v00x_i2c.h ------------------------------------------------------------*/
 
 /* I2C_mode */
@@ -3928,7 +3864,6 @@ typedef enum
 /*EVT3_2 */
 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
 
-
 /* ch32v00x_iwdg.h -----------------------------------------------------------*/
 
 /* IWDG_WriteAccess */
@@ -3948,7 +3883,6 @@ typedef enum
 #define IWDG_FLAG_PVU ((uint16_t)0x0001)
 #define IWDG_FLAG_RVU ((uint16_t)0x0002)
 
-
 /* ch32v00x_misc.h -----------------------------------------------------------*/
 
 /* Preemption_Priority_Group */
@@ -3963,7 +3897,6 @@ typedef enum
 /* Editor's note: I don't know if this is actually useful */
 #ifndef __ASSEMBLER__
 
-
     /* OPA PSEL enumeration */
     typedef enum
     {
@@ -3978,8 +3911,6 @@ typedef enum
         CHN1
     } OPA_NSEL_TypeDef;
 
-
-
     /* OPA Init Structure definition */
     typedef struct
     {
@@ -3987,9 +3918,9 @@ typedef struct
         OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
     } OPA_InitTypeDef;
 
-
     /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
-typedef struct{
+    typedef struct
+    {
         __I uint32_t  ISR[8];
         __I uint32_t  IPR[8];
         __IO uint32_t ITHRESDR;
@@ -4019,7 +3950,6 @@ typedef struct{
 
     /* ch32v00x_pwr.h ------------------------------------------------------------*/
 
-
     /* PVD_detection_level  */
 
 #define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
@@ -4055,28 +3985,22 @@ typedef struct{
 /* PWR_Flag */
 #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
 
-
-
 /* ch32v00x_rcc.h ------------------------------------------------------------*/
 
-
 /* HSE_configuration */
 #define RCC_HSE_OFF ((uint32_t)0x00000000)
 #define RCC_HSE_ON ((uint32_t)0x00010000)
 #define RCC_HSE_Bypass ((uint32_t)0x00040000)
 
-
 /* PLL_entry_clock_source */
 #define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
 #define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
 
-
 /* System_clock_source */
 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
 
-
 /* AHB_clock_source */
 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
@@ -4092,7 +4016,6 @@ typedef struct{
 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
 
-
 /* RCC_Interrupt_source */
 #define RCC_IT_LSIRDY ((uint8_t)0x01)
 #define RCC_IT_HSIRDY ((uint8_t)0x04)
@@ -4100,7 +4023,6 @@ typedef struct{
 #define RCC_IT_PLLRDY ((uint8_t)0x10)
 #define RCC_IT_CSS ((uint8_t)0x80)
 
-
 /* ADC_clock_source */
 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
@@ -4115,8 +4037,6 @@ typedef struct{
 #define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
 #define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
 
-
-
 /* AHB_peripheral */
 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
@@ -4137,8 +4057,6 @@ typedef struct{
 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
 
-
-
 /* Clock_source_to_output_on_MCO_pin */
 #define RCC_MCO_NoClock ((uint8_t)0x00)
 #define RCC_MCO_SYSCLK ((uint8_t)0x04)
@@ -4146,7 +4064,6 @@ typedef struct{
 #define RCC_MCO_HSE ((uint8_t)0x06)
 #define RCC_MCO_PLLCLK ((uint8_t)0x07)
 
-
 /* RCC_Flag */
 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
@@ -4159,20 +4076,12 @@ typedef struct{
 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
 
-
 /* SysTick_clock_source */
 #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
 #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
 
-
-
-
-
-
-
 /* ch32v00x_spi.h ------------------------------------------------------------*/
 
-
 /* SPI_data_direction */
 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
@@ -4212,7 +4121,6 @@ typedef struct{
 /* SPI_MSB transmission */
 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
 
-
 /* SPI_I2S_DMA_transfer_requests */
 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
@@ -4248,7 +4156,6 @@ typedef struct{
 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
 
-
 /* ch32v00x_tim.h ------------------------------------------------------------*/
 
 /* TIM_Output_Compare_and_PWM_modes */
@@ -4537,7 +4444,6 @@ typedef struct{
 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
 
-
 /* ch32v00x_usart.h ----------------------------------------------------------*/
 
 /* USART_Word_Length */
@@ -4629,10 +4535,8 @@ typedef struct{
 
 /* ch32v30x_usb.h ------------------------------------------------------------*/
 
-
 /* ch32v00x_wwdg.h -----------------------------------------------------------*/
 
-
 /* WWDG_Prescaler */
 #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
 #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
@@ -4643,7 +4547,6 @@ typedef struct{
 };
 #endif
 
-
 // For debug writing to the debug interface.
 #ifndef MINICHLINK
 #define DMDATA0 ((volatile uint32_t *)0xe00000f4)
@@ -4653,8 +4556,6 @@ typedef struct{
 
 // Determination of PLL multiplication factor for non-V003 chips
 
-
-
 // xw_ext.inc, thanks to @macyler, @jnk0le, @duk for this reverse engineering.
 
 /*
@@ -4668,7 +4569,10 @@ Examples:
 */
 
 // Let us do some compile-time error checking.
-#define ASM_ASSERT(COND) .if (!(COND)); .err; .endif
+#define ASM_ASSERT(COND) \
+    .if (!(COND));       \
+    .err;                \
+    .endif
 
 // Integer encodings of the possible compressed registers.
 #define C_s0 0
@@ -4697,10 +4601,13 @@ Examples:
 #define XW_OP_SH 0b1010000000000010
 
 // The two different XW encodings supported at the moment.
-#define XW_ENCODE1(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
+#define XW_ENCODE1(OP, R1, R2, IMM)                     \
+    ASM_ASSERT((IMM) >= 0 && (IMM) < 32);               \
+    .2byte((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
            (((IMM) & 0b1) << 12) | (((IMM) & 0b110) << (5 - 1)) | (((IMM) & 0b11000) << (10 - 3)))
 
-#define XW_ENCODE2(OP, R1, R2, IMM) ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
+#define XW_ENCODE2(OP, R1, R2, IMM)                                                            \
+    ASM_ASSERT((IMM) >= 0 && (IMM) < 32); .2byte ((OP) | (REG2I(R1) << 2) | (REG2I(R2) << 7) | \
 	(((IMM) & 0b11) << 5) | (((IMM) & 0b11100) << (10 - 2))
 
 // Compressed load byte, zero-extend result
@@ -4710,16 +4617,15 @@ Examples:
 #define XW_C_SB(RS1, RS2, IMM) XW_ENCODE1(XW_OP_SB, RS1, RS2, IMM)
 
 // Compressed load half, zero-extend result
-#define XW_C_LHU(RD, RS, IMM) ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1)))
+#define XW_C_LHU(RD, RS, IMM) \
+    ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_LHU, RD, RS, ((IMM) >> 1)))
 
 // Compressed store half
-#define XW_C_SH(RS1, RS2, IMM)  ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1)))
+#define XW_C_SH(RS1, RS2, IMM) \
-
+    ASM_ASSERT(((IMM) & 1) == 0); XW_ENCODE2(XW_OP_SH, RS1, RS2, ((IMM) >> 1)))
-
 
 // Applies to all processors
 
-
 /* some bit definitions for systick regs */
 #define SYSTICK_SR_CNTIF (1 << 0)
 #define SYSTICK_CTLR_STE (1 << 0)
@@ -4734,10 +4640,8 @@ Examples:
 #define NVIC_KEY2 ((uint32_t)0xBCAF0000)
 #define NVIC_KEY3 ((uint32_t)0xBEEF0000)
 
-
 #define SysTick ((SysTick_Type *)SysTick_BASE)
 
-
 #define PA1 1
 #define PA2 2
 #define PC0 32

src/CMakeLists.txt

@@ -2,6 +2,7 @@
 add_executable(${PROJECT_NAME}
     main.c
     ch32fun.c
+    #blink/blink.c
 )
 
 target_include_directories(${PROJECT_NAME} PUBLIC
@@ -9,6 +10,7 @@ target_include_directories(${PROJECT_NAME} PUBLIC
 )
 
 target_link_libraries(${PROJECT_NAME} PRIVATE 
+    blink
     gcc
 )
 
@@ -49,7 +51,14 @@ target_link_options(${PROJECT_NAME} PUBLIC
 
 set_target_properties(${PROJECT_NAME} PROPERTIES SUFFIX ".elf")
 
+# Convert output to hex and binary
+add_custom_command(TARGET ${PROJECT_NAME} POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${PROJECT_NAME}> ${CMAKE_PROJECT_NAME}.hex
+)
+
+
 
 #add_subdirectory(attic)
 add_subdirectory(ADC)
 add_subdirectory(RegEdit)
+add_subdirectory(blink)

src/blink/CMakeLists.txt

@@ -0,0 +1,43 @@
+add_library(blink STATIC
+    blink.c
+)
+
+target_include_directories(blink PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}
+)
+
+if(NOT UNIT_TESTING)
+# The `-ffunction-sections` and `-fdata-sections` need to be used 
+# in the compile and linker options otherwise it doesnt't
+# correctly remove the unused functions.
+    target_compile_options(blink PUBLIC
+        -g
+        -Os
+        -flto
+        -ffunction-sections
+        -fdata-sections
+        -fmessage-length=0
+        -msmall-data-limit=8
+        -march=rv32ec
+        -mabi=ilp32e
+        -DCH32V003=1
+    )
+
+#    target_link_options(blink PUBLIC
+#        -flto
+#        -ffunction-sections
+#        -fdata-sections
+#        -fmessage-length=0
+#        -msmall-data-limit=8
+#        -march=rv32ec
+#        -mabi=ilp32e
+#        -static-libgcc
+#        -nostdlib
+#        -L${CMAKE_SOURCE_DIR}/src
+#        -Wl,--print-memory-usage
+#        -Wl,-Map=${PROJECT_NAME}.map
+#        -Wl,--gc-sections
+#        -T${CMAKE_SOURCE_DIR}/src/linker_script.ld
+#    )
+endif()
+

src/blink/blink.c

@@ -0,0 +1,34 @@
+/*
+ * Author: username
+ * Date: 2025
+ * filename: blink.c
+ * description: module_purpose
+ */
+
+#include "blink.h"
+// #include <ch32fun.h>
+
+// Define the function pointer (initialized to NULL)
+DelayFunction delay_ms = 0;
+
+// Returns without caling if function pointer wasn't defined.
+void blink_led(unsigned int times)
+{
+    if (!delay_ms)
+    {
+        return;
+    }
+
+    for (int i = 0; i < times; i++)
+    {
+        // Sets the gpio pin(high).
+        *GPIO_PORT_BSHR |= (1 << 0);
+
+        delay_ms(500);
+
+        // Resets the gpio pin(low).
+        *GPIO_PORT_BSHR |= (1 << (0 + 16));
+
+        delay_ms(500);
+    }
+}

src/blink/blink.h

@@ -0,0 +1,20 @@
+/*
+ * Author: Jake G
+ * Date: 2025
+ * filename: BLINK.h
+ * description: blink LED(for testing.)
+ */
+
+#ifndef BLINK_H
+#define BLINK_H
+
+#include <stdint.h>
+
+extern volatile uint32_t *GPIO_PORT_BSHR;
+
+typedef void (*DelayFunction)(unsigned int ms);
+extern DelayFunction delay_ms;
+
+void                 blink_led(unsigned int times);
+
+#endif // BLINK_H

src/linker_script.ld

@@ -1,11 +1,27 @@
+/* Entry Point of program, interrupt vector table in this case.*/
+/* IVT: data structure that associates list of interrupt handlers with
+ * a list of interrupt requests in a table of interrupt vectors.
+ */
 ENTRY( InterruptVector )
+
+/*
+ * Memory Layout:
+ * Flash(read execute): 
+ * Ram(read write execute)
+ */
 MEMORY
 {
  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K
  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K
 }
+
+
 SECTIONS
 {
+    /*
+     * Initialization section:
+     * handles startup initialization routines stored in flash.
+     */
     .init :
     {
       _sinit = .;
@@ -14,6 +30,12 @@ SECTIONS
       . = ALIGN(4);
       _einit = .;
     } >FLASH AT>FLASH
+
+    /*
+     * Text Section:
+     * Contains executable code and read-only data(rodata)
+     * Stored in flash. 
+     */
     .text :
     {
       . = ALIGN(4);
@@ -22,15 +44,31 @@ SECTIONS
       *(.rodata)
       *(.rodata*)
       *(.gnu.linkonce.t.*)
+    
+      /* Include additional object files. */
+      /* *(EXTERN(*)) /* Link against external symbols */
+
       . = ALIGN(4);
     } >FLASH AT>FLASH
+
+    /*
+     * Finalization Section:
+     * Contains finalization routines, executed before exiting the program.
+     */
     .fini :
     {
       KEEP(*(SORT_NONE(.fini)))
       . = ALIGN(4);
     } >FLASH AT>FLASH
+
+    /*PROVODE: defines a symbol only if it is not already defined elsewhere.*/
     PROVIDE( _etext = . );
     PROVIDE( _eitcm = . );
+
+    /*
+     * The preinit_array and init_array handle static/global constructors and 
+     * initalizers.
+     */
     .preinit_array :
     {
       PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -51,6 +89,8 @@ SECTIONS
       KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
       PROVIDE_HIDDEN (__fini_array_end = .);
     } >FLASH AT>FLASH
+
+    /* Constructors Section: needed for C++ */
     .ctors :
     {
       KEEP (*crtbegin.o(.ctors))
@@ -59,6 +99,8 @@ SECTIONS
       KEEP (*(SORT(.ctors.*)))
       KEEP (*(.ctors))
     } >FLASH AT>FLASH
+
+    /* Destructors Section: needed for C++ */
     .dtors :
     {
       KEEP (*crtbegin.o(.dtors))
@@ -67,16 +109,27 @@ SECTIONS
       KEEP (*(SORT(.dtors.*)))
       KEEP (*(.dtors))
     } >FLASH AT>FLASH
+
+
+    /* Likely for data alignment.*/
     .dalign :
     {
       . = ALIGN(4);
       PROVIDE(_data_vma = .);
     } >RAM AT>FLASH
+
+    /* Likely for  dynamic loader alignment.*/
     .dlalign :
     {
       . = ALIGN(4);
       PROVIDE(_data_lma = .);
     } >FLASH AT>FLASH
+
+    /*
+     * Data section: Initialized Variables
+     * contains initialized variables copied from flash to ram at startup.
+     * `_sdata` and `_edata` mark the start and end of the `.data` section.
+     */
     .data :
     {
       . = ALIGN(4);
@@ -94,9 +147,21 @@ SECTIONS
       *(.srodata.cst4)
       *(.srodata.cst2)
       *(.srodata .srodata.*)
+
+      /* Trying to include datasections for external object files.*/
+      /* 
+       * *(.data)
+       * *(.data.*)
+       */
+
       . = ALIGN(4);
       PROVIDE( _edata = .);
     } >RAM AT>FLASH
+
+    /* BSS Section: Contains uninitialized variables.
+     * Holds uninited global/static vars. The runtime must zero out this
+     * section before main function.
+     */
     .bss :
     {
       . = ALIGN(4);

src/main.c

@@ -1,8 +1,12 @@
 #include "ch32fun.h"
+#include <blink.h>
 #include <stdio.h>
 
 #define ADC_BUFFER_SIZE 32
 
+// external defines.
+volatile uint32_t *GPIO_PORT_BSHR = &GPIOD->BSHR;
+
 // globals
 volatile uint16_t adc_buffer[ADC_BUFFER_SIZE] = {0};
 volatile uint16_t avg                         = 0;
@@ -14,12 +18,12 @@ void GPIO_Init(void);
 void     DMA_Init(void);
 void     ADC_Init(void);
 
-uint16_t ADC_Read(void) {
+uint16_t ADC_Read(void)
+{
     // while (!(ADC1->STATR & ADC_FLAG_EOC)); // Wait for conversion to complete
     return ADC1->RDATAR; // Return ADC value
 }
 
-
 int main(void)
 {
     SystemInit();
@@ -30,14 +34,21 @@ int main(void)
     GPIO_Init();
     ADC_Init();
 
+    // set delay fp.
+    // delay_ms = Delay_Ms;
+
+    blink_led(5);
+
     uint16_t old_value = UINT16_MAX;
 
     printf("DMA_Channel1->CNTR: %d\r\n", (uint16_t)DMA1_Channel1->CNTR);
 
-    if(!(ADC1->STATR & ADC_FLAG_EOC)){
+    if (!(ADC1->STATR & ADC_FLAG_EOC))
+    {
         printf("ADC1 Status register EOC: False\r\n");
     }
-    if(!(DMA1_Channel1->CFGR & DMA_CFGR1_EN)){
+    if (!(DMA1_Channel1->CFGR & DMA_CFGR1_EN))
+    {
         printf("DMA1 Channel1 isn't enabled!\r\n");
     }
 
@@ -50,24 +61,27 @@ int main(void)
     }
     */
 
-    while(1){
+    while (1)
+    {
         printf("ADC_BUFFER: ");
-        for(int i = 0; i < ADC_BUFFER_SIZE; i++){
+        for (int i = 0; i < ADC_BUFFER_SIZE; i++)
+        {
             printf("%d ", adc_buffer[i]);
         }
         printf("\r\n");
     }
 
-    while(1){
+    while (1)
+    {
         // printf("ADC reading: %d\r\n", avg);
         // Delay_Ms(1000);
-        if(avg != old_value){
+        if (avg != old_value)
+        {
             old_value = avg;
             printf("ADC reading: %d\r\n", avg);
             Delay_Ms(500);
         }
     }
-
 }
 
 void GPIO_Init(void)
@@ -80,10 +94,8 @@ void GPIO_Init(void)
     // Configure the GPIO pin C4 as analog input. bits[19:16]
     // CFN(config): Analog, Mode: Input
     GPIOC->CFGLR &= ~(0xf << (4 * 4));
-
 }
 
-
 void ADC_Init(void)
 {
     printf("ADC_Init()\r\n");
@@ -127,7 +139,6 @@ void ADC_Init(void)
     ADC1->CTLR2 |= (1 << 22);
 }
 
-
 void DMA_Init(void)
 {
     // NOTE: Most of this could be a single line for the CFGR but this is more
@@ -181,19 +192,19 @@ void DMA_Init(void)
 
     // Set the enable bit in DMA_CCRx register to start channel x
     DMA1_Channel1->CFGR |= (1 << 0);
-
 }
 
-
 void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt));
 void DMA1_Channel1_IRQHandler()
 {
-    if(DMA1->INTFR & DMA1_FLAG_TC1) {
+    if (DMA1->INTFR & DMA1_FLAG_TC1)
+    {
         DMA1->INTFCR = DMA_CTCIF1;
         printf("DMA ISR!\r\n");
         // current_write_buffer = current_read_buffer;
         avg = 0;
-        for(int i = 0; i < ADC_BUFFER_SIZE; i++){
+        for (int i = 0; i < ADC_BUFFER_SIZE; i++)
+        {
             avg += adc_buffer[i];
         }
         // Divide it by 32

tests/AllTests.cpp

@@ -5,6 +5,7 @@
 IMPORT_TEST_GROUP(simple_test);
 IMPORT_TEST_GROUP(test_ADC);
 IMPORT_TEST_GROUP(test_RegEdit);
+IMPORT_TEST_GROUP(test_blink);
 
 //START: main
 int main(int argc, char** argv)

tests/CMakeLists.txt

@@ -1,6 +1,7 @@
 project(Tests)
 
 # TEST_DIRS
+add_subdirectory(blink)
 add_subdirectory(MockRegEdit)
 add_subdirectory(RegEdit)
 add_subdirectory(simple_test)
@@ -19,6 +20,7 @@ target_link_libraries(AllTests
     ${CPPUTEST_LIBRARIES}/libCppUTest.a
     ${CPPUTEST_LIBRARIES}/libCppUTestExt.a
     # TEST_LINKS
+	test_blink
     test_ADC
     test_RegEdit
     simple_test

tests/blink/CMakeLists.txt

@@ -0,0 +1,10 @@
+# TEST_RUNNER
+add_library(test_blink
+    test_blink.cpp    
+)
+
+target_link_libraries(test_blink
+    ${CPPUTEST_LIBRARIES}/libCppUTest.a
+    ${CPPUTEST_LIBRARIES}/libCppUTestExt.a
+    blink
+)

tests/blink/test_blink.cpp

@@ -0,0 +1,61 @@
+/*
+ * Author: username
+ * Date: todays_date 
+ * filename: test_blink.c
+ * description: module_purpose
+ */
+
+#include "CppUTest/CommandLineTestRunner.h"
+
+extern "C" 
+{
+#include "blink.h"
+}
+
+volatile uint32_t fake_bshr_reg = 0;
+volatile uint32_t* GPIO_PORT_BSHR = &fake_bshr_reg;
+
+unsigned int called;
+void fake_delay(unsigned int ms)
+{
+    called += 1;
+    return;
+}
+
+TEST_GROUP(test_blink)
+{
+    void setup()
+    {
+        fake_bshr_reg = 0;
+        called = 0;
+    }
+    void teardown()
+    {
+
+    }
+};
+
+
+TEST(test_blink, UninitializedFuncPointer)
+{
+    blink_led(5);
+    CHECK_EQUAL(0, fake_bshr_reg);
+}
+
+TEST(test_blink, BlinkChangesReg)
+{
+    //Set the function pointer.
+    delay_ms = fake_delay;
+
+    blink_led(1);
+
+    CHECK_EQUAL_TEXT(2, called, "Delay function not called expeced number of times");
+
+    CHECK(fake_bshr_reg & (1<<0));
+    CHECK(fake_bshr_reg & (1<<(0+16)));
+
+    //Unset function pointer
+    delay_ms = 0;
+}
+
+