Commit Graph

34 Commits

Author SHA1 Message Date
jakeg00dwin d8403a4e82 Added call to helper function for ADC_INIT test 2024-07-27 09:28:29 -07:00
jakeg00dwin a926cc3836 setup usage of the new ReadReg function. 2024-07-27 09:28:17 -07:00
jakeg00dwin 4ab57eb948 Created a helper function for the ADC storage testing 2024-07-27 09:23:36 -07:00
jakeg00dwin 7deea50e91 white space change 2024-07-27 09:23:15 -07:00
jakeg00dwin 4b44d364e0 fixed issue with mock causing a segmentation fault from pointer deref with lower type (void *) --> (uint8_t *) 2024-07-27 09:22:32 -07:00
jakeg00dwin a92cdead2e fixed up ADC code + tests to make them pass 2024-07-27 09:06:23 -07:00
jakeg00dwin 5f547dd844 mplab change 2024-07-26 18:19:44 -07:00
jakeg00dwin 8117d3f890 fix of port storage 2024-07-26 18:19:36 -07:00
jakeg00dwin 6ecbe2f48a linking with the cpputest libs 2024-07-26 18:19:16 -07:00
jakeg00dwin 029b96aade Added two mock calls for the restore of the port state. 2024-07-26 18:19:05 -07:00
jakeg00dwin ce68803cef removed empty whitespace 2024-07-26 18:18:36 -07:00
jakeg00dwin f3c48ba643 Removed magic numbers from the Reading of the ZCD pin. 2024-07-26 18:18:23 -07:00
jakeg00dwin b987d81827 Cleaned up comments in the TriacOut module 2024-07-26 18:18:09 -07:00
jakeg00dwin 29426ad4a5 Updated to follow the mocks 2024-07-26 18:17:53 -07:00
jakeg00dwin f536024959 updated with new function for the RegEdit mock 2024-07-26 18:16:09 -07:00
jakeg00dwin af3a041df8 ignoring the cache and build dir now 2024-07-26 18:15:33 -07:00
jakeg00dwin c64fb08bec MPLABX config updates 2024-07-24 17:54:59 -07:00
jakeg00dwin 7c0fc29687 defined the F_CPU here 2024-07-24 17:54:41 -07:00
jakeg00dwin 437479b0b5 Commented out the unused function 2024-07-24 17:54:27 -07:00
jakeg00dwin 2be04980d1 Changed to using an initial value for u16. 2024-07-24 17:54:11 -07:00
jakeg00dwin 26993753fe Added more stuff to not track. 2024-07-24 17:21:57 -07:00
jakeg00dwin f80f61c9ff Converted to hybrid between MPLABX and Cmake for test harness. 2024-07-24 17:21:29 -07:00
jakeg00dwin 0a2c8b1dab Changed to using the reset default clock divider of 6. More stable given variable voltage, also reduces power consumption of attiny404. 2024-07-10 09:40:56 -07:00
jakeg00dwin c2424c47a8 updated new branch specifically for acting as the testing branch 2024-07-09 19:38:56 -07:00
jakeg00dwin 04a4bc4dea Updated to disable the main clock's pre-scaler. Allows it to run at full 20MHz 2024-07-09 18:47:16 -07:00
jakeg00dwin eba8344e36 Implimented Load detection module that auto cuts G1, G2 and G3 if values on the ADC_LOAD pins is outside parameters. 2024-07-02 17:16:53 -07:00
jakeg00dwin e4f19012b0 moved the threshold values into load.h as defines. 2024-07-02 15:43:49 -07:00
jakeg00dwin fa1dd00965 updated the comments in the main.c filei. 2024-07-02 15:35:10 -07:00
jakeg00dwin 90a27d93d3 Updated the readme file 2024-07-02 15:32:58 -07:00
jakeg00dwin da9bd19199 Updated the repo with the load.h and load.c files in order to impliment the Low Power Operation Mode. 2024-07-02 15:27:57 -07:00
jakeg00dwin fc95e07e71 2024-07-02 11:04:06 -07:00
jakeg00dwin 96153945bc Adding the binary output as well 2024-07-02 08:45:33 -07:00
jakeg00dwin 94817bdb8a updated the git config 2024-07-02 08:45:19 -07:00
Jake Goodwin c70a0cf0ce Converted the template unix project to mplabx 2024-07-01 17:53:09 -07:00